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Listtree.mcc: update version and date
[AROS.git] / rom / devs / ata / lowlevel.c
blob56d3b80bb4a518820861308b8749f533ff332b7c
1 /*
2 Copyright © 2004-2014, The AROS Development Team. All rights reserved.
3 $Id$
4
5 Desc:
6 Lang: English
7 */
8
9 /*
10 * TODO:
11 * - put a critical section around DMA transfers (shared dma channels)
12 */
13
14 // use #define xxx(a) D(a) to enable particular sections.
15 #if DEBUG
16 #define DIRQ(a) D(a)
17 #define DIRQ_MORE(a)
18 #define DUMP(a) D(a)
19 #define DUMP_MORE(a)
20 #define DATA(a) D(a)
21 #define DATAPI(a) D(a)
22 #define DINIT(a) D(a)
23 #else
24 #define DIRQ(a) do { } while (0)
25 #define DIRQ_MORE(a) do { } while (0)
26 #define DUMP(a) do { } while (0)
27 #define DUMP_MORE(a) do { } while (0)
28 #define DATA(a) do { } while (0)
29 #define DATAPI(a) do { } while (0)
30 #define DINIT(a)
31 #endif
32 /* Errors that shouldn't happen */
33 #define DERROR(a) a
34
35 #include <aros/debug.h>
36 #include <exec/types.h>
37 #include <exec/exec.h>
38 #include <exec/resident.h>
39 #include <utility/utility.h>
40 #include <oop/oop.h>
41
42 #include <proto/exec.h>
43 #include <devices/timer.h>
44
45 #include "ata.h"
46 #include "ata_bus.h"
47 #include "timer.h"
48
49 static BYTE ata_Identify(struct ata_Unit *unit);
50 static BYTE ata_ReadSector32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
51 static BYTE ata_ReadSector64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
52 static BYTE ata_ReadMultiple32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
53 static BYTE ata_ReadMultiple64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
54 static BYTE ata_ReadDMA32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
55 static BYTE ata_ReadDMA64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
56 static BYTE ata_WriteSector32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
57 static BYTE ata_WriteSector64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
58 static BYTE ata_WriteMultiple32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
59 static BYTE ata_WriteMultiple64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
60 static BYTE ata_WriteDMA32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
61 static BYTE ata_WriteDMA64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
62 static void ata_ResetBus(struct ata_Bus *bus);
63 static BYTE ata_Eject(struct ata_Unit *);
64 static BOOL ata_WaitBusyTO(struct ata_Unit *unit, UWORD tout, BOOL irq,
65 BOOL fake_irq, UBYTE *stout);
66
67 static BYTE atapi_SendPacket(struct ata_Unit *unit, APTR packet, APTR data,
68 LONG datalen, BOOL *dma, BOOL write);
69 static BYTE atapi_DirectSCSI(struct ata_Unit *unit, struct SCSICmd *cmd);
70 static BYTE atapi_Read(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
71 static BYTE atapi_Write(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
72 static BYTE atapi_Eject(struct ata_Unit *);
73 static ULONG atapi_RequestSense(struct ata_Unit* unit, UBYTE* sense,
74 ULONG senselen);
75 static BYTE atapi_EndCmd(struct ata_Unit *unit);
76
77 static void common_SetBestXferMode(struct ata_Unit* unit);
78
79 #define DEVHEAD_VAL 0xe0
80
81 #if DEBUG
82 static void dump(APTR mem, ULONG len)
83 {
84 register int i, j = 0;
85
86 DUMP_MORE(for (j=0; j<(len+15)>>4; ++j))
87 {
88 bug("[ATA ] %06lx: ", j<<4);
89
90 for (i=0; i<len-(j<<4); i++)
91 {
92 bug("%02lx ", ((unsigned char*)mem)[(j<<4)|i]);
93 if (i == 15)
94 break;
95 }
96
97 for (i=0; i<len-(j<<4); i++)
98 {
99 unsigned char c = ((unsigned char*)mem)[(j<<4)|i];
100
101 bug("%c", c >= 0x20 ? c<=0x7f ? c : '.' : '.');
102 if (i == 15)
103 break;
104 }
105 bug("\n");
106 }
107 }
108 #endif
109
110 static void ata_strcpy(const UBYTE *str1, UBYTE *str2, ULONG size)
111 {
112 register int i = size;
113
114 while (size--)
115 str2[size ^ 1] = str1[size];
116
117 while (i > 0 && str2[--i] <= ' ')
118 str2[i] = '\0';
119 }
120
121 static inline struct ata_Unit* ata_GetSelectedUnit(struct ata_Bus* bus)
122 {
123 return bus->ab_SelectedUnit;
124 }
125
126 static inline UBYTE ata_ReadStatus(struct ata_Bus *bus)
127 {
128 return PIO_In(bus, ata_Status);
129 }
130
131 static inline UBYTE ata_ReadAltStatus(struct ata_Bus *bus)
132 {
133 return PIO_InAlt(bus, ata_AltStatus);
134 }
135
136 static inline BOOL ata_SelectUnit(struct ata_Unit* unit)
137 {
138 struct ata_Bus *bus = unit->au_Bus;
139
140 if (unit == bus->ab_SelectedUnit)
141 return TRUE;
142
143 PIO_Out(bus, unit->au_DevMask, ata_DevHead);
144
145 do
146 {
147 ata_WaitNano(400, bus->ab_Base);
148 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
149 }
150 while (0 != (ATAF_BUSY & ata_ReadStatus(bus)));
151
152 bus->ab_SelectedUnit = unit;
153
154 return TRUE;
155 }
156
157 /*
158 * handle IRQ; still fast and efficient, supposed to verify if this irq is for us and take adequate steps
159 * part of code moved here from ata.c to reduce containment
160 */
161 static void ata_IRQSignalTask(struct ata_Bus *bus)
162 {
163 bus->ab_IntCnt++;
164 Signal(bus->ab_Task, 1UL << bus->ab_SleepySignal);
165 }
166
167 static void ata_IRQSetHandler(struct ata_Unit *unit,
168 void (*handler)(struct ata_Unit*, UBYTE), APTR piomem, ULONG blklen,
169 ULONG piolen)
170 {
171 if (NULL != handler)
172 unit->au_cmd_error = 0;
173
174 unit->au_cmd_data = piomem;
175 unit->au_cmd_length = (piolen < blklen) ? piolen : blklen;
176 unit->au_cmd_total = piolen;
177 unit->au_Bus->ab_HandleIRQ = handler;
178 }
179
180 static void ata_IRQNoData(struct ata_Unit *unit, UBYTE status)
181 {
182 if (status & ATAF_BUSY)
183 return;
184
185 if ((unit->au_cmd_error == 0) && (status & ATAF_ERROR))
186 unit->au_cmd_error = HFERR_BadStatus;
187
188 DIRQ(bug("[ATA%02ld] IRQ: NoData - done; status %02lx.\n", unit->au_UnitNum, status));
189 ata_IRQSetHandler(unit, NULL, NULL, 0, 0);
190 ata_IRQSignalTask(unit->au_Bus);
191 }
192
193 static void ata_IRQPIORead(struct ata_Unit *unit, UBYTE status)
194 {
195 if (status & ATAF_DATAREQ)
196 {
197 DIRQ(bug("[ATA%02ld] IRQ: PIOReadData - DRQ.\n", unit->au_UnitNum));
198
199 Unit_InS(unit, unit->au_cmd_data, unit->au_cmd_length);
200
201 /*
202 * Adjust data pointer and counter. If there's more data left for
203 * this transfer, keep same handler and wait for next interrupt
204 */
205 unit->au_cmd_data += unit->au_cmd_length;
206 unit->au_cmd_total -= unit->au_cmd_length;
207 if (unit->au_cmd_total != 0)
208 {
209 if (unit->au_cmd_length > unit->au_cmd_total)
210 unit->au_cmd_length = unit->au_cmd_total;
211 return;
212 }
213 DIRQ(bug("[ATA%02ld] IRQ: PIOReadData - transfer completed.\n",
214 unit->au_UnitNum));
215 }
216 else
217 unit->au_cmd_error = HFERR_BadStatus;
218 ata_IRQNoData(unit, status);
219 }
220
221 static void ata_PIOWriteBlk(struct ata_Unit *unit)
222 {
223 Unit_OutS(unit, unit->au_cmd_data, unit->au_cmd_length);
224
225 /*
226 * Adjust data pointer and counter
227 */
228 unit->au_cmd_data += unit->au_cmd_length;
229 unit->au_cmd_total -= unit->au_cmd_length;
230 if (unit->au_cmd_length > unit->au_cmd_total)
231 unit->au_cmd_length = unit->au_cmd_total;
232 }
233
234 static void ata_IRQPIOWrite(struct ata_Unit *unit, UBYTE status)
235 {
236 /*
237 * If there's more data left for this transfer, write it, keep same
238 * handler and wait for next interrupt
239 */
240 if (status & ATAF_DATAREQ) {
241 DIRQ(bug("[ATA%02ld] IRQ: PIOWriteData - DRQ.\n", unit->au_UnitNum));
242 ata_PIOWriteBlk(unit);
243 return;
244 }
245 else if (unit->au_cmd_total != 0)
246 unit->au_cmd_error = HFERR_BadStatus;
247 DIRQ(bug("[ATA%02ld] IRQ: PIOWriteData - done.\n", unit->au_UnitNum));
248 ata_IRQNoData(unit, status);
249 }
250
251 static void ata_IRQDMAReadWrite(struct ata_Unit *unit, UBYTE status)
252 {
253 struct ata_Bus *bus = unit->au_Bus;
254 ULONG stat = DMA_GetResult(bus);
255
256 DIRQ(bug("[ATA%02ld] IRQ: IO status %02lx, DMA status %02lx\n", unit->au_UnitNum, status, stat));
257
258 if ((status & ATAF_ERROR) || stat)
259 {
260 /* This is turned on in order to help Phantom - Pavel Fedin <sonic_amiga@rambler.ru> */
261 DERROR(bug("[ATA%02ld] IRQ: IO status %02lx, DMA status %d\n", unit->au_UnitNum, status, stat));
262 DERROR(bug("[ATA%02ld] IRQ: ERROR %02lx\n", unit->au_UnitNum, PIO_In(bus, atapi_Error)));
263 DERROR(bug("[ATA%02ld] IRQ: DMA Failed.\n", unit->au_UnitNum));
264
265 unit->au_cmd_error = stat;
266 ata_IRQNoData(unit, status);
267 }
268 else if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
269 {
270 DIRQ(bug("[ATA%02ld] IRQ: DMA Done.\n", unit->au_UnitNum));
271 ata_IRQNoData(unit, status);
272 }
273 }
274
275 static void ata_IRQPIOReadAtapi(struct ata_Unit *unit, UBYTE status)
276 {
277 struct ata_Bus *bus = unit->au_Bus;
278 ULONG size = 0;
279 LONG remainder = 0;
280 UBYTE reason = PIO_In(bus, atapi_Reason);
281 DIRQ(bug("[ATAPI] Current status: %ld during READ\n", reason));
282
283 /* have we failed yet? */
284 if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
285 ata_IRQNoData(unit, status);
286 if (status & ATAF_ERROR)
287 {
288 ata_IRQNoData(unit, status);
289 return;
290 }
291
292 /* anything for us please? */
293 if (ATAPIF_READ != (reason & ATAPIF_MASK))
294 return;
295
296 size = PIO_In(bus, atapi_ByteCntH) << 8 | PIO_In(bus, atapi_ByteCntL);
297 DIRQ(bug("[ATAPI] IRQ: data available for read (%ld bytes, max: %ld bytes)\n", size, unit->au_cmd_total));
298
299 if (size > unit->au_cmd_total)
300 {
301 DERROR(bug("[ATAPI] IRQ: CRITICAL! MORE DATA OFFERED THAN STORAGE CAN TAKE: %ld bytes vs %ld bytes left!\n", size, unit->au_cmd_total));
302 remainder = size - unit->au_cmd_total;
303 size = unit->au_cmd_total;
304 }
305
306 Unit_InS(unit, unit->au_cmd_data, size);
307
308 unit->au_cmd_data = &((UBYTE*)unit->au_cmd_data)[size];
309 unit->au_cmd_total -= size;
310
311 DIRQ(bug("[ATAPI] IRQ: %lu bytes read.\n", size));
312
313 /*
314 * Soak up excess bytes.
315 */
316 for (; remainder > 0; remainder -= 2)
317 Unit_InS(unit, &size, 2);
318
319 if (unit->au_cmd_total == 0)
320 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
321 }
322
323 static void ata_IRQPIOWriteAtapi(struct ata_Unit *unit, UBYTE status)
324 {
325 struct ata_Bus *bus = unit->au_Bus;
326 ULONG size = 0;
327 UBYTE reason = PIO_In(bus, atapi_Reason);
328
329 DIRQ(bug("[ATAPI] IRQ: Current status: %ld during WRITE\n", reason));
330
331 /*
332 * have we failed yet?
333 * CHECKME: This sequence actually can trigger ata_IRQNoData() twice.
334 * Is this correct ?
335 */
336 if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
337 ata_IRQNoData(unit, status);
338 if (status & ATAF_ERROR)
339 {
340 ata_IRQNoData(unit, status);
341 return;
342 }
343
344 /* anything for us please? */
345 if (ATAPIF_WRITE != (reason & ATAPIF_MASK))
346 return;
347
348 size = PIO_In(bus, atapi_ByteCntH) << 8 | PIO_In(bus, atapi_ByteCntL);
349 DIRQ(bug("[ATAPI] IRQ: data requested for write (%ld bytes, max: %ld bytes)\n", size, unit->au_cmd_total));
350
351 if (size > unit->au_cmd_total)
352 {
353 DERROR(bug("[ATAPI] IRQ: CRITICAL! MORE DATA REQUESTED THAN STORAGE CAN GIVE: %ld bytes vs %ld bytes left!\n", size, unit->au_cmd_total));
354 size = unit->au_cmd_total;
355 }
356
357 Unit_OutS(unit, unit->au_cmd_data, size);
358 unit->au_cmd_data = &((UBYTE*)unit->au_cmd_data)[size];
359 unit->au_cmd_total -= size;
360
361 DIRQ(bug("[ATAPI] IRQ: %lu bytes written.\n", size));
362
363 if (unit->au_cmd_total == 0)
364 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
365 }
366
367 /*
368 * wait for timeout or drive ready
369 */
370 static BOOL ata_WaitBusyTO(struct ata_Unit *unit, UWORD tout, BOOL irq,
371 BOOL fake_irq, UBYTE *stout)
372 {
373 struct ata_Bus *bus = unit->au_Bus;
374 UBYTE status;
375 ULONG step = 0;
376 BOOL res = TRUE;
377
378 if (bus->ab_Base->ata_Poll)
379 irq = FALSE;
380
381 status = PIO_InAlt(bus, ata_AltStatus);
382
383 if (irq)
384 {
385 /*
386 * wait for either IRQ or timeout
387 */
388 DIRQ(bug("[ATA%02ld] Waiting (Current status: %02lx)...\n",
389 unit->au_UnitNum, status));
390 step = ata_WaitTO(unit->au_Bus->ab_Timer, tout, 0,
391 1 << bus->ab_SleepySignal);
392
393 if (step == 0)
394 {
395 DERROR(bug("[ATA%02ld] Timeout while waiting for device to complete"
396 " operation\n", unit->au_UnitNum));
397
398 Disable();
399 if (fake_irq)
400 {
401 /* fake the interrupt we expected */
402 status = PIO_In(bus, ata_Status);
403 while (unit->au_Bus->ab_HandleIRQ != NULL)
404 unit->au_Bus->ab_HandleIRQ(unit, status);
405 }
406 else
407 {
408 /* do nothing if the interrupt eventually arrives */
409 ata_IRQSetHandler(unit, NULL, NULL, 0, 0);
410 res = FALSE;
411 }
412 Enable();
413 }
414 }
415 else
416 {
417 while (status & ATAF_BUSY)
418 {
419 ++step;
420
421 /*
422 * every 16n rounds do some extra stuff
423 */
424 if ((step & 15) == 0)
425 {
426 /*
427 * huhm. so it's been 16n rounds already. any timeout yet?
428 */
429 if (step >> 4 > tout * 1000)
430 {
431 DERROR(bug("[ATA%02ld] Device still busy after timeout."
432 " Aborting\n", unit->au_UnitNum));
433 res = FALSE;
434 break;
435 }
436
437 /*
438 * no timeout just yet, but it's not a good idea to keep
439 * spinning like that. let's give the system some time.
440 */
441 ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1000, 0);
442 }
443
444 status = PIO_InAlt(bus, ata_AltStatus);
445 }
446 }
447
448 /*
449 * get final status and clear any interrupt (may be neccessary if we
450 * were polling, for example)
451 */
452 status = PIO_In(bus, ata_Status);
453
454 /*
455 * be nice to frustrated developer
456 */
457 DIRQ(bug("[ATA%02ld] WaitBusy status: %lx / %ld\n", unit->au_UnitNum,
458 status, res));
459
460 /*
461 * release old junk
462 */
463 SetSignal(0, 1 << bus->ab_SleepySignal);
464
465 /*
466 * and say it went fine (i mean it)
467 */
468 if (stout)
469 *stout = status;
470 return res;
471 }
472
473 /*
474 * Procedure for sending ATA command blocks
475 * it appears LARGE but there's a lot of COMMENTS here :)
476 * handles *all* ata commands (no data, pio and dma)
477 * naturally could be split at some point in the future
478 * depends if anyone believes that the change for 50 lines
479 * would make slow ATA transfers any faster
480 */
481 static BYTE ata_exec_cmd(struct ata_Unit* unit, ata_CommandBlock *block)
482 {
483 struct ata_Bus *bus = unit->au_Bus;
484 BYTE err = 0;
485 APTR mem = block->buffer;
486 UBYTE status;
487
488 /*
489 * Use a short timeout for Identify commands. This is because some bad
490 * drives make us think that there are two devices on the bus when there
491 * is really only one, so when we send an Identify command to the phantom
492 * drive, we can't rely on getting an IRQ. Additionally, some real drives
493 * don't produce an IRQ when the Identify command is complete, so we call
494 * the interrupt handler "manually" if we time out while waiting for it.
495 */
496 BOOL fake_irq = block->command == ATA_IDENTIFY_DEVICE
497 || block->command == ATA_IDENTIFY_ATAPI;
498 UWORD timeout = fake_irq? 1 : TIMEOUT;
499
500 if (FALSE == ata_SelectUnit(unit))
501 return IOERR_UNITBUSY;
502
503 switch (block->type)
504 {
505 case CT_CHS:
506 case CT_LBA28:
507 if (block->sectors > 256)
508 {
509 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Transfer length (%ld) exceeds 256 sectors. Aborting.\n", unit->au_UnitNum, block->sectors));
510 return IOERR_BADLENGTH;
511 }
512
513 /* note:
514 * we want the above to fall in here!
515 * we really do (checking for secmul)
516 */
517
518 case CT_LBA48:
519 if (block->sectors > 65536)
520 {
521 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Transfer length (%ld) exceeds 65536 sectors. Aborting.\n", unit->au_UnitNum, block->sectors));
522 return IOERR_BADLENGTH;
523 }
524 if (block->secmul == 0)
525 {
526 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Invalid transfer multiplier. Should be at least set to 1 (correcting)\n", unit->au_UnitNum));
527 block->secmul = 1;
528 }
529 break;
530
531 case CT_NoBlock:
532 break;
533
534 default:
535 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Invalid command type %lx. Aborting.\n", unit->au_UnitNum, block->type));
536 return IOERR_NOCMD;
537 }
538
539 block->actual = 0;
540 D(bug("[ATA%02ld] ata_exec_cmd: Executing command %02lx\n", unit->au_UnitNum, block->command));
541
542 if (block->feature != 0)
543 PIO_Out(bus, block->feature, ata_Feature);
544
545 /*
546 * - set LBA and sector count
547 */
548 switch (block->type)
549 {
550 case CT_CHS:
551 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses CHS addressing (OLD)\n", unit->au_UnitNum));
552 {
553 ULONG cyl, head, sector;
554 ULONG tmp = unit->au_Heads * unit->au_Sectors;
555 cyl = block->blk / tmp;
556 head = (block->blk % tmp) / unit->au_Sectors;
557 sector = (block->blk % unit->au_Sectors) + 1;
558
559 PIO_Out(bus, ((head) & 0x0f) | unit->au_DevMask, ata_DevHead);
560 PIO_Out(bus, sector, ata_Sector);
561 PIO_Out(bus, cyl & 0xff, ata_CylinderLow);
562 PIO_Out(bus, (cyl >> 8) & 0xff, ata_CylinderHigh);
563 PIO_Out(bus, block->sectors, ata_Count);
564 }
565 break;
566 case CT_LBA28:
567 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses 28bit LBA addressing (OLD)\n", unit->au_UnitNum));
568
569 PIO_Out(bus, ((block->blk >> 24) & 0x0f) | DEVHEAD_VAL | unit->au_DevMask, ata_DevHead);
570 PIO_Out(bus, block->blk >> 16, ata_LBAHigh);
571 PIO_Out(bus, block->blk >> 8, ata_LBAMid);
572 PIO_Out(bus, block->blk, ata_LBALow);
573 PIO_Out(bus, block->sectors, ata_Count);
574 break;
575
576 case CT_LBA48:
577 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses 48bit LBA addressing (NEW)\n", unit->au_UnitNum));
578
579 PIO_Out(bus, DEVHEAD_VAL | unit->au_DevMask, ata_DevHead);
580 PIO_Out(bus, block->blk >> 40, ata_LBAHigh);
581 PIO_Out(bus, block->blk >> 32, ata_LBAMid);
582 PIO_Out(bus, block->blk >> 24, ata_LBALow);
583
584 PIO_Out(bus, block->blk >> 16, ata_LBAHigh);
585 PIO_Out(bus, block->blk >> 8, ata_LBAMid);
586 PIO_Out(bus, block->blk, ata_LBALow);
587
588 PIO_Out(bus, block->sectors >> 8, ata_Count);
589 PIO_Out(bus, block->sectors, ata_Count);
590 break;
591
592 case CT_NoBlock:
593 DATA(bug("[ATA%02ld] ata_exec_cmd: Command does not address any block\n", unit->au_UnitNum));
594 break;
595 }
596
597 switch (block->method)
598 {
599 case CM_PIOWrite:
600 ata_IRQSetHandler(unit, &ata_IRQPIOWrite, mem, block->secmul << unit->au_SectorShift, block->length);
601 break;
602
603 case CM_PIORead:
604 ata_IRQSetHandler(unit, &ata_IRQPIORead, mem, block->secmul << unit->au_SectorShift, block->length);
605 break;
606
607 case CM_DMARead:
608 if (FALSE == DMA_Setup(bus, mem, block->length, TRUE))
609 return IOERR_ABORTED;
610
611 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
612 DMA_Start(bus);
613 break;
614
615 case CM_DMAWrite:
616 if (FALSE == DMA_Setup(bus, mem, block->length, FALSE))
617 return IOERR_ABORTED;
618
619 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
620 DMA_Start(bus);
621 break;
622
623 case CM_NoData:
624 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
625 break;
626
627 default:
628 return IOERR_NOCMD;
629 break;
630 };
631
632 /*
633 * send command now
634 * let drive propagate its signals
635 */
636 DATA(bug("[ATA%02ld] ata_exec_cmd: Sending command\n", unit->au_UnitNum));
637
638 PIO_Out(bus, block->command, ata_Command);
639 ata_WaitNano(400, bus->ab_Base);
640 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
641
642 /*
643 * In case of PIO write the drive won't issue an IRQ before first
644 * data transfer, so we should poll the status and send the first
645 * block upon request.
646 */
647 if (block->method == CM_PIOWrite)
648 {
649 if (FALSE == ata_WaitBusyTO(unit, TIMEOUT, FALSE, FALSE, &status)) {
650 DERROR(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - no response from device. Status %02X\n", unit->au_UnitNum, status));
651 return IOERR_UNITBUSY;
652 }
653 if (status & ATAF_DATAREQ) {
654 DATA(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - DRQ.\n", unit->au_UnitNum));
655 ata_PIOWriteBlk(unit);
656 }
657 else
658 {
659 DERROR(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - bad status: %02X\n", status));
660 return HFERR_BadStatus;
661 }
662 }
663
664 /*
665 * wait for drive to complete what it has to do
666 */
667 if (FALSE == ata_WaitBusyTO(unit, timeout, TRUE, fake_irq, &status))
668 {
669 DERROR(bug("[ATA%02ld] ata_exec_cmd: Device is late - no response\n", unit->au_UnitNum));
670 err = IOERR_UNITBUSY;
671 }
672 else
673 err = unit->au_cmd_error;
674
675 DATA(bug("[ATA%02ld] ata_exec_cmd: Command done\n", unit->au_UnitNum));
676
677 /*
678 * clean up DMA
679 * don't use 'mem' pointer here as it's already invalid.
680 */
681 switch (block->method)
682 {
683 case CM_DMARead:
684 DMA_End(bus, block->buffer, block->length, TRUE);
685 break;
686
687 case CM_DMAWrite:
688 DMA_End(bus, block->buffer, block->length, FALSE);
689 break;
690
691 default:
692 break; /* Shut up the compiler */
693 }
694
695 D(bug("[ATA%02ld] ata_exec_cmd: return code %ld\n", unit->au_UnitNum, err));
696 return err;
697 }
698
699 /*
700 * atapi packet iface
701 */
702 static BYTE atapi_SendPacket(struct ata_Unit *unit, APTR packet, APTR data,
703 LONG datalen, BOOL *dma, BOOL write)
704 {
705 struct ata_Bus *bus = unit->au_Bus;
706 *dma = *dma && (unit->au_Flags & AF_DMA) ? TRUE : FALSE;
707 LONG err = 0;
708
709 UBYTE cmd[12] = {
710 0
711 };
712 register int t=5,l=0;
713
714 if (((UBYTE*)packet)[0] > 0x1f)
715 t+= 4;
716 if (((UBYTE*)packet)[0] > 0x5f)
717 t+= 2;
718
719 switch (((UBYTE*)packet)[0])
720 {
721 case 0x28: // read10
722 case 0xa8: // read12
723 case 0xbe: // readcd
724 case 0xb9: // readcdmsf
725 case 0x2f: // verify
726 case 0x2a: // write
727 case 0xaa: // write12
728 case 0x2e: // writeverify
729 case 0xad: // readdvdstructure
730 case 0xa4: // reportkey
731 case 0xa3: // sendkey
732 break;
733 default:
734 *dma = FALSE;
735 }
736
737 while (l<=t)
738 {
739 cmd[l] = ((UBYTE*)packet)[l];
740 ++l;
741 }
742
743 DATAPI({
744 bug("[ATA%02lx] Sending %s ATA packet: ", unit->au_UnitNum, (*dma) ? "DMA" : "PIO");
745 l=0;
746 while (l<=t)
747 {
748 bug("%02lx ", ((UBYTE*)cmd)[l]);
749 ++l;
750 }
751 bug("\n");
752
753 if (datalen & 1)
754 bug("[ATAPI] ERROR: DATA LENGTH NOT EVEN! Rounding Up! (%ld bytes requested)\n", datalen);
755 });
756
757 datalen = (datalen+1)&~1;
758
759 if (FALSE == ata_SelectUnit(unit))
760 {
761 DATAPI(bug("[ATAPI] WaitBusy failed at first check\n"));
762 return IOERR_UNITBUSY;
763 }
764
765 /*
766 * tell device whether we want to read or write and if we want a dma transfer
767 */
768 PIO_Out(bus,
769 ((*dma) ? 1 : 0) | (((unit->au_Drive->id_DMADir & 0x8000) && !write) ? 4 : 0),
770 atapi_Features);
771 PIO_Out(bus, (datalen & 0xff), atapi_ByteCntL);
772 PIO_Out(bus, (datalen >> 8) & 0xff, atapi_ByteCntH);
773
774 /*
775 * once we're done with that, we can go ahead and inform device that we're about to send atapi packet
776 * after command is dispatched, we are obliged to give 400ns for the unit to parse command and set status
777 */
778 DATAPI(bug("[ATAPI] Issuing ATA_PACKET command.\n"));
779 ata_IRQSetHandler(unit, &ata_IRQNoData, 0, 0, 0);
780 PIO_Out(bus, ATA_PACKET, atapi_Command);
781 ata_WaitNano(400, bus->ab_Base);
782 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
783
784 ata_WaitBusyTO(unit, TIMEOUT, (unit->au_Drive->id_General & 0x60) == 0x20,
785 FALSE, NULL);
786 if (0 == (ata_ReadStatus(bus) & ATAF_DATAREQ))
787 return HFERR_BadStatus;
788
789 /*
790 * setup appropriate hooks
791 */
792 if (datalen == 0)
793 ata_IRQSetHandler(unit, &ata_IRQNoData, 0, 0, 0);
794 else if (*dma)
795 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
796 else if (write)
797 ata_IRQSetHandler(unit, &ata_IRQPIOWriteAtapi, data, 0, datalen);
798 else
799 ata_IRQSetHandler(unit, &ata_IRQPIOReadAtapi, data, 0, datalen);
800
801 if (*dma)
802 {
803 DATAPI(bug("[ATAPI] Starting DMA\n"));
804 DMA_Start(bus);
805 }
806
807 DATAPI(bug("[ATAPI] Sending packet\n"));
808 Unit_OutS(unit, cmd, 12);
809 ata_WaitNano(400, bus->ab_Base);
810
811 DATAPI(bug("[ATAPI] Status after packet: %lx\n", ata_ReadAltStatus(bus)));
812
813 /*
814 * Wait for command to complete. Note that two interrupts will occur
815 * before we wake up if this is a PIO data transfer
816 */
817 if (ata_WaitTO(unit->au_Bus->ab_Timer, TIMEOUT, 0,
818 1 << unit->au_Bus->ab_SleepySignal) == 0)
819 {
820 DATAPI(bug("[DSCSI] Command timed out.\n"));
821 err = IOERR_UNITBUSY;
822 }
823 else
824 err = atapi_EndCmd(unit);
825
826 if (*dma)
827 {
828 DMA_End(bus, data, datalen, !write);
829 }
830
831 DATAPI(bug("[ATAPI] IO error code %ld\n", err));
832 return err;
833 }
834
835 static BYTE atapi_DirectSCSI(struct ata_Unit *unit, struct SCSICmd *cmd)
836 {
837 APTR buffer = cmd->scsi_Data;
838 ULONG length = cmd->scsi_Length;
839 BYTE err = 0;
840 BOOL dma = FALSE;
841
842 cmd->scsi_Actual = 0;
843
844 DATAPI(bug("[DSCSI] Sending packet!\n"));
845
846 /*
847 * setup DMA & push command
848 * it does not really mean we will use dma here btw
849 */
850 if ((unit->au_Flags & AF_DMA) && (length !=0) && (buffer != 0))
851 {
852 dma = DMA_Setup(unit->au_Bus, buffer, length,
853 cmd->scsi_Flags & SCSIF_READ);
854 }
855
856 err = atapi_SendPacket(unit, cmd->scsi_Command, cmd->scsi_Data, cmd->scsi_Length, &dma, (cmd->scsi_Flags & SCSIF_READ) == 0);
857
858 DUMP({ if (cmd->scsi_Data != 0) dump(cmd->scsi_Data, cmd->scsi_Length); });
859
860 /*
861 * on check condition - grab sense data
862 */
863 DATAPI(bug("[ATA%02lx] atapi_DirectSCSI: SCSI Flags: %02lx / Error: %ld\n", unit->au_UnitNum, cmd->scsi_Flags, err));
864 if ((err != 0) && (cmd->scsi_Flags & SCSIF_AUTOSENSE))
865 {
866 DATAPI(bug("[DSCSI] atapi_DirectSCSI: Packet Failed. Calling atapi_RequestSense\n"));
867 atapi_RequestSense(unit, cmd->scsi_SenseData, cmd->scsi_SenseLength);
868 DUMP(dump(cmd->scsi_SenseData, cmd->scsi_SenseLength));
869 }
870
871 return err;
872 }
873
874 /*
875 * chops the large transfers into set of smaller transfers
876 * specifically useful when requested transfer size is >256 sectors for 28bit commands
877 */
878 static BYTE ata_exec_blk(struct ata_Unit *unit, ata_CommandBlock *blk)
879 {
880 BYTE err = 0;
881 ULONG part;
882 ULONG max=256;
883 ULONG count=blk->sectors;
884
885 if (blk->type == CT_LBA48)
886 max <<= 8;
887
888 DATA(bug("[ATA%02ld] ata_exec_blk: Accessing %ld sectors starting from %x%08x\n", unit->au_UnitNum, count, (ULONG)(blk->blk >> 32), (ULONG)blk->blk));
889 while ((count > 0) && (err == 0))
890 {
891 part = (count > max) ? max : count;
892 blk->sectors = part;
893 blk->length = part << unit->au_SectorShift;
894
895 DATA(bug("[ATA%02ld] Transfer of %ld sectors from %x%08x\n", unit->au_UnitNum, part, (ULONG)(blk->blk >> 32), (ULONG)blk->blk));
896 err = ata_exec_cmd(unit, blk);
897 DATA(bug("[ATA%02ld] ata_exec_blk: ata_exec_cmd returned %lx\n", unit->au_UnitNum, err));
898
899 blk->blk += part;
900 blk->buffer = &((char*)blk->buffer)[part << unit->au_SectorShift];
901 count -= part;
902 }
903 return err;
904 }
905
906 /*
907 * Initial device configuration that suits *all* cases
908 */
909 void ata_init_unit(struct ata_Bus *bus, struct ata_Unit *unit, UBYTE u)
910 {
911 struct ataBase *ATABase = bus->ab_Base;
912 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
913
914 unit->au_Bus = bus;
915 unit->pioInterface = bus->pioInterface;
916 unit->au_UnitNum = bus->ab_BusNum << 1 | u; // b << 8 | u
917 unit->au_DevMask = 0xa0 | (u << 4);
918
919 DINIT(bug("[ATA%02u] ata_init_unit: bus %u unit %d\n", unit->au_UnitNum, bus->ab_BusNum, u));
920
921 /* Set PIO transfer functions, either 16 or 32 bits */
922 if (ATABase->ata_32bit && OOP_GET(obj, aHidd_ATABus_Use32Bit))
923 Unit_Enable32Bit(unit);
924 else
925 Unit_Disable32Bit(unit);
926 }
927
928 BOOL ata_setup_unit(struct ata_Bus *bus, struct ata_Unit *unit)
929 {
930 /*
931 * this stuff always goes along the same way
932 * WARNING: NO INTERRUPTS AT THIS POINT!
933 */
934 UBYTE u;
935
936 DINIT(bug("[ATA ] ata_setup_unit(%d)\n", unit->au_UnitNum));
937 ata_SelectUnit(unit);
938
939 if (FALSE == ata_WaitBusyTO(unit, 1, FALSE, FALSE, NULL))
940 {
941 DINIT(bug("[ATA%02ld] ata_setup_unit: ERROR: Drive not ready for use. Keeping functions stubbed\n", unit->au_UnitNum));
942 return FALSE;
943 }
944
945 u = unit->au_UnitNum & 1;
946 switch (bus->ab_Dev[u])
947 {
948 /*
949 * safe fallback settings
950 */
951 case DEV_SATAPI:
952 case DEV_ATAPI:
953 case DEV_SATA:
954 case DEV_ATA:
955 unit->au_Identify = ata_Identify;
956 break;
957
958 default:
959 DINIT(bug("[ATA%02ld] ata_setup_unit: Unsupported device %lx. All functions will remain stubbed.\n", unit->au_UnitNum, bus->ab_Dev[u]));
960 return FALSE;
961 }
962
963 DINIT(bug("[ATA ] ata_setup_unit: Enabling IRQs\n"));
964 PIO_OutAlt(bus, 0x0, ata_AltControl);
965
966 /*
967 * now make unit self diagnose
968 */
969 if (unit->au_Identify(unit) != 0)
970 {
971 return FALSE;
972 }
973
974 return TRUE;
975 }
976
977 /*
978 * ata[pi] identify
979 */
980 static void common_SetXferMode(struct ata_Unit* unit, ata_XferMode mode)
981 {
982 struct ata_Bus *bus = unit->au_Bus;
983 BOOL dma = FALSE;
984 /*
985 * We can't set drive modes unless we also set the controller's timing registers
986 * FIXME: Implement aoHodd_ATABus_CanSetXferMode and moHidd_ATABus_SetXferMode
987 support.
988 * CHECKME: Current code lives with what machine's firmware has set for us. Looks
989 * like all firmwares set up the best DMA mode. But what if the firmware
990 * didn't set it up for some reason (the add-on controller which has been
991 * ignored by it
992 * for example) ? Shouldn't we check unit->au_UseModes here ?
993 */
994 #if 0
995 struct ataBase *ATABase = bus->ab_Base;
996 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
997 UBYTE type=0;
998 ata_CommandBlock acb =
999 {
1000 ATA_SET_FEATURES,
1001 0x03,
1002 0x01,
1003 0x00,
1004 0x00,
1005 0x00,
1006 0x00,
1007 0x00,
1008 0x00,
1009 CM_NoData,
1010 CT_LBA28
1011 };
1012 #endif
1013 DINIT(bug("[ATA%02ld] common_SetXferMode: Trying to set mode %d\n", unit->au_UnitNum, mode));
1014
1015 /* CHECKME: This condition should be not needed. */
1016 if ((!bus->dmaVectors) && (mode >= AB_XFER_MDMA0))
1017 {
1018 DINIT(bug("[ATA%02ld] common_SetXferMode: This controller does not own DMA port! Will set best PIO\n", unit->au_UnitNum));
1019 common_SetBestXferMode(unit);
1020 return;
1021 }
1022
1023 /*
1024 * first, ONLY for ATA devices, set new commands
1025 */
1026 if (0 == (unit->au_XferModes & AF_XFER_PACKET))
1027 {
1028 if ((mode >= AB_XFER_MDMA0) && (mode <= AB_XFER_UDMA6))
1029 {
1030 /* DMA, both multiword and Ultra */
1031 unit->au_Read32 = ata_ReadDMA32;
1032 unit->au_Write32 = ata_WriteDMA32;
1033 if (unit->au_XferModes & AF_XFER_48BIT)
1034 {
1035 unit->au_UseModes |= AF_XFER_48BIT;
1036 unit->au_Read64 = ata_ReadDMA64;
1037 unit->au_Write64 = ata_WriteDMA64;
1038 }
1039 }
1040 else if ((!unit->au_Bus->ab_Base->ata_NoMulti) && (unit->au_XferModes & AF_XFER_RWMULTI))
1041 {
1042 /* Multisector PIO */
1043 ata_IRQSetHandler(unit, ata_IRQNoData, NULL, 0, 0);
1044 PIO_Out(bus, unit->au_Drive->id_RWMultipleSize & 0xFF, ata_Count);
1045 PIO_Out(bus, ATA_SET_MULTIPLE, ata_Command);
1046 ata_WaitBusyTO(unit, -1, TRUE, FALSE, NULL);
1047
1048 unit->au_UseModes |= AF_XFER_RWMULTI;
1049 unit->au_Read32 = ata_ReadMultiple32;
1050 unit->au_Write32 = ata_WriteMultiple32;
1051 if (unit->au_XferModes & AF_XFER_48BIT)
1052 {
1053 unit->au_UseModes |= AF_XFER_48BIT;
1054 unit->au_Read64 = ata_ReadMultiple64;
1055 unit->au_Write64 = ata_WriteMultiple64;
1056 }
1057 }
1058 else
1059 {
1060 /* 1-sector PIO */
1061 unit->au_Read32 = ata_ReadSector32;
1062 unit->au_Write32 = ata_WriteSector32;
1063 if (unit->au_XferModes & AF_XFER_48BIT)
1064 {
1065 unit->au_UseModes |= AF_XFER_48BIT;
1066 unit->au_Read64 = ata_ReadSector64;
1067 unit->au_Write64 = ata_WriteSector64;
1068 }
1069 }
1070 }
1071
1072 #if 0 // We can't set drive modes unless we also set the controller's timing registers
1073 if ((mode >= AB_XFER_PIO0) && (mode <= AB_XFER_PIO4))
1074 {
1075 type = 8 + (mode - AB_XFER_PIO0);
1076 }
1077 else if ((mode >= AB_XFER_MDMA0) && (mode <= AB_XFER_MDMA2))
1078 {
1079 type = 32 + (mode - AB_XFER_MDMA0);
1080 dma=TRUE;
1081 }
1082 else if ((mode >= AB_XFER_UDMA0) && (mode <= AB_XFER_UDMA6))
1083 {
1084 type = 64 + (mode - AB_XFER_UDMA0);
1085 dma=TRUE;
1086 }
1087 else
1088 {
1089 type = 0;
1090 }
1091
1092 acb.sectors = type;
1093 if (0 != ata_exec_cmd(unit, &acb))
1094 {
1095 DINIT(bug("[ATA%02ld] common_SetXferMode: ERROR: Failed to apply new xfer mode.\n", unit->au_UnitNum));
1096 }
1097
1098 if (!HIDD_ATABus_SetXferMode(obj, mode))
1099 {
1100 /*
1101 * DMA mode setup failed.
1102 * FIXME: Should completely revert back to PIO protocol, or try lower mode.
1103 */
1104 dma = FALSE;
1105 }
1106 #else
1107 if (mode >= AB_XFER_MDMA0)
1108 dma = TRUE;
1109 #endif
1110
1111 if (dma)
1112 {
1113 unit->au_Flags |= AF_DMA; /* This flag is used by ATAPI protocol */
1114 }
1115 else
1116 {
1117 unit->au_UseModes &= ~AF_XFER_DMA_MASK;
1118 unit->au_Flags &= ~AF_DMA;
1119 }
1120 }
1121
1122 static void common_SetBestXferMode(struct ata_Unit* unit)
1123 {
1124 struct ata_Bus *bus = unit->au_Bus;
1125 struct ataBase *ATABase = bus->ab_Base;
1126 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
1127 int iter;
1128 int max = AB_XFER_UDMA6;
1129
1130 if ((!bus->dmaInterface)
1131 || ( !(unit->au_Drive->id_MWDMASupport & 0x0700)
1132 && !(unit->au_Drive->id_UDMASupport & 0x7f00)))
1133 {
1134 /*
1135 * make sure you reduce scan search to pio here!
1136 * otherwise this and above function will fall into infinite loop
1137 */
1138 DINIT(bug("[ATA%02ld] common_SetBestXferMode: DMA is disabled for"
1139 " this drive.\n", unit->au_UnitNum));
1140 max = AB_XFER_PIO4;
1141 }
1142 else if (!OOP_GET(obj, aHidd_ATABus_Use80Wire))
1143 {
1144 DINIT(bug("[ATA%02ld] common_SetBestXferMode: "
1145 "An 80-wire cable has not been detected for this drive. "
1146 "Disabling modes above UDMA2.\n", unit->au_UnitNum));
1147 max = AB_XFER_UDMA2;
1148 }
1149
1150 for (iter=max; iter>=AB_XFER_PIO0; --iter)
1151 {
1152 if (unit->au_XferModes & (1<<iter))
1153 {
1154 common_SetXferMode(unit, iter);
1155 return;
1156 }
1157 }
1158 bug("[ATA%02ld] common_SetBestXferMode: ERROR: device never reported any valid xfer modes. will continue at default\n", unit->au_UnitNum);
1159 common_SetXferMode(unit, AB_XFER_PIO0);
1160 }
1161
1162 static void common_DetectXferModes(struct ata_Unit* unit)
1163 {
1164 int iter;
1165
1166 DINIT(bug("[ATA%02ld] common_DetectXferModes: Supports\n", unit->au_UnitNum));
1167
1168 if (unit->au_Drive->id_Commands4 & (1 << 4))
1169 {
1170 DINIT(bug("[ATA%02ld] common_DetectXferModes: - Packet interface\n", unit->au_UnitNum));
1171 unit->au_XferModes |= AF_XFER_PACKET;
1172 unit->au_DirectSCSI = atapi_DirectSCSI;
1173 }
1174 else if (unit->au_Drive->id_Commands5 & (1 << 10))
1175 {
1176 /* ATAPI devices do not use this bit. */
1177 DINIT(bug("[ATA%02ld] common_DetectXferModes: - 48bit I/O\n", unit->au_UnitNum));
1178 unit->au_XferModes |= AF_XFER_48BIT;
1179 }
1180
1181 if ((unit->au_XferModes & AF_XFER_PACKET) || (unit->au_Drive->id_Capabilities & (1<< 9)))
1182 {
1183 DINIT(bug("[ATA%02ld] common_DetectXferModes: - LBA Addressing\n", unit->au_UnitNum));
1184 unit->au_XferModes |= AF_XFER_LBA;
1185 unit->au_UseModes |= AF_XFER_LBA;
1186 }
1187 else
1188 {
1189 DINIT(bug("[ATA%02ld] common_DetectXferModes: - DEVICE DOES NOT SUPPORT LBA ADDRESSING >> THIS IS A POTENTIAL PROBLEM <<\n", unit->au_UnitNum));
1190 unit->au_Flags |= AF_CHSOnly;
1191 }
1192
1193 if (unit->au_Drive->id_RWMultipleSize & 0xff)
1194 {
1195 DINIT(bug("[ATA%02ld] common_DetectXferModes: - R/W Multiple (%ld sectors per xfer)\n", unit->au_UnitNum, unit->au_Drive->id_RWMultipleSize & 0xff));
1196 unit->au_XferModes |= AF_XFER_RWMULTI;
1197 }
1198
1199 DINIT(bug("[ATA%02ld] common_DetectXferModes: - PIO0 PIO1 PIO2 ",
1200 unit->au_UnitNum));
1201 unit->au_XferModes |= AF_XFER_PIO(0) | AF_XFER_PIO(1) | AF_XFER_PIO(2);
1202 if (unit->au_Drive->id_ConfigAvailable & (1 << 1))
1203 {
1204 for (iter = 0; iter < 2; iter++)
1205 {
1206 if (unit->au_Drive->id_PIOSupport & (1 << iter))
1207 {
1208 DINIT(bug("PIO%ld ", 3 + iter));
1209 unit->au_XferModes |= AF_XFER_PIO(3 + iter);
1210 }
1211 }
1212 DINIT(bug("\n"));
1213 }
1214
1215 if ((unit->au_Drive->id_ConfigAvailable & (1 << 1)) &&
1216 (unit->au_Drive->id_Capabilities & (1<<8)))
1217 {
1218 DINIT(bug("[ATA%02ld] common_DetectXferModes: DMA:\n", unit->au_UnitNum));
1219 if (unit->au_Drive->id_MWDMASupport & 0xff)
1220 {
1221 DINIT(bug("[ATA%02ld] common_DetectXferModes: - ", unit->au_UnitNum));
1222 for (iter = 0; iter < 3; iter++)
1223 {
1224 if (unit->au_Drive->id_MWDMASupport & (1 << iter))
1225 {
1226 unit->au_XferModes |= AF_XFER_MDMA(iter);
1227 if (unit->au_Drive->id_MWDMASupport & (256 << iter))
1228 {
1229 unit->au_UseModes |= AF_XFER_MDMA(iter);
1230 DINIT(bug("[MDMA%ld] ", iter));
1231 }
1232 DINIT(else bug("MDMA%ld ", iter);)
1233 }
1234 }
1235 DINIT(bug("\n"));
1236 }
1237
1238 if (unit->au_Drive->id_UDMASupport & 0xff)
1239 {
1240 DINIT(bug("[ATA%02ld] common_DetectXferModes: - ", unit->au_UnitNum));
1241 for (iter = 0; iter < 7; iter++)
1242 {
1243 if (unit->au_Drive->id_UDMASupport & (1 << iter))
1244 {
1245 unit->au_XferModes |= AF_XFER_UDMA(iter);
1246 if (unit->au_Drive->id_UDMASupport & (256 << iter))
1247 {
1248 unit->au_UseModes |= AF_XFER_UDMA(iter);
1249 DINIT(bug("[UDMA%ld] ", iter));
1250 }
1251 DINIT(else bug("UDMA%ld ", iter);)
1252 }
1253 }
1254 DINIT(bug("\n"));
1255 }
1256 }
1257 }
1258
1259 #define SWAP_LE_WORD(x) (x) = AROS_LE2WORD((x))
1260 #define SWAP_LE_LONG(x) (x) = AROS_LE2LONG((x))
1261 #define SWAP_LE_QUAD(x) (x) = AROS_LE2LONG((x) >> 32) | (((QUAD)(AROS_LE2LONG((x) & 0xffffffff))) << 32)
1262
1263 static BYTE ata_Identify(struct ata_Unit *unit)
1264 {
1265 BOOL atapi = unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] & 0x80;
1266 BOOL supportLBA, supportLBA48;
1267 ata_CommandBlock acb =
1268 {
1269 atapi ? ATA_IDENTIFY_ATAPI : ATA_IDENTIFY_DEVICE,
1270 0,
1271 1,
1272 0,
1273 0,
1274 0,
1275 unit->au_Drive,
1276 sizeof(struct DriveIdent),
1277 0,
1278 CM_PIORead,
1279 CT_NoBlock
1280 };
1281 UWORD n = 0, *p, *limit;
1282
1283 /* If the right command fails, try the wrong one. If both fail, abort */
1284 DINIT(bug("[ATA%02ld] ata_Identify: Executing ATA_IDENTIFY_%s command\n",
1285 unit->au_UnitNum, atapi ? "ATAPI" : "DEVICE"));
1286 if (ata_exec_cmd(unit, &acb))
1287 {
1288 acb.command = atapi ? ATA_IDENTIFY_DEVICE : ATA_IDENTIFY_ATAPI;
1289 DINIT(bug("[ATA%02ld] ata_Identify: Executing ATA_IDENTIFY_%s command"
1290 " instead\n", unit->au_UnitNum, atapi ? "DEVICE" : "ATAPI"));
1291 if (ata_exec_cmd(unit, &acb))
1292 {
1293 DINIT(bug("[ATA%02ld] ata_Identify: Both command variants failed."
1294 " Discarding drive.\n",
1295 unit->au_UnitNum));
1296 return IOERR_OPENFAIL;
1297 }
1298 unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] ^= 0x82;
1299 atapi = unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] & 0x80;
1300 DINIT(bug("[ATA%02ld] ata_Identify:"
1301 " Incorrect device signature detected."
1302 " Switching device type to %lx.\n", unit->au_UnitNum,
1303 unit->au_Bus->ab_Dev[unit->au_UnitNum & 1]));
1304 }
1305
1306 /*
1307 * If every second word is zero with 32-bit reads, switch to 16-bit
1308 * accesses for this drive and try again
1309 */
1310 if (unit->au_Bus->ab_Base->ata_32bit)
1311 {
1312 for (p = (UWORD *)unit->au_Drive, limit = p + 256; p < limit; p++)
1313 n |= *++p;
1314
1315 if (n == 0)
1316 {
1317 DINIT(bug("[ATA%02ld] Identify data was invalid with 32-bit reads."
1318 " Switching to 16-bit mode.\n", unit->au_UnitNum));
1319
1320 Unit_Disable32Bit(unit);
1321
1322 if (ata_exec_cmd(unit, &acb))
1323 return IOERR_OPENFAIL;
1324 }
1325 }
1326
1327 #if (AROS_BIG_ENDIAN != 0)
1328 SWAP_LE_WORD(unit->au_Drive->id_General);
1329 SWAP_LE_WORD(unit->au_Drive->id_OldCylinders);
1330 SWAP_LE_WORD(unit->au_Drive->id_SpecificConfig);
1331 SWAP_LE_WORD(unit->au_Drive->id_OldHeads);
1332 SWAP_LE_WORD(unit->au_Drive->id_OldSectors);
1333 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleSize);
1334 SWAP_LE_WORD(unit->au_Drive->id_Capabilities);
1335 SWAP_LE_WORD(unit->au_Drive->id_OldCaps);
1336 SWAP_LE_WORD(unit->au_Drive->id_OldPIO);
1337 SWAP_LE_WORD(unit->au_Drive->id_ConfigAvailable);
1338 SWAP_LE_WORD(unit->au_Drive->id_OldLCylinders);
1339 SWAP_LE_WORD(unit->au_Drive->id_OldLHeads);
1340 SWAP_LE_WORD(unit->au_Drive->id_OldLSectors);
1341 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleTrans);
1342 SWAP_LE_WORD(unit->au_Drive->id_DMADir);
1343 SWAP_LE_WORD(unit->au_Drive->id_MWDMASupport);
1344 SWAP_LE_WORD(unit->au_Drive->id_PIOSupport);
1345 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_MinCycleTime);
1346 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_DefCycleTime);
1347 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTime);
1348 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTimeIORDY);
1349 SWAP_LE_WORD(unit->au_Drive->id_QueueDepth);
1350 SWAP_LE_WORD(unit->au_Drive->id_ATAVersion);
1351 SWAP_LE_WORD(unit->au_Drive->id_ATARevision);
1352 SWAP_LE_WORD(unit->au_Drive->id_Commands1);
1353 SWAP_LE_WORD(unit->au_Drive->id_Commands2);
1354 SWAP_LE_WORD(unit->au_Drive->id_Commands3);
1355 SWAP_LE_WORD(unit->au_Drive->id_Commands4);
1356 SWAP_LE_WORD(unit->au_Drive->id_Commands5);
1357 SWAP_LE_WORD(unit->au_Drive->id_Commands6);
1358 SWAP_LE_WORD(unit->au_Drive->id_UDMASupport);
1359 SWAP_LE_WORD(unit->au_Drive->id_SecurityEraseTime);
1360 SWAP_LE_WORD(unit->au_Drive->id_ESecurityEraseTime);
1361 SWAP_LE_WORD(unit->au_Drive->id_CurrentAdvPowerMode);
1362 SWAP_LE_WORD(unit->au_Drive->id_MasterPwdRevision);
1363 SWAP_LE_WORD(unit->au_Drive->id_HWResetResult);
1364 SWAP_LE_WORD(unit->au_Drive->id_AcousticManagement);
1365 SWAP_LE_WORD(unit->au_Drive->id_StreamMinimunReqSize);
1366 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimeDMA);
1367 SWAP_LE_WORD(unit->au_Drive->id_StreamingLatency);
1368 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimePIO);
1369 SWAP_LE_WORD(unit->au_Drive->id_PhysSectorSize);
1370 SWAP_LE_WORD(unit->au_Drive->id_RemMediaStatusNotificationFeatures);
1371 SWAP_LE_WORD(unit->au_Drive->id_SecurityStatus);
1372
1373 SWAP_LE_LONG(unit->au_Drive->id_WordsPerLogicalSector);
1374 SWAP_LE_LONG(unit->au_Drive->id_LBASectors);
1375 SWAP_LE_LONG(unit->au_Drive->id_StreamingGranularity);
1376
1377 SWAP_LE_QUAD(unit->au_Drive->id_LBA48Sectors);
1378 #endif
1379
1380 DUMP(dump(unit->au_Drive, sizeof(struct DriveIdent)));
1381
1382 if (atapi)
1383 {
1384 unit->au_SectorShift = 11;
1385 unit->au_Read32 = atapi_Read;
1386 unit->au_Write32 = atapi_Write;
1387 unit->au_DirectSCSI = atapi_DirectSCSI;
1388 unit->au_Eject = atapi_Eject;
1389 unit->au_Flags |= AF_DiscChanged;
1390 unit->au_DevType = (unit->au_Drive->id_General >>8) & 0x1f;
1391 unit->au_XferModes = AF_XFER_PACKET;
1392 unit->au_UseModes |= AF_XFER_PACKET; /* OR because this field may already contain AF_XFER_PIO32 */
1393 }
1394 else
1395 {
1396 unit->au_SectorShift = 9;
1397 unit->au_DevType = DG_DIRECT_ACCESS;
1398 unit->au_Read32 = ata_ReadSector32;
1399 unit->au_Write32 = ata_WriteSector32;
1400 unit->au_Eject = ata_Eject;
1401 unit->au_XferModes = 0;
1402 unit->au_Flags |= AF_DiscPresent | AF_DiscChanged;
1403 }
1404
1405 ata_strcpy(unit->au_Drive->id_Model, unit->au_Model, 40);
1406 ata_strcpy(unit->au_Drive->id_SerialNumber, unit->au_SerialNumber, 20);
1407 ata_strcpy(unit->au_Drive->id_FirmwareRev, unit->au_FirmwareRev, 8);
1408
1409 bug("[ATA%02ld] ata_Identify: Unit info: %s / %s / %s\n", unit->au_UnitNum, unit->au_Model, unit->au_SerialNumber, unit->au_FirmwareRev);
1410 common_DetectXferModes(unit);
1411 common_SetBestXferMode(unit);
1412
1413 if (unit->au_Drive->id_General & 0x80)
1414 {
1415 DINIT(bug("[ATA%02ld] ata_Identify: Device is removable.\n", unit->au_UnitNum));
1416 unit->au_Flags |= AF_Removable;
1417 }
1418
1419 supportLBA = (unit->au_Drive->id_Capabilities & (1 << 9)) != 0;
1420 supportLBA48 = supportLBA && (unit->au_Drive->id_Commands5 & (1 << 10)) != 0;
1421
1422 unit->au_Capacity = unit->au_Drive->id_LBASectors;
1423 if (supportLBA48)
1424 unit->au_Capacity48 = unit->au_Drive->id_LBA48Sectors;
1425 else
1426 unit->au_Capacity48 = unit->au_Capacity;
1427
1428 DINIT(bug("[ATA%02ld] ata_Identify: Unit LBA%d: %07lx 28bit / %04lx:%08lx 48bit addressable blocks\n",
1429 unit->au_UnitNum, supportLBA48 ? 48 : (supportLBA ? 28 : 0),
1430 unit->au_Capacity, (ULONG)(unit->au_Capacity48 >> 32), (ULONG)(unit->au_Capacity48 & 0xfffffffful)));
1431
1432 if (atapi)
1433 {
1434 /*
1435 * ok, this is not very original, but quite compatible :P
1436 */
1437 switch (unit->au_DevType)
1438 {
1439 case DG_CDROM:
1440 case DG_WORM:
1441 case DG_OPTICAL_DISK:
1442 unit->au_SectorShift = 11;
1443 unit->au_Heads = 1;
1444 unit->au_Sectors = 75;
1445 unit->au_Cylinders = 4440;
1446 break;
1447
1448 case DG_DIRECT_ACCESS:
1449 unit->au_SectorShift = 9;
1450 if (!strcmp("LS-120", &unit->au_Model[0]))
1451 {
1452 unit->au_Heads = 2;
1453 unit->au_Sectors = 18;
1454 unit->au_Cylinders = 6848;
1455 }
1456 else if (!strcmp("ZIP 100 ", &unit->au_Model[8]))
1457 {
1458 unit->au_Heads = 1;
1459 unit->au_Sectors = 64;
1460 unit->au_Cylinders = 3072;
1461 }
1462 break;
1463 }
1464
1465 atapi_TestUnitOK(unit);
1466 }
1467 else
1468 {
1469 /*
1470 For drive capacities > 8.3GB assume maximal possible layout.
1471 It really doesn't matter here, as BIOS will not handle them in
1472 CHS way anyway :)
1473 i guess this just solves that weirdo div-by-zero crash, if nothing
1474 else...
1475 */
1476 if (supportLBA && ((unit->au_Drive->id_LBA48Sectors > (63 * 255 * 1024)) ||
1477 (unit->au_Drive->id_LBASectors > (63 * 255 * 1024))))
1478 {
1479 ULONG div = 1;
1480 /*
1481 * TODO: this shouldn't be casted down here.
1482 */
1483 ULONG sec = unit->au_Capacity48;
1484
1485 if (sec < unit->au_Capacity48)
1486 sec = ~((ULONG)0);
1487
1488 if (sec < unit->au_Capacity)
1489 sec = unit->au_Capacity;
1490
1491 unit->au_Sectors = 63;
1492 sec /= 63;
1493 /*
1494 * keep dividing by 2
1495 */
1496 do
1497 {
1498 if (((sec >> 1) << 1) != sec)
1499 break;
1500 if ((div << 1) > 255)
1501 break;
1502 div <<= 1;
1503 sec >>= 1;
1504 } while (1);
1505
1506 do
1507 {
1508 if (((sec / 3) * 3) != sec)
1509 break;
1510 if ((div * 3) > 255)
1511 break;
1512 div *= 3;
1513 sec /= 3;
1514 } while (1);
1515
1516 unit->au_Cylinders = sec;
1517 unit->au_Heads = div;
1518 }
1519 else
1520 {
1521 unit->au_Cylinders = unit->au_Drive->id_OldLCylinders;
1522 unit->au_Heads = unit->au_Drive->id_OldLHeads;
1523 unit->au_Sectors = unit->au_Drive->id_OldLSectors;
1524 if (!supportLBA) {
1525 unit->au_Capacity = unit->au_Cylinders * unit->au_Heads * unit->au_Sectors;
1526 unit->au_Capacity48 = unit->au_Capacity;
1527 }
1528 }
1529 }
1530
1531 DINIT(bug("[ATA%02ld] ata_Identify: Unit CHS: %d/%d/%d\n", unit->au_UnitNum, unit->au_Cylinders, unit->au_Heads, unit->au_Sectors));
1532
1533 return 0;
1534 }
1535
1536 /*
1537 * ata read32 commands
1538 */
1539 static BYTE ata_ReadSector32(struct ata_Unit *unit, ULONG block,
1540 ULONG count, APTR buffer, ULONG *act)
1541 {
1542 ata_CommandBlock acb =
1543 {
1544 ATA_READ,
1545 0,
1546 1,
1547 0,
1548 block,
1549 count,
1550 buffer,
1551 count << unit->au_SectorShift,
1552 0,
1553 CM_PIORead,
1554 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1555 };
1556 BYTE err;
1557
1558 D(bug("[ATA%02ld] ata_ReadSector32()\n", unit->au_UnitNum));
1559
1560 *act = 0;
1561 if (0 != (err = ata_exec_blk(unit, &acb)))
1562 return err;
1563
1564 *act = count << unit->au_SectorShift;
1565 return 0;
1566 }
1567
1568 static BYTE ata_ReadMultiple32(struct ata_Unit *unit, ULONG block,
1569 ULONG count, APTR buffer, ULONG *act)
1570 {
1571 ata_CommandBlock acb =
1572 {
1573 ATA_READ_MULTIPLE,
1574 0,
1575 unit->au_Drive->id_RWMultipleSize & 0xff,
1576 0,
1577 block,
1578 count,
1579 buffer,
1580 count << unit->au_SectorShift,
1581 0,
1582 CM_PIORead,
1583 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1584 };
1585 BYTE err;
1586
1587 D(bug("[ATA%02ld] ata_ReadMultiple32()\n", unit->au_UnitNum));
1588
1589 *act = 0;
1590 if (0 != (err = ata_exec_blk(unit, &acb)))
1591 return err;
1592
1593 *act = count << unit->au_SectorShift;
1594 return 0;
1595 }
1596
1597 static BYTE ata_ReadDMA32(struct ata_Unit *unit, ULONG block,
1598 ULONG count, APTR buffer, ULONG *act)
1599 {
1600 BYTE err;
1601 ata_CommandBlock acb =
1602 {
1603 ATA_READ_DMA,
1604 0,
1605 1,
1606 0,
1607 block,
1608 count,
1609 buffer,
1610 count << unit->au_SectorShift,
1611 0,
1612 CM_DMARead,
1613 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1614 };
1615
1616 D(bug("[ATA%02ld] ata_ReadDMA32()\n", unit->au_UnitNum));
1617
1618 *act = 0;
1619 if (0 != (err = ata_exec_blk(unit, &acb)))
1620 return err;
1621
1622 *act = count << unit->au_SectorShift;
1623 return 0;
1624 }
1625
1626 /*
1627 * ata read64 commands
1628 */
1629 static BYTE ata_ReadSector64(struct ata_Unit *unit, UQUAD block,
1630 ULONG count, APTR buffer, ULONG *act)
1631 {
1632 ata_CommandBlock acb =
1633 {
1634 ATA_READ64,
1635 0,
1636 1,
1637 0,
1638 block,
1639 count,
1640 buffer,
1641 count << unit->au_SectorShift,
1642 0,
1643 CM_PIORead,
1644 CT_LBA48
1645 };
1646 BYTE err = 0;
1647
1648 D(bug("[ATA%02ld] ata_ReadSector64()\n", unit->au_UnitNum));
1649
1650 *act = 0;
1651 if (0 != (err = ata_exec_blk(unit, &acb)))
1652 return err;
1653
1654 *act = count << unit->au_SectorShift;
1655 return 0;
1656 }
1657
1658 static BYTE ata_ReadMultiple64(struct ata_Unit *unit, UQUAD block,
1659 ULONG count, APTR buffer, ULONG *act)
1660 {
1661 ata_CommandBlock acb =
1662 {
1663 ATA_READ_MULTIPLE64,
1664 0,
1665 unit->au_Drive->id_RWMultipleSize & 0xff,
1666 0,
1667 block,
1668 count,
1669 buffer,
1670 count << unit->au_SectorShift,
1671 0,
1672 CM_PIORead,
1673 CT_LBA48
1674 };
1675 BYTE err;
1676
1677 D(bug("[ATA%02ld] ata_ReadMultiple64()\n", unit->au_UnitNum));
1678
1679 *act = 0;
1680 if (0 != (err = ata_exec_blk(unit, &acb)))
1681 return err;
1682
1683 *act = count << unit->au_SectorShift;
1684 return 0;
1685 }
1686
1687 static BYTE ata_ReadDMA64(struct ata_Unit *unit, UQUAD block,
1688 ULONG count, APTR buffer, ULONG *act)
1689 {
1690 ata_CommandBlock acb =
1691 {
1692 ATA_READ_DMA64,
1693 0,
1694 1,
1695 0,
1696 block,
1697 count,
1698 buffer,
1699 count << unit->au_SectorShift,
1700 0,
1701 CM_DMARead,
1702 CT_LBA48
1703 };
1704 BYTE err;
1705
1706 D(bug("[ATA%02ld] ata_ReadDMA64()\n", unit->au_UnitNum));
1707
1708 *act = 0;
1709 if (0 != (err = ata_exec_blk(unit, &acb)))
1710 return err;
1711
1712 *act = count << unit->au_SectorShift;
1713 return 0;
1714 }
1715
1716 /*
1717 * ata write32 commands
1718 */
1719 static BYTE ata_WriteSector32(struct ata_Unit *unit, ULONG block,
1720 ULONG count, APTR buffer, ULONG *act)
1721 {
1722 ata_CommandBlock acb =
1723 {
1724 ATA_WRITE,
1725 0,
1726 1,
1727 0,
1728 block,
1729 count,
1730 buffer,
1731 count << unit->au_SectorShift,
1732 0,
1733 CM_PIOWrite,
1734 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1735 };
1736 BYTE err;
1737
1738 D(bug("[ATA%02ld] ata_WriteSector32()\n", unit->au_UnitNum));
1739
1740 *act = 0;
1741 if (0 != (err = ata_exec_blk(unit, &acb)))
1742 return err;
1743
1744 *act = count << unit->au_SectorShift;
1745 return 0;
1746 }
1747
1748 static BYTE ata_WriteMultiple32(struct ata_Unit *unit, ULONG block,
1749 ULONG count, APTR buffer, ULONG *act)
1750 {
1751 ata_CommandBlock acb =
1752 {
1753 ATA_WRITE_MULTIPLE,
1754 0,
1755 unit->au_Drive->id_RWMultipleSize & 0xff,
1756 0,
1757 block,
1758 count,
1759 buffer,
1760 count << unit->au_SectorShift,
1761 0,
1762 CM_PIOWrite,
1763 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1764 };
1765 BYTE err;
1766
1767 D(bug("[ATA%02ld] ata_WriteMultiple32()\n", unit->au_UnitNum));
1768
1769 *act = 0;
1770 if (0 != (err = ata_exec_blk(unit, &acb)))
1771 return err;
1772
1773 *act = count << unit->au_SectorShift;
1774 return 0;
1775 }
1776
1777 static BYTE ata_WriteDMA32(struct ata_Unit *unit, ULONG block,
1778 ULONG count, APTR buffer, ULONG *act)
1779 {
1780 ata_CommandBlock acb =
1781 {
1782 ATA_WRITE_DMA,
1783 0,
1784 1,
1785 0,
1786 block,
1787 count,
1788 buffer,
1789 count << unit->au_SectorShift,
1790 0,
1791 CM_DMAWrite,
1792 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1793 };
1794 BYTE err;
1795
1796 D(bug("[ATA%02ld] ata_WriteDMA32()\n", unit->au_UnitNum));
1797
1798 *act = 0;
1799 if (0 != (err = ata_exec_blk(unit, &acb)))
1800 return err;
1801
1802 *act = count << unit->au_SectorShift;
1803 return 0;
1804 }
1805
1806 /*
1807 * ata write64 commands
1808 */
1809 static BYTE ata_WriteSector64(struct ata_Unit *unit, UQUAD block,
1810 ULONG count, APTR buffer, ULONG *act)
1811 {
1812 ata_CommandBlock acb =
1813 {
1814 ATA_WRITE64,
1815 0,
1816 1,
1817 0,
1818 block,
1819 count,
1820 buffer,
1821 count << unit->au_SectorShift,
1822 0,
1823 CM_PIOWrite,
1824 CT_LBA48
1825 };
1826 BYTE err;
1827
1828 D(bug("[ATA%02ld] ata_WriteSector64()\n", unit->au_UnitNum));
1829
1830 *act = 0;
1831 if (0 != (err = ata_exec_blk(unit, &acb)))
1832 return err;
1833
1834 *act = count << unit->au_SectorShift;
1835 return 0;
1836 }
1837
1838 static BYTE ata_WriteMultiple64(struct ata_Unit *unit, UQUAD block,
1839 ULONG count, APTR buffer, ULONG *act)
1840 {
1841 ata_CommandBlock acb =
1842 {
1843 ATA_WRITE_MULTIPLE64,
1844 0,
1845 unit->au_Drive->id_RWMultipleSize & 0xff,
1846 0,
1847 block,
1848 count,
1849 buffer,
1850 count << unit->au_SectorShift,
1851 0,
1852 CM_PIOWrite,
1853 CT_LBA48
1854 };
1855 BYTE err;
1856
1857 D(bug("[ATA%02ld] ata_WriteMultiple64()\n", unit->au_UnitNum));
1858
1859 *act = 0;
1860 if (0 != (err = ata_exec_blk(unit, &acb)))
1861 return err;
1862
1863 *act = count << unit->au_SectorShift;
1864 return 0;
1865 }
1866
1867 static BYTE ata_WriteDMA64(struct ata_Unit *unit, UQUAD block,
1868 ULONG count, APTR buffer, ULONG *act)
1869 {
1870 ata_CommandBlock acb =
1871 {
1872 ATA_WRITE_DMA64,
1873 0,
1874 1,
1875 0,
1876 block,
1877 count,
1878 buffer,
1879 count << unit->au_SectorShift,
1880 0,
1881 CM_DMAWrite,
1882 CT_LBA48
1883 };
1884 BYTE err;
1885
1886 D(bug("[ATA%02ld] ata_WriteDMA64()\n", unit->au_UnitNum));
1887
1888 *act = 0;
1889 if (0 != (err = ata_exec_blk(unit, &acb)))
1890 return err;
1891
1892 *act = count << unit->au_SectorShift;
1893 return 0;
1894 }
1895
1896 /*
1897 * ata miscellaneous commands
1898 */
1899 static BYTE ata_Eject(struct ata_Unit *unit)
1900 {
1901 ata_CommandBlock acb =
1902 {
1903 ATA_MEDIA_EJECT,
1904 0,
1905 0,
1906 0,
1907 0,
1908 0,
1909 0,
1910 0,
1911 0,
1912 CM_NoData,
1913 CT_NoBlock
1914 };
1915
1916 D(bug("[ATA%02ld] ata_Eject()\n", unit->au_UnitNum));
1917
1918 return ata_exec_cmd(unit, &acb);
1919 }
1920
1921 /*
1922 * atapi commands
1923 */
1924 int atapi_TestUnitOK(struct ata_Unit *unit)
1925 {
1926 UBYTE cmd[6] = {
1927 0
1928 };
1929 UBYTE sense[16] = {
1930 0
1931 };
1932 struct SCSICmd sc = {
1933 0
1934 };
1935
1936 D(bug("[ATA%02ld] atapi_TestUnitOK()\n", unit->au_UnitNum));
1937
1938 sc.scsi_Command = (void*) &cmd;
1939 sc.scsi_CmdLength = sizeof(cmd);
1940 sc.scsi_SenseData = (void*)&sense;
1941 sc.scsi_SenseLength = sizeof(sense);
1942 sc.scsi_Flags = SCSIF_AUTOSENSE;
1943
1944 DATAPI(bug("[ATA%02ld] atapi_TestUnitOK: Testing Unit Ready sense...\n", unit->au_UnitNum));
1945 unit->au_DirectSCSI(unit, &sc);
1946 unit->au_SenseKey = sense[2];
1947
1948 /*
1949 * we may have just lost the disc...?
1950 */
1951 /*
1952 * per MMC, drives are expected to return 02-3a-0# status, when disc is not present
1953 * that would translate into following code:
1954 * int p1 = ((sense[2] == 2) && (sense[12] == 0x3a)) ? 1 : 0;
1955 * unfortunately, it's what MMC says, not what vendors code.
1956 */
1957 int p1 = (sense[2] == 2) ? 1 : 0;
1958 int p2 = (0 != (AF_DiscPresent & unit->au_Flags)) ? 1 : 0;
1959
1960 if (p1 == p2)
1961 {
1962 //unit->au_Flags ^= AF_DiscPresent;
1963 if (p1 == 0)
1964 unit->au_Flags |= AF_DiscPresent;
1965 else
1966 unit->au_Flags &= ~AF_DiscPresent;
1967
1968 unit->au_Flags |= AF_DiscChanged;
1969 }
1970
1971 DATAPI(bug("[ATA%02ld] atapi_TestUnitOK: Test Unit Ready sense: %02lx, Media %s\n", unit->au_UnitNum, sense[2], unit->au_Flags & AF_DiscPresent ? "PRESENT" : "ABSENT"));
1972 return sense[2];
1973 }
1974
1975 static BYTE atapi_Read(struct ata_Unit *unit, ULONG block, ULONG count,
1976 APTR buffer, ULONG *act)
1977 {
1978 UBYTE cmd[] = {
1979 SCSI_READ10, 0, block>>24, block>>16, block>>8, block, 0, count>>8, count, 0
1980 };
1981 struct SCSICmd sc = {
1982 0
1983 };
1984
1985 D(bug("[ATA%02ld] atapi_Read()\n", unit->au_UnitNum));
1986
1987 sc.scsi_Command = (void*) &cmd;
1988 sc.scsi_CmdLength = sizeof(cmd);
1989 sc.scsi_Data = buffer;
1990 sc.scsi_Length = count << unit->au_SectorShift;
1991 sc.scsi_Flags = SCSIF_READ;
1992
1993 return unit->au_DirectSCSI(unit, &sc);
1994 }
1995
1996 static BYTE atapi_Write(struct ata_Unit *unit, ULONG block, ULONG count,
1997 APTR buffer, ULONG *act)
1998 {
1999 UBYTE cmd[] = {
2000 SCSI_WRITE10, 0, block>>24, block>>16, block>>8, block, 0, count>>8, count, 0
2001 };
2002 struct SCSICmd sc = {
2003 0
2004 };
2005
2006 D(bug("[ATA%02ld] atapi_Write()\n", unit->au_UnitNum));
2007
2008 sc.scsi_Command = (void*) &cmd;
2009 sc.scsi_CmdLength = sizeof(cmd);
2010 sc.scsi_Data = buffer;
2011 sc.scsi_Length = count << unit->au_SectorShift;
2012 sc.scsi_Flags = SCSIF_WRITE;
2013
2014 return unit->au_DirectSCSI(unit, &sc);
2015 }
2016
2017 static BYTE atapi_Eject(struct ata_Unit *unit)
2018 {
2019 struct atapi_StartStop cmd = {
2020 command: SCSI_STARTSTOP,
2021 immediate: 1,
2022 flags: ATAPI_SS_EJECT,
2023 };
2024
2025 struct SCSICmd sc = {
2026 0
2027 };
2028
2029 D(bug("[ATA%02ld] atapi_Eject()\n", unit->au_UnitNum));
2030
2031 sc.scsi_Command = (void*) &cmd;
2032 sc.scsi_CmdLength = sizeof(cmd);
2033 sc.scsi_Flags = SCSIF_READ;
2034
2035 return unit->au_DirectSCSI(unit, &sc);
2036 }
2037
2038 static ULONG atapi_RequestSense(struct ata_Unit* unit, UBYTE* sense,
2039 ULONG senselen)
2040 {
2041 UBYTE cmd[] = {
2042 3, 0, 0, 0, senselen & 0xfe, 0
2043 };
2044 struct SCSICmd sc = {
2045 0
2046 };
2047
2048 D(bug("[ATA%02ld] atapi_RequestSense()\n", unit->au_UnitNum));
2049
2050 if ((senselen == 0) || (sense == 0))
2051 {
2052 return 0;
2053 }
2054 sc.scsi_Data = (void*)sense;
2055 sc.scsi_Length = senselen & 0xfe;
2056 sc.scsi_Command = (void*)&cmd;
2057 sc.scsi_CmdLength = 6;
2058 sc.scsi_Flags = SCSIF_READ;
2059
2060 unit->au_DirectSCSI(unit, &sc);
2061
2062 DATAPI(dump(sense, senselen));
2063 DATAPI(bug("[SENSE] atapi_RequestSense: sensed data: %lx %lx %lx\n", sense[2]&0xf, sense[12], sense[13]));
2064 return ((sense[2]&0xf)<<16) | (sense[12]<<8) | (sense[13]);
2065 }
2066
2067 static ULONG ata_ReadSignature(struct ata_Bus *bus, int unit,
2068 BOOL *DiagExecuted)
2069 {
2070 UBYTE tmp1, tmp2;
2071
2072 D(bug("[ATA ] ata_ReadSignature(%02ld)\n", unit));
2073
2074 PIO_Out(bus, DEVHEAD_VAL | (unit << 4), ata_DevHead);
2075 ata_WaitNano(400, bus->ab_Base);
2076 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2077
2078 DINIT(bug("[ATA ] ata_ReadSignature: Status %02lx Device %02lx\n",
2079 ata_ReadStatus(bus), PIO_In(bus, ata_DevHead)));
2080
2081 /* Ok, ATA/ATAPI device. Get detailed signature */
2082 DINIT(bug("[ATA ] ata_ReadSignature: ATA[PI] device present. Attempting to detect specific subtype\n"));
2083
2084 tmp1 = PIO_In(bus, ata_LBAMid);
2085 tmp2 = PIO_In(bus, ata_LBAHigh);
2086
2087 DINIT(bug("[ATA ] ata_ReadSignature: Subtype check returned %02lx:%02lx (%04lx)\n", tmp1, tmp2, (tmp1 << 8) | tmp2));
2088
2089 switch ((tmp1 << 8) | tmp2)
2090 {
2091 case 0x14eb:
2092 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for ATAPI device\n"));
2093 return DEV_ATAPI;
2094
2095 case 0x3cc3:
2096 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for SATA device\n"));
2097 return DEV_SATA;
2098
2099 case 0x6996:
2100 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for SATAPI device\n"));
2101 return DEV_SATAPI;
2102
2103 default:
2104 if (0 == (ata_ReadStatus(bus) & 0xfe)) {
2105 DINIT(bug("[ATA ] ata_ReadSignature: Found NONE\n"));
2106 return DEV_NONE;
2107 }
2108
2109 /* ATA_EXECUTE_DIAG is executed by both devices, do it only once */
2110 if (!*DiagExecuted)
2111 {
2112 DINIT(bug("[ATA ] ata_ReadSignature: ATA_EXECUTE_DIAG\n"));
2113 PIO_Out(bus, ATA_EXECUTE_DIAG, ata_Command);
2114 *DiagExecuted = TRUE;
2115 }
2116
2117 ata_WaitTO(bus->ab_Timer, 0, 2000, 0);
2118 while (ata_ReadStatus(bus) & ATAF_BUSY)
2119 ata_WaitNano(400, bus->ab_Base);
2120 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2121
2122 DINIT(bug("[ATA ] ata_ReadSignature: ATAF_BUSY wait finished\n"));
2123
2124 PIO_Out(bus, DEVHEAD_VAL | (unit << 4), ata_DevHead);
2125 do
2126 {
2127 ata_WaitNano(400, bus->ab_Base);
2128 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
2129 }
2130 while (0 != (ATAF_BUSY & ata_ReadStatus(bus)));
2131 DINIT(bug("[ATA ] ata_ReadSignature: Further validating ATA signature: %lx & 0x7f = 1, %lx & 0x10 = unit\n",
2132 PIO_In(bus, ata_Error), PIO_In(bus, ata_DevHead)));
2133
2134 if ((PIO_In(bus, ata_Error) & 0x7f) == 1)
2135 {
2136 DINIT(bug("[ATA ] ata_ReadSignature: Found *valid* signature for ATA device\n"));
2137 /* this might still be an (S)ATAPI device, but we correct that in ata_Identify */
2138 return DEV_ATA;
2139 }
2140 DERROR(bug("[ATA ] ata_ReadSignature: Found signature for ATA "
2141 "device, but further validation failed\n"));
2142 return DEV_NONE;
2143 }
2144 }
2145
2146 static void ata_ResetBus(struct ata_Bus *bus)
2147 {
2148 struct ataBase *ATABase = bus->ab_Base;
2149 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
2150 ULONG TimeOut;
2151 BOOL DiagExecuted = FALSE;
2152 IPTR haveAltIO;
2153
2154 /*
2155 * Set and then reset the soft reset bit in the Device Control
2156 * register. This causes device 0 to be selected.
2157 */
2158 DINIT(bug("[ATA ] ata_ResetBus()\n"));
2159
2160 PIO_Out(bus, DEVHEAD_VAL, ata_DevHead); /* Select it never the less */
2161 ata_WaitNano(400, ATABase);
2162 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2163
2164 OOP_GetAttr(obj, aHidd_ATABus_UseIOAlt, &haveAltIO);
2165 if (haveAltIO)
2166 {
2167 PIO_OutAlt(bus, ATACTLF_RESET | ATACTLF_INT_DISABLE, ata_AltControl);
2168 ata_WaitTO(bus->ab_Timer, 0, 10, 0); /* sleep 10us; min: 5us */
2169
2170 PIO_OutAlt(bus, ATACTLF_INT_DISABLE, ata_AltControl);
2171 }
2172 else
2173 {
2174 PIO_Out(bus, ATA_EXECUTE_DIAG, ata_Command);
2175 }
2176 ata_WaitTO(bus->ab_Timer, 0, 20000, 0); /* sleep 20ms; min: 2ms */
2177
2178 /* If there is a device 0, wait for device 0 to clear BSY */
2179 if (DEV_NONE != bus->ab_Dev[0])
2180 {
2181 DINIT(bug("[ATA ] ata_ResetBus: Wait for master to clear BSY\n"));
2182 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2183
2184 while ( 1 )
2185 {
2186 if ((ata_ReadStatus(bus) & ATAF_BUSY) == 0)
2187 break;
2188 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2189 if (!(--TimeOut)) {
2190 DINIT(bug("[ATA%02ld] ata_ResetBus: Master device Timed Out!\n"));
2191 bus->ab_Dev[0] = DEV_NONE;
2192 break;
2193 }
2194 }
2195 DINIT(bug("[ATA ] ata_ResetBus: Wait left after %d ms\n", 1000 - TimeOut));
2196 }
2197
2198 /* If there is a device 1, wait some time until device 1 allows
2199 * register access, but fail only if BSY isn't cleared */
2200 if (DEV_NONE != bus->ab_Dev[1])
2201 {
2202 DINIT(bug("[ATA ] ata_ResetBus: Wait DEV1 to allow access\n"));
2203 PIO_Out(bus, DEVHEAD_VAL | (1 << 4), ata_DevHead);
2204 ata_WaitNano(400, bus->ab_Base);
2205 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2206
2207 TimeOut = 50; /* Timeout 50ms (1ms x 50) */
2208 while ( 1 )
2209 {
2210 if ((PIO_In(bus, ata_Count) == 0x01) && (PIO_In(bus, ata_LBALow) == 0x01))
2211 break;
2212 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2213 if (!(--TimeOut))
2214 {
2215 DINIT(bug("[ATA ] ata_ResetBus: DEV1 1/2 TimeOut!\n"));
2216 break;
2217 }
2218 }
2219 DINIT(bug("[ATA ] ata_ResetBus: DEV1 1/2 Wait left after %d ms\n", 1000 - TimeOut));
2220
2221 DINIT(bug("[ATA ] ata_ResetBus: Wait for slave to clear BSY\n"));
2222 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2223 while ( 1 )
2224 {
2225 if ((ata_ReadStatus(bus) & ATAF_BUSY) == 0)
2226 break;
2227 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2228 if (!(--TimeOut)) {
2229 DINIT(bug("[ATA ] ata_ResetBus: Slave device Timed Out!\n"));
2230 bus->ab_Dev[1] = DEV_NONE;
2231 break;
2232 }
2233 }
2234 DINIT(bug("[ATA ] ata_ResetBus: Wait left after %d ms\n", 1000 - TimeOut));
2235 }
2236
2237 if (DEV_NONE != bus->ab_Dev[0])
2238 bus->ab_Dev[0] = ata_ReadSignature(bus, 0, &DiagExecuted);
2239 if (DEV_NONE != bus->ab_Dev[1])
2240 bus->ab_Dev[1] = ata_ReadSignature(bus, 1, &DiagExecuted);
2241 }
2242
2243 void ata_InitBus(struct ata_Bus *bus)
2244 {
2245 UBYTE tmp1, tmp2;
2246 UWORD i;
2247
2248 /*
2249 * initialize timer for the sake of scanning
2250 */
2251 bus->ab_Timer = ata_OpenTimer(bus->ab_Base);
2252
2253 DINIT(bug("[ATA ] ata_InitBus(%p)\n", bus));
2254
2255 bus->ab_Dev[0] = DEV_NONE;
2256 bus->ab_Dev[1] = DEV_NONE;
2257
2258 /* Check if device 0 and/or 1 is present on this bus. It may happen that
2259 a single drive answers for both device addresses, but the phantom
2260 drive will be filtered out later */
2261 for (i = 0; i < MAX_BUSUNITS; i++)
2262 {
2263 /* Select device and disable IRQs */
2264 PIO_Out(bus, DEVHEAD_VAL | (i << 4), ata_DevHead);
2265 ata_WaitTO(bus->ab_Timer, 0, 400, 0);
2266 PIO_OutAlt(bus, ATACTLF_INT_DISABLE, ata_AltControl);
2267
2268 /* Write some pattern to registers. This is a variant of a more
2269 common technique, with the difference that we don't use the
2270 sector count register because some bad ATAPI drives disallow
2271 writing to it */
2272 PIO_Out(bus, 0x55, ata_LBALow);
2273 PIO_Out(bus, 0xaa, ata_LBAMid);
2274 PIO_Out(bus, 0xaa, ata_LBALow);
2275 PIO_Out(bus, 0x55, ata_LBAMid);
2276 PIO_Out(bus, 0x55, ata_LBALow);
2277 PIO_Out(bus, 0xaa, ata_LBAMid);
2278
2279 tmp1 = PIO_In(bus, ata_LBALow);
2280 tmp2 = PIO_In(bus, ata_LBAMid);
2281 DB2(bug("[ATA ] ata_InitBus: Reply 0x%02X 0x%02X\n", tmp1, tmp2));
2282
2283 if ((tmp1 == 0x55) && (tmp2 == 0xaa))
2284 bus->ab_Dev[i] = DEV_UNKNOWN;
2285 DINIT(bug("[ATA ] ata_InitBus: Device type = 0x%02X\n", bus->ab_Dev[i]));
2286 }
2287
2288 ata_ResetBus(bus);
2289 ata_CloseTimer(bus->ab_Timer);
2290 DINIT(bug("[ATA ] ata_InitBus: Finished\n"));
2291 }
2292
2293 /*
2294 * not really sure what this is meant to be - TO BE REPLACED
2295 */
2296 static const ULONG ErrorMap[] = {
2297 CDERR_NotSpecified,
2298 CDERR_NoSecHdr,
2299 CDERR_NoDisk,
2300 CDERR_NoSecHdr,
2301 CDERR_NoSecHdr,
2302 CDERR_NOCMD,
2303 CDERR_NoDisk,
2304 CDERR_WriteProt,
2305 CDERR_NotSpecified,
2306 CDERR_NotSpecified,
2307 CDERR_NotSpecified,
2308 CDERR_ABORTED,
2309 CDERR_NotSpecified,
2310 CDERR_NotSpecified,
2311 CDERR_NoSecHdr,
2312 CDERR_NotSpecified,
2313 };
2314
2315 static BYTE atapi_EndCmd(struct ata_Unit *unit)
2316 {
2317 struct ata_Bus *bus = unit->au_Bus;
2318 UBYTE status;
2319
2320 DATAPI(bug("[ATA%02ld] atapi_EndCmd()\n", unit->au_UnitNum));
2321
2322 /*
2323 * read alternate status register (per specs)
2324 */
2325 status = PIO_InAlt(bus, ata_AltStatus);
2326 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Alternate status: %lx\n", unit->au_UnitNum, status));
2327
2328 status = PIO_In(bus, atapi_Status);
2329
2330 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Command complete. Status: %lx\n",
2331 unit->au_UnitNum, status));
2332
2333 if (!(status & ATAPIF_CHECK))
2334 {
2335 return 0;
2336 }
2337 else
2338 {
2339 status = PIO_In(bus, atapi_Error);
2340 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Error code 0x%lx\n", unit->au_UnitNum, status >> 4));
2341 return ErrorMap[status >> 4];
2342 }
2343 }
Mirror of AROS' svn.