arch/arm-raspi/boot/vc_mb.c

   1 /*
   2     Copyright © 2013-2019, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: VideoCore mailbox support routines
   6     Lang: english
   7 */
   8
   9 #include <exec/types.h>
  10 #include <aros/macros.h>
  11 #include <hardware/bcm2708.h>
  12
  13 #undef ARM_PERIIOBASE
  14
  15 #include <hardware/videocore.h>
  16 #include <stdint.h>
  17
  18 #include "boot.h"
  19 #include "io.h"
  20
  21 #define D(x) /* */
  22
  23 #define ARM_PERIIOBASE (__arm_periiobase)
  24 extern uint32_t __arm_periiobase;
  25
  26 volatile unsigned int *vcmb_read(uintptr_t mb, unsigned int chan)
  27 {
  28     unsigned int try = 0x20000000;
  29     unsigned int msg;
  30
  31     D(kprintf("[VCMB] vcmb_read(%p, %p)\n", mb, chan));
  32
  33     if (chan <= VCMB_CHAN_MAX)
  34     {
  35         while(1)
  36         {
  37             while ((rd32le(mb + VCMB_STATUS) & VCMB_STATUS_READREADY) != 0)
  38             {
  39                 /* Data synchronization barrier */
  40                 asm volatile ("mcr p15, 0, %[r], c7, c10, 4" : : [r] "r" (0) );
  41
  42                 if(try-- == 0)
  43                 {
  44                     break;
  45                 }
  46             }
  47
  48             asm volatile ("mcr p15, #0, %[r], c7, c10, #5" : : [r] "r" (0) );
  49
  50             msg = rd32le(mb + VCMB_READ);
  51             D(kprintf("[VCMB] -> %p\n", msg));
  52
  53             asm volatile ("mcr p15, #0, %[r], c7, c10, #5" : : [r] "r" (0) );
  54
  55             if ((msg & VCMB_CHAN_MASK) == chan)
  56                 return (volatile unsigned int *)(msg & ~VCMB_CHAN_MASK);
  57         }
  58     }
  59     return (volatile unsigned int *)-1;
  60 }
  61
  62 void vcmb_write(uintptr_t mb, unsigned int chan, void *msg)
  63 {
  64     D(kprintf("[VCMB] vcmb_write(%p, %p, %p)\n", mb, chan, msg));
  65
  66     if ((((unsigned int)msg & VCMB_CHAN_MASK) == 0) && (chan <= VCMB_CHAN_MAX))
  67     {
  68         while ((rd32le(mb + VCMB_STATUS) & VCMB_STATUS_WRITEREADY) != 0)
  69         {
  70                 /* Data synchronization barrier */
  71                 asm volatile ("mcr p15, 0, %[r], c7, c10, 4" : : [r] "r" (0) );
  72         }
  73
  74         asm volatile ("mcr p15, #0, %[r], c7, c10, #5" : : [r] "r" (0) );
  75
  76         wr32le(mb + VCMB_WRITE, (uintptr_t)msg | chan);
  77     }
  78 }