From c9daf8eac9ec8f8003cab3f8c092716eb354d1ad Mon Sep 17 00:00:00 2001 From: Tomek Malesinski Date: Fri, 22 Aug 2008 20:19:55 +0200 Subject: [PATCH] Have a full cycle to load playfield and char data --- antic.v | 96 ++++++++++++++++++++++++++++++++++++++++++----------------------- 1 file changed, 62 insertions(+), 34 deletions(-) diff --git a/antic.v b/antic.v index 6d48bf6..0433da2 100644 --- a/antic.v +++ b/antic.v @@ -15,21 +15,25 @@ // along with this program; if not, write to the Free Software // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -module antic_ms_hcount_seq(ms_hcount, - new_block, dma_block, dma_pf_width, ir, - shift_reg_shift, load_pf, load_out, out_reg_shift); - input ms_hcount; - input new_block, dma_block, dma_pf_width, ir; - output shift_reg_shift, load_pf, load_out, out_reg_shift; - +module antic_ms_hcount_seq(clk_i, ms_hcount, + new_block, dma_block, char_block, dma_pf_width, ir, + shift_reg_shift, load_pf, load_char, load_out, + out_reg_shift); + input clk_i, ms_hcount; + input new_block, dma_block, char_block, dma_pf_width, ir; + output shift_reg_shift, load_pf, load_char, load_out, out_reg_shift; + + wire clk_i; wire [7:0] ms_hcount; - wire new_block, dma_block; + wire new_block, dma_block, char_block; wire [1:0] dma_pf_width; wire [7:0] ir; wire shift_reg_shift; - reg load_pf, load_out; + reg load_pf, load_char; + reg load_out; wire out_reg_shift; + reg load_pf_0, load_char_0; reg [3:0] pf_byte_mod; reg [1:0] pf_pixel_mod; @@ -97,7 +101,7 @@ module antic_ms_hcount_seq(ms_hcount, end endcase - assign shift_reg_shift = (ms_hcount >= 3) && (ms_hcount < 195) && + assign shift_reg_shift = (ms_hcount >= 3) && (ms_hcount < 192 + 3) && (ms_hcount[1:0] == 3); assign out_reg_shift = ((ms_hcount[1:0] & pf_pixel_mod) == @@ -105,32 +109,50 @@ module antic_ms_hcount_seq(ms_hcount, always @ (new_block or dma_block or dma_pf_width or ms_hcount or pf_byte_mod or ir) begin - load_pf = 0; + load_pf_0 = 0; if (new_block && dma_block) begin if (dma_pf_width == 1 && !ir[4]) - load_pf = ((ms_hcount & pf_byte_mod) == (3 & pf_byte_mod)) && - (ms_hcount >= 35) && (ms_hcount < 163); + load_pf_0 = ((ms_hcount & pf_byte_mod) == (3 & pf_byte_mod)) && + (ms_hcount >= 32 + 3) && (ms_hcount < 160 + 3); else if (dma_pf_width == (ir[4] ? 1 : 2)) - load_pf = ((ms_hcount & pf_byte_mod) == (3 & pf_byte_mod)) && - (ms_hcount >= 19) && (ms_hcount < 179); + load_pf_0 = ((ms_hcount & pf_byte_mod) == (3 & pf_byte_mod)) && + (ms_hcount >= 16 + 3) && (ms_hcount < 176 + 3); else if (dma_pf_width == 3 || (ir[4] && dma_pf_width == 2)) - load_pf = ((ms_hcount & pf_byte_mod) == (3 & pf_byte_mod)) && - (ms_hcount >= 3) && (ms_hcount < 195); + load_pf_0 = ((ms_hcount & pf_byte_mod) == (3 & pf_byte_mod)) && + (ms_hcount >= 3) && (ms_hcount < 192 + 3); end end always @ (dma_block or dma_pf_width or ms_hcount or pf_byte_mod) begin + load_char_0 = 0; + if (dma_block) + case (dma_pf_width) + 1: load_char_0 = ((ms_hcount & pf_byte_mod) == (9 & pf_byte_mod)) && + (ms_hcount >= 32 + 9 && ms_hcount < 160 + 9); + 2: load_char_0 = ((ms_hcount & pf_byte_mod) == (9 & pf_byte_mod)) && + (ms_hcount >= 16 + 9 && ms_hcount < 176 + 9); + 3: load_char_0 = ((ms_hcount & pf_byte_mod) == (9 & pf_byte_mod)) && + (ms_hcount >= 9 && ms_hcount < 192 + 9); + endcase + end + + always @ (dma_block or dma_pf_width or ms_hcount or pf_byte_mod) begin load_out = 0; if (dma_block) case (dma_pf_width) - 1: load_out = ((ms_hcount & pf_byte_mod) == (9 & pf_byte_mod)) && - (ms_hcount >= 41 && ms_hcount < 169); - 2: load_out = ((ms_hcount & pf_byte_mod) == (9 & pf_byte_mod)) && - (ms_hcount >= 25 && ms_hcount < 185); - 3: load_out = ((ms_hcount & pf_byte_mod) == (9 & pf_byte_mod)) && - (ms_hcount >= 9 && ms_hcount < 201); + 1: load_out = ((ms_hcount & pf_byte_mod) == (12 & pf_byte_mod)) && + (ms_hcount >= 32 + 12 && ms_hcount < 160 + 12); + 2: load_out = ((ms_hcount & pf_byte_mod) == (12 & pf_byte_mod)) && + (ms_hcount >= 16 + 12 && ms_hcount < 176 + 12); + 3: load_out = ((ms_hcount & pf_byte_mod) == (12 & pf_byte_mod)) && + (ms_hcount >= 12 && ms_hcount < 192 + 12); endcase end + + always @ (posedge clk_i) begin + load_pf <= load_pf_0; + load_char <= load_char_0 && char_block; + end endmodule module antic_shift_reg(clk_i, shift, load, in, out); @@ -260,16 +282,16 @@ module antic(rst_i, clk_i, wire [1:0] dma_ply_num; - wire load_out; + wire load_out_p, load_out; wire hblank, vblank, vsync; reg dwin; wire shift_reg_shift; wire [7:0] shift_reg_out; - reg [7:0] out_reg; + reg [7:0] char_data, out_reg; wire out_reg_shift; - reg [1:0] char_color; + reg [1:0] char_color_p, char_color; assign ack_o = stb_i; @@ -539,13 +561,16 @@ module antic(rst_i, clk_i, else ms_hcount <= ms_hcount + 1; - antic_ms_hcount_seq u_ms_hcount_seq(.ms_hcount(ms_hcount), + antic_ms_hcount_seq u_ms_hcount_seq(.clk_i(clk_i), + .ms_hcount(ms_hcount), .new_block(new_block), .dma_block(dma_block), + .char_block(char_block), .dma_pf_width(dma_pf_width), .ir(ir), .shift_reg_shift(shift_reg_shift), .load_pf(load_pf), + .load_char(load_char), .load_out(load_out), .out_reg_shift(out_reg_shift)); @@ -567,15 +592,18 @@ module antic(rst_i, clk_i, // TODO: lines here are approximate. assign vsync = (vcount >= 300 && vcount < 303); - assign load_char = load_out && char_block; + always @ (posedge clk_i) + if (load_char) begin + // TODO: change name out_reg_p na char_data + char_data <= masterdat_i; + char_color_p <= shift_reg_out[7:6]; + end always @ (posedge clk2_i) - if (load_out) - if (char_block) begin - out_reg <= masterdat_i; - char_color <= shift_reg_out[7:6]; - end else - out_reg <= shift_reg_out; + if (load_out) begin + out_reg <= char_block ? char_data : shift_reg_out; + char_color <= char_color_p; + end else if (out_reg_shift) if (one_bit_pixel) out_reg <= {out_reg[6:0], 1'b0}; -- 2.11.4.GIT