From 67c29014b708890bf756ad071f4ff872c936505c Mon Sep 17 00:00:00 2001
From: Ondrej Spinka <spinkao@fel.cvut.cz>
Date: Mon, 30 Mar 2009 11:26:14 +0200
Subject: [PATCH] Now using pll library to set the pll instead of "hard"
 setting

---
 app/rama_dam/Makefile.omk |  2 +-
 app/rama_dam/rama_dam.c   | 15 +++++++++------
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/app/rama_dam/Makefile.omk b/app/rama_dam/Makefile.omk
index 983b861..6a18f11 100644
--- a/app/rama_dam/Makefile.omk
+++ b/app/rama_dam/Makefile.omk
@@ -5,7 +5,7 @@ ifeq ($(BOARD),spejblarm)
 
 bin_PROGRAMS = rama_dam
 rama_dam_SOURCES = rama_dam.c
-rama_dam_LIBS = can uart_zen pwm
+rama_dam_LIBS = pll can uart_zen pwm
 link_VARIANTS = mpflash
 
 endif
diff --git a/app/rama_dam/rama_dam.c b/app/rama_dam/rama_dam.c
index de291a2..02fb5d0 100644
--- a/app/rama_dam/rama_dam.c
+++ b/app/rama_dam/rama_dam.c
@@ -14,6 +14,7 @@
 #include <types.h>
 #include <lpc21xx.h>
 #include <string.h>
+#include <pll.h>
 #include <periph/can.h>
 #include <periph/uart_zen.h>
 #include <pwm.h>
@@ -31,10 +32,15 @@
 #define SUB_VERSION 6
 /*! @} */
 
-/*!\def PCLK
-* Peripheral clock frequency in Hz.
+/*! @defgroup CLK Clock settings
+* @ingroup defines
+* These constants define the crystal frequency, core clock and peripheral clock.
+* @{
 */
+#define OSC_FREQ 10000000
+#define CCLK 60000000
 #define PCLK 60000000
+/*! @} */
 
 /*!\def TRUE
 * Formal definition of logical "TRUE" value.
@@ -990,10 +996,7 @@ int main ( void ) {
 	
 	can_msg_t reset_msg = {.id = DAM_RESET_ID, .dlc = 2, .data = {MAIN_VERSION, SUB_VERSION}}; // GPS CAN data packet
 	
-	PLLCFG = 0x25;
-	PLLCON = 0x03; // set the core clock to 60MHz
-	PLLFEED = 0xAA;
-	PLLFEED = 0x55;
+	sys_pll_init ( CCLK, OSC_FREQ ); // set the core clock to 60MHz
 	
 	VPBDIV = 0x01; // peripheral clock = CPU clock (60MHz)
 	
-- 
2.11.4.GIT