fpga/clk_divider.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16
  17 module clk_divider(
  18     input clk,
  19     input [7:0] divisor,
  20     output [7:0] div_cnt,
  21     output div_clk
  22 );
  23
  24     reg [7:0] div_cnt_ = 0;
  25     reg div_clk_ = 0;
  26     assign div_cnt = div_cnt_;
  27     assign div_clk = div_clk_;
  28
  29     always @(posedge clk)
  30     begin
  31         if(div_cnt == divisor) begin
  32             div_cnt_ <= 8'd0;
  33             div_clk_ = !div_clk_;
  34         end else
  35             div_cnt_ <= div_cnt_ + 1;
  36     end
  37
  38 endmodule
  39