fpga/fpga_icopyx_hf.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16 //
  17 // The FPGA is responsible for interfacing between the A/D, the coil drivers,
  18 // and the ARM. In the low-frequency modes it passes the data straight
  19 // through, so that the ARM gets raw A/D samples over the SSP. In the high-
  20 // frequency modes, the FPGA might perform some demodulation first, to
  21 // reduce the amount of data that we must send to the ARM.
  22 //-----------------------------------------------------------------------------
  23
  24 module fpga_hf(
  25     input spck,
  26     output miso,
  27     input mosi,
  28     input ncs,
  29     input pck0,
  30     input ck_1356meg,
  31     input ck_1356megb,
  32     output pwr_lo,
  33     output pwr_hi,
  34     output pwr_oe1,
  35     output pwr_oe2,
  36     output pwr_oe3,
  37     output pwr_oe4,
  38     input [7:0] adc_d,
  39     output adc_clk,
  40     output adc_noe,
  41     output ssp_frame,
  42     output ssp_din,
  43     input ssp_dout,
  44     output ssp_clk,
  45     input cross_hi,
  46     input cross_lo,
  47     output debug
  48 );
  49
  50 //-----------------------------------------------------------------------------
  51 // The SPI receiver. This sets up the configuration word, which the rest of
  52 // the logic looks at to determine how to connect the A/D and the coil
  53 // drivers (i.e., which section gets it). Also assign some symbolic names
  54 // to the configuration bits, for use below.
  55 //-----------------------------------------------------------------------------
  56
  57 // Receive 16bits of data from ARM here.
  58 reg [15:0] shift_reg;
  59 always @(posedge spck) if (~ncs) shift_reg <= {shift_reg[14:0], mosi};
  60
  61 reg [8:0] conf_word;
  62 reg trace_enable;
  63
  64 // select module (outputs) based on major mode
  65 wire [2:0] major_mode = conf_word[8:6];
  66 // parameter to be passed to modules
  67 wire [3:0] minor_mode = conf_word[3:0];
  68
  69 // configuring the HF reader
  70 wire [1:0] subcarrier_frequency = conf_word[5:4];
  71
  72 // We switch modes between transmitting to the 13.56 MHz tag and receiving
  73 // from it, which means that we must make sure that we can do so without
  74 // glitching, or else we will glitch the transmitted carrier.
  75 always @(posedge ncs)
  76 begin
  77     // 4 bit command
  78     case (shift_reg[15:12])
  79         `FPGA_CMD_SET_CONFREG:  conf_word <= shift_reg[8:0];
  80         `FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
  81     endcase
  82 end
  83
  84 //-----------------------------------------------------------------------------
  85 // And then we instantiate the modules corresponding to each of the FPGA's
  86 // major modes, and use muxes to connect the outputs of the active mode to
  87 // the output pins.
  88 //-----------------------------------------------------------------------------
  89
  90 //   0 - HF reader
  91 hi_reader hr(
  92     .ck_1356meg (ck_1356megb),
  93     .pwr_lo     (hr_pwr_lo),
  94     .pwr_hi     (hr_pwr_hi),
  95     .pwr_oe1    (hr_pwr_oe1),
  96     .pwr_oe2    (hr_pwr_oe2),
  97     .pwr_oe3    (hr_pwr_oe3),
  98     .pwr_oe4    (hr_pwr_oe4),
  99     .adc_d      (adc_d),
 100     .adc_clk    (hr_adc_clk),
 101     .ssp_frame  (hr_ssp_frame),
 102     .ssp_din    (hr_ssp_din),
 103     .ssp_dout   (ssp_dout),
 104     .ssp_clk    (hr_ssp_clk),
 105     .debug      (hr_debug),
 106     .subcarrier_frequency (subcarrier_frequency),
 107     .minor_mode (minor_mode)
 108 );
 109
 110 //   1 - HF simulated tag
 111 hi_simulate hs(
 112     .ck_1356meg (ck_1356meg),
 113     .pwr_lo     (hs_pwr_lo),
 114     .pwr_hi     (hs_pwr_hi),
 115     .pwr_oe1    (hs_pwr_oe1),
 116     .pwr_oe2    (hs_pwr_oe2),
 117     .pwr_oe3    (hs_pwr_oe3),
 118     .pwr_oe4    (hs_pwr_oe4),
 119     .adc_d      (adc_d),
 120     .adc_clk    (hs_adc_clk),
 121     .ssp_frame  (hs_ssp_frame),
 122     .ssp_din    (hs_ssp_din),
 123     .ssp_dout   (ssp_dout),
 124     .ssp_clk    (hs_ssp_clk),
 125     .debug      (hs_debug),
 126     .mod_type   (minor_mode)
 127 );
 128
 129 //   2 - HF ISO14443-A
 130
 131 `define EDGE_DETECT_THRESHOLD   3
 132 `define EDGE_DETECT_THRESHOLDHIGH   20
 133
 134 hi_iso14443a hisn(
 135     .ck_1356meg (ck_1356meg),
 136     .pwr_lo     (hisn_pwr_lo),
 137     .pwr_hi     (hisn_pwr_hi),
 138     .pwr_oe1    (hisn_pwr_oe1),
 139     .pwr_oe2    (hisn_pwr_oe2),
 140     .pwr_oe3    (hisn_pwr_oe3),
 141     .pwr_oe4    (hisn_pwr_oe4),
 142     .adc_d      (adc_d),
 143     .adc_clk    (hisn_adc_clk),
 144     .ssp_frame  (hisn_ssp_frame),
 145     .ssp_din    (hisn_ssp_din),
 146     .ssp_dout   (ssp_dout),
 147     .ssp_clk    (hisn_ssp_clk),
 148     .debug      (hisn_debug),
 149     .mod_type   (minor_mode),
 150     .edge_detect_threshold (`EDGE_DETECT_THRESHOLD),
 151     .edge_detect_threshold_high (`EDGE_DETECT_THRESHOLDHIGH)
 152 );
 153
 154 //   3 - HF sniff
 155 hi_sniffer he(
 156     .ck_1356meg  (ck_1356megb),
 157     .pwr_lo      (he_pwr_lo),
 158     .pwr_hi      (he_pwr_hi),
 159     .pwr_oe1     (he_pwr_oe1),
 160     .pwr_oe2     (he_pwr_oe2),
 161     .pwr_oe3     (he_pwr_oe3),
 162     .pwr_oe4     (he_pwr_oe4),
 163     .adc_d       (adc_d),
 164     .adc_clk     (he_adc_clk),
 165     .ssp_frame   (he_ssp_frame),
 166     .ssp_din     (he_ssp_din),
 167     .ssp_clk     (he_ssp_clk)
 168 );
 169
 170 //   4 - HF ISO18092 FeliCa
 171 hi_flite hfl(
 172     .ck_1356meg  (ck_1356megb),
 173     .pwr_lo      (hfl_pwr_lo),
 174     .pwr_hi      (hfl_pwr_hi),
 175     .pwr_oe1     (hfl_pwr_oe1),
 176     .pwr_oe2     (hfl_pwr_oe2),
 177     .pwr_oe3     (hfl_pwr_oe3),
 178     .pwr_oe4     (hfl_pwr_oe4),
 179     .adc_d       (adc_d),
 180     .adc_clk     (hfl_adc_clk),
 181     .ssp_frame   (hfl_ssp_frame),
 182     .ssp_din     (hfl_ssp_din),
 183     .ssp_dout    (ssp_dout),
 184     .ssp_clk     (hfl_ssp_clk),
 185     .debug       (hfl_debug),
 186     .mod_type    (minor_mode)
 187 );
 188
 189 //   5 - HF get trace
 190 hi_get_trace gt(
 191     .ck_1356megb  (ck_1356megb),
 192     .adc_d        (adc_d),
 193     .trace_enable (trace_enable),
 194     .major_mode   (major_mode),
 195     .ssp_frame    (gt_ssp_frame),
 196     .ssp_din      (gt_ssp_din),
 197     .ssp_clk      (gt_ssp_clk)
 198 );
 199
 200 // Major modes:
 201 //   x0 = HF reader
 202 //   x1 = HF simulated tag
 203 //   x2 = HF ISO14443-A
 204 //   x3 = HF sniff
 205 //   x4 = HF ISO18092 FeliCa
 206 //   x5 = HF get trace
 207 //   x6 = unused
 208 //   x7 = FPGA_MAJOR_MODE_OFF
 209
 210 mux8 mux_ssp_clk   (.sel(major_mode), .y(ssp_clk  ), .x0(hr_ssp_clk   ), .x1(hs_ssp_clk  ), .x2(hisn_ssp_clk  ), .x3(he_ssp_clk  ), .x4(hfl_ssp_clk  ), .x5(gt_ssp_clk  ), .x6(1'b0), .x7(1'b0) );
 211 mux8 mux_ssp_din   (.sel(major_mode), .y(ssp_din  ), .x0(hr_ssp_din   ), .x1(hs_ssp_din  ), .x2(hisn_ssp_din  ), .x3(he_ssp_din  ), .x4(hfl_ssp_din  ), .x5(gt_ssp_din  ), .x6(1'b0), .x7(1'b0) );
 212 mux8 mux_ssp_frame (.sel(major_mode), .y(ssp_frame), .x0(hr_ssp_frame ), .x1(hs_ssp_frame), .x2(hisn_ssp_frame), .x3(he_ssp_frame), .x4(hfl_ssp_frame), .x5(gt_ssp_frame), .x6(1'b0), .x7(1'b0) );
 213 mux8 mux_pwr_oe1   (.sel(major_mode), .y(pwr_oe1  ), .x0(hr_pwr_oe1   ), .x1(hs_pwr_oe1  ), .x2(hisn_pwr_oe1  ), .x3(he_pwr_oe1  ), .x4(hfl_pwr_oe1  ), .x5(1'b0        ), .x6(1'b0), .x7(1'b0) );
 214 mux8 mux_pwr_oe2   (.sel(major_mode), .y(pwr_oe2  ), .x0(hr_pwr_oe2   ), .x1(hs_pwr_oe2  ), .x2(hisn_pwr_oe2  ), .x3(he_pwr_oe2  ), .x4(hfl_pwr_oe2  ), .x5(1'b0        ), .x6(1'b0), .x7(1'b0) );
 215 mux8 mux_pwr_oe3   (.sel(major_mode), .y(pwr_oe3  ), .x0(hr_pwr_oe3   ), .x1(hs_pwr_oe3  ), .x2(hisn_pwr_oe3  ), .x3(he_pwr_oe3  ), .x4(hfl_pwr_oe3  ), .x5(1'b0        ), .x6(1'b0), .x7(1'b0) );
 216 mux8 mux_pwr_oe4   (.sel(major_mode), .y(pwr_oe4  ), .x0(hr_pwr_oe4   ), .x1(hs_pwr_oe4  ), .x2(hisn_pwr_oe4  ), .x3(he_pwr_oe4  ), .x4(hfl_pwr_oe4  ), .x5(1'b0        ), .x6(1'b0), .x7(1'b0) );
 217 mux8 mux_pwr_lo    (.sel(major_mode), .y(pwr_lo   ), .x0(hr_pwr_lo    ), .x1(hs_pwr_lo   ), .x2(hisn_pwr_lo   ), .x3(he_pwr_lo   ), .x4(hfl_pwr_lo   ), .x5(1'b0        ), .x6(1'b0), .x7(1'b0) );
 218 mux8 mux_pwr_hi    (.sel(major_mode), .y(pwr_hi   ), .x0(hr_pwr_hi    ), .x1(hs_pwr_hi   ), .x2(hisn_pwr_hi   ), .x3(he_pwr_hi   ), .x4(hfl_pwr_hi   ), .x5(1'b0        ), .x6(1'b0), .x7(1'b0) );
 219 mux8 mux_adc_clk   (.sel(major_mode), .y(adc_clk  ), .x0(hr_adc_clk   ), .x1(hs_adc_clk  ), .x2(hisn_adc_clk  ), .x3(he_adc_clk  ), .x4(hfl_adc_clk  ), .x5(1'b0        ), .x6(1'b0), .x7(1'b0) );
 220 mux8 mux_dbg       (.sel(major_mode), .y(debug    ), .x0(hr_debug     ), .x1(hs_debug    ), .x2(hisn_debug    ), .x3(he_debug    ), .x4(hfl_debug    ), .x5(1'b0        ), .x6(1'b0), .x7(1'b0) );
 221
 222 // In all modes, let the ADC's outputs be enabled.
 223 assign adc_noe = 1'b0;
 224
 225 endmodule