fpga/lo_simulate.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16 //
  17 // The way that we connect things in low-frequency simulation mode. In this
  18 // case just pass everything through to the ARM, which can bit-bang this
  19 // (because it is so slow).
  20 //
  21 // Jonathan Westhues, April 2006
  22 //-----------------------------------------------------------------------------
  23
  24 module lo_simulate(
  25     input pck0,
  26     input ck_1356meg,
  27     input ck_1356megb,
  28     input [7:0] adc_d,
  29     input [7:0] divisor,
  30     input cross_hi,
  31     input cross_lo,
  32     input ssp_dout,
  33
  34     output ssp_din,
  35     output ssp_frame,
  36     output ssp_clk,
  37     output adc_clk,
  38     output pwr_lo,
  39     output pwr_hi,
  40     output pwr_oe1,
  41     output pwr_oe2,
  42     output pwr_oe3,
  43     output pwr_oe4,
  44     output debug
  45 );
  46
  47 // No logic, straight through.
  48 assign pwr_oe3 = 1'b0;
  49 assign pwr_oe1 = ssp_dout;
  50 assign pwr_oe2 = ssp_dout;
  51 assign pwr_oe4 = ssp_dout;
  52 assign ssp_clk = cross_lo;
  53 assign pwr_lo  = 1'b0;
  54 assign pwr_hi  = 1'b0;
  55 assign debug   = ssp_frame;
  56
  57 // Divide the clock to be used for the ADC
  58 reg [7:0] pck_divider;
  59 reg clk_state;
  60
  61 always @(posedge pck0)
  62 begin
  63     if(pck_divider == divisor[7:0])
  64         begin
  65             pck_divider <= 8'd0;
  66             clk_state = !clk_state;
  67         end
  68     else
  69     begin
  70         pck_divider <= pck_divider + 1;
  71     end
  72 end
  73
  74 assign adc_clk = ~clk_state;
  75
  76 // Toggle the output with hysteresis
  77 //  Set to high if the ADC value is above 200
  78 //  Set to low if the ADC value is below 64
  79 reg is_high;
  80 reg is_low;
  81 reg output_state;
  82
  83 always @(posedge pck0)
  84 begin
  85     if((pck_divider == 8'd7) && !clk_state) begin
  86         is_high = (adc_d >= 8'd191);
  87         is_low = (adc_d <= 8'd64);
  88     end
  89 end
  90
  91 always @(posedge is_high or posedge is_low)
  92 begin
  93     if(is_high)
  94         output_state <= 1'd1;
  95     else if(is_low)
  96         output_state <= 1'd0;
  97 end
  98
  99 assign ssp_frame = output_state;
 100
 101 endmodule
 102