fpga/tests/testbed_lo_read.v

   1 //-----------------------------------------------------------------------------
   2 // Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
   3 //
   4 // This program is free software: you can redistribute it and/or modify
   5 // it under the terms of the GNU General Public License as published by
   6 // the Free Software Foundation, either version 3 of the License, or
   7 // (at your option) any later version.
   8 //
   9 // This program is distributed in the hope that it will be useful,
  10 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 // GNU General Public License for more details.
  13 //
  14 // See LICENSE.txt for the text of the license.
  15 //-----------------------------------------------------------------------------
  16
  17 `include "lo_read.v"
  18 /*
  19     pck0            - input main 24MHz clock (PLL / 4)
  20     [7:0] adc_d     - input data from A/D converter
  21     lo_is_125khz    - input freq selector (1=125kHz, 0=136kHz)
  22
  23     pwr_lo          - output to coil drivers (ssp_clk / 8)
  24     adc_clk         - output A/D clock signal
  25     ssp_frame       - output SSS frame indicator (goes high while the 8 bits are shifted)
  26     ssp_din         - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
  27     ssp_clk         - output SSP clock signal 1MHz/1.09MHz (pck0 / 2*(11+lo_is_125khz) )
  28
  29     ck_1356meg      - input unused
  30     ck_1356megb     - input unused
  31     ssp_dout        - input unused
  32     cross_hi        - input unused
  33     cross_lo        - input unused
  34
  35     pwr_hi          - output unused, tied low
  36     pwr_oe1         - output unused, undefined
  37     pwr_oe2         - output unused, undefined
  38     pwr_oe3         - output unused, undefined
  39     pwr_oe4         - output unused, undefined
  40     dbg             - output alias for adc_clk
  41 */
  42
  43 module testbed_lo_read;
  44     reg  pck0;
  45     reg  [7:0] adc_d;
  46     reg  lo_is_125khz;
  47     reg [15:0] divisor;
  48
  49     wire pwr_lo;
  50     wire adc_clk;
  51     wire ck_1356meg;
  52     wire ck_1356megb;
  53     wire ssp_frame;
  54     wire ssp_din;
  55     wire ssp_clk;
  56     reg ssp_dout;
  57     wire pwr_hi;
  58     wire pwr_oe1;
  59     wire pwr_oe2;
  60     wire pwr_oe3;
  61     wire pwr_oe4;
  62     wire cross_lo;
  63     wire cross_hi;
  64     wire dbg;
  65
  66     lo_read #(5,10) dut(
  67     .pck0(pck0),
  68     .ck_1356meg(ck_1356meg),
  69     .ck_1356megb(ck_1356megb),
  70     .pwr_lo(pwr_lo),
  71     .pwr_hi(pwr_hi),
  72     .pwr_oe1(pwr_oe1),
  73     .pwr_oe2(pwr_oe2),
  74     .pwr_oe3(pwr_oe3),
  75     .pwr_oe4(pwr_oe4),
  76     .adc_d(adc_d),
  77     .adc_clk(adc_clk),
  78     .ssp_frame(ssp_frame),
  79     .ssp_din(ssp_din),
  80     .ssp_dout(ssp_dout),
  81     .ssp_clk(ssp_clk),
  82     .cross_hi(cross_hi),
  83     .cross_lo(cross_lo),
  84     .dbg(dbg),
  85     .lo_is_125khz(lo_is_125khz),
  86     .divisor(divisor)
  87     );
  88
  89     integer idx, i, adc_val=8;
  90
  91     // main clock
  92     always #5 pck0 = !pck0;
  93
  94     task crank_dut;
  95     begin
  96         @(posedge adc_clk) ;
  97         adc_d = adc_val;
  98         adc_val = (adc_val *2) + 53;
  99     end
 100     endtask
 101
 102     initial begin
 103
 104         // init inputs
 105         pck0 = 0;
 106         adc_d = 0;
 107         ssp_dout = 0;
 108         lo_is_125khz = 1;
 109         divisor = 255;  //min 16, 95=125kHz, max 255
 110
 111         // simulate 4 A/D cycles at 125kHz
 112         for (i = 0 ;  i < 8 ;  i = i + 1) begin
 113             crank_dut;
 114         end
 115         $finish;
 116     end
 117 endmodule // main