| blob | 02c2e3803cb1b73fd3dd64a14433f73c8b983a32 |
1 /*
2 * Copyright (C) 2024 Mikulas Patocka
3 *
4 * This file is part of Ajla.
5 *
6 * Ajla is free software: you can redistribute it and/or modify it under the
7 * terms of the GNU General Public License as published by the Free Software
8 * Foundation, either version 3 of the License, or (at your option) any later
9 * version.
10 *
11 * Ajla is distributed in the hope that it will be useful, but WITHOUT ANY
12 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * Ajla. If not, see <https://www.gnu.org/licenses/>.
17 */
19 typedef uint64_t it;
21 #define USE_BRCL Z
23 #define S390_BCR 0x070000000000ULL
24 #define S390_BASR 0x0d0000000000ULL
26 #define S390_LTR 0x120000000000ULL
27 #define S390_LTGR 0xb90200000000ULL
29 #define S390_LCR 0x130000000000ULL
30 #define S390_LCGR 0xb90300000000ULL
32 #define S390_NR 0x140000000000ULL
33 #define S390_NRK 0xb9f400000000ULL
34 #define S390_N 0x540000000000ULL
35 #define S390_NY 0xe30000000054ULL
36 #define S390_NGR 0xb98000000000ULL
37 #define S390_NGRK 0xb9e400000000ULL
38 #define S390_NG 0xe30000000080ULL
39 #define S390_NILL 0xa50700000000ULL
40 #define S390_NILH 0xa50600000000ULL
41 #define S390_NIHL 0xa50500000000ULL
42 #define S390_NIHH 0xa50400000000ULL
43 #define S390_NILF 0xc00b00000000ULL
44 #define S390_NIHF 0xc00a00000000ULL
46 #define S390_CLR 0x150000000000ULL
47 #define S390_CL 0x550000000000ULL
48 #define S390_CLY 0xe30000000055ULL
49 #define S390_CLGR 0xb92100000000ULL
50 #define S390_CLG 0xe30000000021ULL
52 #define S390_OR 0x160000000000ULL
53 #define S390_ORK 0xb9f600000000ULL
54 #define S390_O 0x560000000000ULL
55 #define S390_OY 0xe30000000056ULL
56 #define S390_OGR 0xb98100000000ULL
57 #define S390_OGRK 0xb9e600000000ULL
58 #define S390_OG 0xe30000000081ULL
59 #define S390_OILL 0xa50b00000000ULL
60 #define S390_OILH 0xa50a00000000ULL
61 #define S390_OIHL 0xa50900000000ULL
62 #define S390_OIHH 0xa50800000000ULL
63 #define S390_OILF 0xc00d00000000ULL
64 #define S390_OIHF 0xc00c00000000ULL
66 #define S390_XR 0x170000000000ULL
67 #define S390_XRK 0xb9f700000000ULL
68 #define S390_X 0x570000000000ULL
69 #define S390_XY 0xe30000000057ULL
70 #define S390_XGR 0xb98200000000ULL
71 #define S390_XGRK 0xb9e700000000ULL
72 #define S390_XG 0xe30000000082ULL
73 #define S390_XILF 0xc00700000000ULL
74 #define S390_XIHF 0xc00600000000ULL
76 #define S390_LR 0x180000000000ULL
77 #define S390_L 0x580000000000ULL
78 #define S390_LY 0xe30000000058ULL
79 #define S390_LGR 0xb90400000000ULL
80 #define S390_LG 0xe30000000004ULL
81 #define S390_LHI 0xa70800000000ULL
82 #define S390_LGHI 0xa70900000000ULL
83 #define S390_LGFI 0xc00100000000ULL
84 #define S390_LGFR 0xb91400000000ULL
85 #define S390_LLGCR 0xb98400000000ULL
86 #define S390_LLGC 0xe30000000090ULL
87 #define S390_LLGHR 0xb98500000000ULL
88 #define S390_LLGH 0xe30000000091ULL
89 #define S390_LLGFR 0xb91600000000ULL
90 #define S390_LBR 0xb92600000000ULL
91 #define S390_LB 0xe30000000076ULL
92 #define S390_LGBR 0xb90600000000ULL
93 #define S390_LGB 0xe30000000077ULL
95 #define S390_CR 0x190000000000ULL
96 #define S390_C 0x590000000000ULL
97 #define S390_CY 0xe30000000059ULL
98 #define S390_CGR 0xb92000000000ULL
99 #define S390_CG 0xe30000000020ULL
100 #define S390_CHI 0xa70e00000000ULL
101 #define S390_CGHI 0xa70f00000000ULL
103 #define S390_AR 0x1a0000000000ULL
104 #define S390_ARK 0xb9f800000000ULL
105 #define S390_A 0x5a0000000000ULL
106 #define S390_AY 0xe3000000005aULL
107 #define S390_AGR 0xb90800000000ULL
108 #define S390_AGRK 0xb9e800000000ULL
109 #define S390_AG 0xe30000000008ULL
110 #define S390_AHI 0xa70a00000000ULL
111 #define S390_AGHI 0xa70b00000000ULL
112 #define S390_AGF 0xe30000000018ULL
114 #define S390_SR 0x1b0000000000ULL
115 #define S390_SRK 0xb9f900000000ULL
116 #define S390_S 0x5b0000000000ULL
117 #define S390_SY 0xe3000000005bULL
118 #define S390_SGR 0xb90900000000ULL
119 #define S390_SGRK 0xb9e900000000ULL
120 #define S390_SG 0xe30000000009ULL
122 #define S390_MR 0x1c0000000000ULL
123 #define S390_M 0x5c0000000000ULL
124 #define S390_MFY 0xe3000000005cULL
125 #define S390_MGRK 0xb9ec00000000ULL
126 #define S390_MG 0xe30000000084ULL
127 #define S390_MSR 0xb25200000000ULL
128 #define S390_MS 0x710000000000ULL
129 #define S390_MSY 0xe30000000051ULL
130 #define S390_MSRKC 0xb9fd00000000ULL
131 #define S390_MSC 0xe30000000053ULL
132 #define S390_MSGR 0xb90c00000000ULL
133 #define S390_MSGRKC 0xb9ed00000000ULL
134 #define S390_MSG 0xe3000000000cULL
135 #define S390_MSGC 0xe30000000083ULL
137 #define S390_DR 0x1d0000000000ULL
138 #define S390_DLR 0xb99700000000ULL
139 #define S390_DLGR 0xb98700000000ULL
140 #define S390_DSGR 0xb90d00000000ULL
142 #define S390_ALR 0x1e0000000000ULL
143 #define S390_ALRK 0xb9fa00000000ULL
144 #define S390_AL 0x5e0000000000ULL
145 #define S390_ALY 0xe3000000005eULL
146 #define S390_ALGR 0xb90a00000000ULL
147 #define S390_ALGRK 0xb9ea00000000ULL
148 #define S390_ALG 0xe3000000000aULL
150 #define S390_SLR 0x1f0000000000ULL
151 #define S390_SLRK 0xb9fb00000000ULL
152 #define S390_SL 0x5f0000000000ULL
153 #define S390_SLY 0xe3000000005fULL
154 #define S390_SLGR 0xb90b00000000ULL
155 #define S390_SLGRK 0xb9eb00000000ULL
156 #define S390_SLG 0xe3000000000bULL
158 #define S390_LER 0x380000000000ULL
159 #define S390_LDR 0x280000000000ULL
160 #define S390_LXR 0xb36500000000ULL
161 #define S390_LE 0x780000000000ULL
162 #define S390_LEY 0xed0000000064ULL
163 #define S390_LD 0x680000000000ULL
164 #define S390_LDY 0xed0000000065ULL
166 #define S390_STE 0x700000000000ULL
167 #define S390_STEY 0xed0000000066ULL
168 #define S390_STD 0x600000000000ULL
169 #define S390_STDY 0xed0000000067ULL
171 #define S390_LA 0x410000000000ULL
172 #define S390_LAY 0xe30000000071ULL
174 #define S390_STC 0x420000000000ULL
175 #define S390_STCY 0xe30000000072ULL
176 #define S390_STH 0x400000000000ULL
177 #define S390_STHY 0xe30000000070ULL
178 #define S390_ST 0x500000000000ULL
179 #define S390_STY 0xe30000000050ULL
180 #define S390_STG 0xe30000000024ULL
182 #define S390_IC 0x430000000000ULL
183 #define S390_ICY 0xe30000000073ULL
185 #define S390_LCEBR 0xb30300000000ULL
186 #define S390_LCDBR 0xb31300000000ULL
187 #define S390_LCXBR 0xb34300000000ULL
189 #define S390_CEBR 0xb30900000000ULL
190 #define S390_CDBR 0xb31900000000ULL
191 #define S390_CXBR 0xb34900000000ULL
192 #define S390_CEB 0xed0000000009ULL
193 #define S390_CDB 0xed0000000019ULL
195 #define S390_AEBR 0xb30a00000000ULL
196 #define S390_ADBR 0xb31a00000000ULL
197 #define S390_AXBR 0xb34a00000000ULL
198 #define S390_AEB 0xed000000000aULL
199 #define S390_ADB 0xed000000001aULL
201 #define S390_SEBR 0xb30b00000000ULL
202 #define S390_SDBR 0xb31b00000000ULL
203 #define S390_SXBR 0xb34b00000000ULL
204 #define S390_SEB 0xed000000000bULL
205 #define S390_SDB 0xed000000001bULL
207 #define S390_DEBR 0xb30d00000000ULL
208 #define S390_DDBR 0xb31d00000000ULL
209 #define S390_DXBR 0xb34d00000000ULL
210 #define S390_DEB 0xed000000000dULL
211 #define S390_DDB 0xed000000001dULL
213 #define S390_SQEBR 0xb31400000000ULL
214 #define S390_SQDBR 0xb31500000000ULL
215 #define S390_SQXBR 0xb31600000000ULL
216 #define S390_SQEB 0xed0000000014ULL
217 #define S390_SQDB 0xed0000000015ULL
219 #define S390_MEEBR 0xb31700000000ULL
220 #define S390_MDBR 0xb31c00000000ULL
221 #define S390_MXBR 0xb34c00000000ULL
222 #define S390_MEEB 0xed0000000017ULL
223 #define S390_MDB 0xed000000001cULL
225 #define S390_FIEBR 0xb35700000000ULL
226 #define S390_FIDBR 0xb35f00000000ULL
227 #define S390_FIXBR 0xb34700000000ULL
228 #define S390_FI_ROUND 0x000040000000ULL
229 #define S390_FI_TRUNC 0x000050000000ULL
230 #define S390_FI_CEIL 0x000060000000ULL
231 #define S390_FI_FLOOR 0x000070000000ULL
233 #define S390_CEFBR 0xb39400000000ULL
234 #define S390_CDFBR 0xb39500000000ULL
235 #define S390_CXFBR 0xb39600000000ULL
236 #define S390_CEGBR 0xb3a400000000ULL
237 #define S390_CDGBR 0xb3a500000000ULL
238 #define S390_CXGBR 0xb3a600000000ULL
240 #define S390_CFEBR 0xb39800000000ULL
241 #define S390_CFDBR 0xb39900000000ULL
242 #define S390_CFXBR 0xb39a00000000ULL
243 #define S390_CGEBR 0xb3a800000000ULL
244 #define S390_CGDBR 0xb3a900000000ULL
245 #define S390_CGXBR 0xb3aa00000000ULL
247 #define S390_LHR 0xb92700000000ULL
248 #define S390_LH 0x480000000000ULL
249 #define S390_LHY 0xe30000000078ULL
250 #define S390_LGHR 0xb90700000000ULL
251 #define S390_LGH 0xe30000000015ULL
252 #define S390_LGF 0xe30000000014ULL
253 #define S390_LLGF 0xe30000000016ULL
255 #define S390_RLL 0xeb000000001dULL
256 #define S390_RLLG 0xeb000000001cULL
257 #define S390_SRL 0x880000000000ULL
258 #define S390_SRLK 0xeb00000000deULL
259 #define S390_SRLG 0xeb000000000cULL
260 #define S390_SLL 0x890000000000ULL
261 #define S390_SLLK 0xeb00000000dfULL
262 #define S390_SLLG 0xeb000000000dULL
263 #define S390_SRA 0x8a0000000000ULL
264 #define S390_SRAK 0xeb00000000dcULL
265 #define S390_SRAG 0xeb000000000aULL
266 #define S390_SLA 0x8b0000000000ULL
267 #define S390_SLAK 0xeb00000000ddULL
268 #define S390_SLAG 0xeb000000000bULL
270 #define S390_STM 0x900000000000ULL
271 #define S390_STMY 0xeb0000000090ULL
272 #define S390_STMG 0xeb0000000024ULL
273 #define S390_LM 0x980000000000ULL
274 #define S390_LMY 0xeb0000000098ULL
275 #define S390_LMG 0xeb0000000004ULL
277 #define S390_MVI 0x920000000000ULL
278 #define S390_MVIY 0xeb0000000052ULL
279 #define S390_CLI 0x950000000000ULL
280 #define S390_CLIY 0xeb0000000055ULL
282 #define S390_TMLL 0xa70100000000ULL
283 #define S390_TMLH 0xa70000000000ULL
284 #define S390_TMHL 0xa70300000000ULL
285 #define S390_TMHH 0xa70200000000ULL
287 #define S390_BRC 0xa70400000000ULL
288 #define S390_BRAS 0xa70500000000ULL
289 #define S390_LRVR 0xb91f00000000ULL
290 #define S390_LRVRG 0xb90f00000000ULL
291 #define S390_POPCNT 0xb9e180000000ULL
292 #define S390_LOCR 0xb9f200000000ULL
293 #define S390_LOCGR 0xb9e200000000ULL
294 #define S390_NCRK 0xb9f500000000ULL
295 #define S390_NCGRK 0xb9e500000000ULL
296 #define S390_LOC 0xeb00000000f2ULL
297 #define S390_LOCG 0xeb00000000e2ULL
298 #define S390_BRCL 0xc00400000000ULL
299 #define S390_BRC_OVF 0x1ULL
300 #define S390_BRC_GREATER 0x2ULL
301 #define S390_BRC_LESS 0x4ULL
302 #define S390_BRC_EQ 0x8ULL
304 #define S390_IIHF 0xc00800000000ULL
305 #define S390_IILF 0xc00900000000ULL
307 #define S390_MVC 0xd20000000000ULL
309 struct codes {
310 it rr;
311 it rrk;
312 it rx;
313 it rxy;
314 it rrg;
315 it rrgk;
316 it rxg;
317 it ri;
318 it rig;
319 it rig32;
320 it rill;
321 it rilh;
322 it rihl;
323 it rihh;
324 it rilf;
325 it rihf;
326 int neg_imm;
327 };
329 static const struct codes codes_cmp = { S390_CR, -1, S390_C, S390_CY, S390_CGR, -1, S390_CG, S390_CHI, S390_CGHI, -1, -1, -1, -1, -1, -1, -1, 0 };
330 static const struct codes codes_cmp_log = { S390_CLR, -1, S390_CL, S390_CLY, S390_CLGR, -1, S390_CLG, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
331 static const struct codes codes_ic = { -1, -1, S390_IC, S390_ICY, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
332 static const struct codes codes_load_8 = { S390_LBR, -1, -1, S390_LB, S390_LGBR, -1, S390_LGB, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
333 static const struct codes codes_load_16 = { -1, -1, S390_LH, S390_LHY, S390_LGHR, -1, S390_LGH, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
334 static const struct codes codes_load_32 = { -1, -1, -1, -1, S390_LGFR, -1, S390_LGF, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
335 static const struct codes codes_load_8_unsigned = { -1, -1, -1, -1, S390_LLGCR, -1, S390_LLGC, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
336 static const struct codes codes_load_16_unsigned = { -1, -1, -1, -1, S390_LLGHR, -1, S390_LLGH, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
337 static const struct codes codes_load_32_unsigned = { -1, -1, -1, -1, S390_LLGFR, -1, S390_LLGF, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
338 static const struct codes codes_load = { S390_LR, -1, S390_L, S390_LY, S390_LGR, -1, S390_LG, S390_LHI, S390_LGHI, S390_LGFI, -1, -1, -1, -1, -1, -1, 0 };
339 static const struct codes codes_store_8 = { -1, -1, S390_STC, S390_STCY, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
340 static const struct codes codes_store_16 = { -1, -1, S390_STH, S390_STHY, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
341 static const struct codes codes_store = { -1, -1, S390_ST, S390_STY, -1, -1, S390_STG, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 };
343 static const struct codes codes_alu_no_flags[] = {
344 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
345 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
346 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
347 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
348 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
349 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
350 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
351 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
352 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
353 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
354 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
355 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
356 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
357 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
358 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
359 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
360 { S390_MSR, -1, S390_MS, S390_MSY, S390_MSGR, -1, S390_MSG, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
361 };
363 static const struct codes codes_alu[] = {
364 { S390_AR, S390_ARK, S390_A, S390_AY, S390_AGR, S390_AGRK, S390_AG, S390_AHI, S390_AGHI, -1, -1, -1, -1, -1, -1, -1, 0 },
365 { S390_OR, S390_ORK, S390_O, S390_OY, S390_OGR, S390_OGRK, S390_OG, -1, -1, -1, S390_OILL, S390_OILH, S390_OIHL, S390_OIHH, S390_OILF, S390_OIHF, 0 },
366 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
367 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
368 { S390_NR, S390_NRK, S390_N, S390_NY, S390_NGR, S390_NGRK, S390_NG, -1, -1, -1, S390_NILL, S390_NILH, S390_NIHL, S390_NIHH, S390_NILF, S390_NIHF, 2 },
369 { S390_SR, S390_SRK, S390_S, S390_SY, S390_SGR, S390_SGRK, S390_SG, S390_AHI, S390_AGHI, -1, -1, -1, -1, -1, -1, -1, 1 },
370 { S390_XR, S390_XRK, S390_X, S390_XY, S390_XGR, S390_XGRK, S390_XG, -1, -1, -1, -1, -1, -1, -1, S390_XILF, S390_XIHF, 0 },
371 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
372 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
373 { -1, S390_NCRK, -1, -1, -1, S390_NCGRK, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
374 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
375 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
376 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
377 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
378 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
379 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
380 { -1, S390_MSRKC, -1, S390_MSC, -1, S390_MSGRKC, S390_MSGC, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
381 };
383 static const struct codes codes_alu_log[] = {
384 { S390_ALR, S390_ALRK, S390_AL, S390_ALY, S390_ALGR, S390_ALGRK, S390_ALG, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
385 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
386 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
387 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
388 { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
389 { S390_SLR, S390_SLRK, S390_SL, S390_SLY, S390_SLGR, S390_SLGRK, S390_SLG, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0 },
390 };
392 static const it rot32[9] = {
393 S390_RLL, -1, -1, -1,
394 S390_SLL, S390_SRL, -1, S390_SRA,
395 S390_SLA,
396 };
398 static const it rot32k[9] = {
399 S390_RLL, -1, -1, -1,
400 S390_SLLK, S390_SRLK, -1, S390_SRAK,
401 S390_SLAK,
402 };
404 static const it rot64[9] = {
405 S390_RLLG, -1, -1, -1,
406 S390_SLLG, S390_SRLG, -1, S390_SRAG,
407 S390_SLAG,
408 };
410 static const int8_t jmp_cond[0x30] = {
411 S390_BRC_OVF, S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_EQ,
412 -1, -1,
413 S390_BRC_EQ, S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_OVF,
414 -1, -1,
415 -1, -1,
416 -1, -1,
417 S390_BRC_LESS, S390_BRC_GREATER | S390_BRC_EQ,
418 S390_BRC_LESS | S390_BRC_EQ, S390_BRC_GREATER,
420 -1, -1,
421 S390_BRC_OVF | S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_EQ, -1,
422 -1, -1,
423 -1, -1,
424 -1, -1,
425 -1, -1,
426 -1, -1,
427 -1, -1,
429 -1, -1,
430 S390_BRC_LESS, S390_BRC_GREATER | S390_BRC_EQ,
431 S390_BRC_EQ, S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_OVF,
432 S390_BRC_LESS | S390_BRC_EQ, S390_BRC_GREATER,
433 -1, -1,
434 S390_BRC_OVF, S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_EQ,
435 -1, -1,
436 -1, -1,
437 };
439 static const int8_t jmp_cond_logical[0x8] = {
440 -1, -1,
441 S390_BRC_LESS, S390_BRC_GREATER | S390_BRC_EQ,
442 S390_BRC_EQ, S390_BRC_GREATER | S390_BRC_LESS,
443 S390_BRC_LESS | S390_BRC_EQ, S390_BRC_GREATER,
444 };
446 struct fp_alu {
447 it err;
448 it drr;
449 it xrr;
450 it erx;
451 it drx;
452 };
454 static const struct fp_alu fp_alus[4] = {
455 { S390_AEBR, S390_ADBR, S390_AXBR, S390_AEB, S390_ADB },
456 { S390_SEBR, S390_SDBR, S390_SXBR, S390_SEB, S390_SDB },
457 { S390_MEEBR, S390_MDBR, S390_MXBR, S390_MEEB, S390_MDB },
458 { S390_DEBR, S390_DDBR, S390_DXBR, S390_DEB, S390_DDB },
459 };
461 static const struct fp_alu fp_alu1s[6] = {
462 { S390_LCEBR, S390_LCDBR, S390_LCXBR, -1, -1 },
463 { S390_SQEBR, S390_SQDBR, S390_SQXBR, S390_SQEB, S390_SQDB },
464 { S390_FIEBR | S390_FI_ROUND, S390_FIDBR | S390_FI_ROUND, S390_FIXBR | S390_FI_ROUND, -1, -1 },
465 { S390_FIEBR | S390_FI_FLOOR, S390_FIDBR | S390_FI_FLOOR, S390_FIXBR | S390_FI_FLOOR, -1, -1 },
466 { S390_FIEBR | S390_FI_CEIL, S390_FIDBR | S390_FI_CEIL, S390_FIXBR | S390_FI_CEIL, -1, -1 },
467 { S390_FIEBR | S390_FI_TRUNC, S390_FIDBR | S390_FI_TRUNC, S390_FIXBR | S390_FI_TRUNC, -1, -1 },
468 };
470 static const struct fp_alu fp_cmp = {
471 S390_CEBR, S390_CDBR, S390_CXBR, S390_CEB, S390_CDB
472 };
474 static uint8_t get_jmp_cond(unsigned cond, bool logical)
475 {
476 int8_t c;
477 if (!logical) {
478 if (unlikely(cond >= n_array_elements(jmp_cond)))
479 goto invl;
480 c = jmp_cond[cond];
481 } else {
482 if (unlikely(cond >= n_array_elements(jmp_cond_logical)))
483 goto invl;
484 c = jmp_cond_logical[cond];
485 }
486 if (unlikely(c == -1))
487 goto invl;
488 return (uint8_t)c;
489 invl:
490 internal(file_line, "get_jmp_cond: invalid %scondition %x", logical ? "logical " : "", cond);
491 }
493 static bool attr_w cgen_s390(struct codegen_context *ctx, it code)
494 {
495 unsigned sz = code >> 46;
496 if (sz == 0) {
497 if (unlikely((uint32_t)code))
498 goto invl;
499 cgen_two(code >> 32);
500 } else if (sz == 1 || sz == 2) {
501 if (unlikely((uint16_t)code))
502 goto invl;
503 cgen_four(code >> 16);
504 } else if (sz == 3) {
505 cgen_two(code >> 32);
506 cgen_four(code);
507 } else {
508 invl:
509 internal(file_line, "cgen_s390: invalid insn %"PRIxMAX"", (uintmax_t)code);
510 }
511 return true;
512 }
514 static bool attr_w cgen_rr_rx(struct codegen_context *ctx, unsigned size, uint8_t *arg1, uint8_t *arg2, uint8_t *arg3, const struct codes *codes)
515 {
516 it code;
517 uint8_t b, x;
518 uint8_t *disp;
519 int64_t imm;
520 if (size > OP_SIZE_NATIVE)
521 goto invl;
522 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10))
523 goto invl;
524 if (arg3[0] < 0x10) {
525 unsigned sz;
526 bool k = false;
527 if (size != OP_SIZE_8) {
528 code = codes->rr;
529 if (code == (it)-1 || arg1[0] != arg2[0]) {
530 code = codes->rrk;
531 k = true;
532 }
533 } else {
534 code = codes->rrg;
535 if (code == (it)-1 || arg1[0] != arg2[0]) {
536 code = codes->rrgk;
537 k = true;
538 }
539 }
540 sz = code >> 46;
541 if (k) {
542 code |= (it)arg1[0] << 20;
543 code |= (it)arg2[0] << 16;
544 code |= (it)arg3[0] << 28;
545 } else if (!sz) {
546 code |= (it)arg1[0] << 36;
547 code |= (it)arg3[0] << 32;
548 } else if (sz == 1 || sz == 2) {
549 code |= (it)arg1[0] << 20;
550 code |= (it)arg3[0] << 16;
551 } else {
552 goto invl;
553 }
554 g(cgen_s390(ctx, code));
555 return true;
556 }
557 if (unlikely(arg1[0] != arg2[0]))
558 goto invl;
559 if (arg3[0] == ARG_IMM) {
560 imm = get_imm(&arg3[1]);
561 if (codes->neg_imm == 1)
562 imm = -(uint64_t)imm;
563 if (imm >= -0x8000 && imm < 0x8000) {
564 code = size != OP_SIZE_8 ? codes->ri : codes->rig;
565 if (unlikely(code == (it)-1))
566 goto log_op;
567 code |= (it)arg1[0] << 36;
568 code |= (it)(imm & 0xffff) << 16;
569 } else if (imm >= -0x80000000LL && imm < 0x80000000LL) {
570 code = codes->rig32;
571 if (unlikely(code == (it)-1))
572 goto log_op;
573 code |= (it)arg1[0] << 36;
574 code |= (it)(imm & 0xffffffffLL);
575 } else {
576 goto log_op;
577 }
578 g(cgen_s390(ctx, code));
579 return true;
580 log_op:
581 if (codes->neg_imm == 2)
582 imm = ~imm;
583 if (!(imm & ~0xffffULL) && codes->rill != (it)-1) {
584 code = codes->rill;
585 if (codes->neg_imm == 2)
586 imm = ~imm;
587 code |= (it)(imm & 0xffffULL) << 16;
588 } else if (!(imm & ~0xffff0000ULL) && codes->rilh != (it)-1) {
589 code = codes->rilh;
590 if (codes->neg_imm == 2)
591 imm = ~imm;
592 code |= (it)(imm & 0xffff0000ULL);
593 } else if (!(imm & ~0xffff00000000ULL) && codes->rihl != (it)-1) {
594 code = codes->rihl;
595 if (codes->neg_imm == 2)
596 imm = ~imm;
597 code |= (it)((uint64_t)imm & 0xffff00000000ULL) >> 16;
598 } else if (!(imm & ~0xffff000000000000ULL) && codes->rihh != (it)-1) {
599 code = codes->rihh;
600 if (codes->neg_imm == 2)
601 imm = ~imm;
602 code |= (it)((uint64_t)imm & 0xffff000000000000ULL) >> 32;
603 } else if (!(imm & ~0xffffffffULL) && codes->rilf != (it)-1) {
604 code = codes->rilf;
605 if (codes->neg_imm == 2)
606 imm = ~imm;
607 code |= (it)(imm & 0xffffffffLL);
608 } else if (!(imm & ~0xffffffff00000000ULL) && codes->rihf != (it)-1) {
609 code = codes->rihf;
610 if (codes->neg_imm == 2)
611 imm = ~imm;
612 code |= (it)(((uint64_t)imm & 0xffffffff00000000LL) >> 32);
613 } else {
614 goto invl;
615 }
616 code |= (it)arg1[0] << 36;
617 g(cgen_s390(ctx, code));
618 return true;
619 } else if (arg3[0] == ARG_ADDRESS_0) {
620 b = 0;
621 x = 0;
622 disp = &arg3[1];
623 } else if (arg3[0] == ARG_ADDRESS_1) {
624 b = arg3[1];
625 x = 0;
626 disp = &arg3[2];
627 } else if (arg3[0] == ARG_ADDRESS_2) {
628 b = arg3[1];
629 x = arg3[2];
630 disp = &arg3[3];
631 } else {
632 goto invl;
633 }
635 imm = get_imm(disp);
636 if (size != OP_SIZE_8) {
637 if (imm >= 0 && imm < 0x1000 && codes->rx != (it)-1) {
638 code = codes->rx;
639 code |= (it)arg1[0] << 36;
640 code |= (it)x << 32;
641 code |= (it)b << 28;
642 code |= (it)(imm & 0xfff) << 16;
643 } else if (imm >= -0x80000 && imm < 0x80000) {
644 code = codes->rxy;
645 goto rxya;
646 } else {
647 goto invl;
648 }
649 } else {
650 code = codes->rxg;
651 if (imm >= -0x80000 && imm < 0x80000) {
652 rxya:
653 code |= (it)arg1[0] << 36;
654 code |= (it)x << 32;
655 code |= (it)b << 28;
656 code |= (it)(imm & 0xfff) << 16;
657 code |= (it)(imm & 0xff000) >> 4;
658 } else {
659 goto invl;
660 }
662 }
663 g(cgen_s390(ctx, code));
664 return true;
665 invl:
666 internal(file_line, "cgen_rr_rx: invalid arguments %u, %02x, %02x, %02x", size, *arg1, *arg2, *arg3);
667 return false;
668 }
670 static bool attr_w cgen_fp_mem(struct codegen_context *ctx, unsigned size, uint8_t *arg1, uint8_t *arg2, it e, it ey, it d, it dy)
671 {
672 it code;
673 uint8_t b, x;
674 uint8_t *disp;
675 int64_t imm;
676 if (size != OP_SIZE_4 && size != OP_SIZE_8)
677 goto invl;
678 if (unlikely(!reg_is_fp(arg1[0])))
679 goto invl;
680 if (arg2[0] == ARG_ADDRESS_0) {
681 b = 0;
682 x = 0;
683 disp = &arg2[1];
684 } else if (arg2[0] == ARG_ADDRESS_1) {
685 b = arg2[1];
686 x = 0;
687 disp = &arg2[2];
688 } else if (arg2[0] == ARG_ADDRESS_2) {
689 b = arg2[1];
690 x = arg2[2];
691 disp = &arg2[3];
692 } else {
693 goto invl;
694 }
695 imm = get_imm(disp);
696 if (imm >= 0 && imm < 4096) {
697 code = size == OP_SIZE_4 ? e : d;
698 } else if (imm >= -0x80000 && imm < 0x80000) {
699 code = size == OP_SIZE_4 ? ey : dy;
700 code |= (it)(imm & 0xff000) >> 4;
701 } else {
702 goto invl;
703 }
704 code |= (it)(arg1[0] & 0xf) << 36;
705 code |= (it)x << 32;
706 code |= (it)b << 28;
707 code |= (it)(imm & 0xfff) << 16;
708 g(cgen_s390(ctx, code));
709 return true;
710 invl:
711 internal(file_line, "cgen_fp_mem: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
712 return false;
713 }
715 static bool attr_w cgen_fp_op(struct codegen_context *ctx, unsigned size, uint8_t *arg1, uint8_t *arg2, const struct fp_alu *fp_alu)
716 {
717 it code;
718 uint8_t b, x;
719 uint8_t *disp;
720 int64_t imm;
721 if (size != OP_SIZE_4 && size != OP_SIZE_8 && size != OP_SIZE_16)
722 goto invl;
723 if (reg_is_fp(arg2[0])) {
724 code = size == OP_SIZE_4 ? fp_alu->err : size == OP_SIZE_8 ? fp_alu->drr : fp_alu->xrr;
725 code |= (it)(arg1[0] & 0xf) << 20;
726 code |= (it)(arg2[0] & 0xf) << 16;
727 g(cgen_s390(ctx, code));
728 return true;
729 } else if (arg2[0] == ARG_ADDRESS_0) {
730 b = 0;
731 x = 0;
732 disp = &arg2[1];
733 } else if (arg2[0] == ARG_ADDRESS_1) {
734 b = arg2[1];
735 x = 0;
736 disp = &arg2[2];
737 } else if (arg2[0] == ARG_ADDRESS_2) {
738 b = arg2[1];
739 x = arg2[2];
740 disp = &arg2[3];
741 } else {
742 goto invl;
743 }
744 imm = get_imm(disp);
745 if (unlikely(imm < 0) || unlikely(imm >= 4096))
746 goto invl;
747 if (unlikely(size == OP_SIZE_16))
748 goto invl;
749 code = size == OP_SIZE_4 ? fp_alu->erx : fp_alu->drx;
750 code |= (it)(arg1[0] & 0xf) << 36;
751 code |= (it)x << 32;
752 code |= (it)b << 28;
753 code |= (it)(imm & 0xfff) << 16;
754 g(cgen_s390(ctx, code));
755 return true;
756 invl:
757 internal(file_line, "cgen_fp_op: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
758 return false;
759 }
761 static bool attr_w cgen_xi(struct codegen_context *ctx, uint8_t *arg1, uint8_t *arg2, it xi, it xiy)
762 {
763 it code;
764 uint8_t b;
765 uint8_t *disp;
766 int64_t val, imm;
767 if (unlikely(arg1[0] == ARG_ADDRESS_0)) {
768 b = 0;
769 disp = &arg1[1];
770 } else if (likely(arg1[0] == ARG_ADDRESS_1) && likely(arg2[0] == ARG_IMM)) {
771 b = arg1[1];
772 disp = &arg1[2];
773 } else {
774 goto invl;
775 }
777 imm = get_imm(disp);
778 if (likely(arg2[0] == ARG_IMM)) {
779 val = get_imm(&arg2[1]);
780 } else {
781 goto invl;
782 }
784 if (imm >= 0 && imm < 0x1000) {
785 code = xi;
786 code |= (it)(imm & 0xfff) << 16;
787 } else if (imm >= -0x80000 && imm < 0x80000) {
788 code = xiy;
789 code |= (it)(imm & 0xfff) << 16;
790 code |= (it)(imm & 0xff000) >> 4;
791 } else {
792 goto invl;
793 }
795 code |= (it)(val & 0xff) << 32;
796 code |= (it)b << 28;
798 g(cgen_s390(ctx, code));
799 return true;
800 invl:
801 internal(file_line, "cgen_xi: invalid arguments %02x, %02x", *arg1, *arg2);
802 return false;
803 }
805 static bool attr_w cgen_lm_stm(struct codegen_context *ctx, unsigned size, uint8_t r_start, uint8_t r_end, uint8_t *arg1, it m, it my, it mg)
806 {
807 it code;
808 int64_t imm;
809 if (unlikely(r_start >= 0x10) || unlikely(r_end >= 0x10) || unlikely(arg1[0] != ARG_ADDRESS_1) || unlikely(size < OP_SIZE_4) || unlikely(size > OP_SIZE_8))
810 goto invl;
811 imm = get_imm(&arg1[2]);
812 if (size == OP_SIZE_4 && imm >= 0 && imm < 0x1000) {
813 code = m;
814 code |= (it)(imm & 0xfff) << 16;
815 } else {
816 if (size == OP_SIZE_4)
817 code = my;
818 else
819 code = mg;
820 code |= (it)(imm & 0xfff) << 16;
821 code |= (it)(imm & 0xff000) >> 4;
822 }
823 code |= (it)r_start << 36;
824 code |= (it)r_end << 32;
825 code |= (it)arg1[1] << 28;
826 g(cgen_s390(ctx, code));
827 return true;
828 invl:
829 internal(file_line, "cgen_lm_stm: invalid arguments %02x", *arg1);
830 return false;
831 }
833 static bool attr_w cgen_s390_push_pop(struct codegen_context *ctx, unsigned size, bool push)
834 {
835 uint8_t *arg1;
836 arg1 = ctx->code_position;
837 ctx->code_position = arg1 + arg_size(*arg1);
838 if (!push)
839 g(cgen_lm_stm(ctx, size, R_6, R_15, arg1, S390_LM, S390_LMY, S390_LMG));
840 else
841 g(cgen_lm_stm(ctx, size, R_6, R_15, arg1, S390_STM, S390_STMY, S390_STMG));
842 return true;
843 }
845 static bool attr_w cgen_call_indirect(struct codegen_context *ctx)
846 {
847 uint8_t reg = cget_one(ctx);
848 it code = S390_BASR;
849 code |= (it)R_14 << 36;
850 code |= (it)reg << 32;
851 g(cgen_s390(ctx, code));
852 return true;
853 }
855 static bool attr_w cgen_branch_imm(struct codegen_context *ctx, uint8_t reg, int64_t imm)
856 {
857 it code;
858 code = S390_BRAS;
859 code |= (it)reg << 36;
860 code |= (OP_SIZE_NATIVE == OP_SIZE_4 ? (it)4 : (it)6) << 16;
861 g(cgen_s390(ctx, code));
862 if (OP_SIZE_NATIVE == OP_SIZE_4) {
863 cgen_four(imm);
864 } else {
865 cgen_eight(imm);
866 }
867 code = OP_SIZE_NATIVE == OP_SIZE_4 ? S390_L : S390_LG;
868 code |= (it)reg << 36;
869 code |= (it)reg << 28;
870 g(cgen_s390(ctx, code));
871 return true;
872 }
874 static bool attr_w cgen_mov(struct codegen_context *ctx, unsigned size)
875 {
876 uint8_t *arg1 = ctx->code_position;
877 uint8_t *arg2 = arg1 + arg_size(*arg1);
878 ctx->code_position = arg2 + arg_size(*arg2);
879 if (arg1[0] < 0x10) {
880 if (unlikely(size != OP_SIZE_NATIVE)) {
881 switch (size) {
882 case OP_SIZE_1:
883 if (unlikely(!cpu_test_feature(CPU_FEATURE_extended_imm)))
884 goto invl;
885 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_8_unsigned));
886 return true;
887 case OP_SIZE_2:
888 if (unlikely(!cpu_test_feature(CPU_FEATURE_extended_imm)))
889 goto invl;
890 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_16_unsigned));
891 return true;
892 case OP_SIZE_4:
893 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_32_unsigned));
894 return true;
895 default:
896 goto invl;
897 }
898 }
899 if (!cpu_test_feature(CPU_FEATURE_extended_imm) && arg2[0] == ARG_IMM) {
900 int64_t imm = get_imm(&arg2[1]);
901 if (imm < -0x8000 || imm >= 0x8000) {
902 g(cgen_branch_imm(ctx, arg1[0], imm));
903 return true;
904 }
905 }
906 g(cgen_rr_rx(ctx, size, arg1, arg1, arg2, &codes_load));
907 return true;
908 }
909 if (arg1[0] < 0x20) {
910 if (unlikely(arg2[0] < 0x20))
911 goto invl;
912 if (unlikely(size < OP_SIZE_4) || unlikely(size > OP_SIZE_8))
913 goto invl;
914 g(cgen_fp_mem(ctx, size, arg1, arg2, S390_LE, S390_LEY, S390_LD, S390_LDY));
915 return true;
916 }
917 if (arg2[0] < 0x10) {
918 g(cgen_rr_rx(ctx, size, arg2, arg2, arg1, size == OP_SIZE_1 ? &codes_store_8 : size == OP_SIZE_2 ? &codes_store_16 : &codes_store));
919 return true;
920 }
921 if (arg2[0] < 0x20) {
922 if (unlikely(size < OP_SIZE_4) || unlikely(size > OP_SIZE_8))
923 goto invl;
924 g(cgen_fp_mem(ctx, size, arg2, arg1, S390_STE, S390_STEY, S390_STD, S390_STDY));
925 return true;
926 }
927 if (size == OP_SIZE_1 && arg1[0] == ARG_ADDRESS_1 && arg2[0] == ARG_IMM) {
928 g(cgen_xi(ctx, arg1, arg2, S390_MVI, S390_MVIY));
929 return true;
930 }
931 invl:
932 internal(file_line, "cgen_mov: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
933 return false;
934 }
936 static bool attr_w cgen_movsx(struct codegen_context *ctx, unsigned size)
937 {
938 uint8_t *arg1, *arg2;
939 if (unlikely(size == OP_SIZE_NATIVE)) {
940 g(cgen_mov(ctx, size));
941 return true;
942 }
943 arg1 = ctx->code_position;
944 arg2 = arg1 + arg_size(*arg1);
945 ctx->code_position = arg2 + arg_size(*arg2);
946 switch (size) {
947 case OP_SIZE_1:
948 if (arg2[0] >= 0x10 ? !cpu_test_feature(CPU_FEATURE_long_displacement) : !cpu_test_feature(CPU_FEATURE_extended_imm))
949 goto invl;
950 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_8));
951 return true;
952 case OP_SIZE_2:
953 if (arg2[0] < 0x10 && !cpu_test_feature(CPU_FEATURE_extended_imm))
954 goto invl;
955 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_16));
956 return true;
957 case OP_SIZE_4:
958 g(cgen_rr_rx(ctx, OP_SIZE_NATIVE, arg1, arg1, arg2, &codes_load_32));
959 return true;
960 default:
961 goto invl;
962 }
963 invl:
964 internal(file_line, "cgen_movsx: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
965 return false;
966 }
968 static bool attr_w cgen_cmp(struct codegen_context *ctx, unsigned size, unsigned writes_flags)
969 {
970 uint8_t *arg1, *arg2;
971 arg1 = ctx->code_position;
972 arg2 = arg1 + arg_size(*arg1);
973 ctx->code_position = arg2 + arg_size(*arg2);
974 if (writes_flags == 1) {
975 g(cgen_rr_rx(ctx, size, arg1, arg1, arg2, &codes_cmp));
976 return true;
977 } else if (writes_flags == 2) {
978 if (size == OP_SIZE_1 && arg1[0] == ARG_ADDRESS_1 && arg2[0] == ARG_IMM) {
979 g(cgen_xi(ctx, arg1, arg2, S390_CLI, S390_CLIY));
980 return true;
981 }
982 g(cgen_rr_rx(ctx, size, arg1, arg1, arg2, &codes_cmp_log));
983 return true;
984 }
985 internal(file_line, "cgen_cmp: invalid arguments %u, %02x, %02x, %u", size, *arg1, *arg2, writes_flags);
986 return false;
987 }
989 static bool attr_w cgen_test(struct codegen_context *ctx, unsigned size)
990 {
991 it code;
992 uint8_t *arg1, *arg2;
993 arg1 = ctx->code_position;
994 arg2 = arg1 + arg_size(*arg1);
995 ctx->code_position = arg2 + arg_size(*arg2);
996 if (likely(arg1[0] < 0x10) && likely(arg2[0] == ARG_IMM)) {
997 uint16_t m;
998 int64_t imm = get_imm(&arg2[1]);
999 if (!(imm & ~0xffffULL)) {
1000 code = S390_TMLL;
1001 m = (uint64_t)imm;
1002 } else if (!(imm & ~0xffff0000ULL)) {
1003 code = S390_TMLH;
1004 m = (uint64_t)imm >> 16;
1005 } else if (!(imm & ~0xffff00000000ULL)) {
1006 code = S390_TMHL;
1007 m = (uint64_t)imm >> 32;
1008 } else if (!(imm & ~0xffff000000000000ULL)) {
1009 code = S390_TMHH;
1010 m = (uint64_t)imm >> 48;
1011 } else {
1012 goto invl;
1013 }
1014 code |= (it)m << 16;
1015 code |= (it)arg1[0] << 36;
1016 g(cgen_s390(ctx, code));
1017 return true;
1018 }
1019 if (arg1[0] < 0x10 && arg2[0] == arg1[0]) {
1020 if (size == OP_SIZE_4) {
1021 code = S390_LTR;
1022 code |= (it)arg1[0] << 36;
1023 code |= (it)arg1[0] << 32;
1024 } else if (size == OP_SIZE_8) {
1025 code = S390_LTGR;
1026 code |= (it)arg1[0] << 20;
1027 code |= (it)arg1[0] << 16;
1028 } else {
1029 goto invl;
1030 }
1031 g(cgen_s390(ctx, code));
1032 return true;
1033 }
1034 invl:
1035 internal(file_line, "cgen_test: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
1036 return false;
1037 }
1039 static bool attr_w cgen_alu(struct codegen_context *ctx, unsigned size, unsigned alu, unsigned writes_flags)
1040 {
1041 uint8_t *arg1, *arg2, *arg3;
1042 arg1 = ctx->code_position;
1043 arg2 = arg1 + arg_size(*arg1);
1044 arg3 = arg2 + arg_size(*arg2);
1045 ctx->code_position = arg3 + arg_size(*arg3);
1046 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10))
1047 goto invl;
1048 if (writes_flags == 0) {
1049 if (unlikely(alu >= n_array_elements(codes_alu_no_flags)))
1050 goto invl;
1051 if (unlikely(codes_alu_no_flags[alu].rr == (it)-1) && unlikely(codes_alu_no_flags[alu].rrk == (it)-1))
1052 goto invl;
1053 g(cgen_rr_rx(ctx, size, arg1, arg2, arg3, &codes_alu_no_flags[alu]));
1054 } else if (writes_flags == 1) {
1055 if (unlikely(alu >= n_array_elements(codes_alu)))
1056 goto invl;
1057 if (unlikely(codes_alu[alu].rr == (it)-1) && unlikely(codes_alu[alu].rrk == (it)-1))
1058 goto invl;
1059 g(cgen_rr_rx(ctx, size, arg1, arg2, arg3, &codes_alu[alu]));
1060 } else if (writes_flags == 2) {
1061 if (unlikely(alu >= n_array_elements(codes_alu_log)))
1062 goto invl;
1063 if (unlikely(codes_alu_log[alu].rr == (it)-1) && unlikely(codes_alu_log[alu].rrk == (it)-1))
1064 goto invl;
1065 g(cgen_rr_rx(ctx, size, arg1, arg2, arg3, &codes_alu_log[alu]));
1066 } else {
1067 goto invl;
1068 }
1069 return true;
1070 invl:
1071 /*debug("%s", da(ctx->fn,function)->function_name);*/
1072 internal(file_line, "cgen_alu: invalid arguments %u, %u, %02x, %02x, %02x", size, alu, *arg1, *arg2, *arg3);
1073 return false;
1074 }
1076 static bool attr_w cgen_alu1(struct codegen_context *ctx, unsigned size, unsigned alu, unsigned writes_flags)
1077 {
1078 it code;
1079 uint8_t *arg1 = ctx->code_position;
1080 uint8_t *arg2 = arg1 + arg_size(*arg1);
1081 ctx->code_position = arg2 + arg_size(*arg2);
1082 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] != arg1[0]))
1083 goto invl;
1084 switch (alu) {
1085 case ALU1_NEG:
1086 if (unlikely(writes_flags != 1))
1087 goto invl;
1088 if (size == OP_SIZE_4) {
1089 code = S390_LCR;
1090 code |= (it)arg1[0] << 36;
1091 code |= (it)arg2[0] << 32;
1092 } else if (size == OP_SIZE_8) {
1093 code = S390_LCGR;
1094 code |= (it)arg1[0] << 20;
1095 code |= (it)arg2[0] << 16;
1096 } else {
1097 goto invl;
1098 }
1099 break;
1100 case ALU1_INC:
1101 case ALU1_DEC:
1102 if (unlikely(writes_flags != 1))
1103 goto invl;
1104 if (size == OP_SIZE_4) {
1105 code = S390_AHI;
1106 } else if (size == OP_SIZE_8) {
1107 code = S390_AGHI;
1108 } else {
1109 goto invl;
1110 }
1111 code |= (it)arg1[0] << 36;
1112 if (alu == ALU1_INC)
1113 code |= (it)0x0001 << 16;
1114 else
1115 code |= (it)0xffff << 16;
1116 break;
1117 case ALU1_BSWAP:
1118 if (size == OP_SIZE_4) {
1119 code = S390_LRVR;
1120 } else if (size == OP_SIZE_8) {
1121 code = S390_LRVRG;
1122 } else {
1123 goto invl;
1124 }
1125 code |= (it)arg1[0] << 20;
1126 code |= (it)arg2[0] << 16;
1127 break;
1128 case ALU1_POPCNT:
1129 if (size != OP_SIZE_8)
1130 goto invl;
1131 code = S390_POPCNT;
1132 code |= (it)arg1[0] << 20;
1133 code |= (it)arg2[0] << 16;
1134 break;
1135 default:
1136 goto invl;
1137 }
1138 g(cgen_s390(ctx, code));
1139 return true;
1140 invl:
1141 internal(file_line, "cgen_alu1: invalid arguments %u, %u, %02x, %02x", size, alu, *arg1, *arg2);
1142 return false;
1143 }
1145 static bool attr_w cgen_lea3(struct codegen_context *ctx)
1146 {
1147 it code;
1148 int64_t imm;
1149 uint8_t *arg1, *arg2, *arg3, *arg4;
1150 arg1 = ctx->code_position;
1151 arg2 = arg1 + arg_size(*arg1);
1152 arg3 = arg2 + arg_size(*arg2);
1153 arg4 = arg3 + arg_size(*arg3);
1154 ctx->code_position = arg4 + arg_size(*arg4);
1155 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10) || unlikely(arg3[0] >= 0x10) || arg4[0] != ARG_IMM)
1156 goto invl;
1157 imm = get_imm(&arg4[1]);
1158 if (imm >= 0 && imm < 0x1000) {
1159 code = S390_LA;
1160 } else {
1161 code = S390_LAY;
1162 code |= (it)(imm & 0xff000) >> 4;
1163 }
1164 code |= (it)arg1[0] << 36;
1165 code |= (it)arg2[0] << 32;
1166 code |= (it)arg3[0] << 28;
1167 code |= (it)(imm & 0xfff) << 16;
1168 g(cgen_s390(ctx, code));
1169 return true;
1170 invl:
1171 internal(file_line, "cgen_lea3: invalid arguments %02x, %02x, %02x, %02x", *arg1, *arg2, *arg3, *arg4);
1172 return false;
1173 }
1175 static bool attr_w cgen_rot(struct codegen_context *ctx, unsigned size, unsigned alu)
1176 {
1177 it code;
1178 unsigned sz;
1179 uint8_t *arg1, *arg2, *arg3;
1180 arg1 = ctx->code_position;
1181 arg2 = arg1 + arg_size(*arg1);
1182 arg3 = arg2 + arg_size(*arg2);
1183 ctx->code_position = arg3 + arg_size(*arg3);
1184 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10))
1185 goto invl;
1186 if (arg3[0] >= 0x10 && unlikely(arg3[0] != ARG_IMM))
1187 goto invl;
1189 if (size == OP_SIZE_4 && arg1[0] == arg2[0]) {
1190 code = rot32[alu];
1191 } else if (size == OP_SIZE_4) {
1192 code = rot32k[alu];
1193 } else if (size == OP_SIZE_8) {
1194 code = rot64[alu];
1195 } else {
1196 goto invl;
1197 }
1198 sz = code >> 46;
1199 if (sz == 1 || sz == 2) {
1200 code |= (it)arg1[0] << 36;
1201 } else if (sz == 3) {
1202 code |= (it)arg1[0] << 36;
1203 code |= (it)arg2[0] << 32;
1204 } else {
1205 goto invl;
1206 }
1207 if (arg3[0] == ARG_IMM)
1208 code |= (it)(get_imm(&arg3[1]) & (size == OP_SIZE_4 ? 0x1f : 0x3f)) << 16;
1209 else
1210 code |= (it)arg3[0] << 28;
1211 g(cgen_s390(ctx, code));
1212 return true;
1213 invl:
1214 internal(file_line, "cgen_rot: invalid arguments %u, %u, %02x, %02x, %02x", size, alu, *arg1, *arg2, *arg3);
1215 return false;
1216 }
1218 static bool attr_w cgen_mul_l(struct codegen_context *ctx, unsigned size)
1219 {
1220 it code;
1221 uint8_t *arg1, *arg2, *arg3, *arg4;
1222 arg1 = ctx->code_position;
1223 arg2 = arg1 + arg_size(*arg1);
1224 arg3 = arg2 + arg_size(*arg2);
1225 arg4 = arg3 + arg_size(*arg3);
1226 ctx->code_position = arg4 + arg_size(*arg4);
1227 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10) || unlikely(arg3[0] >= 0x10) || unlikely(arg4[0] >= 0x10))
1228 goto invl;
1229 if (unlikely(arg2[0] & 1) || unlikely(arg1[0] != arg2[0] + 1) || unlikely(arg3[0] != arg1[0]))
1230 goto invl;
1231 if (size == OP_SIZE_4) {
1232 code = S390_MR;
1233 code |= (it)arg2[0] << 36;
1234 code |= (it)arg4[0] << 32;
1235 } else {
1236 code = S390_MGRK;
1237 code |= (it)arg2[0] << 20;
1238 code |= (it)arg3[0] << 16;
1239 code |= (it)arg4[0] << 28;
1240 }
1241 g(cgen_s390(ctx, code));
1242 return true;
1243 invl:
1244 internal(file_line, "cgen_mul_l: invalid arguments %02x, %02x, %02x, %02x", *arg1, *arg2, *arg3, *arg4);
1245 return false;
1246 }
1248 static bool attr_w cgen_div_l(struct codegen_context *ctx, unsigned size, bool sgn)
1249 {
1250 it code;
1251 uint8_t *arg1, *arg2, *arg3, *arg4, *arg5;
1252 arg1 = ctx->code_position;
1253 arg2 = arg1 + arg_size(*arg1);
1254 arg3 = arg2 + arg_size(*arg2);
1255 arg4 = arg3 + arg_size(*arg3);
1256 arg5 = arg4 + arg_size(*arg4);
1257 ctx->code_position = arg5 + arg_size(*arg5);
1258 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] >= 0x10) || unlikely(arg3[0] >= 0x10) || unlikely(arg4[0] >= 0x10) || unlikely(arg5[0] >= 0x10))
1259 goto invl;
1260 if (unlikely(arg1[0] & 1) || unlikely(arg2[0] != arg1[0] + 1))
1261 goto invl;
1262 if (unlikely(arg3[0] != arg1[0]) || unlikely(arg4[0] != arg3[0] + 1))
1263 goto invl;
1264 if (!sgn) {
1265 code = size == OP_SIZE_4 ? S390_DLR : S390_DLGR;
1266 } else {
1267 code = size == OP_SIZE_4 ? S390_DR : S390_DSGR;
1268 }
1269 if (code == S390_DR) {
1270 code |= (it)arg1[0] << 36;
1271 code |= (it)arg5[0] << 32;
1272 } else {
1273 code |= (it)arg1[0] << 20;
1274 code |= (it)arg5[0] << 16;
1275 }
1276 g(cgen_s390(ctx, code));
1277 return true;
1278 invl:
1279 internal(file_line, "cgen_div_l: invalid arguments %02x, %02x, %02x, %02x, %02x", *arg1, *arg2, *arg3, *arg4, *arg4);
1280 return false;
1281 }
1283 static bool attr_w cgen_cmov(struct codegen_context *ctx, unsigned size, unsigned cond, bool logical)
1284 {
1285 uint8_t *arg1 = ctx->code_position;
1286 uint8_t *arg2 = arg1 + arg_size(*arg1);
1287 uint8_t *arg3 = arg2 + arg_size(*arg2);
1288 ctx->code_position = arg3 + arg_size(*arg3);
1289 if (unlikely(arg1[0] != arg2[0]) || arg1[0] >= 0x10)
1290 goto invl;
1292 if (arg3[0] < 0x10) {
1293 it code;
1294 code = size == OP_SIZE_4 ? S390_LOCR : S390_LOCGR;
1295 code |= (it)get_jmp_cond(cond, logical) << 28;
1296 code |= (it)arg1[0] << 20;
1297 code |= (it)arg3[0] << 16;
1298 g(cgen_s390(ctx, code));
1299 return true;
1300 } else if (arg3[0] == ARG_ADDRESS_1) {
1301 it code;
1302 int64_t imm;
1303 code = size == OP_SIZE_4 ? S390_LOC : S390_LOCG;
1304 code |= (it)get_jmp_cond(cond, logical) << 32;
1305 code |= (it)arg1[0] << 36;
1306 code |= (it)arg3[1] << 28;
1307 imm = get_imm(&arg3[2]);
1308 if (imm < -0x80000 || imm >= 0x80000)
1309 goto invl;
1310 code |= (it)(imm & 0xfff) << 16;
1311 code |= (it)(imm & 0xff000) >> 4;
1312 g(cgen_s390(ctx, code));
1313 return true;
1314 }
1316 invl:
1317 internal(file_line, "cgen_cmov: invalid arguments %02x, %02x, %02x", *arg1, *arg2, *arg3);
1318 }
1320 static bool attr_w cgen_ldp_stp(struct codegen_context *ctx, unsigned size, bool st)
1321 {
1322 uint8_t *arg1, *arg2, *arg3;
1323 if (!st) {
1324 arg2 = ctx->code_position;
1325 arg3 = arg2 + arg_size(*arg2);
1326 arg1 = arg3 + arg_size(*arg3);
1327 ctx->code_position = arg1 + arg_size(*arg1);
1328 } else {
1329 arg1 = ctx->code_position;
1330 arg2 = arg1 + arg_size(*arg1);
1331 arg3 = arg2 + arg_size(*arg2);
1332 ctx->code_position = arg3 + arg_size(*arg3);
1333 }
1334 if (unlikely(arg2[0] >= 0x10) || unlikely(arg3[0] >= 0x10))
1335 goto invl;
1336 if (unlikely(arg2[0] != arg3[0] + 1))
1337 goto invl;
1338 if (!st)
1339 g(cgen_lm_stm(ctx, size, arg3[0], arg2[0], arg1, S390_LM, S390_LMY, S390_LMG));
1340 else
1341 g(cgen_lm_stm(ctx, size, arg3[0], arg2[0], arg1, S390_STM, S390_STMY, S390_STMG));
1342 return true;
1343 invl:
1344 internal(file_line, "cgen_ldp_stp: invalid arguments %u, %02x, %02x, %02x", size, *arg1, *arg2, *arg3);
1345 return false;
1346 }
1348 static bool attr_w cgen_ic(struct codegen_context *ctx)
1349 {
1350 uint8_t *arg1, *arg2, *arg3;
1351 arg1 = ctx->code_position;
1352 arg2 = arg1 + arg_size(*arg1);
1353 arg3 = arg2 + arg_size(*arg2);
1354 ctx->code_position = arg3 + arg_size(*arg3);
1355 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] != arg1[0]))
1356 goto invl;
1357 g(cgen_rr_rx(ctx, OP_SIZE_4, arg1, arg2, arg3, &codes_ic));
1358 return true;
1359 invl:
1360 internal(file_line, "cgen_ic: invalid arguments %02x, %02x, %02x", *arg1, *arg2, *arg3);
1361 return false;
1362 }
1364 static bool attr_w cgen_mov_mask(struct codegen_context *ctx)
1365 {
1366 it code;
1367 int64_t imm;
1368 uint8_t *arg1, *arg2, *arg3;
1369 arg1 = ctx->code_position;
1370 arg2 = arg1 + arg_size(*arg1);
1371 arg3 = arg2 + arg_size(*arg2);
1372 ctx->code_position = arg3 + arg_size(*arg3);
1373 if (unlikely(arg1[0] >= 0x10) || unlikely(arg2[0] != arg1[0]) || unlikely(arg3[0] != ARG_IMM))
1374 goto invl;
1375 imm = get_imm(&arg3[1]);
1376 code = S390_IIHF;
1377 code |= (it)arg1[1] << 36;
1378 code |= (it)(imm & 0xffffffffLL);
1379 g(cgen_s390(ctx, code));
1380 return true;
1381 invl:
1382 internal(file_line, "cgen_mov_mask: invalid arguments %02x, %02x, %02x", *arg1, *arg2, *arg3);
1383 return false;
1384 }
1386 static bool attr_w cgen_memcpy(struct codegen_context *ctx)
1387 {
1388 it code;
1389 int64_t disp_dest, disp_src, len;
1390 uint8_t *arg1, *arg2, *arg3;
1391 arg1 = ctx->code_position;
1392 arg2 = arg1 + arg_size(*arg1);
1393 arg3 = arg2 + arg_size(*arg2);
1394 ctx->code_position = arg3 + arg_size(*arg3);
1395 if (unlikely(arg1[0] != ARG_ADDRESS_1) || unlikely(arg2[0] != ARG_ADDRESS_1) || unlikely(arg3[0] != ARG_IMM))
1396 goto invl;
1397 disp_dest = get_imm(&arg1[2]);
1398 disp_src = get_imm(&arg2[2]);
1399 len = get_imm(&arg3[1]);
1400 code = S390_MVC;
1401 code |= (it)((len - 1) & 0xff) << 32;
1402 code |= (it)arg1[1] << 28;
1403 code |= (it)(disp_dest & 0xfff) << 16;
1404 code |= (it)arg2[1] << 12;
1405 code |= (it)(disp_src & 0xfff) << 0;
1406 g(cgen_s390(ctx, code));
1407 return true;
1408 invl:
1409 internal(file_line, "cgen_memcpy: invalid arguments %02x, %02x, %02x", *arg1, *arg2, *arg3);
1410 return false;
1411 }
1413 static bool attr_w cgen_fp_cmp(struct codegen_context *ctx, unsigned size)
1414 {
1415 uint8_t *arg1 = ctx->code_position;
1416 uint8_t *arg2 = arg1 + arg_size(*arg1);
1417 ctx->code_position = arg2 + arg_size(*arg2);
1418 if (unlikely(!reg_is_fp(arg1[0])))
1419 goto invl;
1420 g(cgen_fp_op(ctx, size, arg1, arg2, &fp_cmp));
1421 return true;
1422 invl:
1423 internal(file_line, "cgen_fp_cmp: invalid arguments %u, %02x, %02x", size, *arg1, *arg2);
1424 return false;
1425 }
1427 static bool attr_w cgen_fp_alu(struct codegen_context *ctx, unsigned size, unsigned aux)
1428 {
1429 uint8_t *arg1 = ctx->code_position;
1430 uint8_t *arg2 = arg1 + arg_size(*arg1);
1431 uint8_t *arg3 = arg2 + arg_size(*arg2);
1432 ctx->code_position = arg3 + arg_size(*arg3);
1433 if (unlikely(!reg_is_fp(arg1[0])) || unlikely(arg1[0] != arg2[0]))
1434 goto invl;
1435 g(cgen_fp_op(ctx, size, arg1, arg3, &fp_alus[aux]));
1436 return true;
1437 invl:
1438 internal(file_line, "cgen_fp_alu: invalid arguments %u, %u, %02x, %02x, %02x", size, aux, *arg1, *arg2, *arg3);
1439 return false;
1440 }
1442 static bool attr_w cgen_fp_alu1(struct codegen_context *ctx, unsigned size, unsigned aux)
1443 {
1444 uint8_t *arg1 = ctx->code_position;
1445 uint8_t *arg2 = arg1 + arg_size(*arg1);
1446 ctx->code_position = arg2 + arg_size(*arg2);
1447 if (unlikely(!reg_is_fp(arg1[0])))
1448 goto invl;
1449 g(cgen_fp_op(ctx, size, arg1, arg2, &fp_alu1s[aux]));
1450 return true;
1451 invl:
1452 internal(file_line, "cgen_fp_alu1: invalid arguments %u, %u, %02x, %02x", size, aux, *arg1, *arg2);
1453 return false;
1454 }
1456 static bool attr_w cgen_fp_to_int(struct codegen_context *ctx, unsigned int_op_size, unsigned fp_op_size)
1457 {
1458 it code;
1459 uint8_t *arg1 = ctx->code_position;
1460 uint8_t *arg2 = arg1 + arg_size(*arg1);
1461 ctx->code_position = arg2 + arg_size(*arg2);
1462 if (unlikely(arg1[0] >= 0x10) || unlikely(!reg_is_fp(arg2[0])))
1463 goto invl;
1464 switch (fp_op_size) {
1465 case OP_SIZE_4:
1466 code = int_op_size == OP_SIZE_4 ? S390_CFEBR : S390_CGEBR;
1467 break;
1468 case OP_SIZE_8:
1469 code = int_op_size == OP_SIZE_4 ? S390_CFDBR : S390_CGDBR;
1470 break;
1471 case OP_SIZE_16:
1472 code = int_op_size == OP_SIZE_4 ? S390_CFXBR : S390_CGXBR;
1473 break;
1474 default:
1475 goto invl;
1476 }
1477 code |= (it)5 << 28;
1478 code |= (it)arg1[0] << 20;
1479 code |= (it)(arg2[0] & 0xf) << 16;
1480 g(cgen_s390(ctx, code));
1481 return true;
1482 invl:
1483 internal(file_line, "cgen_fp_to_int: invalid arguments %u, %u, %02x, %02x", int_op_size, fp_op_size, *arg1, *arg2);
1484 return false;
1485 }
1487 static bool attr_w cgen_fp_from_int(struct codegen_context *ctx, unsigned int_op_size, unsigned fp_op_size)
1488 {
1489 it code;
1490 uint8_t *arg1 = ctx->code_position;
1491 uint8_t *arg2 = arg1 + arg_size(*arg1);
1492 ctx->code_position = arg2 + arg_size(*arg2);
1493 if (unlikely(!reg_is_fp(arg1[0])) || unlikely(arg2[0] >= 0x10))
1494 goto invl;
1495 switch (fp_op_size) {
1496 case OP_SIZE_4:
1497 code = int_op_size == OP_SIZE_4 ? S390_CEFBR : S390_CEGBR;
1498 break;
1499 case OP_SIZE_8:
1500 code = int_op_size == OP_SIZE_4 ? S390_CDFBR : S390_CDGBR;
1501 break;
1502 case OP_SIZE_16:
1503 code = int_op_size == OP_SIZE_4 ? S390_CXFBR : S390_CXGBR;
1504 break;
1505 default:
1506 goto invl;
1507 }
1508 code |= (it)(arg1[0] & 0xf) << 20;
1509 code |= (it)arg2[0] << 16;
1510 g(cgen_s390(ctx, code));
1511 return true;
1512 invl:
1513 internal(file_line, "cgen_fp_from_int: invalid arguments %u, %u, %02x, %02x", int_op_size, fp_op_size, *arg1, *arg2);
1514 return false;
1515 }
1517 static bool attr_w cgen_jmp_cond(struct codegen_context *ctx, bool lng, unsigned aux, bool logical)
1518 {
1519 it code;
1520 if (!lng) {
1521 g(add_relocation(ctx, JMP_SHORTEST, 0, NULL));
1522 code = S390_BRC;
1523 } else if (USE_BRCL) {
1524 g(add_relocation(ctx, JMP_SHORT, 0, NULL));
1525 code = S390_BRCL;
1526 } else {
1527 g(add_relocation(ctx, JMP_SHORT, 0, NULL));
1528 code = S390_BRAS;
1529 code |= (it)R_OFFSET_IMM << 36;
1530 code |= (it)4 << 16;
1531 g(cgen_s390(ctx, code));
1532 cgen_four(0);
1533 #if defined(ARCH_S390_32)
1534 code = S390_L;
1535 #else
1536 code = S390_LGF;
1537 #endif
1538 code |= (it)R_CONST_IMM << 36;
1539 code |= (it)R_OFFSET_IMM << 28;
1540 g(cgen_s390(ctx, code));
1541 code = S390_LA;
1542 code |= (it)R_OFFSET_IMM << 36;
1543 code |= (it)R_OFFSET_IMM << 32;
1544 code |= (it)R_CONST_IMM << 28;
1545 g(cgen_s390(ctx, code));
1546 code = S390_BCR;
1547 code |= (it)R_OFFSET_IMM << 32;
1548 code |= (it)get_jmp_cond(aux, logical) << 36;
1549 g(cgen_s390(ctx, code));
1550 return true;
1551 }
1552 code |= (it)get_jmp_cond(aux, logical) << 36;
1553 g(cgen_s390(ctx, code));
1554 return true;
1555 }
1557 static bool attr_w cgen_jmp_indirect(struct codegen_context *ctx)
1558 {
1559 uint8_t reg = cget_one(ctx);
1560 it code = S390_BCR;
1561 code |= (it)(S390_BRC_OVF | S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_EQ) << 36;
1562 code |= (it)reg << 32;
1563 g(cgen_s390(ctx, code));
1564 return true;
1565 }
1567 static bool attr_w resolve_relocation(struct codegen_context *ctx, struct relocation *reloc)
1568 {
1569 int64_t offs = ((int64_t)ctx->label_to_pos[reloc->label_id] - (int64_t)(reloc->position)) / 2;
1570 switch (reloc->length) {
1571 case JMP_SHORTEST: {
1572 int16_t i16;
1573 if (unlikely(offs < -0x8000) || unlikely(offs >= 0x8000))
1574 return false;
1575 i16 = offs;
1576 memcpy(ctx->mcode + reloc->position + 2, &i16, 2);
1577 return true;
1578 }
1579 case JMP_SHORT: {
1580 int32_t i32;
1581 if (USE_BRCL) {
1582 if (unlikely(offs < -0x80000000LL) || unlikely(offs >= 0x80000000LL))
1583 return false;
1584 i32 = offs;
1585 memcpy(ctx->mcode + reloc->position + 2, &i32, 4);
1586 return true;
1587 } else {
1588 offs *= 2;
1589 offs -= 4;
1590 if (unlikely(offs < -0x80000000LL) || unlikely(offs >= 0x80000000LL))
1591 return false;
1592 i32 = offs;
1593 memcpy(ctx->mcode + reloc->position + 4, &i32, 4);
1594 return true;
1595 }
1596 }
1597 default: {
1598 internal(file_line, "resolve_relocation: invalid relocation length %u", reloc->length);
1599 return false;
1600 }
1601 }
1602 }
1604 static bool attr_w cgen_insn(struct codegen_context *ctx, uint32_t insn)
1605 {
1606 /*debug("insn: %08x", insn);*/
1607 switch (insn_opcode(insn)) {
1608 case INSN_ENTRY:
1609 g(cgen_entry(ctx));
1610 return true;
1611 case INSN_LABEL:
1612 g(cgen_label(ctx));
1613 return true;
1614 case INSN_RET:
1615 g(cgen_s390(ctx, S390_BCR | ((it)(S390_BRC_OVF | S390_BRC_GREATER | S390_BRC_LESS | S390_BRC_EQ) << 36) | ((it)R_14 << 32)));
1616 return true;
1617 case INSN_S390_PUSH:
1618 g(cgen_s390_push_pop(ctx, insn_op_size(insn), true));
1619 return true;
1620 case INSN_S390_POP:
1621 g(cgen_s390_push_pop(ctx, insn_op_size(insn), false));
1622 return true;
1623 case INSN_CALL_INDIRECT:
1624 g(cgen_call_indirect(ctx));
1625 return true;
1626 case INSN_MOV:
1627 g(cgen_mov(ctx, insn_op_size(insn)));
1628 return true;
1629 case INSN_MOVSX:
1630 g(cgen_movsx(ctx, insn_op_size(insn)));
1631 return true;
1632 case INSN_CMP:
1633 g(cgen_cmp(ctx, insn_op_size(insn), insn_writes_flags(insn)));
1634 return true;
1635 case INSN_TEST:
1636 if (unlikely(!insn_writes_flags(insn)))
1637 goto invalid_insn;
1638 g(cgen_test(ctx, insn_op_size(insn)));
1639 return true;
1640 case INSN_ALU:
1641 if (unlikely(insn_op_size(insn) != OP_SIZE_NATIVE))
1642 goto invalid_insn;
1643 g(cgen_alu(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1644 return true;
1645 case INSN_ALU_PARTIAL:
1646 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) >= OP_SIZE_NATIVE))
1647 goto invalid_insn;
1648 g(cgen_alu(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1649 return true;
1650 case INSN_ALU1:
1651 if (unlikely(insn_op_size(insn) != OP_SIZE_NATIVE))
1652 goto invalid_insn;
1653 g(cgen_alu1(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1654 return true;
1655 case INSN_ALU1_PARTIAL:
1656 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) >= OP_SIZE_NATIVE))
1657 goto invalid_insn;
1658 g(cgen_alu1(ctx, insn_op_size(insn), insn_aux(insn), insn_writes_flags(insn)));
1659 return true;
1660 case INSN_LEA3:
1661 if (unlikely(insn_op_size(insn) != OP_SIZE_ADDRESS))
1662 goto invalid_insn;
1663 if (unlikely(insn_aux(insn) != 0))
1664 goto invalid_insn;
1665 g(cgen_lea3(ctx));
1666 return true;
1667 case INSN_ROT:
1668 if (unlikely(insn_op_size(insn) != OP_SIZE_NATIVE))
1669 goto invalid_insn;
1670 g(cgen_rot(ctx, insn_op_size(insn), insn_aux(insn)));
1671 return true;
1672 case INSN_ROT_PARTIAL:
1673 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) >= OP_SIZE_NATIVE))
1674 goto invalid_insn;
1675 g(cgen_rot(ctx, insn_op_size(insn), insn_aux(insn)));
1676 return true;
1677 case INSN_MUL_L:
1678 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) > OP_SIZE_NATIVE))
1679 goto invalid_insn;
1680 g(cgen_mul_l(ctx, insn_op_size(insn)));
1681 return true;
1682 case INSN_DIV_L:
1683 g(cgen_div_l(ctx, insn_op_size(insn), insn_aux(insn)));
1684 return true;
1685 case INSN_CMOV:
1686 case INSN_CMOV_XCC:
1687 if (unlikely(!cpu_test_feature(CPU_FEATURE_misc_45)))
1688 goto invalid_insn;
1689 g(cgen_cmov(ctx, insn_op_size(insn), insn_aux(insn), insn_opcode(insn) == INSN_CMOV_XCC));
1690 return true;
1691 case INSN_STP:
1692 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) > OP_SIZE_NATIVE))
1693 goto invalid_insn;
1694 g(cgen_ldp_stp(ctx, insn_op_size(insn), true));
1695 return true;
1696 case INSN_LDP:
1697 if (unlikely(insn_op_size(insn) <= OP_SIZE_2) || unlikely(insn_op_size(insn) > OP_SIZE_NATIVE))
1698 goto invalid_insn;
1699 g(cgen_ldp_stp(ctx, insn_op_size(insn), false));
1700 return true;
1701 case INSN_MOV_MASK:
1702 if (unlikely(insn_op_size(insn) != OP_SIZE_NATIVE))
1703 goto invalid_insn;
1704 if (insn_aux(insn) == MOV_MASK_0_8) {
1705 g(cgen_ic(ctx));
1706 } else if (insn_aux(insn) == MOV_MASK_32_64) {
1707 g(cgen_mov_mask(ctx));
1708 } else {
1709 goto invalid_insn;
1710 }
1711 return true;
1712 case INSN_MEMCPY:
1713 g(cgen_memcpy(ctx));
1714 return true;
1715 case INSN_FP_CMP:
1716 g(cgen_fp_cmp(ctx, insn_op_size(insn)));
1717 return true;
1718 case INSN_FP_ALU:
1719 g(cgen_fp_alu(ctx, insn_op_size(insn), insn_aux(insn)));
1720 return true;
1721 case INSN_FP_ALU1:
1722 g(cgen_fp_alu1(ctx, insn_op_size(insn), insn_aux(insn)));
1723 return true;
1724 case INSN_FP_TO_INT32:
1725 g(cgen_fp_to_int(ctx, OP_SIZE_4, insn_op_size(insn)));
1726 return true;
1727 case INSN_FP_TO_INT64:
1728 g(cgen_fp_to_int(ctx, OP_SIZE_8, insn_op_size(insn)));
1729 return true;
1730 case INSN_FP_FROM_INT32:
1731 g(cgen_fp_from_int(ctx, OP_SIZE_4, insn_op_size(insn)));
1732 return true;
1733 case INSN_FP_FROM_INT64:
1734 g(cgen_fp_from_int(ctx, OP_SIZE_8, insn_op_size(insn)));
1735 return true;
1736 case INSN_JMP:
1737 g(cgen_jmp_cond(ctx, insn_jump_size(insn) == JMP_SHORT, COND_ALWAYS, false));
1738 return true;
1739 case INSN_JMP_COND:
1740 g(cgen_jmp_cond(ctx, insn_jump_size(insn) == JMP_SHORT, insn_aux(insn), false));
1741 return true;
1742 case INSN_JMP_COND_LOGICAL:
1743 g(cgen_jmp_cond(ctx, insn_jump_size(insn) == JMP_SHORT, insn_aux(insn), true));
1744 return true;
1745 case INSN_JMP_INDIRECT:
1746 g(cgen_jmp_indirect(ctx));
1747 return true;
1748 default:
1749 invalid_insn:
1750 internal(file_line, "cgen_insn: invalid insn %08x", insn);
1751 return false;
1752 }
1753 }