From d19d300499ecd18fb2687d71cc5a8c5937bb5f9b Mon Sep 17 00:00:00 2001
From: Mikulas Patocka <mikulas@twibright.com>
Date: Thu, 10 Oct 2024 23:34:49 +0200
Subject: [PATCH] sparc: allocate registers

---
 c1-sparc.inc | 14 ++++++++++----
 codegen.c    |  4 ++++
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/c1-sparc.inc b/c1-sparc.inc
index b2c7861..3eb507c 100644
--- a/c1-sparc.inc
+++ b/c1-sparc.inc
@@ -32,7 +32,7 @@
 
 #define UNALIGNED_TRAP			1
 
-#define ALU_WRITES_FLAGS(alu, im)		0
+#define ALU_WRITES_FLAGS(alu, im)	0
 #define ALU1_WRITES_FLAGS(alu)		0
 #define ROT_WRITES_FLAGS(alu)		0
 #define COND_IS_LOGICAL(cond)		0
@@ -183,7 +183,9 @@
 
 #define R_SCRATCH_NA_1	R_O4
 #define R_SCRATCH_NA_2	R_O5
+#ifdef HAVE_BITWISE_FRAME
 #define R_SCRATCH_NA_3	R_O7
+#endif
 
 #define R_SAVED_1	R_L0
 #define R_SAVED_2	R_L1
@@ -208,9 +210,13 @@ static bool reg_is_fp(unsigned reg)
 	return reg >= 0x20 && reg < 0x40;
 }
 
-static const uint8_t reg_available[] = { 0 };
-#define n_reg_available 0
-#define reg_is_saved(r)	1
+static const uint8_t reg_available[] = { R_L2, R_L3, R_L4, R_L5, R_L6, R_L7, R_I3, R_I4, R_I5, R_G4, R_G5,
+#ifndef HAVE_BITWISE_FRAME
+		R_O7,
+#endif
+	};
+#define n_reg_available n_array_elements(reg_available)
+#define reg_is_saved(r)	((r) >= R_L0 && (r) <= R_I7)
 
 static bool attr_w gen_load_constant(struct codegen_context *ctx, unsigned reg, uint64_t c)
 {
diff --git a/codegen.c b/codegen.c
index 66c2435..5bbf36f 100644
--- a/codegen.c
+++ b/codegen.c
@@ -9604,6 +9604,10 @@ static bool attr_w gen_registers(struct codegen_context *ctx)
 			continue;
 		if (!ARCH_HAS_BWX && t->size < 1U << OP_SIZE_4)
 			continue;
+#if defined(ARCH_PARISC) || defined(ARCH_SPARC)
+		if (t->size > 1U << OP_SIZE_ADDRESS)
+			continue;
+#endif
 		if ((TYPE_TAG_IS_FIXED(t->tag) || TYPE_TAG_IS_INT(t->tag)) && is_power_of_2(t->size) && t->size <= 1U << OP_SIZE_NATIVE) {
 			if (int_reg >= nav)
 				continue;
-- 
2.11.4.GIT