kvm-opensuse/kvm-qemu-ide-ich6.patch

   1 #qemu-only -> submit upstream qemu
   2 Index: kvm-75/qemu/hw/ide.c
   3 ===================================================================
   4 --- kvm-75.orig/qemu/hw/ide.c
   5 +++ kvm-75/qemu/hw/ide.c
   6 @@ -462,6 +462,7 @@ static inline int media_is_cd(IDEState *
   7  #define IDE_TYPE_PIIX3   0
   8  #define IDE_TYPE_CMD646  1
   9  #define IDE_TYPE_PIIX4   2
  10 +#define IDE_TYPE_ICH6    3
  11
  12  /* CMD646 specific */
  13  #define MRDMODE                0x71
  14 @@ -3164,6 +3165,57 @@ void pci_piix3_ide_init(PCIBus *bus, Blo
  15
  16      qemu_register_reset(piix3_reset, d);
  17      piix3_reset(d);
  18 +
  19 +    pci_register_io_region((PCIDevice *)d, 4, 0x10,
  20 +                           PCI_ADDRESS_SPACE_IO, bmdma_map);
  21 +
  22 +    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
  23 +    ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
  24 +    ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
  25 +    ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
  26 +
  27 +    for (i = 0; i < 4; i++)
  28 +        if (hd_table[i])
  29 +            hd_table[i]->devfn = d->dev.devfn;
  30 +
  31 +    register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
  32 +}
  33 +
  34 +
  35 +/* hd_table must contain 4 block drivers */
  36 +/* NOTE: for the ICH-6, the IRQs and IOports are hardcoded */
  37 +void pci_ich6_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
  38 +                        qemu_irq *pic)
  39 +{
  40 +    PCIIDEState *d;
  41 +    uint8_t *pci_conf;
  42 +    int i;
  43 +
  44 +    /* register a function 1 of ICH-6 */
  45 +    d = (PCIIDEState *)pci_register_device(bus, "ICH-6 IDE",
  46 +                                           sizeof(PCIIDEState),
  47 +                                           devfn,
  48 +                                           NULL, NULL);
  49 +    d->type = IDE_TYPE_ICH6;
  50 +
  51 +    pci_conf = d->dev.config;
  52 +    pci_conf[0x00] = 0x86; // Intel
  53 +    pci_conf[0x01] = 0x80;
  54 +    pci_conf[0x02] = 0x9e;
  55 +    pci_conf[0x03] = 0x26;
  56 +
  57 +    pci_conf[0x09] = 0x80; // legacy ATA mode
  58 +    pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
  59 +    pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
  60 +    pci_conf[0x0e] = 0x00; // header_type
  61 +
  62 +    pci_conf[0x40] = 0;
  63 +    pci_conf[0x41] = 0xf0; // primary port enabled
  64 +    pci_conf[0x42] = 0;
  65 +    pci_conf[0x43] = 0x00; // secondary port disabled
  66 +
  67 +    qemu_register_reset(piix3_reset, d);
  68 +    piix3_reset(d);
  69
  70      pci_register_io_region((PCIDevice *)d, 4, 0x10,
  71                             PCI_ADDRESS_SPACE_IO, bmdma_map);
  72 Index: kvm-75/qemu/hw/irq.c
  73 ===================================================================
  74 --- kvm-75.orig/qemu/hw/irq.c
  75 +++ kvm-75/qemu/hw/irq.c
  76 @@ -35,6 +35,7 @@ void qemu_set_irq(qemu_irq irq, int leve
  77      if (!irq)
  78          return;
  79
  80 +//printf("IRQ set %#hhx = %#hhd using %p\n", irq->n, level, irq->handler);
  81      irq->handler(irq->opaque, irq->n, level);
  82  }
  83
  84 Index: kvm-75/qemu/hw/pc.h
  85 ===================================================================
  86 --- kvm-75.orig/qemu/hw/pc.h
  87 +++ kvm-75/qemu/hw/pc.h
  88 @@ -145,6 +145,8 @@ void pci_piix3_ide_init(PCIBus *bus, Blo
  89                          qemu_irq *pic);
  90  void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
  91                          qemu_irq *pic);
  92 +void pci_ich6_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
  93 +                        qemu_irq *pic);
  94
  95  /* ne2000.c */
  96