src/main/drivers/dma.h

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #pragma once
  22
  23 #include "drivers/resource.h"
  24
  25 #if defined(USE_ATBSP_DRIVER)
  26 #include "dma_atbsp.h"
  27 #endif
  28
  29 #if defined(APM32F4)
  30 #include "dma_apm32.h"
  31 #endif
  32
  33 #define CACHE_LINE_SIZE 32
  34 #define CACHE_LINE_MASK (CACHE_LINE_SIZE - 1)
  35
  36 // dmaResource_t is a opaque data type which represents a single DMA engine,
  37 // called and implemented differently in different families of STM32s.
  38 // The opaque data type provides uniform handling of the engine in source code.
  39 // The engines are referenced by dmaResource_t through out the Betaflight code,
  40 // and then converted back to DMA_ARCH_TYPE which is a native type for
  41 // the particular MCU type when calling library functions.
  42
  43 typedef struct dmaResource_s dmaResource_t;
  44
  45 #if defined(STM32F4) || defined(STM32F7)
  46 #define DMA_ARCH_TYPE DMA_Stream_TypeDef
  47 #elif defined(STM32H7)
  48 // H7 has stream based DMA and channel based BDMA, but we ignore BDMA (for now).
  49 #define DMA_ARCH_TYPE DMA_Stream_TypeDef
  50 #elif defined(AT32F435)
  51 #define DMA_ARCH_TYPE dma_channel_type
  52 #elif defined(APM32F4)
  53 #define DMA_ARCH_TYPE DMA_Stream_TypeDef
  54 #else
  55 #define DMA_ARCH_TYPE DMA_Channel_TypeDef
  56 #endif
  57
  58 struct dmaChannelDescriptor_s;
  59 typedef void (*dmaCallbackHandlerFuncPtr)(struct dmaChannelDescriptor_s *channelDescriptor);
  60
  61 typedef struct dmaChannelDescriptor_s {
  62     DMA_TypeDef*                dma;
  63     dmaResource_t               *ref;
  64 #if defined(STM32F4) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(APM32F4)
  65     uint8_t                     stream;
  66 #endif
  67     uint32_t                    channel;
  68     dmaCallbackHandlerFuncPtr   irqHandlerCallback;
  69     uint8_t                     flagsShift;
  70     IRQn_Type                   irqN;
  71     uint32_t                    userParam;
  72     resourceOwner_t             owner;
  73     uint8_t                     resourceIndex;
  74     uint32_t                    completeFlag;
  75 #if defined(USE_ATBSP_DRIVER)
  76     dmamux_channel_type         *dmamux;
  77 #endif
  78 } dmaChannelDescriptor_t;
  79
  80 #define DMA_IDENTIFIER_TO_INDEX(x) ((x) - 1)
  81
  82 #if defined(USE_ATBSP_DRIVER)
  83
  84 #elif defined(APM32F4)
  85 // dma_apm32.h
  86
  87 #elif defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
  88
  89 typedef enum {
  90     DMA_NONE = 0,
  91     DMA1_ST0_HANDLER = 1,
  92     DMA1_ST1_HANDLER,
  93     DMA1_ST2_HANDLER,
  94     DMA1_ST3_HANDLER,
  95     DMA1_ST4_HANDLER,
  96     DMA1_ST5_HANDLER,
  97     DMA1_ST6_HANDLER,
  98     DMA1_ST7_HANDLER,
  99     DMA2_ST0_HANDLER,
 100     DMA2_ST1_HANDLER,
 101     DMA2_ST2_HANDLER,
 102     DMA2_ST3_HANDLER,
 103     DMA2_ST4_HANDLER,
 104     DMA2_ST5_HANDLER,
 105     DMA2_ST6_HANDLER,
 106     DMA2_ST7_HANDLER,
 107     DMA_LAST_HANDLER = DMA2_ST7_HANDLER
 108 } dmaIdentifier_e;
 109
 110 #define DMA_DEVICE_NO(x)    ((((x)-1) / 8) + 1)
 111 #define DMA_DEVICE_INDEX(x) ((((x)-1) % 8))
 112 #define DMA_OUTPUT_INDEX    0
 113 #define DMA_OUTPUT_STRING   "DMA%d Stream %d:"
 114 #define DMA_INPUT_STRING    "DMA%d_ST%d"
 115
 116 #define DEFINE_DMA_CHANNEL(d, s, f) { \
 117     .dma = d, \
 118     .ref = (dmaResource_t *)d ## _Stream ## s, \
 119     .stream = s, \
 120     .irqHandlerCallback = NULL, \
 121     .flagsShift = f, \
 122     .irqN = d ## _Stream ## s ## _IRQn, \
 123     .userParam = 0, \
 124     .owner.owner = 0, \
 125     .owner.resourceIndex = 0 \
 126     }
 127
 128 #define DEFINE_DMA_IRQ_HANDLER(d, s, i) FAST_IRQ_HANDLER void DMA ## d ## _Stream ## s ## _IRQHandler(void) {\
 129                                                                 const uint8_t index = DMA_IDENTIFIER_TO_INDEX(i); \
 130                                                                 dmaCallbackHandlerFuncPtr handler = dmaDescriptors[index].irqHandlerCallback; \
 131                                                                 if (handler) \
 132                                                                     handler(&dmaDescriptors[index]); \
 133                                                             }
 134
 135 #define DMA_CLEAR_FLAG(d, flag) if (d->flagsShift > 31) d->dma->HIFCR = (flag << (d->flagsShift - 32)); else d->dma->LIFCR = (flag << d->flagsShift)
 136 #define DMA_GET_FLAG_STATUS(d, flag) (d->flagsShift > 31 ? d->dma->HISR & (flag << (d->flagsShift - 32)): d->dma->LISR & (flag << d->flagsShift))
 137
 138 #define DMA_IT_TCIF         ((uint32_t)0x00000020)
 139 #define DMA_IT_HTIF         ((uint32_t)0x00000010)
 140 #define DMA_IT_TEIF         ((uint32_t)0x00000008)
 141 #define DMA_IT_DMEIF        ((uint32_t)0x00000004)
 142 #define DMA_IT_FEIF         ((uint32_t)0x00000001)
 143
 144 void dmaMuxEnable(dmaIdentifier_e identifier, uint32_t dmaMuxId);
 145
 146 #else
 147
 148 #if defined(STM32G4)
 149
 150 typedef enum {
 151     DMA_NONE = 0,
 152     DMA1_CH1_HANDLER = 1,
 153     DMA1_CH2_HANDLER,
 154     DMA1_CH3_HANDLER,
 155     DMA1_CH4_HANDLER,
 156     DMA1_CH5_HANDLER,
 157     DMA1_CH6_HANDLER,
 158     DMA1_CH7_HANDLER,
 159     DMA1_CH8_HANDLER,
 160     DMA2_CH1_HANDLER,
 161     DMA2_CH2_HANDLER,
 162     DMA2_CH3_HANDLER,
 163     DMA2_CH4_HANDLER,
 164     DMA2_CH5_HANDLER,
 165     DMA2_CH6_HANDLER,
 166     DMA2_CH7_HANDLER,
 167     DMA2_CH8_HANDLER,
 168     DMA_LAST_HANDLER = DMA2_CH8_HANDLER
 169 } dmaIdentifier_e;
 170
 171 #define DMA_DEVICE_NO(x)    ((((x)-1) / 8) + 1)
 172 #define DMA_DEVICE_INDEX(x) ((((x)-1) % 8) + 1)
 173
 174 uint32_t dmaGetChannel(const uint8_t channel);
 175
 176 #else // !STM32G4
 177
 178 typedef enum {
 179     DMA_NONE = 0,
 180     DMA1_CH1_HANDLER = 1,
 181     DMA1_CH2_HANDLER,
 182     DMA1_CH3_HANDLER,
 183     DMA1_CH4_HANDLER,
 184     DMA1_CH5_HANDLER,
 185     DMA1_CH6_HANDLER,
 186     DMA1_CH7_HANDLER,
 187     DMA_LAST_HANDLER = DMA1_CH7_HANDLER
 188 } dmaIdentifier_e;
 189
 190 #define DMA_DEVICE_NO(x)    ((((x)-1) / 7) + 1)
 191 #define DMA_DEVICE_INDEX(x) ((((x)-1) % 7) + 1)
 192
 193 #endif // STM32G4
 194
 195 #define DMA_OUTPUT_INDEX    0
 196 #define DMA_OUTPUT_STRING   "DMA%d Channel %d:"
 197 #define DMA_INPUT_STRING    "DMA%d_CH%d"
 198
 199 #define DEFINE_DMA_CHANNEL(d, c, f) { \
 200     .dma = d, \
 201     .ref = (dmaResource_t *)d ## _Channel ## c, \
 202     .irqHandlerCallback = NULL, \
 203     .flagsShift = f, \
 204     .irqN = d ## _Channel ## c ## _IRQn, \
 205     .userParam = 0, \
 206     .owner.owner = 0, \
 207     .owner.resourceIndex = 0 \
 208     }
 209
 210 #define DMA_HANDLER_CODE
 211
 212 #define DEFINE_DMA_IRQ_HANDLER(d, c, i) DMA_HANDLER_CODE void DMA ## d ## _Channel ## c ## _IRQHandler(void) {\
 213                                                                         const uint8_t index = DMA_IDENTIFIER_TO_INDEX(i); \
 214                                                                         dmaCallbackHandlerFuncPtr handler = dmaDescriptors[index].irqHandlerCallback; \
 215                                                                         if (handler) \
 216                                                                             handler(&dmaDescriptors[index]); \
 217                                                                     }
 218
 219 #define DMA_CLEAR_FLAG(d, flag) d->dma->IFCR = (flag << d->flagsShift)
 220 #define DMA_GET_FLAG_STATUS(d, flag) (d->dma->ISR & (flag << d->flagsShift))
 221
 222 #define DMA_IT_TCIF         ((uint32_t)0x00000002)
 223 #define DMA_IT_HTIF         ((uint32_t)0x00000004)
 224 #define DMA_IT_TEIF         ((uint32_t)0x00000008)
 225 #endif
 226
 227 // Macros to avoid direct register and register bit access
 228
 229 #if defined(STM32F4) || defined(STM32F7)
 230 #define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CR & DMA_SxCR_EN)
 231 #define REG_NDTR NDTR
 232 #elif defined(STM32H7)
 233 // For H7, we have to differenciate DMA1/2 and BDMA for access to the control register.
 234 // HAL library has a macro for this, but it is extremely inefficient in that it compares
 235 // the address against all possible values.
 236 // Here, we just compare the address against regions of memory.
 237 #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ)
 238 // For H7A3, if it's lower than CD_AHB2PERIPH_BASE, then it's DMA1/2 and it's stream based.
 239 // If not, it's BDMA and it's channel based.
 240 #define IS_DMA_ENABLED(reg) \
 241     ((uint32_t)(reg) < CD_AHB2PERIPH_BASE) ? \
 242         (((DMA_Stream_TypeDef *)(reg))->CR & DMA_SxCR_EN) : \
 243         (((BDMA_Channel_TypeDef *)(reg))->CCR & BDMA_CCR_EN)
 244 #else
 245 // For H743 and H750, if it's not in D3 peripheral area, then it's DMA1/2 and it's stream based.
 246 // If not, it's BDMA and it's channel based.
 247 #define IS_DMA_ENABLED(reg) \
 248     ((uint32_t)(reg) < D3_AHB1PERIPH_BASE) ? \
 249         (((DMA_Stream_TypeDef *)(reg))->CR & DMA_SxCR_EN) : \
 250         (((BDMA_Channel_TypeDef *)(reg))->CCR & BDMA_CCR_EN)
 251 #endif
 252 #elif defined(STM32G4)
 253 #define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CCR & DMA_CCR_EN)
 254 // Missing __HAL_DMA_SET_COUNTER in FW library V1.0.0
 255 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNDTR = (uint16_t)(__COUNTER__))
 256 #elif defined(AT32F4)
 257 #define DMA_CCR_EN 1
 258 #define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->ctrl_bit.chen & DMA_CCR_EN)
 259 #elif defined(APM32F4)
 260 #define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->SCFG & DMA_SCFGx_EN)
 261 #define REG_NDTR NDATA
 262 #else
 263 #define IS_DMA_ENABLED(reg) (((DMA_ARCH_TYPE *)(reg))->CCR & DMA_CCR_EN)
 264 #define DMAx_SetMemoryAddress(reg, address) ((DMA_ARCH_TYPE *)(reg))->CMAR = (uint32_t)&s->port.txBuffer[s->port.txBufferTail]
 265 #endif
 266
 267 dmaIdentifier_e dmaAllocate(dmaIdentifier_e identifier, resourceOwner_e owner, uint8_t resourceIndex);
 268 void dmaEnable(dmaIdentifier_e identifier);
 269 void dmaSetHandler(dmaIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam);
 270
 271 dmaIdentifier_e dmaGetIdentifier(const dmaResource_t* channel);
 272 const resourceOwner_t *dmaGetOwner(dmaIdentifier_e identifier);
 273 dmaChannelDescriptor_t* dmaGetDescriptorByIdentifier(const dmaIdentifier_e identifier);
 274 uint32_t dmaGetChannel(const uint8_t channel);
 275
 276 //
 277 // Wrapper macros to cast dmaResource_t back into DMA_ARCH_TYPE
 278 //
 279
 280 #if defined(USE_HAL_DRIVER)
 281
 282 // We actually need these LL case only
 283
 284 #define xLL_EX_DMA_DeInit(dmaResource) LL_EX_DMA_DeInit((DMA_ARCH_TYPE *)(dmaResource))
 285 #define xLL_EX_DMA_Init(dmaResource, initstruct) LL_EX_DMA_Init((DMA_ARCH_TYPE *)(dmaResource), initstruct)
 286 #define xLL_EX_DMA_DisableResource(dmaResource) LL_EX_DMA_DisableResource((DMA_ARCH_TYPE *)(dmaResource))
 287 #define xLL_EX_DMA_EnableResource(dmaResource) LL_EX_DMA_EnableResource((DMA_ARCH_TYPE *)(dmaResource))
 288 #define xLL_EX_DMA_GetDataLength(dmaResource) LL_EX_DMA_GetDataLength((DMA_ARCH_TYPE *)(dmaResource))
 289 #define xLL_EX_DMA_SetDataLength(dmaResource, length) LL_EX_DMA_SetDataLength((DMA_ARCH_TYPE *)(dmaResource), length)
 290 #define xLL_EX_DMA_EnableIT_TC(dmaResource) LL_EX_DMA_EnableIT_TC((DMA_ARCH_TYPE *)(dmaResource))
 291
 292 #elif defined(USE_ATBSP_DRIVER)
 293
 294 #else
 295
 296 #define xDMA_Init(dmaResource, initStruct) DMA_Init((DMA_ARCH_TYPE *)(dmaResource), initStruct)
 297 #define xDMA_DeInit(dmaResource) DMA_DeInit((DMA_ARCH_TYPE *)(dmaResource))
 298 #define xDMA_Cmd(dmaResource, newState) DMA_Cmd((DMA_ARCH_TYPE *)(dmaResource), newState)
 299 #define xDMA_ITConfig(dmaResource, flags, newState) DMA_ITConfig((DMA_ARCH_TYPE *)(dmaResource), flags, newState)
 300 #define xDMA_GetCurrDataCounter(dmaResource) DMA_GetCurrDataCounter((DMA_ARCH_TYPE *)(dmaResource))
 301 #define xDMA_SetCurrDataCounter(dmaResource, count) DMA_SetCurrDataCounter((DMA_ARCH_TYPE *)(dmaResource), count)
 302 #define xDMA_GetFlagStatus(dmaResource, flags) DMA_GetFlagStatus((DMA_ARCH_TYPE *)(dmaResource), flags)
 303 #define xDMA_ClearFlag(dmaResource, flags) DMA_ClearFlag((DMA_ARCH_TYPE *)(dmaResource), flags)
 304 #define xDMA_MemoryTargetConfig(dmaResource, address, target) DMA_MemoryTargetConfig((DMA_ARCH_TYPE *)(dmaResource), address, target)
 305
 306 #endif