STM32F103xB HAL User Manual: STM32F1xx HAL Drivers

STM32F103xB HAL User Manual
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STM32F1xx HAL Drivers

HAL Drivers User Manual

This document contains the User Manual (UM) of the STM32F103xB HAL (Hardware Abstraction Layer) drivers.

Document tabsheets description:

  • "Modules" : List the different modules.
  • "Files" : List all the files and globals.
  • "Directories" : Firmware Directory hierarchy.
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC

  • Data Structures
  • Files
  • Directories
Modules
ADC
STM32F1xx_LL_Driver

Modules

ADC Private Constants
ADC Private Macros
ADC Exported Init structure
ADC Exported Constants
ADC Exported Macros
ADC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for ADC registers.

Register | Bit | Function
CR1 | AWD1CH | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | AWD1EN | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | AWD1SGL | LL_ADC_GetAnalogWDMonitChannels
 |  | LL_ADC_SetAnalogWDMonitChannels
 | AWDIE | LL_ADC_EnableIT_AWD1
 | DISCEN | LL_ADC_INJ_SetSequencerDiscont
 |  | LL_ADC_REG_GetSequencerDiscont
 |  | LL_ADC_REG_SetSequencerDiscont
 | DISCNUM | LL_ADC_REG_GetSequencerDiscont
 |  | LL_ADC_REG_SetSequencerDiscont
 | DUALMOD | LL_ADC_GetMultimode
 |  | LL_ADC_SetMultimode
 | EOCIE | LL_ADC_DisableIT_EOS
 |  | LL_ADC_EnableIT_EOS
 |  | LL_ADC_IsEnabledIT_EOS
 | JAUTO | LL_ADC_INJ_GetTrigAuto
 |  | LL_ADC_INJ_SetTrigAuto
 | JEOCIE | LL_ADC_EnableIT_JEOS
 | SCAN | LL_ADC_GetSequencersScanMode
 |  | LL_ADC_SetSequencersScanMode
CR2 | ADON | LL_ADC_Disable
 |  | LL_ADC_Enable
 |  | LL_ADC_IsEnabled
 | ALIGN | LL_ADC_SetDataAlignment
 | CAL | LL_ADC_IsCalibrationOnGoing
 |  | LL_ADC_StartCalibration
 | CONT | LL_ADC_REG_GetContinuousMode
 |  | LL_ADC_REG_SetContinuousMode
 | DMA | LL_ADC_REG_GetDMATransfer
 |  | LL_ADC_REG_SetDMATransfer
 | EXTEN | LL_ADC_REG_StartConversionExtTrig
 | EXTSEL | LL_ADC_REG_GetTriggerSource
 |  | LL_ADC_REG_IsTriggerSourceSWStart
 |  | LL_ADC_REG_SetTriggerSource
 |  | LL_ADC_REG_StopConversionExtTrig
 | JEXTEN | LL_ADC_INJ_StartConversionExtTrig
 | JEXTSEL | LL_ADC_INJ_GetTriggerSource
 |  | LL_ADC_INJ_IsTriggerSourceSWStart
 |  | LL_ADC_INJ_SetTriggerSource
 |  | LL_ADC_INJ_StopConversionExtTrig
 | JSWSTART | LL_ADC_INJ_StartConversionSWStart
 | SWSTART | LL_ADC_REG_StartConversionSWStart
 | TSVREFE | LL_ADC_GetCommonPathInternalCh
 |  | LL_ADC_SetCommonPathInternalCh
DR | ADC2DATA | LL_ADC_REG_ReadMultiConversionData32
 | DATA | LL_ADC_DMA_GetRegAddr
 |  | LL_ADC_REG_ReadMultiConversionData32
 | RDATA | LL_ADC_REG_ReadConversionData12
 |  | LL_ADC_REG_ReadConversionData32
HTR | HT | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
JDR1 | JDATA | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
JDR2 | JDATA | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
JDR3 | JDATA | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
JDR4 | JDATA | LL_ADC_INJ_ReadConversionData12
 |  | LL_ADC_INJ_ReadConversionData32
JOFR1 | JOFFSET1 | LL_ADC_INJ_GetOffset
 |  | LL_ADC_INJ_SetOffset
JOFR2 | JOFFSET2 | LL_ADC_INJ_GetOffset
 |  | LL_ADC_INJ_SetOffset
JOFR3 | JOFFSET3 | LL_ADC_INJ_GetOffset
 |  | LL_ADC_INJ_SetOffset
JOFR4 | JOFFSET4 | LL_ADC_INJ_GetOffset
 |  | LL_ADC_INJ_SetOffset
JSQR | JL | LL_ADC_INJ_GetSequencerLength
 |  | LL_ADC_INJ_SetSequencerLength
 | JSQ1 | LL_ADC_INJ_SetSequencerRanks
 | JSQ2 | LL_ADC_INJ_SetSequencerRanks
 | JSQ3 | LL_ADC_INJ_SetSequencerRanks
 | JSQ4 | LL_ADC_INJ_SetSequencerRanks
LTR | LT | LL_ADC_GetAnalogWDThresholds
 |  | LL_ADC_SetAnalogWDThresholds
SMPR1 | SMP10 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP11 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP12 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP13 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP14 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP15 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP16 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP17 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
SMPR2 | SMP0 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP1 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP2 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP3 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP4 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP5 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP6 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP7 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP8 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
 | SMP9 | LL_ADC_GetChannelSamplingTime
 |  | LL_ADC_SetChannelSamplingTime
SQR1 | L | LL_ADC_REG_SetSequencerLength
 | SQ13 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ14 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ15 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ16 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SQR2 | SQ10 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ11 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ12 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ7 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ8 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ9 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SQR3 | SQ1 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ2 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ3 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ4 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ5 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
 | SQ6 | LL_ADC_REG_GetSequencerRanks
 |  | LL_ADC_REG_SetSequencerRanks
SR | AWD | LL_ADC_ClearFlag_AWD1
 |  | LL_ADC_IsActiveFlag_AWD1
 |  | LL_ADC_IsActiveFlag_MST_AWD1
 |  | LL_ADC_IsActiveFlag_SLV_AWD1
 | EOC | LL_ADC_ClearFlag_EOS
 |  | LL_ADC_IsActiveFlag_EOS
 |  | LL_ADC_IsActiveFlag_MST_EOS
 |  | LL_ADC_IsActiveFlag_SLV_EOS
 | JEOC | LL_ADC_ClearFlag_JEOS
 |  | LL_ADC_IsActiveFlag_JEOS
 |  | LL_ADC_IsActiveFlag_MST_JEOS
 |  | LL_ADC_IsActiveFlag_SLV_JEOS
Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Private Constants

Defines
ADC Private Constants
ADC

Defines

#define | ADC_SQR1_REGOFFSET 0x00000000U
#define | ADC_SQR2_REGOFFSET 0x00000100U
#define | ADC_SQR3_REGOFFSET 0x00000200U
#define | ADC_SQR4_REGOFFSET 0x00000300U
#define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
#define | ADC_JDR1_REGOFFSET 0x00000000U
#define | ADC_JDR2_REGOFFSET 0x00000100U
#define | ADC_JDR3_REGOFFSET 0x00000200U
#define | ADC_JDR4_REGOFFSET 0x00000300U
#define | ADC_JOFR1_REGOFFSET 0x00000000U
#define | ADC_JOFR2_REGOFFSET 0x00001000U
#define | ADC_JOFR3_REGOFFSET 0x00002000U
#define | ADC_JOFR4_REGOFFSET 0x00003000U
#define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define | ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
#define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
#define | ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | ADC_SMPR1_REGOFFSET 0x00000000U
#define | ADC_SMPR2_REGOFFSET 0x02000000U
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
#define | ADC_CHANNEL_0_NUMBER 0x00000000U
#define | ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
#define | ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
#define | ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
#define | ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
#define | ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
#define | ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
#define | ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
#define | ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
#define | ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
#define | ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
#define | ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
#define | ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
#define | ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
#define | ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
#define | ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
#define | ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
#define | ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
#define | ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
#define | ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
#define | ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
#define | ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
#define | ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
#define | ADC_AWD_CR1_REGOFFSET 0x00000000U
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
#define | ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
#define | ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
#define | ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */

Define Documentation

#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

Definition at line 206 of file stm32f1xx_ll_adc.h.

#define ADC_AWD_CR1_REGOFFSET 0x00000000U

Definition at line 202 of file stm32f1xx_ll_adc.h.

#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)

Definition at line 207 of file stm32f1xx_ll_adc.h.

#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)

Definition at line 204 of file stm32f1xx_ll_adc.h.

#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U

Definition at line 210 of file stm32f1xx_ll_adc.h.

#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U

Definition at line 211 of file stm32f1xx_ll_adc.h.

#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)

Definition at line 212 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_0_NUMBER 0x00000000U

Definition at line 154 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */

Definition at line 175 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )

Definition at line 164 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */

Definition at line 185 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

Definition at line 165 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */

Definition at line 186 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )

Definition at line 166 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */

Definition at line 187 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)

Definition at line 167 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */

Definition at line 188 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )

Definition at line 168 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */

Definition at line 189 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

Definition at line 169 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */

Definition at line 190 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )

Definition at line 170 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */

Definition at line 191 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)

Definition at line 171 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */

Definition at line 192 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)

Definition at line 155 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */

Definition at line 176 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )

Definition at line 156 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */

Definition at line 177 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

Definition at line 157 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */

Definition at line 178 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )

Definition at line 158 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */

Definition at line 179 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)

Definition at line 159 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */

Definition at line 180 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )

Definition at line 160 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */

Definition at line 181 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

Definition at line 161 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */

Definition at line 182 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )

Definition at line 162 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */

Definition at line 183 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)

Definition at line 163 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */

Definition at line 184 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */

Definition at line 139 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */

Definition at line 140 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)

Definition at line 141 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Definition at line 134 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */

Definition at line 133 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)

Definition at line 132 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetSequencerRanks(), LL_ADC_INJ_SetSequencerRanks(), LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */

Definition at line 136 of file stm32f1xx_ll_adc.h.

#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

Definition at line 147 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U

Definition at line 149 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), and LL_ADC_SetChannelSamplingTime().

#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */

Definition at line 150 of file stm32f1xx_ll_adc.h.

#define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */

Definition at line 215 of file stm32f1xx_ll_adc.h.

#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

Definition at line 121 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_ReadConversionData12(), and LL_ADC_INJ_ReadConversionData32().

#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)

Definition at line 122 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_GetOffset(), and LL_ADC_INJ_SetOffset().

#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 123 of file stm32f1xx_ll_adc.h.

#define ADC_JDR1_REGOFFSET 0x00000000U

Definition at line 109 of file stm32f1xx_ll_adc.h.

#define ADC_JDR2_REGOFFSET 0x00000100U

Definition at line 110 of file stm32f1xx_ll_adc.h.

#define ADC_JDR3_REGOFFSET 0x00000200U

Definition at line 111 of file stm32f1xx_ll_adc.h.

#define ADC_JDR4_REGOFFSET 0x00000300U

Definition at line 112 of file stm32f1xx_ll_adc.h.

#define ADC_JOFR1_REGOFFSET 0x00000000U

Definition at line 116 of file stm32f1xx_ll_adc.h.

#define ADC_JOFR2_REGOFFSET 0x00001000U

Definition at line 117 of file stm32f1xx_ll_adc.h.

#define ADC_JOFR3_REGOFFSET 0x00002000U

Definition at line 118 of file stm32f1xx_ll_adc.h.

#define ADC_JOFR4_REGOFFSET 0x00003000U

Definition at line 119 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */

Definition at line 93 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */

Definition at line 94 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */

Definition at line 95 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */

Definition at line 96 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */

Definition at line 97 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */

Definition at line 98 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */

Definition at line 99 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */

Definition at line 84 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */

Definition at line 85 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */

Definition at line 86 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */

Definition at line 87 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */

Definition at line 88 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */

Definition at line 89 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */

Definition at line 90 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */

Definition at line 91 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */

Definition at line 92 of file stm32f1xx_ll_adc.h.

#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

Definition at line 80 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

Definition at line 79 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_GetSequencerRanks(), and LL_ADC_REG_SetSequencerRanks().

#define ADC_SMPR1_REGOFFSET 0x00000000U

Definition at line 145 of file stm32f1xx_ll_adc.h.

#define ADC_SMPR2_REGOFFSET 0x02000000U

Definition at line 146 of file stm32f1xx_ll_adc.h.

#define ADC_SQR1_REGOFFSET 0x00000000U

Definition at line 74 of file stm32f1xx_ll_adc.h.

#define ADC_SQR2_REGOFFSET 0x00000100U

Definition at line 75 of file stm32f1xx_ll_adc.h.

#define ADC_SQR3_REGOFFSET 0x00000200U

Definition at line 76 of file stm32f1xx_ll_adc.h.

#define ADC_SQR4_REGOFFSET 0x00000300U

Definition at line 77 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Private Macros

Defines
ADC Private Macros
ADC

Defines

#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__)
#define | IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)
#define | IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)
#define | __ADC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Define Documentation

#define __ADC_MASK_SHIFT | ( | __BITS__,
 |  | __MASK__
 | ) | (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))

Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).

Parameters:
__BITS__ | Bits in register 32 bits
__MASK__ | Mask in register 32 bits
Return values:
Bits in register 32 bits

Definition at line 235 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_GetChannelSamplingTime(), LL_ADC_INJ_GetOffset(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_SetOffset(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), and LL_ADC_SetChannelSamplingTime().

#define __ADC_PTR_REG_OFFSET | ( | __REG__,
 |  | __REG_OFFFSET__
 | ) | ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))

Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.

Parameters:
__REG__ | Register basis from which the offset is applied.
__REG_OFFFSET__ | Offset to be applied (unit: number of registers).
Return values:
Pointer to register address

Definition at line 246 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_GetAnalogWDThresholds(), LL_ADC_GetChannelSamplingTime(), LL_ADC_INJ_GetOffset(), LL_ADC_INJ_ReadConversionData12(), LL_ADC_INJ_ReadConversionData32(), LL_ADC_INJ_SetOffset(), LL_ADC_IsActiveFlag_SLV_AWD1(), LL_ADC_IsActiveFlag_SLV_EOS(), LL_ADC_IsActiveFlag_SLV_JEOS(), LL_ADC_REG_GetSequencerRanks(), LL_ADC_REG_SetSequencerRanks(), LL_ADC_SetAnalogWDThresholds(), and LL_ADC_SetChannelSamplingTime().

#define IS_LL_ADC_DATA_ALIGN ( __DATA_ALIGN__ )
Value:
(   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
  )

Definition at line 72 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE ( __INJ_SEQ_DISCONT_MODE__ )
Value:
(   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
  )

Definition at line 244 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH ( __INJ_SEQ_SCAN_LENGTH__ )
Value:
(   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
  )

Definition at line 237 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_AUTO ( __INJ_TRIG_AUTO__ )
Value:
(   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
  )

Definition at line 232 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_INJ_TRIG_SOURCE ( __INJ_TRIG_SOURCE__ )
Value:
(   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
  )

Definition at line 220 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_INJ_Init().

#define IS_LL_ADC_MULTI_MASTER_SLAVE ( __MULTI_MASTER_SLAVE__ )
Value:
(   ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                        \
   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
  )

Definition at line 265 of file stm32f1xx_ll_adc.c.

#define IS_LL_ADC_MULTI_MODE ( __MULTI_MODE__ )
Value:
(   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST)                  \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW)                  \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM)              \
   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM)              \
  )

Definition at line 252 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_CommonInit().

#define IS_LL_ADC_REG_CONTINUOUS_MODE ( __REG_CONTINUOUS_MODE__ )
Value:
(   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
  )

Definition at line 139 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_DMA_TRANSFER ( __REG_DMA_TRANSFER__ )
Value:
(   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
  )

Definition at line 144 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE ( __REG_SEQ_DISCONT_MODE__ )
Value:
(   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
  )

Definition at line 168 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH ( __REG_SEQ_SCAN_LENGTH__ )
Value:
(   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
  )

Definition at line 149 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_REG_TRIG_SOURCE ( __REG_TRIG_SOURCE__ )
Value:
(   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
  )

Definition at line 127 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_REG_Init().

#define IS_LL_ADC_SCAN_SELECTION ( __SCAN_SELECTION__ )
Value:
(   ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE)                        \
   || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE)                         \
  )

Definition at line 77 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_Init().

#define IS_LL_ADC_SEQ_SCAN_MODE ( __SEQ_SCAN_MODE__ )
Value:
(   ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE)                             \
   || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE)                              \
  )

Definition at line 82 of file stm32f1xx_ll_adc.c.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_ADC_CommonInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_CommonInitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...

#include <stm32f1xx_ll_adc.h>

Data Fields

uint32_t Multimode

Detailed Description

Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance).

Note:
The setting of these parameters by function LL_ADC_CommonInit() is conditioned to ADC instances state (all ADC instances sharing the same ADC common instance): All ADC instances sharing the same ADC common instance must be disabled.

Definition at line 270 of file stm32f1xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_CommonInitTypeDef::Multimode

Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). This parameter can be a value of Multimode - Mode

This feature can be modified afterwards using unitary function LL_ADC_SetMultimode().

Definition at line 272 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_adc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC instance. More...

#include <stm32f1xx_ll_adc.h>

Data Fields

uint32_t | DataAlignment
uint32_t | SequencersScanMode

Detailed Description

Structure definition of some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 families). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 297 of file stm32f1xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_InitTypeDef::DataAlignment

Set ADC conversion data alignment. This parameter can be a value of ADC instance - Data alignment

This feature can be modified afterwards using unitary function LL_ADC_SetDataAlignment().

Definition at line 299 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

uint32_t LL_ADC_InitTypeDef::SequencersScanMode

Set ADC scan selection. This parameter can be a value of ADC instance - Scan selection

This feature can be modified afterwards using unitary function LL_ADC_SetSequencersScanMode().

Definition at line 304 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_Init(), and LL_ADC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_adc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_ADC_REG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_REG_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group regular. More...

#include <stm32f1xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | ContinuousMode
uint32_t | DMATransfer

Detailed Description

Structure definition of some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_REG_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 330 of file stm32f1xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_REG_InitTypeDef::ContinuousMode

Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of ADC group regular - Continuous mode Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

This feature can be modified afterwards using unitary function LL_ADC_REG_SetContinuousMode().

Definition at line 352 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::DMATransfer

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of ADC group regular - DMA transfer of ADC conversion data

This feature can be modified afterwards using unitary function LL_ADC_REG_SetDMATransfer().

Definition at line 358 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerDiscont

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group regular - Sequencer discontinuous mode

Note:
This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerDiscont().

Definition at line 345 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::SequencerLength

Set ADC group regular sequencer length. This parameter can be a value of ADC group regular - Sequencer scan length

Note:
This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').

This feature can be modified afterwards using unitary function LL_ADC_REG_SetSequencerLength().

Definition at line 339 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

uint32_t LL_ADC_REG_InitTypeDef::TriggerSource

Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). This parameter can be a value of ADC group regular - Trigger source

Note:
On this STM32 serie, external trigger is set with trigger polarity: rising edge (only trigger polarity available on this STM32 serie).

This feature can be modified afterwards using unitary function LL_ADC_REG_SetTriggerSource().

Definition at line 332 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_adc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_ADC_INJ_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_ADC_INJ_InitTypeDef Struct Reference
ADC Exported Init structure

Structure definition of some features of ADC group injected. More...

#include <stm32f1xx_ll_adc.h>

Data Fields

uint32_t | TriggerSource
uint32_t | SequencerLength
uint32_t | SequencerDiscont
uint32_t | TrigAuto

Detailed Description

Structure definition of some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_INJ_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.

Definition at line 384 of file stm32f1xx_ll_adc.h.

Field Documentation

uint32_t LL_ADC_INJ_InitTypeDef::SequencerDiscont

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of ADC group injected - Sequencer discontinuous mode

Note:
This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more).

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerDiscont().

Definition at line 399 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::SequencerLength

Set ADC group injected sequencer length. This parameter can be a value of ADC group injected - Sequencer scan length

Note:
This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetSequencerLength().

Definition at line 393 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TrigAuto

Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of ADC group injected - Automatic trigger mode Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTrigAuto().

Definition at line 406 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

uint32_t LL_ADC_INJ_InitTypeDef::TriggerSource

Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). This parameter can be a value of ADC group injected - Trigger source

Note:
On this STM32 serie, external trigger is set with trigger polarity: rising edge (only trigger polarity available on this STM32 serie).

This feature can be modified afterwards using unitary function LL_ADC_INJ_SetTriggerSource().

Definition at line 386 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_adc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC flags

Defines
ADC flags
ADC Exported Constants

Flags defines which can be used with LL_ADC_ReadReg function. More...

Defines

#define | LL_ADC_FLAG_STRT ADC_SR_STRT
#define | LL_ADC_FLAG_EOS ADC_SR_EOC
#define | LL_ADC_FLAG_JSTRT ADC_SR_JSTRT
#define | LL_ADC_FLAG_JEOS ADC_SR_JEOC
#define | LL_ADC_FLAG_AWD1 ADC_SR_AWD
#define | LL_ADC_FLAG_EOS_MST ADC_SR_EOC
#define | LL_ADC_FLAG_EOS_SLV ADC_SR_EOC
#define | LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC
#define | LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC
#define | LL_ADC_FLAG_AWD1_MST ADC_SR_AWD
#define | LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD

Detailed Description

Flags defines which can be used with LL_ADC_ReadReg function.

Define Documentation

#define LL_ADC_FLAG_AWD1 ADC_SR_AWD

ADC flag ADC analog watchdog 1

Definition at line 432 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_AWD1(), LL_ADC_DeInit(), LL_ADC_IsActiveFlag_AWD1(), LL_ADC_IsActiveFlag_MST_AWD1(), and LL_ADC_IsActiveFlag_SLV_AWD1().

#define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD

ADC flag ADC multimode master analog watchdog 1 of the ADC master

Definition at line 438 of file stm32f1xx_ll_adc.h.

#define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD

ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2)

Definition at line 439 of file stm32f1xx_ll_adc.h.

#define LL_ADC_FLAG_EOS ADC_SR_EOC

ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families)

Definition at line 429 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_EOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_EOS().

#define LL_ADC_FLAG_EOS_MST ADC_SR_EOC

ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families)

Definition at line 434 of file stm32f1xx_ll_adc.h.

#define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC

ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2)

Definition at line 435 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_EOS().

#define LL_ADC_FLAG_JEOS ADC_SR_JEOC

ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families)

Definition at line 431 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_ClearFlag_JEOS(), LL_ADC_DeInit(), and LL_ADC_IsActiveFlag_JEOS().

#define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC

ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families)

Definition at line 436 of file stm32f1xx_ll_adc.h.

#define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC

ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2)

Definition at line 437 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_IsActiveFlag_SLV_JEOS().

#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT

ADC flag ADC group injected conversion start

Definition at line 430 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

#define LL_ADC_FLAG_STRT ADC_SR_STRT

ADC flag ADC group regular conversion start

Definition at line 428 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC interruptions for configuration (interruption enable or disable)

Defines
ADC interruptions for configuration (interruption enable or disable)
ADC Exported Constants

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions. More...

Defines

#define | LL_ADC_IT_EOS ADC_CR1_EOCIE
#define | LL_ADC_IT_JEOS ADC_CR1_JEOCIE
#define | LL_ADC_IT_AWD1 ADC_CR1_AWDIE

Detailed Description

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

Define Documentation

#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE

ADC interruption ADC analog watchdog 1

Definition at line 451 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DisableIT_AWD1(), LL_ADC_EnableIT_AWD1(), and LL_ADC_IsEnabledIT_AWD1().

#define LL_ADC_IT_EOS ADC_CR1_EOCIE

ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families)

Definition at line 449 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_IsEnabledIT_EOS().

#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE

ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families)

Definition at line 450 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DisableIT_JEOS(), LL_ADC_EnableIT_JEOS(), and LL_ADC_IsEnabledIT_JEOS().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC registers compliant with specific purpose

Defines
ADC registers compliant with specific purpose
ADC Exported Constants

Defines

#define | LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define | LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */

Define Documentation

#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

Definition at line 462 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DMA_GetRegAddr().

#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */

Definition at line 464 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC common - Measurement path to internal channels

Defines
ADC common - Measurement path to internal channels
ADC Exported Constants

Defines

#define | LL_ADC_PATH_INTERNAL_NONE 0x00000000U
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE)

Define Documentation

#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U

ADC measurement pathes all disabled

Definition at line 478 of file stm32f1xx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE)

ADC measurement path to internal channel temperature sensor

Definition at line 480 of file stm32f1xx_ll_adc.h.

#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE)

ADC measurement path to internal channel VrefInt

Definition at line 479 of file stm32f1xx_ll_adc.h.

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STM32F103xB HAL User Manual: ADC instance - Resolution

Defines
ADC instance - Resolution
ADC Exported Constants

Defines

#define LL_ADC_RESOLUTION_12B 0x00000000U

Define Documentation

#define LL_ADC_RESOLUTION_12B 0x00000000U

ADC resolution 12 bits

Definition at line 488 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC instance - Data alignment

Defines
ADC instance - Data alignment
ADC Exported Constants

Defines

#define | LL_ADC_DATA_ALIGN_RIGHT 0x00000000U
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN)

Define Documentation

#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN)

ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)

Definition at line 497 of file stm32f1xx_ll_adc.h.

#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U

ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)

Definition at line 496 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC instance - Scan selection

Defines
ADC instance - Scan selection
ADC Exported Constants

Defines

#define | LL_ADC_SEQ_SCAN_DISABLE 0x00000000U
#define | LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN)

Define Documentation

#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U

ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.

Definition at line 505 of file stm32f1xx_ll_adc.h.

#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN)

ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...).

Definition at line 506 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_StructInit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC instance - Groups

Defines
ADC instance - Groups
ADC Exported Constants

Defines

#define | LL_ADC_GROUP_REGULAR 0x00000001U
#define | LL_ADC_GROUP_INJECTED 0x00000002U
#define | LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U

Define Documentation

#define LL_ADC_GROUP_INJECTED 0x00000002U

ADC group injected (not available on all STM32 devices)

Definition at line 515 of file stm32f1xx_ll_adc.h.

#define LL_ADC_GROUP_REGULAR 0x00000001U

ADC group regular (available on all STM32 devices)

Definition at line 514 of file stm32f1xx_ll_adc.h.

#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U

ADC both groups regular and injected

Definition at line 516 of file stm32f1xx_ll_adc.h.

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STM32F103xB HAL User Manual: ADC instance - Channel number

Defines
ADC instance - Channel number
ADC Exported Constants

Defines

#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP)
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP)
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP)
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP)
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP)
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP)
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP)
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP)
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP)
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP)
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)

Define Documentation

#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN0

Definition at line 524 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN1

Definition at line 525 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN10

Definition at line 534 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN11

Definition at line 535 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN12

Definition at line 536 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN13

Definition at line 537 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN14

Definition at line 538 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN15

Definition at line 539 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN16

Definition at line 540 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN17

Definition at line 541 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN2

Definition at line 526 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN3

Definition at line 527 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN4

Definition at line 528 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN5

Definition at line 529 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN6

Definition at line 530 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN7

Definition at line 531 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN8

Definition at line 532 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP)

ADC external channel (channel connected to GPIO pin) ADCx_IN9

Definition at line 533 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to Temperature sensor.

Definition at line 543 of file stm32f1xx_ll_adc.h.

#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)

ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1.

Definition at line 542 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC group regular - Trigger source

Defines
ADC group regular - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2)
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)

Define Documentation

#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)

ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting).

Definition at line 560 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U

ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 555 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0)

ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 556 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1)

ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 553 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)

ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 557 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2)

ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 558 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)

ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 559 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)

ADC group regular conversion trigger internal: SW start.

Definition at line 552 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_REG_IsTriggerSourceSWStart(), and LL_ADC_REG_StructInit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC group regular - Trigger edge

Defines
ADC group regular - Trigger edge
ADC Exported Constants

Defines

#define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG

Define Documentation

#define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG

ADC group regular conversion trigger polarity set to rising edge

Definition at line 585 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC group regular - Continuous mode

Defines
ADC group regular - Continuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_CONV_SINGLE 0x00000000U
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT)

Define Documentation

#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT)

ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically

Definition at line 594 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_CONV_SINGLE 0x00000000U

ADC conversions are performed in single mode: one conversion per trigger

Definition at line 593 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC group regular - DMA transfer of ADC conversion data

Defines
ADC group regular - DMA transfer of ADC conversion data
ADC Exported Constants

Defines

#define | LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA)

Define Documentation

#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U

ADC conversions are not transferred by DMA

Definition at line 602 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_StructInit().

#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA)

ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.

Definition at line 603 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC group regular - Sequencer scan length

Defines
ADC group regular - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

Define Documentation

#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U

ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 611 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 10 ranks in the sequence

Definition at line 620 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 11 ranks in the sequence

Definition at line 621 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 12 ranks in the sequence

Definition at line 622 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )

ADC group regular sequencer enable with 13 ranks in the sequence

Definition at line 623 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 14 ranks in the sequence

Definition at line 624 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 15 ranks in the sequence

Definition at line 625 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 16 ranks in the sequence

Definition at line 626 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)

ADC group regular sequencer enable with 2 ranks in the sequence

Definition at line 612 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )

ADC group regular sequencer enable with 3 ranks in the sequence

Definition at line 613 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 4 ranks in the sequence

Definition at line 614 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )

ADC group regular sequencer enable with 5 ranks in the sequence

Definition at line 615 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 6 ranks in the sequence

Definition at line 616 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )

ADC group regular sequencer enable with 7 ranks in the sequence

Definition at line 617 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)

ADC group regular sequencer enable with 8 ranks in the sequence

Definition at line 618 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )

ADC group regular sequencer enable with 9 ranks in the sequence

Definition at line 619 of file stm32f1xx_ll_adc.h.

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STM32F103xB HAL User Manual: ADC group regular - Sequencer discontinuous mode

Defines
ADC group regular - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U
#define | LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

Define Documentation

#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 635 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks

Definition at line 636 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks

Definition at line 637 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks

Definition at line 638 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks

Definition at line 639 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks

Definition at line 640 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks

Definition at line 641 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)

ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks

Definition at line 642 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U

ADC group regular sequencer discontinuous mode disable

Definition at line 634 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), LL_ADC_REG_Init(), and LL_ADC_REG_StructInit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC group regular - Sequencer ranks

Defines
ADC group regular - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

Define Documentation

#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 1

Definition at line 650 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 10

Definition at line 659 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 11

Definition at line 660 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 12

Definition at line 661 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 13

Definition at line 662 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 14

Definition at line 663 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 15

Definition at line 664 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 16

Definition at line 665 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 2

Definition at line 651 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 3

Definition at line 652 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 4

Definition at line 653 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 5

Definition at line 654 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 6

Definition at line 655 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 7

Definition at line 656 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 8

Definition at line 657 of file stm32f1xx_ll_adc.h.

#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)

ADC group regular sequencer rank 9

Definition at line 658 of file stm32f1xx_ll_adc.h.

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STM32F103xB HAL User Manual: ADC group injected - Trigger source

Defines
ADC group injected - Trigger source
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)

ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting).

Definition at line 682 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0)

ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 676 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U

ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 675 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)

ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 679 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1)

ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 678 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2)

ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).

Definition at line 680 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)

ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting).

Definition at line 681 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)

ADC group injected conversion trigger internal: SW start.

Definition at line 674 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_INJ_IsTriggerSourceSWStart(), and LL_ADC_INJ_StructInit().

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STM32F103xB HAL User Manual: ADC group injected - Trigger edge

Defines
ADC group injected - Trigger edge
ADC Exported Constants

Defines

#define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG

Define Documentation

#define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG

ADC group injected conversion trigger polarity set to rising edge

Definition at line 706 of file stm32f1xx_ll_adc.h.

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STM32F103xB HAL User Manual: ADC group injected - Automatic trigger mode

Defines
ADC group injected - Automatic trigger mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO)

Define Documentation

#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO)

ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.

Definition at line 715 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U

ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger.

Definition at line 714 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_StructInit().

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STM32F103xB HAL User Manual: ADC group injected - Sequencer scan length

Defines
ADC group injected - Sequencer scan length
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

Define Documentation

#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U

ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel)

Definition at line 724 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init(), and LL_ADC_INJ_StructInit().

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)

ADC group injected sequencer enable with 2 ranks in the sequence

Definition at line 725 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )

ADC group injected sequencer enable with 3 ranks in the sequence

Definition at line 726 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)

ADC group injected sequencer enable with 4 ranks in the sequence

Definition at line 727 of file stm32f1xx_ll_adc.h.

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STM32F103xB HAL User Manual: ADC group injected - Sequencer discontinuous mode

Defines
ADC group injected - Sequencer discontinuous mode
ADC Exported Constants

Defines

#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN)

Define Documentation

#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN)

ADC group injected sequencer discontinuous mode enable with sequence interruption every rank

Definition at line 736 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U

ADC group injected sequencer discontinuous mode disable

Definition at line 735 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_StructInit().

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STM32F103xB HAL User Manual: ADC group injected - Sequencer ranks

Defines
ADC group injected - Sequencer ranks
ADC Exported Constants

Defines

#define | LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U)
#define | LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U)
#define | LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U)
#define | LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U)

Define Documentation

#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U)

ADC group injected sequencer rank 1

Definition at line 744 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U)

ADC group injected sequencer rank 2

Definition at line 745 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U)

ADC group injected sequencer rank 3

Definition at line 746 of file stm32f1xx_ll_adc.h.

#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U)

ADC group injected sequencer rank 4

Definition at line 747 of file stm32f1xx_ll_adc.h.

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STM32F103xB HAL User Manual: Channel - Sampling time

Defines
Channel - Sampling time
ADC Exported Constants

Defines

#define | LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U
#define | LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1)
#define | LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2)
#define | LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)
#define | LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)

Define Documentation

#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1)

Sampling time 13.5 ADC clock cycles

Definition at line 757 of file stm32f1xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U

Sampling time 1.5 ADC clock cycle

Definition at line 755 of file stm32f1xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)

Sampling time 239.5 ADC clock cycles

Definition at line 762 of file stm32f1xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)

Sampling time 28.5 ADC clock cycles

Definition at line 758 of file stm32f1xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2)

Sampling time 41.5 ADC clock cycles

Definition at line 759 of file stm32f1xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)

Sampling time 55.5 ADC clock cycles

Definition at line 760 of file stm32f1xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)

Sampling time 71.5 ADC clock cycles

Definition at line 761 of file stm32f1xx_ll_adc.h.

#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0)

Sampling time 7.5 ADC clock cycles

Definition at line 756 of file stm32f1xx_ll_adc.h.

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STM32F103xB HAL User Manual: Analog watchdog - Analog watchdog number

Defines
Analog watchdog - Analog watchdog number
ADC Exported Constants

Defines

#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)

Define Documentation

#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)

ADC analog watchdog number 1

Definition at line 770 of file stm32f1xx_ll_adc.h.

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STM32F103xB HAL User Manual: Analog watchdog - Monitored channels

Defines
Analog watchdog - Monitored channels
ADC Exported Constants

Defines

#define | LL_ADC_AWD_DISABLE 0x00000000U
#define | LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN )
#define | LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN )
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

Define Documentation

#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN )

ADC analog watchdog monitoring of all channels, converted by group injected only

Definition at line 780 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN )

ADC analog watchdog monitoring of all channels, converted by group regular only

Definition at line 779 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN )

ADC analog watchdog monitoring of all channels, converted by either group regular or injected

Definition at line 781 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only

Definition at line 840 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only

Definition at line 839 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected

Definition at line 841 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only

Definition at line 837 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only

Definition at line 836 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected

Definition at line 838 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only

Definition at line 783 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only

Definition at line 782 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected

Definition at line 784 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only

Definition at line 813 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only

Definition at line 812 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected

Definition at line 814 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only

Definition at line 816 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only

Definition at line 815 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected

Definition at line 817 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only

Definition at line 819 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only

Definition at line 818 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected

Definition at line 820 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only

Definition at line 822 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only

Definition at line 821 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected

Definition at line 823 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only

Definition at line 825 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only

Definition at line 824 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected

Definition at line 826 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only

Definition at line 828 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only

Definition at line 827 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected

Definition at line 829 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only

Definition at line 831 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only

Definition at line 830 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected

Definition at line 832 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only

Definition at line 834 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only

Definition at line 833 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected

Definition at line 835 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only

Definition at line 786 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only

Definition at line 785 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected

Definition at line 787 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only

Definition at line 789 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only

Definition at line 788 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected

Definition at line 790 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only

Definition at line 792 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only

Definition at line 791 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected

Definition at line 793 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only

Definition at line 795 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only

Definition at line 794 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected

Definition at line 796 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only

Definition at line 798 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only

Definition at line 797 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected

Definition at line 799 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only

Definition at line 801 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only

Definition at line 800 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected

Definition at line 802 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only

Definition at line 804 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only

Definition at line 803 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected

Definition at line 805 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only

Definition at line 807 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only

Definition at line 806 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected

Definition at line 808 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only

Definition at line 810 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only

Definition at line 809 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected

Definition at line 811 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_DISABLE 0x00000000U

ADC analog watchdog monitoring disabled

Definition at line 778 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Analog watchdog - Thresholds

Defines
Analog watchdog - Thresholds
ADC Exported Constants

Defines

#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET)
#define | LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET)

Define Documentation

#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET)

ADC analog watchdog threshold high

Definition at line 849 of file stm32f1xx_ll_adc.h.

#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET)

ADC analog watchdog threshold low

Definition at line 850 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Multimode - Mode

Defines
Multimode - Mode
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_INDEPENDENT 0x00000000U
#define | LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )
#define | LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)
#define | LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 )
#define | LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)
#define | LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 )
#define | LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)
#define | LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 )

Define Documentation

#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)

ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start)

Definition at line 873 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)

ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices))

Definition at line 872 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)

ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices))

Definition at line 870 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 )

ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices))

Definition at line 871 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)

ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous

Definition at line 876 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 )

ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous

Definition at line 877 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 )

ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger

Definition at line 875 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0)

ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous

Definition at line 874 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )

ADC dual mode enabled: group regular simultaneous

Definition at line 869 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_INDEPENDENT 0x00000000U

ADC dual mode disabled (ADC independent mode)

Definition at line 868 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_CommonInit(), and LL_ADC_CommonStructInit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Multimode - ADC master or slave

Defines
Multimode - ADC master or slave
ADC Exported Constants

Defines

#define | LL_ADC_MULTI_MASTER ( ADC_DR_DATA)
#define | LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA )
#define | LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA)

Define Documentation

#define LL_ADC_MULTI_MASTER ( ADC_DR_DATA)

In multimode, selection among several ADC instances: ADC master

Definition at line 886 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA)

In multimode, selection among several ADC instances: both ADC master and ADC slave

Definition at line 888 of file stm32f1xx_ll_adc.h.

#define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA )

In multimode, selection among several ADC instances: ADC slave

Definition at line 887 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Definitions of ADC hardware constraints delays

Defines
Definitions of ADC hardware constraints delays
ADC Exported Constants

Defines

#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U)
#define | LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U)
#define | LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U)

Detailed Description

Note:
Only ADC IP HW delays are defined in ADC LL driver driver, not timeout values. For details on delays values, refer to descriptions in source code above each literal definition.

Define Documentation

#define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U)

Delay required between ADC disable and ADC calibration start

Definition at line 933 of file stm32f1xx_ll_adc.h.

#define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U)

Delay required between end of ADC enable and the start of ADC calibration

Definition at line 943 of file stm32f1xx_ll_adc.h.

#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U)

Delay for internal voltage reference stabilization time

Definition at line 921 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Common write and read registers Macros

Defines
Common write and read registers Macros
ADC Exported Macros

Defines

#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.

Define Documentation

#define LL_ADC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 978 of file stm32f1xx_ll_adc.h.

#define LL_ADC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in ADC register.

Parameters:
__INSTANCE__ | ADC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 970 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC helper macro

Defines
ADC helper macro
ADC Exported Macros

Defines

#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << (0U))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) (__AWD_THRESHOLD_12_BITS__)
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA)
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFU)
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Define Documentation

#define __LL_ADC_ANALOGWD_CHANNEL_GROUP | ( | __CHANNEL__,
 |  | __GROUP__
 | ) |
Value:
(((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)                            \
      :                                                                                                   \
      ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
       ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)                        \
         :                                                                                                \
         (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)        \
  )

Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.

Note:
To be used with function LL_ADC_SetAnalogWDMonitChannels(). Example: LL_ADC_SetAnalogWDMonitChannels( ADC1, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
(1) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
__GROUP__ This parameter can be one of the following values:
  • LL_ADC_GROUP_REGULAR
  • LL_ADC_GROUP_INJECTED
  • LL_ADC_GROUP_REGULAR_INJECTED
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG
  • LL_ADC_AWD_ALL_CHANNELS_INJ
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG
  • LL_ADC_AWD_CHANNEL_0_INJ
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG
  • LL_ADC_AWD_CHANNEL_1_INJ
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG
  • LL_ADC_AWD_CHANNEL_2_INJ
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG
  • LL_ADC_AWD_CHANNEL_3_INJ
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG
  • LL_ADC_AWD_CHANNEL_4_INJ
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG
  • LL_ADC_AWD_CHANNEL_5_INJ
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG
  • LL_ADC_AWD_CHANNEL_6_INJ
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG
  • LL_ADC_AWD_CHANNEL_7_INJ
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG
  • LL_ADC_AWD_CHANNEL_8_INJ
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG
  • LL_ADC_AWD_CHANNEL_9_INJ
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG
  • LL_ADC_AWD_CHANNEL_10_INJ
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG
  • LL_ADC_AWD_CHANNEL_11_INJ
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG
  • LL_ADC_AWD_CHANNEL_12_INJ
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG
  • LL_ADC_AWD_CHANNEL_13_INJ
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG
  • LL_ADC_AWD_CHANNEL_14_INJ
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG
  • LL_ADC_AWD_CHANNEL_15_INJ
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG
  • LL_ADC_AWD_CHANNEL_16_INJ
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG
  • LL_ADC_AWD_CHANNEL_17_INJ
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (1)
  • LL_ADC_AWD_CH_VREFINT_INJ (1)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.

Definition at line 1315 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD_12_BITS__
 | ) | (__AWD_THRESHOLD_12_BITS__)

Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_GetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to get the value of analog watchdog threshold high (on 8 bits): < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION (LL_ADC_RESOLUTION_8B, LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
__AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1366 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION | ( | __ADC_RESOLUTION__,
 |  | __AWD_THRESHOLD__
 | ) | ((__AWD_THRESHOLD__) << (0U))

Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.

Note:
To be used with function LL_ADC_SetAnalogWDThresholds(). Example, with a ADC resolution of 8 bits, to set the value of analog watchdog threshold high (on 8 bits): LL_ADC_SetAnalogWDThresholds (< ADCx param >, __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) );
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
__AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1344 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_CALC_DATA_TO_VOLTAGE | ( | __VREFANALOG_VOLTAGE__,
 |  | __ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
  )

Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).

Note:
Analog reference voltage (Vref+) must be known from user board environment or can be calculated using ADC measurement.
Parameters:
__VREFANALOG_VOLTAGE__ | Analog reference voltage (unit: mV)
__ADC_DATA__ | ADC conversion data (resolution 12 bits) (unit: digital value).
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 1496 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS | ( | __TEMPSENSOR_TYP_AVGSLOPE__,
 |  | __TEMPSENSOR_TYP_CALX_V__,
 |  | __TEMPSENSOR_CALX_TEMP__,
 |  | __VREFANALOG_VOLTAGE__,
 |  | __TEMPSENSOR_ADC_DATA__,
 |  | __ADC_RESOLUTION__
 | ) |
Value:
((( (                                                                        \
       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
                 * 1000)                                                       \
       -                                                                       \
       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
                 * 1000)                                                       \
      )                                                                        \
    ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
   ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
  )

Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Note:
Computation is using temperature sensor typical values (refer to device datasheet).
Calculation formula: Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) / Avg_Slope + CALx_TEMP with TS_ADC_DATA = temperature sensor raw data measured by ADC (unit: digital value) Avg_Slope = temperature sensor slope (unit: uV/Degree Celsius) TS_TYP_CALx_VOLT = temperature sensor digital value at temperature CALx_TEMP (unit: mV) Caution: Calculation relevancy under reserve the temperature sensor of the current device has characteristics in line with datasheet typical values. If temperature sensor calibration values are available on on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), temperature calculation will be more accurate using helper macro __LL_ADC_CALC_TEMPERATURE().
As calculation input, the analog reference voltage (Vref+) must be defined as it impacts the ADC LSB equivalent voltage.
Analog reference voltage (Vref+) must be known from user board environment or can be calculated using ADC measurement.
ADC measurement data must correspond to a resolution of 12bits (full scale digital value 4095). If not the case, the data must be preliminarily rescaled to an equivalent resolution of 12 bits.
Parameters:
__TEMPSENSOR_TYP_AVGSLOPE__ | Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). On STM32F1, refer to device datasheet parameter "Avg_Slope".
__TEMPSENSOR_TYP_CALX_V__ | Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). On STM32F1, refer to device datasheet parameter "V25".
__TEMPSENSOR_CALX_TEMP__ | Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
__VREFANALOG_VOLTAGE__ | Analog voltage reference (Vref+) voltage (unit: mV)
__TEMPSENSOR_ADC_DATA__ | ADC conversion data of internal temperature sensor (unit: digital value).
__ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
Return values:
Temperature (unit: degree Celsius)

Definition at line 1544 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL ( __CHANNEL__ ) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

Note:
The channel parameter can be, additionally to a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17

Definition at line 1173 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_CHANNEL_TO_DECIMAL_NB ( __CHANNEL__ ) (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)

Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.

Note:
Example: __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) will return decimal number "4".
The input can be a value from functions where a channel number is returned, either defined with number or with bitfield (only one bit must be set).
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
Return values:
Value between Min_Data=0 and Max_Data=18

Definition at line 1021 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_COMMON_INSTANCE ( __ADCx__ ) (ADC12_COMMON)

Helper macro to select the ADC common instance to which is belonging the selected ADC instance.

Note:
ADC common register instance can be used for:
  • Set parameters common to several ADC instances
  • Multimode (for devices with several ADC instances) Refer to functions having argument "ADCxy_COMMON" as parameter.
On STM32F1, there is no common ADC instance. However, ADC instance ADC1 has a role of common ADC instance for ADC1 and ADC2: this instance is used to manage internal channels and multimode (these features are managed in ADC common instances on some other STM32 devices). ADC instance ADC3 (if available on the selected device) has no ADC common instance.
Parameters:
__ADCx__ ADC instance
Return values:
ADC common register instance

Definition at line 1417 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_DECIMAL_NB_TO_CHANNEL ( __DECIMAL_NB__ )
Value:
(((__DECIMAL_NB__) <= 9U)                                                                                     \
    ? (                                                                                                         \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \
       (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \
      )                                                                                                         \
      :                                                                                                         \
      (                                                                                                         \
       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \
       (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
      )                                                                                                         \
  )

Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.

Note:
Example: __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) will return a data equivalent to "LL_ADC_CHANNEL_4".
Parameters:
__DECIMAL_NB__,: Value between Min_Data=0 and Max_Data=18
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
(1) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 1058 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_DIGITAL_SCALE ( __ADC_RESOLUTION__ ) (0xFFFU)

Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.

Note:
ADC conversion data full-scale corresponds to voltage range determined by analog voltage references Vref+ and Vref- (refer to reference manual).
Parameters:
__ADC_RESOLUTION__ This parameter can be one of the following values:
  • LL_ADC_RESOLUTION_12B
Return values:
ADC conversion data equivalent voltage value (unit: mVolt)

Definition at line 1480 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_IS_CHANNEL_INTERNAL ( __CHANNEL__ ) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)

Helper macro to determine whether the selected channel corresponds to literal definitions of driver.

Note:
The different literal definitions of ADC channels are:
  • ADC internal channel: LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
  • ADC external channel (channel connected to a GPIO pin): LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
The channel parameter must be a value defined from literal definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), must not be a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
Return values:
Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

Definition at line 1114 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE | ( | __ADC_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__ADC_INSTANCE__) == ADC1)                                                \
    ? (                                                                        \
       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)                            \
      )                                                                        \
      :                                                                        \
      (0U)                                                                     \
  )

Helper macro to determine whether the internal channel selected is available on the ADC instance selected.

Note:
The channel parameter must be a value defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), must not be a value defined from parameter definition of ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) or a value from functions where a channel number is returned from ADC registers, because internal and external channels share the same channel number in ADC registers. The differentiation is made only with parameters definitions of driver.
Parameters:
__ADC_INSTANCE__ ADC instance
__CHANNEL__ This parameter can be one of the following values:
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
Return values:
Value "0" if the internal channel selected is not available on the ADC instance selected. Value "1" if the internal channel selected is available on the ADC instance selected.

Definition at line 1198 of file stm32f1xx_ll_adc.h.

#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE ( __ADCXY_COMMON__ )
Value:
(LL_ADC_IsEnabled(ADC1) |                                                    \
   LL_ADC_IsEnabled(ADC2)  )

Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.

Note:
This check is required by functions with setting conditioned to ADC state: All ADC instances of the ADC common group must be disabled. Refer to functions having argument "ADCxy_COMMON" as parameter.
On devices with only 1 ADC common instance, parameter of this macro is useless and can be ignored (parameter kept for compatibility with devices featuring several ADC common instances).
On STM32F1, there is no common ADC instance. However, ADC instance ADC1 has a role of common ADC instance for ADC1 and ADC2: this instance is used to manage internal channels and multimode (these features are managed in ADC common instances on some other STM32 devices). ADC instance ADC3 (if available on the selected device) has no ADC common instance.
Parameters:
__ADCXY_COMMON__ ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Value "0" if all ADC instances sharing the same ADC common instance are disabled. Value "1" if at least one ADC instance sharing the same ADC common instance is enabled.

Definition at line 1462 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_CommonInit().

#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE | ( | __ADC_MULTI_MASTER_SLAVE__,
 |  | __ADC_MULTI_CONV_DATA__
 | ) | (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA)

Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.

Note:
This macro is intended to be used when multimode transfer by DMA is enabled. In this case the transferred data need to processed with this macro to separate the conversion data of ADC master and ADC slave.
Parameters:
__ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
  • LL_ADC_MULTI_MASTER
  • LL_ADC_MULTI_SLAVE
__ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 1383 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC DMA management

Functions
ADC DMA management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Register
 | ) |  |

Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.

Note:
These ADC registers are data registers: when ADC conversion data is available in ADC data registers, ADC generates a DMA transfer request.
This macro is intended to be used with LL DMA driver, refer to function "LL_DMA_ConfigAddresses()". Example: LL_DMA_ConfigAddresses(DMA1, LL_DMA_CHANNEL_1, LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), (uint32_t)&< array or variable >, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
For devices with several ADC: in multimode, some devices use a different data register outside of ADC instance scope (common data register). This macro manages this register difference, only ADC instance has to be set as parameter.
On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer capability, not ADC2 (ADC2 and ADC3 instances not available on all devices).
On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3. Therefore, the corresponding parameter of data transfer for multimode can be used only with ADC1 and ADC2. (ADC2 and ADC3 instances not available on all devices).
Reference Manual to LL API cross reference:
DR DATA LL_ADC_DMA_GetRegAddr
Parameters:
ADCx ADC instance
Register This parameter can be one of the following values:
  • LL_ADC_DMA_REG_REGULAR_DATA
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
(1) Available on devices with several ADC instances.
Return values:
ADC register address

Definition at line 1619 of file stm32f1xx_ll_adc.h.

References LL_ADC_DMA_REG_REGULAR_DATA.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration of ADC hierarchical scope: common to several ADC instances

Functions
Configuration of ADC hierarchical scope: common to several ADC instances
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh ( ADC_Common_TypeDef * ADCxy_COMMON )

Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Reference Manual to LL API cross reference:
CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR

Definition at line 1696 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | PathInternal
 | ) |  |

Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).

Note:
One or several values can be selected. Example: (LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_PATH_INTERNAL_TEMPSENSOR)
Stabilization time of measurement path to internal channel: After enabling internal paths, before starting ADC conversion, a delay is required for internal voltage reference and temperature sensor stabilization time. Refer to device datasheet. Refer to literal LL_ADC_DELAY_TEMPSENSOR_STAB_US.
ADC internal channel sampling time constraint: For ADC conversion of internal channels, a sampling time minimum value is required. Refer to device datasheet.
Reference Manual to LL API cross reference:
CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
PathInternal This parameter can be a combination of the following values:
  • LL_ADC_PATH_INTERNAL_NONE
  • LL_ADC_PATH_INTERNAL_VREFINT
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR
Return values:
None

Definition at line 1677 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration of ADC hierarchical scope: ADC instance

Functions
Configuration of ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetSequencersScanMode (ADC_TypeDef *ADCx, uint32_t ScanMode)
Set ADC sequencers scan mode, for all ADC groups (group regular, group injected).
__STATIC_INLINE uint32_t | LL_ADC_GetSequencersScanMode (ADC_TypeDef *ADCx)
Get ADC sequencers scan mode, for all ADC groups (group regular, group injected).

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment ( ADC_TypeDef * ADCx )

Get ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
Reference Manual to LL API cross reference:
CR2 ALIGN LL_ADC_SetDataAlignment
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT

Definition at line 1735 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode ( ADC_TypeDef * ADCx )

Get ADC sequencers scan mode, for all ADC groups (group regular, group injected).

Note:
According to sequencers scan mode :
  • If disabled: ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of sequencers of all ADC groups (sequencer scan length, ...) is discarded: equivalent to scan length of 1 rank.
  • If enabled: ADC conversions are performed in sequence conversions mode, according to configuration of sequencers of each ADC group (sequencer scan length, ...). Refer to function LL_ADC_REG_SetSequencerLength() and to function LL_ADC_INJ_SetSequencerLength().
Reference Manual to LL API cross reference:
CR1 SCAN LL_ADC_GetSequencersScanMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_SEQ_SCAN_DISABLE
  • LL_ADC_SEQ_SCAN_ENABLE

Definition at line 1786 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetDataAlignment | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DataAlignment
 | ) |  |

Set ADC conversion data alignment.

Note:
Refer to reference manual for alignments formats dependencies to ADC resolutions.
Reference Manual to LL API cross reference:
CR2 ALIGN LL_ADC_SetDataAlignment
Parameters:
ADCx ADC instance
DataAlignment This parameter can be one of the following values:
  • LL_ADC_DATA_ALIGN_RIGHT
  • LL_ADC_DATA_ALIGN_LEFT
Return values:
None

Definition at line 1720 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetSequencersScanMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ScanMode
 | ) |  |

Set ADC sequencers scan mode, for all ADC groups (group regular, group injected).

Note:
According to sequencers scan mode :
  • If disabled: ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of sequencers of all ADC groups (sequencer scan length, ...) is discarded: equivalent to scan length of 1 rank.
  • If enabled: ADC conversions are performed in sequence conversions mode, according to configuration of sequencers of each ADC group (sequencer scan length, ...). Refer to function LL_ADC_REG_SetSequencerLength() and to function LL_ADC_INJ_SetSequencerLength().
Reference Manual to LL API cross reference:
CR1 SCAN LL_ADC_SetSequencersScanMode
Parameters:
ADCx ADC instance
ScanMode This parameter can be one of the following values:
  • LL_ADC_SEQ_SCAN_DISABLE
  • LL_ADC_SEQ_SCAN_ENABLE
Return values:
None

Definition at line 1761 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration of ADC hierarchical scope: group regular

Functions
Configuration of ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode ( ADC_TypeDef * ADCx )

Get ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
Reference Manual to LL API cross reference:
CR2 CONT LL_ADC_REG_GetContinuousMode
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS

Definition at line 2285 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR2 DMA LL_ADC_REG_GetDMATransfer
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED

Definition at line 2348 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS

Definition at line 2069 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function retrieves:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
On this STM32 serie, group regular sequencer configuration is conditioned to ADC instance sequencer mode. If ADC instance sequencer mode is disabled, sequencers of all groups (group regular, group injected) can be configured but their execution is disabled (limited to rank 1). Refer to function LL_ADC_SetSequencersScanMode().
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_SetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

Definition at line 2018 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group regular sequence: channel on the selected scan sequence rank.

Note:
On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
SQR3 SQ1 LL_ADC_REG_GetSequencerRanks
SQR3 SQ2 LL_ADC_REG_GetSequencerRanks
SQR3 SQ3 LL_ADC_REG_GetSequencerRanks
SQR3 SQ4 LL_ADC_REG_GetSequencerRanks
SQR3 SQ5 LL_ADC_REG_GetSequencerRanks
SQR3 SQ6 LL_ADC_REG_GetSequencerRanks
SQR2 SQ7 LL_ADC_REG_GetSequencerRanks
SQR2 SQ8 LL_ADC_REG_GetSequencerRanks
SQR2 SQ9 LL_ADC_REG_GetSequencerRanks
SQR2 SQ10 LL_ADC_REG_GetSequencerRanks
SQR2 SQ11 LL_ADC_REG_GetSequencerRanks
SQR2 SQ12 LL_ADC_REG_GetSequencerRanks
SQR1 SQ13 LL_ADC_REG_GetSequencerRanks
SQR1 SQ14 LL_ADC_REG_GetSequencerRanks
SQR1 SQ15 LL_ADC_REG_GetSequencerRanks
SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
(1) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 2243 of file stm32f1xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_MASK, ADC_REG_RANK_ID_SQRX_MASK, and ADC_REG_SQRX_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

Note:
To determine whether group regular trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") use function LL_ADC_REG_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR2 EXTSEL LL_ADC_REG_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
  • LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
  • LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
  • LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
  • LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
  • LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
(1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).
(2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).
(3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).
(4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).

Definition at line 1880 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group regular conversion trigger source internal (SW start) or external.

Note:
In case of group regular trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_REG_GetTriggerSource().
Reference Manual to LL API cross reference:
CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 1896 of file stm32f1xx_ll_adc.h.

References LL_ADC_REG_TRIG_SOFTWARE.

__STATIC_INLINE void LL_ADC_REG_SetContinuousMode | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Continuous
 | ) |  |

Set ADC continuous conversion mode on ADC group regular.

Note:
Description of ADC continuous conversion mode:
  • single mode: one conversion per trigger
  • continuous mode: after the first trigger, following conversions launched successively automatically.
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CR2 CONT LL_ADC_REG_SetContinuousMode
Parameters:
ADCx ADC instance
Continuous This parameter can be one of the following values:
  • LL_ADC_REG_CONV_SINGLE
  • LL_ADC_REG_CONV_CONTINUOUS
Return values:
None

Definition at line 2268 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetDMATransfer | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | DMATransfer
 | ) |  |

Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

Note:
If transfer by DMA selected, specifies the DMA requests mode:
  • Limited mode (One shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular.
  • Unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transfers (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular.
If ADC DMA requests mode is set to unlimited and DMA is set to mode non-circular: when DMA transfers size will be reached, DMA will stop transfers of ADC conversions data ADC will raise an overrun error (overrun flag and interruption if enabled).
To configure DMA source address (peripheral address), use function LL_ADC_DMA_GetRegAddr().
Reference Manual to LL API cross reference:
CR2 DMA LL_ADC_REG_SetDMATransfer
Parameters:
ADCx ADC instance
DMATransfer This parameter can be one of the following values:
  • LL_ADC_REG_DMA_TRANSFER_NONE
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED
Return values:
None

Definition at line 2317 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group regular continuous mode and sequencer discontinuous mode.
It is not possible to enable both ADC auto-injected mode and ADC group regular sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CR1 DISCEN LL_ADC_REG_SetSequencerDiscont
CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_DISCONT_DISABLE
  • LL_ADC_REG_SEQ_DISCONT_1RANK
  • LL_ADC_REG_SEQ_DISCONT_2RANKS
  • LL_ADC_REG_SEQ_DISCONT_3RANKS
  • LL_ADC_REG_SEQ_DISCONT_4RANKS
  • LL_ADC_REG_SEQ_DISCONT_5RANKS
  • LL_ADC_REG_SEQ_DISCONT_6RANKS
  • LL_ADC_REG_SEQ_DISCONT_7RANKS
  • LL_ADC_REG_SEQ_DISCONT_8RANKS
Return values:
None

Definition at line 2046 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group regular sequencer length and scan direction.

Note:
Description of ADC group regular sequencer features:
  • For devices with sequencer fully configurable (function "LL_ADC_REG_SetSequencerRanks()" available): sequencer length and each rank affectation to a channel are configurable. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence.
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerRanks()".
  • For devices with sequencer not fully configurable (function "LL_ADC_REG_SetSequencerChannels()" available): sequencer length and each rank affectation to a channel are defined by channel number. This function performs configuration of:
    • Sequence length: Number of ranks in the scan sequence is defined by number of channels set in the sequence, rank of each channel is fixed by channel HW number. (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
    • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from lowest channel number to highest channel number). Sequencer ranks are selected using function "LL_ADC_REG_SetSequencerChannels()".
On this STM32 serie, group regular sequencer configuration is conditioned to ADC instance sequencer mode. If ADC instance sequencer mode is disabled, sequencers of all groups (group regular, group injected) can be configured but their execution is disabled (limited to rank 1). Refer to function LL_ADC_SetSequencersScanMode().
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
SQR1 L LL_ADC_REG_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_REG_SEQ_SCAN_DISABLE
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
Return values:
None

Definition at line 1958 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_REG_Init().

__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group regular sequence: channel on the selected scan sequence rank.

Note:
This function performs configuration of:
  • Channels ordering into each rank of scan sequence: whatever channel can be placed into whatever rank.
On this STM32 serie, ADC group regular sequencer is fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function LL_ADC_REG_SetSequencerLength().
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
Reference Manual to LL API cross reference:
SQR3 SQ1 LL_ADC_REG_SetSequencerRanks
SQR3 SQ2 LL_ADC_REG_SetSequencerRanks
SQR3 SQ3 LL_ADC_REG_SetSequencerRanks
SQR3 SQ4 LL_ADC_REG_SetSequencerRanks
SQR3 SQ5 LL_ADC_REG_SetSequencerRanks
SQR3 SQ6 LL_ADC_REG_SetSequencerRanks
SQR2 SQ7 LL_ADC_REG_SetSequencerRanks
SQR2 SQ8 LL_ADC_REG_SetSequencerRanks
SQR2 SQ9 LL_ADC_REG_SetSequencerRanks
SQR2 SQ10 LL_ADC_REG_SetSequencerRanks
SQR2 SQ11 LL_ADC_REG_SetSequencerRanks
SQR2 SQ12 LL_ADC_REG_SetSequencerRanks
SQR1 SQ13 LL_ADC_REG_SetSequencerRanks
SQR1 SQ14 LL_ADC_REG_SetSequencerRanks
SQR1 SQ15 LL_ADC_REG_SetSequencerRanks
SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_REG_RANK_1
  • LL_ADC_REG_RANK_2
  • LL_ADC_REG_RANK_3
  • LL_ADC_REG_RANK_4
  • LL_ADC_REG_RANK_5
  • LL_ADC_REG_RANK_6
  • LL_ADC_REG_RANK_7
  • LL_ADC_REG_RANK_8
  • LL_ADC_REG_RANK_9
  • LL_ADC_REG_RANK_10
  • LL_ADC_REG_RANK_11
  • LL_ADC_REG_RANK_12
  • LL_ADC_REG_RANK_13
  • LL_ADC_REG_RANK_14
  • LL_ADC_REG_RANK_15
  • LL_ADC_REG_RANK_16
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
Return values:
None

Definition at line 2149 of file stm32f1xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_ID_NUMBER_MASK, ADC_REG_RANK_ID_SQRX_MASK, and ADC_REG_SQRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_REG_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

Note:
On this STM32 serie, external trigger is set with trigger polarity: rising edge (only trigger polarity available on this STM32 serie).
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR2 EXTSEL LL_ADC_REG_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_SOFTWARE
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
  • LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
  • LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
  • LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
  • LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
  • LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
  • LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
(1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).
(2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).
(3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).
(4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
Return values:
None

Definition at line 1833 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration of ADC hierarchical scope: group injected

Functions
Configuration of ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetOffset (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
Set ADC group injected offset.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetOffset (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected offset.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected offset.

Note:
It gives offset level (offset to be subtracted from the raw converted data). Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
Reference Manual to LL API cross reference:
JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset
JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset
JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset
JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 2766 of file stm32f1xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JOFRX_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont ( ADC_TypeDef * ADCx )

Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Reference Manual to LL API cross reference:
CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK

Definition at line 2544 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength ( ADC_TypeDef * ADCx )

Get ADC group injected sequencer length and scan direction.

Note:
This function retrieves:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
On this STM32 serie, group injected sequencer configuration is conditioned to ADC instance sequencer mode. If ADC instance sequencer mode is disabled, sequencers of all groups (group regular, group injected) can be configured but their execution is disabled (limited to rank 1). Refer to function LL_ADC_SetSequencersScanMode().
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_GetSequencerLength
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

Definition at line 2511 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB().
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Returned value can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
(1) For ADC channel read back from ADC register, comparison with internal channel parameter to be done using helper macro __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

Definition at line 2659 of file stm32f1xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger: independent or from ADC group regular.

Reference Manual to LL API cross reference:
CR1 JAUTO LL_ADC_INJ_GetTrigAuto
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

Definition at line 2709 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

Note:
To determine whether group injected trigger source is internal (SW start) or external, without detail of which peripheral is selected as external trigger, (equivalent to "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") use function LL_ADC_INJ_IsTriggerSourceSWStart.
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
  • LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
  • LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
(1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).
(2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).
(3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).
(4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).

Definition at line 2440 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart ( ADC_TypeDef * ADCx )

Get ADC group injected conversion trigger source internal (SW start) or external.

Note:
In case of group injected trigger source set to external trigger, to determine which peripheral is selected as external trigger, use function LL_ADC_INJ_GetTriggerSource.
Reference Manual to LL API cross reference:
CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
Parameters:
ADCx ADC instance
Return values:
Value "0" if trigger source external trigger Value "1" if trigger source SW start.

Definition at line 2456 of file stm32f1xx_ll_adc.h.

References LL_ADC_INJ_TRIG_SOFTWARE.

__STATIC_INLINE void LL_ADC_INJ_SetOffset | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | OffsetLevel
 | ) |  |

Set ADC group injected offset.

Note:
It sets:
  • ADC group injected rank to which the offset programmed will be applied
  • Offset level (offset to be subtracted from the raw converted data). Caution: Offset format is dependent to ADC resolution: offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
Offset cannot be enabled or disabled. To emulate offset disabled, set an offset value equal to 0.
Reference Manual to LL API cross reference:
JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset
JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset
JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset
JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
Parameters:
ADCx | ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
OffsetLevel | Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 2739 of file stm32f1xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JOFRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SeqDiscont
 | ) |  |

Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

Note:
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
Parameters:
ADCx ADC instance
SeqDiscont This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE
  • LL_ADC_INJ_SEQ_DISCONT_1RANK
Return values:
None

Definition at line 2529 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | SequencerNbRanks
 | ) |  |

Set ADC group injected sequencer length and scan direction.

Note:
This function performs configuration of:
  • Sequence length: Number of ranks in the scan sequence.
  • Sequence direction: Unless specified in parameters, sequencer scan direction is forward (from rank 1 to rank n).
On this STM32 serie, group injected sequencer configuration is conditioned to ADC instance sequencer mode. If ADC instance sequencer mode is disabled, sequencers of all groups (group regular, group injected) can be configured but their execution is disabled (limited to rank 1). Refer to function LL_ADC_SetSequencersScanMode().
Sequencer disabled is equivalent to sequencer of 1 rank: ADC conversion on only 1 channel.
Reference Manual to LL API cross reference:
JSQR JL LL_ADC_INJ_SetSequencerLength
Parameters:
ADCx ADC instance
SequencerNbRanks This parameter can be one of the following values:
  • LL_ADC_INJ_SEQ_SCAN_DISABLE
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
Return values:
None

Definition at line 2484 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_INJ_Init().

__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank,
 |  | uint32_t | Channel
 | ) |  |

Set ADC group injected sequence: channel on the selected sequence rank.

Note:
Depending on devices and packages, some channels may not be available. Refer to device datasheet for channels availability.
On this STM32 serie, to measure internal channels (VrefInt, TempSensor, ...), measurement paths to internal channels must be enabled separately. This can be done using function LL_ADC_SetCommonPathInternalCh().
Reference Manual to LL API cross reference:
JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks
JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
Return values:
None

Definition at line 2593 of file stm32f1xx_ll_adc.h.

References ADC_CHANNEL_ID_NUMBER_MASK.

__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TrigAuto
 | ) |  |

Set ADC group injected conversion trigger: independent or from ADC group regular.

Note:
This mode can be used to extend number of data registers updated after one ADC conversion trigger and with data permanently kept (not erased by successive conversions of scan of ADC sequencer ranks), up to 5 data registers: 1 data register on ADC group regular, 4 data registers on ADC group injected.
If ADC group injected injected trigger source is set to an external trigger, this feature must be must be set to independent trigger. ADC group injected automatic trigger is compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular.
It is not possible to enable both ADC group injected auto-injected mode and sequencer discontinuous mode.
Reference Manual to LL API cross reference:
CR1 JAUTO LL_ADC_INJ_SetTrigAuto
Parameters:
ADCx ADC instance
TrigAuto This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_INDEPENDENT
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
Return values:
None

Definition at line 2695 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | TriggerSource
 | ) |  |

Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

Note:
On this STM32 serie, external trigger is set with trigger polarity: rising edge (only trigger polarity available on this STM32 serie).
Availability of parameters of trigger sources from timer depends on timers availability on the selected device.
Reference Manual to LL API cross reference:
CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
Parameters:
ADCx ADC instance
TriggerSource This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_SOFTWARE
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
  • LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
  • LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
  • LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
  • LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
(1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).
(2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).
(3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).
(4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
Return values:
None

Definition at line 2394 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration of ADC hierarchical scope: channels

Functions
Configuration of ADC hierarchical scope: channels
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel
 | ) |  |

Get sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
Conversion time is the addition of sampling time and processing time. Refer to reference manual for ADC processing time of this STM32 serie.
Reference Manual to LL API cross reference:
SMPR1 SMP17 LL_ADC_GetChannelSamplingTime
SMPR1 SMP16 LL_ADC_GetChannelSamplingTime
SMPR1 SMP15 LL_ADC_GetChannelSamplingTime
SMPR1 SMP14 LL_ADC_GetChannelSamplingTime
SMPR1 SMP13 LL_ADC_GetChannelSamplingTime
SMPR1 SMP12 LL_ADC_GetChannelSamplingTime
SMPR1 SMP11 LL_ADC_GetChannelSamplingTime
SMPR1 SMP10 LL_ADC_GetChannelSamplingTime
SMPR2 SMP9 LL_ADC_GetChannelSamplingTime
SMPR2 SMP8 LL_ADC_GetChannelSamplingTime
SMPR2 SMP7 LL_ADC_GetChannelSamplingTime
SMPR2 SMP6 LL_ADC_GetChannelSamplingTime
SMPR2 SMP5 LL_ADC_GetChannelSamplingTime
SMPR2 SMP4 LL_ADC_GetChannelSamplingTime
SMPR2 SMP3 LL_ADC_GetChannelSamplingTime
SMPR2 SMP2 LL_ADC_GetChannelSamplingTime
SMPR2 SMP1 LL_ADC_GetChannelSamplingTime
SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
Return values:
Returned value can be one of the following values:
  • LL_ADC_SAMPLINGTIME_1CYCLE_5
  • LL_ADC_SAMPLINGTIME_7CYCLES_5
  • LL_ADC_SAMPLINGTIME_13CYCLES_5
  • LL_ADC_SAMPLINGTIME_28CYCLES_5
  • LL_ADC_SAMPLINGTIME_41CYCLES_5
  • LL_ADC_SAMPLINGTIME_55CYCLES_5
  • LL_ADC_SAMPLINGTIME_71CYCLES_5
  • LL_ADC_SAMPLINGTIME_239CYCLES_5

Definition at line 2928 of file stm32f1xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, and ADC_CHANNEL_SMPx_BITOFFSET_MASK.

__STATIC_INLINE void LL_ADC_SetChannelSamplingTime | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Channel,
 |  | uint32_t | SamplingTime
 | ) |  |

Set sampling time of the selected ADC channel Unit: ADC clock cycles.

Note:
On this device, sampling time is on channel scope: independently of channel mapped on ADC group regular or injected.
In case of internal channel (VrefInt, TempSensor, ...) to be converted: sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting). Refer to device datasheet for timings values (parameters TS_vrefint, TS_temp, ...).
Conversion time is the addition of sampling time and processing time. Refer to reference manual for ADC processing time of this STM32 serie.
In case of ADC conversion of internal channel (VrefInt, temperature sensor, ...), a sampling time minimum value is required. Refer to device datasheet.
Reference Manual to LL API cross reference:
SMPR1 SMP17 LL_ADC_SetChannelSamplingTime
SMPR1 SMP16 LL_ADC_SetChannelSamplingTime
SMPR1 SMP15 LL_ADC_SetChannelSamplingTime
SMPR1 SMP14 LL_ADC_SetChannelSamplingTime
SMPR1 SMP13 LL_ADC_SetChannelSamplingTime
SMPR1 SMP12 LL_ADC_SetChannelSamplingTime
SMPR1 SMP11 LL_ADC_SetChannelSamplingTime
SMPR1 SMP10 LL_ADC_SetChannelSamplingTime
SMPR2 SMP9 LL_ADC_SetChannelSamplingTime
SMPR2 SMP8 LL_ADC_SetChannelSamplingTime
SMPR2 SMP7 LL_ADC_SetChannelSamplingTime
SMPR2 SMP6 LL_ADC_SetChannelSamplingTime
SMPR2 SMP5 LL_ADC_SetChannelSamplingTime
SMPR2 SMP4 LL_ADC_SetChannelSamplingTime
SMPR2 SMP3 LL_ADC_SetChannelSamplingTime
SMPR2 SMP2 LL_ADC_SetChannelSamplingTime
SMPR2 SMP1 LL_ADC_SetChannelSamplingTime
SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
Parameters:
ADCx ADC instance
Channel This parameter can be one of the following values:
  • LL_ADC_CHANNEL_0
  • LL_ADC_CHANNEL_1
  • LL_ADC_CHANNEL_2
  • LL_ADC_CHANNEL_3
  • LL_ADC_CHANNEL_4
  • LL_ADC_CHANNEL_5
  • LL_ADC_CHANNEL_6
  • LL_ADC_CHANNEL_7
  • LL_ADC_CHANNEL_8
  • LL_ADC_CHANNEL_9
  • LL_ADC_CHANNEL_10
  • LL_ADC_CHANNEL_11
  • LL_ADC_CHANNEL_12
  • LL_ADC_CHANNEL_13
  • LL_ADC_CHANNEL_14
  • LL_ADC_CHANNEL_15
  • LL_ADC_CHANNEL_16
  • LL_ADC_CHANNEL_17
  • LL_ADC_CHANNEL_VREFINT (1)
  • LL_ADC_CHANNEL_TEMPSENSOR (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
SamplingTime This parameter can be one of the following values:
  • LL_ADC_SAMPLINGTIME_1CYCLE_5
  • LL_ADC_SAMPLINGTIME_7CYCLES_5
  • LL_ADC_SAMPLINGTIME_13CYCLES_5
  • LL_ADC_SAMPLINGTIME_28CYCLES_5
  • LL_ADC_SAMPLINGTIME_41CYCLES_5
  • LL_ADC_SAMPLINGTIME_55CYCLES_5
  • LL_ADC_SAMPLINGTIME_71CYCLES_5
  • LL_ADC_SAMPLINGTIME_239CYCLES_5
Return values:
None

Definition at line 2855 of file stm32f1xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, ADC_CHANNEL_SMPRX_REGOFFSET_MASK, and ADC_CHANNEL_SMPx_BITOFFSET_MASK.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration of ADC transversal scope: analog watchdog

Functions
Configuration of ADC transversal scope: analog watchdog
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high or threshold low.

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels ( ADC_TypeDef * ADCx )

Get ADC analog watchdog monitored channel.

Note:
Usage of the returned channel number:
  • To reinject this channel into another function LL_ADC_xxx: the returned channel number is only partly formatted on definition of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared with parts of literals LL_ADC_CHANNEL_x or using helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Then the selected literal LL_ADC_CHANNEL_x can be used as parameter for another function.
  • To get the channel number in decimal format: process the returned value with the helper macro __LL_ADC_CHANNEL_TO_DECIMAL_NB(). Applicable only when the analog watchdog is set to monitor one channel.
On this STM32 serie, there is only 1 kind of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
Reference Manual to LL API cross reference:
CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels
CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels
CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
Return values:
Returned value can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG
  • LL_ADC_AWD_ALL_CHANNELS_INJ
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG
  • LL_ADC_AWD_CHANNEL_0_INJ
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG
  • LL_ADC_AWD_CHANNEL_1_INJ
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG
  • LL_ADC_AWD_CHANNEL_2_INJ
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG
  • LL_ADC_AWD_CHANNEL_3_INJ
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG
  • LL_ADC_AWD_CHANNEL_4_INJ
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG
  • LL_ADC_AWD_CHANNEL_5_INJ
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG
  • LL_ADC_AWD_CHANNEL_6_INJ
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG
  • LL_ADC_AWD_CHANNEL_7_INJ
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG
  • LL_ADC_AWD_CHANNEL_8_INJ
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG
  • LL_ADC_AWD_CHANNEL_9_INJ
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG
  • LL_ADC_AWD_CHANNEL_10_INJ
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG
  • LL_ADC_AWD_CHANNEL_11_INJ
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG
  • LL_ADC_AWD_CHANNEL_12_INJ
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG
  • LL_ADC_AWD_CHANNEL_13_INJ
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG
  • LL_ADC_AWD_CHANNEL_14_INJ
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG
  • LL_ADC_AWD_CHANNEL_15_INJ
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG
  • LL_ADC_AWD_CHANNEL_16_INJ
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG
  • LL_ADC_AWD_CHANNEL_17_INJ
  • LL_ADC_AWD_CHANNEL_17_REG_INJ

Definition at line 3128 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDThresholdsHighLow
 | ) |  |

Get ADC analog watchdog threshold value of threshold high or threshold low.

Note:
In case of ADC resolution different of 12 bits, analog watchdog thresholds data require a specific shift. Use helper macro __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
Reference Manual to LL API cross reference:
HTR HT LL_ADC_GetAnalogWDThresholds
LTR LT LL_ADC_GetAnalogWDThresholds
Parameters:
ADCx ADC instance
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 3175 of file stm32f1xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDChannelGroup
 | ) |  |

Set ADC analog watchdog monitored channels: a single channel or all channels, on ADC groups regular and-or injected.

Note:
Once monitored channels are selected, analog watchdog is enabled.
In case of need to define a single channel to monitor with analog watchdog from sequencer channel definition, use helper macro __LL_ADC_ANALOGWD_CHANNEL_GROUP().
On this STM32 serie, there is only 1 kind of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
Reference Manual to LL API cross reference:
CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels
CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels
CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
Parameters:
ADCx ADC instance
AWDChannelGroup This parameter can be one of the following values:
  • LL_ADC_AWD_DISABLE
  • LL_ADC_AWD_ALL_CHANNELS_REG
  • LL_ADC_AWD_ALL_CHANNELS_INJ
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ
  • LL_ADC_AWD_CHANNEL_0_REG
  • LL_ADC_AWD_CHANNEL_0_INJ
  • LL_ADC_AWD_CHANNEL_0_REG_INJ
  • LL_ADC_AWD_CHANNEL_1_REG
  • LL_ADC_AWD_CHANNEL_1_INJ
  • LL_ADC_AWD_CHANNEL_1_REG_INJ
  • LL_ADC_AWD_CHANNEL_2_REG
  • LL_ADC_AWD_CHANNEL_2_INJ
  • LL_ADC_AWD_CHANNEL_2_REG_INJ
  • LL_ADC_AWD_CHANNEL_3_REG
  • LL_ADC_AWD_CHANNEL_3_INJ
  • LL_ADC_AWD_CHANNEL_3_REG_INJ
  • LL_ADC_AWD_CHANNEL_4_REG
  • LL_ADC_AWD_CHANNEL_4_INJ
  • LL_ADC_AWD_CHANNEL_4_REG_INJ
  • LL_ADC_AWD_CHANNEL_5_REG
  • LL_ADC_AWD_CHANNEL_5_INJ
  • LL_ADC_AWD_CHANNEL_5_REG_INJ
  • LL_ADC_AWD_CHANNEL_6_REG
  • LL_ADC_AWD_CHANNEL_6_INJ
  • LL_ADC_AWD_CHANNEL_6_REG_INJ
  • LL_ADC_AWD_CHANNEL_7_REG
  • LL_ADC_AWD_CHANNEL_7_INJ
  • LL_ADC_AWD_CHANNEL_7_REG_INJ
  • LL_ADC_AWD_CHANNEL_8_REG
  • LL_ADC_AWD_CHANNEL_8_INJ
  • LL_ADC_AWD_CHANNEL_8_REG_INJ
  • LL_ADC_AWD_CHANNEL_9_REG
  • LL_ADC_AWD_CHANNEL_9_INJ
  • LL_ADC_AWD_CHANNEL_9_REG_INJ
  • LL_ADC_AWD_CHANNEL_10_REG
  • LL_ADC_AWD_CHANNEL_10_INJ
  • LL_ADC_AWD_CHANNEL_10_REG_INJ
  • LL_ADC_AWD_CHANNEL_11_REG
  • LL_ADC_AWD_CHANNEL_11_INJ
  • LL_ADC_AWD_CHANNEL_11_REG_INJ
  • LL_ADC_AWD_CHANNEL_12_REG
  • LL_ADC_AWD_CHANNEL_12_INJ
  • LL_ADC_AWD_CHANNEL_12_REG_INJ
  • LL_ADC_AWD_CHANNEL_13_REG
  • LL_ADC_AWD_CHANNEL_13_INJ
  • LL_ADC_AWD_CHANNEL_13_REG_INJ
  • LL_ADC_AWD_CHANNEL_14_REG
  • LL_ADC_AWD_CHANNEL_14_INJ
  • LL_ADC_AWD_CHANNEL_14_REG_INJ
  • LL_ADC_AWD_CHANNEL_15_REG
  • LL_ADC_AWD_CHANNEL_15_INJ
  • LL_ADC_AWD_CHANNEL_15_REG_INJ
  • LL_ADC_AWD_CHANNEL_16_REG
  • LL_ADC_AWD_CHANNEL_16_INJ
  • LL_ADC_AWD_CHANNEL_16_REG_INJ
  • LL_ADC_AWD_CHANNEL_17_REG
  • LL_ADC_AWD_CHANNEL_17_INJ
  • LL_ADC_AWD_CHANNEL_17_REG_INJ
  • LL_ADC_AWD_CH_VREFINT_REG (1)
  • LL_ADC_AWD_CH_VREFINT_INJ (1)
  • LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
(1) On STM32F1, parameter available only on ADC instance: ADC1.
Return values:
None

Definition at line 3035 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | AWDThresholdsHighLow,
 |  | uint32_t | AWDThresholdValue
 | ) |  |

Set ADC analog watchdog threshold value of threshold high or low.

Note:
On this STM32 serie, there is only 1 kind of analog watchdog instance:
  • AWD standard (instance AWD1):
    • channels monitored: can monitor 1 channel or all channels.
    • groups monitored: ADC groups regular and-or injected.
    • resolution: resolution is not limited (corresponds to ADC resolution configured).
Reference Manual to LL API cross reference:
HTR HT LL_ADC_SetAnalogWDThresholds
LTR LT LL_ADC_SetAnalogWDThresholds
Parameters:
ADCx ADC instance
AWDThresholdsHighLow This parameter can be one of the following values:
  • LL_ADC_AWD_THRESHOLD_HIGH
  • LL_ADC_AWD_THRESHOLD_LOW
AWDThresholdValue,: Value between Min_Data=0x000 and Max_Data=0xFFF
Return values:
None

Definition at line 3152 of file stm32f1xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration of ADC hierarchical scope: multimode

Functions
Configuration of ADC hierarchical scope: multimode
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_SetMultimode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t | LL_ADC_GetMultimode (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

Function Documentation

__STATIC_INLINE uint32_t LL_ADC_GetMultimode ( ADC_Common_TypeDef * ADCxy_COMMON )

Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

Note:
If multimode configuration: the selected ADC instance is either master or slave depending on hardware. Refer to reference manual.
Reference Manual to LL API cross reference:
CR1 DUALMOD LL_ADC_GetMultimode
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
Returned value can be one of the following values:
  • LL_ADC_MULTI_INDEPENDENT
  • LL_ADC_MULTI_DUAL_REG_SIMULT
  • LL_ADC_MULTI_DUAL_REG_INTERL_FAST
  • LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
  • LL_ADC_MULTI_DUAL_INJ_SIMULT
  • LL_ADC_MULTI_DUAL_INJ_ALTERN
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  • LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
  • LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM

Definition at line 3239 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_SetMultimode | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | uint32_t | Multimode
 | ) |  |

Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

Note:
If multimode configuration: the selected ADC instance is either master or slave depending on hardware. Refer to reference manual.
Reference Manual to LL API cross reference:
CR1 DUALMOD LL_ADC_SetMultimode
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Multimode This parameter can be one of the following values:
  • LL_ADC_MULTI_INDEPENDENT
  • LL_ADC_MULTI_DUAL_REG_SIMULT
  • LL_ADC_MULTI_DUAL_REG_INTERL_FAST
  • LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
  • LL_ADC_MULTI_DUAL_INJ_SIMULT
  • LL_ADC_MULTI_DUAL_INJ_ALTERN
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
  • LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
  • LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
Return values:
None

Definition at line 3213 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Operation on ADC hierarchical scope: ADC instance

Functions
Operation on ADC hierarchical scope: ADC instance
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.

Function Documentation

__STATIC_INLINE void LL_ADC_Disable ( ADC_TypeDef * ADCx )

Disable the selected ADC instance.

Reference Manual to LL API cross reference:
CR2 ADON LL_ADC_Disable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3274 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DeInit().

__STATIC_INLINE void LL_ADC_Enable ( ADC_TypeDef * ADCx )

Enable the selected ADC instance.

Note:
On this STM32 serie, after ADC enable, a delay for ADC internal analog stabilization is required before performing a ADC conversion start. Refer to device datasheet, parameter tSTAB.
Reference Manual to LL API cross reference:
CR2 ADON LL_ADC_Enable
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3263 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing ( ADC_TypeDef * ADCx )

Get ADC calibration state.

Reference Manual to LL API cross reference:
CR2 CAL LL_ADC_IsCalibrationOnGoing
Parameters:
ADCx ADC instance
Return values:
0,: calibration complete, 1: calibration in progress.

Definition at line 3316 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsEnabled ( ADC_TypeDef * ADCx )

Get the selected ADC instance enable state.

Reference Manual to LL API cross reference:
CR2 ADON LL_ADC_IsEnabled
Parameters:
ADCx ADC instance
Return values:
0,: ADC is disabled, 1: ADC is enabled.

Definition at line 3285 of file stm32f1xx_ll_adc.h.

Referenced by LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

__STATIC_INLINE void LL_ADC_StartCalibration ( ADC_TypeDef * ADCx )

Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).

Note:
On this STM32 serie, before starting a calibration, ADC must be disabled. A minimum number of ADC clock cycles are required between ADC disable state and calibration start. Refer to literal LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
On this STM32 serie, hardware prerequisite before starting a calibration: the ADC must have been in power-on state for at least two ADC clock cycles.
Reference Manual to LL API cross reference:
CR2 CAL LL_ADC_StartCalibration
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3305 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Operation on ADC hierarchical scope: group regular

Functions
Operation on ADC hierarchical scope: group regular
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_REG_StartConversionSWStart (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StartConversionExtTrig (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Start ADC group regular conversion from external trigger.
__STATIC_INLINE void | LL_ADC_REG_StopConversionExtTrig (ADC_TypeDef *ADCx)
Stop ADC group regular conversion from external trigger.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadMultiConversionData32 (ADC_TypeDef *ADCx, uint32_t ConversionData)
Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.

Function Documentation

__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_REG_ReadConversionData32.
Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData12
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 3411 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32 ( ADC_TypeDef * ADCx )

Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
DR RDATA LL_ADC_REG_ReadConversionData32
Parameters:
ADCx ADC instance
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 3396 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ConversionData
 | ) |  |

Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.

Note:
If raw data with ADC master and slave concatenated is retrieved, a macro is available to get the conversion data of ADC master or ADC slave: see helper macro __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). (however this macro is mainly intended for multimode transfer by DMA, because this function can do the same by getting multimode conversion data of ADC master or ADC slave separately).
Reference Manual to LL API cross reference:
DR DATA LL_ADC_REG_ReadMultiConversionData32
DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32
Parameters:
ADCx ADC instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
ConversionData This parameter can be one of the following values:
  • LL_ADC_MULTI_MASTER
  • LL_ADC_MULTI_SLAVE
  • LL_ADC_MULTI_MASTER_SLAVE
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 3438 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Start ADC group regular conversion from external trigger.

Note:
ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 serie, this function is relevant for ADC conversion start from external trigger. If internal trigger (SW start) is needed, perform ADC conversion start using function LL_ADC_REG_StartConversionSWStart().
Reference Manual to LL API cross reference:
CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
Parameters:
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_REG_TRIG_EXT_RISING
ADCx ADC instance
Return values:
None

Definition at line 3364 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart ( ADC_TypeDef * ADCx )

Start ADC group regular conversion.

Note:
On this STM32 serie, this function is relevant only for internal trigger (SW start), not for external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion start must be performed using function LL_ADC_REG_StartConversionExtTrig(). (if external trigger edge would have been set during ADC other settings, ADC conversion would start at trigger event as soon as ADC is enabled).
Reference Manual to LL API cross reference:
CR2 SWSTART LL_ADC_REG_StartConversionSWStart
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3345 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig ( ADC_TypeDef * ADCx )

Stop ADC group regular conversion from external trigger.

Note:
No more ADC conversion will start at next trigger event following the ADC stop conversion command. If a conversion is on-going, it will be completed.
On this STM32 serie, there is no specific command to stop a conversion on-going or to stop ADC converting in continuous mode. These actions can be performed using function LL_ADC_Disable().
Reference Manual to LL API cross reference:
CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3382 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Operation on ADC hierarchical scope: group injected

Functions
Operation on ADC hierarchical scope: group injected
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_INJ_StartConversionSWStart (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StartConversionExtTrig (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Start ADC group injected conversion from external trigger.
__STATIC_INLINE void | LL_ADC_INJ_StopConversionExtTrig (ADC_TypeDef *ADCx)
Stop ADC group injected conversion from external trigger.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.

Function Documentation

__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group injected conversion data, range fit for ADC resolution 12 bits.

Note:
For devices with feature oversampling: Oversampling can increase data width, function for extended range may be needed: LL_ADC_INJ_ReadConversionData32.
Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData12
JDR2 JDATA LL_ADC_INJ_ReadConversionData12
JDR3 JDATA LL_ADC_INJ_ReadConversionData12
JDR4 JDATA LL_ADC_INJ_ReadConversionData12
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x000 and Max_Data=0xFFF

Definition at line 3557 of file stm32f1xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JDRX_REGOFFSET_MASK.

__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32 | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | Rank
 | ) |  |

Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).

Reference Manual to LL API cross reference:
JDR1 JDATA LL_ADC_INJ_ReadConversionData32
JDR2 JDATA LL_ADC_INJ_ReadConversionData32
JDR3 JDATA LL_ADC_INJ_ReadConversionData32
JDR4 JDATA LL_ADC_INJ_ReadConversionData32
Parameters:
ADCx ADC instance
Rank This parameter can be one of the following values:
  • LL_ADC_INJ_RANK_1
  • LL_ADC_INJ_RANK_2
  • LL_ADC_INJ_RANK_3
  • LL_ADC_INJ_RANK_4
Return values:
Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

Definition at line 3530 of file stm32f1xx_ll_adc.h.

References __ADC_MASK_SHIFT, __ADC_PTR_REG_OFFSET, and ADC_INJ_JDRX_REGOFFSET_MASK.

__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig | ( | ADC_TypeDef * | ADCx,
 |  | uint32_t | ExternalTriggerEdge
 | ) |  |

Start ADC group injected conversion from external trigger.

Note:
ADC conversion will start at next trigger event (on the selected trigger edge) following the ADC start conversion command.
On this STM32 serie, this function is relevant for ADC conversion start from external trigger. If internal trigger (SW start) is needed, perform ADC conversion start using function LL_ADC_INJ_StartConversionSWStart().
Reference Manual to LL API cross reference:
CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
Parameters:
ExternalTriggerEdge This parameter can be one of the following values:
  • LL_ADC_INJ_TRIG_EXT_RISING
ADCx ADC instance
Return values:
None

Definition at line 3490 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart ( ADC_TypeDef * ADCx )

Start ADC group injected conversion.

Note:
On this STM32 serie, this function is relevant only for internal trigger (SW start), not for external trigger:
  • If ADC trigger has been set to software start, ADC conversion starts immediately.
  • If ADC trigger has been set to external trigger, ADC conversion start must be performed using function LL_ADC_INJ_StartConversionExtTrig(). (if external trigger edge would have been set during ADC other settings, ADC conversion would start at trigger event as soon as ADC is enabled).
Reference Manual to LL API cross reference:
CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3471 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig ( ADC_TypeDef * ADCx )

Stop ADC group injected conversion from external trigger.

Note:
No more ADC conversion will start at next trigger event following the ADC stop conversion command. If a conversion is on-going, it will be completed.
On this STM32 serie, there is no specific command to stop a conversion on-going or to stop ADC converting in continuous mode. These actions can be performed using function LL_ADC_Disable().
Reference Manual to LL API cross reference:
CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3508 of file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC flag management

Functions
ADC flag management
ADC Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 1 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode analog watchdog 1 of the ADC slave.

Function Documentation

__STATIC_INLINE void LL_ADC_ClearFlag_AWD1 ( ADC_TypeDef * ADCx )

Clear flag ADC analog watchdog 1.

Reference Manual to LL API cross reference:
SR AWD LL_ADC_ClearFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3653 of file stm32f1xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE void LL_ADC_ClearFlag_EOS ( ADC_TypeDef * ADCx )

Clear flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
SR EOC LL_ADC_ClearFlag_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3622 of file stm32f1xx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE void LL_ADC_ClearFlag_JEOS ( ADC_TypeDef * ADCx )

Clear flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
SR JEOC LL_ADC_ClearFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3638 of file stm32f1xx_ll_adc.h.

References LL_ADC_FLAG_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1 ( ADC_TypeDef * ADCx )

Get flag ADC analog watchdog 1 flag.

Reference Manual to LL API cross reference:
SR AWD LL_ADC_IsActiveFlag_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 3611 of file stm32f1xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS ( ADC_TypeDef * ADCx )

Get flag ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
SR EOC LL_ADC_IsActiveFlag_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 3580 of file stm32f1xx_ll_adc.h.

References LL_ADC_FLAG_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS ( ADC_TypeDef * ADCx )

Get flag ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
SR JEOC LL_ADC_IsActiveFlag_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 3596 of file stm32f1xx_ll_adc.h.

References LL_ADC_FLAG_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC analog watchdog 1 of the ADC master.

Reference Manual to LL API cross reference:
SR AWD LL_ADC_IsActiveFlag_MST_AWD1
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 3737 of file stm32f1xx_ll_adc.h.

References LL_ADC_FLAG_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sequence conversions of the ADC master.

Reference Manual to LL API cross reference:
SR EOC LL_ADC_IsActiveFlag_MST_EOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 3666 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of sequence conversions of the ADC master.

Reference Manual to LL API cross reference:
SR JEOC LL_ADC_IsActiveFlag_MST_JEOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 3702 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1 ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode analog watchdog 1 of the ADC slave.

Reference Manual to LL API cross reference:
SR AWD LL_ADC_IsActiveFlag_SLV_AWD1
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 3749 of file stm32f1xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, and LL_ADC_FLAG_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group regular end of sequence conversions of the ADC slave.

Reference Manual to LL API cross reference:
SR EOC LL_ADC_IsActiveFlag_SLV_EOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 3682 of file stm32f1xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, and LL_ADC_FLAG_EOS_SLV.

__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS ( ADC_Common_TypeDef * ADCxy_COMMON )

Get flag multimode ADC group injected end of sequence conversions of the ADC slave.

Reference Manual to LL API cross reference:
SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS
Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
State of bit (1 or 0).

Definition at line 3718 of file stm32f1xx_ll_adc.h.

References __ADC_PTR_REG_OFFSET, and LL_ADC_FLAG_JEOS_SLV.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC IT management

Functions
ADC IT management
ADC Exported Functions

Functions

__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).

Function Documentation

__STATIC_INLINE void LL_ADC_DisableIT_AWD1 ( ADC_TypeDef * ADCx )

Disable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
CR1 AWDIE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3845 of file stm32f1xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE void LL_ADC_DisableIT_EOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
CR1 EOCIE LL_ADC_DisableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3814 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_DisableIT_JEOS ( ADC_TypeDef * ADCx )

Disable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
CR1 JEOCIE LL_ADC_EnableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3830 of file stm32f1xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE void LL_ADC_EnableIT_AWD1 ( ADC_TypeDef * ADCx )

Enable interruption ADC analog watchdog 1.

Reference Manual to LL API cross reference:
CR1 AWDIE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3803 of file stm32f1xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE void LL_ADC_EnableIT_EOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group regular end of sequence conversions.

Reference Manual to LL API cross reference:
CR1 EOCIE LL_ADC_EnableIT_EOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3772 of file stm32f1xx_ll_adc.h.

__STATIC_INLINE void LL_ADC_EnableIT_JEOS ( ADC_TypeDef * ADCx )

Enable interruption ADC group injected end of sequence conversions.

Reference Manual to LL API cross reference:
CR1 JEOCIE LL_ADC_EnableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
None

Definition at line 3788 of file stm32f1xx_ll_adc.h.

References LL_ADC_IT_JEOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1 ( ADC_TypeDef * ADCx )

Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
CR1 AWDIE LL_ADC_EnableIT_AWD1
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 3890 of file stm32f1xx_ll_adc.h.

References LL_ADC_IT_AWD1.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
CR1 EOCIE LL_ADC_IsEnabledIT_EOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 3857 of file stm32f1xx_ll_adc.h.

References LL_ADC_IT_EOS.

__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS ( ADC_TypeDef * ADCx )

Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).

Reference Manual to LL API cross reference:
CR1 JEOCIE LL_ADC_EnableIT_JEOS
Parameters:
ADCx ADC instance
Return values:
State of bit (1 or 0).

Definition at line 3874 of file stm32f1xx_ll_adc.h.

References LL_ADC_IT_JEOS.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
ADC Exported Functions

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_ADC_CommonDeInit ( ADC_Common_TypeDef * ADCxy_COMMON )

De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.

Parameters:
ADCxy_COMMON ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are de-initialized
  • ERROR: not applicable

Definition at line 297 of file stm32f1xx_ll_adc.c.

References assert_param, LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_ADC1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_ADC_CommonInit | ( | ADC_Common_TypeDef * | ADCxy_COMMON,
 |  | LL_ADC_CommonInitTypeDef * | ADC_CommonInitStruct
 | ) |  |

Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).

Note:
The setting of ADC common parameters is conditioned to ADC instances state: All ADC instances belonging to the same ADC common instance must be disabled.
Parameters:
ADCxy_COMMON | ADC common instance (can be set directly from CMSIS definition or by using helper macro __LL_ADC_COMMON_INSTANCE() )
ADC_CommonInitStruct | Pointer to a LL_ADC_CommonInitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC common registers are initialized
  • ERROR: ADC common registers are not initialized

Definition at line 326 of file stm32f1xx_ll_adc.c.

References __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE, assert_param, IS_LL_ADC_MULTI_MODE, LL_ADC_MULTI_INDEPENDENT, and LL_ADC_CommonInitTypeDef::Multimode.

void LL_ADC_CommonStructInit ( LL_ADC_CommonInitTypeDef * ADC_CommonInitStruct )

Set each LL_ADC_CommonInitTypeDef field to default value.

Parameters:
ADC_CommonInitStruct Pointer to a LL_ADC_CommonInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 384 of file stm32f1xx_ll_adc.c.

References LL_ADC_MULTI_INDEPENDENT, and LL_ADC_CommonInitTypeDef::Multimode.

ErrorStatus LL_ADC_DeInit ( ADC_TypeDef * ADCx )

De-initialize registers of the selected ADC instance to their default reset values.

Note:
To reset all ADC instances quickly (perform a hard reset), use function LL_ADC_CommonDeInit().
Parameters:
ADCx ADC instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are de-initialized
  • ERROR: ADC registers are not de-initialized

Definition at line 406 of file stm32f1xx_ll_adc.c.

References assert_param, LL_ADC_Disable(), LL_ADC_FLAG_AWD1, LL_ADC_FLAG_EOS, LL_ADC_FLAG_JEOS, LL_ADC_FLAG_JSTRT, LL_ADC_FLAG_STRT, LL_ADC_INJ_SetTriggerSource(), LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_IsEnabled(), LL_ADC_REG_SetTriggerSource(), and LL_ADC_REG_TRIG_SOFTWARE.

ErrorStatus LL_ADC_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_InitTypeDef * | ADC_InitStruct
 | ) |  |

Initialize some features of ADC instance.

Note:
These parameters have an impact on ADC scope: ADC instance. Affects both group regular and group injected (availability of ADC group injected depends on STM32 families). Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: ADC instance .
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, some other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 568 of file stm32f1xx_ll_adc.c.

References assert_param, LL_ADC_InitTypeDef::DataAlignment, IS_LL_ADC_DATA_ALIGN, IS_LL_ADC_SCAN_SELECTION, LL_ADC_IsEnabled(), and LL_ADC_InitTypeDef::SequencersScanMode.

ErrorStatus LL_ADC_INJ_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_INJ_InitTypeDef * | ADC_INJ_InitStruct
 | ) |  |

Initialize some features of ADC group injected.

Note:
These parameters have an impact on ADC scope: ADC group injected. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "INJ").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_INJ_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_INJ_InitStruct | Pointer to a LL_ADC_INJ_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 792 of file stm32f1xx_ll_adc.c.

References assert_param, IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_INJ_SEQ_SCAN_LENGTH, IS_LL_ADC_INJ_TRIG_AUTO, IS_LL_ADC_INJ_TRIG_SOURCE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_INJ_SetSequencerLength(), LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

void LL_ADC_INJ_StructInit ( LL_ADC_INJ_InitTypeDef * ADC_INJ_InitStruct )

Set each LL_ADC_INJ_InitTypeDef field to default value.

Parameters:
ADC_INJ_InitStruct Pointer to a LL_ADC_INJ_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 873 of file stm32f1xx_ll_adc.c.

References LL_ADC_INJ_SEQ_DISCONT_DISABLE, LL_ADC_INJ_SEQ_SCAN_DISABLE, LL_ADC_INJ_TRIG_INDEPENDENT, LL_ADC_INJ_TRIG_SOFTWARE, LL_ADC_INJ_InitTypeDef::SequencerDiscont, LL_ADC_INJ_InitTypeDef::SequencerLength, LL_ADC_INJ_InitTypeDef::TrigAuto, and LL_ADC_INJ_InitTypeDef::TriggerSource.

ErrorStatus LL_ADC_REG_Init | ( | ADC_TypeDef * | ADCx,
 |  | LL_ADC_REG_InitTypeDef * | ADC_REG_InitStruct
 | ) |  |

Initialize some features of ADC group regular.

Note:
These parameters have an impact on ADC scope: ADC group regular. Refer to corresponding unitary functions into Configuration of ADC hierarchical scope: group regular (functions with prefix "REG").
The setting of these parameters by function LL_ADC_Init() is conditioned to ADC state: ADC instance must be disabled. This condition is applied to all ADC features, for efficiency and compatibility over all STM32 families. However, the different features can be set under different ADC state conditions (setting possible with ADC enabled without conversion on going, ADC enabled with conversion on going, ...) Each feature can be updated afterwards with a unitary function and potentially with ADC in a different state than disabled, refer to description of each function for setting conditioned to ADC state.
After using this function, other features must be configured using LL unitary functions. The minimum configuration remaining to be done is:
  • Set ADC group regular or group injected sequencer: map channel on the selected sequencer rank. Refer to function LL_ADC_REG_SetSequencerRanks().
  • Set ADC channel sampling time Refer to function LL_ADC_SetChannelSamplingTime();
Parameters:
ADCx | ADC instance
ADC_REG_InitStruct | Pointer to a LL_ADC_REG_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: ADC registers are initialized
  • ERROR: ADC registers are not initialized

Definition at line 658 of file stm32f1xx_ll_adc.c.

References assert_param, LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, IS_LL_ADC_REG_CONTINUOUS_MODE, IS_LL_ADC_REG_DMA_TRANSFER, IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE, IS_LL_ADC_REG_SEQ_SCAN_LENGTH, IS_LL_ADC_REG_TRIG_SOURCE, LL_ADC_IsEnabled(), LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_SetSequencerLength(), LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_REG_StructInit ( LL_ADC_REG_InitTypeDef * ADC_REG_InitStruct )

Set each LL_ADC_REG_InitTypeDef field to default value.

Parameters:
ADC_REG_InitStruct Pointer to a LL_ADC_REG_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 746 of file stm32f1xx_ll_adc.c.

References LL_ADC_REG_InitTypeDef::ContinuousMode, LL_ADC_REG_InitTypeDef::DMATransfer, LL_ADC_REG_CONV_SINGLE, LL_ADC_REG_DMA_TRANSFER_NONE, LL_ADC_REG_SEQ_DISCONT_DISABLE, LL_ADC_REG_SEQ_SCAN_DISABLE, LL_ADC_REG_TRIG_SOFTWARE, LL_ADC_REG_InitTypeDef::SequencerDiscont, LL_ADC_REG_InitTypeDef::SequencerLength, and LL_ADC_REG_InitTypeDef::TriggerSource.

void LL_ADC_StructInit ( LL_ADC_InitTypeDef * ADC_InitStruct )

Set each LL_ADC_InitTypeDef field to default value.

Parameters:
ADC_InitStruct Pointer to a LL_ADC_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 612 of file stm32f1xx_ll_adc.c.

References LL_ADC_InitTypeDef::DataAlignment, LL_ADC_DATA_ALIGN_RIGHT, LL_ADC_SEQ_SCAN_ENABLE, and LL_ADC_InitTypeDef::SequencersScanMode.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: BUS

Modules
BUS
STM32F1xx_LL_Driver

Modules

BUS Exported Constants
BUS Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for BUS registers.

Register | Bit | Function
AHBENR | CRCEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | DMA1EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | DMA2EN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | ETHMACEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | ETHMACRXEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | ETHMACTXEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | FLITFEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | FSMCEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | OTGFSEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | SDIOEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
 | SRAMEN | LL_AHB1_GRP1_DisableClock
 |  | LL_AHB1_GRP1_EnableClock
 |  | LL_AHB1_GRP1_IsEnabledClock
APB1ENR | BKPEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | CAN1EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | CAN2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | CECEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | DACEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | I2C1EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | I2C2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | PWREN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | SPI2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | SPI3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM12EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM13EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM14EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM4EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM5EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM6EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | TIM7EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | UART4EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | UART5EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | USART2EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | USART3EN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | USBEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
 | WWDGEN | LL_APB1_GRP1_DisableClock
 |  | LL_APB1_GRP1_EnableClock
 |  | LL_APB1_GRP1_IsEnabledClock
APB1RSTR | BKPRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | CAN1RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | CAN2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | CECRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | DACRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | I2C1RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | I2C2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | PWRRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | SPI2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | SPI3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM12RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM13RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM14RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM4RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM5RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM6RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | TIM7RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | UART4RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | UART5RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | USART2RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | USART3RST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | USBRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
 | WWDGRST | LL_APB1_GRP1_ForceReset
 |  | LL_APB1_GRP1_ReleaseReset
APB2ENR | ADC1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | ADC2EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | ADC3EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | AFIOEN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | IOPAEN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | IOPBEN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | IOPCEN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | IOPDEN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | IOPEEN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | IOPFEN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | IOPGEN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | SPI1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM10EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM11EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM15EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM16EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM17EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM8EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | TIM9EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
 | USART1EN | LL_APB2_GRP1_DisableClock
 |  | LL_APB2_GRP1_EnableClock
 |  | LL_APB2_GRP1_IsEnabledClock
APB2RSTR | ADC1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | ADC2RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | ADC3RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | AFIORST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | IOPARST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | IOPBRST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | IOPCRST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | IOPDRST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | IOPERST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | IOPFRST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | IOPGRST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | SPI1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM10RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM11RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM15RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM16RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM17RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM8RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | TIM9RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
 | USART1RST | LL_APB2_GRP1_ForceReset
 |  | LL_APB2_GRP1_ReleaseReset
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: AHB1 GRP1 PERIPH

Defines
AHB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
#define | LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
#define | LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN

Define Documentation

#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 95 of file stm32f1xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN

Definition at line 96 of file stm32f1xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN

Definition at line 97 of file stm32f1xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN

Definition at line 106 of file stm32f1xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN

Definition at line 114 of file stm32f1xx_ll_bus.h.

#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN

Definition at line 116 of file stm32f1xx_ll_bus.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB1 GRP1 PERIPH

Defines
APB1 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
#define | LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
#define | LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
#define | LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN

Define Documentation

#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 124 of file stm32f1xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN

Definition at line 125 of file stm32f1xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN

Definition at line 127 of file stm32f1xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN

Definition at line 138 of file stm32f1xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN

Definition at line 140 of file stm32f1xx_ll_bus.h.

Referenced by LL_I2C_DeInit().

#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN

Definition at line 142 of file stm32f1xx_ll_bus.h.

Referenced by LL_PWR_DeInit().

#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN

Definition at line 144 of file stm32f1xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN

Definition at line 158 of file stm32f1xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN

Definition at line 159 of file stm32f1xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN

Definition at line 161 of file stm32f1xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN

Definition at line 178 of file stm32f1xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN

Definition at line 180 of file stm32f1xx_ll_bus.h.

Referenced by LL_USART_DeInit().

#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN

Definition at line 183 of file stm32f1xx_ll_bus.h.

#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN

Definition at line 185 of file stm32f1xx_ll_bus.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB2 GRP1 PERIPH

Defines
APB2 GRP1 PERIPH
BUS Exported Constants

Defines

#define | LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
#define | LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
#define | LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
#define | LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
#define | LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
#define | LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
#define | LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
#define | LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN

Define Documentation

#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN

Definition at line 194 of file stm32f1xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit().

#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN

Definition at line 196 of file stm32f1xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN

Definition at line 201 of file stm32f1xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU

Definition at line 193 of file stm32f1xx_ll_bus.h.

#define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN

Definition at line 202 of file stm32f1xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN

Definition at line 203 of file stm32f1xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN

Definition at line 204 of file stm32f1xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN

Definition at line 205 of file stm32f1xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN

Definition at line 207 of file stm32f1xx_ll_bus.h.

Referenced by LL_GPIO_DeInit().

#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN

Definition at line 215 of file stm32f1xx_ll_bus.h.

Referenced by LL_SPI_DeInit().

#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN

Definition at line 231 of file stm32f1xx_ll_bus.h.

Referenced by LL_TIM_DeInit().

#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN

Definition at line 238 of file stm32f1xx_ll_bus.h.

Referenced by LL_USART_DeInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: AHB1

Functions
AHB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.

Function Documentation

__STATIC_INLINE void LL_AHB1_GRP1_DisableClock ( uint32_t Periphs )

Disable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHBENR CRCEN LL_AHB1_GRP1_DisableClock
AHBENR DMA1EN LL_AHB1_GRP1_DisableClock
AHBENR DMA2EN LL_AHB1_GRP1_DisableClock
AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock
AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock
AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock
AHBENR FLITFEN LL_AHB1_GRP1_DisableClock
AHBENR FSMCEN LL_AHB1_GRP1_DisableClock
AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock
AHBENR SDIOEN LL_AHB1_GRP1_DisableClock
AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2 (*)
  • LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_FSMC (*)
  • LL_AHB1_GRP1_PERIPH_OTGFS (*)
  • LL_AHB1_GRP1_PERIPH_SDIO (*)
  • LL_AHB1_GRP1_PERIPH_SRAM
(*) value not defined in all devices.
Return values:
None

Definition at line 359 of file stm32f1xx_ll_bus.h.

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock ( uint32_t Periphs )

Enable AHB1 peripherals clock.

Reference Manual to LL API cross reference:
AHBENR CRCEN LL_AHB1_GRP1_EnableClock
AHBENR DMA1EN LL_AHB1_GRP1_EnableClock
AHBENR DMA2EN LL_AHB1_GRP1_EnableClock
AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock
AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock
AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock
AHBENR FLITFEN LL_AHB1_GRP1_EnableClock
AHBENR FSMCEN LL_AHB1_GRP1_EnableClock
AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock
AHBENR SDIOEN LL_AHB1_GRP1_EnableClock
AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2 (*)
  • LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_FSMC (*)
  • LL_AHB1_GRP1_PERIPH_OTGFS (*)
  • LL_AHB1_GRP1_PERIPH_SDIO (*)
  • LL_AHB1_GRP1_PERIPH_SRAM
(*) value not defined in all devices.
Return values:
None

Definition at line 287 of file stm32f1xx_ll_bus.h.

__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if AHB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock
AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock
AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock
AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock
AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock
AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock
AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock
AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock
AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock
AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2 (*)
  • LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  • LL_AHB1_GRP1_PERIPH_FLASH
  • LL_AHB1_GRP1_PERIPH_FSMC (*)
  • LL_AHB1_GRP1_PERIPH_OTGFS (*)
  • LL_AHB1_GRP1_PERIPH_SDIO (*)
  • LL_AHB1_GRP1_PERIPH_SRAM
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 325 of file stm32f1xx_ll_bus.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB1

Functions
APB1
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.

Function Documentation

__STATIC_INLINE void LL_APB1_GRP1_DisableClock ( uint32_t Periphs )

Disable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR BKPEN LL_APB1_GRP1_DisableClock
APB1ENR CAN1EN LL_APB1_GRP1_DisableClock
APB1ENR CAN2EN LL_APB1_GRP1_DisableClock
APB1ENR CECEN LL_APB1_GRP1_DisableClock
APB1ENR DACEN LL_APB1_GRP1_DisableClock
APB1ENR I2C1EN LL_APB1_GRP1_DisableClock
APB1ENR I2C2EN LL_APB1_GRP1_DisableClock
APB1ENR PWREN LL_APB1_GRP1_DisableClock
APB1ENR SPI2EN LL_APB1_GRP1_DisableClock
APB1ENR SPI3EN LL_APB1_GRP1_DisableClock
APB1ENR TIM12EN LL_APB1_GRP1_DisableClock
APB1ENR TIM13EN LL_APB1_GRP1_DisableClock
APB1ENR TIM14EN LL_APB1_GRP1_DisableClock
APB1ENR TIM2EN LL_APB1_GRP1_DisableClock
APB1ENR TIM3EN LL_APB1_GRP1_DisableClock
APB1ENR TIM4EN LL_APB1_GRP1_DisableClock
APB1ENR TIM5EN LL_APB1_GRP1_DisableClock
APB1ENR TIM6EN LL_APB1_GRP1_DisableClock
APB1ENR TIM7EN LL_APB1_GRP1_DisableClock
APB1ENR UART4EN LL_APB1_GRP1_DisableClock
APB1ENR UART5EN LL_APB1_GRP1_DisableClock
APB1ENR USART2EN LL_APB1_GRP1_DisableClock
APB1ENR USART3EN LL_APB1_GRP1_DisableClock
APB1ENR USBEN LL_APB1_GRP1_DisableClock
APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_BKP
  • LL_APB1_GRP1_PERIPH_CAN1 (*)
  • LL_APB1_GRP1_PERIPH_CAN2 (*)
  • LL_APB1_GRP1_PERIPH_CEC (*)
  • LL_APB1_GRP1_PERIPH_DAC1 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3 (*)
  • LL_APB1_GRP1_PERIPH_TIM12 (*)
  • LL_APB1_GRP1_PERIPH_TIM13 (*)
  • LL_APB1_GRP1_PERIPH_TIM14 (*)
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6 (*)
  • LL_APB1_GRP1_PERIPH_TIM7 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_WWDG
(*) value not defined in all devices.
Return values:
None

Definition at line 593 of file stm32f1xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_EnableClock ( uint32_t Periphs )

Enable APB1 peripherals clock.

Reference Manual to LL API cross reference:
APB1ENR BKPEN LL_APB1_GRP1_EnableClock
APB1ENR CAN1EN LL_APB1_GRP1_EnableClock
APB1ENR CAN2EN LL_APB1_GRP1_EnableClock
APB1ENR CECEN LL_APB1_GRP1_EnableClock
APB1ENR DACEN LL_APB1_GRP1_EnableClock
APB1ENR I2C1EN LL_APB1_GRP1_EnableClock
APB1ENR I2C2EN LL_APB1_GRP1_EnableClock
APB1ENR PWREN LL_APB1_GRP1_EnableClock
APB1ENR SPI2EN LL_APB1_GRP1_EnableClock
APB1ENR SPI3EN LL_APB1_GRP1_EnableClock
APB1ENR TIM12EN LL_APB1_GRP1_EnableClock
APB1ENR TIM13EN LL_APB1_GRP1_EnableClock
APB1ENR TIM14EN LL_APB1_GRP1_EnableClock
APB1ENR TIM2EN LL_APB1_GRP1_EnableClock
APB1ENR TIM3EN LL_APB1_GRP1_EnableClock
APB1ENR TIM4EN LL_APB1_GRP1_EnableClock
APB1ENR TIM5EN LL_APB1_GRP1_EnableClock
APB1ENR TIM6EN LL_APB1_GRP1_EnableClock
APB1ENR TIM7EN LL_APB1_GRP1_EnableClock
APB1ENR UART4EN LL_APB1_GRP1_EnableClock
APB1ENR UART5EN LL_APB1_GRP1_EnableClock
APB1ENR USART2EN LL_APB1_GRP1_EnableClock
APB1ENR USART3EN LL_APB1_GRP1_EnableClock
APB1ENR USBEN LL_APB1_GRP1_EnableClock
APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_BKP
  • LL_APB1_GRP1_PERIPH_CAN1 (*)
  • LL_APB1_GRP1_PERIPH_CAN2 (*)
  • LL_APB1_GRP1_PERIPH_CEC (*)
  • LL_APB1_GRP1_PERIPH_DAC1 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3 (*)
  • LL_APB1_GRP1_PERIPH_TIM12 (*)
  • LL_APB1_GRP1_PERIPH_TIM13 (*)
  • LL_APB1_GRP1_PERIPH_TIM14 (*)
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6 (*)
  • LL_APB1_GRP1_PERIPH_TIM7 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_WWDG
(*) value not defined in all devices.
Return values:
None

Definition at line 465 of file stm32f1xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ForceReset ( uint32_t Periphs )

Force APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR BKPRST LL_APB1_GRP1_ForceReset
APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset
APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset
APB1RSTR CECRST LL_APB1_GRP1_ForceReset
APB1RSTR DACRST LL_APB1_GRP1_ForceReset
APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset
APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset
APB1RSTR PWRRST LL_APB1_GRP1_ForceReset
APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset
APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset
APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset
APB1RSTR UART4RST LL_APB1_GRP1_ForceReset
APB1RSTR UART5RST LL_APB1_GRP1_ForceReset
APB1RSTR USART2RST LL_APB1_GRP1_ForceReset
APB1RSTR USART3RST LL_APB1_GRP1_ForceReset
APB1RSTR USBRST LL_APB1_GRP1_ForceReset
APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_ALL
  • LL_APB1_GRP1_PERIPH_BKP
  • LL_APB1_GRP1_PERIPH_CAN1 (*)
  • LL_APB1_GRP1_PERIPH_CAN2 (*)
  • LL_APB1_GRP1_PERIPH_CEC (*)
  • LL_APB1_GRP1_PERIPH_DAC1 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3 (*)
  • LL_APB1_GRP1_PERIPH_TIM12 (*)
  • LL_APB1_GRP1_PERIPH_TIM13 (*)
  • LL_APB1_GRP1_PERIPH_TIM14 (*)
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6 (*)
  • LL_APB1_GRP1_PERIPH_TIM7 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_WWDG
(*) value not defined in all devices.
Return values:
None

Definition at line 656 of file stm32f1xx_ll_bus.h.

Referenced by LL_I2C_DeInit(), LL_PWR_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB1 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock
APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock
APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock
APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock
APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock
APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock
APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock
APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock
APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock
APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock
APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock
APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock
APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_BKP
  • LL_APB1_GRP1_PERIPH_CAN1 (*)
  • LL_APB1_GRP1_PERIPH_CAN2 (*)
  • LL_APB1_GRP1_PERIPH_CEC (*)
  • LL_APB1_GRP1_PERIPH_DAC1 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3 (*)
  • LL_APB1_GRP1_PERIPH_TIM12 (*)
  • LL_APB1_GRP1_PERIPH_TIM13 (*)
  • LL_APB1_GRP1_PERIPH_TIM14 (*)
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6 (*)
  • LL_APB1_GRP1_PERIPH_TIM7 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_WWDG
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 531 of file stm32f1xx_ll_bus.h.

__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB1 peripherals reset.

Reference Manual to LL API cross reference:
APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset
APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset
APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset
APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset
APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset
APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset
APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset
APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset
APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset
APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset
APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset
APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset
APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB1_GRP1_PERIPH_ALL
  • LL_APB1_GRP1_PERIPH_BKP
  • LL_APB1_GRP1_PERIPH_CAN1 (*)
  • LL_APB1_GRP1_PERIPH_CAN2 (*)
  • LL_APB1_GRP1_PERIPH_CEC (*)
  • LL_APB1_GRP1_PERIPH_DAC1 (*)
  • LL_APB1_GRP1_PERIPH_I2C1
  • LL_APB1_GRP1_PERIPH_I2C2 (*)
  • LL_APB1_GRP1_PERIPH_PWR
  • LL_APB1_GRP1_PERIPH_SPI2 (*)
  • LL_APB1_GRP1_PERIPH_SPI3 (*)
  • LL_APB1_GRP1_PERIPH_TIM12 (*)
  • LL_APB1_GRP1_PERIPH_TIM13 (*)
  • LL_APB1_GRP1_PERIPH_TIM14 (*)
  • LL_APB1_GRP1_PERIPH_TIM2
  • LL_APB1_GRP1_PERIPH_TIM3
  • LL_APB1_GRP1_PERIPH_TIM4 (*)
  • LL_APB1_GRP1_PERIPH_TIM5 (*)
  • LL_APB1_GRP1_PERIPH_TIM6 (*)
  • LL_APB1_GRP1_PERIPH_TIM7 (*)
  • LL_APB1_GRP1_PERIPH_UART4 (*)
  • LL_APB1_GRP1_PERIPH_UART5 (*)
  • LL_APB1_GRP1_PERIPH_USART2
  • LL_APB1_GRP1_PERIPH_USART3 (*)
  • LL_APB1_GRP1_PERIPH_USB (*)
  • LL_APB1_GRP1_PERIPH_WWDG
(*) value not defined in all devices.
Return values:
None

Definition at line 719 of file stm32f1xx_ll_bus.h.

Referenced by LL_I2C_DeInit(), LL_PWR_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB2

Functions
APB2
BUS Exported Functions

Functions

__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.

Function Documentation

__STATIC_INLINE void LL_APB2_GRP1_DisableClock ( uint32_t Periphs )

Disable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR ADC1EN LL_APB2_GRP1_DisableClock
APB2ENR ADC2EN LL_APB2_GRP1_DisableClock
APB2ENR ADC3EN LL_APB2_GRP1_DisableClock
APB2ENR AFIOEN LL_APB2_GRP1_DisableClock
APB2ENR IOPAEN LL_APB2_GRP1_DisableClock
APB2ENR IOPBEN LL_APB2_GRP1_DisableClock
APB2ENR IOPCEN LL_APB2_GRP1_DisableClock
APB2ENR IOPDEN LL_APB2_GRP1_DisableClock
APB2ENR IOPEEN LL_APB2_GRP1_DisableClock
APB2ENR IOPFEN LL_APB2_GRP1_DisableClock
APB2ENR IOPGEN LL_APB2_GRP1_DisableClock
APB2ENR SPI1EN LL_APB2_GRP1_DisableClock
APB2ENR TIM10EN LL_APB2_GRP1_DisableClock
APB2ENR TIM11EN LL_APB2_GRP1_DisableClock
APB2ENR TIM15EN LL_APB2_GRP1_DisableClock
APB2ENR TIM16EN LL_APB2_GRP1_DisableClock
APB2ENR TIM17EN LL_APB2_GRP1_DisableClock
APB2ENR TIM1EN LL_APB2_GRP1_DisableClock
APB2ENR TIM8EN LL_APB2_GRP1_DisableClock
APB2ENR TIM9EN LL_APB2_GRP1_DisableClock
APB2ENR USART1EN LL_APB2_GRP1_DisableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ADC1
  • LL_APB2_GRP1_PERIPH_ADC2 (*)
  • LL_APB2_GRP1_PERIPH_ADC3 (*)
  • LL_APB2_GRP1_PERIPH_AFIO
  • LL_APB2_GRP1_PERIPH_GPIOA
  • LL_APB2_GRP1_PERIPH_GPIOB
  • LL_APB2_GRP1_PERIPH_GPIOC
  • LL_APB2_GRP1_PERIPH_GPIOD
  • LL_APB2_GRP1_PERIPH_GPIOE (*)
  • LL_APB2_GRP1_PERIPH_GPIOF (*)
  • LL_APB2_GRP1_PERIPH_GPIOG (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM10 (*)
  • LL_APB2_GRP1_PERIPH_TIM11 (*)
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16 (*)
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_TIM9 (*)
  • LL_APB2_GRP1_PERIPH_USART1
(*) value not defined in all devices.
Return values:
None

Definition at line 893 of file stm32f1xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_EnableClock ( uint32_t Periphs )

Enable APB2 peripherals clock.

Reference Manual to LL API cross reference:
APB2ENR ADC1EN LL_APB2_GRP1_EnableClock
APB2ENR ADC2EN LL_APB2_GRP1_EnableClock
APB2ENR ADC3EN LL_APB2_GRP1_EnableClock
APB2ENR AFIOEN LL_APB2_GRP1_EnableClock
APB2ENR IOPAEN LL_APB2_GRP1_EnableClock
APB2ENR IOPBEN LL_APB2_GRP1_EnableClock
APB2ENR IOPCEN LL_APB2_GRP1_EnableClock
APB2ENR IOPDEN LL_APB2_GRP1_EnableClock
APB2ENR IOPEEN LL_APB2_GRP1_EnableClock
APB2ENR IOPFEN LL_APB2_GRP1_EnableClock
APB2ENR IOPGEN LL_APB2_GRP1_EnableClock
APB2ENR SPI1EN LL_APB2_GRP1_EnableClock
APB2ENR TIM10EN LL_APB2_GRP1_EnableClock
APB2ENR TIM11EN LL_APB2_GRP1_EnableClock
APB2ENR TIM15EN LL_APB2_GRP1_EnableClock
APB2ENR TIM16EN LL_APB2_GRP1_EnableClock
APB2ENR TIM17EN LL_APB2_GRP1_EnableClock
APB2ENR TIM1EN LL_APB2_GRP1_EnableClock
APB2ENR TIM8EN LL_APB2_GRP1_EnableClock
APB2ENR TIM9EN LL_APB2_GRP1_EnableClock
APB2ENR USART1EN LL_APB2_GRP1_EnableClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ADC1
  • LL_APB2_GRP1_PERIPH_ADC2 (*)
  • LL_APB2_GRP1_PERIPH_ADC3 (*)
  • LL_APB2_GRP1_PERIPH_AFIO
  • LL_APB2_GRP1_PERIPH_GPIOA
  • LL_APB2_GRP1_PERIPH_GPIOB
  • LL_APB2_GRP1_PERIPH_GPIOC
  • LL_APB2_GRP1_PERIPH_GPIOD
  • LL_APB2_GRP1_PERIPH_GPIOE (*)
  • LL_APB2_GRP1_PERIPH_GPIOF (*)
  • LL_APB2_GRP1_PERIPH_GPIOG (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM10 (*)
  • LL_APB2_GRP1_PERIPH_TIM11 (*)
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16 (*)
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_TIM9 (*)
  • LL_APB2_GRP1_PERIPH_USART1
(*) value not defined in all devices.
Return values:
None

Definition at line 781 of file stm32f1xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ForceReset ( uint32_t Periphs )

Force APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset
APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset
APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset
APB2RSTR AFIORST LL_APB2_GRP1_ForceReset
APB2RSTR IOPARST LL_APB2_GRP1_ForceReset
APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset
APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset
APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset
APB2RSTR IOPERST LL_APB2_GRP1_ForceReset
APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset
APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset
APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset
APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset
APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ALL
  • LL_APB2_GRP1_PERIPH_ADC1
  • LL_APB2_GRP1_PERIPH_ADC2 (*)
  • LL_APB2_GRP1_PERIPH_ADC3 (*)
  • LL_APB2_GRP1_PERIPH_AFIO
  • LL_APB2_GRP1_PERIPH_GPIOA
  • LL_APB2_GRP1_PERIPH_GPIOB
  • LL_APB2_GRP1_PERIPH_GPIOC
  • LL_APB2_GRP1_PERIPH_GPIOD
  • LL_APB2_GRP1_PERIPH_GPIOE (*)
  • LL_APB2_GRP1_PERIPH_GPIOF (*)
  • LL_APB2_GRP1_PERIPH_GPIOG (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM10 (*)
  • LL_APB2_GRP1_PERIPH_TIM11 (*)
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16 (*)
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_TIM9 (*)
  • LL_APB2_GRP1_PERIPH_USART1
(*) value not defined in all devices.
Return values:
None

Definition at line 948 of file stm32f1xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_GPIO_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock ( uint32_t Periphs )

Check if APB2 peripheral clock is enabled or not.

Reference Manual to LL API cross reference:
APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock
APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock
APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock
APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock
APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock
APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock
APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock
APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock
APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock
APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock
APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock
APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock
APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ADC1
  • LL_APB2_GRP1_PERIPH_ADC2 (*)
  • LL_APB2_GRP1_PERIPH_ADC3 (*)
  • LL_APB2_GRP1_PERIPH_AFIO
  • LL_APB2_GRP1_PERIPH_GPIOA
  • LL_APB2_GRP1_PERIPH_GPIOB
  • LL_APB2_GRP1_PERIPH_GPIOC
  • LL_APB2_GRP1_PERIPH_GPIOD
  • LL_APB2_GRP1_PERIPH_GPIOE (*)
  • LL_APB2_GRP1_PERIPH_GPIOF (*)
  • LL_APB2_GRP1_PERIPH_GPIOG (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM10 (*)
  • LL_APB2_GRP1_PERIPH_TIM11 (*)
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16 (*)
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_TIM9 (*)
  • LL_APB2_GRP1_PERIPH_USART1
(*) value not defined in all devices.
Return values:
State of Periphs (1 or 0).

Definition at line 839 of file stm32f1xx_ll_bus.h.

__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset ( uint32_t Periphs )

Release APB2 peripherals reset.

Reference Manual to LL API cross reference:
APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset
APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset
APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset
APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset
APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset
APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset
APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset
APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset
APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset
APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset
APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset
APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset
APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_APB2_GRP1_PERIPH_ALL
  • LL_APB2_GRP1_PERIPH_ADC1
  • LL_APB2_GRP1_PERIPH_ADC2 (*)
  • LL_APB2_GRP1_PERIPH_ADC3 (*)
  • LL_APB2_GRP1_PERIPH_AFIO
  • LL_APB2_GRP1_PERIPH_GPIOA
  • LL_APB2_GRP1_PERIPH_GPIOB
  • LL_APB2_GRP1_PERIPH_GPIOC
  • LL_APB2_GRP1_PERIPH_GPIOD
  • LL_APB2_GRP1_PERIPH_GPIOE (*)
  • LL_APB2_GRP1_PERIPH_GPIOF (*)
  • LL_APB2_GRP1_PERIPH_GPIOG (*)
  • LL_APB2_GRP1_PERIPH_SPI1
  • LL_APB2_GRP1_PERIPH_TIM10 (*)
  • LL_APB2_GRP1_PERIPH_TIM11 (*)
  • LL_APB2_GRP1_PERIPH_TIM15 (*)
  • LL_APB2_GRP1_PERIPH_TIM16 (*)
  • LL_APB2_GRP1_PERIPH_TIM17 (*)
  • LL_APB2_GRP1_PERIPH_TIM1
  • LL_APB2_GRP1_PERIPH_TIM8 (*)
  • LL_APB2_GRP1_PERIPH_TIM9 (*)
  • LL_APB2_GRP1_PERIPH_USART1
(*) value not defined in all devices.
Return values:
None

Definition at line 1003 of file stm32f1xx_ll_bus.h.

Referenced by LL_ADC_CommonDeInit(), LL_GPIO_DeInit(), LL_SPI_DeInit(), LL_TIM_DeInit(), and LL_USART_DeInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CORTEX

Modules
CORTEX
STM32F1xx_LL_Driver

Modules

CORTEX Exported Constants
CORTEX Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for CORTEX registers.

Register | Bit | Function
SCB_CPUID | ARCHITECTURE | LL_CPUID_GetConstant
 | IMPLEMENTER | LL_CPUID_GetImplementer
 | PARTNO | LL_CPUID_GetParNo
 | REVISION | LL_CPUID_GetRevision
 | VARIANT | LL_CPUID_GetVariant
SCB_SCR | SEVEONPEND | LL_LPM_DisableEventOnPend
 |  | LL_LPM_EnableEventOnPend
 | SLEEPDEEP | LL_LPM_EnableDeepSleep
 |  | LL_LPM_EnableSleep
 | SLEEPONEXIT | LL_LPM_DisableSleepOnExit
 |  | LL_LPM_EnableSleepOnExit
SCB_SHCSR | MEMFAULTENA | LL_HANDLER_DisableFault
 |  | LL_HANDLER_EnableFault
STK_CTRL | CLKSOURCE | LL_SYSTICK_GetClkSource
 |  | LL_SYSTICK_SetClkSource
 | COUNTFLAG | LL_SYSTICK_IsActiveCounterFlag
 | TICKINT | LL_SYSTICK_DisableIT
 |  | LL_SYSTICK_EnableIT
 |  | LL_SYSTICK_IsEnabledIT
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SYSTICK Clock Source

Defines
SYSTICK Clock Source
CORTEX Exported Constants

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

Define Documentation

#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk

AHB clock selected as SysTick clock source.

Definition at line 90 of file stm32f1xx_ll_cortex.h.

Referenced by LL_SYSTICK_GetClkSource(), and LL_SYSTICK_SetClkSource().

#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U

AHB clock divided by 8 selected as SysTick clock source.

Definition at line 89 of file stm32f1xx_ll_cortex.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Handler Fault type

Defines
Handler Fault type
CORTEX Exported Constants

Defines

#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Define Documentation

#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk

Bus fault

Definition at line 99 of file stm32f1xx_ll_cortex.h.

#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Memory management fault

Definition at line 100 of file stm32f1xx_ll_cortex.h.

#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk

Usage fault

Definition at line 98 of file stm32f1xx_ll_cortex.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SYSTICK

Functions
SYSTICK
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_SYSTICK_DisableIT ( void )

Disable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_DisableIT
Return values:
None

Definition at line 301 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_EnableIT ( void )

Enable SysTick exception request.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_EnableIT
Return values:
None

Definition at line 291 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource ( void )

Get the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
Return values:
Returned value can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK

Definition at line 281 of file stm32f1xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag ( void )

This function checks if the Systick counter flag is active or not.

Note:
It can be used in timeout function on application side.
Reference Manual to LL API cross reference:
STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
Return values:
State of bit (1 or 0).

Definition at line 249 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT ( void )

Checks if the SYSTICK interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
Return values:
State of bit (1 or 0).

Definition at line 311 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE void LL_SYSTICK_SetClkSource ( uint32_t Source )

Configures the SysTick clock source.

Reference Manual to LL API cross reference:
STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8
  • LL_SYSTICK_CLKSOURCE_HCLK
Return values:
None

Definition at line 262 of file stm32f1xx_ll_cortex.h.

References LL_SYSTICK_CLKSOURCE_HCLK.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LOW POWER MODE

Functions
LOW POWER MODE
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Function Documentation

__STATIC_INLINE void LL_LPM_DisableEventOnPend ( void )

Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
Return values:
None

Definition at line 388 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_DisableSleepOnExit ( void )

Do not sleep when returning to Thread mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
Return values:
None

Definition at line 364 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableDeepSleep ( void )

Processor uses deep sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
Return values:
None

Definition at line 340 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableEventOnPend ( void )

Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

Reference Manual to LL API cross reference:
SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
Return values:
None

Definition at line 376 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleep ( void )

Processor uses sleep as its low power mode.

Reference Manual to LL API cross reference:
SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
Return values:
None

Definition at line 329 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE void LL_LPM_EnableSleepOnExit ( void )

Configures sleep-on-exit when returning from Handler mode to Thread mode.

Note:
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
Reference Manual to LL API cross reference:
SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
Return values:
None

Definition at line 353 of file stm32f1xx_ll_cortex.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: HANDLER

Functions
HANDLER
CORTEX Exported Functions

Functions

__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)

Function Documentation

__STATIC_INLINE void LL_HANDLER_DisableFault ( uint32_t Fault )

Disable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 426 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE void LL_HANDLER_EnableFault ( uint32_t Fault )

Enable a fault in System handler control register (SHCSR)

Reference Manual to LL API cross reference:
SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
Parameters:
Fault This parameter can be a combination of the following values:
  • LL_HANDLER_FAULT_USG
  • LL_HANDLER_FAULT_BUS
  • LL_HANDLER_FAULT_MEM
Return values:
None

Definition at line 411 of file stm32f1xx_ll_cortex.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: MCU INFO

Functions
MCU INFO
CORTEX Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetConstant (void)
Get Constant number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Function Documentation

__STATIC_INLINE uint32_t LL_CPUID_GetConstant ( void )

Get Constant number.

Reference Manual to LL API cross reference:
SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
Return values:
Value should be equal to 0xF for Cortex-M3 devices

Definition at line 465 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetImplementer ( void )

Get Implementer code.

Reference Manual to LL API cross reference:
SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
Return values:
Value should be equal to 0x41 for ARM

Definition at line 445 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetParNo ( void )

Get Part number.

Reference Manual to LL API cross reference:
SCB_CPUID PARTNO LL_CPUID_GetParNo
Return values:
Value should be equal to 0xC23 for Cortex-M3

Definition at line 475 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetRevision ( void )

Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Reference Manual to LL API cross reference:
SCB_CPUID REVISION LL_CPUID_GetRevision
Return values:
Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)

Definition at line 485 of file stm32f1xx_ll_cortex.h.

__STATIC_INLINE uint32_t LL_CPUID_GetVariant ( void )

Get Variant number (The r value in the rnpn product revision identifier)

Reference Manual to LL API cross reference:
SCB_CPUID VARIANT LL_CPUID_GetVariant
Return values:
Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)

Definition at line 455 of file stm32f1xx_ll_cortex.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CRC

Modules
CRC
STM32F1xx_LL_Driver

Modules

CRC Exported Macros
CRC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for CRC registers.

Register | Bit | Function
CR | RESET | LL_CRC_ResetCRCCalculationUnit
DR | DR | LL_CRC_FeedData32
 |  | LL_CRC_ReadData32
IDR | IDR | LL_CRC_Read_IDR
 |  | LL_CRC_Write_IDR
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
CRC Exported Macros

Defines

#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Define Documentation

#define LL_CRC_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 91 of file stm32f1xx_ll_crc.h.

#define LL_CRC_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in CRC register.

Parameters:
__INSTANCE__ | CRC Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 83 of file stm32f1xx_ll_crc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CRC Configuration functions

Functions
CRC Configuration functions
CRC Exported Functions

Functions

__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.

Function Documentation

__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit ( CRC_TypeDef * CRCx )

Reset the CRC calculation unit.

Reference Manual to LL API cross reference:
CR RESET LL_CRC_ResetCRCCalculationUnit
Parameters:
CRCx CRC Instance
Return values:
None

Definition at line 116 of file stm32f1xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data_Management

Functions
Data_Management
CRC Exported Functions

Functions

__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.

Function Documentation

__STATIC_INLINE void LL_CRC_FeedData32 | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Write given 32-bit data to the CRC calculator.

Reference Manual to LL API cross reference:
DR DR LL_CRC_FeedData32
Parameters:
CRCx | CRC Instance
InData | value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
Return values:
None

Definition at line 136 of file stm32f1xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_Read_IDR ( CRC_TypeDef * CRCx )

Return data stored in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one byte.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Read_IDR
Parameters:
CRCx CRC Instance
Return values:
Value stored in CRC_IDR register (General-purpose 8-bit data register).

Definition at line 159 of file stm32f1xx_ll_crc.h.

__STATIC_INLINE uint32_t LL_CRC_ReadData32 ( CRC_TypeDef * CRCx )

Return current CRC calculation result.

32 bits value is returned.

Reference Manual to LL API cross reference:
DR DR LL_CRC_ReadData32
Parameters:
CRCx CRC Instance
Return values:
Current CRC calculation result as stored in CRC_DR register (32 bits).

Definition at line 147 of file stm32f1xx_ll_crc.h.

__STATIC_INLINE void LL_CRC_Write_IDR | ( | CRC_TypeDef * | CRCx,
 |  | uint32_t | InData
 | ) |  |

Store data in the Independent Data(IDR) register.

Note:
This register can be used as a temporary storage location for one byte.
Reference Manual to LL API cross reference:
IDR IDR LL_CRC_Write_IDR
Parameters:
CRCx | CRC Instance
InData | value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
Return values:
None

Definition at line 172 of file stm32f1xx_ll_crc.h.

Referenced by LL_CRC_DeInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Functions

ErrorStatus LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Function Documentation

ErrorStatus LL_CRC_DeInit ( CRC_TypeDef * CRCx )

De-initialize CRC registers (Registers restored to their default values).

Parameters:
CRCx CRC Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: CRC registers are de-initialized
  • ERROR: CRC registers are not de-initialized

Definition at line 81 of file stm32f1xx_ll_crc.c.

References assert_param, LL_CRC_ResetCRCCalculationUnit(), and LL_CRC_Write_IDR().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA

Modules
DMA
STM32F1xx_LL_Driver

Modules

DMA Private Variables
DMA Private Macros
DMA Exported Init structure
DMA Exported Constants
DMA Exported Macros
DMA Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for DMA registers.

Register | Bit | Function
CCR | CIRC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMode
 |  | LL_DMA_SetMode
 | DIR | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetDataTransferDirection
 |  | LL_DMA_SetDataTransferDirection
 | EN | LL_DMA_DisableChannel
 |  | LL_DMA_EnableChannel
 |  | LL_DMA_IsEnabledChannel
 | HTIE | LL_DMA_DisableIT_HT
 |  | LL_DMA_EnableIT_HT
 |  | LL_DMA_IsEnabledIT_HT
 | MEM2MEM | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetDataTransferDirection
 |  | LL_DMA_SetDataTransferDirection
 | MINC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMemoryIncMode
 |  | LL_DMA_SetMemoryIncMode
 | MSIZE | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetMemorySize
 |  | LL_DMA_SetMemorySize
 | PINC | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetPeriphIncMode
 |  | LL_DMA_SetPeriphIncMode
 | PL | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetChannelPriorityLevel
 |  | LL_DMA_SetChannelPriorityLevel
 | PSIZE | LL_DMA_ConfigTransfer
 |  | LL_DMA_GetPeriphSize
 |  | LL_DMA_SetPeriphSize
 | TCIE | LL_DMA_DisableIT_TC
 |  | LL_DMA_EnableIT_TC
 |  | LL_DMA_IsEnabledIT_TC
 | TEIE | LL_DMA_DisableIT_TE
 |  | LL_DMA_EnableIT_TE
 |  | LL_DMA_IsEnabledIT_TE
CMAR | MA | LL_DMA_ConfigAddresses
 |  | LL_DMA_GetM2MDstAddress
 |  | LL_DMA_GetMemoryAddress
 |  | LL_DMA_SetM2MDstAddress
 |  | LL_DMA_SetMemoryAddress
CNDTR | NDT | LL_DMA_GetDataLength
 |  | LL_DMA_SetDataLength
CPAR | PA | LL_DMA_ConfigAddresses
 |  | LL_DMA_GetM2MSrcAddress
 |  | LL_DMA_GetPeriphAddress
 |  | LL_DMA_SetM2MSrcAddress
 |  | LL_DMA_SetPeriphAddress
IFCR | CGIF1 | LL_DMA_ClearFlag_GI1
 | CGIF2 | LL_DMA_ClearFlag_GI2
 | CGIF3 | LL_DMA_ClearFlag_GI3
 | CGIF4 | LL_DMA_ClearFlag_GI4
 | CGIF5 | LL_DMA_ClearFlag_GI5
 | CGIF6 | LL_DMA_ClearFlag_GI6
 | CGIF7 | LL_DMA_ClearFlag_GI7
 | CHTIF1 | LL_DMA_ClearFlag_HT1
 | CHTIF2 | LL_DMA_ClearFlag_HT2
 | CHTIF3 | LL_DMA_ClearFlag_HT3
 | CHTIF4 | LL_DMA_ClearFlag_HT4
 | CHTIF5 | LL_DMA_ClearFlag_HT5
 | CHTIF6 | LL_DMA_ClearFlag_HT6
 | CHTIF7 | LL_DMA_ClearFlag_HT7
 | CTCIF1 | LL_DMA_ClearFlag_TC1
 | CTCIF2 | LL_DMA_ClearFlag_TC2
 | CTCIF3 | LL_DMA_ClearFlag_TC3
 | CTCIF4 | LL_DMA_ClearFlag_TC4
 | CTCIF5 | LL_DMA_ClearFlag_TC5
 | CTCIF6 | LL_DMA_ClearFlag_TC6
 | CTCIF7 | LL_DMA_ClearFlag_TC7
 | CTEIF1 | LL_DMA_ClearFlag_TE1
 | CTEIF2 | LL_DMA_ClearFlag_TE2
 | CTEIF3 | LL_DMA_ClearFlag_TE3
 | CTEIF4 | LL_DMA_ClearFlag_TE4
 | CTEIF5 | LL_DMA_ClearFlag_TE5
 | CTEIF6 | LL_DMA_ClearFlag_TE6
 | CTEIF7 | LL_DMA_ClearFlag_TE7
ISR | GIF1 | LL_DMA_IsActiveFlag_GI1
 | GIF2 | LL_DMA_IsActiveFlag_GI2
 | GIF3 | LL_DMA_IsActiveFlag_GI3
 | GIF4 | LL_DMA_IsActiveFlag_GI4
 | GIF5 | LL_DMA_IsActiveFlag_GI5
 | GIF6 | LL_DMA_IsActiveFlag_GI6
 | GIF7 | LL_DMA_IsActiveFlag_GI7
 | HTIF1 | LL_DMA_IsActiveFlag_HT1
 | HTIF2 | LL_DMA_IsActiveFlag_HT2
 | HTIF3 | LL_DMA_IsActiveFlag_HT3
 | HTIF4 | LL_DMA_IsActiveFlag_HT4
 | HTIF5 | LL_DMA_IsActiveFlag_HT5
 | HTIF6 | LL_DMA_IsActiveFlag_HT6
 | HTIF7 | LL_DMA_IsActiveFlag_HT7
 | TCIF1 | LL_DMA_IsActiveFlag_TC1
 | TCIF2 | LL_DMA_IsActiveFlag_TC2
 | TCIF3 | LL_DMA_IsActiveFlag_TC3
 | TCIF4 | LL_DMA_IsActiveFlag_TC4
 | TCIF5 | LL_DMA_IsActiveFlag_TC5
 | TCIF6 | LL_DMA_IsActiveFlag_TC6
 | TCIF7 | LL_DMA_IsActiveFlag_TC7
 | TEIF1 | LL_DMA_IsActiveFlag_TE1
 | TEIF2 | LL_DMA_IsActiveFlag_TE2
 | TEIF3 | LL_DMA_IsActiveFlag_TE3
 | TEIF4 | LL_DMA_IsActiveFlag_TE4
 | TEIF5 | LL_DMA_IsActiveFlag_TE5
 | TEIF6 | LL_DMA_IsActiveFlag_TE6
 | TEIF7 | LL_DMA_IsActiveFlag_TE7
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Private Variables

Variables
DMA Private Variables
DMA

Variables

static const uint8_t CHANNEL_OFFSET_TAB []

Variable Documentation

const uint8_t CHANNEL_OFFSET_TAB[] [static]
Initial value:
{
  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
}

Definition at line 65 of file stm32f1xx_ll_dma.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Define Documentation

#define IS_LL_DMA_ALL_CHANNEL_INSTANCE | ( | INSTANCE,
 |  | CHANNEL
 | ) |
Value:
((((INSTANCE) == DMA1) && \
                                                            (((CHANNEL) == LL_DMA_CHANNEL_1) || \
                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
                                                             ((CHANNEL) == LL_DMA_CHANNEL_5) || \
                                                             ((CHANNEL) == LL_DMA_CHANNEL_6) || \
                                                             ((CHANNEL) == LL_DMA_CHANNEL_7))))

Definition at line 109 of file stm32f1xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

#define IS_LL_DMA_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))

Definition at line 65 of file stm32f1xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))

Definition at line 82 of file stm32f1xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MEMORYINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))

Definition at line 75 of file stm32f1xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_MODE_NORMAL) || \
                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))

Definition at line 69 of file stm32f1xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_NBDATA ( __VALUE__ ) ((__VALUE__) <= 0x0000FFFFU)

Definition at line 86 of file stm32f1xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHDATASIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))

Definition at line 78 of file stm32f1xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PERIPHINCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))

Definition at line 72 of file stm32f1xx_ll_dma.c.

Referenced by LL_DMA_Init().

#define IS_LL_DMA_PRIORITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))

Definition at line 88 of file stm32f1xx_ll_dma.c.

Referenced by LL_DMA_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_DMA_InitTypeDef Struct Reference
DMA Exported Init structure

#include <stm32f1xx_ll_dma.h>

Data Fields

uint32_t | PeriphOrM2MSrcAddress
uint32_t | MemoryOrM2MDstAddress
uint32_t | Direction
uint32_t | Mode
uint32_t | PeriphOrM2MSrcIncMode
uint32_t | MemoryOrM2MDstIncMode
uint32_t | PeriphOrM2MSrcDataSize
uint32_t | MemoryOrM2MDstDataSize
uint32_t | NbData
uint32_t | Priority

Detailed Description

Definition at line 94 of file stm32f1xx_ll_dma.h.

Field Documentation

uint32_t LL_DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of Transfer Direction

This feature can be modified afterwards using unitary function LL_DMA_SetDataTransferDirection().

Definition at line 106 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstAddress

Specifies the memory base address for DMA transfer or as Destination base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 101 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize

Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Memory data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetMemorySize().

Definition at line 137 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode

Specifies whether the Memory address or Destination address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Memory increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetMemoryIncMode().

Definition at line 125 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Mode

Specifies the normal or circular operation mode. This parameter can be a value of Transfer mode

Note:
: The circular buffer mode cannot be used if the memory to memory data transfer direction is configured on the selected Channel

This feature can be modified afterwards using unitary function LL_DMA_SetMode().

Definition at line 112 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::NbData

Specifies the number of data to transfer, in data unit. The data unit is equal to the source buffer configuration set in PeripheralSize or MemorySize parameters depending in the transfer direction. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF

This feature can be modified afterwards using unitary function LL_DMA_SetDataLength().

Definition at line 143 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress

Specifies the peripheral base address for DMA transfer or as Source base address in case of memory to memory transfer direction.

This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

Definition at line 96 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize

Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) in case of memory to memory transfer direction. This parameter can be a value of Peripheral data alignment

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphSize().

Definition at line 131 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode

Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction is incremented or not. This parameter can be a value of Peripheral increment mode

This feature can be modified afterwards using unitary function LL_DMA_SetPeriphIncMode().

Definition at line 119 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

uint32_t LL_DMA_InitTypeDef::Priority

Specifies the channel priority level. This parameter can be a value of Transfer Priority level

This feature can be modified afterwards using unitary function LL_DMA_SetChannelPriorityLevel().

Definition at line 150 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init(), and LL_DMA_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_dma.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_WriteReg function. More...

Defines

#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
#define | LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
#define | LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
#define | LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7

Detailed Description

Flags defines which can be used with LL_DMA_WriteReg function.

Define Documentation

#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1

Channel 1 global flag

Definition at line 169 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2

Channel 2 global flag

Definition at line 173 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3

Channel 3 global flag

Definition at line 177 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4

Channel 4 global flag

Definition at line 181 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5

Channel 5 global flag

Definition at line 185 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6

Channel 6 global flag

Definition at line 189 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7

Channel 7 global flag

Definition at line 193 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1

Channel 1 half transfer flag

Definition at line 171 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2

Channel 2 half transfer flag

Definition at line 175 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3

Channel 3 half transfer flag

Definition at line 179 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4

Channel 4 half transfer flag

Definition at line 183 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5

Channel 5 half transfer flag

Definition at line 187 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6

Channel 6 half transfer flag

Definition at line 191 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7

Channel 7 half transfer flag

Definition at line 195 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1

Channel 1 transfer complete flag

Definition at line 170 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2

Channel 2 transfer complete flag

Definition at line 174 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3

Channel 3 transfer complete flag

Definition at line 178 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4

Channel 4 transfer complete flag

Definition at line 182 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5

Channel 5 transfer complete flag

Definition at line 186 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6

Channel 6 transfer complete flag

Definition at line 190 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7

Channel 7 transfer complete flag

Definition at line 194 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1

Channel 1 transfer error flag

Definition at line 172 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2

Channel 2 transfer error flag

Definition at line 176 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3

Channel 3 transfer error flag

Definition at line 180 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4

Channel 4 transfer error flag

Definition at line 184 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5

Channel 5 transfer error flag

Definition at line 188 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6

Channel 6 transfer error flag

Definition at line 192 of file stm32f1xx_ll_dma.h.

#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7

Channel 7 transfer error flag

Definition at line 196 of file stm32f1xx_ll_dma.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
DMA Exported Constants

Flags defines which can be used with LL_DMA_ReadReg function. More...

Defines

#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_ISR_GIF7 DMA_ISR_GIF7
#define | LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
#define | LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
#define | LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7

Detailed Description

Flags defines which can be used with LL_DMA_ReadReg function.

Define Documentation

#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1

Channel 1 global flag

Definition at line 205 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2

Channel 2 global flag

Definition at line 209 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3

Channel 3 global flag

Definition at line 213 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4

Channel 4 global flag

Definition at line 217 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5

Channel 5 global flag

Definition at line 221 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6

Channel 6 global flag

Definition at line 225 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7

Channel 7 global flag

Definition at line 229 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1

Channel 1 half transfer flag

Definition at line 207 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2

Channel 2 half transfer flag

Definition at line 211 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3

Channel 3 half transfer flag

Definition at line 215 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4

Channel 4 half transfer flag

Definition at line 219 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5

Channel 5 half transfer flag

Definition at line 223 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6

Channel 6 half transfer flag

Definition at line 227 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7

Channel 7 half transfer flag

Definition at line 231 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1

Channel 1 transfer complete flag

Definition at line 206 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2

Channel 2 transfer complete flag

Definition at line 210 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3

Channel 3 transfer complete flag

Definition at line 214 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4

Channel 4 transfer complete flag

Definition at line 218 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5

Channel 5 transfer complete flag

Definition at line 222 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6

Channel 6 transfer complete flag

Definition at line 226 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7

Channel 7 transfer complete flag

Definition at line 230 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1

Channel 1 transfer error flag

Definition at line 208 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2

Channel 2 transfer error flag

Definition at line 212 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3

Channel 3 transfer error flag

Definition at line 216 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4

Channel 4 transfer error flag

Definition at line 220 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5

Channel 5 transfer error flag

Definition at line 224 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6

Channel 6 transfer error flag

Definition at line 228 of file stm32f1xx_ll_dma.h.

#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7

Channel 7 transfer error flag

Definition at line 232 of file stm32f1xx_ll_dma.h.

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STM32F103xB HAL User Manual: IT Defines

Defines
IT Defines
DMA Exported Constants

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions. More...

Defines

#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE

Detailed Description

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

Define Documentation

#define LL_DMA_CCR_HTIE DMA_CCR_HTIE

Half Transfer interrupt

Definition at line 242 of file stm32f1xx_ll_dma.h.

#define LL_DMA_CCR_TCIE DMA_CCR_TCIE

Transfer complete interrupt

Definition at line 241 of file stm32f1xx_ll_dma.h.

#define LL_DMA_CCR_TEIE DMA_CCR_TEIE

Transfer error interrupt

Definition at line 243 of file stm32f1xx_ll_dma.h.

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STM32F103xB HAL User Manual: CHANNEL

Defines
CHANNEL
DMA Exported Constants

Defines

#define | LL_DMA_CHANNEL_1 0x00000001U
#define | LL_DMA_CHANNEL_2 0x00000002U
#define | LL_DMA_CHANNEL_3 0x00000003U
#define | LL_DMA_CHANNEL_4 0x00000004U
#define | LL_DMA_CHANNEL_5 0x00000005U
#define | LL_DMA_CHANNEL_6 0x00000006U
#define | LL_DMA_CHANNEL_7 0x00000007U
#define | LL_DMA_CHANNEL_ALL 0xFFFF0000U

Define Documentation

#define LL_DMA_CHANNEL_1 0x00000001U

DMA Channel 1

Definition at line 251 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_2 0x00000002U

DMA Channel 2

Definition at line 252 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_3 0x00000003U

DMA Channel 3

Definition at line 253 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_4 0x00000004U

DMA Channel 4

Definition at line 254 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_5 0x00000005U

DMA Channel 5

Definition at line 255 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_6 0x00000006U

DMA Channel 6

Definition at line 256 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_7 0x00000007U

DMA Channel 7

Definition at line 257 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define LL_DMA_CHANNEL_ALL 0xFFFF0000U

DMA Channel all (used only for function LL_DMA_DeInit().

Definition at line 259 of file stm32f1xx_ll_dma.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Transfer Direction

Defines
Transfer Direction
DMA Exported Constants

Defines

#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Define Documentation

#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM

Memory to memory direction

Definition at line 270 of file stm32f1xx_ll_dma.h.

#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR

Memory to peripheral direction

Definition at line 269 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_ConfigAddresses().

#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

Definition at line 268 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32F103xB HAL User Manual: Transfer mode

Defines
Transfer mode
DMA Exported Constants

Defines

#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Define Documentation

#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC

Circular Mode

Definition at line 279 of file stm32f1xx_ll_dma.h.

#define LL_DMA_MODE_NORMAL 0x00000000U

Normal Mode

Definition at line 278 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32F103xB HAL User Manual: Peripheral increment mode

Defines
Peripheral increment mode
DMA Exported Constants

Defines

#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Define Documentation

#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC

Peripheral increment mode Enable

Definition at line 287 of file stm32f1xx_ll_dma.h.

#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U

Peripheral increment mode Disable

Definition at line 288 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

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STM32F103xB HAL User Manual: Memory increment mode

Defines
Memory increment mode
DMA Exported Constants

Defines

#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Define Documentation

#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC

Memory increment mode Enable

Definition at line 296 of file stm32f1xx_ll_dma.h.

#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U

Memory increment mode Disable

Definition at line 297 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral data alignment

Defines
Peripheral data alignment
DMA Exported Constants

Defines

#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Define Documentation

#define LL_DMA_PDATAALIGN_BYTE 0x00000000U

Peripheral data alignment : Byte

Definition at line 305 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0

Peripheral data alignment : HalfWord

Definition at line 306 of file stm32f1xx_ll_dma.h.

#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1

Peripheral data alignment : Word

Definition at line 307 of file stm32f1xx_ll_dma.h.

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STM32F103xB HAL User Manual: Memory data alignment

Defines
Memory data alignment
DMA Exported Constants

Defines

#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Define Documentation

#define LL_DMA_MDATAALIGN_BYTE 0x00000000U

Memory data alignment : Byte

Definition at line 315 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0

Memory data alignment : HalfWord

Definition at line 316 of file stm32f1xx_ll_dma.h.

#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1

Memory data alignment : Word

Definition at line 317 of file stm32f1xx_ll_dma.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Transfer Priority level

Defines
Transfer Priority level
DMA Exported Constants

Defines

#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Define Documentation

#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1

Priority level : High

Definition at line 327 of file stm32f1xx_ll_dma.h.

#define LL_DMA_PRIORITY_LOW 0x00000000U

Priority level : Low

Definition at line 325 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_StructInit().

#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0

Priority level : Medium

Definition at line 326 of file stm32f1xx_ll_dma.h.

#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL

Priority level : Very_High

Definition at line 328 of file stm32f1xx_ll_dma.h.

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STM32F103xB HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
DMA Exported Macros

Defines

#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.

Define Documentation

#define LL_DMA_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 360 of file stm32f1xx_ll_dma.h.

#define LL_DMA_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in DMA register.

Parameters:
__INSTANCE__ | DMA Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 352 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Convert DMAxChannely

Defines
Convert DMAxChannely
DMA Exported Macros

Defines

#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Define Documentation

#define __LL_DMA_GET_CHANNEL ( __CHANNEL_INSTANCE__ )
Value:
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
 LL_DMA_CHANNEL_7)

Convert DMAx_Channely into LL_DMA_CHANNEL_y.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
LL_DMA_CHANNEL_y

Definition at line 401 of file stm32f1xx_ll_dma.h.

#define __LL_DMA_GET_CHANNEL_INSTANCE | ( | __DMA_INSTANCE__,
 |  | __CHANNEL__
 | ) |
Value:
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
 DMA1_Channel7)

Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Parameters:
__DMA_INSTANCE__ | DMAx
__CHANNEL__ | LL_DMA_CHANNEL_y
Return values:
DMAx_Channely

Definition at line 432 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

#define __LL_DMA_GET_INSTANCE ( __CHANNEL_INSTANCE__ ) (DMA1)

Convert DMAx_Channely into DMAx.

Parameters:
__CHANNEL_INSTANCE__ DMAx_Channely
Return values:
DMAx

Definition at line 378 of file stm32f1xx_ll_dma.h.

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STM32F103xB HAL User Manual: Configuration

Functions
Configuration
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.

Function Documentation

__STATIC_INLINE void LL_DMA_ConfigAddresses | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | Direction
 | ) |  |

Configure the Source and Destination addresses.

Note:
This API must not be called when the DMA channel is enabled.
Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_ConfigAddresses
CMAR MA LL_DMA_ConfigAddresses
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
SrcAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
DstAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 949 of file stm32f1xx_ll_dma.h.

References LL_DMA_DIRECTION_MEMORY_TO_PERIPH.

__STATIC_INLINE void LL_DMA_ConfigTransfer | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure all parameters link to DMA transfer.

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_ConfigTransfer
CCR MEM2MEM LL_DMA_ConfigTransfer
CCR CIRC LL_DMA_ConfigTransfer
CCR PINC LL_DMA_ConfigTransfer
CCR MINC LL_DMA_ConfigTransfer
CCR PSIZE LL_DMA_ConfigTransfer
CCR MSIZE LL_DMA_ConfigTransfer
CCR PL LL_DMA_ConfigTransfer
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Configuration This parameter must be a combination of all the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH or LL_DMA_DIRECTION_MEMORY_TO_MEMORY
  • LL_DMA_MODE_NORMAL or LL_DMA_MODE_CIRCULAR
  • LL_DMA_PERIPH_INCREMENT or LL_DMA_PERIPH_NOINCREMENT
  • LL_DMA_MEMORY_INCREMENT or LL_DMA_MEMORY_NOINCREMENT
  • LL_DMA_PDATAALIGN_BYTE or LL_DMA_PDATAALIGN_HALFWORD or LL_DMA_PDATAALIGN_WORD
  • LL_DMA_MDATAALIGN_BYTE or LL_DMA_MDATAALIGN_HALFWORD or LL_DMA_MDATAALIGN_WORD
  • LL_DMA_PRIORITY_LOW or LL_DMA_PRIORITY_MEDIUM or LL_DMA_PRIORITY_HIGH or LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 545 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_DisableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_DisableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 491 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable DMA channel.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_EnableChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 472 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_GetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH

Definition at line 875 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Number of data to transfer.

Note:
Once the channel is enabled, the return value indicate the remaining bytes to be transmitted.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_GetDataLength
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 920 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_GetDataTransferDirection
CCR MEM2MEM LL_DMA_GetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY

Definition at line 595 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetM2MDstAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1129 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetM2MSrcAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1109 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_GetMemoryAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1025 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_GetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT

Definition at line 732 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_GetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD

Definition at line 826 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get DMA mode circular or normal.

Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_GetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR

Definition at line 642 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_GetPeriphAddress
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

Definition at line 1045 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_GetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT

Definition at line 687 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Get Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_GetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
Returned value can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD

Definition at line 779 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if DMA channel is enabled or disabled.

Reference Manual to LL API cross reference:
CCR EN LL_DMA_IsEnabledChannel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 510 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Priority
 | ) |  |

Set Channel priority level.

Reference Manual to LL API cross reference:
CCR PL LL_DMA_SetChannelPriorityLevel
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Priority This parameter can be one of the following values:
  • LL_DMA_PRIORITY_LOW
  • LL_DMA_PRIORITY_MEDIUM
  • LL_DMA_PRIORITY_HIGH
  • LL_DMA_PRIORITY_VERYHIGH
Return values:
None

Definition at line 851 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetDataLength | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | NbData
 | ) |  |

Set Number of data to transfer.

Note:
This action has no effect if channel is enabled.
Reference Manual to LL API cross reference:
CNDTR NDT LL_DMA_SetDataLength
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
NbData | Between Min_Data = 0 and Max_Data = 0x0000FFFF
Return values:
None

Definition at line 898 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetDataTransferDirection | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Direction
 | ) |  |

Set Data transfer direction (read from peripheral or from memory).

Reference Manual to LL API cross reference:
CCR DIR LL_DMA_SetDataTransferDirection
CCR MEM2MEM LL_DMA_SetDataTransferDirection
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Direction This parameter can be one of the following values:
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY
Return values:
None

Definition at line 571 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MDstAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Destination address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetM2MDstAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1089 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetM2MSrcAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory to Memory Source address.

Note:
Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetM2MSrcAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1067 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemoryAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryAddress
 | ) |  |

Set the Memory address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CMAR MA LL_DMA_SetMemoryAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 983 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetMemoryIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstIncMode
 | ) |  |

Set Memory increment mode.

Reference Manual to LL API cross reference:
CCR MINC LL_DMA_SetMemoryIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryOrM2MDstIncMode This parameter can be one of the following values:
  • LL_DMA_MEMORY_INCREMENT
  • LL_DMA_MEMORY_NOINCREMENT
Return values:
None

Definition at line 710 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMemorySize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | MemoryOrM2MDstDataSize
 | ) |  |

Set Memory size.

Reference Manual to LL API cross reference:
CCR MSIZE LL_DMA_SetMemorySize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
MemoryOrM2MDstDataSize This parameter can be one of the following values:
  • LL_DMA_MDATAALIGN_BYTE
  • LL_DMA_MDATAALIGN_HALFWORD
  • LL_DMA_MDATAALIGN_WORD
Return values:
None

Definition at line 803 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Set DMA mode circular or normal.

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel.
Reference Manual to LL API cross reference:
CCR CIRC LL_DMA_SetMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Mode This parameter can be one of the following values:
  • LL_DMA_MODE_NORMAL
  • LL_DMA_MODE_CIRCULAR
Return values:
None

Definition at line 620 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphAddress | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphAddress
 | ) |  |

Set the Peripheral address.

Note:
Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
This API must not be called when the DMA channel is enabled.
Reference Manual to LL API cross reference:
CPAR PA LL_DMA_SetPeriphAddress
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphAddress | Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
Return values:
None

Definition at line 1005 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_Init().

__STATIC_INLINE void LL_DMA_SetPeriphIncMode | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcIncMode
 | ) |  |

Set Peripheral increment mode.

Reference Manual to LL API cross reference:
CCR PINC LL_DMA_SetPeriphIncMode
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphOrM2MSrcIncMode This parameter can be one of the following values:
  • LL_DMA_PERIPH_INCREMENT
  • LL_DMA_PERIPH_NOINCREMENT
Return values:
None

Definition at line 665 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_SetPeriphSize | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | uint32_t | PeriphOrM2MSrcDataSize
 | ) |  |

Set Peripheral size.

Reference Manual to LL API cross reference:
CCR PSIZE LL_DMA_SetPeriphSize
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
PeriphOrM2MSrcDataSize This parameter can be one of the following values:
  • LL_DMA_PDATAALIGN_BYTE
  • LL_DMA_PDATAALIGN_HALFWORD
  • LL_DMA_PDATAALIGN_WORD
Return values:
None

Definition at line 756 of file stm32f1xx_ll_dma.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLAG_Management

Functions
FLAG_Management
DMA Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI7 (DMA_TypeDef *DMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI7 (DMA_TypeDef *DMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer error flag.

Function Documentation

__STATIC_INLINE void LL_DMA_ClearFlag_GI1 ( DMA_TypeDef * DMAx )

Clear Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF1 LL_DMA_ClearFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1456 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI2 ( DMA_TypeDef * DMAx )

Clear Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF2 LL_DMA_ClearFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1467 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI3 ( DMA_TypeDef * DMAx )

Clear Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF3 LL_DMA_ClearFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1478 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI4 ( DMA_TypeDef * DMAx )

Clear Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF4 LL_DMA_ClearFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1489 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI5 ( DMA_TypeDef * DMAx )

Clear Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF5 LL_DMA_ClearFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1500 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI6 ( DMA_TypeDef * DMAx )

Clear Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF6 LL_DMA_ClearFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1511 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_GI7 ( DMA_TypeDef * DMAx )

Clear Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
IFCR CGIF7 LL_DMA_ClearFlag_GI7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1522 of file stm32f1xx_ll_dma.h.

Referenced by LL_DMA_DeInit().

__STATIC_INLINE void LL_DMA_ClearFlag_HT1 ( DMA_TypeDef * DMAx )

Clear Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF1 LL_DMA_ClearFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1610 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT2 ( DMA_TypeDef * DMAx )

Clear Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF2 LL_DMA_ClearFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1621 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT3 ( DMA_TypeDef * DMAx )

Clear Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF3 LL_DMA_ClearFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1632 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT4 ( DMA_TypeDef * DMAx )

Clear Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF4 LL_DMA_ClearFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1643 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT5 ( DMA_TypeDef * DMAx )

Clear Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF5 LL_DMA_ClearFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1654 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT6 ( DMA_TypeDef * DMAx )

Clear Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF6 LL_DMA_ClearFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1665 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_HT7 ( DMA_TypeDef * DMAx )

Clear Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
IFCR CHTIF7 LL_DMA_ClearFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1676 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF1 LL_DMA_ClearFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1533 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF2 LL_DMA_ClearFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1544 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF3 LL_DMA_ClearFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1555 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF4 LL_DMA_ClearFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1566 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF5 LL_DMA_ClearFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1577 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF6 LL_DMA_ClearFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1588 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TC7 ( DMA_TypeDef * DMAx )

Clear Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
IFCR CTCIF7 LL_DMA_ClearFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1599 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE1 ( DMA_TypeDef * DMAx )

Clear Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF1 LL_DMA_ClearFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1687 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE2 ( DMA_TypeDef * DMAx )

Clear Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF2 LL_DMA_ClearFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1698 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE3 ( DMA_TypeDef * DMAx )

Clear Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF3 LL_DMA_ClearFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1709 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE4 ( DMA_TypeDef * DMAx )

Clear Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF4 LL_DMA_ClearFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1720 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE5 ( DMA_TypeDef * DMAx )

Clear Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF5 LL_DMA_ClearFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1731 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE6 ( DMA_TypeDef * DMAx )

Clear Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF6 LL_DMA_ClearFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1742 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_ClearFlag_TE7 ( DMA_TypeDef * DMAx )

Clear Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
IFCR CTEIF7 LL_DMA_ClearFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
None

Definition at line 1753 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1 ( DMA_TypeDef * DMAx )

Get Channel 1 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF1 LL_DMA_IsActiveFlag_GI1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1148 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2 ( DMA_TypeDef * DMAx )

Get Channel 2 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF2 LL_DMA_IsActiveFlag_GI2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1159 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3 ( DMA_TypeDef * DMAx )

Get Channel 3 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF3 LL_DMA_IsActiveFlag_GI3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1170 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4 ( DMA_TypeDef * DMAx )

Get Channel 4 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF4 LL_DMA_IsActiveFlag_GI4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1181 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5 ( DMA_TypeDef * DMAx )

Get Channel 5 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF5 LL_DMA_IsActiveFlag_GI5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1192 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6 ( DMA_TypeDef * DMAx )

Get Channel 6 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF6 LL_DMA_IsActiveFlag_GI6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1203 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7 ( DMA_TypeDef * DMAx )

Get Channel 7 global interrupt flag.

Reference Manual to LL API cross reference:
ISR GIF7 LL_DMA_IsActiveFlag_GI7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1214 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1 ( DMA_TypeDef * DMAx )

Get Channel 1 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF1 LL_DMA_IsActiveFlag_HT1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1302 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2 ( DMA_TypeDef * DMAx )

Get Channel 2 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF2 LL_DMA_IsActiveFlag_HT2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1313 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3 ( DMA_TypeDef * DMAx )

Get Channel 3 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF3 LL_DMA_IsActiveFlag_HT3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1324 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4 ( DMA_TypeDef * DMAx )

Get Channel 4 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF4 LL_DMA_IsActiveFlag_HT4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1335 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5 ( DMA_TypeDef * DMAx )

Get Channel 5 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF5 LL_DMA_IsActiveFlag_HT5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1346 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6 ( DMA_TypeDef * DMAx )

Get Channel 6 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF6 LL_DMA_IsActiveFlag_HT6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1357 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7 ( DMA_TypeDef * DMAx )

Get Channel 7 half transfer flag.

Reference Manual to LL API cross reference:
ISR HTIF7 LL_DMA_IsActiveFlag_HT7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1368 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF1 LL_DMA_IsActiveFlag_TC1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1225 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF2 LL_DMA_IsActiveFlag_TC2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1236 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF3 LL_DMA_IsActiveFlag_TC3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1247 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF4 LL_DMA_IsActiveFlag_TC4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1258 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF5 LL_DMA_IsActiveFlag_TC5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1269 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF6 LL_DMA_IsActiveFlag_TC6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1280 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7 ( DMA_TypeDef * DMAx )

Get Channel 7 transfer complete flag.

Reference Manual to LL API cross reference:
ISR TCIF7 LL_DMA_IsActiveFlag_TC7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1291 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1 ( DMA_TypeDef * DMAx )

Get Channel 1 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF1 LL_DMA_IsActiveFlag_TE1
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1379 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2 ( DMA_TypeDef * DMAx )

Get Channel 2 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF2 LL_DMA_IsActiveFlag_TE2
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1390 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3 ( DMA_TypeDef * DMAx )

Get Channel 3 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF3 LL_DMA_IsActiveFlag_TE3
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1401 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4 ( DMA_TypeDef * DMAx )

Get Channel 4 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF4 LL_DMA_IsActiveFlag_TE4
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1412 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5 ( DMA_TypeDef * DMAx )

Get Channel 5 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF5 LL_DMA_IsActiveFlag_TE5
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1423 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6 ( DMA_TypeDef * DMAx )

Get Channel 6 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF6 LL_DMA_IsActiveFlag_TE6
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1434 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7 ( DMA_TypeDef * DMAx )

Get Channel 7 transfer error flag.

Reference Manual to LL API cross reference:
ISR TEIF7 LL_DMA_IsActiveFlag_TE7
Parameters:
DMAx DMAx Instance
Return values:
State of bit (1 or 0).

Definition at line 1445 of file stm32f1xx_ll_dma.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IT_Management

Functions
IT_Management
DMA Exported Functions

Functions

__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_DMA_DisableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_DisableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1856 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_DisableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1837 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_DisableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Disable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_DisableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1875 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Half transfer interrupt.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_EnableIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1799 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer complete interrupt.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_EnableIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1780 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE void LL_DMA_EnableIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Enable Transfer error interrupt.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_EnableIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
None

Definition at line 1818 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Half transfer Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR HTIE LL_DMA_IsEnabledIT_HT
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 1914 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer complete Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TCIE LL_DMA_IsEnabledIT_TC
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 1894 of file stm32f1xx_ll_dma.h.

__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

Check if Transfer error Interrupt is enabled.

Reference Manual to LL API cross reference:
CCR TEIE LL_DMA_IsEnabledIT_TE
Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
State of bit (1 or 0).

Definition at line 1934 of file stm32f1xx_ll_dma.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Functions

uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Function Documentation

uint32_t LL_DMA_DeInit | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel
 | ) |  |

De-initialize the DMA registers to their default reset values.

Parameters:
DMAx DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are de-initialized
  • ERROR: DMA registers are not de-initialized

Definition at line 147 of file stm32f1xx_ll_dma.c.

References __LL_DMA_GET_CHANNEL_INSTANCE, assert_param, IS_LL_DMA_ALL_CHANNEL_INSTANCE, LL_DMA_CHANNEL_1, LL_DMA_CHANNEL_2, LL_DMA_CHANNEL_3, LL_DMA_CHANNEL_4, LL_DMA_CHANNEL_5, LL_DMA_CHANNEL_6, LL_DMA_CHANNEL_7, LL_DMA_ClearFlag_GI1(), LL_DMA_ClearFlag_GI2(), LL_DMA_ClearFlag_GI3(), LL_DMA_ClearFlag_GI4(), LL_DMA_ClearFlag_GI5(), LL_DMA_ClearFlag_GI6(), LL_DMA_ClearFlag_GI7(), and LL_DMA_WriteReg.

uint32_t LL_DMA_Init | ( | DMA_TypeDef * | DMAx,
 |  | uint32_t | Channel,
 |  | LL_DMA_InitTypeDef * | DMA_InitStruct
 | ) |  |

Initialize the DMA registers according to the specified parameters in DMA_InitStruct.

Note:
To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
  • __LL_DMA_GET_INSTANCE
  • __LL_DMA_GET_CHANNEL
Parameters:
DMAx | DMAx Instance
Channel This parameter can be one of the following values:
  • LL_DMA_CHANNEL_1
  • LL_DMA_CHANNEL_2
  • LL_DMA_CHANNEL_3
  • LL_DMA_CHANNEL_4
  • LL_DMA_CHANNEL_5
  • LL_DMA_CHANNEL_6
  • LL_DMA_CHANNEL_7
DMA_InitStruct | pointer to a LL_DMA_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: DMA registers are initialized
  • ERROR: Not applicable

Definition at line 235 of file stm32f1xx_ll_dma.c.

References assert_param, LL_DMA_InitTypeDef::Direction, IS_LL_DMA_ALL_CHANNEL_INSTANCE, IS_LL_DMA_DIRECTION, IS_LL_DMA_MEMORYDATASIZE, IS_LL_DMA_MEMORYINCMODE, IS_LL_DMA_MODE, IS_LL_DMA_NBDATA, IS_LL_DMA_PERIPHDATASIZE, IS_LL_DMA_PERIPHINCMODE, IS_LL_DMA_PRIORITY, LL_DMA_ConfigTransfer(), LL_DMA_SetDataLength(), LL_DMA_SetMemoryAddress(), LL_DMA_SetPeriphAddress(), LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, and LL_DMA_InitTypeDef::Priority.

void LL_DMA_StructInit ( LL_DMA_InitTypeDef * DMA_InitStruct )

Set each LL_DMA_InitTypeDef field to default value.

Parameters:
DMA_InitStruct Pointer to a LL_DMA_InitTypeDef structure.
Return values:
None

Definition at line 296 of file stm32f1xx_ll_dma.c.

References LL_DMA_InitTypeDef::Direction, LL_DMA_DIRECTION_PERIPH_TO_MEMORY, LL_DMA_MDATAALIGN_BYTE, LL_DMA_MEMORY_NOINCREMENT, LL_DMA_MODE_NORMAL, LL_DMA_PDATAALIGN_BYTE, LL_DMA_PERIPH_NOINCREMENT, LL_DMA_PRIORITY_LOW, LL_DMA_InitTypeDef::MemoryOrM2MDstAddress, LL_DMA_InitTypeDef::MemoryOrM2MDstDataSize, LL_DMA_InitTypeDef::MemoryOrM2MDstIncMode, LL_DMA_InitTypeDef::Mode, LL_DMA_InitTypeDef::NbData, LL_DMA_InitTypeDef::PeriphOrM2MSrcAddress, LL_DMA_InitTypeDef::PeriphOrM2MSrcDataSize, LL_DMA_InitTypeDef::PeriphOrM2MSrcIncMode, and LL_DMA_InitTypeDef::Priority.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: EXTI

Modules
EXTI
STM32F1xx_LL_Driver

Modules

EXTI Private Macros
EXTI Exported Init structure
EXTI Exported Constants
EXTI Exported Macros
EXTI Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for EXTI registers.

Register | Bit | Function
EMR | EMx | LL_EXTI_DisableEvent_0_31
 |  | LL_EXTI_EnableEvent_0_31
 |  | LL_EXTI_IsEnabledEvent_0_31
FTSR | FTx | LL_EXTI_DisableFallingTrig_0_31
 |  | LL_EXTI_EnableFallingTrig_0_31
 |  | LL_EXTI_IsEnabledFallingTrig_0_31
IMR | IMx | LL_EXTI_DisableIT_0_31
 |  | LL_EXTI_EnableIT_0_31
 |  | LL_EXTI_IsEnabledIT_0_31
PR | PIFx | LL_EXTI_ClearFlag_0_31
 |  | LL_EXTI_IsActiveFlag_0_31
 |  | LL_EXTI_ReadFlag_0_31
RTSR | RTx | LL_EXTI_DisableRisingTrig_0_31
 |  | LL_EXTI_EnableRisingTrig_0_31
 |  | LL_EXTI_IsEnabledRisingTrig_0_31
SWIER | SWIx | LL_EXTI_GenerateSWI_0_31
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: EXTI Private Macros

Defines
EXTI Private Macros
EXTI

Defines

#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Define Documentation

#define IS_LL_EXTI_LINE_0_31 ( __VALUE__ ) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)

Definition at line 65 of file stm32f1xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_MODE_IT)            \
                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))

Definition at line 67 of file stm32f1xx_ll_exti.c.

Referenced by LL_EXTI_Init().

#define IS_LL_EXTI_TRIGGER ( __VALUE__ )
Value:
(((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))

Definition at line 72 of file stm32f1xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_EXTI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_EXTI_InitTypeDef Struct Reference
EXTI Exported Init structure

#include <stm32f1xx_ll_exti.h>

Data Fields

uint32_t | Line_0_31
FunctionalState | LineCommand
uint8_t | Mode
uint8_t | Trigger

Detailed Description

Definition at line 76 of file stm32f1xx_ll_exti.h.

Field Documentation

uint32_t LL_EXTI_InitTypeDef::Line_0_31

Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 This parameter can be any combination of LINE

Definition at line 79 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

FunctionalState LL_EXTI_InitTypeDef::LineCommand

Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE

Definition at line 82 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Mode

Specifies the mode for the EXTI lines. This parameter can be a value of Mode.

Definition at line 85 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

uint8_t LL_EXTI_InitTypeDef::Trigger

Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of Edge Trigger.

Definition at line 88 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_exti.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LINE

Defines
LINE
EXTI Exported Constants

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR_IM18
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM
#define | LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE ((uint32_t)0x00000000U)

Define Documentation

#define LL_EXTI_LINE_0 EXTI_IMR_IM0

Extended line 0

Definition at line 105 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_1 EXTI_IMR_IM1

Extended line 1

Definition at line 106 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_10 EXTI_IMR_IM10

Extended line 10

Definition at line 115 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_11 EXTI_IMR_IM11

Extended line 11

Definition at line 116 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_12 EXTI_IMR_IM12

Extended line 12

Definition at line 117 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_13 EXTI_IMR_IM13

Extended line 13

Definition at line 118 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_14 EXTI_IMR_IM14

Extended line 14

Definition at line 119 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_15 EXTI_IMR_IM15

Extended line 15

Definition at line 120 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_16 EXTI_IMR_IM16

Extended line 16

Definition at line 122 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_17 EXTI_IMR_IM17

Extended line 17

Definition at line 124 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_18 EXTI_IMR_IM18

Extended line 18

Definition at line 126 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_2 EXTI_IMR_IM2

Extended line 2

Definition at line 107 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_3 EXTI_IMR_IM3

Extended line 3

Definition at line 108 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_4 EXTI_IMR_IM4

Extended line 4

Definition at line 109 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_5 EXTI_IMR_IM5

Extended line 5

Definition at line 110 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_6 EXTI_IMR_IM6

Extended line 6

Definition at line 111 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_7 EXTI_IMR_IM7

Extended line 7

Definition at line 112 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_8 EXTI_IMR_IM8

Extended line 8

Definition at line 113 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_9 EXTI_IMR_IM9

Extended line 9

Definition at line 114 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU)

All Extended line

Definition at line 170 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM

All Extended line not reserved

Definition at line 167 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U)

None Extended line

Definition at line 173 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Mode

Defines
Mode
EXTI Exported Constants

Defines

#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Define Documentation

#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U)

Event Mode

Definition at line 185 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_MODE_IT ((uint8_t)0x00U)

Interrupt Mode

Definition at line 184 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)

Interrupt & Event Mode

Definition at line 186 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Edge Trigger

Defines
Edge Trigger
EXTI Exported Constants

Defines

#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Define Documentation

#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)

Trigger Falling Mode

Definition at line 196 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init(), and LL_EXTI_StructInit().

#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)

No Trigger Mode

Definition at line 194 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)

Trigger Rising Mode

Definition at line 195 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)

Trigger Rising & Falling Mode

Definition at line 197 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
EXTI Exported Macros

Defines

#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Define Documentation

#define LL_EXTI_ReadReg ( __REG__ ) READ_REG(EXTI->__REG__)

Read a value in EXTI register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 233 of file stm32f1xx_ll_exti.h.

#define LL_EXTI_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(EXTI->__REG__, (__VALUE__))

Write a value in EXTI register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 226 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_DeInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IT_Management

Functions
IT_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableIT_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Interrupt request for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR IMx LL_EXTI_DisableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 320 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableIT_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Interrupt request for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR IMx LL_EXTI_EnableIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 284 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.

Note:
The reset value for the direct or internal lines (see RM) is set to 1 in order to enable the interrupt by default. Bits are set automatically at Power on.
Reference Manual to LL API cross reference:
IMR IMx LL_EXTI_IsEnabledIT_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 357 of file stm32f1xx_ll_exti.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Event_Management

Functions
Event_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableEvent_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR EMx LL_EXTI_DisableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 434 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableEvent_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Event request for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR EMx LL_EXTI_EnableEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 399 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31 ( uint32_t ExtiLine )

Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
EMR EMx LL_EXTI_IsEnabledEvent_0_31
Parameters:
ExtiLine This parameter can be one of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_17
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
  • LL_EXTI_LINE_ALL_0_31
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 468 of file stm32f1xx_ll_exti.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Rising_Trigger_Management

Functions
Rising_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR RTx LL_EXTI_DisableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 556 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a rising edge on a configurable interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
RTSR RTx LL_EXTI_EnableRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 516 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31 ( uint32_t ExtiLine )

Check if rising edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 589 of file stm32f1xx_ll_exti.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Falling_Trigger_Management

Functions
Falling_Trigger_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31 ( uint32_t ExtiLine )

Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a Falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR FTx LL_EXTI_DisableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 674 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31 ( uint32_t ExtiLine )

Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.

Note:
The configurable wakeup lines are edge-triggered. No glitch must be generated on these lines. If a falling edge on a configurable interrupt line occurs during a write operation in the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.
Reference Manual to LL API cross reference:
FTSR FTx LL_EXTI_EnableFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 636 of file stm32f1xx_ll_exti.h.

Referenced by LL_EXTI_Init().

__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31 ( uint32_t ExtiLine )

Check if falling edge trigger is enabled for Lines in range 0 to 31.

Reference Manual to LL API cross reference:
FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 706 of file stm32f1xx_ll_exti.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Software_Interrupt_Management

Functions
Software_Interrupt_Management
EXTI Exported Functions

Functions

__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31 ( uint32_t ExtiLine )

Generate a software Interrupt Event for Lines in range 0 to 31.

Note:
If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by writing a 1 into the bit)
Reference Manual to LL API cross reference:
SWIER SWIx LL_EXTI_GenerateSWI_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 751 of file stm32f1xx_ll_exti.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Flag_Management

Functions
Flag_Management
EXTI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.

Function Documentation

__STATIC_INLINE void LL_EXTI_ClearFlag_0_31 ( uint32_t ExtiLine )

Clear ExtLine Flags for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR PIFx LL_EXTI_ClearFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
Note:
Please check each device line mapping for EXTI Line availability
Return values:
None

Definition at line 861 of file stm32f1xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31 ( uint32_t ExtiLine )

Check if the ExtLine Flag is set or not for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR PIFx LL_EXTI_IsActiveFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
Note:
Please check each device line mapping for EXTI Line availability
Return values:
State of bit (1 or 0).

Definition at line 793 of file stm32f1xx_ll_exti.h.

__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31 ( uint32_t ExtiLine )

Read ExtLine Combination Flag for Lines in range 0 to 31.

Note:
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing a 1 to the bit.
Reference Manual to LL API cross reference:
PR PIFx LL_EXTI_ReadFlag_0_31
Parameters:
ExtiLine This parameter can be a combination of the following values:
  • LL_EXTI_LINE_0
  • LL_EXTI_LINE_1
  • LL_EXTI_LINE_2
  • LL_EXTI_LINE_3
  • LL_EXTI_LINE_4
  • LL_EXTI_LINE_5
  • LL_EXTI_LINE_6
  • LL_EXTI_LINE_7
  • LL_EXTI_LINE_8
  • LL_EXTI_LINE_9
  • LL_EXTI_LINE_10
  • LL_EXTI_LINE_11
  • LL_EXTI_LINE_12
  • LL_EXTI_LINE_13
  • LL_EXTI_LINE_14
  • LL_EXTI_LINE_15
  • LL_EXTI_LINE_16
  • LL_EXTI_LINE_18
  • LL_EXTI_LINE_19
Note:
Please check each device line mapping for EXTI Line availability
Return values:
@note This bit is set when the selected edge event arrives on the interrupt

Definition at line 827 of file stm32f1xx_ll_exti.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
EXTI Exported Functions

Functions

uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Function Documentation

uint32_t LL_EXTI_DeInit ( void )

De-initialize the EXTI registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: EXTI registers are de-initialized
  • ERROR: not applicable

Definition at line 98 of file stm32f1xx_ll_exti.c.

References LL_EXTI_WriteReg.

uint32_t LL_EXTI_Init ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.

Parameters:
EXTI_InitStruct pointer to a LL_EXTI_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: EXTI registers are initialized
  • ERROR: not applicable

Definition at line 123 of file stm32f1xx_ll_exti.c.

References assert_param, IS_LL_EXTI_LINE_0_31, IS_LL_EXTI_MODE, IS_LL_EXTI_TRIGGER, LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_DisableEvent_0_31(), LL_EXTI_DisableFallingTrig_0_31(), LL_EXTI_DisableIT_0_31(), LL_EXTI_DisableRisingTrig_0_31(), LL_EXTI_EnableEvent_0_31(), LL_EXTI_EnableFallingTrig_0_31(), LL_EXTI_EnableIT_0_31(), LL_EXTI_EnableRisingTrig_0_31(), LL_EXTI_LINE_NONE, LL_EXTI_MODE_EVENT, LL_EXTI_MODE_IT, LL_EXTI_MODE_IT_EVENT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_TRIGGER_NONE, LL_EXTI_TRIGGER_RISING, LL_EXTI_TRIGGER_RISING_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

void LL_EXTI_StructInit ( LL_EXTI_InitTypeDef * EXTI_InitStruct )

Set each LL_EXTI_InitTypeDef field to default value.

Parameters:
EXTI_InitStruct Pointer to a LL_EXTI_InitTypeDef structure.
Return values:
None

Definition at line 204 of file stm32f1xx_ll_exti.c.

References LL_EXTI_InitTypeDef::Line_0_31, LL_EXTI_InitTypeDef::LineCommand, LL_EXTI_LINE_NONE, LL_EXTI_MODE_IT, LL_EXTI_TRIGGER_FALLING, LL_EXTI_InitTypeDef::Mode, and LL_EXTI_InitTypeDef::Trigger.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO

Modules
GPIO
STM32F1xx_LL_Driver

Modules

GPIO Private Constants
GPIO Private Macros
GPIO Exported Init structures
GPIO Exported Constants
GPIO Exported Macros
GPIO Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for GPIO registers.

Register | Bit | Function
BRR | BRy | LL_GPIO_ResetOutputPin
BSRR | BSy | LL_GPIO_SetOutputPin
CRH | CNFy | LL_GPIO_GetPinMode
 |  | LL_GPIO_SetPinMode
 | MODEy | LL_GPIO_GetPinMode
 |  | LL_GPIO_GetPinOutputType
 |  | LL_GPIO_GetPinSpeed
 |  | LL_GPIO_SetPinMode
 |  | LL_GPIO_SetPinOutputType
 |  | LL_GPIO_SetPinSpeed
CRL | CNFy | LL_GPIO_GetPinMode
 |  | LL_GPIO_SetPinMode
 | MODEy | LL_GPIO_GetPinMode
 |  | LL_GPIO_GetPinOutputType
 |  | LL_GPIO_GetPinSpeed
 |  | LL_GPIO_SetPinMode
 |  | LL_GPIO_SetPinOutputType
 |  | LL_GPIO_SetPinSpeed
IDR | IDy | LL_GPIO_IsInputPinSet
 |  | LL_GPIO_ReadInputPort
LCKR | LCKK | LL_GPIO_IsAnyPinLocked
 |  | LL_GPIO_LockPin
 | LCKy | LL_GPIO_IsPinLocked
ODR | ODR | LL_GPIO_GetPinPull
 |  | LL_GPIO_SetPinPull
 | ODy | LL_GPIO_IsOutputPinSet
 |  | LL_GPIO_ReadOutputPort
 |  | LL_GPIO_TogglePin
 |  | LL_GPIO_WriteOutputPort
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STM32F103xB HAL User Manual: GPIO Private Constants

GPIO Private Constants
GPIO
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)

Define Documentation

#define IS_LL_GPIO_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_MODE_ANALOG)       ||\
                                            ((__VALUE__) == LL_GPIO_MODE_FLOATING)     ||\
                                            ((__VALUE__) == LL_GPIO_MODE_INPUT)        ||\
                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)       ||\
                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE))

Definition at line 67 of file stm32f1xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_OUTPUT_TYPE ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))

Definition at line 77 of file stm32f1xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PIN ( __VALUE__ ) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))

Definition at line 65 of file stm32f1xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_PULL ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_PULL_DOWN)   ||\
                                            ((__VALUE__) == LL_GPIO_PULL_UP))

Definition at line 80 of file stm32f1xx_ll_gpio.c.

Referenced by LL_GPIO_Init().

#define IS_LL_GPIO_SPEED ( __VALUE__ )
Value:
(((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))

Definition at line 73 of file stm32f1xx_ll_gpio.c.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_GPIO_InitTypeDef Struct Reference
GPIO Exported Init structures

LL GPIO Init Structure definition. More...

#include <stm32f1xx_ll_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Speed
uint32_t | OutputType
uint32_t | Pull

Detailed Description

LL GPIO Init Structure definition.

Definition at line 91 of file stm32f1xx_ll_gpio.h.

Field Documentation

uint32_t LL_GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of Mode.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinMode().

Definition at line 96 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::OutputType

Specifies the operating output type for the selected pins. This parameter can be a value of Output Type.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinOutputType().

Definition at line 106 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of PIN

Definition at line 93 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Pull

Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of Pull Up Pull Down.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinPull().

Definition at line 111 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

uint32_t LL_GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of Output Speed.

GPIO HW configuration can be modified afterwards using unitary function LL_GPIO_SetPinSpeed().

Definition at line 101 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_gpio.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PIN

Defines
PIN
GPIO Exported Constants

Defines

#define | LL_GPIO_PIN_0 (GPIO_BSRR_BS0 << 8) | 0x00000001U
#define | LL_GPIO_PIN_1 (GPIO_BSRR_BS1 << 8) | 0x00000002U
#define | LL_GPIO_PIN_2 (GPIO_BSRR_BS2 << 8) | 0x00000004U
#define | LL_GPIO_PIN_3 (GPIO_BSRR_BS3 << 8) | 0x00000008U
#define | LL_GPIO_PIN_4 (GPIO_BSRR_BS4 << 8) | 0x00000010U
#define | LL_GPIO_PIN_5 (GPIO_BSRR_BS5 << 8) | 0x00000020U
#define | LL_GPIO_PIN_6 (GPIO_BSRR_BS6 << 8) | 0x00000040U
#define | LL_GPIO_PIN_7 (GPIO_BSRR_BS7 << 8) | 0x00000080U
#define | LL_GPIO_PIN_8 (GPIO_BSRR_BS8 << 8) | 0x04000001U
#define | LL_GPIO_PIN_9 (GPIO_BSRR_BS9 << 8) | 0x04000002U
#define | LL_GPIO_PIN_10 (GPIO_BSRR_BS10 << 8) | 0x04000004U
#define | LL_GPIO_PIN_11 (GPIO_BSRR_BS11 << 8) | 0x04000008U
#define | LL_GPIO_PIN_12 (GPIO_BSRR_BS12 << 8) | 0x04000010U
#define | LL_GPIO_PIN_13 (GPIO_BSRR_BS13 << 8) | 0x04000020U
#define | LL_GPIO_PIN_14 (GPIO_BSRR_BS14 << 8) | 0x04000040U
#define | LL_GPIO_PIN_15 (GPIO_BSRR_BS15 << 8) | 0x04000080U
#define | LL_GPIO_PIN_ALL

Define Documentation

#define LL_GPIO_PIN_0 (GPIO_BSRR_BS0 << 8) | 0x00000001U

Select pin 0

Definition at line 130 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_1 (GPIO_BSRR_BS1 << 8) | 0x00000002U

Select pin 1

Definition at line 131 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_10 (GPIO_BSRR_BS10 << 8) | 0x04000004U

Select pin 10

Definition at line 140 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_11 (GPIO_BSRR_BS11 << 8) | 0x04000008U

Select pin 11

Definition at line 141 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_12 (GPIO_BSRR_BS12 << 8) | 0x04000010U

Select pin 12

Definition at line 142 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_13 (GPIO_BSRR_BS13 << 8) | 0x04000020U

Select pin 13

Definition at line 143 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_14 (GPIO_BSRR_BS14 << 8) | 0x04000040U

Select pin 14

Definition at line 144 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_15 (GPIO_BSRR_BS15 << 8) | 0x04000080U

Select pin 15

Definition at line 145 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_2 (GPIO_BSRR_BS2 << 8) | 0x00000004U

Select pin 2

Definition at line 132 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_3 (GPIO_BSRR_BS3 << 8) | 0x00000008U

Select pin 3

Definition at line 133 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_4 (GPIO_BSRR_BS4 << 8) | 0x00000010U

Select pin 4

Definition at line 134 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_5 (GPIO_BSRR_BS5 << 8) | 0x00000020U

Select pin 5

Definition at line 135 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_6 (GPIO_BSRR_BS6 << 8) | 0x00000040U

Select pin 6

Definition at line 136 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_7 (GPIO_BSRR_BS7 << 8) | 0x00000080U

Select pin 7

Definition at line 137 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_8 (GPIO_BSRR_BS8 << 8) | 0x04000001U

Select pin 8

Definition at line 138 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_9 (GPIO_BSRR_BS9 << 8) | 0x04000002U

Select pin 9

Definition at line 139 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_PIN_ALL
Value:
(LL_GPIO_PIN_0  | LL_GPIO_PIN_1  | LL_GPIO_PIN_2  | \
                                          LL_GPIO_PIN_3  | LL_GPIO_PIN_4  | LL_GPIO_PIN_5  | \
                                          LL_GPIO_PIN_6  | LL_GPIO_PIN_7  | LL_GPIO_PIN_8  | \
                                          LL_GPIO_PIN_9  | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
                                          LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
                                          LL_GPIO_PIN_15)

Select all pins

Definition at line 146 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Mode

Defines
Mode
GPIO Exported Constants

Defines

#define | LL_GPIO_MODE_ANALOG 0x00000000U
#define | LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0
#define | LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1
#define | LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0)

Define Documentation

#define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0)

Select alternate function mode

Definition at line 163 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_MODE_ANALOG 0x00000000U

Select analog mode

Definition at line 159 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0

Select floating mode

Definition at line 160 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init(), and LL_GPIO_StructInit().

#define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1

Select input mode

Definition at line 161 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0

Select general purpose output mode

Definition at line 162 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Output Type

Defines
Output Type
GPIO Exported Constants

Defines

#define | LL_GPIO_OUTPUT_PUSHPULL 0x00000000U
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0

Define Documentation

#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0

Select open-drain as output type

Definition at line 172 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U

Select push-pull as output type

Definition at line 171 of file stm32f1xx_ll_gpio.h.

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STM32F103xB HAL User Manual: Output Speed

Defines
Output Speed
GPIO Exported Constants

Defines

#define | LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0
#define | LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1
#define | LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0

Define Documentation

#define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0

Select Output mode, max speed 10 MHz

Definition at line 180 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1

Select Output mode, max speed 20 MHz

Definition at line 181 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0

Select Output mode, max speed 50 MHz

Definition at line 182 of file stm32f1xx_ll_gpio.h.

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STM32F103xB HAL User Manual: Pull Up Pull Down

Defines
Pull Up Pull Down
GPIO Exported Constants

Defines

#define | LL_GPIO_PULL_DOWN 0x00000000U
#define | LL_GPIO_PULL_UP GPIO_ODR_ODR0

Define Documentation

#define LL_GPIO_PULL_DOWN 0x00000000U

Select I/O pull down

Definition at line 194 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_StructInit().

#define LL_GPIO_PULL_UP GPIO_ODR_ODR0

Select I/O pull up

Definition at line 195 of file stm32f1xx_ll_gpio.h.

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STM32F103xB HAL User Manual: EVENTOUT Pin

Defines
EVENTOUT Pin
GPIO Exported Constants

Defines

#define | LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0
#define | LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1
#define | LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2
#define | LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3
#define | LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4
#define | LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5
#define | LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6
#define | LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7
#define | LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8
#define | LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9
#define | LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10
#define | LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11
#define | LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12
#define | LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13
#define | LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14
#define | LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15

Define Documentation

#define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0

EVENTOUT on pin 0

Definition at line 205 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1

EVENTOUT on pin 1

Definition at line 206 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10

EVENTOUT on pin 10

Definition at line 215 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11

EVENTOUT on pin 11

Definition at line 216 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12

EVENTOUT on pin 12

Definition at line 217 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13

EVENTOUT on pin 13

Definition at line 218 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14

EVENTOUT on pin 14

Definition at line 219 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15

EVENTOUT on pin 15

Definition at line 220 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2

EVENTOUT on pin 2

Definition at line 207 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3

EVENTOUT on pin 3

Definition at line 208 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4

EVENTOUT on pin 4

Definition at line 209 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5

EVENTOUT on pin 5

Definition at line 210 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6

EVENTOUT on pin 6

Definition at line 211 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7

EVENTOUT on pin 7

Definition at line 212 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8

EVENTOUT on pin 8

Definition at line 213 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9

EVENTOUT on pin 9

Definition at line 214 of file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: EVENTOUT Port

Defines
EVENTOUT Port
GPIO Exported Constants

Defines

#define | LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA
#define | LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB
#define | LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC
#define | LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD
#define | LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE

Define Documentation

#define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA

EVENTOUT on port A

Definition at line 230 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB

EVENTOUT on port B

Definition at line 231 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC

EVENTOUT on port C

Definition at line 232 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD

EVENTOUT on port D

Definition at line 233 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE

EVENTOUT on port E

Definition at line 234 of file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO EXTI PORT

Defines
GPIO EXTI PORT
GPIO Exported Constants

Defines

#define | LL_GPIO_AF_EXTI_PORTA (uint32_t)0
#define | LL_GPIO_AF_EXTI_PORTB (uint32_t)1
#define | LL_GPIO_AF_EXTI_PORTC (uint32_t)2
#define | LL_GPIO_AF_EXTI_PORTD (uint32_t)3
#define | LL_GPIO_AF_EXTI_PORTE (uint32_t)4
#define | LL_GPIO_AF_EXTI_PORTF (uint32_t)5
#define | LL_GPIO_AF_EXTI_PORTG (uint32_t)6

Define Documentation

#define LL_GPIO_AF_EXTI_PORTA (uint32_t)0

EXTI PORT A

Definition at line 243 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_PORTB (uint32_t)1

EXTI PORT B

Definition at line 244 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_PORTC (uint32_t)2

EXTI PORT C

Definition at line 245 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_PORTD (uint32_t)3

EXTI PORT D

Definition at line 246 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_PORTE (uint32_t)4

EXTI PORT E

Definition at line 247 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_PORTF (uint32_t)5

EXTI PORT F

Definition at line 248 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_PORTG (uint32_t)6

EXTI PORT G

Definition at line 249 of file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO EXTI LINE

Defines
GPIO EXTI LINE
GPIO Exported Constants

Defines

#define | LL_GPIO_AF_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0)
#define | LL_GPIO_AF_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0)
#define | LL_GPIO_AF_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0)
#define | LL_GPIO_AF_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0)
#define | LL_GPIO_AF_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1)
#define | LL_GPIO_AF_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1)
#define | LL_GPIO_AF_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1)
#define | LL_GPIO_AF_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1)
#define | LL_GPIO_AF_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2)
#define | LL_GPIO_AF_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2)
#define | LL_GPIO_AF_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2)
#define | LL_GPIO_AF_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2)
#define | LL_GPIO_AF_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3)
#define | LL_GPIO_AF_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3)
#define | LL_GPIO_AF_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3)
#define | LL_GPIO_AF_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3)

Define Documentation

#define LL_GPIO_AF_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0)

EXTI_POSITION_0 | EXTICR[0]

Definition at line 257 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0)

EXTI_POSITION_4 | EXTICR[0]

Definition at line 258 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2)

EXTI_POSITION_8 | EXTICR[2]

Definition at line 267 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2)

EXTI_POSITION_12 | EXTICR[2]

Definition at line 268 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3)

EXTI_POSITION_0 | EXTICR[3]

Definition at line 269 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3)

EXTI_POSITION_4 | EXTICR[3]

Definition at line 270 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3)

EXTI_POSITION_8 | EXTICR[3]

Definition at line 271 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3)

EXTI_POSITION_12 | EXTICR[3]

Definition at line 272 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0)

EXTI_POSITION_8 | EXTICR[0]

Definition at line 259 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0)

EXTI_POSITION_12 | EXTICR[0]

Definition at line 260 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1)

EXTI_POSITION_0 | EXTICR[1]

Definition at line 261 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1)

EXTI_POSITION_4 | EXTICR[1]

Definition at line 262 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1)

EXTI_POSITION_8 | EXTICR[1]

Definition at line 263 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1)

EXTI_POSITION_12 | EXTICR[1]

Definition at line 264 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2)

EXTI_POSITION_0 | EXTICR[2]

Definition at line 265 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_AF_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2)

EXTI_POSITION_4 | EXTICR[2]

Definition at line 266 of file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO Exported Constants

Modules | Defines
GPIO Exported Constants
GPIO

Modules

PIN
Mode
Output Type
Output Speed
Pull Up Pull Down
EVENTOUT Pin
EVENTOUT Port
GPIO EXTI PORT
GPIO EXTI LINE

Defines

#define | LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz
#define | LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz
#define | LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz

Define Documentation

#define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz

Select I/O high output speed

Definition at line 189 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz

Select I/O low output speed

Definition at line 187 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz

Select I/O medium output speed

Definition at line 188 of file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
GPIO Exported Macros

Defines

#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Define Documentation

#define LL_GPIO_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 305 of file stm32f1xx_ll_gpio.h.

#define LL_GPIO_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in GPIO register.

Parameters:
__INSTANCE__ | GPIO Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 297 of file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Port Configuration

Functions
Port Configuration
GPIO Exported Functions

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_GetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, Alternate function Output.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
CRL CNFy LL_GPIO_GetPinMode
Reference Manual to LL API cross reference:
CRL MODEy LL_GPIO_GetPinMode
Reference Manual to LL API cross reference:
CRH CNFy LL_GPIO_GetPinMode
Reference Manual to LL API cross reference:
CRH MODEy LL_GPIO_GetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_MODE_ANALOG
  • LL_GPIO_MODE_FLOATING
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE

Definition at line 398 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
CRL MODEy LL_GPIO_GetPinOutputType
Reference Manual to LL API cross reference:
CRH MODEy LL_GPIO_GetPinOutputType
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
Returned value can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN

Definition at line 549 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
ODR ODR LL_GPIO_GetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_PULL_DOWN
  • LL_GPIO_PULL_UP

Definition at line 615 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin
 | ) |  |

Return gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium, Fast or High speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
CRL MODEy LL_GPIO_GetPinSpeed
Reference Manual to LL API cross reference:
CRH MODEy LL_GPIO_GetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH

Definition at line 475 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked ( GPIO_TypeDef * GPIOx )

Return 1 if one of the pin of a dedicated port is locked.

else return 0.

Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_IsAnyPinLocked
Parameters:
GPIOx GPIO Port
Return values:
State of bit (1 or 0).

Definition at line 695 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return 1 if all pins passed as parameter, of a dedicated port, are locked.

else Return 0.

Reference Manual to LL API cross reference:
LCKR LCKy LL_GPIO_IsPinLocked
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 684 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Lock configuration of several pins for a dedicated port.

Note:
When the lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next reset.
Each lock bit freezes a specific configuration register (control and alternate function registers).
Reference Manual to LL API cross reference:
LCKR LCKK LL_GPIO_LockPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 650 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetPinMode | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Mode
 | ) |  |

Configure gpio mode for a dedicated pin on dedicated port.

Note:
I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, Alternate function Output.
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
CRL CNFy LL_GPIO_SetPinMode
Reference Manual to LL API cross reference:
CRL MODEy LL_GPIO_SetPinMode
Reference Manual to LL API cross reference:
CRH CNFy LL_GPIO_SetPinMode
Reference Manual to LL API cross reference:
CRH MODEy LL_GPIO_SetPinMode
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Mode This parameter can be one of the following values:
  • LL_GPIO_MODE_ANALOG
  • LL_GPIO_MODE_FLOATING
  • LL_GPIO_MODE_INPUT
  • LL_GPIO_MODE_OUTPUT
  • LL_GPIO_MODE_ALTERNATE
Return values:
None

Definition at line 358 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinOutputType | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | OutputType
 | ) |  |

Configure gpio output type for several pins on dedicated port.

Note:
Output type as to be set when gpio pin is in output or alternate modes. Possible type are Push-pull or Open-drain.
Reference Manual to LL API cross reference:
CRL MODEy LL_GPIO_SetPinOutputType
Reference Manual to LL API cross reference:
CRH MODEy LL_GPIO_SetPinOutputType
Parameters:
GPIOx GPIO Port
Pin This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
OutputType This parameter can be one of the following values:
  • LL_GPIO_OUTPUT_PUSHPULL
  • LL_GPIO_OUTPUT_OPENDRAIN
Return values:
None

Definition at line 512 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinPull | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Pull
 | ) |  |

Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.

Note:
Warning: only one pin can be passed as parameter.
Reference Manual to LL API cross reference:
ODR ODR LL_GPIO_SetPinPull
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Pull This parameter can be one of the following values:
  • LL_GPIO_PULL_DOWN
  • LL_GPIO_PULL_UP
Return values:
None

Definition at line 584 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

__STATIC_INLINE void LL_GPIO_SetPinSpeed | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | Pin,
 |  | uint32_t | Speed
 | ) |  |

Configure gpio speed for a dedicated pin on dedicated port.

Note:
I/O speed can be Low, Medium or Fast speed.
Warning: only one pin can be passed as parameter.
Refer to datasheet for frequency specifications and the power supply and load conditions for each speed.
Reference Manual to LL API cross reference:
CRL MODEy LL_GPIO_SetPinSpeed
Reference Manual to LL API cross reference:
CRH MODEy LL_GPIO_SetPinSpeed
Parameters:
GPIOx GPIO Port
Pin This parameter can be one of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
Speed This parameter can be one of the following values:
  • LL_GPIO_SPEED_FREQ_LOW
  • LL_GPIO_SPEED_FREQ_MEDIUM
  • LL_GPIO_SPEED_FREQ_HIGH
Return values:
None

Definition at line 437 of file stm32f1xx_ll_gpio.h.

Referenced by LL_GPIO_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Access

Functions
Data Access
GPIO Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_IsInputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 743 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Return if input data level for several pins of dedicated port is high or low.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_IsOutputPinSet
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
State of bit (1 or 0).

Definition at line 795 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort ( GPIO_TypeDef * GPIOx )

Return full input data register value for a dedicated port.

Reference Manual to LL API cross reference:
IDR IDy LL_GPIO_ReadInputPort
Parameters:
GPIOx GPIO Port
Return values:
Input data register value of port

Definition at line 714 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort ( GPIO_TypeDef * GPIOx )

Return full output data register value for a dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_ReadOutputPort
Parameters:
GPIOx GPIO Port
Return values:
Output data register value of port

Definition at line 766 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_ResetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to low level on dedicated gpio port.

Reference Manual to LL API cross reference:
BRR BRy LL_GPIO_ResetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 853 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_SetOutputPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Set several pins to high level on dedicated gpio port.

Reference Manual to LL API cross reference:
BSRR BSy LL_GPIO_SetOutputPin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 824 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PinMask
 | ) |  |

Toggle data value for several pin of dedicated port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_TogglePin
Parameters:
GPIOx GPIO Port
PinMask This parameter can be a combination of the following values:
  • LL_GPIO_PIN_0
  • LL_GPIO_PIN_1
  • LL_GPIO_PIN_2
  • LL_GPIO_PIN_3
  • LL_GPIO_PIN_4
  • LL_GPIO_PIN_5
  • LL_GPIO_PIN_6
  • LL_GPIO_PIN_7
  • LL_GPIO_PIN_8
  • LL_GPIO_PIN_9
  • LL_GPIO_PIN_10
  • LL_GPIO_PIN_11
  • LL_GPIO_PIN_12
  • LL_GPIO_PIN_13
  • LL_GPIO_PIN_14
  • LL_GPIO_PIN_15
  • LL_GPIO_PIN_ALL
Return values:
None

Definition at line 882 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_WriteOutputPort | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | PortValue
 | ) |  |

Write output data register for the port.

Reference Manual to LL API cross reference:
ODR ODy LL_GPIO_WriteOutputPort
Parameters:
GPIOx | GPIO Port
PortValue | Level value for each pin of the port
Return values:
None

Definition at line 755 of file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Alternate Function Remapping

Functions
Alternate Function Remapping
GPIO Exported Functions

This section propose definition to remap the alternate function to some other port/pins. More...

Functions

__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_SPI1 (void)
Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_SPI1 (void)
Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_SPI1 (void)
Check if SPI1 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_I2C1 (void)
Enable the remapping of I2C1 alternate function SCL and SDA.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_I2C1 (void)
Disable the remapping of I2C1 alternate function SCL and SDA.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_I2C1 (void)
Check if I2C1 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_USART1 (void)
Enable the remapping of USART1 alternate function TX and RX.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_USART1 (void)
Disable the remapping of USART1 alternate function TX and RX.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_USART1 (void)
Check if USART1 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_USART2 (void)
Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_USART2 (void)
Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_USART2 (void)
Check if USART2 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_USART3 (void)
Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial_USART3 (void)
Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_USART3 (void)
Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_TIM1 (void)
Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial_TIM1 (void)
Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_TIM1 (void)
Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_TIM2 (void)
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial2_TIM2 (void)
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial1_TIM2 (void)
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_TIM2 (void)
Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_TIM3 (void)
Enable the remapping of TIM3 alternate function channels 1 to 4.
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial_TIM3 (void)
Enable the remapping of TIM3 alternate function channels 1 to 4.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_TIM3 (void)
Disable the remapping of TIM3 alternate function channels 1 to 4.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_TIM4 (void)
Enable the remapping of TIM4 alternate function channels 1 to 4.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_TIM4 (void)
Disable the remapping of TIM4 alternate function channels 1 to 4.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_TIM4 (void)
Check if TIM4 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial1_CAN1 (void)
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial2_CAN1 (void)
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial3_CAN1 (void)
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_PD01 (void)
Enable the remapping of PD0 and PD1.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_PD01 (void)
Disable the remapping of PD0 and PD1.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_PD01 (void)
Check if PD01 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_SWJ (void)
Enable the Serial wire JTAG configuration.
__STATIC_INLINE void | LL_GPIO_AF_Remap_SWJ_NONJTRST (void)
Enable the Serial wire JTAG configuration.
__STATIC_INLINE void | LL_GPIO_AF_Remap_SWJ_NOJTAG (void)
Enable the Serial wire JTAG configuration.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_SWJ (void)
Disable the Serial wire JTAG configuration.

Detailed Description

This section propose definition to remap the alternate function to some other port/pins.

Function Documentation

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1 ( void )

Disable the remapping of I2C1 alternate function SCL and SDA.

Reference Manual to LL API cross reference:
MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
Note:
DISABLE: No remap (SCL/PB6, SDA/PB7)
Return values:
None

Definition at line 945 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01 ( void )

Disable the remapping of PD0 and PD1.

When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping).

Reference Manual to LL API cross reference:
MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
Note:
DISABLE: No remapping of PD0 and PD1
Return values:
None

Definition at line 1282 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1 ( void )

Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.

Reference Manual to LL API cross reference:
MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
Note:
DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
Return values:
None

Definition at line 913 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ ( void )

Disable the Serial wire JTAG configuration.

Reference Manual to LL API cross reference:
MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
Note:
DISABLE: JTAG-DP Disabled and SW-DP Disabled
Return values:
None

Definition at line 1611 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1 ( void )

Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)

Reference Manual to LL API cross reference:
MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
Note:
DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
Return values:
None

Definition at line 1092 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2 ( void )

Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)

Reference Manual to LL API cross reference:
MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
Note:
DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
Return values:
None

Definition at line 1140 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3 ( void )

Disable the remapping of TIM3 alternate function channels 1 to 4.

Reference Manual to LL API cross reference:
MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
Note:
DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
TIM3_ETR on PE0 is not re-mapped.
Return values:
None

Definition at line 1179 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4 ( void )

Disable the remapping of TIM4 alternate function channels 1 to 4.

Reference Manual to LL API cross reference:
MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
Note:
DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
TIM4_ETR on PE0 is not re-mapped.
Return values:
None

Definition at line 1204 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1 ( void )

Disable the remapping of USART1 alternate function TX and RX.

Reference Manual to LL API cross reference:
MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
Note:
DISABLE: No remap (TX/PA9, RX/PA10)
Return values:
None

Definition at line 977 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2 ( void )

Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.

Reference Manual to LL API cross reference:
MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
Note:
DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
Return values:
None

Definition at line 1009 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3 ( void )

Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.

Reference Manual to LL API cross reference:
MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
Note:
DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
Return values:
None

Definition at line 1055 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1 ( void )

Enable the remapping of I2C1 alternate function SCL and SDA.

Reference Manual to LL API cross reference:
MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
Note:
ENABLE: Remap (SCL/PB8, SDA/PB9)
Return values:
None

Definition at line 934 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01 ( void )

Enable the remapping of PD0 and PD1.

When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping).

Reference Manual to LL API cross reference:
MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
Note:
ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
Return values:
None

Definition at line 1268 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1 ( void )

Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.

Reference Manual to LL API cross reference:
MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
Note:
ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
Return values:
None

Definition at line 902 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ ( void )

Enable the Serial wire JTAG configuration.

Reference Manual to LL API cross reference:
MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
Note:
ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
Return values:
None

Definition at line 1575 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1 ( void )

Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)

Reference Manual to LL API cross reference:
MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
Note:
ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
Return values:
None

Definition at line 1068 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2 ( void )

Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)

Reference Manual to LL API cross reference:
MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
Note:
ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
Return values:
None

Definition at line 1104 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3 ( void )

Enable the remapping of TIM3 alternate function channels 1 to 4.

Reference Manual to LL API cross reference:
MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
Note:
ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
TIM3_ETR on PE0 is not re-mapped.
Return values:
None

Definition at line 1153 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4 ( void )

Enable the remapping of TIM4 alternate function channels 1 to 4.

Reference Manual to LL API cross reference:
MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
Note:
ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
TIM4_ETR on PE0 is not re-mapped.
Return values:
None

Definition at line 1193 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1 ( void )

Enable the remapping of USART1 alternate function TX and RX.

Reference Manual to LL API cross reference:
MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
Note:
ENABLE: Remap (TX/PB6, RX/PB7)
Return values:
None

Definition at line 966 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2 ( void )

Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.

Reference Manual to LL API cross reference:
MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
Note:
ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
Return values:
None

Definition at line 998 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3 ( void )

Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.

Reference Manual to LL API cross reference:
MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
Note:
ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
Return values:
None

Definition at line 1031 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1 ( void )

Check if I2C1 has been remaped or not.

Reference Manual to LL API cross reference:
MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
Return values:
State of bit (1 or 0).

Definition at line 955 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01 ( void )

Check if PD01 has been remaped or not.

Reference Manual to LL API cross reference:
MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
Return values:
State of bit (1 or 0).

Definition at line 1292 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1 ( void )

Check if SPI1 has been remaped or not.

Reference Manual to LL API cross reference:
MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
Return values:
State of bit (1 or 0).

Definition at line 923 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4 ( void )

Check if TIM4 has been remaped or not.

Reference Manual to LL API cross reference:
MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
Return values:
State of bit (1 or 0).

Definition at line 1214 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1 ( void )

Check if USART1 has been remaped or not.

Reference Manual to LL API cross reference:
MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
Return values:
State of bit (1 or 0).

Definition at line 987 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2 ( void )

Check if USART2 has been remaped or not.

Reference Manual to LL API cross reference:
MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
Return values:
State of bit (1 or 0).

Definition at line 1019 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG ( void )

Enable the Serial wire JTAG configuration.

Reference Manual to LL API cross reference:
MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
Note:
NOJTAG: JTAG-DP Disabled and SW-DP Enabled
Return values:
None

Definition at line 1599 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST ( void )

Enable the Serial wire JTAG configuration.

Reference Manual to LL API cross reference:
MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
Note:
NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
Return values:
None

Definition at line 1587 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1 ( void )

Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.

Reference Manual to LL API cross reference:
MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
Note:
CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
Return values:
None

Definition at line 1228 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2 ( void )

Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)

Reference Manual to LL API cross reference:
MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
Note:
PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
Return values:
None

Definition at line 1128 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1 ( void )

Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.

Reference Manual to LL API cross reference:
MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
Note:
CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
Return values:
None

Definition at line 1240 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2 ( void )

Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)

Reference Manual to LL API cross reference:
MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
Note:
PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
Return values:
None

Definition at line 1116 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1 ( void )

Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.

Reference Manual to LL API cross reference:
MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
Note:
CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
Return values:
None

Definition at line 1252 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1 ( void )

Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)

Reference Manual to LL API cross reference:
MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
Note:
PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
Return values:
None

Definition at line 1080 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3 ( void )

Enable the remapping of TIM3 alternate function channels 1 to 4.

Reference Manual to LL API cross reference:
MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
Note:
PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
TIM3_ETR on PE0 is not re-mapped.
Return values:
None

Definition at line 1166 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3 ( void )

Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.

Reference Manual to LL API cross reference:
MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
Note:
PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
Return values:
None

Definition at line 1043 of file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Output Event configuration

Functions
Output Event configuration
GPIO Exported Functions

This section propose definition to Configure EVENTOUT Cortex feature . More...

Functions

__STATIC_INLINE void | LL_GPIO_AF_ConfigEventout (uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
__STATIC_INLINE void | LL_GPIO_AF_EnableEventout (void)
Enables the Event Output.
__STATIC_INLINE void | LL_GPIO_AF_DisableEventout (void)
Disables the Event Output.

Detailed Description

This section propose definition to Configure EVENTOUT Cortex feature .

Function Documentation

__STATIC_INLINE void LL_GPIO_AF_ConfigEventout | ( | uint32_t | LL_GPIO_PortSource,
 |  | uint32_t | LL_GPIO_PinSource
 | ) |  |

Configures the port and pin on which the EVENTOUT Cortex signal will be connected.

Reference Manual to LL API cross reference:
EVCR PORT LL_GPIO_AF_ConfigEventout
EVCR PIN LL_GPIO_AF_ConfigEventout
Parameters:
LL_GPIO_PortSource This parameter can be one of the following values:
  • LL_GPIO_AF_EVENTOUT_PORT_A
  • LL_GPIO_AF_EVENTOUT_PORT_B
  • LL_GPIO_AF_EVENTOUT_PORT_C
  • LL_GPIO_AF_EVENTOUT_PORT_D
  • LL_GPIO_AF_EVENTOUT_PORT_E
LL_GPIO_PinSource This parameter can be one of the following values:
  • LL_GPIO_AF_EVENTOUT_PIN_0
  • LL_GPIO_AF_EVENTOUT_PIN_1
  • LL_GPIO_AF_EVENTOUT_PIN_2
  • LL_GPIO_AF_EVENTOUT_PIN_3
  • LL_GPIO_AF_EVENTOUT_PIN_4
  • LL_GPIO_AF_EVENTOUT_PIN_5
  • LL_GPIO_AF_EVENTOUT_PIN_6
  • LL_GPIO_AF_EVENTOUT_PIN_7
  • LL_GPIO_AF_EVENTOUT_PIN_8
  • LL_GPIO_AF_EVENTOUT_PIN_9
  • LL_GPIO_AF_EVENTOUT_PIN_10
  • LL_GPIO_AF_EVENTOUT_PIN_11
  • LL_GPIO_AF_EVENTOUT_PIN_12
  • LL_GPIO_AF_EVENTOUT_PIN_13
  • LL_GPIO_AF_EVENTOUT_PIN_14
  • LL_GPIO_AF_EVENTOUT_PIN_15
Return values:
None

Definition at line 2236 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_DisableEventout ( void )

Disables the Event Output.

Reference Manual to LL API cross reference:
EVCR EVOE LL_GPIO_AF_DisableEventout
Return values:
None

Definition at line 2256 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_EnableEventout ( void )

Enables the Event Output.

Reference Manual to LL API cross reference:
EVCR EVOE LL_GPIO_AF_EnableEventout
Return values:
None

Definition at line 2246 of file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: EXTI external interrupt

Functions
EXTI external interrupt
GPIO Exported Functions

This section Configure source input for the EXTI external interrupt . More...

Functions

__STATIC_INLINE void | LL_GPIO_AF_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_GPIO_AF_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.

Detailed Description

This section Configure source input for the EXTI external interrupt .

Function Documentation

__STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource ( uint32_t Line )

Get the configured defined for specific EXTI Line.

Reference Manual to LL API cross reference:
AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource
AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource
AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource
AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
Parameters:
Line This parameter can be one of the following values:
  • LL_GPIO_AF_EXTI_LINE0
  • LL_GPIO_AF_EXTI_LINE1
  • LL_GPIO_AF_EXTI_LINE2
  • LL_GPIO_AF_EXTI_LINE3
  • LL_GPIO_AF_EXTI_LINE4
  • LL_GPIO_AF_EXTI_LINE5
  • LL_GPIO_AF_EXTI_LINE6
  • LL_GPIO_AF_EXTI_LINE7
  • LL_GPIO_AF_EXTI_LINE8
  • LL_GPIO_AF_EXTI_LINE9
  • LL_GPIO_AF_EXTI_LINE10
  • LL_GPIO_AF_EXTI_LINE11
  • LL_GPIO_AF_EXTI_LINE12
  • LL_GPIO_AF_EXTI_LINE13
  • LL_GPIO_AF_EXTI_LINE14
  • LL_GPIO_AF_EXTI_LINE15
Return values:
Returned value can be one of the following values:
  • LL_GPIO_AF_EXTI_PORTA
  • LL_GPIO_AF_EXTI_PORTB
  • LL_GPIO_AF_EXTI_PORTC
  • LL_GPIO_AF_EXTI_PORTD
  • LL_GPIO_AF_EXTI_PORTE
  • LL_GPIO_AF_EXTI_PORTF
  • LL_GPIO_AF_EXTI_PORTG

Definition at line 2339 of file stm32f1xx_ll_gpio.h.

__STATIC_INLINE void LL_GPIO_AF_SetEXTISource | ( | uint32_t | Port,
 |  | uint32_t | Line
 | ) |  |

Configure source input for the EXTI external interrupt.

Reference Manual to LL API cross reference:
AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource
AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource
AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource
AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
Parameters:
Port This parameter can be one of the following values:
  • LL_GPIO_AF_EXTI_PORTA
  • LL_GPIO_AF_EXTI_PORTB
  • LL_GPIO_AF_EXTI_PORTC
  • LL_GPIO_AF_EXTI_PORTD
  • LL_GPIO_AF_EXTI_PORTE
  • LL_GPIO_AF_EXTI_PORTF
  • LL_GPIO_AF_EXTI_PORTG
Line This parameter can be one of the following values:
  • LL_GPIO_AF_EXTI_LINE0
  • LL_GPIO_AF_EXTI_LINE1
  • LL_GPIO_AF_EXTI_LINE2
  • LL_GPIO_AF_EXTI_LINE3
  • LL_GPIO_AF_EXTI_LINE4
  • LL_GPIO_AF_EXTI_LINE5
  • LL_GPIO_AF_EXTI_LINE6
  • LL_GPIO_AF_EXTI_LINE7
  • LL_GPIO_AF_EXTI_LINE8
  • LL_GPIO_AF_EXTI_LINE9
  • LL_GPIO_AF_EXTI_LINE10
  • LL_GPIO_AF_EXTI_LINE11
  • LL_GPIO_AF_EXTI_LINE12
  • LL_GPIO_AF_EXTI_LINE13
  • LL_GPIO_AF_EXTI_LINE14
  • LL_GPIO_AF_EXTI_LINE15
Return values:
None

Definition at line 2302 of file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_GPIO_DeInit ( GPIO_TypeDef * GPIOx )

De-initialize GPIO registers (Registers restored to their default values).

Parameters:
GPIOx GPIO Port
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are de-initialized
  • ERROR: Wrong GPIO Port

Definition at line 105 of file stm32f1xx_ll_gpio.c.

References assert_param, LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_GPIOA, LL_APB2_GRP1_PERIPH_GPIOB, LL_APB2_GRP1_PERIPH_GPIOC, LL_APB2_GRP1_PERIPH_GPIOD, LL_APB2_GRP1_PERIPH_GPIOE, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | LL_GPIO_InitTypeDef * | GPIO_InitStruct
 | ) |  |

Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.

Parameters:
GPIOx GPIO Port
GPIO_InitStruct,: pointer to a LL_GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
  • ERROR: Not applicable

Definition at line 171 of file stm32f1xx_ll_gpio.c.

References assert_param, IS_LL_GPIO_MODE, IS_LL_GPIO_OUTPUT_TYPE, IS_LL_GPIO_PIN, IS_LL_GPIO_PULL, LL_GPIO_MODE_FLOATING, LL_GPIO_MODE_OUTPUT, LL_GPIO_SetPinMode(), LL_GPIO_SetPinOutputType(), LL_GPIO_SetPinPull(), LL_GPIO_SetPinSpeed(), LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

void LL_GPIO_StructInit ( LL_GPIO_InitTypeDef * GPIO_InitStruct )

Set each LL_GPIO_InitTypeDef field to default value.

Parameters:
GPIO_InitStruct,: pointer to a LL_GPIO_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 234 of file stm32f1xx_ll_gpio.c.

References LL_GPIO_MODE_FLOATING, LL_GPIO_OUTPUT_OPENDRAIN, LL_GPIO_PIN_ALL, LL_GPIO_PULL_DOWN, LL_GPIO_InitTypeDef::Mode, LL_GPIO_InitTypeDef::OutputType, LL_GPIO_InitTypeDef::Pin, LL_GPIO_InitTypeDef::Pull, and LL_GPIO_InitTypeDef::Speed.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C

Modules
I2C
STM32F1xx_LL_Driver

Modules

I2C Private Constants
I2C Private Macros
I2C Exported Init structure
I2C Exported Constants
I2C Exported Macros
I2C Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for I2C registers.

Register | Bit | Function
CCR | CCR | LL_I2C_ConfigSpeed
 |  | LL_I2C_GetClockPeriod
 |  | LL_I2C_SetClockPeriod
 | DUTY | LL_I2C_ConfigSpeed
 |  | LL_I2C_GetDutyCycle
 |  | LL_I2C_SetDutyCycle
 | FS | LL_I2C_ConfigSpeed
 |  | LL_I2C_GetClockSpeedMode
 |  | LL_I2C_SetClockSpeedMode
CR1 | ACK | LL_I2C_AcknowledgeNextData
 | ALERT | LL_I2C_DisableSMBusAlert
 |  | LL_I2C_EnableSMBusAlert
 |  | LL_I2C_IsEnabledSMBusAlert
 | ENARP | LL_I2C_GetMode
 |  | LL_I2C_SetMode
 | ENGC | LL_I2C_DisableGeneralCall
 |  | LL_I2C_EnableGeneralCall
 |  | LL_I2C_IsEnabledGeneralCall
 | ENPEC | LL_I2C_DisableSMBusPEC
 |  | LL_I2C_EnableSMBusPEC
 |  | LL_I2C_IsEnabledSMBusPEC
 | NOSTRETCH | LL_I2C_DisableClockStretching
 |  | LL_I2C_EnableClockStretching
 |  | LL_I2C_IsEnabledClockStretching
 | PE | LL_I2C_ClearFlag_STOP
 |  | LL_I2C_Disable
 |  | LL_I2C_Enable
 |  | LL_I2C_IsEnabled
 | PEC | LL_I2C_DisableSMBusPECCompare
 |  | LL_I2C_EnableSMBusPECCompare
 |  | LL_I2C_IsEnabledSMBusPECCompare
 | POS | LL_I2C_DisableBitPOS
 |  | LL_I2C_EnableBitPOS
 |  | LL_I2C_IsEnabledBitPOS
 | SMBTYPE | LL_I2C_GetMode
 |  | LL_I2C_SetMode
 | SMBUS | LL_I2C_GetMode
 |  | LL_I2C_SetMode
 | START | LL_I2C_GenerateStartCondition
 | STOP | LL_I2C_GenerateStopCondition
 | SWRST | LL_I2C_DisableReset
 |  | LL_I2C_EnableReset
 |  | LL_I2C_IsResetEnabled
CR2 | DMAEN | LL_I2C_DisableDMAReq_RX
 |  | LL_I2C_DisableDMAReq_TX
 |  | LL_I2C_EnableDMAReq_RX
 |  | LL_I2C_EnableDMAReq_TX
 |  | LL_I2C_IsEnabledDMAReq_RX
 |  | LL_I2C_IsEnabledDMAReq_TX
 | FREQ | LL_I2C_ConfigSpeed
 |  | LL_I2C_GetPeriphClock
 |  | LL_I2C_SetPeriphClock
 | ITBUFEN | LL_I2C_DisableIT_BUF
 |  | LL_I2C_DisableIT_RX
 |  | LL_I2C_DisableIT_TX
 |  | LL_I2C_EnableIT_BUF
 |  | LL_I2C_EnableIT_RX
 |  | LL_I2C_EnableIT_TX
 |  | LL_I2C_IsEnabledIT_BUF
 |  | LL_I2C_IsEnabledIT_RX
 |  | LL_I2C_IsEnabledIT_TX
 | ITERREN | LL_I2C_DisableIT_ERR
 |  | LL_I2C_EnableIT_ERR
 |  | LL_I2C_IsEnabledIT_ERR
 | ITEVTEN | LL_I2C_DisableIT_EVT
 |  | LL_I2C_DisableIT_RX
 |  | LL_I2C_DisableIT_TX
 |  | LL_I2C_EnableIT_EVT
 |  | LL_I2C_EnableIT_RX
 |  | LL_I2C_EnableIT_TX
 |  | LL_I2C_IsEnabledIT_EVT
 |  | LL_I2C_IsEnabledIT_RX
 |  | LL_I2C_IsEnabledIT_TX
 | LAST | LL_I2C_DisableLastDMA
 |  | LL_I2C_EnableLastDMA
 |  | LL_I2C_IsEnabledLastDMA
DR | DR | LL_I2C_DMA_GetRegAddr
 |  | LL_I2C_ReceiveData8
 |  | LL_I2C_TransmitData8
OAR1 | ADD0 | LL_I2C_SetOwnAddress1
 | ADD1_7 | LL_I2C_SetOwnAddress1
 | ADD8_9 | LL_I2C_SetOwnAddress1
 | ADDMODE | LL_I2C_SetOwnAddress1
OAR2 | ADD2 | LL_I2C_SetOwnAddress2
 | ENDUAL | LL_I2C_DisableOwnAddress2
 |  | LL_I2C_EnableOwnAddress2
 |  | LL_I2C_IsEnabledOwnAddress2
SR1 | ADD10 | LL_I2C_IsActiveFlag_ADD10
 | ADDR | LL_I2C_ClearFlag_ADDR
 |  | LL_I2C_IsActiveFlag_ADDR
 | AF | LL_I2C_ClearFlag_AF
 |  | LL_I2C_IsActiveFlag_AF
 | ARLO | LL_I2C_ClearFlag_ARLO
 |  | LL_I2C_IsActiveFlag_ARLO
 | BERR | LL_I2C_ClearFlag_BERR
 |  | LL_I2C_IsActiveFlag_BERR
 | BTF | LL_I2C_IsActiveFlag_BTF
 | OVR | LL_I2C_ClearFlag_OVR
 |  | LL_I2C_IsActiveFlag_OVR
 | PECERR | LL_I2C_ClearSMBusFlag_PECERR
 |  | LL_I2C_IsActiveSMBusFlag_PECERR
 | RXNE | LL_I2C_IsActiveFlag_RXNE
 | SB | LL_I2C_IsActiveFlag_SB
 | SMBALERT | LL_I2C_ClearSMBusFlag_ALERT
 |  | LL_I2C_IsActiveSMBusFlag_ALERT
 | STOPF | LL_I2C_ClearFlag_STOP
 |  | LL_I2C_IsActiveFlag_STOP
 | TIMEOUT | LL_I2C_ClearSMBusFlag_TIMEOUT
 |  | LL_I2C_IsActiveSMBusFlag_TIMEOUT
 | TXE | LL_I2C_IsActiveFlag_TXE
SR2 | BUSY | LL_I2C_IsActiveFlag_BUSY
 | DUALF | LL_I2C_IsActiveFlag_DUAL
 | GENCALL | LL_I2C_IsActiveFlag_GENCALL
 | MSL | LL_I2C_IsActiveFlag_MSL
 | PEC | LL_I2C_GetSMBusPEC
 | SMBDEFAULT | LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
 | SMBHOST | LL_I2C_IsActiveSMBusFlag_SMBHOST
 | TRA | LL_I2C_GetTransferDirection
TRISE | TRISE | LL_I2C_ConfigSpeed
 |  | LL_I2C_GetRiseTime
 |  | LL_I2C_SetRiseTime
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Private Constants

Defines
I2C Private Constants
I2C

Defines

#define | LL_I2C_MAX_SPEED_STANDARD 100000U
#define | LL_I2C_MAX_SPEED_FAST 400000U

Define Documentation

#define LL_I2C_MAX_SPEED_FAST 400000U

Definition at line 69 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_MAX_SPEED_STANDARD 100000U

Definition at line 68 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_ConfigSpeed().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Private Macros

Defines
I2C Private Macros
I2C

Defines

#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
#define | IS_I2C_DUTY_CYCLE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Define Documentation

#define IS_I2C_CLOCK_SPEED ( __VALUE__ ) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))

Definition at line 72 of file stm32f1xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_I2C_DUTY_CYCLE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
                                                 ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))

Definition at line 74 of file stm32f1xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRESS1 ( __VALUE__ ) ((__VALUE__) <= 0x000003FFU)

Definition at line 77 of file stm32f1xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_OWN_ADDRSIZE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))

Definition at line 82 of file stm32f1xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_PERIPHERAL_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_MODE_I2C)          || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))

Definition at line 67 of file stm32f1xx_ll_i2c.c.

Referenced by LL_I2C_Init().

#define IS_LL_I2C_TYPE_ACKNOWLEDGE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2C_ACK) || \
                                                 ((__VALUE__) == LL_I2C_NACK))

Definition at line 79 of file stm32f1xx_ll_i2c.c.

Referenced by LL_I2C_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2C_InitTypeDef Struct Reference
I2C Exported Init structure

#include <stm32f1xx_ll_i2c.h>

Data Fields

uint32_t | PeripheralMode
uint32_t | ClockSpeed
uint32_t | DutyCycle
uint32_t | OwnAddress1
uint32_t | TypeAcknowledge
uint32_t | OwnAddrSize

Detailed Description

Definition at line 89 of file stm32f1xx_ll_i2c.h.

Field Documentation

uint32_t LL_I2C_InitTypeDef::ClockSpeed

Specifies the clock frequency. This parameter must be set to a value lower than 400kHz (in Hz)

This feature can be modified afterwards using unitary function LL_I2C_SetClockPeriod() or LL_I2C_SetDutyCycle() or LL_I2C_SetClockSpeedMode() or LL_I2C_ConfigSpeed().

Definition at line 96 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::DutyCycle

Specifies the I2C fast mode duty cycle. This parameter can be a value of Fast Mode Duty Cycle

This feature can be modified afterwards using unitary function LL_I2C_SetDutyCycle().

Definition at line 102 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddress1

Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 107 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::OwnAddrSize

Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of Own Address 1 Length

This feature can be modified afterwards using unitary function LL_I2C_SetOwnAddress1().

Definition at line 117 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::PeripheralMode

Specifies the peripheral mode. This parameter can be a value of Peripheral Mode

This feature can be modified afterwards using unitary function LL_I2C_SetMode().

Definition at line 91 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

uint32_t LL_I2C_InitTypeDef::TypeAcknowledge

Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. This parameter can be a value of Acknowledge Generation

This feature can be modified afterwards using unitary function LL_I2C_AcknowledgeNextData().

Definition at line 112 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init(), and LL_I2C_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_i2c.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2C Exported Constants

Flags defines which can be used with LL_I2C_ReadReg function. More...

Defines

#define | LL_I2C_SR1_SB I2C_SR1_SB
#define | LL_I2C_SR1_ADDR I2C_SR1_ADDR
#define | LL_I2C_SR1_BTF I2C_SR1_BTF
#define | LL_I2C_SR1_ADD10 I2C_SR1_ADD10
#define | LL_I2C_SR1_STOPF I2C_SR1_STOPF
#define | LL_I2C_SR1_RXNE I2C_SR1_RXNE
#define | LL_I2C_SR1_TXE I2C_SR1_TXE
#define | LL_I2C_SR1_BERR I2C_SR1_BERR
#define | LL_I2C_SR1_ARLO I2C_SR1_ARLO
#define | LL_I2C_SR1_AF I2C_SR1_AF
#define | LL_I2C_SR1_OVR I2C_SR1_OVR
#define | LL_I2C_SR1_PECERR I2C_ISR_PECERR
#define | LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_SR1_SMALERT I2C_ISR_SMALERT
#define | LL_I2C_SR2_MSL I2C_SR2_MSL
#define | LL_I2C_SR2_BUSY I2C_SR2_BUSY
#define | LL_I2C_SR2_TRA I2C_SR2_TRA
#define | LL_I2C_SR2_GENCALL I2C_SR2_GENCALL
#define | LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT
#define | LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST
#define | LL_I2C_SR2_DUALF I2C_SR2_DUALF

Detailed Description

Flags defines which can be used with LL_I2C_ReadReg function.

Define Documentation

#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10

10-bit header sent (master mode)

Definition at line 140 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_ADDR I2C_SR1_ADDR

Address sent (master mode) or Address matched flag (slave mode)

Definition at line 137 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_AF I2C_SR1_AF

Acknowledge failure flag

Definition at line 146 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_ARLO I2C_SR1_ARLO

Arbitration lost

Definition at line 145 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_BERR I2C_SR1_BERR

Bus error

Definition at line 144 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_BTF I2C_SR1_BTF

Byte Transfer Finished flag

Definition at line 139 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_OVR I2C_SR1_OVR

Overrun/Underrun

Definition at line 147 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_PECERR I2C_ISR_PECERR

PEC Error in reception (SMBus mode)

Definition at line 148 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_RXNE I2C_SR1_RXNE

Data register not empty (receivers)

Definition at line 142 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_SB I2C_SR1_SB

Start Bit (master mode)

Definition at line 136 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT

SMBus alert (SMBus mode)

Definition at line 150 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_STOPF I2C_SR1_STOPF

Stop detection flag (slave mode)

Definition at line 141 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT

Timeout detection flag (SMBus mode)

Definition at line 149 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR1_TXE I2C_SR1_TXE

Data register empty (transmitters)

Definition at line 143 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR2_BUSY I2C_SR2_BUSY

Bus busy flag

Definition at line 152 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR2_DUALF I2C_SR2_DUALF

Dual flag (Slave mode)

Definition at line 157 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL

General call address (Slave mode)

Definition at line 154 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR2_MSL I2C_SR2_MSL

Master/Slave flag

Definition at line 151 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT

SMBus Device default address (Slave mode)

Definition at line 155 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST

SMBus Host address (Slave mode)

Definition at line 156 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_SR2_TRA I2C_SR2_TRA

Transmitter/receiver direction

Definition at line 153 of file stm32f1xx_ll_i2c.h.

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STM32F103xB HAL User Manual: IT Defines

Defines
IT Defines
I2C Exported Constants

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions. More...

Defines

#define | LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN
#define | LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN
#define | LL_I2C_CR2_ITERREN I2C_CR2_ITERREN

Detailed Description

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Define Documentation

#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN

Buffer interrupts enable

Definition at line 167 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN

Error interrupts enable

Definition at line 168 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN

Events interrupts enable

Definition at line 166 of file stm32f1xx_ll_i2c.h.

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STM32F103xB HAL User Manual: Own Address 1 Length

Defines
Own Address 1 Length
I2C Exported Constants

Defines

#define | LL_I2C_OWNADDRESS1_7BIT 0x00004000U
#define | LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U)

Define Documentation

#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U)

Own address 1 is a 10-bit address.

Definition at line 177 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U

Own address 1 is a 7-bit address.

Definition at line 176 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Fast Mode Duty Cycle

Defines
Fast Mode Duty Cycle
I2C Exported Constants

Defines

#define | LL_I2C_DUTYCYCLE_2 0x00000000U
#define | LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY

Define Documentation

#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY

I2C fast mode Tlow/Thigh = 16/9

Definition at line 186 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_DUTYCYCLE_2 0x00000000U

I2C fast mode Tlow/Thigh = 2

Definition at line 185 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Master Clock Speed Mode

Defines
Master Clock Speed Mode
I2C Exported Constants

Defines

#define | LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U
#define | LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS

Define Documentation

#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS

Master clock speed range is fast mode

Definition at line 195 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_ConfigSpeed().

#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U

Master clock speed range is standard mode

Definition at line 194 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_ConfigSpeed().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Mode

Defines
Peripheral Mode
I2C Exported Constants

Defines

#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP)
#define | LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP)

Define Documentation

#define LL_I2C_MODE_I2C 0x00000000U

I2C Master or Slave mode

Definition at line 203 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS

SMBus Device default mode (Default address not acknowledge)

Definition at line 205 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP)

SMBus Device Default address acknowledge

Definition at line 206 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP)

SMBus Host address acknowledge

Definition at line 204 of file stm32f1xx_ll_i2c.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Acknowledge Generation

Defines
Acknowledge Generation
I2C Exported Constants

Defines

#define | LL_I2C_ACK I2C_CR1_ACK
#define | LL_I2C_NACK 0x00000000U

Define Documentation

#define LL_I2C_ACK I2C_CR1_ACK

ACK is sent after current received byte.

Definition at line 214 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_NACK 0x00000000U

NACK is sent after current received byte.

Definition at line 215 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Read Write Direction

Defines
Read Write Direction
I2C Exported Constants

Defines

#define | LL_I2C_DIRECTION_WRITE I2C_SR2_TRA
#define | LL_I2C_DIRECTION_READ 0x00000000U

Define Documentation

#define LL_I2C_DIRECTION_READ 0x00000000U

Bus is in read transfer

Definition at line 224 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA

Bus is in write transfer

Definition at line 223 of file stm32f1xx_ll_i2c.h.

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STM32F103xB HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2C Exported Macros

Defines

#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.

Define Documentation

#define LL_I2C_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 257 of file stm32f1xx_ll_i2c.h.

#define LL_I2C_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2C register.

Parameters:
__INSTANCE__ | I2C Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 249 of file stm32f1xx_ll_i2c.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Exported_Macros_Helper

Defines
Exported_Macros_Helper
I2C Exported Macros

Defines

#define | __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
Convert Peripheral Clock Frequency in Mhz.
#define | __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
Convert Peripheral Clock Frequency in Hz.
#define | __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
Compute I2C Clock rising time.
#define | __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__)
Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
#define | __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
#define | __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__)
Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
#define | __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
Get the Least significant bits of a 10-Bits address.
#define | __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
Convert a 10-Bits address to a 10-Bits header with Write direction.
#define | __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
Convert a 10-Bits address to a 10-Bits header with Read direction.

Define Documentation

#define __LL_I2C_10BIT_ADDRESS ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))

Get the Least significant bits of a 10-Bits address.

Parameters:
__ADDRESS__ This parameter must be a value of a 10-Bits slave address.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 327 of file stm32f1xx_ll_i2c.h.

#define __LL_I2C_10BIT_HEADER_READ ( __ADDRESS__ ) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))

Convert a 10-Bits address to a 10-Bits header with Read direction.

Parameters:
__ADDRESS__ This parameter must be a value of a 10-Bits slave address.
Return values:
Value between Min_Data=0xF1 and Max_Data=0xF7

Definition at line 341 of file stm32f1xx_ll_i2c.h.

#define __LL_I2C_10BIT_HEADER_WRITE ( __ADDRESS__ ) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))

Convert a 10-Bits address to a 10-Bits header with Write direction.

Parameters:
__ADDRESS__ This parameter must be a value of a 10-Bits slave address.
Return values:
Value between Min_Data=0xF0 and Max_Data=0xF6

Definition at line 334 of file stm32f1xx_ll_i2c.h.

#define __LL_I2C_FREQ_HZ_TO_MHZ ( __PCLK__ ) (uint32_t)((__PCLK__)/1000000U)

Convert Peripheral Clock Frequency in Mhz.

Parameters:
__PCLK__ This parameter must be a value of peripheral clock (in Hz).
Return values:
Value of peripheral clock (in Mhz)

Definition at line 271 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_ConfigSpeed(), and LL_I2C_SetPeriphClock().

#define __LL_I2C_FREQ_MHZ_TO_HZ ( __PCLK__ ) (uint32_t)((__PCLK__)*1000000U)

Convert Peripheral Clock Frequency in Hz.

Parameters:
__PCLK__ This parameter must be a value of peripheral clock (in Mhz).
Return values:
Value of peripheral clock (in Hz)

Definition at line 278 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_GetPeriphClock().

#define __LL_I2C_RISE_TIME | ( | __FREQRANGE__,
 |  | __SPEED__
 | ) | (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))

Compute I2C Clock rising time.

Parameters:
__FREQRANGE__ | This parameter must be a value of peripheral clock (in Mhz).
__SPEED__ | This parameter must be a value lower than 400kHz (in Hz).
Return values:
Value between Min_Data=0x02 and Max_Data=0x3F

Definition at line 286 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_ConfigSpeed().

#define __LL_I2C_SPEED_FAST_TO_CCR | ( | __PCLK__,
 |  | __SPEED__,
 |  | __DUTYCYCLE__
 | ) |
Value:
(uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
                                                                            (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
                                                                            (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))

Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.

Parameters:
__PCLK__ | This parameter must be a value of peripheral clock (in Hz).
__SPEED__ | This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
__DUTYCYCLE__ This parameter can be one of the following values:
  • LL_I2C_DUTYCYCLE_2
  • LL_I2C_DUTYCYCLE_16_9
Return values:
Value between Min_Data=0x001 and Max_Data=0xFFF

Definition at line 318 of file stm32f1xx_ll_i2c.h.

#define __LL_I2C_SPEED_STANDARD_TO_CCR | ( | __PCLK__,
 |  | __SPEED__
 | ) | (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))

Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.

Parameters:
__PCLK__ | This parameter must be a value of peripheral clock (in Hz).
__SPEED__ | This parameter must be a value lower than 100kHz (in Hz).
Return values:
Value between Min_Data=0x004 and Max_Data=0xFFF.

Definition at line 307 of file stm32f1xx_ll_i2c.h.

#define __LL_I2C_SPEED_TO_CCR | ( | __PCLK__,
 |  | __SPEED__,
 |  | __DUTYCYCLE__
 | ) |
Value:
(uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
                                                                                (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
                                                                                (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))

Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.

Parameters:
__PCLK__ | This parameter must be a value of peripheral clock (in Hz).
__SPEED__ | This parameter must be a value lower than 400kHz (in Hz).
__DUTYCYCLE__ This parameter can be one of the following values:
  • LL_I2C_DUTYCYCLE_2
  • LL_I2C_DUTYCYCLE_16_9
Return values:
Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.

Definition at line 297 of file stm32f1xx_ll_i2c.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration

Functions
Configuration
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetPeriphClock (I2C_TypeDef *I2Cx, uint32_t PeriphClock)
Configure the Peripheral clock frequency.
__STATIC_INLINE uint32_t | LL_I2C_GetPeriphClock (I2C_TypeDef *I2Cx)
Get the Peripheral clock frequency.
__STATIC_INLINE void | LL_I2C_SetDutyCycle (I2C_TypeDef *I2Cx, uint32_t DutyCycle)
Configure the Duty cycle (Fast mode only).
__STATIC_INLINE uint32_t | LL_I2C_GetDutyCycle (I2C_TypeDef *I2Cx)
Get the Duty cycle (Fast mode only).
__STATIC_INLINE void | LL_I2C_SetClockSpeedMode (I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
Configure the I2C master clock speed mode.
__STATIC_INLINE uint32_t | LL_I2C_GetClockSpeedMode (I2C_TypeDef *I2Cx)
Get the the I2C master speed mode.
__STATIC_INLINE void | LL_I2C_SetRiseTime (I2C_TypeDef *I2Cx, uint32_t RiseTime)
Configure the SCL, SDA rising time.
__STATIC_INLINE uint32_t | LL_I2C_GetRiseTime (I2C_TypeDef *I2Cx)
Get the SCL, SDA rising time.
__STATIC_INLINE void | LL_I2C_SetClockPeriod (I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
Configure the SCL high and low period.
__STATIC_INLINE uint32_t | LL_I2C_GetClockPeriod (I2C_TypeDef *I2Cx)
Get the SCL high and low period.
__STATIC_INLINE void | LL_I2C_ConfigSpeed (I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed, uint32_t DutyCycle)
Configure the SCL speed.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_ConfigSpeed | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | PeriphClock,
 |  | uint32_t | ClockSpeed,
 |  | uint32_t | DutyCycle
 | ) |  |

Configure the SCL speed.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR2 FREQ LL_I2C_ConfigSpeed
TRISE TRISE LL_I2C_ConfigSpeed
CCR FS LL_I2C_ConfigSpeed
CCR DUTY LL_I2C_ConfigSpeed
CCR CCR LL_I2C_ConfigSpeed
Parameters:
I2Cx | I2C Instance.
PeriphClock | Peripheral Clock (in Hz)
ClockSpeed | This parameter must be a value lower than 400kHz (in Hz).
DutyCycle This parameter can be one of the following values:
  • LL_I2C_DUTYCYCLE_2
  • LL_I2C_DUTYCYCLE_16_9
Return values:
None

Definition at line 747 of file stm32f1xx_ll_i2c.h.

References __LL_I2C_FREQ_HZ_TO_MHZ, __LL_I2C_RISE_TIME, LL_I2C_CLOCK_SPEED_FAST_MODE, LL_I2C_CLOCK_SPEED_STANDARD_MODE, and LL_I2C_MAX_SPEED_STANDARD.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_Disable ( I2C_TypeDef * I2Cx )

Disable I2C peripheral (PE = 0).

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Disable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 378 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableClockStretching ( I2C_TypeDef * I2Cx )

Disable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_DisableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 491 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_RX ( I2C_TypeDef * I2Cx )

Disable DMA reception requests.

Reference Manual to LL API cross reference:
CR2 DMAEN LL_I2C_DisableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 445 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableDMAReq_TX ( I2C_TypeDef * I2Cx )

Disable DMA transmission requests.

Reference Manual to LL API cross reference:
CR2 DMAEN LL_I2C_DisableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 412 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableGeneralCall ( I2C_TypeDef * I2Cx )

Disable General Call.

Note:
When disabled the Address 0x00 is NACKed.
Reference Manual to LL API cross reference:
CR1 ENGC LL_I2C_DisableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 526 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableOwnAddress2 ( I2C_TypeDef * I2Cx )

Disable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 ENDUAL LL_I2C_DisableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 590 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusAlert ( I2C_TypeDef * I2Cx )

Disable SMBus alert (Host or Device mode)

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is not drived (can be used as a standard GPIO) and Alert Response Address Header acknowledge is disabled. SMBus Host mode:
  • SMBus Alert pin management is not supported.
Reference Manual to LL API cross reference:
CR1 ALERT LL_I2C_DisableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 851 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusPEC ( I2C_TypeDef * I2Cx )

Disable SMBus Packet Error Calculation (PEC).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ENPEC LL_I2C_DisableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 890 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr ( I2C_TypeDef * I2Cx )

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
DR DR LL_I2C_DMA_GetRegAddr
Parameters:
I2Cx I2C Instance.
Return values:
Address of data register

Definition at line 467 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_Enable ( I2C_TypeDef * I2Cx )

Enable I2C peripheral (PE = 1).

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_Enable
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 367 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_EnableClockStretching ( I2C_TypeDef * I2Cx )

Enable Clock stretching.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_EnableClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 479 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_RX ( I2C_TypeDef * I2Cx )

Enable DMA reception requests.

Reference Manual to LL API cross reference:
CR2 DMAEN LL_I2C_EnableDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 434 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableDMAReq_TX ( I2C_TypeDef * I2Cx )

Enable DMA transmission requests.

Reference Manual to LL API cross reference:
CR2 DMAEN LL_I2C_EnableDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 401 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableGeneralCall ( I2C_TypeDef * I2Cx )

Enable General Call.

Note:
When enabled the Address 0x00 is ACKed.
Reference Manual to LL API cross reference:
CR1 ENGC LL_I2C_EnableGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 514 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableOwnAddress2 ( I2C_TypeDef * I2Cx )

Enable acknowledge on Own Address2 match address.

Reference Manual to LL API cross reference:
OAR2 ENDUAL LL_I2C_EnableOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 579 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusAlert ( I2C_TypeDef * I2Cx )

Enable SMBus alert (Host or Device mode)

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
SMBus Device mode:
  • SMBus Alert pin is drived low and Alert Response Address Header acknowledge is enabled. SMBus Host mode:
  • SMBus Alert pin management is supported.
Reference Manual to LL API cross reference:
CR1 ALERT LL_I2C_EnableSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 833 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPEC ( I2C_TypeDef * I2Cx )

Enable SMBus Packet Error Calculation (PEC).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ENPEC LL_I2C_EnableSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 877 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod ( I2C_TypeDef * I2Cx )

Get the SCL high and low period.

Reference Manual to LL API cross reference:
CCR CCR LL_I2C_GetClockPeriod
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.

Definition at line 726 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode ( I2C_TypeDef * I2Cx )

Get the the I2C master speed mode.

Reference Manual to LL API cross reference:
CCR FS LL_I2C_GetClockSpeedMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_CLOCK_SPEED_STANDARD_MODE
  • LL_I2C_CLOCK_SPEED_FAST_MODE

Definition at line 678 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle ( I2C_TypeDef * I2Cx )

Get the Duty cycle (Fast mode only).

Reference Manual to LL API cross reference:
CCR DUTY LL_I2C_GetDutyCycle
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_DUTYCYCLE_2
  • LL_I2C_DUTYCYCLE_16_9

Definition at line 651 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetMode ( I2C_TypeDef * I2Cx )

Get peripheral mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBUS LL_I2C_GetMode
CR1 SMBTYPE LL_I2C_GetMode
CR1 ENARP LL_I2C_GetMode
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP

Definition at line 815 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock ( I2C_TypeDef * I2Cx )

Get the Peripheral clock frequency.

Reference Manual to LL API cross reference:
CR2 FREQ LL_I2C_GetPeriphClock
Parameters:
I2Cx I2C Instance.
Return values:
Value of Peripheral Clock (in Hz)

Definition at line 624 of file stm32f1xx_ll_i2c.h.

References __LL_I2C_FREQ_MHZ_TO_HZ.

__STATIC_INLINE uint32_t LL_I2C_GetRiseTime ( I2C_TypeDef * I2Cx )

Get the SCL, SDA rising time.

Reference Manual to LL API cross reference:
TRISE TRISE LL_I2C_GetRiseTime
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x02 and Max_Data=0x3F

Definition at line 702 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabled ( I2C_TypeDef * I2Cx )

Check if the I2C peripheral is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PE LL_I2C_IsEnabled
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 389 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching ( I2C_TypeDef * I2Cx )

Check if Clock stretching is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 502 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX ( I2C_TypeDef * I2Cx )

Check if DMA reception requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 456 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX ( I2C_TypeDef * I2Cx )

Check if DMA transmission requests are enabled or disabled.

Reference Manual to LL API cross reference:
CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 423 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall ( I2C_TypeDef * I2Cx )

Check if General Call is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 ENGC LL_I2C_IsEnabledGeneralCall
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 537 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2 ( I2C_TypeDef * I2Cx )

Check if Own Address1 acknowledge is enabled or disabled.

Reference Manual to LL API cross reference:
OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 601 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert ( I2C_TypeDef * I2Cx )

Check if SMBus alert (Host or Device mode) is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ALERT LL_I2C_IsEnabledSMBusAlert
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 864 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC ( I2C_TypeDef * I2Cx )

Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 903 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetClockPeriod | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockPeriod
 | ) |  |

Configure the SCL high and low period.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
CCR CCR LL_I2C_SetClockPeriod
Parameters:
I2Cx | I2C Instance.
ClockPeriod | This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
Return values:
None

Definition at line 715 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetClockSpeedMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | ClockSpeedMode
 | ) |  |

Configure the I2C master clock speed mode.

Reference Manual to LL API cross reference:
CCR FS LL_I2C_SetClockSpeedMode
Parameters:
I2Cx I2C Instance.
ClockSpeedMode This parameter can be one of the following values:
  • LL_I2C_CLOCK_SPEED_STANDARD_MODE
  • LL_I2C_CLOCK_SPEED_FAST_MODE
Return values:
None

Definition at line 665 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetDutyCycle | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | DutyCycle
 | ) |  |

Configure the Duty cycle (Fast mode only).

Reference Manual to LL API cross reference:
CCR DUTY LL_I2C_SetDutyCycle
Parameters:
I2Cx I2C Instance.
DutyCycle This parameter can be one of the following values:
  • LL_I2C_DUTYCYCLE_2
  • LL_I2C_DUTYCYCLE_16_9
Return values:
None

Definition at line 638 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetMode | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | PeripheralMode
 | ) |  |

Configure peripheral mode.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 SMBUS LL_I2C_SetMode
CR1 SMBTYPE LL_I2C_SetMode
CR1 ENARP LL_I2C_SetMode
Parameters:
I2Cx I2C Instance.
PeripheralMode This parameter can be one of the following values:
  • LL_I2C_MODE_I2C
  • LL_I2C_MODE_SMBUS_HOST
  • LL_I2C_MODE_SMBUS_DEVICE
  • LL_I2C_MODE_SMBUS_DEVICE_ARP
Return values:
None

Definition at line 796 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress1 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress1,
 |  | uint32_t | OwnAddrSize
 | ) |  |

Set the Own Address1.

Reference Manual to LL API cross reference:
OAR1 ADD0 LL_I2C_SetOwnAddress1
OAR1 ADD1_7 LL_I2C_SetOwnAddress1
OAR1 ADD8_9 LL_I2C_SetOwnAddress1
OAR1 ADDMODE LL_I2C_SetOwnAddress1
Parameters:
I2Cx | I2C Instance.
OwnAddress1 | This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
OwnAddrSize This parameter can be one of the following values:
  • LL_I2C_OWNADDRESS1_7BIT
  • LL_I2C_OWNADDRESS1_10BIT
Return values:
None

Definition at line 555 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_SetOwnAddress2 | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | OwnAddress2
 | ) |  |

Set the 7bits Own Address2.

Note:
This action has no effect if own address2 is enabled.
Reference Manual to LL API cross reference:
OAR2 ADD2 LL_I2C_SetOwnAddress2
Parameters:
I2Cx | I2C Instance.
OwnAddress2 | This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
Return values:
None

Definition at line 568 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_SetPeriphClock | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | PeriphClock
 | ) |  |

Configure the Peripheral clock frequency.

Reference Manual to LL API cross reference:
CR2 FREQ LL_I2C_SetPeriphClock
Parameters:
I2Cx | I2C Instance.
PeriphClock | Peripheral Clock (in Hz)
Return values:
None

Definition at line 613 of file stm32f1xx_ll_i2c.h.

References __LL_I2C_FREQ_HZ_TO_MHZ.

__STATIC_INLINE void LL_I2C_SetRiseTime | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | RiseTime
 | ) |  |

Configure the SCL, SDA rising time.

Note:
This bit can only be programmed when the I2C is disabled (PE = 0).
Reference Manual to LL API cross reference:
TRISE TRISE LL_I2C_SetRiseTime
Parameters:
I2Cx | I2C Instance.
RiseTime | This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
Return values:
None

Definition at line 691 of file stm32f1xx_ll_i2c.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IT_Management

Functions
IT_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_EVT (I2C_TypeDef *I2Cx)
Enable Events interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_EVT (I2C_TypeDef *I2Cx)
Disable Events interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_EVT (I2C_TypeDef *I2Cx)
Check if Events interrupts are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_BUF (I2C_TypeDef *I2Cx)
Enable Buffer interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_BUF (I2C_TypeDef *I2Cx)
Disable Buffer interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_BUF (I2C_TypeDef *I2Cx)
Check if Buffer interrupts are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_I2C_DisableIT_BUF ( I2C_TypeDef * I2Cx )

Disable Buffer interrupts.

Note:
Any of these Buffer events will generate interrupt : Receive buffer not empty (RXNE) Transmit buffer empty (TXE)
Reference Manual to LL API cross reference:
CR2 ITBUFEN LL_I2C_DisableIT_BUF
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1062 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_ERR ( I2C_TypeDef * I2Cx )

Disable Error interrupts.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Bus Error detection (BERR) Arbitration Loss (ARLO) Acknowledge Failure(AF) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (SMBALERT)
Reference Manual to LL API cross reference:
CR2 ITERREN LL_I2C_DisableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1115 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_EVT ( I2C_TypeDef * I2Cx )

Disable Events interrupts.

Note:
Any of these events will generate interrupt : Start Bit (SB) Address sent, Address matched (ADDR) 10-bit header sent (ADD10) Stop detection (STOPF) Byte transfer finished (BTF) Receive buffer not empty (RXNE) Transmit buffer empty (TXE)
Reference Manual to LL API cross reference:
CR2 ITEVTEN LL_I2C_DisableIT_EVT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1023 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_RX ( I2C_TypeDef * I2Cx )

Disable RXNE interrupt.

Reference Manual to LL API cross reference:
CR2 ITEVTEN LL_I2C_DisableIT_RX
CR2 ITBUFEN LL_I2C_DisableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 971 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableIT_TX ( I2C_TypeDef * I2Cx )

Disable TXE interrupt.

Reference Manual to LL API cross reference:
CR2 ITEVTEN LL_I2C_DisableIT_TX
CR2 ITBUFEN LL_I2C_DisableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 935 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_BUF ( I2C_TypeDef * I2Cx )

Enable Buffer interrupts.

Note:
Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function LL_I2C_EnableIT_EVT()) : Receive buffer not empty (RXNE) Transmit buffer empty (TXE)
Reference Manual to LL API cross reference:
CR2 ITBUFEN LL_I2C_EnableIT_BUF
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1048 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_ERR ( I2C_TypeDef * I2Cx )

Enable Error interrupts.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Any of these errors will generate interrupt : Bus Error detection (BERR) Arbitration Loss (ARLO) Acknowledge Failure(AF) Overrun/Underrun (OVR) SMBus Timeout detection (TIMEOUT) SMBus PEC error detection (PECERR) SMBus Alert pin event detection (SMBALERT)
Reference Manual to LL API cross reference:
CR2 ITERREN LL_I2C_EnableIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1094 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_EVT ( I2C_TypeDef * I2Cx )

Enable Events interrupts.

Note:
Any of these events will generate interrupt : Start Bit (SB) Address sent, Address matched (ADDR) 10-bit header sent (ADD10) Stop detection (STOPF) Byte transfer finished (BTF)
Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function LL_I2C_EnableIT_BUF()) : Receive buffer not empty (RXNE) Transmit buffer empty (TXE)
Reference Manual to LL API cross reference:
CR2 ITEVTEN LL_I2C_EnableIT_EVT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1004 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_RX ( I2C_TypeDef * I2Cx )

Enable RXNE interrupt.

Reference Manual to LL API cross reference:
CR2 ITEVTEN LL_I2C_EnableIT_RX
CR2 ITBUFEN LL_I2C_EnableIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 959 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableIT_TX ( I2C_TypeDef * I2Cx )

Enable TXE interrupt.

Reference Manual to LL API cross reference:
CR2 ITEVTEN LL_I2C_EnableIT_TX
CR2 ITBUFEN LL_I2C_EnableIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 923 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF ( I2C_TypeDef * I2Cx )

Check if Buffer interrupts are enabled or disabled.

Reference Manual to LL API cross reference:
CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1073 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR ( I2C_TypeDef * I2Cx )

Check if Error interrupts are enabled or disabled.

Reference Manual to LL API cross reference:
CR2 ITERREN LL_I2C_IsEnabledIT_ERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1126 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT ( I2C_TypeDef * I2Cx )

Check if Events interrupts are enabled or disabled.

Reference Manual to LL API cross reference:
CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1034 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX ( I2C_TypeDef * I2Cx )

Check if the RXNE Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 ITEVTEN LL_I2C_IsEnabledIT_RX
CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 983 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX ( I2C_TypeDef * I2Cx )

Check if the TXE Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 ITEVTEN LL_I2C_IsEnabledIT_TX
CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 947 of file stm32f1xx_ll_i2c.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLAG_management

Functions
FLAG_management
I2C Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BTF (I2C_TypeDef *I2Cx)
Indicate the status of Byte Transfer Finished flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_SB (I2C_TypeDef *I2Cx)
Indicate the status of Start Bit (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADD10 (I2C_TypeDef *I2Cx)
Indicate the status of 10-bit header sent (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_AF (I2C_TypeDef *I2Cx)
Indicate the status of Acknowledge failure flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_DUAL (I2C_TypeDef *I2Cx)
Indicate the status of Dual flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_SMBHOST (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Host address reception (Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_SMBDEFAULT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Device default address reception (Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_GENCALL (I2C_TypeDef *I2Cx)
Indicate the status of General call address reception (Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_MSL (I2C_TypeDef *I2Cx)
Indicate the status of Master/Slave flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_AF (I2C_TypeDef *I2Cx)
Clear Acknowledge failure flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.

Function Documentation

__STATIC_INLINE void LL_I2C_ClearFlag_ADDR ( I2C_TypeDef * I2Cx )

Clear Address Matched flag.

Note:
Clearing this flag is done by a read access to the I2Cx_SR1 register followed by a read access to the I2Cx_SR2 register.
Reference Manual to LL API cross reference:
SR1 ADDR LL_I2C_ClearFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1414 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_AF ( I2C_TypeDef * I2Cx )

Clear Acknowledge failure flag.

Reference Manual to LL API cross reference:
SR1 AF LL_I2C_ClearFlag_AF
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1429 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_ARLO ( I2C_TypeDef * I2Cx )

Clear Arbitration lost flag.

Reference Manual to LL API cross reference:
SR1 ARLO LL_I2C_ClearFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1468 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_BERR ( I2C_TypeDef * I2Cx )

Clear Bus error flag.

Reference Manual to LL API cross reference:
SR1 BERR LL_I2C_ClearFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1457 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_OVR ( I2C_TypeDef * I2Cx )

Clear Overrun/Underrun flag.

Reference Manual to LL API cross reference:
SR1 OVR LL_I2C_ClearFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1479 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearFlag_STOP ( I2C_TypeDef * I2Cx )

Clear Stop detection flag.

Note:
Clearing this flag is done by a read access to the I2Cx_SR1 register followed by a write access to I2Cx_CR1 register.
Reference Manual to LL API cross reference:
SR1 STOPF LL_I2C_ClearFlag_STOP
CR1 PE LL_I2C_ClearFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1443 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Clear SMBus Alert flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1516 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Clear SMBus PEC error flag.

Reference Manual to LL API cross reference:
SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1490 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Clear SMBus Timeout detection flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1503 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10 ( I2C_TypeDef * I2Cx )

Indicate the status of 10-bit header sent (master mode).

Note:
RESET: When no ADD10 event occured. SET: When the master has sent the first address byte (header).
Reference Manual to LL API cross reference:
SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1212 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR ( I2C_TypeDef * I2Cx )

Indicate the status of Address sent (master mode) or Address matched flag (slave mode).

Note:
RESET: Clear default value. SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
Reference Manual to LL API cross reference:
SR1 ADDR LL_I2C_IsActiveFlag_ADDR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1199 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF ( I2C_TypeDef * I2Cx )

Indicate the status of Acknowledge failure flag.

Note:
RESET: No acknowledge failure. SET: When an acknowledge failure is received after a byte transmission.
Reference Manual to LL API cross reference:
SR1 AF LL_I2C_IsActiveFlag_AF
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1225 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO ( I2C_TypeDef * I2Cx )

Indicate the status of Arbitration lost flag.

Note:
RESET: Clear default value. SET: When arbitration lost.
Reference Manual to LL API cross reference:
SR1 ARLO LL_I2C_IsActiveFlag_ARLO
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1264 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR ( I2C_TypeDef * I2Cx )

Indicate the status of Bus error flag.

Note:
RESET: Clear default value. SET: When a misplaced Start or Stop condition is detected.
Reference Manual to LL API cross reference:
SR1 BERR LL_I2C_IsActiveFlag_BERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1251 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF ( I2C_TypeDef * I2Cx )

Indicate the status of Byte Transfer Finished flag.

RESET: When Data byte transfer not done. SET: When Data byte transfer succeeded.

Reference Manual to LL API cross reference:
SR1 BTF LL_I2C_IsActiveFlag_BTF
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1160 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY ( I2C_TypeDef * I2Cx )

Indicate the status of Bus Busy flag.

Note:
RESET: Clear default value. SET: When a Start condition is detected.
Reference Manual to LL API cross reference:
SR2 BUSY LL_I2C_IsActiveFlag_BUSY
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1329 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL ( I2C_TypeDef * I2Cx )

Indicate the status of Dual flag.

Note:
RESET: Received address matched with OAR1. SET: Received address matched with OAR2.
Reference Manual to LL API cross reference:
SR2 DUALF LL_I2C_IsActiveFlag_DUAL
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1342 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL ( I2C_TypeDef * I2Cx )

Indicate the status of General call address reception (Slave mode).

Note:
RESET: No Generall call address SET: General call address received.
This status is cleared by hardware after a STOP condition or repeated START condition.
Reference Manual to LL API cross reference:
SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1388 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL ( I2C_TypeDef * I2Cx )

Indicate the status of Master/Slave flag.

Note:
RESET: Slave Mode. SET: Master Mode.
Reference Manual to LL API cross reference:
SR2 MSL LL_I2C_IsActiveFlag_MSL
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1401 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR ( I2C_TypeDef * I2Cx )

Indicate the status of Overrun/Underrun flag.

Note:
RESET: Clear default value. SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
Reference Manual to LL API cross reference:
SR1 OVR LL_I2C_IsActiveFlag_OVR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1277 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE ( I2C_TypeDef * I2Cx )

Indicate the status of Receive data register not empty flag.

Note:
RESET: When Receive data register is read. SET: When the received data is copied in Receive data register.
Reference Manual to LL API cross reference:
SR1 RXNE LL_I2C_IsActiveFlag_RXNE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1173 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB ( I2C_TypeDef * I2Cx )

Indicate the status of Start Bit (master mode).

Note:
RESET: When No Start condition. SET: When Start condition is generated.
Reference Manual to LL API cross reference:
SR1 SB LL_I2C_IsActiveFlag_SB
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1186 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP ( I2C_TypeDef * I2Cx )

Indicate the status of Stop detection flag (slave mode).

Note:
RESET: Clear default value. SET: When a Stop condition is detected.
Reference Manual to LL API cross reference:
SR1 STOPF LL_I2C_IsActiveFlag_STOP
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1238 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE ( I2C_TypeDef * I2Cx )

Indicate the status of Transmit data register empty flag.

Note:
RESET: When next data is written in Transmit data register. SET: When Transmit data register is empty.
Reference Manual to LL API cross reference:
SR1 TXE LL_I2C_IsActiveFlag_TXE
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1147 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus alert flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1316 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus PEC error flag in reception.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1290 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus Device default address reception (Slave mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: No SMBus Device default address SET: SMBus Device default address received.
This status is cleared by hardware after a STOP condition or repeated START condition.
Reference Manual to LL API cross reference:
SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1374 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus Host address reception (Slave mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
RESET: No SMBus Host address SET: SMBus Host address received.
This status is cleared by hardware after a STOP condition or repeated START condition.
Reference Manual to LL API cross reference:
SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1358 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT ( I2C_TypeDef * I2Cx )

Indicate the status of SMBus Timeout detection flag.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1303 of file stm32f1xx_ll_i2c.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data_Management

Functions
Data_Management
I2C Exported Functions

Functions

__STATIC_INLINE void | LL_I2C_EnableReset (I2C_TypeDef *I2Cx)
Enable Reset of I2C peripheral.
__STATIC_INLINE void | LL_I2C_DisableReset (I2C_TypeDef *I2Cx)
Disable Reset of I2C peripheral.
__STATIC_INLINE uint32_t | LL_I2C_IsResetEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is under reset state or not.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableBitPOS (I2C_TypeDef *I2Cx)
Enable bit POS (master/host mode).
__STATIC_INLINE void | LL_I2C_DisableBitPOS (I2C_TypeDef *I2Cx)
Disable bit POS (master/host mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledBitPOS (I2C_TypeDef *I2Cx)
Check if bit POS is enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction.
__STATIC_INLINE void | LL_I2C_EnableLastDMA (I2C_TypeDef *I2Cx)
Enable DMA last transfer.
__STATIC_INLINE void | LL_I2C_DisableLastDMA (I2C_TypeDef *I2Cx)
Disable DMA last transfer.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledLastDMA (I2C_TypeDef *I2Cx)
Check if DMA last transfer is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE void | LL_I2C_DisableSMBusPECCompare (I2C_TypeDef *I2Cx)
Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .

Function Documentation

__STATIC_INLINE void LL_I2C_AcknowledgeNextData | ( | I2C_TypeDef * | I2Cx,
 |  | uint32_t | TypeAcknowledge
 | ) |  |

Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.

Note:
Usage in Slave or Master mode.
Reference Manual to LL API cross reference:
CR1 ACK LL_I2C_AcknowledgeNextData
Parameters:
I2Cx I2C Instance.
TypeAcknowledge This parameter can be one of the following values:
  • LL_I2C_ACK
  • LL_I2C_NACK
Return values:
None

Definition at line 1572 of file stm32f1xx_ll_i2c.h.

Referenced by LL_I2C_Init().

__STATIC_INLINE void LL_I2C_DisableBitPOS ( I2C_TypeDef * I2Cx )

Disable bit POS (master/host mode).

Note:
In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
Reference Manual to LL API cross reference:
CR1 POS LL_I2C_DisableBitPOS
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1620 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableLastDMA ( I2C_TypeDef * I2Cx )

Disable DMA last transfer.

Note:
This action mean that next DMA EOT is not the last transfer.
Reference Manual to LL API cross reference:
CR2 LAST LL_I2C_DisableLastDMA
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1670 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableReset ( I2C_TypeDef * I2Cx )

Disable Reset of I2C peripheral.

Reference Manual to LL API cross reference:
CR1 SWRST LL_I2C_DisableReset
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1546 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare ( I2C_TypeDef * I2Cx )

Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PEC LL_I2C_DisableSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1709 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableBitPOS ( I2C_TypeDef * I2Cx )

Enable bit POS (master/host mode).

Note:
In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
Reference Manual to LL API cross reference:
CR1 POS LL_I2C_EnableBitPOS
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1608 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableLastDMA ( I2C_TypeDef * I2Cx )

Enable DMA last transfer.

Note:
This action mean that next DMA EOT is the last transfer.
Reference Manual to LL API cross reference:
CR2 LAST LL_I2C_EnableLastDMA
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1658 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableReset ( I2C_TypeDef * I2Cx )

Enable Reset of I2C peripheral.

Reference Manual to LL API cross reference:
CR1 SWRST LL_I2C_EnableReset
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1535 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare ( I2C_TypeDef * I2Cx )

Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
This feature is cleared by hardware when the PEC byte is transferred or compared, or by a START or STOP condition, it is also cleared by software.
Reference Manual to LL API cross reference:
CR1 PEC LL_I2C_EnableSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1696 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStartCondition ( I2C_TypeDef * I2Cx )

Generate a START or RESTART condition.

Note:
The START bit can be set even if bus is BUSY or I2C is in slave mode. This action has no effect when RELOAD is set.
Reference Manual to LL API cross reference:
CR1 START LL_I2C_GenerateStartCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1585 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_GenerateStopCondition ( I2C_TypeDef * I2Cx )

Generate a STOP condition after the current byte transfer (master mode).

Reference Manual to LL API cross reference:
CR1 STOP LL_I2C_GenerateStopCondition
Parameters:
I2Cx I2C Instance.
Return values:
None

Definition at line 1596 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC ( I2C_TypeDef * I2Cx )

Get the SMBus Packet Error byte calculated.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
SR2 PEC LL_I2C_GetSMBusPEC
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1735 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection ( I2C_TypeDef * I2Cx )

Indicate the value of transfer direction.

Note:
RESET: Bus is in read transfer (peripheral point of view). SET: Bus is in write transfer (peripheral point of view).
Reference Manual to LL API cross reference:
SR2 TRA LL_I2C_GetTransferDirection
Parameters:
I2Cx I2C Instance.
Return values:
Returned value can be one of the following values:
  • LL_I2C_DIRECTION_WRITE
  • LL_I2C_DIRECTION_READ

Definition at line 1646 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS ( I2C_TypeDef * I2Cx )

Check if bit POS is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 POS LL_I2C_IsEnabledBitPOS
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1631 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA ( I2C_TypeDef * I2Cx )

Check if DMA last transfer is enabled or disabled.

Reference Manual to LL API cross reference:
CR2 LAST LL_I2C_IsEnabledLastDMA
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1681 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare ( I2C_TypeDef * I2Cx )

Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.

Note:
Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not SMBus feature is supported by the I2Cx Instance.
Reference Manual to LL API cross reference:
CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1722 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled ( I2C_TypeDef * I2Cx )

Check if the I2C peripheral is under reset state or not.

Reference Manual to LL API cross reference:
CR1 SWRST LL_I2C_IsResetEnabled
Parameters:
I2Cx I2C Instance.
Return values:
State of bit (1 or 0).

Definition at line 1557 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE uint8_t LL_I2C_ReceiveData8 ( I2C_TypeDef * I2Cx )

Read Receive Data register.

Reference Manual to LL API cross reference:
DR DR LL_I2C_ReceiveData8
Parameters:
I2Cx I2C Instance.
Return values:
Value between Min_Data=0x0 and Max_Data=0xFF

Definition at line 1746 of file stm32f1xx_ll_i2c.h.

__STATIC_INLINE void LL_I2C_TransmitData8 | ( | I2C_TypeDef * | I2Cx,
 |  | uint8_t | Data
 | ) |  |

Write in Transmit Data Register .

Reference Manual to LL API cross reference:
DR DR LL_I2C_TransmitData8
Parameters:
I2Cx | I2C Instance.
Data | Value between Min_Data=0x0 and Max_Data=0xFF
Return values:
None

Definition at line 1758 of file stm32f1xx_ll_i2c.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Functions

uint32_t | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
uint32_t | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Function Documentation

uint32_t LL_I2C_DeInit ( I2C_TypeDef * I2Cx )

De-initialize the I2C registers to their default reset values.

Parameters:
I2Cx I2C Instance.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are de-initialized
  • ERROR: I2C registers are not de-initialized

Definition at line 106 of file stm32f1xx_ll_i2c.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_I2C1, LL_APB1_GRP1_PERIPH_I2C2, and LL_APB1_GRP1_ReleaseReset().

uint32_t LL_I2C_Init | ( | I2C_TypeDef * | I2Cx,
 |  | LL_I2C_InitTypeDef * | I2C_InitStruct
 | ) |  |

Initialize the I2C registers according to the specified parameters in I2C_InitStruct.

Parameters:
I2Cx | I2C Instance.
I2C_InitStruct | pointer to a LL_I2C_InitTypeDef structure.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: I2C registers are initialized
  • ERROR: Not applicable

Definition at line 146 of file stm32f1xx_ll_i2c.c.

References assert_param, LL_I2C_InitTypeDef::ClockSpeed, LL_I2C_InitTypeDef::DutyCycle, IS_I2C_CLOCK_SPEED, IS_I2C_DUTY_CYCLE, IS_LL_I2C_OWN_ADDRESS1, IS_LL_I2C_OWN_ADDRSIZE, IS_LL_I2C_PERIPHERAL_MODE, IS_LL_I2C_TYPE_ACKNOWLEDGE, LL_I2C_AcknowledgeNextData(), LL_I2C_ConfigSpeed(), LL_I2C_Disable(), LL_I2C_Enable(), LL_I2C_SetMode(), LL_I2C_SetOwnAddress1(), LL_RCC_GetSystemClocksFreq(), LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_RCC_ClocksTypeDef::PCLK1_Frequency, LL_I2C_InitTypeDef::PeripheralMode, and LL_I2C_InitTypeDef::TypeAcknowledge.

void LL_I2C_StructInit ( LL_I2C_InitTypeDef * I2C_InitStruct )

Set each LL_I2C_InitTypeDef field to default value.

Parameters:
I2C_InitStruct Pointer to a LL_I2C_InitTypeDef structure.
Return values:
None

Definition at line 206 of file stm32f1xx_ll_i2c.c.

References LL_I2C_InitTypeDef::ClockSpeed, LL_I2C_InitTypeDef::DutyCycle, LL_I2C_DUTYCYCLE_2, LL_I2C_MODE_I2C, LL_I2C_NACK, LL_I2C_OWNADDRESS1_7BIT, LL_I2C_InitTypeDef::OwnAddress1, LL_I2C_InitTypeDef::OwnAddrSize, LL_I2C_InitTypeDef::PeripheralMode, and LL_I2C_InitTypeDef::TypeAcknowledge.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2S

Modules
I2S
STM32F1xx_LL_Driver

Modules

I2S Private Constants
I2S Private Macros
I2S Exported Init structure
I2S Exported Constants
I2S Exported Macros
I2S Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for I2S registers.

Register | Bit | Function
CR2 | ERRIE | LL_I2S_DisableIT_ERR
 |  | LL_I2S_EnableIT_ERR
 |  | LL_I2S_IsEnabledIT_ERR
 | RXDMAEN | LL_I2S_DisableDMAReq_RX
 |  | LL_I2S_EnableDMAReq_RX
 |  | LL_I2S_IsEnabledDMAReq_RX
 | RXNEIE | LL_I2S_DisableIT_RXNE
 |  | LL_I2S_EnableIT_RXNE
 |  | LL_I2S_IsEnabledIT_RXNE
 | TXDMAEN | LL_I2S_DisableDMAReq_TX
 |  | LL_I2S_EnableDMAReq_TX
 |  | LL_I2S_IsEnabledDMAReq_TX
 | TXEIE | LL_I2S_DisableIT_TXE
 |  | LL_I2S_EnableIT_TXE
 |  | LL_I2S_IsEnabledIT_TXE
DR | DR | LL_I2S_ReceiveData16
 |  | LL_I2S_TransmitData16
I2SCFGR | CHLEN | LL_I2S_GetDataFormat
 |  | LL_I2S_SetDataFormat
 | CKPOL | LL_I2S_GetClockPolarity
 |  | LL_I2S_SetClockPolarity
 | DATLEN | LL_I2S_GetDataFormat
 |  | LL_I2S_SetDataFormat
 | I2SCFG | LL_I2S_GetTransferMode
 |  | LL_I2S_SetTransferMode
 | I2SE | LL_I2S_Disable
 |  | LL_I2S_Enable
 |  | LL_I2S_IsEnabled
 | I2SMOD | LL_I2S_Enable
 | I2SSTD | LL_I2S_GetStandard
 |  | LL_I2S_SetStandard
 | PCMSYNC | LL_I2S_GetStandard
 |  | LL_I2S_SetStandard
I2SPR | I2SDIV | LL_I2S_GetPrescalerLinear
 |  | LL_I2S_SetPrescalerLinear
 | MCKOE | LL_I2S_DisableMasterClock
 |  | LL_I2S_EnableMasterClock
 |  | LL_I2S_IsEnabledMasterClock
 | ODD | LL_I2S_GetPrescalerParity
 |  | LL_I2S_SetPrescalerParity
SR | BSY | LL_I2S_IsActiveFlag_BSY
 | CHSIDE | LL_I2S_IsActiveFlag_CHSIDE
 | FRE | LL_I2S_ClearFlag_FRE
 |  | LL_I2S_IsActiveFlag_FRE
 | OVR | LL_I2S_ClearFlag_OVR
 |  | LL_I2S_IsActiveFlag_OVR
 | RXNE | LL_I2S_IsActiveFlag_RXNE
 | TXE | LL_I2S_IsActiveFlag_TXE
 | UDR | LL_I2S_ClearFlag_UDR
 |  | LL_I2S_IsActiveFlag_UDR
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2S Private Constants

Defines
I2S Private Constants
I2S

Defines

#define | I2S_I2SCFGR_CLEAR_MASK
#define | I2S_I2SPR_CLEAR_MASK 0x0002U

Define Documentation

#define I2S_I2SCFGR_CLEAR_MASK
Value:
(SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
                                            SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
                                            SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )

Definition at line 65 of file stm32f1xx_ll_i2s.c.

Referenced by LL_I2S_Init().

#define I2S_I2SPR_CLEAR_MASK 0x0002U

Definition at line 69 of file stm32f1xx_ll_i2s.c.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2S Private Macros

Defines
I2S Private Macros
I2S

Defines

#define | IS_LL_I2S_DATAFORMAT(__VALUE__)
#define | IS_LL_I2S_CPOL(__VALUE__)
#define | IS_LL_I2S_STANDARD(__VALUE__)
#define | IS_LL_I2S_MODE(__VALUE__)
#define | IS_LL_I2S_MCLK_OUTPUT(__VALUE__)
#define | IS_LL_I2S_AUDIO_FREQ(__VALUE__)
#define | IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define | IS_LL_I2S_PRESCALER_PARITY(__VALUE__)

Define Documentation

#define IS_LL_I2S_AUDIO_FREQ ( __VALUE__ )
Value:
((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)    \
                                       && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
                                       || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))

Definition at line 100 of file stm32f1xx_ll_i2s.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_CPOL ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_POLARITY_LOW)  \
                                       || ((__VALUE__) == LL_I2S_POLARITY_HIGH))

Definition at line 83 of file stm32f1xx_ll_i2s.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_DATAFORMAT ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_DATAFORMAT_16B)          \
                                       || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
                                       || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
                                       || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))

Definition at line 78 of file stm32f1xx_ll_i2s.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_MCLK_OUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
                                       || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))

Definition at line 97 of file stm32f1xx_ll_i2s.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_MODE_SLAVE_TX)  \
                                       || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
                                       || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
                                       || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))

Definition at line 92 of file stm32f1xx_ll_i2s.c.

Referenced by LL_I2S_Init().

#define IS_LL_I2S_PRESCALER_LINEAR ( __VALUE__ ) ((__VALUE__) >= 0x2U)

Definition at line 104 of file stm32f1xx_ll_i2s.c.

Referenced by LL_I2S_ConfigPrescaler().

#define IS_LL_I2S_PRESCALER_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
                                           || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))

Definition at line 106 of file stm32f1xx_ll_i2s.c.

Referenced by LL_I2S_ConfigPrescaler().

#define IS_LL_I2S_STANDARD ( __VALUE__ )
Value:
(((__VALUE__) == LL_I2S_STANDARD_PHILIPS)   \
                                       || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
                                       || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
                                       || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
                                       || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))

Definition at line 86 of file stm32f1xx_ll_i2s.c.

Referenced by LL_I2S_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_I2S_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_I2S_InitTypeDef Struct Reference
I2S Exported Init structure

I2S Init structure definition. More...

#include <stm32f1xx_ll_i2s.h>

Data Fields

uint32_t | Mode
uint32_t | Standard
uint32_t | DataFormat
uint32_t | MCLKOutput
uint32_t | AudioFreq
uint32_t | ClockPolarity

Detailed Description

I2S Init structure definition.

Definition at line 71 of file stm32f1xx_ll_i2s.h.

Field Documentation

uint32_t LL_I2S_InitTypeDef::AudioFreq

Specifies the frequency selected for the I2S communication. This parameter can be a value of Audio Frequency

Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity and unitary functions LL_I2S_SetPrescalerLinear() and LL_I2S_SetPrescalerParity() to set it.

Definition at line 96 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::ClockPolarity

Specifies the idle state of the I2S clock. This parameter can be a value of Clock Polarity

This feature can be modified afterwards using unitary function LL_I2S_SetClockPolarity().

Definition at line 103 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::DataFormat

Specifies the data format for the I2S communication. This parameter can be a value of Data format

This feature can be modified afterwards using unitary function LL_I2S_SetDataFormat().

Definition at line 84 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::MCLKOutput

Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of MCLK Output

This feature can be modified afterwards using unitary functions LL_I2S_EnableMasterClock() or LL_I2S_DisableMasterClock.

Definition at line 90 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::Mode

Specifies the I2S operating mode. This parameter can be a value of Operation Mode

This feature can be modified afterwards using unitary function LL_I2S_SetTransferMode().

Definition at line 73 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

uint32_t LL_I2S_InitTypeDef::Standard

Specifies the standard used for the I2S communication. This parameter can be a value of I2s Standard

This feature can be modified afterwards using unitary function LL_I2S_SetStandard().

Definition at line 78 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_i2s.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
I2S Exported Constants

Flags defines which can be used with LL_I2S_ReadReg function. More...

Defines

#define | LL_I2S_SR_RXNE LL_SPI_SR_RXNE
#define | LL_I2S_SR_TXE LL_SPI_SR_TXE
#define | LL_I2S_SR_BSY LL_SPI_SR_BSY
#define | LL_I2S_SR_UDR SPI_SR_UDR
#define | LL_I2S_SR_OVR LL_SPI_SR_OVR
#define | LL_I2S_SR_FRE LL_SPI_SR_FRE

Detailed Description

Flags defines which can be used with LL_I2S_ReadReg function.

Define Documentation

#define LL_I2S_SR_BSY LL_SPI_SR_BSY

Busy flag

Definition at line 126 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_SR_FRE LL_SPI_SR_FRE

TI mode frame format error flag

Definition at line 129 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_SR_OVR LL_SPI_SR_OVR

Overrun flag

Definition at line 128 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE

Rx buffer not empty flag

Definition at line 124 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_SR_TXE LL_SPI_SR_TXE

Tx buffer empty flag

Definition at line 125 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_SR_UDR SPI_SR_UDR

Underrun flag

Definition at line 127 of file stm32f1xx_ll_i2s.h.

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STM32F103xB HAL User Manual: IT Defines

Defines
IT Defines
I2S Exported Constants | SPI Exported Constants

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions. More...

Defines

#define | LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE
#define | LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE
#define | LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE
#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE

Detailed Description

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Define Documentation

#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE

Error interrupt enable

Definition at line 140 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE

Rx buffer not empty interrupt enable

Definition at line 138 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE

Tx buffer empty interrupt enable

Definition at line 139 of file stm32f1xx_ll_i2s.h.

#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE

Error interrupt enable

Definition at line 158 of file stm32f1xx_ll_spi.h.

#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE

Rx buffer not empty interrupt enable

Definition at line 156 of file stm32f1xx_ll_spi.h.

#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE

Tx buffer empty interrupt enable

Definition at line 157 of file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data format

Defines
Data format
I2S Exported Constants

Defines

#define | LL_I2S_DATAFORMAT_16B 0x00000000U
#define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
#define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

Define Documentation

#define LL_I2S_DATAFORMAT_16B 0x00000000U

Data length 16 bits, Channel lenght 16bit

Definition at line 148 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)

Data length 16 bits, Channel lenght 32bit

Definition at line 149 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)

Data length 24 bits, Channel lenght 32bit

Definition at line 150 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

Data length 16 bits, Channel lenght 32bit

Definition at line 151 of file stm32f1xx_ll_i2s.h.

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STM32F103xB HAL User Manual: Clock Polarity

Defines
Clock Polarity
I2S Exported Constants

Defines

#define | LL_I2S_POLARITY_LOW 0x00000000U
#define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)

Define Documentation

#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)

Clock steady state is high level

Definition at line 160 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_POLARITY_LOW 0x00000000U

Clock steady state is low level

Definition at line 159 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2s Standard

Defines
I2s Standard
I2S Exported Constants

Defines

#define | LL_I2S_STANDARD_PHILIPS 0x00000000U
#define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

Define Documentation

#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)

LSB justified standard (right justified)

Definition at line 170 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)

MSB justified standard (left justified)

Definition at line 169 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

PCM standard, long frame synchronization

Definition at line 172 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)

PCM standard, short frame synchronization

Definition at line 171 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_STANDARD_PHILIPS 0x00000000U

I2S standard philips

Definition at line 168 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_StructInit().

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STM32F103xB HAL User Manual: Operation Mode

Defines
Operation Mode
I2S Exported Constants

Defines

#define | LL_I2S_MODE_SLAVE_TX 0x00000000U
#define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)

Define Documentation

#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)

Master Rx configuration

Definition at line 183 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)

Master Tx configuration

Definition at line 182 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)

Slave Rx configuration

Definition at line 181 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_MODE_SLAVE_TX 0x00000000U

Slave Tx configuration

Definition at line 180 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_StructInit().

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STM32F103xB HAL User Manual: Prescaler Factor

Defines
Prescaler Factor
I2S Exported Constants

Defines

#define | LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U
#define | LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)

Define Documentation

#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U

Odd factor: Real divider value is = I2SDIV * 2

Definition at line 191 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)

Odd factor: Real divider value is = (I2SDIV * 2)+1

Definition at line 192 of file stm32f1xx_ll_i2s.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: MCLK Output

Defines
MCLK Output
I2S Exported Constants

Defines

#define | LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U
#define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)

Define Documentation

#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U

Master clock output is disabled

Definition at line 202 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_StructInit().

#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)

Master clock output is enabled

Definition at line 203 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Audio Frequency

Defines
Audio Frequency
I2S Exported Constants

Defines

#define | LL_I2S_AUDIOFREQ_192K 192000U
#define | LL_I2S_AUDIOFREQ_96K 96000U
#define | LL_I2S_AUDIOFREQ_48K 48000U
#define | LL_I2S_AUDIOFREQ_44K 44100U
#define | LL_I2S_AUDIOFREQ_32K 32000U
#define | LL_I2S_AUDIOFREQ_22K 22050U
#define | LL_I2S_AUDIOFREQ_16K 16000U
#define | LL_I2S_AUDIOFREQ_11K 11025U
#define | LL_I2S_AUDIOFREQ_8K 8000U
#define | LL_I2S_AUDIOFREQ_DEFAULT 2U

Define Documentation

#define LL_I2S_AUDIOFREQ_11K 11025U

Audio Frequency configuration 11025 Hz

Definition at line 219 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_AUDIOFREQ_16K 16000U

Audio Frequency configuration 16000 Hz

Definition at line 218 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_AUDIOFREQ_192K 192000U

Audio Frequency configuration 192000 Hz

Definition at line 212 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_AUDIOFREQ_22K 22050U

Audio Frequency configuration 22050 Hz

Definition at line 217 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_AUDIOFREQ_32K 32000U

Audio Frequency configuration 32000 Hz

Definition at line 216 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_AUDIOFREQ_44K 44100U

Audio Frequency configuration 44100 Hz

Definition at line 215 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_AUDIOFREQ_48K 48000U

Audio Frequency configuration 48000 Hz

Definition at line 214 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_AUDIOFREQ_8K 8000U

Audio Frequency configuration 8000 Hz

Definition at line 220 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_AUDIOFREQ_96K 96000U

Audio Frequency configuration 96000 Hz

Definition at line 213 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_AUDIOFREQ_DEFAULT 2U

Audio Freq not specified. Register I2SDIV = 2

Definition at line 221 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_Init(), and LL_I2S_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
I2S Exported Macros

Defines

#define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2S register.
#define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2S register.

Define Documentation

#define LL_I2S_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in I2S register.

Parameters:
__INSTANCE__ | I2S Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 255 of file stm32f1xx_ll_i2s.h.

#define LL_I2S_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in I2S register.

Parameters:
__INSTANCE__ | I2S Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 247 of file stm32f1xx_ll_i2s.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration

Functions
Configuration
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx)
Select I2S mode and Enable I2S peripheral.
__STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx)
Disable I2S peripheral.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabled (SPI_TypeDef *SPIx)
Check if I2S peripheral is enabled.
__STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataFormat)
Set I2S data frame length.
__STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx)
Get I2S data frame length.
__STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set I2S clock polarity.
__STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx)
Get I2S clock polarity.
__STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S standard protocol.
__STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx)
Get I2S standard protocol.
__STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set I2S transfer mode.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx)
Get I2S transfer mode.
__STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
Set I2S linear prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx)
Get I2S linear prescaler.
__STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity)
Set I2S parity prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx)
Get I2S parity prescaler.
__STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx)
Enable the master clock ouput (Pin MCK)
__STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx)
Disable the master clock ouput (Pin MCK)
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx)
Check if the master clock ouput (Pin MCK) is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_Disable ( SPI_TypeDef * SPIx )

Disable I2S peripheral.

Reference Manual to LL API cross reference:
I2SCFGR I2SE LL_I2S_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 293 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE void LL_I2S_DisableMasterClock ( SPI_TypeDef * SPIx )

Disable the master clock ouput (Pin MCK)

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_DisableMasterClock
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 502 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE void LL_I2S_Enable ( SPI_TypeDef * SPIx )

Select I2S mode and Enable I2S peripheral.

Reference Manual to LL API cross reference:
I2SCFGR I2SMOD LL_I2S_Enable
I2SCFGR I2SE LL_I2S_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 282 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE void LL_I2S_EnableMasterClock ( SPI_TypeDef * SPIx )

Enable the master clock ouput (Pin MCK)

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_EnableMasterClock
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 491 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity ( SPI_TypeDef * SPIx )

Get I2S clock polarity.

Reference Manual to LL API cross reference:
I2SCFGR CKPOL LL_I2S_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_POLARITY_LOW
  • LL_I2S_POLARITY_HIGH

Definition at line 364 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE uint32_t LL_I2S_GetDataFormat ( SPI_TypeDef * SPIx )

Get I2S data frame length.

Reference Manual to LL API cross reference:
I2SCFGR DATLEN LL_I2S_GetDataFormat
I2SCFGR CHLEN LL_I2S_GetDataFormat
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_DATAFORMAT_16B
  • LL_I2S_DATAFORMAT_16B_EXTENDED
  • LL_I2S_DATAFORMAT_24B
  • LL_I2S_DATAFORMAT_32B

Definition at line 337 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear ( SPI_TypeDef * SPIx )

Get I2S linear prescaler.

Reference Manual to LL API cross reference:
I2SPR I2SDIV LL_I2S_GetPrescalerLinear
Parameters:
SPIx SPI Instance
Return values:
PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF

Definition at line 453 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity ( SPI_TypeDef * SPIx )

Get I2S parity prescaler.

Reference Manual to LL API cross reference:
I2SPR ODD LL_I2S_GetPrescalerParity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD

Definition at line 480 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE uint32_t LL_I2S_GetStandard ( SPI_TypeDef * SPIx )

Get I2S standard protocol.

Reference Manual to LL API cross reference:
I2SCFGR I2SSTD LL_I2S_GetStandard
I2SCFGR PCMSYNC LL_I2S_GetStandard
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_STANDARD_PHILIPS
  • LL_I2S_STANDARD_MSB
  • LL_I2S_STANDARD_LSB
  • LL_I2S_STANDARD_PCM_SHORT
  • LL_I2S_STANDARD_PCM_LONG

Definition at line 399 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE uint32_t LL_I2S_GetTransferMode ( SPI_TypeDef * SPIx )

Get I2S transfer mode.

Reference Manual to LL API cross reference:
I2SCFGR I2SCFG LL_I2S_GetTransferMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_I2S_MODE_SLAVE_TX
  • LL_I2S_MODE_SLAVE_RX
  • LL_I2S_MODE_MASTER_TX
  • LL_I2S_MODE_MASTER_RX

Definition at line 430 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE uint32_t LL_I2S_IsEnabled ( SPI_TypeDef * SPIx )

Check if I2S peripheral is enabled.

Reference Manual to LL API cross reference:
I2SCFGR I2SE LL_I2S_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 304 of file stm32f1xx_ll_i2s.h.

Referenced by LL_I2S_Init().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock ( SPI_TypeDef * SPIx )

Check if the master clock ouput (Pin MCK) is enabled.

Reference Manual to LL API cross reference:
I2SPR MCKOE LL_I2S_IsEnabledMasterClock
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 513 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE void LL_I2S_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set I2S clock polarity.

Reference Manual to LL API cross reference:
I2SCFGR CKPOL LL_I2S_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_I2S_POLARITY_LOW
  • LL_I2S_POLARITY_HIGH
Return values:
None

Definition at line 351 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE void LL_I2S_SetDataFormat | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataFormat
 | ) |  |

Set I2S data frame length.

Reference Manual to LL API cross reference:
I2SCFGR DATLEN LL_I2S_SetDataFormat
I2SCFGR CHLEN LL_I2S_SetDataFormat
Parameters:
SPIx SPI Instance
DataFormat This parameter can be one of the following values:
  • LL_I2S_DATAFORMAT_16B
  • LL_I2S_DATAFORMAT_16B_EXTENDED
  • LL_I2S_DATAFORMAT_24B
  • LL_I2S_DATAFORMAT_32B
Return values:
None

Definition at line 321 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE void LL_I2S_SetPrescalerLinear | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | PrescalerLinear
 | ) |  |

Set I2S linear prescaler.

Reference Manual to LL API cross reference:
I2SPR I2SDIV LL_I2S_SetPrescalerLinear
Parameters:
SPIx | SPI Instance
PrescalerLinear | Value between Min_Data=0x02 and Max_Data=0xFF
Return values:
None

Definition at line 442 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE void LL_I2S_SetPrescalerParity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set I2S parity prescaler.

Reference Manual to LL API cross reference:
I2SPR ODD LL_I2S_SetPrescalerParity
Parameters:
SPIx SPI Instance
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 467 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE void LL_I2S_SetStandard | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Standard
 | ) |  |

Set I2S standard protocol.

Reference Manual to LL API cross reference:
I2SCFGR I2SSTD LL_I2S_SetStandard
I2SCFGR PCMSYNC LL_I2S_SetStandard
Parameters:
SPIx SPI Instance
Standard This parameter can be one of the following values:
  • LL_I2S_STANDARD_PHILIPS
  • LL_I2S_STANDARD_MSB
  • LL_I2S_STANDARD_LSB
  • LL_I2S_STANDARD_PCM_SHORT
  • LL_I2S_STANDARD_PCM_LONG
Return values:
None

Definition at line 382 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE void LL_I2S_SetTransferMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set I2S transfer mode.

Reference Manual to LL API cross reference:
I2SCFGR I2SCFG LL_I2S_SetTransferMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_I2S_MODE_SLAVE_TX
  • LL_I2S_MODE_SLAVE_RX
  • LL_I2S_MODE_MASTER_TX
  • LL_I2S_MODE_MASTER_RX
Return values:
None

Definition at line 415 of file stm32f1xx_ll_i2s.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLAG Management

Functions
FLAG Management
I2S Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get underrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_CHSIDE (SPI_TypeDef *SPIx)
Get channel side flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear underrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.

Function Documentation

__STATIC_INLINE void LL_I2S_ClearFlag_FRE ( SPI_TypeDef * SPIx )

Clear frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_I2S_ClearFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 636 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE void LL_I2S_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_I2S_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 612 of file stm32f1xx_ll_i2s.h.

References LL_SPI_ClearFlag_OVR().

__STATIC_INLINE void LL_I2S_ClearFlag_UDR ( SPI_TypeDef * SPIx )

Clear underrun error flag.

Reference Manual to LL API cross reference:
SR UDR LL_I2S_ClearFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 623 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY ( SPI_TypeDef * SPIx )

Get busy flag.

Reference Manual to LL API cross reference:
SR BSY LL_I2S_IsActiveFlag_BSY
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 554 of file stm32f1xx_ll_i2s.h.

References LL_SPI_IsActiveFlag_BSY().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE ( SPI_TypeDef * SPIx )

Get channel side flag.

Note:
0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
It has no significance in PCM mode.
Reference Manual to LL API cross reference:
SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 601 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE ( SPI_TypeDef * SPIx )

Get frame format error flag.

Reference Manual to LL API cross reference:
SR FRE LL_I2S_IsActiveFlag_FRE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 587 of file stm32f1xx_ll_i2s.h.

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_I2S_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 565 of file stm32f1xx_ll_i2s.h.

References LL_SPI_IsActiveFlag_OVR().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer is not empty.

Reference Manual to LL API cross reference:
SR RXNE LL_I2S_IsActiveFlag_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 532 of file stm32f1xx_ll_i2s.h.

References LL_SPI_IsActiveFlag_RXNE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer is empty.

Reference Manual to LL API cross reference:
SR TXE LL_I2S_IsActiveFlag_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 543 of file stm32f1xx_ll_i2s.h.

References LL_SPI_IsActiveFlag_TXE().

__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR ( SPI_TypeDef * SPIx )

Get underrun error flag.

Reference Manual to LL API cross reference:
SR UDR LL_I2S_IsActiveFlag_UDR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 576 of file stm32f1xx_ll_i2s.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Interrupt Management

Functions
Interrupt Management
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error IT.
__STATIC_INLINE void | LL_I2S_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error IT.
__STATIC_INLINE void | LL_I2S_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty IT.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if ERR IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if RXNE IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if TXE IT is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_DisableIT_ERR ( SPI_TypeDef * SPIx )

Disable error IT.

Note:
This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_DisableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 690 of file stm32f1xx_ll_i2s.h.

References LL_SPI_DisableIT_ERR().

__STATIC_INLINE void LL_I2S_DisableIT_RXNE ( SPI_TypeDef * SPIx )

Disable Rx buffer not empty IT.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_DisableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 701 of file stm32f1xx_ll_i2s.h.

References LL_SPI_DisableIT_RXNE().

__STATIC_INLINE void LL_I2S_DisableIT_TXE ( SPI_TypeDef * SPIx )

Disable Tx buffer empty IT.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_DisableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 712 of file stm32f1xx_ll_i2s.h.

References LL_SPI_DisableIT_TXE().

__STATIC_INLINE void LL_I2S_EnableIT_ERR ( SPI_TypeDef * SPIx )

Enable error IT.

Note:
This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_EnableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 656 of file stm32f1xx_ll_i2s.h.

References LL_SPI_EnableIT_ERR().

__STATIC_INLINE void LL_I2S_EnableIT_RXNE ( SPI_TypeDef * SPIx )

Enable Rx buffer not empty IT.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_EnableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 667 of file stm32f1xx_ll_i2s.h.

References LL_SPI_EnableIT_RXNE().

__STATIC_INLINE void LL_I2S_EnableIT_TXE ( SPI_TypeDef * SPIx )

Enable Tx buffer empty IT.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_EnableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 678 of file stm32f1xx_ll_i2s.h.

References LL_SPI_EnableIT_TXE().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR ( SPI_TypeDef * SPIx )

Check if ERR IT is enabled.

Reference Manual to LL API cross reference:
CR2 ERRIE LL_I2S_IsEnabledIT_ERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 723 of file stm32f1xx_ll_i2s.h.

References LL_SPI_IsEnabledIT_ERR().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE ( SPI_TypeDef * SPIx )

Check if RXNE IT is enabled.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 734 of file stm32f1xx_ll_i2s.h.

References LL_SPI_IsEnabledIT_RXNE().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE ( SPI_TypeDef * SPIx )

Check if TXE IT is enabled.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_I2S_IsEnabledIT_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 745 of file stm32f1xx_ll_i2s.h.

References LL_SPI_IsEnabledIT_TXE().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Management

Functions
DMA Management
I2S Exported Functions

Functions

__STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.

Function Documentation

__STATIC_INLINE void LL_I2S_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 775 of file stm32f1xx_ll_i2s.h.

References LL_SPI_DisableDMAReq_RX().

__STATIC_INLINE void LL_I2S_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 808 of file stm32f1xx_ll_i2s.h.

References LL_SPI_DisableDMAReq_TX().

__STATIC_INLINE void LL_I2S_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 764 of file stm32f1xx_ll_i2s.h.

References LL_SPI_EnableDMAReq_RX().

__STATIC_INLINE void LL_I2S_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 797 of file stm32f1xx_ll_i2s.h.

References LL_SPI_EnableDMAReq_TX().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 786 of file stm32f1xx_ll_i2s.h.

References LL_SPI_IsEnabledDMAReq_RX().

__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 819 of file stm32f1xx_ll_i2s.h.

References LL_SPI_IsEnabledDMAReq_TX().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DATA Management

Functions
DATA Management
I2S Exported Functions

Functions

__STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in data register.
__STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in data register.

Function Documentation

__STATIC_INLINE uint16_t LL_I2S_ReceiveData16 ( SPI_TypeDef * SPIx )

Read 16-Bits in data register.

Reference Manual to LL API cross reference:
DR DR LL_I2S_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF

Definition at line 838 of file stm32f1xx_ll_i2s.h.

References LL_SPI_ReceiveData16().

__STATIC_INLINE void LL_I2S_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write 16-Bits in data register.

Reference Manual to LL API cross reference:
DR DR LL_I2S_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x0000 and Max_Data=0xFFFF
Return values:
None

Definition at line 850 of file stm32f1xx_ll_i2s.h.

References LL_SPI_TransmitData16().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2S Exported Functions

Functions

ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Function Documentation

void LL_I2S_ConfigPrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | PrescalerLinear,
 |  | uint32_t | PrescalerParity
 | ) |  |

Set linear and parity prescaler.

Note:
To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)
Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
Parameters:
SPIx | SPI Instance
PrescalerLinear | value: Min_Data=0x02 and Max_Data=0xFF.
PrescalerParity This parameter can be one of the following values:
  • LL_I2S_PRESCALER_PARITY_EVEN
  • LL_I2S_PRESCALER_PARITY_ODD
Return values:
None

Definition at line 272 of file stm32f1xx_ll_i2s.c.

References assert_param, IS_LL_I2S_PRESCALER_LINEAR, and IS_LL_I2S_PRESCALER_PARITY.

ErrorStatus LL_I2S_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI/I2S registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 130 of file stm32f1xx_ll_i2s.c.

References LL_SPI_DeInit().

ErrorStatus LL_I2S_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_I2S_InitTypeDef * | I2S_InitStruct
 | ) |  |

Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
I2S_InitStruct | pointer to a LL_I2S_InitTypeDef structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are Initialized
  • ERROR: SPI registers are not Initialized

Definition at line 145 of file stm32f1xx_ll_i2s.c.

References assert_param, LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, I2S_I2SCFGR_CLEAR_MASK, IS_LL_I2S_AUDIO_FREQ, IS_LL_I2S_CPOL, IS_LL_I2S_DATAFORMAT, IS_LL_I2S_MCLK_OUTPUT, IS_LL_I2S_MODE, IS_LL_I2S_STANDARD, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_IsEnabled(), LL_I2S_MCLK_OUTPUT_ENABLE, LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, and LL_I2S_InitTypeDef::Standard.

void LL_I2S_StructInit ( LL_I2S_InitTypeDef * I2S_InitStruct )

Set each LL_I2S_InitTypeDef field to default value.

Parameters:
I2S_InitStruct pointer to a LL_I2S_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 250 of file stm32f1xx_ll_i2s.c.

References LL_I2S_InitTypeDef::AudioFreq, LL_I2S_InitTypeDef::ClockPolarity, LL_I2S_InitTypeDef::DataFormat, LL_I2S_AUDIOFREQ_DEFAULT, LL_I2S_DATAFORMAT_16B, LL_I2S_MCLK_OUTPUT_DISABLE, LL_I2S_MODE_SLAVE_TX, LL_I2S_POLARITY_LOW, LL_I2S_STANDARD_PHILIPS, LL_I2S_InitTypeDef::MCLKOutput, LL_I2S_InitTypeDef::Mode, and LL_I2S_InitTypeDef::Standard.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG

Modules
IWDG
STM32F1xx_LL_Driver

Modules

IWDG Private Constants
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for IWDG registers.

Register | Bit | Function
KR | KEY | LL_IWDG_DisableWriteAccess
 |  | LL_IWDG_Enable
 |  | LL_IWDG_EnableWriteAccess
 |  | LL_IWDG_ReloadCounter
PR | PR | LL_IWDG_GetPrescaler
 |  | LL_IWDG_SetPrescaler
RLR | RL | LL_IWDG_GetReloadCounter
 |  | LL_IWDG_SetReloadCounter
SR | PVU | LL_IWDG_IsActiveFlag_PVU
 |  | LL_IWDG_IsReady
 | RVU | LL_IWDG_IsActiveFlag_RVU
 |  | LL_IWDG_IsReady
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

Define Documentation

#define LL_IWDG_KEY_ENABLE 0x0000CCCCU

IWDG Peripheral Enable

Definition at line 68 of file stm32f1xx_ll_iwdg.h.

Referenced by LL_IWDG_Enable().

#define LL_IWDG_KEY_RELOAD 0x0000AAAAU

IWDG Reload Counter Enable

Definition at line 67 of file stm32f1xx_ll_iwdg.h.

Referenced by LL_IWDG_ReloadCounter().

#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U

IWDG KR Write Access Disable

Definition at line 70 of file stm32f1xx_ll_iwdg.h.

Referenced by LL_IWDG_DisableWriteAccess().

#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U

IWDG KR Write Access Enable

Definition at line 69 of file stm32f1xx_ll_iwdg.h.

Referenced by LL_IWDG_EnableWriteAccess().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
IWDG Exported Constants

Flags defines which can be used with LL_IWDG_ReadReg function. More...

Defines

#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU

Detailed Description

Flags defines which can be used with LL_IWDG_ReadReg function.

Define Documentation

#define LL_IWDG_SR_PVU IWDG_SR_PVU

Watchdog prescaler value update

Definition at line 88 of file stm32f1xx_ll_iwdg.h.

#define LL_IWDG_SR_RVU IWDG_SR_RVU

Watchdog counter reload value update

Definition at line 89 of file stm32f1xx_ll_iwdg.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Prescaler Divider

Defines
Prescaler Divider
IWDG Exported Constants

Defines

#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

Divider by 128

Definition at line 103 of file stm32f1xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)

Divider by 16

Definition at line 100 of file stm32f1xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Divider by 256

Definition at line 104 of file stm32f1xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

Divider by 32

Definition at line 101 of file stm32f1xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_4 0x00000000U

Divider by 4

Definition at line 98 of file stm32f1xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)

Divider by 64

Definition at line 102 of file stm32f1xx_ll_iwdg.h.

#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)

Divider by 8

Definition at line 99 of file stm32f1xx_ll_iwdg.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
IWDG Exported Macros

Defines

#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Define Documentation

#define LL_IWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 137 of file stm32f1xx_ll_iwdg.h.

#define LL_IWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in IWDG register.

Parameters:
__INSTANCE__ | IWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 129 of file stm32f1xx_ll_iwdg.h.

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STM32F103xB HAL User Manual: Configuration

Functions
Configuration
IWDG Exported Functions

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.

Function Documentation

__STATIC_INLINE void LL_IWDG_DisableWriteAccess ( IWDG_TypeDef * IWDGx )

Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_DisableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 195 of file stm32f1xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_DISABLE.

__STATIC_INLINE void LL_IWDG_Enable ( IWDG_TypeDef * IWDGx )

Start the Independent Watchdog.

Note:
Except if the hardware watchdog option is selected
Reference Manual to LL API cross reference:
KR KEY LL_IWDG_Enable
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 162 of file stm32f1xx_ll_iwdg.h.

References LL_IWDG_KEY_ENABLE.

__STATIC_INLINE void LL_IWDG_EnableWriteAccess ( IWDG_TypeDef * IWDGx )

Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_EnableWriteAccess
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 184 of file stm32f1xx_ll_iwdg.h.

References LL_IWDG_KEY_WR_ACCESS_ENABLE.

__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler ( IWDG_TypeDef * IWDGx )

Get the selected prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_GetPrescaler
Parameters:
IWDGx IWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256

Definition at line 232 of file stm32f1xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter ( IWDG_TypeDef * IWDGx )

Get the specified IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_GetReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
Value between Min_Data=0 and Max_Data=0x0FFF

Definition at line 255 of file stm32f1xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_ReloadCounter ( IWDG_TypeDef * IWDGx )

Reloads IWDG counter with value defined in the reload register.

Reference Manual to LL API cross reference:
KR KEY LL_IWDG_ReloadCounter
Parameters:
IWDGx IWDG Instance
Return values:
None

Definition at line 173 of file stm32f1xx_ll_iwdg.h.

References LL_IWDG_KEY_RELOAD.

__STATIC_INLINE void LL_IWDG_SetPrescaler | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Select the prescaler of the IWDG.

Reference Manual to LL API cross reference:
PR PR LL_IWDG_SetPrescaler
Parameters:
IWDGx IWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_IWDG_PRESCALER_4
  • LL_IWDG_PRESCALER_8
  • LL_IWDG_PRESCALER_16
  • LL_IWDG_PRESCALER_32
  • LL_IWDG_PRESCALER_64
  • LL_IWDG_PRESCALER_128
  • LL_IWDG_PRESCALER_256
Return values:
None

Definition at line 214 of file stm32f1xx_ll_iwdg.h.

__STATIC_INLINE void LL_IWDG_SetReloadCounter | ( | IWDG_TypeDef * | IWDGx,
 |  | uint32_t | Counter
 | ) |  |

Specify the IWDG down-counter reload value.

Reference Manual to LL API cross reference:
RLR RL LL_IWDG_SetReloadCounter
Parameters:
IWDGx | IWDG Instance
Counter | Value between Min_Data=0 and Max_Data=0x0FFF
Return values:
None

Definition at line 244 of file stm32f1xx_ll_iwdg.h.

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STM32F103xB HAL User Manual: FLAG_Management

Functions
FLAG_Management
IWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Function Documentation

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU ( IWDG_TypeDef * IWDGx )

Check if flag Prescaler Value Update is set or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsActiveFlag_PVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 275 of file stm32f1xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU ( IWDG_TypeDef * IWDGx )

Check if flag Reload Value Update is set or not.

Reference Manual to LL API cross reference:
SR RVU LL_IWDG_IsActiveFlag_RVU
Parameters:
IWDGx IWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 286 of file stm32f1xx_ll_iwdg.h.

__STATIC_INLINE uint32_t LL_IWDG_IsReady ( IWDG_TypeDef * IWDGx )

Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Reference Manual to LL API cross reference:
SR PVU LL_IWDG_IsReady
SR RVU LL_IWDG_IsReady
Parameters:
IWDGx IWDG Instance
Return values:
State of bits (1 or 0).

Definition at line 299 of file stm32f1xx_ll_iwdg.h.

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STM32F103xB HAL User Manual: PWR

Modules
PWR
STM32F1xx_LL_Driver

Modules

PWR Exported Constants
PWR Exported Macros
PWR Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for PWR registers.

Register | Bit | Function
CR | CSBF | LL_PWR_ClearFlag_SB
 | CWUF | LL_PWR_ClearFlag_WU
 | DBP | LL_PWR_DisableBkUpAccess
 |  | LL_PWR_EnableBkUpAccess
 |  | LL_PWR_IsEnabledBkUpAccess
 | LPDS | LL_PWR_GetPowerMode
 |  | LL_PWR_GetRegulModeDS
 |  | LL_PWR_SetPowerMode
 |  | LL_PWR_SetRegulModeDS
 | PDDS | LL_PWR_GetPowerMode
 |  | LL_PWR_SetPowerMode
 | PLS | LL_PWR_GetPVDLevel
 |  | LL_PWR_SetPVDLevel
 | PVDE | LL_PWR_DisablePVD
 |  | LL_PWR_EnablePVD
 |  | LL_PWR_IsEnabledPVD
CSR | EWUP | LL_PWR_DisableWakeUpPin
 |  | LL_PWR_EnableWakeUpPin
 |  | LL_PWR_IsEnabledWakeUpPin
 | PVDO | LL_PWR_IsActiveFlag_PVDO
 | SBF | LL_PWR_IsActiveFlag_SB
 | WUF | LL_PWR_IsActiveFlag_WU
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STM32F103xB HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_WriteReg function. More...

Defines

#define | LL_PWR_CR_CSBF PWR_CR_CSBF
#define | LL_PWR_CR_CWUF PWR_CR_CWUF

Detailed Description

Flags defines which can be used with LL_PWR_WriteReg function.

Define Documentation

#define LL_PWR_CR_CSBF PWR_CR_CSBF

Clear standby flag

Definition at line 73 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_CR_CWUF PWR_CR_CWUF

Clear wakeup flag

Definition at line 74 of file stm32f1xx_ll_pwr.h.

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STM32F103xB HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
PWR Exported Constants

Flags defines which can be used with LL_PWR_ReadReg function. More...

Defines

#define | LL_PWR_CSR_WUF PWR_CSR_WUF
#define | LL_PWR_CSR_SBF PWR_CSR_SBF
#define | LL_PWR_CSR_PVDO PWR_CSR_PVDO
#define | LL_PWR_CSR_EWUP1 PWR_CSR_EWUP

Detailed Description

Flags defines which can be used with LL_PWR_ReadReg function.

Define Documentation

#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP

Enable WKUP pin 1

Definition at line 86 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_CSR_PVDO PWR_CSR_PVDO

Power voltage detector output flag

Definition at line 85 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_CSR_SBF PWR_CSR_SBF

Standby flag

Definition at line 84 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_CSR_WUF PWR_CSR_WUF

Wakeup flag

Definition at line 83 of file stm32f1xx_ll_pwr.h.

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STM32F103xB HAL User Manual: Mode Power

Defines
Mode Power
PWR Exported Constants

Defines

#define | LL_PWR_MODE_STOP_MAINREGU 0x00000000U
#define | LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS)
#define | LL_PWR_MODE_STANDBY (PWR_CR_PDDS)

Define Documentation

#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS)

Enter Standby mode when the CPU enters deepsleep

Definition at line 97 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS)

Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep

Definition at line 96 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U

Enter Stop mode when the CPU enters deepsleep

Definition at line 95 of file stm32f1xx_ll_pwr.h.

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STM32F103xB HAL User Manual: Regulator Mode In Deep Sleep Mode

Defines
Regulator Mode In Deep Sleep Mode
PWR Exported Constants

Defines

#define | LL_PWR_REGU_DSMODE_MAIN 0x00000000U
#define | LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS)

Define Documentation

#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS)

Voltage Regulator in low-power mode during deepsleep mode

Definition at line 106 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U

Voltage Regulator in main mode during deepsleep mode

Definition at line 105 of file stm32f1xx_ll_pwr.h.

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STM32F103xB HAL User Manual: Power Voltage Detector Level

Defines
Power Voltage Detector Level
PWR Exported Constants

Defines

#define | LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0)
#define | LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1)
#define | LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2)
#define | LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3)
#define | LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4)
#define | LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5)
#define | LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6)
#define | LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7)

Define Documentation

#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0)

Voltage threshold detected by PVD 2.2 V

Definition at line 114 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1)

Voltage threshold detected by PVD 2.3 V

Definition at line 115 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2)

Voltage threshold detected by PVD 2.4 V

Definition at line 116 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3)

Voltage threshold detected by PVD 2.5 V

Definition at line 117 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4)

Voltage threshold detected by PVD 2.6 V

Definition at line 118 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5)

Voltage threshold detected by PVD 2.7 V

Definition at line 119 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6)

Voltage threshold detected by PVD 2.8 V

Definition at line 120 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7)

Voltage threshold detected by PVD 2.9 V

Definition at line 121 of file stm32f1xx_ll_pwr.h.

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STM32F103xB HAL User Manual: Wakeup Pins

Defines
Wakeup Pins
PWR Exported Constants

Defines

#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP)

Define Documentation

#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP)

WKUP pin 1 : PA0

Definition at line 128 of file stm32f1xx_ll_pwr.h.

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STM32F103xB HAL User Manual: Common write and read registers Macros

Defines
Common write and read registers Macros
PWR Exported Macros

Defines

#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Define Documentation

#define LL_PWR_ReadReg ( __REG__ ) READ_REG(PWR->__REG__)

Read a value in PWR register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 160 of file stm32f1xx_ll_pwr.h.

#define LL_PWR_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(PWR->__REG__, (__VALUE__))

Write a value in PWR register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 153 of file stm32f1xx_ll_pwr.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration

Functions
Configuration
PWR Exported Functions

Functions

__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_SetRegulModeDS (uint32_t RegulMode)
Set voltage Regulator mode during deep sleep mode.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulModeDS (void)
Get voltage Regulator mode during deep sleep mode.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t PDMode)
Set Power Down mode when CPU enters deepsleep.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Power Down mode when CPU enters deepsleep.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.

Function Documentation

__STATIC_INLINE void LL_PWR_DisableBkUpAccess ( void )

Disable access to the backup domain.

Reference Manual to LL API cross reference:
CR DBP LL_PWR_DisableBkUpAccess
Return values:
None

Definition at line 193 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisablePVD ( void )

Disable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR PVDE LL_PWR_DisablePVD
Return values:
None

Definition at line 314 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_DisableWakeUpPin ( uint32_t WakeUpPin )

Disable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CSR EWUP LL_PWR_DisableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
Return values:
None

Definition at line 348 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableBkUpAccess ( void )

Enable access to the backup domain.

Reference Manual to LL API cross reference:
CR DBP LL_PWR_EnableBkUpAccess
Return values:
None

Definition at line 183 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnablePVD ( void )

Enable Power Voltage Detector.

Reference Manual to LL API cross reference:
CR PVDE LL_PWR_EnablePVD
Return values:
None

Definition at line 304 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_EnableWakeUpPin ( uint32_t WakeUpPin )

Enable the WakeUp PINx functionality.

Reference Manual to LL API cross reference:
CSR EWUP LL_PWR_EnableWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
Return values:
None

Definition at line 336 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPowerMode ( void )

Get Power Down mode when CPU enters deepsleep.

Reference Manual to LL API cross reference:
CR PDDS LL_PWR_GetPowerMode
Reference Manual to LL API cross reference:
CR LPDS LL_PWR_GetPowerMode
Return values:
Returned value can be one of the following values:
  • LL_PWR_MODE_STOP_MAINREGU
  • LL_PWR_MODE_STOP_LPREGU
  • LL_PWR_MODE_STANDBY

Definition at line 257 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel ( void )

Get the voltage threshold detection.

Reference Manual to LL API cross reference:
CR PLS LL_PWR_GetPVDLevel
Return values:
Returned value can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7

Definition at line 294 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS ( void )

Get voltage Regulator mode during deep sleep mode.

Reference Manual to LL API cross reference:
CR LPDS LL_PWR_GetRegulModeDS
Return values:
Returned value can be one of the following values:
  • LL_PWR_REGU_DSMODE_MAIN
  • LL_PWR_REGU_DSMODE_LOW_POWER

Definition at line 228 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess ( void )

Check if the backup domain is enabled.

Reference Manual to LL API cross reference:
CR DBP LL_PWR_IsEnabledBkUpAccess
Return values:
State of bit (1 or 0).

Definition at line 203 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD ( void )

Check if Power Voltage Detector is enabled.

Reference Manual to LL API cross reference:
CR PVDE LL_PWR_IsEnabledPVD
Return values:
State of bit (1 or 0).

Definition at line 324 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin ( uint32_t WakeUpPin )

Check if the WakeUp PINx functionality is enabled.

Reference Manual to LL API cross reference:
CSR EWUP LL_PWR_IsEnabledWakeUpPin
Parameters:
WakeUpPin This parameter can be one of the following values:
  • LL_PWR_WAKEUP_PIN1
Return values:
State of bit (1 or 0).

Definition at line 360 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPowerMode ( uint32_t PDMode )

Set Power Down mode when CPU enters deepsleep.

Reference Manual to LL API cross reference:
CR PDDS LL_PWR_SetPowerMode
Reference Manual to LL API cross reference:
CR LPDS LL_PWR_SetPowerMode
Parameters:
PDMode This parameter can be one of the following values:
  • LL_PWR_MODE_STOP_MAINREGU
  • LL_PWR_MODE_STOP_LPREGU
  • LL_PWR_MODE_STANDBY
Return values:
None

Definition at line 243 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetPVDLevel ( uint32_t PVDLevel )

Configure the voltage threshold detected by the Power Voltage Detector.

Reference Manual to LL API cross reference:
CR PLS LL_PWR_SetPVDLevel
Parameters:
PVDLevel This parameter can be one of the following values:
  • LL_PWR_PVDLEVEL_0
  • LL_PWR_PVDLEVEL_1
  • LL_PWR_PVDLEVEL_2
  • LL_PWR_PVDLEVEL_3
  • LL_PWR_PVDLEVEL_4
  • LL_PWR_PVDLEVEL_5
  • LL_PWR_PVDLEVEL_6
  • LL_PWR_PVDLEVEL_7
Return values:
None

Definition at line 276 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_SetRegulModeDS ( uint32_t RegulMode )

Set voltage Regulator mode during deep sleep mode.

Reference Manual to LL API cross reference:
CR LPDS LL_PWR_SetRegulModeDS
Parameters:
RegulMode This parameter can be one of the following values:
  • LL_PWR_REGU_DSMODE_MAIN
  • LL_PWR_REGU_DSMODE_LOW_POWER
Return values:
None

Definition at line 216 of file stm32f1xx_ll_pwr.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLAG_Management

Functions
FLAG_Management
PWR Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU (void)
Get Wake-up Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SB (void)
Get Standby Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below the selected PVD threshold.
__STATIC_INLINE void | LL_PWR_ClearFlag_SB (void)
Clear Standby Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.

Function Documentation

__STATIC_INLINE void LL_PWR_ClearFlag_SB ( void )

Clear Standby Flag.

Reference Manual to LL API cross reference:
CR CSBF LL_PWR_ClearFlag_SB
Return values:
None

Definition at line 409 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE void LL_PWR_ClearFlag_WU ( void )

Clear Wake-up Flags.

Reference Manual to LL API cross reference:
CR CWUF LL_PWR_ClearFlag_WU
Return values:
None

Definition at line 419 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO ( void )

Indicate whether VDD voltage is below the selected PVD threshold.

Reference Manual to LL API cross reference:
CSR PVDO LL_PWR_IsActiveFlag_PVDO
Return values:
State of bit (1 or 0).

Definition at line 399 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB ( void )

Get Standby Flag.

Reference Manual to LL API cross reference:
CSR SBF LL_PWR_IsActiveFlag_SB
Return values:
State of bit (1 or 0).

Definition at line 389 of file stm32f1xx_ll_pwr.h.

__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU ( void )

Get Wake-up Flag.

Reference Manual to LL API cross reference:
CSR WUF LL_PWR_IsActiveFlag_WU
Return values:
State of bit (1 or 0).

Definition at line 379 of file stm32f1xx_ll_pwr.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: De-initialization function

Functions
De-initialization function
PWR Exported Functions

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Function Documentation

ErrorStatus LL_PWR_DeInit ( void )

De-initialize the PWR registers to their default reset values.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PWR registers are de-initialized
  • ERROR: not applicable

Definition at line 74 of file stm32f1xx_ll_pwr.c.

References LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_PWR, and LL_APB1_GRP1_ReleaseReset().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC

Modules
RCC
STM32F1xx_LL_Driver

Modules

RCC Private functions
RCC Private Macros
RCC Exported Types
RCC Exported Constants
RCC Exported Macros
RCC Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for RCC registers.

Register | Bit | Function
BDCR | BDRST | LL_RCC_ForceBackupDomainReset
 |  | LL_RCC_ReleaseBackupDomainReset
 | LSEBYP | LL_RCC_LSE_DisableBypass
 |  | LL_RCC_LSE_EnableBypass
 | LSEON | LL_RCC_LSE_Disable
 |  | LL_RCC_LSE_Enable
 | LSERDY | LL_RCC_LSE_IsReady
 | RTCEN | LL_RCC_DisableRTC
 |  | LL_RCC_EnableRTC
 |  | LL_RCC_IsEnabledRTC
 | RTCSEL | LL_RCC_GetRTCClockSource
 |  | LL_RCC_SetRTCClockSource
CFGR | ADCPRE | LL_RCC_GetADCClockSource
 |  | LL_RCC_SetADCClockSource
 | HPRE | LL_RCC_GetAHBPrescaler
 |  | LL_RCC_SetAHBPrescaler
 | MCO | LL_RCC_ConfigMCO
 | OTGFSPRE | LL_RCC_GetUSBClockSource
 |  | LL_RCC_SetUSBClockSource
 | PLLMULL | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetMultiplicator
 | PLLSRC | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetMainSource
 | PLLXTPRE | LL_RCC_PLL_ConfigDomain_SYS
 | PPRE1 | LL_RCC_GetAPB1Prescaler
 |  | LL_RCC_SetAPB1Prescaler
 | PPRE2 | LL_RCC_GetAPB2Prescaler
 |  | LL_RCC_SetAPB2Prescaler
 | SW | LL_RCC_SetSysClkSource
 | SWS | LL_RCC_GetSysClkSource
 | USBPRE | LL_RCC_GetUSBClockSource
 |  | LL_RCC_SetUSBClockSource
CFGR2 | PLLXTPRE | LL_RCC_PLL_GetPrediv
 | PREDIV1 | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetPrediv
 | PREDIV1SRC | LL_RCC_PLL_ConfigDomain_SYS
 |  | LL_RCC_PLL_GetMainSource
CIR | CSSC | LL_RCC_ClearFlag_HSECSS
 | CSSF | LL_RCC_IsActiveFlag_HSECSS
 | HSERDYC | LL_RCC_ClearFlag_HSERDY
 | HSERDYF | LL_RCC_IsActiveFlag_HSERDY
 | HSERDYIE | LL_RCC_DisableIT_HSERDY
 |  | LL_RCC_EnableIT_HSERDY
 |  | LL_RCC_IsEnabledIT_HSERDY
 | HSIRDYC | LL_RCC_ClearFlag_HSIRDY
 | HSIRDYF | LL_RCC_IsActiveFlag_HSIRDY
 | HSIRDYIE | LL_RCC_DisableIT_HSIRDY
 |  | LL_RCC_EnableIT_HSIRDY
 |  | LL_RCC_IsEnabledIT_HSIRDY
 | LSERDYC | LL_RCC_ClearFlag_LSERDY
 | LSERDYF | LL_RCC_IsActiveFlag_LSERDY
 | LSERDYIE | LL_RCC_DisableIT_LSERDY
 |  | LL_RCC_EnableIT_LSERDY
 |  | LL_RCC_IsEnabledIT_LSERDY
 | LSIRDYC | LL_RCC_ClearFlag_LSIRDY
 | LSIRDYF | LL_RCC_IsActiveFlag_LSIRDY
 | LSIRDYIE | LL_RCC_DisableIT_LSIRDY
 |  | LL_RCC_EnableIT_LSIRDY
 |  | LL_RCC_IsEnabledIT_LSIRDY
 | PLLRDYC | LL_RCC_ClearFlag_PLLRDY
 | PLLRDYF | LL_RCC_IsActiveFlag_PLLRDY
 | PLLRDYIE | LL_RCC_DisableIT_PLLRDY
 |  | LL_RCC_EnableIT_PLLRDY
 |  | LL_RCC_IsEnabledIT_PLLRDY
CR | CSSON | LL_RCC_HSE_EnableCSS
 | HSEBYP | LL_RCC_HSE_DisableBypass
 |  | LL_RCC_HSE_EnableBypass
 | HSEON | LL_RCC_HSE_Disable
 |  | LL_RCC_HSE_Enable
 | HSERDY | LL_RCC_HSE_IsReady
 | HSICAL | LL_RCC_HSI_GetCalibration
 | HSION | LL_RCC_HSI_Disable
 |  | LL_RCC_HSI_Enable
 | HSIRDY | LL_RCC_HSI_IsReady
 | HSITRIM | LL_RCC_HSI_GetCalibTrimming
 |  | LL_RCC_HSI_SetCalibTrimming
 | PLLON | LL_RCC_PLL_Disable
 |  | LL_RCC_PLL_Enable
 | PLLRDY | LL_RCC_PLL_IsReady
CSR | IWDGRSTF | LL_RCC_IsActiveFlag_IWDGRST
 | LPWRRSTF | LL_RCC_IsActiveFlag_LPWRRST
 | LSION | LL_RCC_LSI_Disable
 |  | LL_RCC_LSI_Enable
 | LSIRDY | LL_RCC_LSI_IsReady
 | PINRSTF | LL_RCC_IsActiveFlag_PINRST
 | PORRSTF | LL_RCC_IsActiveFlag_PORRST
 | RMVF | LL_RCC_ClearResetFlags
 | SFTRSTF | LL_RCC_IsActiveFlag_SFTRST
 | WWDGRSTF | LL_RCC_IsActiveFlag_WWDGRST
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC Private functions

Functions
RCC Private functions
RCC

Functions

uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock frequency used for system domain.

Function Documentation

uint32_t RCC_GetHCLKClockFreq ( uint32_t SYSCLK_Frequency )

Return HCLK clock frequency.

Parameters:
SYSCLK_Frequency SYSCLK clock frequency
Return values:
HCLK clock frequency (in Hz)

Definition at line 405 of file stm32f1xx_ll_rcc.c.

References __LL_RCC_CALC_HCLK_FREQ, and LL_RCC_GetAHBPrescaler().

Referenced by LL_RCC_GetADCClockFreq(), and LL_RCC_GetSystemClocksFreq().

uint32_t RCC_GetPCLK1ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK1 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 416 of file stm32f1xx_ll_rcc.c.

References __LL_RCC_CALC_PCLK1_FREQ, and LL_RCC_GetAPB1Prescaler().

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t RCC_GetPCLK2ClockFreq ( uint32_t HCLK_Frequency )

Return PCLK2 clock frequency.

Parameters:
HCLK_Frequency HCLK clock frequency
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 427 of file stm32f1xx_ll_rcc.c.

References __LL_RCC_CALC_PCLK2_FREQ, and LL_RCC_GetAPB2Prescaler().

Referenced by LL_RCC_GetADCClockFreq(), and LL_RCC_GetSystemClocksFreq().

uint32_t RCC_GetSystemClockFreq ( void )

Return SYSTEM clock frequency.

Return values:
SYSTEM clock frequency (in Hz)

Definition at line 373 of file stm32f1xx_ll_rcc.c.

References HSE_VALUE, HSI_VALUE, LL_RCC_GetSysClkSource(), LL_RCC_SYS_CLKSOURCE_STATUS_HSE, LL_RCC_SYS_CLKSOURCE_STATUS_HSI, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, and RCC_PLL_GetFreqDomain_SYS().

Referenced by LL_RCC_GetADCClockFreq(), and LL_RCC_GetSystemClocksFreq().

uint32_t RCC_PLL_GetFreqDomain_SYS ( void )

Return PLL clock frequency used for system domain.

Return values:
PLL clock frequency (in Hz)

Definition at line 437 of file stm32f1xx_ll_rcc.c.

References __LL_RCC_CALC_PLLCLK_FREQ, HSE_VALUE, HSI_VALUE, LL_RCC_PLL_GetMainSource(), LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv(), LL_RCC_PLLSOURCE_HSE, and LL_RCC_PLLSOURCE_HSI_DIV_2.

Referenced by LL_RCC_GetUSBClockFreq(), and RCC_GetSystemClockFreq().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC Private Macros

Defines
RCC Private Macros
RCC

Defines

#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))

Define Documentation

#define IS_LL_RCC_ADC_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))

Definition at line 72 of file stm32f1xx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq().

#define IS_LL_RCC_USB_CLKSOURCE ( __VALUE__ ) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))

Definition at line 69 of file stm32f1xx_ll_rcc.c.

Referenced by LL_RCC_GetUSBClockFreq().

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STM32F103xB HAL User Manual: LL_RCC_ClocksTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_RCC_ClocksTypeDef Struct Reference
Clocks Frequency Structure

RCC Clocks Frequency Structure. More...

#include <stm32f1xx_ll_rcc.h>

Data Fields

uint32_t | SYSCLK_Frequency
uint32_t | HCLK_Frequency
uint32_t | PCLK1_Frequency
uint32_t | PCLK2_Frequency

Detailed Description

RCC Clocks Frequency Structure.

Definition at line 84 of file stm32f1xx_ll_rcc.h.

Field Documentation

uint32_t LL_RCC_ClocksTypeDef::HCLK_Frequency

HCLK clock frequency

Definition at line 87 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

uint32_t LL_RCC_ClocksTypeDef::PCLK1_Frequency

PCLK1 clock frequency

Definition at line 88 of file stm32f1xx_ll_rcc.h.

Referenced by LL_I2C_Init(), LL_RCC_GetSystemClocksFreq(), and LL_USART_Init().

uint32_t LL_RCC_ClocksTypeDef::PCLK2_Frequency

PCLK2 clock frequency

Definition at line 89 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq(), and LL_USART_Init().

uint32_t LL_RCC_ClocksTypeDef::SYSCLK_Frequency

SYSCLK clock frequency

Definition at line 86 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_GetSystemClocksFreq().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_rcc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Oscillator Values adaptation

Defines
Oscillator Values adaptation
RCC Exported Constants

Defines used to adapt values of different oscillators. More...

Defines

#define | HSE_VALUE 8000000U
#define | HSI_VALUE 8000000U
#define | LSE_VALUE 32768U
#define | LSI_VALUE 32000U

Detailed Description

Defines used to adapt values of different oscillators.

Note:
These values could be modified in the user environment according to HW set-up.

Define Documentation

#define HSE_VALUE 8000000U

Value of the HSE oscillator in Hz

Definition at line 113 of file stm32f1xx_ll_rcc.h.

#define HSI_VALUE 8000000U

Value of the HSI oscillator in Hz

Definition at line 117 of file stm32f1xx_ll_rcc.h.

#define LSE_VALUE 32768U

Value of the LSE oscillator in Hz

Definition at line 121 of file stm32f1xx_ll_rcc.h.

#define LSI_VALUE 32000U

Value of the LSI oscillator in Hz

Definition at line 125 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: Clear Flags Defines

Defines
Clear Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_WriteReg function. More...

Defines

#define | LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC
#define | LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC
#define | LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC
#define | LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC
#define | LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC
#define | LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC
#define | LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC
#define | LL_RCC_CIR_CSSC RCC_CIR_CSSC

Detailed Description

Flags defines which can be used with LL_RCC_WriteReg function.

Define Documentation

#define LL_RCC_CIR_CSSC RCC_CIR_CSSC

Clock Security System Interrupt Clear

Definition at line 142 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC

HSE Ready Interrupt Clear

Definition at line 138 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC

HSI Ready Interrupt Clear

Definition at line 137 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC

LSE Ready Interrupt Clear

Definition at line 136 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC

LSI Ready Interrupt Clear

Definition at line 135 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC

PLL2 Ready Interrupt Clear

Definition at line 141 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC

PLL3(PLLI2S) Ready Interrupt Clear

Definition at line 140 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC

PLL Ready Interrupt Clear

Definition at line 139 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
RCC Exported Constants

Flags defines which can be used with LL_RCC_ReadReg function. More...

Defines

#define | LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF
#define | LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF
#define | LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF
#define | LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF
#define | LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF
#define | LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF
#define | LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF
#define | LL_RCC_CIR_CSSF RCC_CIR_CSSF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF

Detailed Description

Flags defines which can be used with LL_RCC_ReadReg function.

Define Documentation

#define LL_RCC_CIR_CSSF RCC_CIR_CSSF

Clock Security System Interrupt flag

Definition at line 158 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF

HSE Ready Interrupt flag

Definition at line 154 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF

HSI Ready Interrupt flag

Definition at line 153 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF

LSE Ready Interrupt flag

Definition at line 152 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF

LSI Ready Interrupt flag

Definition at line 151 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF

PLL2 Ready Interrupt flag

Definition at line 157 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF

PLL3(PLLI2S) Ready Interrupt flag

Definition at line 156 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF

PLL Ready Interrupt flag

Definition at line 155 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF

Independent Watchdog reset flag

Definition at line 162 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF

Low-Power reset flag

Definition at line 164 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF

PIN reset flag

Definition at line 159 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF

POR/PDR reset flag

Definition at line 160 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF

Software Reset flag

Definition at line 161 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF

Window watchdog reset flag

Definition at line 163 of file stm32f1xx_ll_rcc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IT Defines

Defines
IT Defines
RCC Exported Constants

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions. More...

Defines

#define | LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE
#define | LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE
#define | LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE
#define | LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE
#define | LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE
#define | LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE
#define | LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE

Detailed Description

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

Define Documentation

#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE

HSE Ready Interrupt Enable

Definition at line 176 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE

HSI Ready Interrupt Enable

Definition at line 175 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE

LSE Ready Interrupt Enable

Definition at line 174 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE

LSI Ready Interrupt Enable

Definition at line 173 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE

PLL2 Ready Interrupt Enable

Definition at line 179 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE

PLL3(PLLI2S) Ready Interrupt Enable

Definition at line 178 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE

PLL Ready Interrupt Enable

Definition at line 177 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: System clock switch

Defines
System clock switch
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE

HSE selection as system clock

Definition at line 214 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI

HSI selection as system clock

Definition at line 213 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL

PLL selection as system clock

Definition at line 215 of file stm32f1xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

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STM32F103xB HAL User Manual: System clock switch status

Defines
System clock switch status
RCC Exported Constants

Defines

#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL

Define Documentation

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 224 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 223 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq().

#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL

PLL used as system clock

Definition at line 225 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: AHB prescaler

Defines
AHB prescaler
RCC Exported Constants

Defines

#define | LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
#define | LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
#define | LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
#define | LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
#define | LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
#define | LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
#define | LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
#define | LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512

Define Documentation

#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1

SYSCLK not divided

Definition at line 233 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128

SYSCLK divided by 128

Definition at line 239 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16

SYSCLK divided by 16

Definition at line 237 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2

SYSCLK divided by 2

Definition at line 234 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256

SYSCLK divided by 256

Definition at line 240 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4

SYSCLK divided by 4

Definition at line 235 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512

SYSCLK divided by 512

Definition at line 241 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64

SYSCLK divided by 64

Definition at line 238 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8

SYSCLK divided by 8

Definition at line 236 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: APB low-speed prescaler (APB1)

Defines
APB low-speed prescaler (APB1)
RCC Exported Constants

Defines

#define | LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
#define | LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
#define | LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
#define | LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16

Define Documentation

#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1

HCLK not divided

Definition at line 249 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16

HCLK divided by 16

Definition at line 253 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2

HCLK divided by 2

Definition at line 250 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4

HCLK divided by 4

Definition at line 251 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8

HCLK divided by 8

Definition at line 252 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: APB high-speed prescaler (APB2)

Defines
APB high-speed prescaler (APB2)
RCC Exported Constants

Defines

#define | LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
#define | LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
#define | LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
#define | LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16

Define Documentation

#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1

HCLK not divided

Definition at line 261 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16

HCLK divided by 16

Definition at line 265 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2

HCLK divided by 2

Definition at line 262 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4

HCLK divided by 4

Definition at line 263 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8

HCLK divided by 8

Definition at line 264 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: MCO1 SOURCE selection

Defines
MCO1 SOURCE selection
RCC Exported Constants

Defines

#define | LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
#define | LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE
#define | LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2

Define Documentation

#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE

HSE selection as MCO source

Definition at line 276 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI

HSI selection as MCO source

Definition at line 275 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK

MCO output disabled, no clock on MCO

Definition at line 273 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2

PLL clock divided by 2

Definition at line 277 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK

SYSCLK selection as MCO source

Definition at line 274 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: Peripheral clock frequency

Defines
Peripheral clock frequency
RCC Exported Constants

Defines

#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Define Documentation

#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU

Frequency cannot be provided as external clock

Definition at line 299 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U

No clock enabled for the peripheral

Definition at line 298 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq(), and LL_USART_Init().

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STM32F103xB HAL User Manual: Peripheral USB clock source selection

Defines
Peripheral USB clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE
#define | LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U

Define Documentation

#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE

PLL clock is not divided

Definition at line 323 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U

PLL clock is divided by 1.5

Definition at line 324 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

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STM32F103xB HAL User Manual: Peripheral ADC clock source selection

Defines
Peripheral ADC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/

Define Documentation

#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/

Definition at line 338 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/

Definition at line 339 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/

Definition at line 340 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/

Definition at line 341 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: Peripheral USB get clock source

Defines
Peripheral USB get clock source
RCC Exported Constants

Defines

#define LL_RCC_USB_CLKSOURCE 0x00400000U

Define Documentation

#define LL_RCC_USB_CLKSOURCE 0x00400000U

USB Clock source selection

Definition at line 362 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: Peripheral ADC get clock source

Defines
Peripheral ADC get clock source
RCC Exported Constants

Defines

#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE

Define Documentation

#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE

ADC Clock source selection

Definition at line 372 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: RTC clock source selection

Defines
RTC clock source selection
RCC Exported Constants

Defines

#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL

Define Documentation

#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL

HSE oscillator clock divided by 128 used as RTC clock

Definition at line 383 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0

LSE oscillator clock used as RTC clock

Definition at line 381 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1

LSI oscillator clock used as RTC clock

Definition at line 382 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U

No clock used as RTC clock

Definition at line 380 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: PLL Multiplicator factor

Defines
PLL Multiplicator factor
RCC Exported Constants

Defines

#define | LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2
#define | LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3
#define | LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4
#define | LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5
#define | LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6
#define | LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7
#define | LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8
#define | LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9
#define | LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10
#define | LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11
#define | LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12
#define | LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13
#define | LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14
#define | LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15
#define | LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16

Define Documentation

#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10

PLL input clock*10

Definition at line 406 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11

PLL input clock*11

Definition at line 407 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12

PLL input clock*12

Definition at line 408 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13

PLL input clock*13

Definition at line 409 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14

PLL input clock*14

Definition at line 410 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15

PLL input clock*15

Definition at line 411 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16

PLL input clock*16

Definition at line 412 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2

PLL input clock*2

Definition at line 392 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3

PLL input clock*3

Definition at line 395 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4

PLL input clock*4

Definition at line 397 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5

PLL input clock*5

Definition at line 398 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6

PLL input clock*6

Definition at line 399 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7

PLL input clock*7

Definition at line 400 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8

PLL input clock*8

Definition at line 401 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9

PLL input clock*9

Definition at line 402 of file stm32f1xx_ll_rcc.h.

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STM32F103xB HAL User Manual: PLL SOURCE

Defines
PLL SOURCE
RCC Exported Constants

Defines

#define | LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U
#define | LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC
#define | LL_RCC_PLLSOURCE_HSE_DIV_1 RCC_CFGR_PLLSRC
#define | LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)

Define Documentation

#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC

HSE/PREDIV1 clock selected as PLL entry clock source

Definition at line 422 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

#define LL_RCC_PLLSOURCE_HSE_DIV_1 RCC_CFGR_PLLSRC

HSE clock selected as PLL entry clock source

Definition at line 427 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)

HSE/2 clock selected as PLL entry clock source

Definition at line 462 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U

HSI clock divided by 2 selected as PLL entry clock source

Definition at line 421 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), and RCC_PLL_GetFreqDomain_SYS().

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STM32F103xB HAL User Manual: PREDIV Division factor

Defines
PREDIV Division factor
RCC Exported Constants

Defines

#define | LL_RCC_PREDIV_DIV_1 0x00000000U
#define | LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE

Define Documentation

#define LL_RCC_PREDIV_DIV_1 0x00000000U

HSE divider clock clock not divided

Definition at line 489 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE

HSE divider clock divided by 2 for PLL entry

Definition at line 490 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI().

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STM32F103xB HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
RCC Exported Macros

Defines

#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.

Define Documentation

#define LL_RCC_ReadReg ( __REG__ ) READ_REG(RCC->__REG__)

Read a value in RCC register.

Parameters:
__REG__ Register to be read
Return values:
Register value

Definition at line 560 of file stm32f1xx_ll_rcc.h.

#define LL_RCC_WriteReg | ( | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(RCC->__REG__, (__VALUE__))

Write a value in RCC register.

Parameters:
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 553 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

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STM32F103xB HAL User Manual: Calculate frequencies

Defines
Calculate frequencies
RCC Exported Macros

Defines

#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))
Helper macro to calculate the PLLCLK frequency.
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
Helper macro to calculate the HCLK frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
Helper macro to calculate the PCLK2 frequency (ABP2)

Define Documentation

#define __LL_RCC_CALC_HCLK_FREQ | ( | __SYSCLKFREQ__,
 |  | __AHBPRESCALER__
 | ) | ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])

Helper macro to calculate the HCLK frequency.

Note:
: __AHBPRESCALER__ be retrieved by LL_RCC_GetAHBPrescaler ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
Parameters:
__SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
__AHBPRESCALER__,: This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
HCLK clock frequency (in Hz)

Definition at line 706 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

#define __LL_RCC_CALC_PCLK1_FREQ | ( | __HCLKFREQ__,
 |  | __APB1PRESCALER__
 | ) | ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])

Helper macro to calculate the PCLK1 frequency (ABP1)

Note:
: __APB1PRESCALER__ be retrieved by LL_RCC_GetAPB1Prescaler ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
Parameters:
__HCLKFREQ__ HCLK frequency
__APB1PRESCALER__,: This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
PCLK1 clock frequency (in Hz)

Definition at line 721 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

#define __LL_RCC_CALC_PCLK2_FREQ | ( | __HCLKFREQ__,
 |  | __APB2PRESCALER__
 | ) | ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])

Helper macro to calculate the PCLK2 frequency (ABP2)

Note:
: __APB2PRESCALER__ be retrieved by LL_RCC_GetAPB2Prescaler ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
Parameters:
__HCLKFREQ__ HCLK frequency
__APB2PRESCALER__,: This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
PCLK2 clock frequency (in Hz)

Definition at line 736 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

#define __LL_RCC_CALC_PLLCLK_FREQ | ( | __INPUTFREQ__,
 |  | __PLLMUL__
 | ) | ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))

Helper macro to calculate the PLLCLK frequency.

Note:
ex: __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (LL_RCC_PLL_GetPrediv () + 1), LL_RCC_PLL_GetMultiplicator ());
Parameters:
__INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
__PLLMUL__,: This parameter can be one of the following values:
  • LL_RCC_PLL_MUL_2
  • LL_RCC_PLL_MUL_3
  • LL_RCC_PLL_MUL_4
  • LL_RCC_PLL_MUL_5
  • LL_RCC_PLL_MUL_6
  • LL_RCC_PLL_MUL_7
  • LL_RCC_PLL_MUL_8
  • LL_RCC_PLL_MUL_9
  • LL_RCC_PLL_MUL_10
  • LL_RCC_PLL_MUL_11
  • LL_RCC_PLL_MUL_12
  • LL_RCC_PLL_MUL_13
  • LL_RCC_PLL_MUL_14
  • LL_RCC_PLL_MUL_15
  • LL_RCC_PLL_MUL_16
Return values:
PLL clock frequency (in Hz)

Definition at line 612 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS(), and UTILS_GetPLLOutputFrequency().

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STM32F103xB HAL User Manual: HSE

Functions
HSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_HSE_Disable ( void )

Disable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Disable
Return values:
None

Definition at line 800 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSE_DisableBypass ( void )

Disable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_DisableBypass
Return values:
None

Definition at line 780 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_Enable ( void )

Enable HSE crystal oscillator (HSE ON)

Reference Manual to LL API cross reference:
CR HSEON LL_RCC_HSE_Enable
Return values:
None

Definition at line 790 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableBypass ( void )

Enable HSE external oscillator (HSE Bypass)

Reference Manual to LL API cross reference:
CR HSEBYP LL_RCC_HSE_EnableBypass
Return values:
None

Definition at line 770 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

__STATIC_INLINE void LL_RCC_HSE_EnableCSS ( void )

Enable the Clock Security System.

Reference Manual to LL API cross reference:
CR CSSON LL_RCC_HSE_EnableCSS
Return values:
None

Definition at line 760 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady ( void )

Check if HSE oscillator Ready.

Reference Manual to LL API cross reference:
CR HSERDY LL_RCC_HSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 810 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: HSI

Functions
HSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.

Function Documentation

__STATIC_INLINE void LL_RCC_HSI_Disable ( void )

Disable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Disable
Return values:
None

Definition at line 866 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_HSI_Enable ( void )

Enable HSI oscillator.

Reference Manual to LL API cross reference:
CR HSION LL_RCC_HSI_Enable
Return values:
None

Definition at line 856 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI(), and LL_RCC_DeInit().

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration ( void )

Get HSI Calibration value.

Note:
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value
Reference Manual to LL API cross reference:
CR HSICAL LL_RCC_HSI_GetCalibration
Return values:
Between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 888 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming ( void )

Get HSI Calibration trimming.

Reference Manual to LL API cross reference:
CR HSITRIM LL_RCC_HSI_GetCalibTrimming
Return values:
Between Min_Data = 0x00 and Max_Data = 0x1F

Definition at line 912 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady ( void )

Check if HSI clock is ready.

Reference Manual to LL API cross reference:
CR HSIRDY LL_RCC_HSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 876 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming ( uint32_t Value )

Set HSI Calibration trimming.

Note:
user-programmable trimming value that is added to the HSICAL
Default value is 16, which, when added to the HSICAL value, should trim the HSI to 16 MHz +/- 1 %
Reference Manual to LL API cross reference:
CR HSITRIM LL_RCC_HSI_SetCalibTrimming
Parameters:
Value between Min_Data = 0x00 and Max_Data = 0x1F
Return values:
None

Definition at line 902 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_DeInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LSE

Functions
LSE
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_LSE_Disable ( void )

Disable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Disable
Return values:
None

Definition at line 940 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_DisableBypass ( void )

Disable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_DisableBypass
Return values:
None

Definition at line 960 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_Enable ( void )

Enable Low Speed External (LSE) crystal.

Reference Manual to LL API cross reference:
BDCR LSEON LL_RCC_LSE_Enable
Return values:
None

Definition at line 930 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSE_EnableBypass ( void )

Enable external clock source (LSE bypass).

Reference Manual to LL API cross reference:
BDCR LSEBYP LL_RCC_LSE_EnableBypass
Return values:
None

Definition at line 950 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady ( void )

Check if LSE oscillator Ready.

Reference Manual to LL API cross reference:
BDCR LSERDY LL_RCC_LSE_IsReady
Return values:
State of bit (1 or 0).

Definition at line 970 of file stm32f1xx_ll_rcc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LSI

Functions
LSI
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.

Function Documentation

__STATIC_INLINE void LL_RCC_LSI_Disable ( void )

Disable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Disable
Return values:
None

Definition at line 998 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_LSI_Enable ( void )

Enable LSI Oscillator.

Reference Manual to LL API cross reference:
CSR LSION LL_RCC_LSI_Enable
Return values:
None

Definition at line 988 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady ( void )

Check if LSI is Ready.

Reference Manual to LL API cross reference:
CSR LSIRDY LL_RCC_LSI_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1008 of file stm32f1xx_ll_rcc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: System

Functions
System
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler ( void )

Get AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_GetAHBPrescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512

Definition at line 1114 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_GetHCLKClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler ( void )

Get APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE1 LL_RCC_GetAPB1Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16

Definition at line 1129 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_GetPCLK1ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler ( void )

Get APB2 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE2 LL_RCC_GetAPB2Prescaler
Return values:
Returned value can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16

Definition at line 1144 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_GetPCLK2ClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource ( void )

Get the system clock source.

Reference Manual to LL API cross reference:
CFGR SWS LL_RCC_GetSysClkSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL

Definition at line 1043 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_GetSystemClockFreq(), and UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAHBPrescaler ( uint32_t Prescaler )

Set AHB prescaler.

Reference Manual to LL API cross reference:
CFGR HPRE LL_RCC_SetAHBPrescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_SYSCLK_DIV_1
  • LL_RCC_SYSCLK_DIV_2
  • LL_RCC_SYSCLK_DIV_4
  • LL_RCC_SYSCLK_DIV_8
  • LL_RCC_SYSCLK_DIV_16
  • LL_RCC_SYSCLK_DIV_64
  • LL_RCC_SYSCLK_DIV_128
  • LL_RCC_SYSCLK_DIV_256
  • LL_RCC_SYSCLK_DIV_512
Return values:
None

Definition at line 1063 of file stm32f1xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB1Prescaler ( uint32_t Prescaler )

Set APB1 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE1 LL_RCC_SetAPB1Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB1_DIV_1
  • LL_RCC_APB1_DIV_2
  • LL_RCC_APB1_DIV_4
  • LL_RCC_APB1_DIV_8
  • LL_RCC_APB1_DIV_16
Return values:
None

Definition at line 1079 of file stm32f1xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetAPB2Prescaler ( uint32_t Prescaler )

Set APB2 prescaler.

Reference Manual to LL API cross reference:
CFGR PPRE2 LL_RCC_SetAPB2Prescaler
Parameters:
Prescaler This parameter can be one of the following values:
  • LL_RCC_APB2_DIV_1
  • LL_RCC_APB2_DIV_2
  • LL_RCC_APB2_DIV_4
  • LL_RCC_APB2_DIV_8
  • LL_RCC_APB2_DIV_16
Return values:
None

Definition at line 1095 of file stm32f1xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE void LL_RCC_SetSysClkSource ( uint32_t Source )

Configure the system clock source.

Reference Manual to LL API cross reference:
CFGR SW LL_RCC_SetSysClkSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_SYS_CLKSOURCE_HSI
  • LL_RCC_SYS_CLKSOURCE_HSE
  • LL_RCC_SYS_CLKSOURCE_PLL
Return values:
None

Definition at line 1030 of file stm32f1xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: MCO

Functions
MCO
RCC Exported Functions

Functions

__STATIC_INLINE void LL_RCC_ConfigMCO (uint32_t MCOxSource)
Configure MCOx.

Function Documentation

__STATIC_INLINE void LL_RCC_ConfigMCO ( uint32_t MCOxSource )

Configure MCOx.

Reference Manual to LL API cross reference:
CFGR MCO LL_RCC_ConfigMCO
Parameters:
MCOxSource This parameter can be one of the following values:
  • LL_RCC_MCO1SOURCE_NOCLOCK
  • LL_RCC_MCO1SOURCE_SYSCLK
  • LL_RCC_MCO1SOURCE_HSI
  • LL_RCC_MCO1SOURCE_HSE
  • LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
  • LL_RCC_MCO1SOURCE_PLL2CLK (*)
  • LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
  • LL_RCC_MCO1SOURCE_EXT_HSE (*)
  • LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
(*) value not defined in all devices
Return values:
None

Definition at line 1174 of file stm32f1xx_ll_rcc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Clock Source

Functions
Peripheral Clock Source
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.

Function Documentation

__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource ( uint32_t ADCx )

Get ADCx clock source.

Reference Manual to LL API cross reference:
CFGR ADCPRE LL_RCC_GetADCClockSource
Parameters:
ADCx This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_8

Definition at line 1296 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_GetADCClockFreq().

__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource ( uint32_t USBx )

Get USBx clock source.

Reference Manual to LL API cross reference:
CFGR OTGFSPRE LL_RCC_GetUSBClockSource
CFGR USBPRE LL_RCC_GetUSBClockSource
Parameters:
USBx This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
Returned value can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_PLL (*)
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
(*) value not defined in all devices

Definition at line 1279 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq().

__STATIC_INLINE void LL_RCC_SetADCClockSource ( uint32_t ADCxSource )

Configure ADC clock source.

Reference Manual to LL API cross reference:
CFGR ADCPRE LL_RCC_SetADCClockSource
Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
Return values:
None

Definition at line 1239 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetUSBClockSource ( uint32_t USBxSource )

Configure USB clock source.

Reference Manual to LL API cross reference:
CFGR OTGFSPRE LL_RCC_SetUSBClockSource
CFGR USBPRE LL_RCC_SetUSBClockSource
Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE_PLL (*)
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
(*) value not defined in all devices
Return values:
None

Definition at line 1219 of file stm32f1xx_ll_rcc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC

Functions
RTC
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableRTC ( void )

Disable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_DisableRTC
Return values:
None

Definition at line 1355 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableRTC ( void )

Enable RTC.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_EnableRTC
Return values:
None

Definition at line 1345 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ForceBackupDomainReset ( void )

Force the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ForceBackupDomainReset
Return values:
None

Definition at line 1375 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource ( void )

Get RTC Clock Source.

Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_GetRTCClockSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV128

Definition at line 1335 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC ( void )

Check if RTC has been enabled or not.

Reference Manual to LL API cross reference:
BDCR RTCEN LL_RCC_IsEnabledRTC
Return values:
State of bit (1 or 0).

Definition at line 1365 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset ( void )

Release the Backup domain reset.

Reference Manual to LL API cross reference:
BDCR BDRST LL_RCC_ReleaseBackupDomainReset
Return values:
None

Definition at line 1385 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_SetRTCClockSource ( uint32_t Source )

Set RTC Clock Source.

Note:
Once the RTC clock source has been selected, it cannot be changed any more unless the Backup domain is reset. The BDRST bit can be used to reset them.
Reference Manual to LL API cross reference:
BDCR RTCSEL LL_RCC_SetRTCClockSource
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_RTC_CLKSOURCE_NONE
  • LL_RCC_RTC_CLKSOURCE_LSE
  • LL_RCC_RTC_CLKSOURCE_LSI
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV128
Return values:
None

Definition at line 1321 of file stm32f1xx_ll_rcc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PLL

Functions
PLL
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLMul)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMultiplicator (void)
Get PLL multiplication Factor.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetPrediv (void)
Get PREDIV1 division factor for the main PLL.

Function Documentation

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS | ( | uint32_t | Source,
 |  | uint32_t | PLLMul
 | ) |  |

Configure PLL used for SYSCLK Domain.

Reference Manual to LL API cross reference:
CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS
CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS
CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS
CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS
CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS
Parameters:
Source This parameter can be one of the following values:
  • LL_RCC_PLLSOURCE_HSI_DIV_2
  • LL_RCC_PLLSOURCE_HSE_DIV_1
  • LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
  • LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
  • LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
(*) value not defined in all devices
PLLMul This parameter can be one of the following values:
  • LL_RCC_PLL_MUL_2 (*)
  • LL_RCC_PLL_MUL_3 (*)
  • LL_RCC_PLL_MUL_4
  • LL_RCC_PLL_MUL_5
  • LL_RCC_PLL_MUL_6
  • LL_RCC_PLL_MUL_7
  • LL_RCC_PLL_MUL_8
  • LL_RCC_PLL_MUL_9
  • LL_RCC_PLL_MUL_6_5 (*)
  • LL_RCC_PLL_MUL_10 (*)
  • LL_RCC_PLL_MUL_11 (*)
  • LL_RCC_PLL_MUL_12 (*)
  • LL_RCC_PLL_MUL_13 (*)
  • LL_RCC_PLL_MUL_14 (*)
  • LL_RCC_PLL_MUL_15 (*)
  • LL_RCC_PLL_MUL_16 (*)
(*) value not defined in all devices
Return values:
None

Definition at line 1492 of file stm32f1xx_ll_rcc.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

__STATIC_INLINE void LL_RCC_PLL_Disable ( void )

Disable PLL.

Note:
Cannot be disabled if the PLL clock is used as the system clock
Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Disable
Return values:
None

Definition at line 1414 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_PLL_Enable ( void )

Enable PLL.

Reference Manual to LL API cross reference:
CR PLLON LL_RCC_PLL_Enable
Return values:
None

Definition at line 1403 of file stm32f1xx_ll_rcc.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource ( void )

Get the oscillator used as PLL clock source.

Reference Manual to LL API cross reference:
CFGR PLLSRC LL_RCC_PLL_GetMainSource
CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLLSOURCE_HSI_DIV_2
  • LL_RCC_PLLSOURCE_HSE
  • LL_RCC_PLLSOURCE_PLL2 (*)
(*) value not defined in all devices

Definition at line 1517 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator ( void )

Get PLL multiplication Factor.

Reference Manual to LL API cross reference:
CFGR PLLMULL LL_RCC_PLL_GetMultiplicator
Return values:
Returned value can be one of the following values:
  • LL_RCC_PLL_MUL_2 (*)
  • LL_RCC_PLL_MUL_3 (*)
  • LL_RCC_PLL_MUL_4
  • LL_RCC_PLL_MUL_5
  • LL_RCC_PLL_MUL_6
  • LL_RCC_PLL_MUL_7
  • LL_RCC_PLL_MUL_8
  • LL_RCC_PLL_MUL_9
  • LL_RCC_PLL_MUL_6_5 (*)
  • LL_RCC_PLL_MUL_10 (*)
  • LL_RCC_PLL_MUL_11 (*)
  • LL_RCC_PLL_MUL_12 (*)
  • LL_RCC_PLL_MUL_13 (*)
  • LL_RCC_PLL_MUL_14 (*)
  • LL_RCC_PLL_MUL_15 (*)
  • LL_RCC_PLL_MUL_16 (*)
(*) value not defined in all devices

Definition at line 1551 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv ( void )

Get PREDIV1 division factor for the main PLL.

Note:
They can be written only when the PLL is disabled
Reference Manual to LL API cross reference:
CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv
CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv
Return values:
Returned value can be one of the following values:
  • LL_RCC_PREDIV_DIV_1
  • LL_RCC_PREDIV_DIV_2
  • LL_RCC_PREDIV_DIV_3 (*)
  • LL_RCC_PREDIV_DIV_4 (*)
  • LL_RCC_PREDIV_DIV_5 (*)
  • LL_RCC_PREDIV_DIV_6 (*)
  • LL_RCC_PREDIV_DIV_7 (*)
  • LL_RCC_PREDIV_DIV_8 (*)
  • LL_RCC_PREDIV_DIV_9 (*)
  • LL_RCC_PREDIV_DIV_10 (*)
  • LL_RCC_PREDIV_DIV_11 (*)
  • LL_RCC_PREDIV_DIV_12 (*)
  • LL_RCC_PREDIV_DIV_13 (*)
  • LL_RCC_PREDIV_DIV_14 (*)
  • LL_RCC_PREDIV_DIV_15 (*)
  • LL_RCC_PREDIV_DIV_16 (*)
(*) value not defined in all devices

Definition at line 1581 of file stm32f1xx_ll_rcc.h.

Referenced by RCC_PLL_GetFreqDomain_SYS().

__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady ( void )

Check if PLL Ready.

Reference Manual to LL API cross reference:
CR PLLRDY LL_RCC_PLL_IsReady
Return values:
State of bit (1 or 0).

Definition at line 1424 of file stm32f1xx_ll_rcc.h.

Referenced by LL_RCC_GetUSBClockFreq(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_PLL_IsBusy().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLAG Management

Functions
FLAG Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PORRST (void)
Check if RCC flag POR/PDR reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.

Function Documentation

__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS ( void )

Clear Clock security system interrupt flag.

Reference Manual to LL API cross reference:
CIR CSSC LL_RCC_ClearFlag_HSECSS
Return values:
None

Definition at line 1871 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY ( void )

Clear HSE ready interrupt flag.

Reference Manual to LL API cross reference:
CIR HSERDYC LL_RCC_ClearFlag_HSERDY
Return values:
None

Definition at line 1827 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY ( void )

Clear HSI ready interrupt flag.

Reference Manual to LL API cross reference:
CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
Return values:
None

Definition at line 1817 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY ( void )

Clear LSE ready interrupt flag.

Reference Manual to LL API cross reference:
CIR LSERDYC LL_RCC_ClearFlag_LSERDY
Return values:
None

Definition at line 1807 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY ( void )

Clear LSI ready interrupt flag.

Reference Manual to LL API cross reference:
CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
Return values:
None

Definition at line 1797 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY ( void )

Clear PLL ready interrupt flag.

Reference Manual to LL API cross reference:
CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
Return values:
None

Definition at line 1837 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_ClearResetFlags ( void )

Set RMVF bit to clear the reset flags.

Reference Manual to LL API cross reference:
CSR RMVF LL_RCC_ClearResetFlags
Return values:
None

Definition at line 2025 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS ( void )

Check if Clock security system interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR CSSF LL_RCC_IsActiveFlag_HSECSS
Return values:
State of bit (1 or 0).

Definition at line 1955 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY ( void )

Check if HSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 1911 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY ( void )

Check if HSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 1901 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST ( void )

Check if RCC flag Independent Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
Return values:
State of bit (1 or 0).

Definition at line 1965 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST ( void )

Check if RCC flag Low Power reset is set or not.

Reference Manual to LL API cross reference:
CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
Return values:
State of bit (1 or 0).

Definition at line 1975 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY ( void )

Check if LSE ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 1891 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY ( void )

Check if LSI ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 1881 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST ( void )

Check if RCC flag Pin reset is set or not.

Reference Manual to LL API cross reference:
CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
Return values:
State of bit (1 or 0).

Definition at line 1985 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY ( void )

Check if PLL ready interrupt occurred or not.

Reference Manual to LL API cross reference:
CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 1921 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST ( void )

Check if RCC flag POR/PDR reset is set or not.

Reference Manual to LL API cross reference:
CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
Return values:
State of bit (1 or 0).

Definition at line 1995 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST ( void )

Check if RCC flag Software reset is set or not.

Reference Manual to LL API cross reference:
CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
Return values:
State of bit (1 or 0).

Definition at line 2005 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST ( void )

Check if RCC flag Window Watchdog reset is set or not.

Reference Manual to LL API cross reference:
CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
Return values:
State of bit (1 or 0).

Definition at line 2015 of file stm32f1xx_ll_rcc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IT Management

Functions
IT Management
RCC Exported Functions

Functions

__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_RCC_DisableIT_HSERDY ( void )

Disable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIR HSERDYIE LL_RCC_DisableIT_HSERDY
Return values:
None

Definition at line 2147 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY ( void )

Disable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
Return values:
None

Definition at line 2137 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSERDY ( void )

Disable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIR LSERDYIE LL_RCC_DisableIT_LSERDY
Return values:
None

Definition at line 2127 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY ( void )

Disable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
Return values:
None

Definition at line 2117 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY ( void )

Disable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
Return values:
None

Definition at line 2157 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSERDY ( void )

Enable HSE ready interrupt.

Reference Manual to LL API cross reference:
CIR HSERDYIE LL_RCC_EnableIT_HSERDY
Return values:
None

Definition at line 2073 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY ( void )

Enable HSI ready interrupt.

Reference Manual to LL API cross reference:
CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
Return values:
None

Definition at line 2063 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSERDY ( void )

Enable LSE ready interrupt.

Reference Manual to LL API cross reference:
CIR LSERDYIE LL_RCC_EnableIT_LSERDY
Return values:
None

Definition at line 2053 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY ( void )

Enable LSI ready interrupt.

Reference Manual to LL API cross reference:
CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
Return values:
None

Definition at line 2043 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY ( void )

Enable PLL ready interrupt.

Reference Manual to LL API cross reference:
CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
Return values:
None

Definition at line 2083 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY ( void )

Checks if HSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
Return values:
State of bit (1 or 0).

Definition at line 2221 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY ( void )

Checks if HSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
Return values:
State of bit (1 or 0).

Definition at line 2211 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY ( void )

Checks if LSE ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
Return values:
State of bit (1 or 0).

Definition at line 2201 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY ( void )

Checks if LSI ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
Return values:
State of bit (1 or 0).

Definition at line 2191 of file stm32f1xx_ll_rcc.h.

__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY ( void )

Checks if PLL ready interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
Return values:
State of bit (1 or 0).

Definition at line 2231 of file stm32f1xx_ll_rcc.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: De-initialization function

Functions
De-initialization function
RCC Exported Functions

Functions

ErrorStatus LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.

Function Documentation

ErrorStatus LL_RCC_DeInit ( void )

Reset the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE PLL, PLL2, PLL3 OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: RCC registers are de-initialized
  • ERROR: not applicable

Definition at line 120 of file stm32f1xx_ll_rcc.c.

References LL_RCC_HSI_Enable(), LL_RCC_HSI_SetCalibTrimming(), and LL_RCC_WriteReg.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Get system and peripherals clocks frequency functions

Functions
Get system and peripherals clocks frequency functions
RCC Exported Functions

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device. More...

Functions

void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.

Detailed Description

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device.

Note:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
If SYSCLK source is PLL, function returns values based on HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
(**) HSI_VALUE is a defined constant but the real value may vary depending on the variations in voltage and temperature.
(***) HSE_VALUE is a defined constant, user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be incorrect when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.

Function Documentation

uint32_t LL_RCC_GetADCClockFreq ( uint32_t ADCxSource )

Return ADCx clock frequency.

Parameters:
ADCxSource This parameter can be one of the following values:
  • LL_RCC_ADC_CLKSOURCE
Return values:
ADC clock frequency (in Hz)

Definition at line 339 of file stm32f1xx_ll_rcc.c.

References assert_param, IS_LL_RCC_ADC_CLKSOURCE, LL_RCC_GetADCClockSource(), RCC_GetHCLKClockFreq(), RCC_GetPCLK2ClockFreq(), and RCC_GetSystemClockFreq().

void LL_RCC_GetSystemClocksFreq ( LL_RCC_ClocksTypeDef * RCC_Clocks )

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.

Note:
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update structure fields. Otherwise, any configuration based on this function will be incorrect.
Parameters:
RCC_Clocks pointer to a LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
Return values:
None

Definition at line 223 of file stm32f1xx_ll_rcc.c.

References LL_RCC_ClocksTypeDef::HCLK_Frequency, LL_RCC_ClocksTypeDef::PCLK1_Frequency, LL_RCC_ClocksTypeDef::PCLK2_Frequency, RCC_GetHCLKClockFreq(), RCC_GetPCLK1ClockFreq(), RCC_GetPCLK2ClockFreq(), RCC_GetSystemClockFreq(), and LL_RCC_ClocksTypeDef::SYSCLK_Frequency.

Referenced by LL_I2C_Init(), and LL_USART_Init().

uint32_t LL_RCC_GetUSBClockFreq ( uint32_t USBxSource )

Return USBx clock frequency.

Parameters:
USBxSource This parameter can be one of the following values:
  • LL_RCC_USB_CLKSOURCE
Return values:
USB clock frequency (in Hz)
  • LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready

Definition at line 280 of file stm32f1xx_ll_rcc.c.

References assert_param, IS_LL_RCC_USB_CLKSOURCE, LL_RCC_GetUSBClockSource(), LL_RCC_PERIPH_FREQUENCY_NO, LL_RCC_PLL_IsReady(), LL_RCC_USB_CLKSOURCE_PLL, LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5, and RCC_PLL_GetFreqDomain_SYS().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI

Modules
SPI
STM32F1xx_LL_Driver

Modules

SPI Private Constants
SPI Private Macros
SPI Exported Init structure
SPI Exported Constants
SPI Exported Macros
SPI Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for SPI registers.

Register | Bit | Function
CR1 | BIDIMODE | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | BIDIOE | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | BR | LL_SPI_GetBaudRatePrescaler
 |  | LL_SPI_SetBaudRatePrescaler
 | CPHA | LL_SPI_GetClockPhase
 |  | LL_SPI_SetClockPhase
 | CPOL | LL_SPI_GetClockPolarity
 |  | LL_SPI_SetClockPolarity
 | CRCEN | LL_SPI_DisableCRC
 |  | LL_SPI_EnableCRC
 |  | LL_SPI_IsEnabledCRC
 | CRCNEXT | LL_SPI_SetCRCNext
 | DFF | LL_SPI_GetDataWidth
 |  | LL_SPI_SetDataWidth
 | LSBFIRST | LL_SPI_GetTransferBitOrder
 |  | LL_SPI_SetTransferBitOrder
 | MSTR | LL_SPI_GetMode
 |  | LL_SPI_SetMode
 | RXONLY | LL_SPI_GetTransferDirection
 |  | LL_SPI_SetTransferDirection
 | SPE | LL_SPI_Disable
 |  | LL_SPI_Enable
 |  | LL_SPI_IsEnabled
 | SSI | LL_SPI_GetMode
 |  | LL_SPI_SetMode
 | SSM | LL_SPI_GetNSSMode
 |  | LL_SPI_SetNSSMode
CR2 | ERRIE | LL_SPI_DisableIT_ERR
 |  | LL_SPI_EnableIT_ERR
 |  | LL_SPI_IsEnabledIT_ERR
 | RXDMAEN | LL_SPI_DisableDMAReq_RX
 |  | LL_SPI_EnableDMAReq_RX
 |  | LL_SPI_IsEnabledDMAReq_RX
 | RXNEIE | LL_SPI_DisableIT_RXNE
 |  | LL_SPI_EnableIT_RXNE
 |  | LL_SPI_IsEnabledIT_RXNE
 | SSOE | LL_SPI_GetNSSMode
 |  | LL_SPI_SetNSSMode
 | TXDMAEN | LL_SPI_DisableDMAReq_TX
 |  | LL_SPI_EnableDMAReq_TX
 |  | LL_SPI_IsEnabledDMAReq_TX
 | TXEIE | LL_SPI_DisableIT_TXE
 |  | LL_SPI_EnableIT_TXE
 |  | LL_SPI_IsEnabledIT_TXE
CRCPR | CRCPOLY | LL_SPI_GetCRCPolynomial
 |  | LL_SPI_SetCRCPolynomial
DR | DR | LL_SPI_DMA_GetRegAddr
 |  | LL_SPI_ReceiveData16
 |  | LL_SPI_ReceiveData8
 |  | LL_SPI_TransmitData16
 |  | LL_SPI_TransmitData8
RXCRCR | RXCRC | LL_SPI_GetRxCRC
SR | BSY | LL_SPI_IsActiveFlag_BSY
 | CRCERR | LL_SPI_ClearFlag_CRCERR
 |  | LL_SPI_IsActiveFlag_CRCERR
 | MODF | LL_SPI_ClearFlag_MODF
 |  | LL_SPI_IsActiveFlag_MODF
 | OVR | LL_SPI_ClearFlag_OVR
 |  | LL_SPI_IsActiveFlag_OVR
 | RXNE | LL_SPI_IsActiveFlag_RXNE
 | TXE | LL_SPI_IsActiveFlag_TXE
TXCRCR | TXCRC | LL_SPI_GetTxCRC
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define SPI_CR1_CLEAR_MASK

Define Documentation

#define SPI_CR1_CLEAR_MASK
Value:
(SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_DFF    | \
                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
                                            SPI_CR1_BIDIMODE)

Definition at line 68 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)

Define Documentation

#define IS_LL_SPI_BAUDRATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
                                    || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))

Definition at line 102 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_BITORDER ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_LSB_FIRST) \
                                    || ((__VALUE__) == LL_SPI_MSB_FIRST))

Definition at line 111 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRC_POLYNOMIAL ( __VALUE__ ) ((__VALUE__) >= 0x1U)

Definition at line 117 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_CRCCALCULATION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
                                          || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))

Definition at line 114 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
                                     || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))

Definition at line 89 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_MODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_MODE_MASTER) \
                                || ((__VALUE__) == LL_SPI_MODE_SLAVE))

Definition at line 86 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_NSS ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_NSS_SOFT) \
                               || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
                               || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))

Definition at line 98 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_PHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_PHASE_1EDGE) \
                                 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))

Definition at line 95 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_POLARITY_LOW) \
                                    || ((__VALUE__) == LL_SPI_POLARITY_HIGH))

Definition at line 92 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

#define IS_LL_SPI_TRANSFER_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
                                              || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
                                              || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
                                              || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))

Definition at line 81 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_SPI_InitTypeDef Struct Reference
SPI Exported Init structure

SPI Init structures definition. More...

#include <stm32f1xx_ll_spi.h>

Data Fields

uint32_t | TransferDirection
uint32_t | Mode
uint32_t | DataWidth
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | NSS
uint32_t | BaudRate
uint32_t | BitOrder
uint32_t | CRCCalculation
uint32_t | CRCPoly

Detailed Description

SPI Init structures definition.

Definition at line 72 of file stm32f1xx_ll_spi.h.

Field Documentation

uint32_t LL_SPI_InitTypeDef::BaudRate

Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of Baud Rate Prescaler.

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

This feature can be modified afterwards using unitary function LL_SPI_SetBaudRatePrescaler().

Definition at line 104 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::BitOrder

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of Transmission Bit Order.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferBitOrder().

Definition at line 110 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of Clock Phase.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPhase().

Definition at line 94 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::ClockPolarity

Specifies the serial clock steady state. This parameter can be a value of Clock Polarity.

This feature can be modified afterwards using unitary function LL_SPI_SetClockPolarity().

Definition at line 89 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of CRC Calculation.

This feature can be modified afterwards using unitary functions LL_SPI_EnableCRC() and LL_SPI_DisableCRC().

Definition at line 115 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::CRCPoly

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_SPI_SetCRCPolynomial().

Definition at line 120 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::DataWidth

Specifies the SPI data width. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_SPI_SetDataWidth().

Definition at line 84 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::Mode

Specifies the SPI mode (Master/Slave). This parameter can be a value of Operation Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetMode().

Definition at line 79 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of Slave Select Pin Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetNSSMode().

Definition at line 99 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

uint32_t LL_SPI_InitTypeDef::TransferDirection

Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of Transfer Mode.

This feature can be modified afterwards using unitary function LL_SPI_SetTransferDirection().

Definition at line 74 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init(), and LL_SPI_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_spi.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
SPI Exported Constants

Flags defines which can be used with LL_SPI_ReadReg function. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE

Detailed Description

Flags defines which can be used with LL_SPI_ReadReg function.

Define Documentation

#define LL_SPI_SR_BSY SPI_SR_BSY

Busy flag

Definition at line 143 of file stm32f1xx_ll_spi.h.

#define LL_SPI_SR_CRCERR SPI_SR_CRCERR

CRC error flag

Definition at line 144 of file stm32f1xx_ll_spi.h.

#define LL_SPI_SR_FRE SPI_SR_FRE

TI mode frame format error flag

Definition at line 147 of file stm32f1xx_ll_spi.h.

#define LL_SPI_SR_MODF SPI_SR_MODF

Mode fault flag

Definition at line 145 of file stm32f1xx_ll_spi.h.

#define LL_SPI_SR_OVR SPI_SR_OVR

Overrun flag

Definition at line 146 of file stm32f1xx_ll_spi.h.

#define LL_SPI_SR_RXNE SPI_SR_RXNE

Rx buffer not empty flag

Definition at line 141 of file stm32f1xx_ll_spi.h.

#define LL_SPI_SR_TXE SPI_SR_TXE

Tx buffer empty flag

Definition at line 142 of file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Operation Mode

Defines
Operation Mode
SPI Exported Constants

Defines

#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE 0x00000000U

Define Documentation

#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Master configuration

Definition at line 166 of file stm32f1xx_ll_spi.h.

#define LL_SPI_MODE_SLAVE 0x00000000U

Slave configuration

Definition at line 167 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Clock Phase

Defines
Clock Phase
SPI Exported Constants

Defines

#define | LL_SPI_PHASE_1EDGE 0x00000000U
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Define Documentation

#define LL_SPI_PHASE_1EDGE 0x00000000U

First clock transition is the first data capture edge

Definition at line 176 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)

Second clock transition is the first data capture edge

Definition at line 177 of file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Clock Polarity

Defines
Clock Polarity
SPI Exported Constants

Defines

#define | LL_SPI_POLARITY_LOW 0x00000000U
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Define Documentation

#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)

Clock to 1 when idle

Definition at line 186 of file stm32f1xx_ll_spi.h.

#define LL_SPI_POLARITY_LOW 0x00000000U

Clock to 0 when idle

Definition at line 185 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Baud Rate Prescaler

Defines
Baud Rate Prescaler
SPI Exported Constants

Defines

#define | LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)

BaudRate control equal to fPCLK/128

Definition at line 200 of file stm32f1xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/16

Definition at line 197 of file stm32f1xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U

BaudRate control equal to fPCLK/2

Definition at line 194 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/256

Definition at line 201 of file stm32f1xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)

BaudRate control equal to fPCLK/32

Definition at line 198 of file stm32f1xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)

BaudRate control equal to fPCLK/4

Definition at line 195 of file stm32f1xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)

BaudRate control equal to fPCLK/64

Definition at line 199 of file stm32f1xx_ll_spi.h.

#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)

BaudRate control equal to fPCLK/8

Definition at line 196 of file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Transmission Bit Order

Defines
Transmission Bit Order
SPI Exported Constants

Defines

#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST 0x00000000U

Define Documentation

#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)

Data is transmitted/received with the LSB first

Definition at line 209 of file stm32f1xx_ll_spi.h.

#define LL_SPI_MSB_FIRST 0x00000000U

Data is transmitted/received with the MSB first

Definition at line 210 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Transfer Mode

Defines
Transfer Mode
SPI Exported Constants

Defines

#define | LL_SPI_FULL_DUPLEX 0x00000000U
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Define Documentation

#define LL_SPI_FULL_DUPLEX 0x00000000U

Full-Duplex mode. Rx and Tx transfer on 2 lines

Definition at line 218 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)

Half-Duplex Rx mode. Rx transfer on 1 line

Definition at line 220 of file stm32f1xx_ll_spi.h.

#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)

Half-Duplex Tx mode. Tx transfer on 1 line

Definition at line 221 of file stm32f1xx_ll_spi.h.

#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)

Simplex Rx mode. Rx transfer only on 1 line

Definition at line 219 of file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Slave Select Pin Mode

Defines
Slave Select Pin Mode
SPI Exported Constants

Defines

#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT 0x00000000U
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

Define Documentation

#define LL_SPI_NSS_HARD_INPUT 0x00000000U

NSS pin used in Input. Only used in Master mode

Definition at line 230 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))

NSS pin used in Output. Only used in Slave mode as chip select

Definition at line 231 of file stm32f1xx_ll_spi.h.

#define LL_SPI_NSS_SOFT (SPI_CR1_SSM)

NSS managed internally. NSS pin not used and free

Definition at line 229 of file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Datawidth

Defines
Datawidth
SPI Exported Constants

Defines

#define | LL_SPI_DATAWIDTH_8BIT 0x00000000U
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF)

Define Documentation

#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF)

Data length for SPI transfer: 16 bits

Definition at line 240 of file stm32f1xx_ll_spi.h.

#define LL_SPI_DATAWIDTH_8BIT 0x00000000U

Data length for SPI transfer: 8 bits

Definition at line 239 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CRC Calculation

Defines
CRC Calculation
SPI Exported Constants

Defines

#define | LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

Define Documentation

#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U

CRC calculation disabled

Definition at line 249 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_StructInit().

#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)

CRC calculation enabled

Definition at line 250 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
SPI Exported Macros

Defines

#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.

Define Documentation

#define LL_SPI_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 284 of file stm32f1xx_ll_spi.h.

#define LL_SPI_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in SPI register.

Parameters:
__INSTANCE__ | SPI Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 276 of file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration

Functions
Configuration
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.

Function Documentation

__STATIC_INLINE void LL_SPI_Disable ( SPI_TypeDef * SPIx )

Disable SPI peripheral.

Note:
When disabling the SPI, follow the procedure described in the Reference Manual.
Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Disable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 320 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_Enable ( SPI_TypeDef * SPIx )

Enable SPI peripheral.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_Enable
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 308 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler ( SPI_TypeDef * SPIx )

Get baud rate prescaler.

Reference Manual to LL API cross reference:
CR1 BR LL_SPI_GetBaudRatePrescaler
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256

Definition at line 460 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPhase ( SPI_TypeDef * SPIx )

Get clock phase.

Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_GetClockPhase
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE

Definition at line 391 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity ( SPI_TypeDef * SPIx )

Get clock polarity.

Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_GetClockPolarity
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH

Definition at line 420 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetDataWidth ( SPI_TypeDef * SPIx )

Get frame data width.

Reference Manual to LL API cross reference:
CR1 DFF LL_SPI_GetDataWidth
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_16BIT

Definition at line 552 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetMode ( SPI_TypeDef * SPIx )

Get SPI operation mode (Master or Slave)

Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_GetMode
CR1 SSI LL_SPI_GetMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE

Definition at line 361 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder ( SPI_TypeDef * SPIx )

Get transfer bit order.

Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_GetTransferBitOrder
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST

Definition at line 488 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection ( SPI_TypeDef * SPIx )

Get transfer direction mode.

Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_GetTransferDirection
CR1 BIDIMODE LL_SPI_GetTransferDirection
CR1 BIDIOE LL_SPI_GetTransferDirection
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX

Definition at line 525 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabled ( SPI_TypeDef * SPIx )

Check if SPI peripheral is enabled.

Reference Manual to LL API cross reference:
CR1 SPE LL_SPI_IsEnabled
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 331 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init().

__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BaudRate
 | ) |  |

Set baud rate prescaler.

Note:
These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
Reference Manual to LL API cross reference:
CR1 BR LL_SPI_SetBaudRatePrescaler
Parameters:
SPIx SPI Instance
BaudRate This parameter can be one of the following values:
  • LL_SPI_BAUDRATEPRESCALER_DIV2
  • LL_SPI_BAUDRATEPRESCALER_DIV4
  • LL_SPI_BAUDRATEPRESCALER_DIV8
  • LL_SPI_BAUDRATEPRESCALER_DIV16
  • LL_SPI_BAUDRATEPRESCALER_DIV32
  • LL_SPI_BAUDRATEPRESCALER_DIV64
  • LL_SPI_BAUDRATEPRESCALER_DIV128
  • LL_SPI_BAUDRATEPRESCALER_DIV256
Return values:
None

Definition at line 441 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPhase | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPhase
 | ) |  |

Set clock phase.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPHA LL_SPI_SetClockPhase
Parameters:
SPIx SPI Instance
ClockPhase This parameter can be one of the following values:
  • LL_SPI_PHASE_1EDGE
  • LL_SPI_PHASE_2EDGE
Return values:
None

Definition at line 378 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetClockPolarity | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Set clock polarity.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 CPOL LL_SPI_SetClockPolarity
Parameters:
SPIx SPI Instance
ClockPolarity This parameter can be one of the following values:
  • LL_SPI_POLARITY_LOW
  • LL_SPI_POLARITY_HIGH
Return values:
None

Definition at line 407 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetDataWidth | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | DataWidth
 | ) |  |

Set frame data width.

Reference Manual to LL API cross reference:
CR1 DFF LL_SPI_SetDataWidth
Parameters:
SPIx SPI Instance
DataWidth This parameter can be one of the following values:
  • LL_SPI_DATAWIDTH_8BIT
  • LL_SPI_DATAWIDTH_16BIT
Return values:
None

Definition at line 539 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | Mode
 | ) |  |

Set SPI operation mode to Master or Slave.

Note:
This bit should not be changed when communication is ongoing.
Reference Manual to LL API cross reference:
CR1 MSTR LL_SPI_SetMode
CR1 SSI LL_SPI_SetMode
Parameters:
SPIx SPI Instance
Mode This parameter can be one of the following values:
  • LL_SPI_MODE_MASTER
  • LL_SPI_MODE_SLAVE
Return values:
None

Definition at line 347 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferBitOrder | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | BitOrder
 | ) |  |

Set transfer bit order.

Note:
This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 LSBFIRST LL_SPI_SetTransferBitOrder
Parameters:
SPIx SPI Instance
BitOrder This parameter can be one of the following values:
  • LL_SPI_LSB_FIRST
  • LL_SPI_MSB_FIRST
Return values:
None

Definition at line 475 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetTransferDirection | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | TransferDirection
 | ) |  |

Set transfer direction mode.

Note:
For Half-Duplex mode, Rx Direction is set by default. In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
Reference Manual to LL API cross reference:
CR1 RXONLY LL_SPI_SetTransferDirection
CR1 BIDIMODE LL_SPI_SetTransferDirection
CR1 BIDIOE LL_SPI_SetTransferDirection
Parameters:
SPIx SPI Instance
TransferDirection This parameter can be one of the following values:
  • LL_SPI_FULL_DUPLEX
  • LL_SPI_SIMPLEX_RX
  • LL_SPI_HALF_DUPLEX_RX
  • LL_SPI_HALF_DUPLEX_TX
Return values:
None

Definition at line 508 of file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CRC Management

Functions
CRC Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableCRC ( SPI_TypeDef * SPIx )

Disable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_DisableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 584 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableCRC ( SPI_TypeDef * SPIx )

Enable CRC.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_EnableCRC
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 572 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial ( SPI_TypeDef * SPIx )

Get polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 631 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetRxCRC ( SPI_TypeDef * SPIx )

Get Rx CRC.

Reference Manual to LL API cross reference:
RXCRCR RXCRC LL_SPI_GetRxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 642 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_GetTxCRC ( SPI_TypeDef * SPIx )

Get Tx CRC.

Reference Manual to LL API cross reference:
TXCRCR TXCRC LL_SPI_GetTxCRC
Parameters:
SPIx SPI Instance
Return values:
Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF

Definition at line 653 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC ( SPI_TypeDef * SPIx )

Check if CRC is enabled.

Note:
This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
Reference Manual to LL API cross reference:
CR1 CRCEN LL_SPI_IsEnabledCRC
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 596 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCNext ( SPI_TypeDef * SPIx )

Set CRCNext to transfer CRC on the line.

Note:
This bit has to be written as soon as the last data is written in the SPIx_DR register.
Reference Manual to LL API cross reference:
CR1 CRCNEXT LL_SPI_SetCRCNext
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 608 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetCRCPolynomial | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | CRCPoly
 | ) |  |

Set polynomial for CRC calculation.

Reference Manual to LL API cross reference:
CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
Parameters:
SPIx | SPI Instance
CRCPoly | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
Return values:
None

Definition at line 620 of file stm32f1xx_ll_spi.h.

Referenced by LL_SPI_Init().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Slave Select Pin Management

Functions
Slave Select Pin Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.

Function Documentation

__STATIC_INLINE uint32_t LL_SPI_GetNSSMode ( SPI_TypeDef * SPIx )

Get NSS mode.

Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_GetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_GetNSSMode
Parameters:
SPIx SPI Instance
Return values:
Returned value can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT

Definition at line 694 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_SetNSSMode | ( | SPI_TypeDef * | SPIx,
 |  | uint32_t | NSS
 | ) |  |

Set NSS mode.

Note:
LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
Reference Manual to LL API cross reference:
CR1 SSM LL_SPI_SetNSSMode
Reference Manual to LL API cross reference:
CR2 SSOE LL_SPI_SetNSSMode
Parameters:
SPIx SPI Instance
NSS This parameter can be one of the following values:
  • LL_SPI_NSS_SOFT
  • LL_SPI_NSS_HARD_INPUT
  • LL_SPI_NSS_HARD_OUTPUT
Return values:
None

Definition at line 678 of file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLAG Management

Functions
FLAG Management
SPI Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.

Function Documentation

__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR ( SPI_TypeDef * SPIx )

Clear CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_ClearFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 789 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_MODF ( SPI_TypeDef * SPIx )

Clear mode fault error flag.

Note:
Clearing this flag is done by a read access to the SPIx_SR register followed by a write access to the SPIx_CR1 register
Reference Manual to LL API cross reference:
SR MODF LL_SPI_ClearFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 802 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_ClearFlag_OVR ( SPI_TypeDef * SPIx )

Clear overrun error flag.

Note:
Clearing this flag is done by a read access to the SPIx_DR register followed by a read access to the SPIx_SR register
Reference Manual to LL API cross reference:
SR OVR LL_SPI_ClearFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 819 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_ClearFlag_OVR().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY ( SPI_TypeDef * SPIx )

Get busy flag.

Note:
The BSY flag is cleared under any one of the following conditions: -When the SPI is correctly disabled -When a fault is detected in Master mode (MODF bit set to 1) -In Master mode, when it finishes a data transmission and no new data is ready to be sent -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between each data transfer.
Reference Manual to LL API cross reference:
SR BSY LL_SPI_IsActiveFlag_BSY
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 777 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_BSY().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR ( SPI_TypeDef * SPIx )

Get CRC error flag.

Reference Manual to LL API cross reference:
SR CRCERR LL_SPI_IsActiveFlag_CRCERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 737 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF ( SPI_TypeDef * SPIx )

Get mode fault error flag.

Reference Manual to LL API cross reference:
SR MODF LL_SPI_IsActiveFlag_MODF
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 748 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR ( SPI_TypeDef * SPIx )

Get overrun error flag.

Reference Manual to LL API cross reference:
SR OVR LL_SPI_IsActiveFlag_OVR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 759 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_OVR().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer is not empty.

Reference Manual to LL API cross reference:
SR RXNE LL_SPI_IsActiveFlag_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 715 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_RXNE().

__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer is empty.

Reference Manual to LL API cross reference:
SR TXE LL_SPI_IsActiveFlag_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 726 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_IsActiveFlag_TXE().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Interrupt Management

Functions
Interrupt Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableIT_ERR ( SPI_TypeDef * SPIx )

Disable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_DisableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 878 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_ERR().

__STATIC_INLINE void LL_SPI_DisableIT_RXNE ( SPI_TypeDef * SPIx )

Disable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_DisableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 889 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_RXNE().

__STATIC_INLINE void LL_SPI_DisableIT_TXE ( SPI_TypeDef * SPIx )

Disable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_DisableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 900 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_DisableIT_TXE().

__STATIC_INLINE void LL_SPI_EnableIT_ERR ( SPI_TypeDef * SPIx )

Enable error interrupt.

Note:
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_EnableIT_ERR
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 844 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_ERR().

__STATIC_INLINE void LL_SPI_EnableIT_RXNE ( SPI_TypeDef * SPIx )

Enable Rx buffer not empty interrupt.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_EnableIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 855 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_RXNE().

__STATIC_INLINE void LL_SPI_EnableIT_TXE ( SPI_TypeDef * SPIx )

Enable Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_EnableIT_TXE
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 866 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_EnableIT_TXE().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR ( SPI_TypeDef * SPIx )

Check if error interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 ERRIE LL_SPI_IsEnabledIT_ERR
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 911 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_ERR().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE ( SPI_TypeDef * SPIx )

Check if Rx buffer not empty interrupt is enabled.

Reference Manual to LL API cross reference:
CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 922 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_RXNE().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE ( SPI_TypeDef * SPIx )

Check if Tx buffer empty interrupt.

Reference Manual to LL API cross reference:
CR2 TXEIE LL_SPI_IsEnabledIT_TXE
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 933 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledIT_TXE().

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Management

Functions
DMA Management
SPI Exported Functions

Functions

__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_SPI_DisableDMAReq_RX ( SPI_TypeDef * SPIx )

Disable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 963 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_DisableDMAReq_RX().

__STATIC_INLINE void LL_SPI_DisableDMAReq_TX ( SPI_TypeDef * SPIx )

Disable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 996 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_DisableDMAReq_TX().

__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr ( SPI_TypeDef * SPIx )

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
DR DR LL_SPI_DMA_GetRegAddr
Parameters:
SPIx SPI Instance
Return values:
Address of data register

Definition at line 1018 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_EnableDMAReq_RX ( SPI_TypeDef * SPIx )

Enable DMA Rx.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 952 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_EnableDMAReq_RX().

__STATIC_INLINE void LL_SPI_EnableDMAReq_TX ( SPI_TypeDef * SPIx )

Enable DMA Tx.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
None

Definition at line 985 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_EnableDMAReq_TX().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX ( SPI_TypeDef * SPIx )

Check if DMA Rx is enabled.

Reference Manual to LL API cross reference:
CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 974 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledDMAReq_RX().

__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX ( SPI_TypeDef * SPIx )

Check if DMA Tx is enabled.

Reference Manual to LL API cross reference:
CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
Parameters:
SPIx SPI Instance
Return values:
State of bit (1 or 0).

Definition at line 1007 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_IsEnabledDMAReq_TX().

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DATA Management

Functions
DATA Management
SPI Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.

Function Documentation

__STATIC_INLINE uint16_t LL_SPI_ReceiveData16 ( SPI_TypeDef * SPIx )

Read 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData16
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 1048 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_ReceiveData16().

__STATIC_INLINE uint8_t LL_SPI_ReceiveData8 ( SPI_TypeDef * SPIx )

Read 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_ReceiveData8
Parameters:
SPIx SPI Instance
Return values:
RxData Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 1037 of file stm32f1xx_ll_spi.h.

__STATIC_INLINE void LL_SPI_TransmitData16 | ( | SPI_TypeDef * | SPIx,
 |  | uint16_t | TxData
 | ) |  |

Write 16-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData16
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFFFF
Return values:
None

Definition at line 1072 of file stm32f1xx_ll_spi.h.

Referenced by LL_I2S_TransmitData16().

__STATIC_INLINE void LL_SPI_TransmitData8 | ( | SPI_TypeDef * | SPIx,
 |  | uint8_t | TxData
 | ) |  |

Write 8-Bits in the data register.

Reference Manual to LL API cross reference:
DR DR LL_SPI_TransmitData8
Parameters:
SPIx | SPI Instance
TxData | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1060 of file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Function Documentation

ErrorStatus LL_SPI_DeInit ( SPI_TypeDef * SPIx )

De-initialize the SPI registers to their default reset values.

Parameters:
SPIx SPI Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: SPI registers are de-initialized
  • ERROR: SPI registers are not de-initialized

Definition at line 141 of file stm32f1xx_ll_spi.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_SPI2, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_SPI1, and LL_APB2_GRP1_ReleaseReset().

Referenced by LL_I2S_DeInit().

ErrorStatus LL_SPI_Init | ( | SPI_TypeDef * | SPIx,
 |  | LL_SPI_InitTypeDef * | SPI_InitStruct
 | ) |  |

Initialize the SPI registers according to the specified parameters in SPI_InitStruct.

Note:
As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
SPIx | SPI Instance
SPI_InitStruct | pointer to a LL_SPI_InitTypeDef structure
Return values:
An ErrorStatus enumeration value. (Return always SUCCESS)

Definition at line 196 of file stm32f1xx_ll_spi.c.

References assert_param, LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, IS_LL_SPI_BAUDRATE, IS_LL_SPI_BITORDER, IS_LL_SPI_CRC_POLYNOMIAL, IS_LL_SPI_CRCCALCULATION, IS_LL_SPI_DATAWIDTH, IS_LL_SPI_MODE, IS_LL_SPI_NSS, IS_LL_SPI_PHASE, IS_LL_SPI_POLARITY, IS_LL_SPI_TRANSFER_DIRECTION, LL_SPI_CRCCALCULATION_ENABLE, LL_SPI_IsEnabled(), LL_SPI_SetCRCPolynomial(), LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, SPI_CR1_CLEAR_MASK, and LL_SPI_InitTypeDef::TransferDirection.

void LL_SPI_StructInit ( LL_SPI_InitTypeDef * SPI_InitStruct )

Set each LL_SPI_InitTypeDef field to default value.

Parameters:
SPI_InitStruct pointer to a LL_SPI_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 266 of file stm32f1xx_ll_spi.c.

References LL_SPI_InitTypeDef::BaudRate, LL_SPI_InitTypeDef::BitOrder, LL_SPI_InitTypeDef::ClockPhase, LL_SPI_InitTypeDef::ClockPolarity, LL_SPI_InitTypeDef::CRCCalculation, LL_SPI_InitTypeDef::CRCPoly, LL_SPI_InitTypeDef::DataWidth, LL_SPI_BAUDRATEPRESCALER_DIV2, LL_SPI_CRCCALCULATION_DISABLE, LL_SPI_DATAWIDTH_8BIT, LL_SPI_FULL_DUPLEX, LL_SPI_MODE_SLAVE, LL_SPI_MSB_FIRST, LL_SPI_NSS_HARD_INPUT, LL_SPI_PHASE_1EDGE, LL_SPI_POLARITY_LOW, LL_SPI_InitTypeDef::Mode, LL_SPI_InitTypeDef::NSS, and LL_SPI_InitTypeDef::TransferDirection.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SYSTEM

Modules
SYSTEM
STM32F1xx_LL_Driver

Modules

SYSTEM Private Constants
SYSTEM Exported Constants
SYSTEM Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for SYSTEM registers.

Register | Bit | Function
DBGMCU_CR | DBG_SLEEP | LL_DBGMCU_DisableDBGSleepMode
 |  | LL_DBGMCU_EnableDBGSleepMode
 | DBG_STANDBY | LL_DBGMCU_DisableDBGStandbyMode
 |  | LL_DBGMCU_EnableDBGStandbyMode
 | DBG_STOP | LL_DBGMCU_DisableDBGStopMode
 |  | LL_DBGMCU_EnableDBGStopMode
 | TRACE_IOEN | LL_DBGMCU_GetTracePinAssignment
 |  | LL_DBGMCU_SetTracePinAssignment
 | TRACE_MODE | LL_DBGMCU_GetTracePinAssignment
 |  | LL_DBGMCU_SetTracePinAssignment
DBGMCU_CR_APB1 | DBG_CAN1_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_CAN2_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_I2C1_SMBUS_TIMEOUT | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_I2C2_SMBUS_TIMEOUT | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_IWDG_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_RTC_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM12_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM13_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM14_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM2_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM3_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM4_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM5_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM6_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_TIM7_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
 | DBG_WWDG_STOP | LL_DBGMCU_APB1_GRP1_FreezePeriph
 |  | LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB2 | DBG_TIM10_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 | DBG_TIM11_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 | DBG_TIM15_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 | DBG_TIM16_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 | DBG_TIM17_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 | DBG_TIM1_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 | DBG_TIM8_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
 | DBG_TIM9_STOP | LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_IDCODE | DEV_ID | LL_DBGMCU_GetDeviceID
 | REV_ID | LL_DBGMCU_GetRevisionID
FLASH_ACR | HLFCYA | LL_FLASH_DisableHalfCycleAccess
 |  | LL_FLASH_EnableHalfCycleAccess
 |  | LL_FLASH_IsHalfCycleAccessEnabled
 | LATENCY | LL_FLASH_GetLatency
 |  | LL_FLASH_SetLatency
 | PRFTBE | LL_FLASH_DisablePrefetch
 |  | LL_FLASH_EnablePrefetch
 | PRFTBS | LL_FLASH_IsPrefetchEnabled
Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SYSTEM Private Constants

SYSTEM Private Constants
SYSTEM
Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DBGMCU TRACE Pin Assignment

Defines
DBGMCU TRACE Pin Assignment
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_TRACE_NONE 0x00000000U
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)

Define Documentation

#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN

TRACE pin assignment for Asynchronous Mode

Definition at line 97 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_TRACE_NONE 0x00000000U

TRACE pins not assigned (default state)

Definition at line 96 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1

Definition at line 98 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2

Definition at line 99 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)

TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4

Definition at line 100 of file stm32f1xx_ll_system.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DBGMCU APB1 GRP1 STOP IP

Defines
DBGMCU APB1 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_CR_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_STOP
#define | LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP

Define Documentation

#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP

CAN1 debug stopped when Core is halted

Definition at line 135 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_STOP

I2C1 SMBUS timeout mode stopped when Core is halted

Definition at line 132 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_STOP

I2C2 SMBUS timeout mode stopped when Core is halted

Definition at line 133 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP

Debug Independent Watchdog stopped when Core is halted

Definition at line 131 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_CR_DBG_RTC_STOP

RTC counter stopped when core is halted

Definition at line 129 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP

TIM2 counter stopped when core is halted

Definition at line 108 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP

TIM3 counter stopped when core is halted

Definition at line 109 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP

TIM4 counter stopped when core is halted

Definition at line 110 of file stm32f1xx_ll_system.h.

#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP

Debug Window Watchdog stopped when Core is halted

Definition at line 130 of file stm32f1xx_ll_system.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DBGMCU APB2 GRP1 STOP IP

Defines
DBGMCU APB2 GRP1 STOP IP
SYSTEM Exported Constants

Defines

#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP

Define Documentation

#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP

TIM1 counter stopped when core is halted

Definition at line 147 of file stm32f1xx_ll_system.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH LATENCY

Defines
FLASH LATENCY
SYSTEM Exported Constants

Defines

#define | LL_FLASH_LATENCY_0 0x00000000U
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

Define Documentation

#define LL_FLASH_LATENCY_0 0x00000000U

FLASH Zero Latency cycle

Definition at line 177 of file stm32f1xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0

FLASH One Latency cycle

Definition at line 178 of file stm32f1xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

FLASH Two wait states

Definition at line 179 of file stm32f1xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DBGMCU

Functions
DBGMCU
SYSTEM Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_SetTracePinAssignment (uint32_t PinAssignment)
Set Trace pin assignment control.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetTracePinAssignment (void)
Get Trace pin assignment control.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.

Function Documentation

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP
  • LL_DBGMCU_APB1_GRP1_TIM12_STOP
  • LL_DBGMCU_APB1_GRP1_TIM13_STOP
  • LL_DBGMCU_APB1_GRP1_TIM14_STOP
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP
  • LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
  • LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 366 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB1 peripherals (group1 peripherals)

Reference Manual to LL API cross reference:
DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP
  • LL_DBGMCU_APB1_GRP1_TIM5_STOP
  • LL_DBGMCU_APB1_GRP1_TIM6_STOP
  • LL_DBGMCU_APB1_GRP1_TIM7_STOP
  • LL_DBGMCU_APB1_GRP1_TIM12_STOP
  • LL_DBGMCU_APB1_GRP1_TIM13_STOP
  • LL_DBGMCU_APB1_GRP1_TIM14_STOP
  • LL_DBGMCU_APB1_GRP1_RTC_STOP
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP
  • LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
  • LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 410 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph ( uint32_t Periphs )

Freeze APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 438 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph ( uint32_t Periphs )

Unfreeze APB2 peripherals.

Reference Manual to LL API cross reference:
DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
Parameters:
Periphs This parameter can be a combination of the following values:
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP
  • LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
  • LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
(*) value not defined in all devices.
Return values:
None

Definition at line 466 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
Return values:
None

Definition at line 249 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
Return values:
None

Definition at line 289 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
Return values:
None

Definition at line 269 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
Return values:
None

Definition at line 239 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
Return values:
None

Definition at line 279 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode.

Reference Manual to LL API cross reference:
DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
Return values:
None

Definition at line 259 of file stm32f1xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID ( void )

Return the device identifier.

Note:
For Low Density devices, the device ID is 0x412
For Medium Density devices, the device ID is 0x410
For High Density devices, the device ID is 0x414
For XL Density devices, the device ID is 0x430
For Connectivity Line devices, the device ID is 0x418
Reference Manual to LL API cross reference:
DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFF

Definition at line 213 of file stm32f1xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID ( void )

Return the device revision identifier.

Note:
This field indicates the revision of the device. For example, it is read as revA -> 0x1000,for Low Density devices For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices For example, it is read as revA or 1 -> 0x1003,for XL Density devices For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
Reference Manual to LL API cross reference:
DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
Return values:
Values between Min_Data=0x00 and Max_Data=0xFFFF

Definition at line 229 of file stm32f1xx_ll_system.h.

__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment ( void )

Get Trace pin assignment control.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment
DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
Return values:
Returned value can be one of the following values:
  • LL_DBGMCU_TRACE_NONE
  • LL_DBGMCU_TRACE_ASYNCH
  • LL_DBGMCU_TRACE_SYNCH_SIZE1
  • LL_DBGMCU_TRACE_SYNCH_SIZE2
  • LL_DBGMCU_TRACE_SYNCH_SIZE4

Definition at line 322 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment ( uint32_t PinAssignment )

Set Trace pin assignment control.

Reference Manual to LL API cross reference:
DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment
DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
Parameters:
PinAssignment This parameter can be one of the following values:
  • LL_DBGMCU_TRACE_NONE
  • LL_DBGMCU_TRACE_ASYNCH
  • LL_DBGMCU_TRACE_SYNCH_SIZE1
  • LL_DBGMCU_TRACE_SYNCH_SIZE2
  • LL_DBGMCU_TRACE_SYNCH_SIZE4
Return values:
None

Definition at line 306 of file stm32f1xx_ll_system.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH

Functions
FLASH
SYSTEM Exported Functions

Functions

__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.
__STATIC_INLINE void | LL_FLASH_EnableHalfCycleAccess (void)
Enable Flash Half Cycle Access.
__STATIC_INLINE void | LL_FLASH_DisableHalfCycleAccess (void)
Disable Flash Half Cycle Access.
__STATIC_INLINE uint32_t | LL_FLASH_IsHalfCycleAccessEnabled (void)
Check if Flash Half Cycle Access is enabled or not.

Function Documentation

__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess ( void )

Disable Flash Half Cycle Access.

Reference Manual to LL API cross reference:
FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
Return values:
None

Definition at line 552 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_DisablePrefetch ( void )

Disable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
Return values:
None

Definition at line 521 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess ( void )

Enable Flash Half Cycle Access.

Reference Manual to LL API cross reference:
FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
Return values:
None

Definition at line 542 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_EnablePrefetch ( void )

Enable Prefetch.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
Return values:
None

Definition at line 511 of file stm32f1xx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_GetLatency ( void )

Get FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_GetLatency
Return values:
Returned value can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2

Definition at line 501 of file stm32f1xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled ( void )

Check if Flash Half Cycle Access is enabled or not.

Reference Manual to LL API cross reference:
FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
Return values:
State of bit (1 or 0).

Definition at line 562 of file stm32f1xx_ll_system.h.

__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled ( void )

Check if Prefetch buffer is enabled.

Reference Manual to LL API cross reference:
FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
Return values:
State of bit (1 or 0).

Definition at line 531 of file stm32f1xx_ll_system.h.

__STATIC_INLINE void LL_FLASH_SetLatency ( uint32_t Latency )

Set FLASH Latency.

Reference Manual to LL API cross reference:
FLASH_ACR LATENCY LL_FLASH_SetLatency
Parameters:
Latency This parameter can be one of the following values:
  • LL_FLASH_LATENCY_0
  • LL_FLASH_LATENCY_1
  • LL_FLASH_LATENCY_2
Return values:
None

Definition at line 488 of file stm32f1xx_ll_system.h.

Referenced by UTILS_SetFlashLatency().

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM

Modules
TIM
STM32F1xx_LL_Driver

Modules

TIM Private Functions

Private functions.

TIM Private Variables
TIM Private Constants
TIM Private Macros
TIM Exported Init structure
TIM Exported Constants
TIM Exported Macros
TIM Exported Functions
FLAG-Management
IT-Management
DMA-Management
EVENT-Management
Initialisation and deinitialisation functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for TIM registers.

Register | Bit | Function
ARR | ARR | LL_TIM_GetAutoReload
 |  | LL_TIM_SetAutoReload
BDTR | AOE | LL_TIM_DisableAutomaticOutput
 |  | LL_TIM_EnableAutomaticOutput
 |  | LL_TIM_IsEnabledAutomaticOutput
 | BKE | LL_TIM_DisableBRK
 |  | LL_TIM_EnableBRK
 | BKP | LL_TIM_ConfigBRK
 | DTG | LL_TIM_OC_SetDeadTime
 | LOCK | LL_TIM_CC_SetLockLevel
 | MOE | LL_TIM_DisableAllOutputs
 |  | LL_TIM_EnableAllOutputs
 |  | LL_TIM_IsEnabledAllOutputs
 | OSSI | LL_TIM_SetOffStates
 | OSSR | LL_TIM_SetOffStates
CCER | CC1E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC1NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC1NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC1P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC2E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC2NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC2NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC2P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC3E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC3NE | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC3NP | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC3P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
 | CC4E | LL_TIM_CC_DisableChannel
 |  | LL_TIM_CC_EnableChannel
 |  | LL_TIM_CC_IsEnabledChannel
 | CC4P | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPolarity
 |  | LL_TIM_IC_SetPolarity
 |  | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetPolarity
 |  | LL_TIM_OC_SetPolarity
CCMR1 | CC1S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | CC2S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | IC1F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC1PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | IC2F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC2PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | OC1CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC1FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC1M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC1PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
 | OC2CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC2FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC2M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC2PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
CCMR2 | CC3S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | CC4S | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetActiveInput
 |  | LL_TIM_IC_SetActiveInput
 |  | LL_TIM_OC_ConfigOutput
 | IC3F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC3PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | IC4F | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetFilter
 |  | LL_TIM_IC_SetFilter
 | IC4PSC | LL_TIM_IC_Config
 |  | LL_TIM_IC_GetPrescaler
 |  | LL_TIM_IC_SetPrescaler
 | OC3CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC3FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC3M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC3PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
 | OC4CE | LL_TIM_OC_DisableClear
 |  | LL_TIM_OC_EnableClear
 |  | LL_TIM_OC_IsEnabledClear
 | OC4FE | LL_TIM_OC_DisableFast
 |  | LL_TIM_OC_EnableFast
 |  | LL_TIM_OC_IsEnabledFast
 | OC4M | LL_TIM_OC_GetMode
 |  | LL_TIM_OC_SetMode
 | OC4PE | LL_TIM_OC_DisablePreload
 |  | LL_TIM_OC_EnablePreload
 |  | LL_TIM_OC_IsEnabledPreload
CCR1 | CCR1 | LL_TIM_IC_GetCaptureCH1
 |  | LL_TIM_OC_GetCompareCH1
 |  | LL_TIM_OC_SetCompareCH1
CCR2 | CCR2 | LL_TIM_IC_GetCaptureCH2
 |  | LL_TIM_OC_GetCompareCH2
 |  | LL_TIM_OC_SetCompareCH2
CCR3 | CCR3 | LL_TIM_IC_GetCaptureCH3
 |  | LL_TIM_OC_GetCompareCH3
 |  | LL_TIM_OC_SetCompareCH3
CCR4 | CCR4 | LL_TIM_IC_GetCaptureCH4
 |  | LL_TIM_OC_GetCompareCH4
 |  | LL_TIM_OC_SetCompareCH4
CNT | CNT | LL_TIM_GetCounter
 |  | LL_TIM_SetCounter
CR1 | ARPE | LL_TIM_DisableARRPreload
 |  | LL_TIM_EnableARRPreload
 |  | LL_TIM_IsEnabledARRPreload
 | CEN | LL_TIM_DisableCounter
 |  | LL_TIM_EnableCounter
 |  | LL_TIM_IsEnabledCounter
 | CKD | LL_TIM_GetClockDivision
 |  | LL_TIM_SetClockDivision
 | CMS | LL_TIM_GetCounterMode
 |  | LL_TIM_SetCounterMode
 | DIR | LL_TIM_GetCounterMode
 |  | LL_TIM_GetDirection
 |  | LL_TIM_SetCounterMode
 | OPM | LL_TIM_GetOnePulseMode
 |  | LL_TIM_SetOnePulseMode
 | UDIS | LL_TIM_DisableUpdateEvent
 |  | LL_TIM_EnableUpdateEvent
 |  | LL_TIM_IsEnabledUpdateEvent
 | URS | LL_TIM_GetUpdateSource
 |  | LL_TIM_SetUpdateSource
CR2 | CCDS | LL_TIM_CC_GetDMAReqTrigger
 |  | LL_TIM_CC_SetDMAReqTrigger
 | CCPC | LL_TIM_CC_DisablePreload
 |  | LL_TIM_CC_EnablePreload
 | CCUS | LL_TIM_CC_SetUpdate
 | MMS | LL_TIM_SetTriggerOutput
 | OIS1 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS1N | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS2 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS2N | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS3 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS3N | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | OIS4 | LL_TIM_OC_ConfigOutput
 |  | LL_TIM_OC_GetIdleState
 |  | LL_TIM_OC_SetIdleState
 | TI1S | LL_TIM_IC_DisableXORCombination
 |  | LL_TIM_IC_EnableXORCombination
 |  | LL_TIM_IC_IsEnabledXORCombination
DCR | DBA | LL_TIM_ConfigDMABurst
 | DBL | LL_TIM_ConfigDMABurst
DIER | BIE | LL_TIM_DisableIT_BRK
 |  | LL_TIM_EnableIT_BRK
 |  | LL_TIM_IsEnabledIT_BRK
 | CC1DE | LL_TIM_DisableDMAReq_CC1
 |  | LL_TIM_EnableDMAReq_CC1
 |  | LL_TIM_IsEnabledDMAReq_CC1
 | CC1IE | LL_TIM_DisableIT_CC1
 |  | LL_TIM_EnableIT_CC1
 |  | LL_TIM_IsEnabledIT_CC1
 | CC2DE | LL_TIM_DisableDMAReq_CC2
 |  | LL_TIM_EnableDMAReq_CC2
 |  | LL_TIM_IsEnabledDMAReq_CC2
 | CC2IE | LL_TIM_DisableIT_CC2
 |  | LL_TIM_EnableIT_CC2
 |  | LL_TIM_IsEnabledIT_CC2
 | CC3DE | LL_TIM_DisableDMAReq_CC3
 |  | LL_TIM_EnableDMAReq_CC3
 |  | LL_TIM_IsEnabledDMAReq_CC3
 | CC3IE | LL_TIM_DisableIT_CC3
 |  | LL_TIM_EnableIT_CC3
 |  | LL_TIM_IsEnabledIT_CC3
 | CC4DE | LL_TIM_DisableDMAReq_CC4
 |  | LL_TIM_EnableDMAReq_CC4
 |  | LL_TIM_IsEnabledDMAReq_CC4
 | CC4IE | LL_TIM_DisableIT_CC4
 |  | LL_TIM_EnableIT_CC4
 |  | LL_TIM_IsEnabledIT_CC4
 | COMDE | LL_TIM_DisableDMAReq_COM
 |  | LL_TIM_EnableDMAReq_COM
 |  | LL_TIM_IsEnabledDMAReq_COM
 | COMIE | LL_TIM_DisableIT_COM
 |  | LL_TIM_EnableIT_COM
 |  | LL_TIM_IsEnabledIT_COM
 | TDE | LL_TIM_DisableDMAReq_TRIG
 |  | LL_TIM_EnableDMAReq_TRIG
 |  | LL_TIM_IsEnabledDMAReq_TRIG
 | TIE | LL_TIM_DisableIT_TRIG
 |  | LL_TIM_EnableIT_TRIG
 |  | LL_TIM_IsEnabledIT_TRIG
 | UDE | LL_TIM_DisableDMAReq_UPDATE
 |  | LL_TIM_EnableDMAReq_UPDATE
 |  | LL_TIM_IsEnabledDMAReq_UPDATE
 | UIE | LL_TIM_DisableIT_UPDATE
 |  | LL_TIM_EnableIT_UPDATE
 |  | LL_TIM_IsEnabledIT_UPDATE
EGR | BG | LL_TIM_GenerateEvent_BRK
 | CC1G | LL_TIM_GenerateEvent_CC1
 | CC2G | LL_TIM_GenerateEvent_CC2
 | CC3G | LL_TIM_GenerateEvent_CC3
 | CC4G | LL_TIM_GenerateEvent_CC4
 | COMG | LL_TIM_GenerateEvent_COM
 | TG | LL_TIM_GenerateEvent_TRIG
 | UG | LL_TIM_GenerateEvent_UPDATE
PSC | PSC | LL_TIM_GetPrescaler
 |  | LL_TIM_SetPrescaler
RCR | REP | LL_TIM_GetRepetitionCounter
 |  | LL_TIM_SetRepetitionCounter
SMCR | ECE | LL_TIM_DisableExternalClock
 |  | LL_TIM_EnableExternalClock
 |  | LL_TIM_IsEnabledExternalClock
 |  | LL_TIM_SetClockSource
 | ETF | LL_TIM_ConfigETR
 | ETP | LL_TIM_ConfigETR
 | ETPS | LL_TIM_ConfigETR
 | MSM | LL_TIM_DisableMasterSlaveMode
 |  | LL_TIM_EnableMasterSlaveMode
 |  | LL_TIM_IsEnabledMasterSlaveMode
 | SMS | LL_TIM_SetClockSource
 |  | LL_TIM_SetEncoderMode
 |  | LL_TIM_SetSlaveMode
 | TS | LL_TIM_SetTriggerInput
SR | BIF | LL_TIM_ClearFlag_BRK
 |  | LL_TIM_IsActiveFlag_BRK
 | CC1IF | LL_TIM_ClearFlag_CC1
 |  | LL_TIM_IsActiveFlag_CC1
 | CC1OF | LL_TIM_ClearFlag_CC1OVR
 |  | LL_TIM_IsActiveFlag_CC1OVR
 | CC2IF | LL_TIM_ClearFlag_CC2
 |  | LL_TIM_IsActiveFlag_CC2
 | CC2OF | LL_TIM_ClearFlag_CC2OVR
 |  | LL_TIM_IsActiveFlag_CC2OVR
 | CC3IF | LL_TIM_ClearFlag_CC3
 |  | LL_TIM_IsActiveFlag_CC3
 | CC3OF | LL_TIM_ClearFlag_CC3OVR
 |  | LL_TIM_IsActiveFlag_CC3OVR
 | CC4IF | LL_TIM_ClearFlag_CC4
 |  | LL_TIM_IsActiveFlag_CC4
 | CC4OF | LL_TIM_ClearFlag_CC4OVR
 |  | LL_TIM_IsActiveFlag_CC4OVR
 | COMIF | LL_TIM_ClearFlag_COM
 |  | LL_TIM_IsActiveFlag_COM
 | TIF | LL_TIM_ClearFlag_TRIG
 |  | LL_TIM_IsActiveFlag_TRIG
 | UIF | LL_TIM_ClearFlag_UPDATE
 |  | LL_TIM_IsActiveFlag_UPDATE
Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Private functions. More...

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.

Detailed Description

Private functions.

Function Documentation

static ErrorStatus IC1Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 1.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1075 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC2Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 2.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1108 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC3Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 3.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1141 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus IC4Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_IC_InitTypeDef * | TIM_ICInitStruct
 | ) |  | [static]

Configure the TIMx input channel 4.

Parameters:
TIMx | Timer Instance
TIM_ICInitStruct | pointer to the the TIMx input channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1174 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY, and IS_LL_TIM_ICPSC.

Referenced by LL_TIM_IC_Init().

static ErrorStatus OC1Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 1.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 1 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 767 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH1(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC2Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 2.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 2 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 846 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH2(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC3Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 3.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 3 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 925 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH3(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

static ErrorStatus OC4Config | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OCInitStruct
 | ) |  | [static]

Configure the TIMx output channel 4.

Parameters:
TIMx | Timer Instance
TIM_OCInitStruct | pointer to the the TIMx output channel 4 configuration data structure
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 1004 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_OC_InitTypeDef::CompareValue, IS_LL_TIM_OCIDLESTATE, IS_LL_TIM_OCMODE, IS_LL_TIM_OCPOLARITY, IS_LL_TIM_OCSTATE, LL_TIM_OC_SetCompareCH4(), LL_TIM_ReadReg, LL_TIM_WriteReg, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

Referenced by LL_TIM_OC_Init().

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Private Variables

Variables
TIM Private Variables
TIM

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Variable Documentation

const uint8_t OFFSET_TAB_CCMRx[] [static]
Initial value:
{
  0x00U,
  0x00U,
  0x00U,
  0x00U,
  0x04U,
  0x04U,
  0x04U
}

Definition at line 64 of file stm32f1xx_ll_tim.h.

const uint8_t SHIFT_TAB_CCxP[] [static]
Initial value:
{
  0U,
  2U,
  4U,
  6U,
  8U,
  10U,
  12U
}

Definition at line 97 of file stm32f1xx_ll_tim.h.

const uint8_t SHIFT_TAB_ICxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U
}

Definition at line 86 of file stm32f1xx_ll_tim.h.

const uint8_t SHIFT_TAB_OCxx[] [static]
Initial value:
{
  0U,
  0U,
  8U,
  0U,
  0U,
  0U,
  8U
}

Definition at line 75 of file stm32f1xx_ll_tim.h.

const uint8_t SHIFT_TAB_OISx[] [static]
Initial value:
{
  0U,
  1U,
  2U,
  3U,
  4U,
  5U,
  6U
}

Definition at line 108 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | DT_DELAY_1 ((uint8_t)0x7FU)
#define | DT_DELAY_2 ((uint8_t)0x3FU)
#define | DT_DELAY_3 ((uint8_t)0x1FU)
#define | DT_DELAY_4 ((uint8_t)0x1FU)
#define | DT_RANGE_1 ((uint8_t)0x00U)
#define | DT_RANGE_2 ((uint8_t)0x80U)
#define | DT_RANGE_3 ((uint8_t)0xC0U)
#define | DT_RANGE_4 ((uint8_t)0xE0U)

Define Documentation

#define DT_DELAY_1 ((uint8_t)0x7FU)

Definition at line 131 of file stm32f1xx_ll_tim.h.

#define DT_DELAY_2 ((uint8_t)0x3FU)

Definition at line 132 of file stm32f1xx_ll_tim.h.

#define DT_DELAY_3 ((uint8_t)0x1FU)

Definition at line 133 of file stm32f1xx_ll_tim.h.

#define DT_DELAY_4 ((uint8_t)0x1FU)

Definition at line 134 of file stm32f1xx_ll_tim.h.

#define DT_RANGE_1 ((uint8_t)0x00U)

Definition at line 137 of file stm32f1xx_ll_tim.h.

#define DT_RANGE_2 ((uint8_t)0x80U)

Definition at line 138 of file stm32f1xx_ll_tim.h.

#define DT_RANGE_3 ((uint8_t)0xC0U)

Definition at line 139 of file stm32f1xx_ll_tim.h.

#define DT_RANGE_4 ((uint8_t)0xE0U)

Definition at line 140 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).

Define Documentation

#define IS_LL_TIM_ACTIVEINPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
                                       || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
                                       || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))

Definition at line 94 of file stm32f1xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_ENCODER_Init().

#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
                                                  || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))

Definition at line 147 of file stm32f1xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
                                          || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))

Definition at line 144 of file stm32f1xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_BREAK_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_BREAK_DISABLE) \
                                       || ((__VALUE__) == LL_TIM_BREAK_ENABLE))

Definition at line 141 of file stm32f1xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_CLOCKDIVISION ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
                                         || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
                                         || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))

Definition at line 72 of file stm32f1xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_COUNTERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
                                       || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))

Definition at line 66 of file stm32f1xx_ll_tim.c.

Referenced by LL_TIM_Init().

#define IS_LL_TIM_ENCODERMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
                                       || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
                                       || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))

Definition at line 123 of file stm32f1xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init().

#define IS_LL_TIM_IC_FILTER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
                                     || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))

Definition at line 103 of file stm32f1xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_IC_POLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                       || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))

Definition at line 120 of file stm32f1xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), and IC4Config().

#define IS_LL_TIM_IC_POLARITY_ENCODER ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
                                               || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))

Definition at line 127 of file stm32f1xx_ll_tim.c.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_ICPSC ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_ICPSC_DIV1) \
                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
                                 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))

Definition at line 98 of file stm32f1xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_ENCODER_Init(), and LL_TIM_HALLSENSOR_Init().

#define IS_LL_TIM_LOCK_LEVEL ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
                                      || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))

Definition at line 136 of file stm32f1xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OCIDLESTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
                                       || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))

Definition at line 91 of file stm32f1xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), and OC4Config().

#define IS_LL_TIM_OCMODE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
                                  || ((__VALUE__) == LL_TIM_OCMODE_PWM2))

Definition at line 76 of file stm32f1xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), and OC4Config().

#define IS_LL_TIM_OCPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
                                      || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))

Definition at line 88 of file stm32f1xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), and OC4Config().

#define IS_LL_TIM_OCSTATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
                                   || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))

Definition at line 85 of file stm32f1xx_ll_tim.c.

Referenced by OC1Config(), OC2Config(), OC3Config(), and OC4Config().

#define IS_LL_TIM_OSSI_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSI_DISABLE) \
                                      || ((__VALUE__) == LL_TIM_OSSI_ENABLE))

Definition at line 133 of file stm32f1xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define IS_LL_TIM_OSSR_STATE ( __VALUE__ )
Value:
(((__VALUE__) == LL_TIM_OSSR_DISABLE) \
                                     || ((__VALUE__) == LL_TIM_OSSR_ENABLE))

Definition at line 130 of file stm32f1xx_ll_tim.c.

Referenced by LL_TIM_BDTR_Init().

#define TIM_CALC_DTS | ( | __TIMCLK__,
 |  | __CKD__
 | ) |
Value:
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
     ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
     ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))

Calculate the deadtime sampling period(in ps).

Parameters:
__TIMCLK__ timer input clock frequency (in Hz).
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
none

Definition at line 178 of file stm32f1xx_ll_tim.h.

#define TIM_GET_CHANNEL_INDEX ( __CHANNEL__ )
Value:
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)

Convert channel id into channel index.

Parameters:
__CHANNEL__ This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
Return values:
none

Definition at line 162 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_IC_Config(), LL_TIM_IC_GetActiveInput(), LL_TIM_IC_GetFilter(), LL_TIM_IC_GetPolarity(), LL_TIM_IC_GetPrescaler(), LL_TIM_IC_SetActiveInput(), LL_TIM_IC_SetFilter(), LL_TIM_IC_SetPolarity(), LL_TIM_IC_SetPrescaler(), LL_TIM_OC_ConfigOutput(), LL_TIM_OC_DisableClear(), LL_TIM_OC_DisableFast(), LL_TIM_OC_DisablePreload(), LL_TIM_OC_EnableClear(), LL_TIM_OC_EnableFast(), LL_TIM_OC_EnablePreload(), LL_TIM_OC_GetIdleState(), LL_TIM_OC_GetMode(), LL_TIM_OC_GetPolarity(), LL_TIM_OC_IsEnabledClear(), LL_TIM_OC_IsEnabledFast(), LL_TIM_OC_IsEnabledPreload(), LL_TIM_OC_SetIdleState(), LL_TIM_OC_SetMode(), and LL_TIM_OC_SetPolarity().

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_TIM_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Time Base configuration structure definition. More...

#include <stm32f1xx_ll_tim.h>

Data Fields

uint16_t | Prescaler
uint32_t | CounterMode
uint32_t | Autoreload
uint32_t | ClockDivision
uint8_t | RepetitionCounter

Detailed Description

TIM Time Base configuration structure definition.

Definition at line 196 of file stm32f1xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_InitTypeDef::Autoreload

Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetAutoReload().

Definition at line 208 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of Clock Division.

This feature can be modified afterwards using unitary function LL_TIM_SetClockDivision().

Definition at line 215 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint32_t LL_TIM_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of Counter Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetCounterMode().

Definition at line 203 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint16_t LL_TIM_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_SetPrescaler().

Definition at line 198 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

uint8_t LL_TIM_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between 0x00 and 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_SetRepetitionCounter().

Definition at line 220 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_Init(), and LL_TIM_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_OC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Output Compare configuration structure definition. More...

#include <stm32f1xx_ll_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | OCState
uint32_t | OCNState
uint32_t | CompareValue
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare configuration structure definition.

Definition at line 234 of file stm32f1xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_OC_InitTypeDef::CompareValue

Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).

Definition at line 251 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 267 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCMode

Specifies the output mode. This parameter can be a value of Output Configuration Mode.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetMode().

Definition at line 236 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of Output Configuration Idle State.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetIdleState().

Definition at line 272 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 261 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCNState

Specifies the TIM complementary Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 246 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of Output Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetPolarity().

Definition at line 256 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

uint32_t LL_TIM_OC_InitTypeDef::OCState

Specifies the TIM Output Compare state. This parameter can be a value of Output Configuration State.

This feature can be modified afterwards using unitary functions LL_TIM_CC_EnableChannel() or LL_TIM_CC_DisableChannel().

Definition at line 241 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_IC_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Input Capture configuration structure definition. More...

#include <stm32f1xx_ll_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICActiveInput
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture configuration structure definition.

Definition at line 282 of file stm32f1xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_IC_InitTypeDef::ICActiveInput

Specifies the input. This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 290 of file stm32f1xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 300 of file stm32f1xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 285 of file stm32f1xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

uint32_t LL_TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 295 of file stm32f1xx_ll_tim.h.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), and LL_TIM_IC_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_TIM_ENCODER_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_ENCODER_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Encoder interface configuration structure definition. More...

#include <stm32f1xx_ll_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1ActiveInput
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2ActiveInput
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder interface configuration structure definition.

Definition at line 310 of file stm32f1xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_ENCODER_InitTypeDef::EncoderMode

Specifies the encoder resolution (x2 or x4). This parameter can be a value of Encoder Mode.

This feature can be modified afterwards using unitary function LL_TIM_SetEncoderMode().

Definition at line 312 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput

Specifies the TI1 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 322 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 332 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 317 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 327 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput

Specifies the TI2 input source This parameter can be a value of Active Input Selection.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetActiveInput().

Definition at line 342 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Filter

Specifies the TI2 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 352 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Polarity

Specifies the active edge of TI2 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 337 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

uint32_t LL_TIM_ENCODER_InitTypeDef::IC2Prescaler

Specifies the TI2 input prescaler value. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 347 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), and LL_TIM_ENCODER_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_TIM_HALLSENSOR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_HALLSENSOR_InitTypeDef Struct Reference
TIM Exported Init structure

TIM Hall sensor interface configuration structure definition. More...

#include <stm32f1xx_ll_tim.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | CommutationDelay

Detailed Description

TIM Hall sensor interface configuration structure definition.

Definition at line 362 of file stm32f1xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay

Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCH2().

Definition at line 382 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter

Specifies the TI1 input filter. This parameter can be a value of Input Configuration Filter.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetFilter().

Definition at line 377 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity

Specifies the active edge of TI1 input. This parameter can be a value of Input Configuration Polarity.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPolarity().

Definition at line 365 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

uint32_t LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler

Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of Input Configuration Prescaler.

This feature can be modified afterwards using unitary function LL_TIM_IC_SetPrescaler().

Definition at line 370 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and LL_TIM_HALLSENSOR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_TIM_BDTR_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_TIM_BDTR_InitTypeDef Struct Reference
TIM Exported Init structure

BDTR (Break and Dead Time) structure definition. More...

#include <stm32f1xx_ll_tim.h>

Data Fields

uint32_t | OSSRState
uint32_t | OSSIState
uint32_t | LockLevel
uint8_t | DeadTime
uint16_t | BreakState
uint32_t | BreakPolarity
uint32_t | AutomaticOutput

Detailed Description

BDTR (Break and Dead Time) structure definition.

Definition at line 393 of file stm32f1xx_ll_tim.h.

Field Documentation

uint32_t LL_TIM_BDTR_InitTypeDef::AutomaticOutput

Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of Automatic output enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableAutomaticOutput() or LL_TIM_DisableAutomaticOutput()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 437 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::BreakPolarity

Specifies the TIM Break Input pin polarity. This parameter can be a value of break polarity

This feature can be modified afterwards using unitary function LL_TIM_ConfigBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 430 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint16_t LL_TIM_BDTR_InitTypeDef::BreakState

Specifies whether the TIM Break input is enabled or not. This parameter can be a value of Break Enable

This feature can be modified afterwards using unitary functions LL_TIM_EnableBRK() or LL_TIM_DisableBRK()

Note:
This bit-field can not be modified as long as LOCK level 1 has been programmed.

Definition at line 423 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint8_t LL_TIM_BDTR_InitTypeDef::DeadTime

Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.

This feature can be modified afterwards using unitary function LL_TIM_OC_SetDeadTime()

Note:
This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed.

Definition at line 415 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::LockLevel

Specifies the LOCK level parameters. This parameter can be a value of Lock Level

Note:
The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

Definition at line 409 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSIState

Specifies the Off-State used in Idle state. This parameter can be a value of OSSI

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 402 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

uint32_t LL_TIM_BDTR_InitTypeDef::OSSRState

Specifies the Off-State selection used in Run mode. This parameter can be a value of OSSR

This feature can be modified afterwards using unitary function LL_TIM_SetOffStates()

Note:
This bit-field cannot be modified as long as LOCK level 2 has been programmed.

Definition at line 395 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), and LL_TIM_BDTR_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
TIM Exported Constants

Flags defines which can be used with LL_TIM_ReadReg function. More...

Defines

#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF

Detailed Description

Flags defines which can be used with LL_TIM_ReadReg function.

Define Documentation

#define LL_TIM_SR_BIF TIM_SR_BIF

Break interrupt flag

Definition at line 466 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_CC1IF TIM_SR_CC1IF

Capture/compare 1 interrupt flag

Definition at line 460 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_CC1OF TIM_SR_CC1OF

Capture/Compare 1 overcapture flag

Definition at line 467 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_CC2IF TIM_SR_CC2IF

Capture/compare 2 interrupt flag

Definition at line 461 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_CC2OF TIM_SR_CC2OF

Capture/Compare 2 overcapture flag

Definition at line 468 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_CC3IF TIM_SR_CC3IF

Capture/compare 3 interrupt flag

Definition at line 462 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_CC3OF TIM_SR_CC3OF

Capture/Compare 3 overcapture flag

Definition at line 469 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_CC4IF TIM_SR_CC4IF

Capture/compare 4 interrupt flag

Definition at line 463 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_CC4OF TIM_SR_CC4OF

Capture/Compare 4 overcapture flag

Definition at line 470 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_COMIF TIM_SR_COMIF

COM interrupt flag

Definition at line 464 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_TIF TIM_SR_TIF

Trigger interrupt flag

Definition at line 465 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SR_UIF TIM_SR_UIF

Update interrupt flag

Definition at line 459 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Break Enable

Defines
Break Enable
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Define Documentation

#define LL_TIM_BREAK_DISABLE 0x00000000U

Break function disabled

Definition at line 479 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE

Break function enabled

Definition at line 480 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Automatic output enable

Defines
Automatic output enable
TIM Exported Constants

Defines

#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

Define Documentation

#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

MOE can be set only by software

Definition at line 488 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE

MOE can be set by software or automatically at the next update event

Definition at line 489 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: IT Defines

Defines
IT Defines
TIM Exported Constants

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. More...

Defines

#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE

Detailed Description

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Define Documentation

#define LL_TIM_DIER_BIE TIM_DIER_BIE

Break interrupt enable

Definition at line 506 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE

Capture/compare 1 interrupt enable

Definition at line 500 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE

Capture/compare 2 interrupt enable

Definition at line 501 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE

Capture/compare 3 interrupt enable

Definition at line 502 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE

Capture/compare 4 interrupt enable

Definition at line 503 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DIER_COMIE TIM_DIER_COMIE

COM interrupt enable

Definition at line 504 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DIER_TIE TIM_DIER_TIE

Trigger interrupt enable

Definition at line 505 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DIER_UIE TIM_DIER_UIE

Update interrupt enable

Definition at line 499 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Update Source

Defines
Update Source
TIM Exported Constants

Defines

#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Define Documentation

#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS

Only counter overflow/underflow generates an update request

Definition at line 515 of file stm32f1xx_ll_tim.h.

#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U

Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request

Definition at line 514 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: One Pulse Mode

Defines
One Pulse Mode
TIM Exported Constants

Defines

#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Define Documentation

#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U

Counter stops counting at the next update event

Definition at line 524 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM

Counter is not stopped at update event

Definition at line 523 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Counter Mode

Defines
Counter Mode
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

Define Documentation

#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up

Definition at line 535 of file stm32f1xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down.

Definition at line 534 of file stm32f1xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS

The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down.

Definition at line 536 of file stm32f1xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Counter used as downcounter

Definition at line 533 of file stm32f1xx_ll_tim.h.

#define LL_TIM_COUNTERMODE_UP 0x00000000U

Counter used as upcounter

Definition at line 532 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

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STM32F103xB HAL User Manual: Clock Division

Defines
Clock Division
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

Define Documentation

#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U

tDTS=tCK_INT

Definition at line 544 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_StructInit().

#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0

tDTS=2*tCK_INT

Definition at line 545 of file stm32f1xx_ll_tim.h.

#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1

tDTS=4*tCK_INT

Definition at line 546 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Counter Direction

Defines
Counter Direction
TIM Exported Constants

Defines

#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Define Documentation

#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR

Timer counter counts down

Definition at line 555 of file stm32f1xx_ll_tim.h.

#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U

Timer counter counts up

Definition at line 554 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Capture Compare Update Source

Defines
Capture Compare Update Source
TIM Exported Constants

Defines

#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Define Documentation

#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS

Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI)

Definition at line 564 of file stm32f1xx_ll_tim.h.

#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U

Capture/compare control bits are updated by setting the COMG bit only

Definition at line 563 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Capture Compare DMA Request

Defines
Capture Compare DMA Request
TIM Exported Constants

Defines

#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

Define Documentation

#define LL_TIM_CCDMAREQUEST_CC 0x00000000U

CCx DMA request sent when CCx event occurs

Definition at line 572 of file stm32f1xx_ll_tim.h.

#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS

CCx DMA requests sent when update event occurs

Definition at line 573 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Lock Level

Defines
Lock Level
TIM Exported Constants

Defines

#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

Define Documentation

#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0

LOCK Level 1

Definition at line 582 of file stm32f1xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1

LOCK Level 2

Definition at line 583 of file stm32f1xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK

LOCK Level 3

Definition at line 584 of file stm32f1xx_ll_tim.h.

#define LL_TIM_LOCKLEVEL_OFF 0x00000000U

LOCK OFF - No bit is write protected

Definition at line 581 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

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STM32F103xB HAL User Manual: Channel

Defines
Channel
TIM Exported Constants

Defines

#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E

Define Documentation

#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E

Timer input/output channel 1

Definition at line 592 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE

Timer complementary output channel 1

Definition at line 593 of file stm32f1xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E

Timer input/output channel 2

Definition at line 594 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE

Timer complementary output channel 2

Definition at line 595 of file stm32f1xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E

Timer input/output channel 3

Definition at line 596 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE

Timer complementary output channel 3

Definition at line 597 of file stm32f1xx_ll_tim.h.

#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E

Timer input/output channel 4

Definition at line 598 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_IC_Init(), and LL_TIM_OC_Init().

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STM32F103xB HAL User Manual: Output Configuration State

Defines
Output Configuration State
TIM Exported Constants

Defines

#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

Define Documentation

#define LL_TIM_OCSTATE_DISABLE 0x00000000U

OCx is not active

Definition at line 607 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E

OCx signal is output on the corresponding output pin

Definition at line 608 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Output Configuration Mode

Defines
Output Configuration Mode
TIM Exported Constants

Defines

#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

Define Documentation

#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0

OCyREF is forced high on compare match

Definition at line 618 of file stm32f1xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)

OCyREF is forced high

Definition at line 622 of file stm32f1xx_ll_tim.h.

#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2

OCyREF is forced low

Definition at line 621 of file stm32f1xx_ll_tim.h.

#define LL_TIM_OCMODE_FROZEN 0x00000000U

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level

Definition at line 617 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1

OCyREF is forced low on compare match

Definition at line 619 of file stm32f1xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)

In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.

Definition at line 623 of file stm32f1xx_ll_tim.h.

#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive

Definition at line 624 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)

OCyREF toggles on compare match

Definition at line 620 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Output Configuration Polarity

Defines
Output Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

Define Documentation

#define LL_TIM_OCPOLARITY_HIGH 0x00000000U

OCxactive high

Definition at line 632 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P

OCxactive low

Definition at line 633 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Output Configuration Idle State

Defines
Output Configuration Idle State
TIM Exported Constants

Defines

#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

Define Documentation

#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1

OCx=1 (after a dead-time if OC is implemented) when MOE=0

Definition at line 642 of file stm32f1xx_ll_tim.h.

#define LL_TIM_OCIDLESTATE_LOW 0x00000000U

OCx=0 (after a dead-time if OC is implemented) when MOE=0

Definition at line 641 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_OC_StructInit().

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STM32F103xB HAL User Manual: Active Input Selection

Defines
Active Input Selection
TIM Exported Constants

Defines

#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

Define Documentation

#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)

ICx is mapped on TIx

Definition at line 651 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)

ICx is mapped on TIy

Definition at line 652 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)

ICx is mapped on TRC

Definition at line 653 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

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STM32F103xB HAL User Manual: Input Configuration Prescaler

Defines
Input Configuration Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Define Documentation

#define LL_TIM_ICPSC_DIV1 0x00000000U

No prescaler, capture is done each time an edge is detected on the capture input

Definition at line 661 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)

Capture is done once every 2 events

Definition at line 662 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)

Capture is done once every 4 events

Definition at line 663 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)

Capture is done once every 8 events

Definition at line 664 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Input Configuration Filter

Defines
Input Configuration Filter
TIM Exported Constants

Defines

#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

Define Documentation

#define LL_TIM_IC_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 672 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/16, N=5

Definition at line 682 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/16, N=6

Definition at line 683 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)

fSAMPLING=fDTS/16, N=8

Definition at line 684 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)

fSAMPLING=fCK_INT, N=2

Definition at line 673 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)

fSAMPLING=fCK_INT, N=4

Definition at line 674 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fCK_INT, N=8

Definition at line 675 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)

fSAMPLING=fDTS/2, N=6

Definition at line 676 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/2, N=8

Definition at line 677 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/32, N=5

Definition at line 685 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/32, N=6

Definition at line 686 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)

fSAMPLING=fDTS/32, N=8

Definition at line 687 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)

fSAMPLING=fDTS/4, N=6

Definition at line 678 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/4, N=8

Definition at line 679 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)

fSAMPLING=fDTS/8, N=6

Definition at line 680 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)

fSAMPLING=fDTS/8, N=8

Definition at line 681 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Input Configuration Polarity

Defines
Input Configuration Polarity
TIM Exported Constants

Defines

#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P

Define Documentation

#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P

The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted

Definition at line 696 of file stm32f1xx_ll_tim.h.

#define LL_TIM_IC_POLARITY_RISING 0x00000000U

The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted

Definition at line 695 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit(), LL_TIM_HALLSENSOR_StructInit(), and LL_TIM_IC_StructInit().

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STM32F103xB HAL User Manual: Clock Source

Defines
Clock Source
TIM Exported Constants

Defines

#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Define Documentation

#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Counter counts at each rising or falling edge on a selected inpu t

Definition at line 705 of file stm32f1xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE

Counter counts at each rising or falling edge on the external trigger input ETR

Definition at line 706 of file stm32f1xx_ll_tim.h.

#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U

The timer is clocked by the internal clock provided from the RCC

Definition at line 704 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Encoder Mode

Defines
Encoder Mode
TIM Exported Constants

Defines

#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0

Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level

Definition at line 714 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_StructInit().

#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1

Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level

Definition at line 715 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l

Definition at line 716 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Trigger Output

Defines
Trigger Output
TIM Exported Constants

Defines

#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

Define Documentation

#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

CC1 capture or a compare match is used as trigger output

Definition at line 727 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0

Counter Enable signal (CNT_EN) is used as trigger output

Definition at line 725 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2

OC1REF signal is used as trigger output

Definition at line 728 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)

OC2REF signal is used as trigger output

Definition at line 729 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)

OC3REF signal is used as trigger output

Definition at line 730 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)

OC4REF signal is used as trigger output

Definition at line 731 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TRGO_RESET 0x00000000U

UG bit from the TIMx_EGR register is used as trigger output

Definition at line 724 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1

Update event is used as trigger output

Definition at line 726 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Slave Mode

Defines
Slave Mode
TIM Exported Constants

Defines

#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Define Documentation

#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U

Slave mode disabled

Definition at line 740 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)

Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high

Definition at line 742 of file stm32f1xx_ll_tim.h.

#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2

Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter

Definition at line 741 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)

Trigger Mode - The counter starts at a rising edge of the trigger TRGI

Definition at line 743 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: Trigger Selection

Defines
Trigger Selection
TIM Exported Constants

Defines

#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Define Documentation

#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)

Filtered external Trigger (ETRF) is used as trigger input

Definition at line 758 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TS_ITR0 0x00000000U

Internal Trigger 0 (ITR0) is used as trigger input

Definition at line 751 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0

Internal Trigger 1 (ITR1) is used as trigger input

Definition at line 752 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1

Internal Trigger 2 (ITR2) is used as trigger input

Definition at line 753 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Internal Trigger 3 (ITR3) is used as trigger input

Definition at line 754 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2

TI1 Edge Detector (TI1F_ED) is used as trigger input

Definition at line 755 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init().

#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)

Filtered Timer Input 1 (TI1FP1) is used as trigger input

Definition at line 756 of file stm32f1xx_ll_tim.h.

#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)

Filtered Timer Input 2 (TI12P2) is used as trigger input

Definition at line 757 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: External Trigger Polarity

Defines
External Trigger Polarity
TIM Exported Constants

Defines

#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

Define Documentation

#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP

ETR is inverted, active at low level or falling edge

Definition at line 767 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U

ETR is non-inverted, active at high level or rising edge

Definition at line 766 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: External Trigger Prescaler

Defines
External Trigger Prescaler
TIM Exported Constants

Defines

#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

Define Documentation

#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U

ETR prescaler OFF

Definition at line 775 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0

ETR frequency is divided by 2

Definition at line 776 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1

ETR frequency is divided by 4

Definition at line 777 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS

ETR frequency is divided by 8

Definition at line 778 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: External Trigger Filter

Defines
External Trigger Filter
TIM Exported Constants

Defines

#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

Define Documentation

#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U

No filter, sampling is done at fDTS

Definition at line 786 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/16, N=6

Definition at line 796 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=8

Definition at line 797 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)

fSAMPLING=fDTS/16, N=5

Definition at line 798 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0

fSAMPLING=fCK_INT, N=2

Definition at line 787 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1

fSAMPLING=fCK_INT, N=4

Definition at line 788 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fCK_INT, N=8

Definition at line 789 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2

fSAMPLING=fDTS/2, N=6

Definition at line 790 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/2, N=8

Definition at line 791 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/32, N=5

Definition at line 799 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/32, N=6

Definition at line 800 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF

fSAMPLING=fDTS/32, N=8

Definition at line 801 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)

fSAMPLING=fDTS/4, N=6

Definition at line 792 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/4, N=8

Definition at line 793 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3

fSAMPLING=fDTS/8, N=8

Definition at line 794 of file stm32f1xx_ll_tim.h.

#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)

fSAMPLING=fDTS/16, N=5

Definition at line 795 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: break polarity

Defines
break polarity
TIM Exported Constants

Defines

#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Define Documentation

#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP

Break input BRK is active high

Definition at line 811 of file stm32f1xx_ll_tim.h.

#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U

Break input BRK is active low

Definition at line 810 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

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STM32F103xB HAL User Manual: OSSI

Defines
OSSI
TIM Exported Constants

Defines

#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

Define Documentation

#define LL_TIM_OSSI_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 822 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI

When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime

Definition at line 823 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: OSSR

Defines
OSSR
TIM Exported Constants

Defines

#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

Define Documentation

#define LL_TIM_OSSR_DISABLE 0x00000000U

When inactive, OCx/OCxN outputs are disabled

Definition at line 831 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_StructInit().

#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR

When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1

Definition at line 832 of file stm32f1xx_ll_tim.h.

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STM32F103xB HAL User Manual: DMA Burst Base Address

Defines
DMA Burst Base Address
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)

Define Documentation

#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_ARR register is the DMA base address for DMA burst

Definition at line 852 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)

TIMx_BDTR register is the DMA base address for DMA burst

Definition at line 858 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3

TIMx_CCER register is the DMA base address for DMA burst

Definition at line 849 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCMR1 register is the DMA base address for DMA burst

Definition at line 847 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCMR2 register is the DMA base address for DMA burst

Definition at line 848 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_CCR1 register is the DMA base address for DMA burst

Definition at line 854 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)

TIMx_CCR2 register is the DMA base address for DMA burst

Definition at line 855 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_CCR3 register is the DMA base address for DMA burst

Definition at line 856 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4

TIMx_CCR4 register is the DMA base address for DMA burst

Definition at line 857 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)

TIMx_CNT register is the DMA base address for DMA burst

Definition at line 850 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U

TIMx_CR1 register is the DMA base address for DMA burst

Definition at line 841 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0

TIMx_CR2 register is the DMA base address for DMA burst

Definition at line 842 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)

TIMx_DIER register is the DMA base address for DMA burst

Definition at line 844 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)

TIMx_EGR register is the DMA base address for DMA burst

Definition at line 846 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)

TIMx_PSC register is the DMA base address for DMA burst

Definition at line 851 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)

TIMx_RCR register is the DMA base address for DMA burst

Definition at line 853 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1

TIMx_SMCR register is the DMA base address for DMA burst

Definition at line 843 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2

TIMx_SR register is the DMA base address for DMA burst

Definition at line 845 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Burst Length

Defines
DMA Burst Length
TIM Exported Constants

Defines

#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Define Documentation

#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)

Transfer is done to 10 registers starting from the DMA burst base address

Definition at line 875 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)

Transfer is done to 11 registers starting from the DMA burst base address

Definition at line 876 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 12 registers starting from the DMA burst base address

Definition at line 877 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)

Transfer is done to 13 registers starting from the DMA burst base address

Definition at line 878 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 14 registers starting from the DMA burst base address

Definition at line 879 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 15 registers starting from the DMA burst base address

Definition at line 880 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 16 registers starting from the DMA burst base address

Definition at line 881 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4

Transfer is done to 17 registers starting from the DMA burst base address

Definition at line 882 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)

Transfer is done to 18 registers starting from the DMA burst base address

Definition at line 883 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U

Transfer is done to 1 register starting from the DMA burst base address

Definition at line 866 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0

Transfer is done to 2 registers starting from the DMA burst base address

Definition at line 867 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1

Transfer is done to 3 registers starting from the DMA burst base address

Definition at line 868 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 4 registers starting from the DMA burst base address

Definition at line 869 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2

Transfer is done to 5 registers starting from the DMA burst base address

Definition at line 870 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)

Transfer is done to 6 registers starting from the DMA burst base address

Definition at line 871 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)

Transfer is done to 7 registers starting from the DMA burst base address

Definition at line 872 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)

Transfer is done to 1 registers starting from the DMA burst base address

Definition at line 873 of file stm32f1xx_ll_tim.h.

#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3

Transfer is done to 9 registers starting from the DMA burst base address

Definition at line 874 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
TIM Exported Macros

Defines

#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in TIM register.

Define Documentation

#define LL_TIM_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 917 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

#define LL_TIM_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in TIM register.

Parameters:
__INSTANCE__ | TIM Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 909 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_BDTR_Init(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Exported_Macros

Defines
Exported_Macros
TIM Exported Macros

Defines

#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Define Documentation

#define __LL_TIM_CALC_ARR | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __FREQ__
 | ) | (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U

HELPER macro calculating the auto-reload value to achieve the required output signal frequency.

Note:
ex: __LL_TIM_CALC_ARR (1000000, LL_TIM_GetPrescaler (), 10000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__FREQ__ | output signal frequency (in Hz)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 962 of file stm32f1xx_ll_tim.h.

#define __LL_TIM_CALC_DEADTIME | ( | __TIMCLK__,
 |  | __CKD__,
 |  | __DT__
 | ) |
Value:
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))           ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
      (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
      (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
      (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
       0U)

HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.

Note:
ex: __LL_TIM_CALC_DEADTIME (80000000, LL_TIM_GetClockDivision (), 120);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CKD__ This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
__DT__ | deadtime duration (in ns)
Return values:
DTG[0:7]

Definition at line 937 of file stm32f1xx_ll_tim.h.

#define __LL_TIM_CALC_DELAY | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__
 | ) |
Value:
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
          / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.

Note:
ex: __LL_TIM_CALC_DELAY (1000000, LL_TIM_GetPrescaler (), 10);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
Return values:
Compare value (between Min_Data=0 and Max_Data=65535)

Definition at line 973 of file stm32f1xx_ll_tim.h.

#define __LL_TIM_CALC_PSC | ( | __TIMCLK__,
 |  | __CNTCLK__
 | ) | ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U

HELPER macro calculating the prescaler value to achieve the required counter clock frequency.

Note:
ex: __LL_TIM_CALC_PSC (80000000, 1000000);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__CNTCLK__ | counter clock frequency (in Hz)
Return values:
Prescaler value (between Min_Data=0 and Max_Data=65535)

Definition at line 951 of file stm32f1xx_ll_tim.h.

#define __LL_TIM_CALC_PULSE | ( | __TIMCLK__,
 |  | __PSC__,
 |  | __DELAY__,
 |  | __PULSE__
 | ) |
Value:
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
           + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))

HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).

Note:
ex: __LL_TIM_CALC_PULSE (1000000, LL_TIM_GetPrescaler (), 10, 20);
Parameters:
__TIMCLK__ | timer input clock frequency (in Hz)
__PSC__ | prescaler
__DELAY__ | timer output compare active/inactive delay (in us)
__PULSE__ | pulse duration (in us)
Return values:
Auto-reload value (between Min_Data=0 and Max_Data=65535)

Definition at line 986 of file stm32f1xx_ll_tim.h.

#define __LL_TIM_GET_ICPSC_RATIO ( __ICPSC__ ) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))

HELPER macro retrieving the ratio of the input capture prescaler.

Note:
ex: __LL_TIM_GET_ICPSC_RATIO (LL_TIM_IC_GetPrescaler ());
Parameters:
__ICPSC__ This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
Input capture prescaler ratio (1, 2, 4 or 8)

Definition at line 1000 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Time Base configuration

Functions
Time Base configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx)
Get the repetition counter value.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableARRPreload ( TIM_TypeDef * TIMx )

Disable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_DisableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1206 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableCounter ( TIM_TypeDef * TIMx )

Disable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_DisableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1038 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableUpdateEvent ( TIM_TypeDef * TIMx )

Disable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_DisableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1071 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableARRPreload ( TIM_TypeDef * TIMx )

Enable auto-reload (ARR) preload.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_EnableARRPreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1195 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableCounter ( TIM_TypeDef * TIMx )

Enable timer counter.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_EnableCounter
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1027 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableUpdateEvent ( TIM_TypeDef * TIMx )

Enable update event generation.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_EnableUpdateEvent
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1060 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetAutoReload ( TIM_TypeDef * TIMx )

Get the auto-reload value.

Reference Manual to LL API cross reference:
ARR ARR LL_TIM_GetAutoReload
Parameters:
TIMx Timer instance
Return values:
Auto-reload value

Definition at line 1340 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetClockDivision ( TIM_TypeDef * TIMx )

Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_GetClockDivision
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4

Definition at line 1252 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounter ( TIM_TypeDef * TIMx )

Get the counter value.

Reference Manual to LL API cross reference:
CNT CNT LL_TIM_GetCounter
Parameters:
TIMx Timer instance
Return values:
Counter value (between Min_Data=0 and Max_Data=0xFFFF)

Definition at line 1275 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetCounterMode ( TIM_TypeDef * TIMx )

Get actual counter mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetCounterMode
CR1 CMS LL_TIM_GetCounterMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN

Definition at line 1184 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetDirection ( TIM_TypeDef * TIMx )

Get the current direction of the counter.

Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_GetDirection
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_COUNTERDIRECTION_UP
  • LL_TIM_COUNTERDIRECTION_DOWN

Definition at line 1288 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode ( TIM_TypeDef * TIMx )

Get actual one pulse mode.

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_GetOnePulseMode
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE

Definition at line 1143 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetPrescaler ( TIM_TypeDef * TIMx )

Get the prescaler value.

Reference Manual to LL API cross reference:
PSC PSC LL_TIM_GetPrescaler
Parameters:
TIMx Timer instance
Return values:
Prescaler value between Min_Data=0 and Max_Data=65535

Definition at line 1315 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter ( TIM_TypeDef * TIMx )

Get the repetition counter value.

Note:
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_GetRepetitionCounter
Parameters:
TIMx Timer instance
Return values:
Repetition counter value

Definition at line 1367 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource ( TIM_TypeDef * TIMx )

Get actual event update source.

Reference Manual to LL API cross reference:
CR1 URS LL_TIM_GetUpdateSource
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER

Definition at line 1116 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload ( TIM_TypeDef * TIMx )

Indicates whether auto-reload (ARR) preload is enabled.

Reference Manual to LL API cross reference:
CR1 ARPE LL_TIM_IsEnabledARRPreload
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1217 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter ( TIM_TypeDef * TIMx )

Indicates whether the timer counter is enabled.

Reference Manual to LL API cross reference:
CR1 CEN LL_TIM_IsEnabledCounter
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1049 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent ( TIM_TypeDef * TIMx )

Indicates whether update event generation is enabled.

Reference Manual to LL API cross reference:
CR1 UDIS LL_TIM_IsEnabledUpdateEvent
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 1082 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetAutoReload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | AutoReload
 | ) |  |

Set the auto-reload value.

Note:
The counter is blocked while the auto-reload value is null.
Helper macro __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
Reference Manual to LL API cross reference:
ARR ARR LL_TIM_SetAutoReload
Parameters:
TIMx | Timer instance
AutoReload | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1329 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetClockDivision | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockDivision
 | ) |  |

Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.

Note:
Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check whether or not the clock division feature is supported by the timer instance.
Reference Manual to LL API cross reference:
CR1 CKD LL_TIM_SetClockDivision
Parameters:
TIMx Timer instance
ClockDivision This parameter can be one of the following values:
  • LL_TIM_CLOCKDIVISION_DIV1
  • LL_TIM_CLOCKDIVISION_DIV2
  • LL_TIM_CLOCKDIVISION_DIV4
Return values:
None

Definition at line 1235 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Counter
 | ) |  |

Set the counter value.

Reference Manual to LL API cross reference:
CNT CNT LL_TIM_SetCounter
Parameters:
TIMx | Timer instance
Counter | Counter value (between Min_Data=0 and Max_Data=0xFFFF)
Return values:
None

Definition at line 1264 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetCounterMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CounterMode
 | ) |  |

Set the timer counter counting mode.

Note:
Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to check whether or not the counter mode selection feature is supported by a timer instance.
Reference Manual to LL API cross reference:
CR1 DIR LL_TIM_SetCounterMode
CR1 CMS LL_TIM_SetCounterMode
Parameters:
TIMx Timer instance
CounterMode This parameter can be one of the following values:
  • LL_TIM_COUNTERMODE_UP
  • LL_TIM_COUNTERMODE_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP
  • LL_TIM_COUNTERMODE_CENTER_DOWN
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN
Return values:
None

Definition at line 1164 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetOnePulseMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OnePulseMode
 | ) |  |

Set one pulse mode (one shot v.s.

repetitive).

Reference Manual to LL API cross reference:
CR1 OPM LL_TIM_SetOnePulseMode
Parameters:
TIMx Timer instance
OnePulseMode This parameter can be one of the following values:
  • LL_TIM_ONEPULSEMODE_SINGLE
  • LL_TIM_ONEPULSEMODE_REPETITIVE
Return values:
None

Definition at line 1130 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the prescaler value.

Note:
The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
The prescaler can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.
Helper macro __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
Reference Manual to LL API cross reference:
PSC PSC LL_TIM_SetPrescaler
Parameters:
TIMx | Timer instance
Prescaler | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1304 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetRepetitionCounter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | RepetitionCounter
 | ) |  |

Set the repetition counter value.

Note:
Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check whether or not a timer instance supports a repetition counter.
Reference Manual to LL API cross reference:
RCR REP LL_TIM_SetRepetitionCounter
Parameters:
TIMx | Timer instance
RepetitionCounter | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 1354 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_Init().

__STATIC_INLINE void LL_TIM_SetUpdateSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | UpdateSource
 | ) |  |

Set update event source.

Note:
Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events generate an update interrupt or DMA request if enabled:
  • Counter overflow/underflow
  • Setting the UG bit
  • Update generation through the slave mode controller
Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Reference Manual to LL API cross reference:
CR1 URS LL_TIM_SetUpdateSource
Parameters:
TIMx Timer instance
UpdateSource This parameter can be one of the following values:
  • LL_TIM_UPDATESOURCE_REGULAR
  • LL_TIM_UPDATESOURCE_COUNTER
Return values:
None

Definition at line 1103 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Capture Compare configuration

Functions
Capture Compare configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_CC_DisableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Disable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_DisableChannel
CCER CC1NE LL_TIM_CC_DisableChannel
CCER CC2E LL_TIM_CC_DisableChannel
CCER CC2NE LL_TIM_CC_DisableChannel
CCER CC3E LL_TIM_CC_DisableChannel
CCER CC3NE LL_TIM_CC_DisableChannel
CCER CC4E LL_TIM_CC_DisableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
Return values:
None

Definition at line 1515 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_DisablePreload ( TIM_TypeDef * TIMx )

Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_DisablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1403 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnableChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Enable capture/compare channels.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_EnableChannel
CCER CC1NE LL_TIM_CC_EnableChannel
CCER CC2E LL_TIM_CC_EnableChannel
CCER CC2NE LL_TIM_CC_EnableChannel
CCER CC3E LL_TIM_CC_EnableChannel
CCER CC3NE LL_TIM_CC_EnableChannel
CCER CC4E LL_TIM_CC_EnableChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
Return values:
None

Definition at line 1490 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_EnablePreload ( TIM_TypeDef * TIMx )

Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

Note:
CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs.
Only on channels that have a complementary output.
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCPC LL_TIM_CC_EnablePreload
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 1390 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger ( TIM_TypeDef * TIMx )

Get actual trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
Parameters:
TIMx Timer instance
Return values:
Returned value can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE

Definition at line 1446 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channels
 | ) |  |

Indicate whether channel(s) is(are) enabled.

Reference Manual to LL API cross reference:
CCER CC1E LL_TIM_CC_IsEnabledChannel
CCER CC1NE LL_TIM_CC_IsEnabledChannel
CCER CC2E LL_TIM_CC_IsEnabledChannel
CCER CC2NE LL_TIM_CC_IsEnabledChannel
CCER CC3E LL_TIM_CC_IsEnabledChannel
CCER CC3NE LL_TIM_CC_IsEnabledChannel
CCER CC4E LL_TIM_CC_IsEnabledChannel
Parameters:
TIMx Timer instance
Channels This parameter can be a combination of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
Return values:
State of bit (1 or 0).

Definition at line 1540 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMAReqTrigger
 | ) |  |

Set the trigger of the capture/compare DMA request.

Reference Manual to LL API cross reference:
CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
Parameters:
TIMx Timer instance
DMAReqTrigger This parameter can be one of the following values:
  • LL_TIM_CCDMAREQUEST_CC
  • LL_TIM_CCDMAREQUEST_UPDATE
Return values:
None

Definition at line 1433 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetLockLevel | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | LockLevel
 | ) |  |

Set the lock level to freeze the configuration of several capture/compare parameters.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not the lock mechanism is supported by a timer instance.
Reference Manual to LL API cross reference:
BDTR LOCK LL_TIM_CC_SetLockLevel
Parameters:
TIMx Timer instance
LockLevel This parameter can be one of the following values:
  • LL_TIM_LOCKLEVEL_OFF
  • LL_TIM_LOCKLEVEL_1
  • LL_TIM_LOCKLEVEL_2
  • LL_TIM_LOCKLEVEL_3
Return values:
None

Definition at line 1465 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_CC_SetUpdate | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CCUpdateSource
 | ) |  |

Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).

Note:
Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check whether or not a timer instance is able to generate a commutation event.
Reference Manual to LL API cross reference:
CR2 CCUS LL_TIM_CC_SetUpdate
Parameters:
TIMx Timer instance
CCUpdateSource This parameter can be one of the following values:
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
Return values:
None

Definition at line 1419 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Output channel configuration

Functions
Output channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.

Function Documentation

__STATIC_INLINE void LL_TIM_OC_ConfigOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure an output channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_OC_ConfigOutput
CCMR1 CC2S LL_TIM_OC_ConfigOutput
CCMR2 CC3S LL_TIM_OC_ConfigOutput
CCMR2 CC4S LL_TIM_OC_ConfigOutput
CCER CC1P LL_TIM_OC_ConfigOutput
CCER CC2P LL_TIM_OC_ConfigOutput
CCER CC3P LL_TIM_OC_ConfigOutput
CCER CC4P LL_TIM_OC_ConfigOutput
CR2 OIS1 LL_TIM_OC_ConfigOutput
CR2 OIS2 LL_TIM_OC_ConfigOutput
CR2 OIS3 LL_TIM_OC_ConfigOutput
CR2 OIS4 LL_TIM_OC_ConfigOutput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_OCPOLARITY_HIGH or LL_TIM_OCPOLARITY_LOW
  • LL_TIM_OCIDLESTATE_LOW or LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 1577 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable clearing the output channel on an external event.

Note:
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_DisableClear
CCMR1 OC2CE LL_TIM_OC_DisableClear
CCMR2 OC3CE LL_TIM_OC_DisableClear
CCMR2 OC4CE LL_TIM_OC_DisableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
None

Definition at line 1937 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable fast mode for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_DisableFast
CCMR1 OC2FE LL_TIM_OC_DisableFast
CCMR2 OC3FE LL_TIM_OC_DisableFast
CCMR2 OC4FE LL_TIM_OC_DisableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
None

Definition at line 1803 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_DisablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Disable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_DisablePreload
CCMR1 OC2PE LL_TIM_OC_DisablePreload
CCMR2 OC3PE LL_TIM_OC_DisablePreload
CCMR2 OC4PE LL_TIM_OC_DisablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
None

Definition at line 1868 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable clearing the output channel on an external event.

Note:
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_EnableClear
CCMR1 OC2CE LL_TIM_OC_EnableClear
CCMR2 OC3CE LL_TIM_OC_EnableClear
CCMR2 OC4CE LL_TIM_OC_EnableClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
None

Definition at line 1914 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnableFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable fast mode for the output channel.

Note:
Acts only if the channel is configured in PWM1 or PWM2 mode.
Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_EnableFast
CCMR1 OC2FE LL_TIM_OC_EnableFast
CCMR2 OC3FE LL_TIM_OC_EnableFast
CCMR2 OC4FE LL_TIM_OC_EnableFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
None

Definition at line 1781 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_EnablePreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Enable compare register (TIMx_CCRx) preload for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_EnablePreload
CCMR1 OC2PE LL_TIM_OC_EnablePreload
CCMR2 OC3PE LL_TIM_OC_EnablePreload
CCMR2 OC4PE LL_TIM_OC_EnablePreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
None

Definition at line 1847 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR1) set for output channel 1.

Note:
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_GetCompareCH1
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2049 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR2) set for output channel 2.

Note:
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_GetCompareCH2
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2062 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR3) set for output channel 3.

Note:
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_GetCompareCH3
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2075 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4 ( TIM_TypeDef * TIMx )

Get compare value (TIMx_CCR4) set for output channel 4.

Note:
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_GetCompareCH4
Parameters:
TIMx Timer instance
Return values:
CompareValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2088 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the IDLE state of an output channel.

Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_GetIdleState
CR2 OIS1N LL_TIM_OC_GetIdleState
CR2 OIS2 LL_TIM_OC_GetIdleState
CR2 OIS2N LL_TIM_OC_GetIdleState
CR2 OIS3 LL_TIM_OC_GetIdleState
CR2 OIS3N LL_TIM_OC_GetIdleState
CR2 OIS4 LL_TIM_OC_GetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH

Definition at line 1760 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the output compare mode of an output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_GetMode
CCMR1 OC2M LL_TIM_OC_GetMode
CCMR2 OC3M LL_TIM_OC_GetMode
CCMR2 OC4M LL_TIM_OC_GetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2

Definition at line 1641 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_GetPolarity
CCER CC1NP LL_TIM_OC_GetPolarity
CCER CC2P LL_TIM_OC_GetPolarity
CCER CC2NP LL_TIM_OC_GetPolarity
CCER CC3P LL_TIM_OC_GetPolarity
CCER CC3NP LL_TIM_OC_GetPolarity
CCER CC4P LL_TIM_OC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW

Definition at line 1699 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates clearing the output channel on an external event is enabled for the output channel.

Note:
This function enables clearing the output channel on an external event.
This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether or not a timer instance can clear the OCxREF signal on an external event.
Reference Manual to LL API cross reference:
CCMR1 OC1CE LL_TIM_OC_IsEnabledClear
CCMR1 OC2CE LL_TIM_OC_IsEnabledClear
CCMR2 OC3CE LL_TIM_OC_IsEnabledClear
CCMR2 OC4CE LL_TIM_OC_IsEnabledClear
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
State of bit (1 or 0).

Definition at line 1962 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether fast mode is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1FE LL_TIM_OC_IsEnabledFast
CCMR1 OC2FE LL_TIM_OC_IsEnabledFast
CCMR2 OC3FE LL_TIM_OC_IsEnabledFast
CCMR2 OC4FE LL_TIM_OC_IsEnabledFast
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
State of bit (1 or 0).

Definition at line 1825 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.

Reference Manual to LL API cross reference:
CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload
CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload
CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
State of bit (1 or 0).

Definition at line 1889 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetCompareCH1 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 1 (TIMx_CCR1).

Note:
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not output channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_OC_SetCompareCH1
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 1994 of file stm32f1xx_ll_tim.h.

Referenced by OC1Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH2 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 2 (TIMx_CCR2).

Note:
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not output channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_OC_SetCompareCH2
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2008 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_HALLSENSOR_Init(), and OC2Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH3 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 3 (TIMx_CCR3).

Note:
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not output channel is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_OC_SetCompareCH3
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2022 of file stm32f1xx_ll_tim.h.

Referenced by OC3Config().

__STATIC_INLINE void LL_TIM_OC_SetCompareCH4 | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | CompareValue
 | ) |  |

Set compare value for output channel 4 (TIMx_CCR4).

Note:
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not output channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_OC_SetCompareCH4
Parameters:
TIMx | Timer instance
CompareValue | between Min_Data=0 and Max_Data=65535
Return values:
None

Definition at line 2036 of file stm32f1xx_ll_tim.h.

Referenced by OC4Config().

__STATIC_INLINE void LL_TIM_OC_SetDeadTime | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DeadTime
 | ) |  |

Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not dead-time insertion feature is supported by a timer instance.
Helper macro __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
Reference Manual to LL API cross reference:
BDTR DTG LL_TIM_OC_SetDeadTime
Parameters:
TIMx | Timer instance
DeadTime | between Min_Data=0 and Max_Data=255
Return values:
None

Definition at line 1980 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_OC_SetIdleState | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | IdleState
 | ) |  |

Set the IDLE state of an output channel.

Note:
This function is significant only for the timer instances supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
CR2 OIS1 LL_TIM_OC_SetIdleState
CR2 OIS1N LL_TIM_OC_SetIdleState
CR2 OIS2 LL_TIM_OC_SetIdleState
CR2 OIS2N LL_TIM_OC_SetIdleState
CR2 OIS3 LL_TIM_OC_SetIdleState
CR2 OIS3N LL_TIM_OC_SetIdleState
CR2 OIS4 LL_TIM_OC_SetIdleState
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
IdleState This parameter can be one of the following values:
  • LL_TIM_OCIDLESTATE_LOW
  • LL_TIM_OCIDLESTATE_HIGH
Return values:
None

Definition at line 1732 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Mode
 | ) |  |

Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.

Reference Manual to LL API cross reference:
CCMR1 OC1M LL_TIM_OC_SetMode
CCMR1 OC2M LL_TIM_OC_SetMode
CCMR2 OC3M LL_TIM_OC_SetMode
CCMR2 OC4M LL_TIM_OC_SetMode
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Mode This parameter can be one of the following values:
  • LL_TIM_OCMODE_FROZEN
  • LL_TIM_OCMODE_ACTIVE
  • LL_TIM_OCMODE_INACTIVE
  • LL_TIM_OCMODE_TOGGLE
  • LL_TIM_OCMODE_FORCED_INACTIVE
  • LL_TIM_OCMODE_FORCED_ACTIVE
  • LL_TIM_OCMODE_PWM1
  • LL_TIM_OCMODE_PWM2
Return values:
None

Definition at line 1612 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_OC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Polarity
 | ) |  |

Set the polarity of an output channel.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_OC_SetPolarity
CCER CC1NP LL_TIM_OC_SetPolarity
CCER CC2P LL_TIM_OC_SetPolarity
CCER CC2NP LL_TIM_OC_SetPolarity
CCER CC3P LL_TIM_OC_SetPolarity
CCER CC3NP LL_TIM_OC_SetPolarity
CCER CC4P LL_TIM_OC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH1N
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH2N
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH3N
  • LL_TIM_CHANNEL_CH4
Polarity This parameter can be one of the following values:
  • LL_TIM_OCPOLARITY_HIGH
  • LL_TIM_OCPOLARITY_LOW
Return values:
None

Definition at line 1671 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Input channel configuration

Functions
Input channel configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx)
Get captured value for input channel 4.

Function Documentation

__STATIC_INLINE void LL_TIM_IC_Config | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | Configuration
 | ) |  |

Configure input channel.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_Config
CCMR1 IC1PSC LL_TIM_IC_Config
CCMR1 IC1F LL_TIM_IC_Config
CCMR1 CC2S LL_TIM_IC_Config
CCMR1 IC2PSC LL_TIM_IC_Config
CCMR1 IC2F LL_TIM_IC_Config
CCMR2 CC3S LL_TIM_IC_Config
CCMR2 IC3PSC LL_TIM_IC_Config
CCMR2 IC3F LL_TIM_IC_Config
CCMR2 CC4S LL_TIM_IC_Config
CCMR2 IC4PSC LL_TIM_IC_Config
CCMR2 IC4F LL_TIM_IC_Config
CCER CC1P LL_TIM_IC_Config
CCER CC1NP LL_TIM_IC_Config
CCER CC2P LL_TIM_IC_Config
CCER CC2NP LL_TIM_IC_Config
CCER CC3P LL_TIM_IC_Config
CCER CC3NP LL_TIM_IC_Config
CCER CC4P LL_TIM_IC_Config
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Configuration This parameter must be a combination of all the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI or LL_TIM_ACTIVEINPUT_INDIRECTTI or LL_TIM_ACTIVEINPUT_TRC
  • LL_TIM_ICPSC_DIV1 or ... or LL_TIM_ICPSC_DIV8
  • LL_TIM_IC_FILTER_FDIV1 or ... or LL_TIM_IC_FILTER_FDIV32_N8
  • LL_TIM_IC_POLARITY_RISING or LL_TIM_IC_POLARITY_FALLING
Return values:
None

Definition at line 2134 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_DisableXORCombination ( TIM_TypeDef * TIMx )

Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_DisableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2393 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_EnableXORCombination ( TIM_TypeDef * TIMx )

Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_EnableXORCombination
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2380 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_GetActiveInput
CCMR1 CC2S LL_TIM_IC_GetActiveInput
CCMR2 CC3S LL_TIM_IC_GetActiveInput
CCMR2 CC4S LL_TIM_IC_GetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC

Definition at line 2186 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1 ( TIM_TypeDef * TIMx )

Get captured value for input channel 1.

Note:
Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not input channel 1 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2419 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2 ( TIM_TypeDef * TIMx )

Get captured value for input channel 2.

Note:
Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not input channel 2 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2432 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3 ( TIM_TypeDef * TIMx )

Get captured value for input channel 3.

Note:
Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not input channel 3 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2445 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4 ( TIM_TypeDef * TIMx )

Get captured value for input channel 4.

Note:
Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not input channel 4 is supported by a timer instance.
Reference Manual to LL API cross reference:
CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
Parameters:
TIMx Timer instance
Return values:
CapturedValue (between Min_Data=0 and Max_Data=65535)

Definition at line 2458 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_GetFilter
CCMR1 IC2F LL_TIM_IC_GetFilter
CCMR2 IC3F LL_TIM_IC_GetFilter
CCMR2 IC4F LL_TIM_IC_GetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8

Definition at line 2312 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_GetPolarity
CCER CC1NP LL_TIM_IC_GetPolarity
CCER CC2P LL_TIM_IC_GetPolarity
CCER CC2NP LL_TIM_IC_GetPolarity
CCER CC3P LL_TIM_IC_GetPolarity
CCER CC3NP LL_TIM_IC_GetPolarity
CCER CC4P LL_TIM_IC_GetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING

Definition at line 2365 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel
 | ) |  |

Get the current prescaler value acting on an input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_GetPrescaler
CCMR1 IC2PSC LL_TIM_IC_GetPrescaler
CCMR2 IC3PSC LL_TIM_IC_GetPrescaler
CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
Return values:
Returned value can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8

Definition at line 2237 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination ( TIM_TypeDef * TIMx )

Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.

Note:
Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an XOR input.
Reference Manual to LL API cross reference:
CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2406 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_IC_SetActiveInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICActiveInput
 | ) |  |

Set the active input.

Reference Manual to LL API cross reference:
CCMR1 CC1S LL_TIM_IC_SetActiveInput
CCMR1 CC2S LL_TIM_IC_SetActiveInput
CCMR2 CC3S LL_TIM_IC_SetActiveInput
CCMR2 CC4S LL_TIM_IC_SetActiveInput
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICActiveInput This parameter can be one of the following values:
  • LL_TIM_ACTIVEINPUT_DIRECTTI
  • LL_TIM_ACTIVEINPUT_INDIRECTTI
  • LL_TIM_ACTIVEINPUT_TRC
Return values:
None

Definition at line 2162 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetFilter | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICFilter
 | ) |  |

Set the input filter duration.

Reference Manual to LL API cross reference:
CCMR1 IC1F LL_TIM_IC_SetFilter
CCMR1 IC2F LL_TIM_IC_SetFilter
CCMR2 IC3F LL_TIM_IC_SetFilter
CCMR2 IC4F LL_TIM_IC_SetFilter
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICFilter This parameter can be one of the following values:
  • LL_TIM_IC_FILTER_FDIV1
  • LL_TIM_IC_FILTER_FDIV1_N2
  • LL_TIM_IC_FILTER_FDIV1_N4
  • LL_TIM_IC_FILTER_FDIV1_N8
  • LL_TIM_IC_FILTER_FDIV2_N6
  • LL_TIM_IC_FILTER_FDIV2_N8
  • LL_TIM_IC_FILTER_FDIV4_N6
  • LL_TIM_IC_FILTER_FDIV4_N8
  • LL_TIM_IC_FILTER_FDIV8_N6
  • LL_TIM_IC_FILTER_FDIV8_N8
  • LL_TIM_IC_FILTER_FDIV16_N5
  • LL_TIM_IC_FILTER_FDIV16_N6
  • LL_TIM_IC_FILTER_FDIV16_N8
  • LL_TIM_IC_FILTER_FDIV32_N5
  • LL_TIM_IC_FILTER_FDIV32_N6
  • LL_TIM_IC_FILTER_FDIV32_N8
Return values:
None

Definition at line 2275 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPolarity | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPolarity
 | ) |  |

Set the input channel polarity.

Reference Manual to LL API cross reference:
CCER CC1P LL_TIM_IC_SetPolarity
CCER CC1NP LL_TIM_IC_SetPolarity
CCER CC2P LL_TIM_IC_SetPolarity
CCER CC2NP LL_TIM_IC_SetPolarity
CCER CC3P LL_TIM_IC_SetPolarity
CCER CC3NP LL_TIM_IC_SetPolarity
CCER CC4P LL_TIM_IC_SetPolarity
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPolarity This parameter can be one of the following values:
  • LL_TIM_IC_POLARITY_RISING
  • LL_TIM_IC_POLARITY_FALLING
Return values:
None

Definition at line 2339 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

__STATIC_INLINE void LL_TIM_IC_SetPrescaler | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ICPrescaler
 | ) |  |

Set the prescaler of input channel.

Reference Manual to LL API cross reference:
CCMR1 IC1PSC LL_TIM_IC_SetPrescaler
CCMR1 IC2PSC LL_TIM_IC_SetPrescaler
CCMR2 IC3PSC LL_TIM_IC_SetPrescaler
CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
Parameters:
TIMx Timer instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
ICPrescaler This parameter can be one of the following values:
  • LL_TIM_ICPSC_DIV1
  • LL_TIM_ICPSC_DIV2
  • LL_TIM_ICPSC_DIV4
  • LL_TIM_ICPSC_DIV8
Return values:
None

Definition at line 2212 of file stm32f1xx_ll_tim.h.

References TIM_GET_CHANNEL_INDEX.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Counter clock selection

Functions
Counter clock selection
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableExternalClock ( TIM_TypeDef * TIMx )

Disable external clock mode 2.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_DisableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2492 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableExternalClock ( TIM_TypeDef * TIMx )

Enable external clock mode 2.

Note:
When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_EnableExternalClock
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2479 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock ( TIM_TypeDef * TIMx )

Indicate whether external clock mode 2 is enabled.

Note:
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR ECE LL_TIM_IsEnabledExternalClock
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2505 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetClockSource | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ClockSource
 | ) |  |

Set the clock source of the counter clock.

Note:
when selected clock source is external clock mode 1, the timer input the external clock is applied is selected by calling the LL_TIM_SetTriggerInput() function. This timer input must be configured by calling the LL_TIM_IC_Config() function.
Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode1.
Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check whether or not a timer instance supports external clock mode2.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetClockSource
SMCR ECE LL_TIM_SetClockSource
Parameters:
TIMx Timer instance
ClockSource This parameter can be one of the following values:
  • LL_TIM_CLOCKSOURCE_INTERNAL
  • LL_TIM_CLOCKSOURCE_EXT_MODE1
  • LL_TIM_CLOCKSOURCE_EXT_MODE2
Return values:
None

Definition at line 2529 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetEncoderMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | EncoderMode
 | ) |  |

Set the encoder interface mode.

Note:
Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the encoder mode.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetEncoderMode
Parameters:
TIMx Timer instance
EncoderMode This parameter can be one of the following values:
  • LL_TIM_ENCODERMODE_X2_TI1
  • LL_TIM_ENCODERMODE_X2_TI2
  • LL_TIM_ENCODERMODE_X4_TI12
Return values:
None

Definition at line 2546 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_ENCODER_Init().

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Timer synchronisation configuration

Functions
Timer synchronisation configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigETR | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | ETRPolarity,
 |  | uint32_t | ETRPrescaler,
 |  | uint32_t | ETRFilter
 | ) |  |

Configure the external trigger (ETR) input.

Note:
Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not a timer instance provides an external trigger input.
Reference Manual to LL API cross reference:
SMCR ETP LL_TIM_ConfigETR
SMCR ETPS LL_TIM_ConfigETR
SMCR ETF LL_TIM_ConfigETR
Parameters:
TIMx Timer instance
ETRPolarity This parameter can be one of the following values:
  • LL_TIM_ETR_POLARITY_NONINVERTED
  • LL_TIM_ETR_POLARITY_INVERTED
ETRPrescaler This parameter can be one of the following values:
  • LL_TIM_ETR_PRESCALER_DIV1
  • LL_TIM_ETR_PRESCALER_DIV2
  • LL_TIM_ETR_PRESCALER_DIV4
  • LL_TIM_ETR_PRESCALER_DIV8
ETRFilter This parameter can be one of the following values:
  • LL_TIM_ETR_FILTER_FDIV1
  • LL_TIM_ETR_FILTER_FDIV1_N2
  • LL_TIM_ETR_FILTER_FDIV1_N4
  • LL_TIM_ETR_FILTER_FDIV1_N8
  • LL_TIM_ETR_FILTER_FDIV2_N6
  • LL_TIM_ETR_FILTER_FDIV2_N8
  • LL_TIM_ETR_FILTER_FDIV4_N6
  • LL_TIM_ETR_FILTER_FDIV4_N8
  • LL_TIM_ETR_FILTER_FDIV8_N6
  • LL_TIM_ETR_FILTER_FDIV8_N8
  • LL_TIM_ETR_FILTER_FDIV16_N5
  • LL_TIM_ETR_FILTER_FDIV16_N6
  • LL_TIM_ETR_FILTER_FDIV16_N8
  • LL_TIM_ETR_FILTER_FDIV32_N5
  • LL_TIM_ETR_FILTER_FDIV32_N6
  • LL_TIM_ETR_FILTER_FDIV32_N8
Return values:
None

Definition at line 2694 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode ( TIM_TypeDef * TIMx )

Disable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_DisableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2641 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode ( TIM_TypeDef * TIMx )

Enable the Master/Slave mode.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_EnableMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2628 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode ( TIM_TypeDef * TIMx )

Indicates whether the Master/Slave mode is enabled.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2654 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetSlaveMode | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | SlaveMode
 | ) |  |

Set the synchronization mode of a slave timer.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR SMS LL_TIM_SetSlaveMode
Parameters:
TIMx Timer instance
SlaveMode This parameter can be one of the following values:
  • LL_TIM_SLAVEMODE_DISABLED
  • LL_TIM_SLAVEMODE_RESET
  • LL_TIM_SLAVEMODE_GATED
  • LL_TIM_SLAVEMODE_TRIGGER
Return values:
None

Definition at line 2593 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerInput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TriggerInput
 | ) |  |

Set the selects the trigger input to be used to synchronize the counter.

Note:
Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a slave timer.
Reference Manual to LL API cross reference:
SMCR TS LL_TIM_SetTriggerInput
Parameters:
TIMx Timer instance
TriggerInput This parameter can be one of the following values:
  • LL_TIM_TS_ITR0
  • LL_TIM_TS_ITR1
  • LL_TIM_TS_ITR2
  • LL_TIM_TS_ITR3
  • LL_TIM_TS_TI1F_ED
  • LL_TIM_TS_TI1FP1
  • LL_TIM_TS_TI2FP2
  • LL_TIM_TS_ETRF
Return values:
None

Definition at line 2615 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetTriggerOutput | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TimerSynchronization
 | ) |  |

Set the trigger output (TRGO) used for timer synchronization .

Note:
Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check whether or not a timer instance can operate as a master timer.
Reference Manual to LL API cross reference:
CR2 MMS LL_TIM_SetTriggerOutput
Parameters:
TIMx Timer instance
TimerSynchronization This parameter can be one of the following values:
  • LL_TIM_TRGO_RESET
  • LL_TIM_TRGO_ENABLE
  • LL_TIM_TRGO_UPDATE
  • LL_TIM_TRGO_CC1IF
  • LL_TIM_TRGO_OC1REF
  • LL_TIM_TRGO_OC2REF
  • LL_TIM_TRGO_OC3REF
  • LL_TIM_TRGO_OC4REF
Return values:
None

Definition at line 2575 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Break function configuration

Functions
Break function configuration
TIM Exported Functions

Functions

__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity)
Configure the break input.
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigBRK | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | BreakPolarity
 | ) |  |

Configure the break input.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKP LL_TIM_ConfigBRK
Parameters:
TIMx Timer instance
BreakPolarity This parameter can be one of the following values:
  • LL_TIM_BREAK_POLARITY_LOW
  • LL_TIM_BREAK_POLARITY_HIGH
Return values:
None

Definition at line 2744 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAllOutputs ( TIM_TypeDef * TIMx )

Disable the outputs (reset the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_DisableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2833 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableAutomaticOutput ( TIM_TypeDef * TIMx )

Disable automatic output (MOE can be set only by software).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_DisableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2790 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableBRK ( TIM_TypeDef * TIMx )

Disable the break function.

Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_DisableBRK
Parameters:
TIMx Timer instance
Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Return values:
None

Definition at line 2728 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAllOutputs ( TIM_TypeDef * TIMx )

Enable the outputs (set the MOE bit in TIMx_BDTR register).

Note:
The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_EnableAllOutputs
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2818 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableAutomaticOutput ( TIM_TypeDef * TIMx )

Enable automatic output (MOE can be set by software or automatically when a break input is active).

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_EnableAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2777 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableBRK ( TIM_TypeDef * TIMx )

Enable the break function.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR BKE LL_TIM_EnableBRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2715 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs ( TIM_TypeDef * TIMx )

Indicates whether outputs are enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR MOE LL_TIM_IsEnabledAllOutputs
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2846 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput ( TIM_TypeDef * TIMx )

Indicate whether automatic output is enabled.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR AOE LL_TIM_IsEnabledAutomaticOutput
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2803 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_SetOffStates | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | OffStateIdle,
 |  | uint32_t | OffStateRun
 | ) |  |

Select the outputs off state (enabled v.s.

disabled) in Idle and Run modes.

Note:
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Reference Manual to LL API cross reference:
BDTR OSSI LL_TIM_SetOffStates
BDTR OSSR LL_TIM_SetOffStates
Parameters:
TIMx Timer instance
OffStateIdle This parameter can be one of the following values:
  • LL_TIM_OSSI_DISABLE
  • LL_TIM_OSSI_ENABLE
OffStateRun This parameter can be one of the following values:
  • LL_TIM_OSSR_DISABLE
  • LL_TIM_OSSR_ENABLE
Return values:
None

Definition at line 2764 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA burst mode configuration

Functions
DMA burst mode configuration
TIM Exported Functions

Functions

__STATIC_INLINE void LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.

Function Documentation

__STATIC_INLINE void LL_TIM_ConfigDMABurst | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | DMABurstBaseAddress,
 |  | uint32_t | DMABurstLength
 | ) |  |

Configures the timer DMA burst feature.

Note:
Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or not a timer instance supports the DMA burst mode.
Reference Manual to LL API cross reference:
DCR DBL LL_TIM_ConfigDMABurst
DCR DBA LL_TIM_ConfigDMABurst
Parameters:
TIMx Timer instance
DMABurstBaseAddress This parameter can be one of the following values:
  • LL_TIM_DMABURST_BASEADDR_CR1
  • LL_TIM_DMABURST_BASEADDR_CR2
  • LL_TIM_DMABURST_BASEADDR_SMCR
  • LL_TIM_DMABURST_BASEADDR_DIER
  • LL_TIM_DMABURST_BASEADDR_SR
  • LL_TIM_DMABURST_BASEADDR_EGR
  • LL_TIM_DMABURST_BASEADDR_CCMR1
  • LL_TIM_DMABURST_BASEADDR_CCMR2
  • LL_TIM_DMABURST_BASEADDR_CCER
  • LL_TIM_DMABURST_BASEADDR_CNT
  • LL_TIM_DMABURST_BASEADDR_PSC
  • LL_TIM_DMABURST_BASEADDR_ARR
  • LL_TIM_DMABURST_BASEADDR_RCR
  • LL_TIM_DMABURST_BASEADDR_CCR1
  • LL_TIM_DMABURST_BASEADDR_CCR2
  • LL_TIM_DMABURST_BASEADDR_CCR3
  • LL_TIM_DMABURST_BASEADDR_CCR4
  • LL_TIM_DMABURST_BASEADDR_BDTR
DMABurstLength This parameter can be one of the following values:
  • LL_TIM_DMABURST_LENGTH_1TRANSFER
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS
Return values:
None

Definition at line 2905 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialisation and deinitialisation functions

Functions
Initialisation and deinitialisation functions
TIM | TIM Exported Functions

Functions

ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Function Documentation

ErrorStatus LL_TIM_BDTR_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_BDTR_InitTypeDef * | TIM_BDTRInitStruct
 | ) |  |

Configure the Break and Dead Time feature of the timer instance.

Note:
As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.
Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not a timer instance provides a break input.
Parameters:
TIMx | Timer Instance
TIM_BDTRInitStruct | pointer to a LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Break and Dead Time is initialized
  • ERROR: not applicable

Definition at line 716 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, IS_LL_TIM_AUTOMATIC_OUTPUT_STATE, IS_LL_TIM_BREAK_POLARITY, IS_LL_TIM_BREAK_STATE, IS_LL_TIM_LOCK_LEVEL, IS_LL_TIM_OSSI_STATE, IS_LL_TIM_OSSR_STATE, LL_TIM_WriteReg, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

void LL_TIM_BDTR_StructInit ( LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct )

Set the fields of the Break and Dead Time configuration data structure to their default values.

Parameters:
TIM_BDTRInitStruct pointer to a LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
Return values:
None

Definition at line 691 of file stm32f1xx_ll_tim.c.

References LL_TIM_BDTR_InitTypeDef::AutomaticOutput, LL_TIM_BDTR_InitTypeDef::BreakPolarity, LL_TIM_BDTR_InitTypeDef::BreakState, LL_TIM_BDTR_InitTypeDef::DeadTime, LL_TIM_AUTOMATICOUTPUT_DISABLE, LL_TIM_BREAK_DISABLE, LL_TIM_BREAK_POLARITY_LOW, LL_TIM_LOCKLEVEL_OFF, LL_TIM_OSSI_DISABLE, LL_TIM_OSSR_DISABLE, LL_TIM_BDTR_InitTypeDef::LockLevel, LL_TIM_BDTR_InitTypeDef::OSSIState, and LL_TIM_BDTR_InitTypeDef::OSSRState.

ErrorStatus LL_TIM_DeInit ( TIM_TypeDef * TIMx )

Set TIMx registers to their reset values.

Parameters:
TIMx Timer instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: invalid TIMx instance

Definition at line 186 of file stm32f1xx_ll_tim.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_TIM2, LL_APB1_GRP1_PERIPH_TIM3, LL_APB1_GRP1_PERIPH_TIM4, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_TIM1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_TIM_ENCODER_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_ENCODER_InitTypeDef * | TIM_EncoderInitStruct
 | ) |  |

Configure the encoder interface of the timer instance.

Parameters:
TIMx | Timer Instance
TIM_EncoderInitStruct | pointer to a LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 524 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, IS_LL_TIM_ACTIVEINPUT, IS_LL_TIM_ENCODERMODE, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ReadReg, LL_TIM_SetEncoderMode(), and LL_TIM_WriteReg.

void LL_TIM_ENCODER_StructInit ( LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct )

Fills each TIM_EncoderInitStruct field with its default value.

Parameters:
TIM_EncoderInitStruct pointer to a LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
Return values:
None

Definition at line 502 of file stm32f1xx_ll_tim.c.

References LL_TIM_ENCODER_InitTypeDef::EncoderMode, LL_TIM_ENCODER_InitTypeDef::IC1ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC1Filter, LL_TIM_ENCODER_InitTypeDef::IC1Polarity, LL_TIM_ENCODER_InitTypeDef::IC1Prescaler, LL_TIM_ENCODER_InitTypeDef::IC2ActiveInput, LL_TIM_ENCODER_InitTypeDef::IC2Filter, LL_TIM_ENCODER_InitTypeDef::IC2Polarity, LL_TIM_ENCODER_InitTypeDef::IC2Prescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_ENCODERMODE_X2_TI1, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_HALLSENSOR_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_HALLSENSOR_InitTypeDef * | TIM_HallSensorInitStruct
 | ) |  |

Configure the Hall sensor interface of the timer instance.

Note:
TIMx CH1, CH2 and CH3 inputs connected through a XOR to the TI1 input channel
TIMx slave mode controller is configured in reset mode. Selected internal trigger is TI1F_ED.
Channel 1 is configured as input, IC1 is mapped on TRC.
Captured value stored in TIMx_CCR1 correspond to the time elapsed between 2 changes on the inputs. It gives information about motor speed.
Channel 2 is configured in output PWM 2 mode.
Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
OC2REF is selected as trigger output on TRGO.
Parameters:
TIMx | Timer Instance
TIM_HallSensorInitStruct | pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 613 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, IS_LL_TIM_IC_FILTER, IS_LL_TIM_IC_POLARITY_ENCODER, IS_LL_TIM_ICPSC, LL_TIM_ACTIVEINPUT_TRC, LL_TIM_OC_SetCompareCH2(), LL_TIM_OCMODE_PWM2, LL_TIM_ReadReg, LL_TIM_SLAVEMODE_RESET, LL_TIM_TRGO_OC2REF, LL_TIM_TS_TI1F_ED, and LL_TIM_WriteReg.

void LL_TIM_HALLSENSOR_StructInit ( LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct )

Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.

Parameters:
TIM_HallSensorInitStruct pointer to a LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
Return values:
None

Definition at line 586 of file stm32f1xx_ll_tim.c.

References LL_TIM_HALLSENSOR_InitTypeDef::CommutationDelay, LL_TIM_HALLSENSOR_InitTypeDef::IC1Filter, LL_TIM_HALLSENSOR_InitTypeDef::IC1Polarity, LL_TIM_HALLSENSOR_InitTypeDef::IC1Prescaler, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_IC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | LL_TIM_IC_InitTypeDef * | TIM_IC_InitStruct
 | ) |  |

Configure the TIMx input channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
TIM_IC_InitStruct | pointer to a LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 472 of file stm32f1xx_ll_tim.c.

References IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, and LL_TIM_CHANNEL_CH4.

void LL_TIM_IC_StructInit ( LL_TIM_IC_InitTypeDef * TIM_ICInitStruct )

Set the fields of the TIMx input channel configuration data structure to their default values.

Parameters:
TIM_ICInitStruct pointer to a LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
Return values:
None

Definition at line 450 of file stm32f1xx_ll_tim.c.

References LL_TIM_IC_InitTypeDef::ICActiveInput, LL_TIM_IC_InitTypeDef::ICFilter, LL_TIM_IC_InitTypeDef::ICPolarity, LL_TIM_IC_InitTypeDef::ICPrescaler, LL_TIM_ACTIVEINPUT_DIRECTTI, LL_TIM_IC_FILTER_FDIV1, LL_TIM_IC_POLARITY_RISING, and LL_TIM_ICPSC_DIV1.

ErrorStatus LL_TIM_Init | ( | TIM_TypeDef * | TIMx,
 |  | LL_TIM_InitTypeDef * | TIM_InitStruct
 | ) |  |

Configure the TIMx time base unit.

Parameters:
TIMx | Timer Instance
TIM_InitStruct | pointer to a LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx registers are de-initialized
  • ERROR: not applicable

Definition at line 342 of file stm32f1xx_ll_tim.c.

References assert_param, LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, IS_LL_TIM_CLOCKDIVISION, IS_LL_TIM_COUNTERMODE, LL_TIM_GenerateEvent_UPDATE(), LL_TIM_ReadReg, LL_TIM_SetAutoReload(), LL_TIM_SetPrescaler(), LL_TIM_SetRepetitionCounter(), LL_TIM_WriteReg, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

ErrorStatus LL_TIM_OC_Init | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | LL_TIM_OC_InitTypeDef * | TIM_OC_InitStruct
 | ) |  |

Configure the TIMx output channel.

Parameters:
TIMx | Timer Instance
Channel This parameter can be one of the following values:
  • LL_TIM_CHANNEL_CH1
  • LL_TIM_CHANNEL_CH2
  • LL_TIM_CHANNEL_CH3
  • LL_TIM_CHANNEL_CH4
TIM_OC_InitStruct | pointer to a LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: TIMx output channel is initialized
  • ERROR: TIMx output channel is not initialized

Definition at line 419 of file stm32f1xx_ll_tim.c.

References LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2, LL_TIM_CHANNEL_CH3, LL_TIM_CHANNEL_CH4, OC1Config(), OC2Config(), OC3Config(), and OC4Config().

void LL_TIM_OC_StructInit ( LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct )

Set the fields of the TIMx output channel configuration data structure to their default values.

Parameters:
TIM_OC_InitStruct pointer to a LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
Return values:
None

Definition at line 393 of file stm32f1xx_ll_tim.c.

References LL_TIM_OC_InitTypeDef::CompareValue, LL_TIM_OCIDLESTATE_LOW, LL_TIM_OCMODE_FROZEN, LL_TIM_OCPOLARITY_HIGH, LL_TIM_OCSTATE_DISABLE, LL_TIM_OC_InitTypeDef::OCIdleState, LL_TIM_OC_InitTypeDef::OCMode, LL_TIM_OC_InitTypeDef::OCNIdleState, LL_TIM_OC_InitTypeDef::OCNPolarity, LL_TIM_OC_InitTypeDef::OCNState, LL_TIM_OC_InitTypeDef::OCPolarity, and LL_TIM_OC_InitTypeDef::OCState.

void LL_TIM_StructInit ( LL_TIM_InitTypeDef * TIM_InitStruct )

Set the fields of the time base unit configuration data structure to their default values.

Parameters:
TIM_InitStruct pointer to a LL_TIM_InitTypeDef structure (time base unit configuration data structure)
Return values:
None

Definition at line 324 of file stm32f1xx_ll_tim.c.

References LL_TIM_InitTypeDef::Autoreload, LL_TIM_InitTypeDef::ClockDivision, LL_TIM_InitTypeDef::CounterMode, LL_TIM_CLOCKDIVISION_DIV1, LL_TIM_COUNTERMODE_UP, LL_TIM_InitTypeDef::Prescaler, and LL_TIM_InitTypeDef::RepetitionCounter.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLAG-Management

Functions
FLAG-Management
TIM

Functions

__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

Function Documentation

__STATIC_INLINE void LL_TIM_ClearFlag_BRK ( TIM_TypeDef * TIMx )

Clear the break interrupt flag (BIF).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_ClearFlag_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3083 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 interrupt flag (CC1F).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_ClearFlag_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2951 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_ClearFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3105 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 interrupt flag (CC2F).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_ClearFlag_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2973 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_ClearFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3127 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 interrupt flag (CC3F).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_ClearFlag_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2995 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_ClearFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3149 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4 ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 interrupt flag (CC4F).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_ClearFlag_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3017 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR ( TIM_TypeDef * TIMx )

Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_ClearFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3171 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_COM ( TIM_TypeDef * TIMx )

Clear the commutation interrupt flag (COMIF).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_ClearFlag_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3039 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_TRIG ( TIM_TypeDef * TIMx )

Clear the trigger interrupt flag (TIF).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_ClearFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3061 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE ( TIM_TypeDef * TIMx )

Clear the update interrupt flag (UIF).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_ClearFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 2929 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK ( TIM_TypeDef * TIMx )

Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).

Reference Manual to LL API cross reference:
SR BIF LL_TIM_IsActiveFlag_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3094 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1IF LL_TIM_IsActiveFlag_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2962 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3116 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2IF LL_TIM_IsActiveFlag_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2984 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3138 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3IF LL_TIM_IsActiveFlag_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3006 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3160 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4 ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4IF LL_TIM_IsActiveFlag_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3028 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR ( TIM_TypeDef * TIMx )

Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

Reference Manual to LL API cross reference:
SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3182 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM ( TIM_TypeDef * TIMx )

Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).

Reference Manual to LL API cross reference:
SR COMIF LL_TIM_IsActiveFlag_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3050 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG ( TIM_TypeDef * TIMx )

Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).

Reference Manual to LL API cross reference:
SR TIF LL_TIM_IsActiveFlag_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3072 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE ( TIM_TypeDef * TIMx )

Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).

Reference Manual to LL API cross reference:
SR UIF LL_TIM_IsActiveFlag_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 2940 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IT-Management

Functions
IT-Management
TIM

Functions

__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableIT_BRK ( TIM_TypeDef * TIMx )

Disable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_DisableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3442 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_DisableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3244 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_DisableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3277 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_DisableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3310 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_DisableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3343 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_COM ( TIM_TypeDef * TIMx )

Disable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_DisableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3376 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_DisableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3409 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableIT_UPDATE ( TIM_TypeDef * TIMx )

Disable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_DisableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3211 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_BRK ( TIM_TypeDef * TIMx )

Enable break interrupt (BIE).

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_EnableIT_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3431 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 interrupt (CC1IE).

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_EnableIT_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3233 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 interrupt (CC2IE).

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_EnableIT_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3266 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 interrupt (CC3IE).

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_EnableIT_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3299 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 interrupt (CC4IE).

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_EnableIT_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3332 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_COM ( TIM_TypeDef * TIMx )

Enable commutation interrupt (COMIE).

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_EnableIT_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3365 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TIE).

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_EnableIT_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3398 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableIT_UPDATE ( TIM_TypeDef * TIMx )

Enable update interrupt (UIE).

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_EnableIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3200 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK ( TIM_TypeDef * TIMx )

Indicates whether the break interrupt (BIE) is enabled.

Reference Manual to LL API cross reference:
DIER BIE LL_TIM_IsEnabledIT_BRK
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3453 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1IE LL_TIM_IsEnabledIT_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3255 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2IE LL_TIM_IsEnabledIT_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3288 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3IE LL_TIM_IsEnabledIT_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3321 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4IE LL_TIM_IsEnabledIT_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3354 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM ( TIM_TypeDef * TIMx )

Indicates whether the commutation interrupt (COMIE) is enabled.

Reference Manual to LL API cross reference:
DIER COMIE LL_TIM_IsEnabledIT_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3387 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG ( TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TIE) is enabled.

Reference Manual to LL API cross reference:
DIER TIE LL_TIM_IsEnabledIT_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3420 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE ( TIM_TypeDef * TIMx )

Indicates whether the update interrupt (UIE) is enabled.

Reference Manual to LL API cross reference:
DIER UIE LL_TIM_IsEnabledIT_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3222 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA-Management

Functions
DMA-Management
TIM

Functions

__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.

Function Documentation

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Disable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_DisableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3515 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Disable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_DisableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3548 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Disable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_DisableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3581 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Disable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_DisableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3614 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_COM ( TIM_TypeDef * TIMx )

Disable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_DisableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3647 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Disable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_DisableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3680 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Disable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_DisableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3482 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1 ( TIM_TypeDef * TIMx )

Enable capture/compare 1 DMA request (CC1DE).

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_EnableDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3504 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2 ( TIM_TypeDef * TIMx )

Enable capture/compare 2 DMA request (CC2DE).

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_EnableDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3537 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3 ( TIM_TypeDef * TIMx )

Enable capture/compare 3 DMA request (CC3DE).

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_EnableDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3570 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4 ( TIM_TypeDef * TIMx )

Enable capture/compare 4 DMA request (CC4DE).

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_EnableDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3603 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_COM ( TIM_TypeDef * TIMx )

Enable commutation DMA request (COMDE).

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_EnableDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3636 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG ( TIM_TypeDef * TIMx )

Enable trigger interrupt (TDE).

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_EnableDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3669 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Enable update DMA request (UDE).

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_EnableDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3471 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3526 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3559 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3592 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4 ( TIM_TypeDef * TIMx )

Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.

Reference Manual to LL API cross reference:
DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3625 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM ( TIM_TypeDef * TIMx )

Indicates whether the commutation DMA request (COMDE) is enabled.

Reference Manual to LL API cross reference:
DIER COMDE LL_TIM_IsEnabledDMAReq_COM
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3658 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG ( TIM_TypeDef * TIMx )

Indicates whether the trigger interrupt (TDE) is enabled.

Reference Manual to LL API cross reference:
DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3691 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE ( TIM_TypeDef * TIMx )

Indicates whether the update DMA request (UDE) is enabled.

Reference Manual to LL API cross reference:
DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
Parameters:
TIMx Timer instance
Return values:
State of bit (1 or 0).

Definition at line 3493 of file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: EVENT-Management

Functions
EVENT-Management
TIM

Functions

__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.

Function Documentation

__STATIC_INLINE void LL_TIM_GenerateEvent_BRK ( TIM_TypeDef * TIMx )

Generate break event.

Reference Manual to LL API cross reference:
EGR BG LL_TIM_GenerateEvent_BRK
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3786 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC1 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 1 event.

Reference Manual to LL API cross reference:
EGR CC1G LL_TIM_GenerateEvent_CC1
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3720 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC2 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 2 event.

Reference Manual to LL API cross reference:
EGR CC2G LL_TIM_GenerateEvent_CC2
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3731 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC3 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 3 event.

Reference Manual to LL API cross reference:
EGR CC3G LL_TIM_GenerateEvent_CC3
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3742 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_CC4 ( TIM_TypeDef * TIMx )

Generate Capture/Compare 4 event.

Reference Manual to LL API cross reference:
EGR CC4G LL_TIM_GenerateEvent_CC4
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3753 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_COM ( TIM_TypeDef * TIMx )

Generate commutation event.

Reference Manual to LL API cross reference:
EGR COMG LL_TIM_GenerateEvent_COM
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3764 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG ( TIM_TypeDef * TIMx )

Generate trigger event.

Reference Manual to LL API cross reference:
EGR TG LL_TIM_GenerateEvent_TRIG
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3775 of file stm32f1xx_ll_tim.h.

__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE ( TIM_TypeDef * TIMx )

Generate an update event.

Reference Manual to LL API cross reference:
EGR UG LL_TIM_GenerateEvent_UPDATE
Parameters:
TIMx Timer instance
Return values:
None

Definition at line 3709 of file stm32f1xx_ll_tim.h.

Referenced by LL_TIM_Init().

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART

Modules
USART
STM32F1xx_LL_Driver

Modules

USART Private Constants
USART Private Macros
USART Exported Init structures
USART Exported Constants
USART Exported Macros
USART Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for USART registers.

Register | Bit | Function
BRR | BRR | LL_USART_GetBaudRate
 |  | LL_USART_SetBaudRate
CR1 | IDLEIE | LL_USART_DisableIT_IDLE
 |  | LL_USART_EnableIT_IDLE
 |  | LL_USART_IsEnabledIT_IDLE
 | M | LL_USART_ConfigCharacter
 |  | LL_USART_GetDataWidth
 |  | LL_USART_SetDataWidth
 | PCE | LL_USART_ConfigCharacter
 |  | LL_USART_GetParity
 |  | LL_USART_SetParity
 | PEIE | LL_USART_DisableIT_PE
 |  | LL_USART_EnableIT_PE
 |  | LL_USART_IsEnabledIT_PE
 | PS | LL_USART_ConfigCharacter
 |  | LL_USART_GetParity
 |  | LL_USART_SetParity
 | RE | LL_USART_DisableDirectionRx
 |  | LL_USART_EnableDirectionRx
 |  | LL_USART_GetTransferDirection
 |  | LL_USART_SetTransferDirection
 | RWU | LL_USART_IsActiveFlag_RWU
 |  | LL_USART_RequestEnterMuteMode
 |  | LL_USART_RequestExitMuteMode
 | RXNEIE | LL_USART_DisableIT_RXNE
 |  | LL_USART_EnableIT_RXNE
 |  | LL_USART_IsEnabledIT_RXNE
 | SBK | LL_USART_IsActiveFlag_SBK
 |  | LL_USART_RequestBreakSending
 | TCIE | LL_USART_DisableIT_TC
 |  | LL_USART_EnableIT_TC
 |  | LL_USART_IsEnabledIT_TC
 | TE | LL_USART_DisableDirectionTx
 |  | LL_USART_EnableDirectionTx
 |  | LL_USART_GetTransferDirection
 |  | LL_USART_SetTransferDirection
 | TXEIE | LL_USART_DisableIT_TXE
 |  | LL_USART_EnableIT_TXE
 |  | LL_USART_IsEnabledIT_TXE
 | UE | LL_USART_Disable
 |  | LL_USART_Enable
 |  | LL_USART_IsEnabled
 | WAKE | LL_USART_GetWakeUpMethod
 |  | LL_USART_SetWakeUpMethod
CR2 | ADD | LL_USART_GetNodeAddress
 |  | LL_USART_SetNodeAddress
 | CLKEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableSCLKOutput
 |  | LL_USART_EnableSCLKOutput
 |  | LL_USART_IsEnabledSCLKOutput
 | CPHA | LL_USART_ConfigClock
 |  | LL_USART_GetClockPhase
 |  | LL_USART_SetClockPhase
 | CPOL | LL_USART_ConfigClock
 |  | LL_USART_GetClockPolarity
 |  | LL_USART_SetClockPolarity
 | LBCL | LL_USART_ConfigClock
 |  | LL_USART_GetLastClkPulseOutput
 |  | LL_USART_SetLastClkPulseOutput
 | LBDIE | LL_USART_DisableIT_LBD
 |  | LL_USART_EnableIT_LBD
 |  | LL_USART_IsEnabledIT_LBD
 | LBDL | LL_USART_GetLINBrkDetectionLen
 |  | LL_USART_SetLINBrkDetectionLen
 | LINEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableLIN
 |  | LL_USART_EnableLIN
 |  | LL_USART_IsEnabledLIN
 | STOP | LL_USART_ConfigCharacter
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_GetStopBitsLength
 |  | LL_USART_SetStopBitsLength
CR3 | CTSE | LL_USART_DisableCTSHWFlowCtrl
 |  | LL_USART_EnableCTSHWFlowCtrl
 |  | LL_USART_GetHWFlowCtrl
 |  | LL_USART_SetHWFlowCtrl
 | CTSIE | LL_USART_DisableIT_CTS
 |  | LL_USART_EnableIT_CTS
 |  | LL_USART_IsEnabledIT_CTS
 | DMAR | LL_USART_DisableDMAReq_RX
 |  | LL_USART_EnableDMAReq_RX
 |  | LL_USART_IsEnabledDMAReq_RX
 | DMAT | LL_USART_DisableDMAReq_TX
 |  | LL_USART_EnableDMAReq_TX
 |  | LL_USART_IsEnabledDMAReq_TX
 | EIE | LL_USART_DisableIT_ERROR
 |  | LL_USART_EnableIT_ERROR
 |  | LL_USART_IsEnabledIT_ERROR
 | HDSEL | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableHalfDuplex
 |  | LL_USART_EnableHalfDuplex
 |  | LL_USART_IsEnabledHalfDuplex
 | IREN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableIrda
 |  | LL_USART_EnableIrda
 |  | LL_USART_IsEnabledIrda
 | IRLP | LL_USART_GetIrdaPowerMode
 |  | LL_USART_SetIrdaPowerMode
 | NACK | LL_USART_DisableSmartcardNACK
 |  | LL_USART_EnableSmartcardNACK
 |  | LL_USART_IsEnabledSmartcardNACK
 | RTSE | LL_USART_DisableRTSHWFlowCtrl
 |  | LL_USART_EnableRTSHWFlowCtrl
 |  | LL_USART_GetHWFlowCtrl
 |  | LL_USART_SetHWFlowCtrl
 | SCEN | LL_USART_ConfigAsyncMode
 |  | LL_USART_ConfigHalfDuplexMode
 |  | LL_USART_ConfigIrdaMode
 |  | LL_USART_ConfigLINMode
 |  | LL_USART_ConfigMultiProcessMode
 |  | LL_USART_ConfigSmartcardMode
 |  | LL_USART_ConfigSyncMode
 |  | LL_USART_DisableSmartcard
 |  | LL_USART_EnableSmartcard
 |  | LL_USART_IsEnabledSmartcard
DR | DR | LL_USART_DMA_GetRegAddr
 |  | LL_USART_ReceiveData8
 |  | LL_USART_ReceiveData9
 |  | LL_USART_TransmitData8
 |  | LL_USART_TransmitData9
GTPR | GT | LL_USART_GetSmartcardGuardTime
 |  | LL_USART_SetSmartcardGuardTime
 | PSC | LL_USART_GetIrdaPrescaler
 |  | LL_USART_GetSmartcardPrescaler
 |  | LL_USART_SetIrdaPrescaler
 |  | LL_USART_SetSmartcardPrescaler
SR | CTS | LL_USART_ClearFlag_nCTS
 |  | LL_USART_IsActiveFlag_nCTS
 | FE | LL_USART_ClearFlag_FE
 |  | LL_USART_IsActiveFlag_FE
 | IDLE | LL_USART_ClearFlag_IDLE
 |  | LL_USART_IsActiveFlag_IDLE
 | LBD | LL_USART_ClearFlag_LBD
 |  | LL_USART_IsActiveFlag_LBD
 | NF | LL_USART_ClearFlag_NE
 |  | LL_USART_IsActiveFlag_NE
 | ORE | LL_USART_ClearFlag_ORE
 |  | LL_USART_IsActiveFlag_ORE
 | PE | LL_USART_ClearFlag_PE
 |  | LL_USART_IsActiveFlag_PE
 | RXNE | LL_USART_ClearFlag_RXNE
 |  | LL_USART_IsActiveFlag_RXNE
 | TC | LL_USART_ClearFlag_TC
 |  | LL_USART_IsActiveFlag_TC
 | TXE | LL_USART_IsActiveFlag_TXE
Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos

Define Documentation

#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos

Definition at line 68 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_GetSmartcardGuardTime(), and LL_USART_SetSmartcardGuardTime().

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Define Documentation

#define IS_LL_USART_BAUDRATE ( __BAUDRATE__ ) ((__BAUDRATE__) <= 10000000U)

Definition at line 78 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_CLOCKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_CLOCK_DISABLE) \
                                         || ((__VALUE__) == LL_USART_CLOCK_ENABLE))

Definition at line 104 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPHASE ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PHASE_1EDGE) \
                                        || ((__VALUE__) == LL_USART_PHASE_2EDGE))

Definition at line 98 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_CLOCKPOLARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_POLARITY_LOW) \
                                           || ((__VALUE__) == LL_USART_POLARITY_HIGH))

Definition at line 101 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_DATAWIDTH ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DATAWIDTH_8B) \
                                       || ((__VALUE__) == LL_USART_DATAWIDTH_9B))

Definition at line 89 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_DIRECTION ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_DIRECTION_NONE) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_RX) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_TX) \
                                       || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))

Definition at line 80 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_HWCONTROL ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_HWCONTROL_NONE) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))

Definition at line 112 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_LASTBITCLKOUTPUT ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
                                              || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))

Definition at line 95 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_ClockInit().

#define IS_LL_USART_OVERSAMPLING ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_OVERSAMPLING_16) \
                                          || ((__VALUE__) == LL_USART_OVERSAMPLING_8))

Definition at line 92 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_PARITY ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_PARITY_NONE) \
                                    || ((__VALUE__) == LL_USART_PARITY_EVEN) \
                                    || ((__VALUE__) == LL_USART_PARITY_ODD))

Definition at line 85 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_Init().

#define IS_LL_USART_STOPBITS ( __VALUE__ )
Value:
(((__VALUE__) == LL_USART_STOPBITS_0_5) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_1) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
                                      || ((__VALUE__) == LL_USART_STOPBITS_2))

Definition at line 107 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_Init().

Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_InitTypeDef Struct Reference
USART Exported Init structures

LL USART Init Structure definition. More...

#include <stm32f1xx_ll_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | DataWidth
uint32_t | StopBits
uint32_t | Parity
uint32_t | TransferDirection
uint32_t | HardwareFlowControl

Detailed Description

LL USART Init Structure definition.

Definition at line 92 of file stm32f1xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_InitTypeDef::BaudRate

This field defines expected Usart communication baud rate.

This feature can be modified afterwards using unitary function LL_USART_SetBaudRate().

Definition at line 94 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::DataWidth

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of Datawidth.

This feature can be modified afterwards using unitary function LL_USART_SetDataWidth().

Definition at line 98 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::HardwareFlowControl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of Hardware Control.

This feature can be modified afterwards using unitary function LL_USART_SetHWFlowCtrl().

Definition at line 118 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of Parity Control.

This feature can be modified afterwards using unitary function LL_USART_SetParity().

Definition at line 108 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of Stop Bits.

This feature can be modified afterwards using unitary function LL_USART_SetStopBitsLength().

Definition at line 103 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

uint32_t LL_USART_InitTypeDef::TransferDirection

Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of Communication Direction.

This feature can be modified afterwards using unitary function LL_USART_SetTransferDirection().

Definition at line 113 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_Init(), and LL_USART_StructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_usart.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_USART_ClockInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_USART_ClockInitTypeDef Struct Reference
USART Exported Init structures

LL USART Clock Init Structure definition. More...

#include <stm32f1xx_ll_usart.h>

Data Fields

uint32_t | ClockOutput
uint32_t | ClockPolarity
uint32_t | ClockPhase
uint32_t | LastBitClockPulse

Detailed Description

LL USART Clock Init Structure definition.

Definition at line 135 of file stm32f1xx_ll_usart.h.

Field Documentation

uint32_t LL_USART_ClockInitTypeDef::ClockOutput

Specifies whether the USART clock is enabled or disabled. This parameter can be a value of Clock Signal.

USART HW configuration can be modified afterwards using unitary functions LL_USART_EnableSCLKOutput() or LL_USART_DisableSCLKOutput(). For more details, refer to description of this function.

Definition at line 137 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of Clock Phase.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPhase(). For more details, refer to description of this function.

Definition at line 150 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::ClockPolarity

Specifies the steady state of the serial clock. This parameter can be a value of Clock Polarity.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetClockPolarity(). For more details, refer to description of this function.

Definition at line 144 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

uint32_t LL_USART_ClockInitTypeDef::LastBitClockPulse

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of Last Clock Pulse.

USART HW configuration can be modified afterwards using unitary functions LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function.

Definition at line 156 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_usart.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Get Flags Defines

Defines
Get Flags Defines
USART Exported Constants

Flags defines which can be used with LL_USART_ReadReg function. More...

Defines

#define | LL_USART_SR_PE USART_SR_PE
#define | LL_USART_SR_FE USART_SR_FE
#define | LL_USART_SR_NE USART_SR_NE
#define | LL_USART_SR_ORE USART_SR_ORE
#define | LL_USART_SR_IDLE USART_SR_IDLE
#define | LL_USART_SR_RXNE USART_SR_RXNE
#define | LL_USART_SR_TC USART_SR_TC
#define | LL_USART_SR_TXE USART_SR_TXE
#define | LL_USART_SR_LBD USART_SR_LBD
#define | LL_USART_SR_CTS USART_SR_CTS

Detailed Description

Flags defines which can be used with LL_USART_ReadReg function.

Define Documentation

#define LL_USART_SR_CTS USART_SR_CTS

CTS flag

Definition at line 188 of file stm32f1xx_ll_usart.h.

#define LL_USART_SR_FE USART_SR_FE

Framing error flag

Definition at line 180 of file stm32f1xx_ll_usart.h.

#define LL_USART_SR_IDLE USART_SR_IDLE

Idle line detected flag

Definition at line 183 of file stm32f1xx_ll_usart.h.

#define LL_USART_SR_LBD USART_SR_LBD

LIN break detection flag

Definition at line 187 of file stm32f1xx_ll_usart.h.

#define LL_USART_SR_NE USART_SR_NE

Noise detected flag

Definition at line 181 of file stm32f1xx_ll_usart.h.

#define LL_USART_SR_ORE USART_SR_ORE

Overrun error flag

Definition at line 182 of file stm32f1xx_ll_usart.h.

#define LL_USART_SR_PE USART_SR_PE

Parity error flag

Definition at line 179 of file stm32f1xx_ll_usart.h.

#define LL_USART_SR_RXNE USART_SR_RXNE

Read data register not empty flag

Definition at line 184 of file stm32f1xx_ll_usart.h.

#define LL_USART_SR_TC USART_SR_TC

Transmission complete flag

Definition at line 185 of file stm32f1xx_ll_usart.h.

#define LL_USART_SR_TXE USART_SR_TXE

Transmit data register empty flag

Definition at line 186 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: IT Defines

Defines
IT Defines
USART Exported Constants

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions. More...

Defines

#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE USART_CR1_RXNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE USART_CR1_TXEIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE

Detailed Description

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

Define Documentation

#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE

IDLE interrupt enable

Definition at line 197 of file stm32f1xx_ll_usart.h.

#define LL_USART_CR1_PEIE USART_CR1_PEIE

Parity error

Definition at line 201 of file stm32f1xx_ll_usart.h.

#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE

Read data register not empty interrupt enable

Definition at line 198 of file stm32f1xx_ll_usart.h.

#define LL_USART_CR1_TCIE USART_CR1_TCIE

Transmission complete interrupt enable

Definition at line 199 of file stm32f1xx_ll_usart.h.

#define LL_USART_CR1_TXEIE USART_CR1_TXEIE

Transmit data register empty interrupt enable

Definition at line 200 of file stm32f1xx_ll_usart.h.

#define LL_USART_CR2_LBDIE USART_CR2_LBDIE

LIN break detection interrupt enable

Definition at line 202 of file stm32f1xx_ll_usart.h.

#define LL_USART_CR3_CTSIE USART_CR3_CTSIE

CTS interrupt enable

Definition at line 204 of file stm32f1xx_ll_usart.h.

#define LL_USART_CR3_EIE USART_CR3_EIE

Error interrupt enable

Definition at line 203 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: Communication Direction

Defines
Communication Direction
USART Exported Constants

Defines

#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Define Documentation

#define LL_USART_DIRECTION_NONE 0x00000000U

Transmitter and Receiver are disabled

Definition at line 212 of file stm32f1xx_ll_usart.h.

#define LL_USART_DIRECTION_RX USART_CR1_RE

Transmitter is disabled and Receiver is enabled

Definition at line 213 of file stm32f1xx_ll_usart.h.

#define LL_USART_DIRECTION_TX USART_CR1_TE

Transmitter is enabled and Receiver is disabled

Definition at line 214 of file stm32f1xx_ll_usart.h.

#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)

Transmitter and Receiver are enabled

Definition at line 215 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_StructInit().

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STM32F103xB HAL User Manual: Parity Control

Defines
Parity Control
USART Exported Constants

Defines

#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Define Documentation

#define LL_USART_PARITY_EVEN USART_CR1_PCE

Parity control enabled and Even Parity is selected

Definition at line 224 of file stm32f1xx_ll_usart.h.

#define LL_USART_PARITY_NONE 0x00000000U

Parity control disabled

Definition at line 223 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)

Parity control enabled and Odd Parity is selected

Definition at line 225 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: Wakeup

Defines
Wakeup
USART Exported Constants

Defines

#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

Define Documentation

#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE

USART wake up from Mute mode on Address Mark

Definition at line 234 of file stm32f1xx_ll_usart.h.

#define LL_USART_WAKEUP_IDLELINE 0x00000000U

USART wake up from Mute mode on Idle Line

Definition at line 233 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: Datawidth

Defines
Datawidth
USART Exported Constants

Defines

#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M

Define Documentation

#define LL_USART_DATAWIDTH_8B 0x00000000U

8 bits word length : Start bit, 8 data bits, n stop bits

Definition at line 242 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_DATAWIDTH_9B USART_CR1_M

9 bits word length : Start bit, 9 data bits, n stop bits

Definition at line 243 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: Clock Signal

Defines
Clock Signal
USART Exported Constants

Defines

#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Define Documentation

#define LL_USART_CLOCK_DISABLE 0x00000000U

Clock signal not provided

Definition at line 264 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_ClockStructInit().

#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN

Clock signal provided

Definition at line 265 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: Last Clock Pulse

Defines
Last Clock Pulse
USART Exported Constants

Defines

#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

Define Documentation

#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U

The clock pulse of the last data bit is not output to the SCLK pin

Definition at line 274 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL

The clock pulse of the last data bit is output to the SCLK pin

Definition at line 275 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: Clock Phase

Defines
Clock Phase
USART Exported Constants

Defines

#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA

Define Documentation

#define LL_USART_PHASE_1EDGE 0x00000000U

The first clock transition is the first data capture edge

Definition at line 283 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

#define LL_USART_PHASE_2EDGE USART_CR2_CPHA

The second clock transition is the first data capture edge

Definition at line 284 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: Clock Polarity

Defines
Clock Polarity
USART Exported Constants

Defines

#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL

Define Documentation

#define LL_USART_POLARITY_HIGH USART_CR2_CPOL

Steady high value on SCLK pin outside transmission window

Definition at line 293 of file stm32f1xx_ll_usart.h.

#define LL_USART_POLARITY_LOW 0x00000000U

Steady low value on SCLK pin outside transmission window

Definition at line 292 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_ClockStructInit().

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STM32F103xB HAL User Manual: Stop Bits

Defines
Stop Bits
USART Exported Constants

Defines

#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1

Define Documentation

#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0

0.5 stop bit

Definition at line 301 of file stm32f1xx_ll_usart.h.

#define LL_USART_STOPBITS_1 0x00000000U

1 stop bit

Definition at line 302 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)

1.5 stop bits

Definition at line 303 of file stm32f1xx_ll_usart.h.

#define LL_USART_STOPBITS_2 USART_CR2_STOP_1

2 stop bits

Definition at line 304 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: Hardware Control

Defines
Hardware Control
USART Exported Constants

Defines

#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

Define Documentation

#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE

CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0)

Definition at line 314 of file stm32f1xx_ll_usart.h.

#define LL_USART_HWCONTROL_NONE 0x00000000U

CTS and RTS hardware flow control disabled

Definition at line 312 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_StructInit().

#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE

RTS output enabled, data is only requested when there is space in the receive buffer

Definition at line 313 of file stm32f1xx_ll_usart.h.

#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)

CTS and RTS hardware flow control enabled

Definition at line 315 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: IrDA Power

Defines
IrDA Power
USART Exported Constants

Defines

#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

Define Documentation

#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP

IrDA low power mode

Definition at line 324 of file stm32f1xx_ll_usart.h.

#define LL_USART_IRDA_POWER_NORMAL 0x00000000U

IrDA normal power mode

Definition at line 323 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: LIN Break Detection Length

Defines
LIN Break Detection Length
USART Exported Constants

Defines

#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

Define Documentation

#define LL_USART_LINBREAK_DETECT_10B 0x00000000U

10-bit break detection method selected

Definition at line 332 of file stm32f1xx_ll_usart.h.

#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL

11-bit break detection method selected

Definition at line 333 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: Common Write and read registers Macros

Defines
Common Write and read registers Macros
USART Exported Macros

Defines

#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.

Define Documentation

#define LL_USART_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 366 of file stm32f1xx_ll_usart.h.

#define LL_USART_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in USART register.

Parameters:
__INSTANCE__ | USART Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 358 of file stm32f1xx_ll_usart.h.

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STM32F103xB HAL User Manual: Exported_Macros_Helper

Defines
Exported_Macros_Helper
USART Exported Macros

Defines

#define | __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
#define | __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)
#define | __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
#define | __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)

Define Documentation

#define __LL_USART_DIV_SAMPLING16 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) |
Value:
(((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))

Definition at line 403 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_SetBaudRate().

#define __LL_USART_DIV_SAMPLING16_100 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_16 case

Definition at line 398 of file stm32f1xx_ll_usart.h.

#define __LL_USART_DIV_SAMPLING8 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) |
Value:
(((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
                                                                           ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
                                                                           (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))

Definition at line 387 of file stm32f1xx_ll_usart.h.

#define __LL_USART_DIV_SAMPLING8_100 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))

Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)

Parameters:
__PERIPHCLK__ | Peripheral Clock frequency used for USART instance
__BAUDRATE__ | Baud rate value to achieve
Return values:
USARTDIV value to be used for BRR register filling in OverSampling_8 case

Definition at line 382 of file stm32f1xx_ll_usart.h.

#define __LL_USART_DIVFRAQ_SAMPLING16 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)

Definition at line 400 of file stm32f1xx_ll_usart.h.

#define __LL_USART_DIVFRAQ_SAMPLING8 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)

Definition at line 384 of file stm32f1xx_ll_usart.h.

#define __LL_USART_DIVMANT_SAMPLING16 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)

Definition at line 399 of file stm32f1xx_ll_usart.h.

#define __LL_USART_DIVMANT_SAMPLING8 | ( | __PERIPHCLK__,
 |  | __BAUDRATE__
 | ) | (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)

Definition at line 383 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration functions

Functions
Configuration functions
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetNodeAddress (USART_TypeDef *USARTx, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (USART_TypeDef *USARTx)
Return 4 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.

Function Documentation

__STATIC_INLINE void LL_USART_ConfigCharacter | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth,
 |  | uint32_t | Parity,
 |  | uint32_t | StopBits
 | ) |  |

Configure Character frame format (Datawidth, Parity control, Stop Bits)

Note:
Call of this function is equivalent to following function call sequence :
  • Data Width configuration using LL_USART_SetDataWidth() function
  • Parity Control and mode configuration using LL_USART_SetParity() function
  • Stop bits configuration using LL_USART_SetStopBitsLength() function
Reference Manual to LL API cross reference:
CR1 PS LL_USART_ConfigCharacter
CR1 PCE LL_USART_ConfigCharacter
CR1 M LL_USART_ConfigCharacter
CR2 STOP LL_USART_ConfigCharacter
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 873 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigClock | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Phase,
 |  | uint32_t | Polarity,
 |  | uint32_t | LBCPOutput
 | ) |  |

Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clock Phase configuration using LL_USART_SetClockPhase() function
  • Clock Polarity configuration using LL_USART_SetClockPolarity() function
  • Output of Last bit Clock pulse configuration using LL_USART_SetLastClkPulseOutput() function
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_ConfigClock
CR2 CPOL LL_USART_ConfigClock
CR2 LBCL LL_USART_ConfigClock
Parameters:
USARTx USART Instance
Phase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Polarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
LBCPOutput This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 773 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_Disable ( USART_TypeDef * USARTx )

USART Disable (all USART prescalers and outputs are disabled)

Note:
When USART is disabled, USART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the USART is kept, but all the status flags, in the USARTx_SR are set to their default values.
Reference Manual to LL API cross reference:
CR1 UE LL_USART_Disable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 445 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 953 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionRx ( USART_TypeDef * USARTx )

Receiver Disable.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_DisableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 478 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Disable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_DisableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 500 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Disable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 927 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSCLKOutput ( USART_TypeDef * USARTx )

Disable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_DisableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 799 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_ClockInit().

__STATIC_INLINE void LL_USART_Enable ( USART_TypeDef * USARTx )

USART Enable.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_Enable
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 431 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable CTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 940 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionRx ( USART_TypeDef * USARTx )

Receiver Enable (Receiver is enabled and begins searching for a start bit)

Reference Manual to LL API cross reference:
CR1 RE LL_USART_EnableDirectionRx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 467 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDirectionTx ( USART_TypeDef * USARTx )

Transmitter Enable.

Reference Manual to LL API cross reference:
CR1 TE LL_USART_EnableDirectionTx
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 489 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl ( USART_TypeDef * USARTx )

Enable RTS HW Flow Control.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 914 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSCLKOutput ( USART_TypeDef * USARTx )

Enable Clock output on SCLK pin.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_EnableSCLKOutput
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 786 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk
 | ) |  |

Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.

Note:
In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
Reference Manual to LL API cross reference:
BRR BRR LL_USART_GetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
Return values:
Baud Rate

Definition at line 1122 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPhase ( USART_TypeDef * USARTx )

Return phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_GetClockPhase
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE

Definition at line 714 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetClockPolarity ( USART_TypeDef * USARTx )

Return polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_GetClockPolarity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH

Definition at line 745 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetDataWidth ( USART_TypeDef * USARTx )

Return Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_USART_GetDataWidth
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B

Definition at line 622 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl ( USART_TypeDef * USARTx )

Return HW Flow Control configuration (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_GetHWFlowCtrl
CR3 CTSE LL_USART_GetHWFlowCtrl
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS

Definition at line 990 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput ( USART_TypeDef * USARTx )

Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_GetLastClkPulseOutput
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT

Definition at line 683 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetNodeAddress ( USART_TypeDef * USARTx )

Return 4 bit Address of the USART node as set in ADD field of CR2.

Note:
only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_GetNodeAddress
Parameters:
USARTx USART Instance
Return values:
Address of the USART node (Value between Min_Data=0 and Max_Data=255)

Definition at line 901 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetParity ( USART_TypeDef * USARTx )

Return Parity configuration (enabled/disabled and parity mode if enabled)

Reference Manual to LL API cross reference:
CR1 PS LL_USART_GetParity
CR1 PCE LL_USART_GetParity
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD

Definition at line 568 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength ( USART_TypeDef * USARTx )

Retrieve the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_GetStopBitsLength
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2

Definition at line 843 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetTransferDirection ( USART_TypeDef * USARTx )

Return enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_GetTransferDirection
CR1 TE LL_USART_GetTransferDirection
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX

Definition at line 534 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod ( USART_TypeDef * USARTx )

Return Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_GetWakeUpMethod
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK

Definition at line 595 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabled ( USART_TypeDef * USARTx )

Indicate if USART is enabled.

Reference Manual to LL API cross reference:
CR1 UE LL_USART_IsEnabled
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 456 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_ClockInit(), and LL_USART_Init().

__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput ( USART_TypeDef * USARTx )

Indicate if Clock output on SCLK pin is enabled.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_IsEnabledSCLKOutput
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 812 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetBaudRate | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PeriphClk,
 |  | uint32_t | BaudRate
 | ) |  |

Configure USART BRR register for achieving expected Baud Rate value.

Note:
Compute and set USARTDIV value in BRR Register (full BRR content) according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
Peripheral clock and Baud rate values provided as function parameters should be valid (Baud rate value != 0)
Reference Manual to LL API cross reference:
BRR BRR LL_USART_SetBaudRate
Parameters:
USARTx | USART Instance
PeriphClk | Peripheral Clock
BaudRate | Baud Rate
Return values:
None

Definition at line 1108 of file stm32f1xx_ll_usart.h.

References __LL_USART_DIV_SAMPLING16.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetClockPhase | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPhase
 | ) |  |

Select the phase of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPHA LL_USART_SetClockPhase
Parameters:
USARTx USART Instance
ClockPhase This parameter can be one of the following values:
  • LL_USART_PHASE_1EDGE
  • LL_USART_PHASE_2EDGE
Return values:
None

Definition at line 699 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetClockPolarity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | ClockPolarity
 | ) |  |

Select the polarity of the clock output on the SCLK pin in synchronous mode.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 CPOL LL_USART_SetClockPolarity
Parameters:
USARTx USART Instance
ClockPolarity This parameter can be one of the following values:
  • LL_USART_POLARITY_LOW
  • LL_USART_POLARITY_HIGH
Return values:
None

Definition at line 730 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetDataWidth | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | DataWidth
 | ) |  |

Set Word length (i.e.

nb of data bits, excluding start and stop bits)

Reference Manual to LL API cross reference:
CR1 M LL_USART_SetDataWidth
Parameters:
USARTx USART Instance
DataWidth This parameter can be one of the following values:
  • LL_USART_DATAWIDTH_8B
  • LL_USART_DATAWIDTH_9B
Return values:
None

Definition at line 609 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetHWFlowCtrl | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | HardwareFlowControl
 | ) |  |

Configure HW Flow Control mode (both CTS and RTS)

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 RTSE LL_USART_SetHWFlowCtrl
CR3 CTSE LL_USART_SetHWFlowCtrl
Parameters:
USARTx USART Instance
HardwareFlowControl This parameter can be one of the following values:
  • LL_USART_HWCONTROL_NONE
  • LL_USART_HWCONTROL_RTS
  • LL_USART_HWCONTROL_CTS
  • LL_USART_HWCONTROL_RTS_CTS
Return values:
None

Definition at line 972 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetLastClkPulseOutput | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LastBitClockPulse
 | ) |  |

Configure if Clock pulse of the last data bit is output to the SCLK pin or not.

Note:
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBCL LL_USART_SetLastClkPulseOutput
Parameters:
USARTx USART Instance
LastBitClockPulse This parameter can be one of the following values:
  • LL_USART_LASTCLKPULSE_NO_OUTPUT
  • LL_USART_LASTCLKPULSE_OUTPUT
Return values:
None

Definition at line 667 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetNodeAddress | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | NodeAddress
 | ) |  |

Set Address of the USART node.

Note:
This is used in multiprocessor communication during Mute mode or Stop mode, for wake up with address mark detection.
Reference Manual to LL API cross reference:
CR2 ADD LL_USART_SetNodeAddress
Parameters:
USARTx | USART Instance
NodeAddress | 4 bit Address of the USART node.
Return values:
None

Definition at line 889 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetParity | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Parity
 | ) |  |

Configure Parity (enabled/disabled and parity mode if enabled).

Note:
This function selects if hardware parity control (generation and detection) is enabled or disabled. When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position (9th or 8th bit depending on data width) and parity is checked on the received data.
Reference Manual to LL API cross reference:
CR1 PS LL_USART_SetParity
CR1 PCE LL_USART_SetParity
Parameters:
USARTx USART Instance
Parity This parameter can be one of the following values:
  • LL_USART_PARITY_NONE
  • LL_USART_PARITY_EVEN
  • LL_USART_PARITY_ODD
Return values:
None

Definition at line 553 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetStopBitsLength | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | StopBits
 | ) |  |

Set the length of the stop bits.

Reference Manual to LL API cross reference:
CR2 STOP LL_USART_SetStopBitsLength
Parameters:
USARTx USART Instance
StopBits This parameter can be one of the following values:
  • LL_USART_STOPBITS_0_5
  • LL_USART_STOPBITS_1
  • LL_USART_STOPBITS_1_5
  • LL_USART_STOPBITS_2
Return values:
None

Definition at line 828 of file stm32f1xx_ll_usart.h.

Referenced by LL_USART_Init().

__STATIC_INLINE void LL_USART_SetTransferDirection | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | TransferDirection
 | ) |  |

Configure simultaneously enabled/disabled states of Transmitter and Receiver.

Reference Manual to LL API cross reference:
CR1 RE LL_USART_SetTransferDirection
CR1 TE LL_USART_SetTransferDirection
Parameters:
USARTx USART Instance
TransferDirection This parameter can be one of the following values:
  • LL_USART_DIRECTION_NONE
  • LL_USART_DIRECTION_RX
  • LL_USART_DIRECTION_TX
  • LL_USART_DIRECTION_TX_RX
Return values:
None

Definition at line 518 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetWakeUpMethod | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | Method
 | ) |  |

Set Receiver Wake Up method from Mute mode.

Reference Manual to LL API cross reference:
CR1 WAKE LL_USART_SetWakeUpMethod
Parameters:
USARTx USART Instance
Method This parameter can be one of the following values:
  • LL_USART_WAKEUP_IDLELINE
  • LL_USART_WAKEUP_ADDRESSMARK
Return values:
None

Definition at line 582 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration functions related to Irda feature

Functions
Configuration functions related to Irda feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableIrda ( USART_TypeDef * USARTx )

Disable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_DisableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1166 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIrda ( USART_TypeDef * USARTx )

Enable IrDA mode.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_EnableIrda
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1153 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode ( USART_TypeDef * USARTx )

Retrieve IrDA Power Mode configuration (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_GetIrdaPowerMode
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_PHASE_2EDGE

Definition at line 1210 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler ( USART_TypeDef * USARTx )

Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetIrdaPrescaler
Parameters:
USARTx USART Instance
Return values:
Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 1239 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda ( USART_TypeDef * USARTx )

Indicate if IrDA mode is enabled.

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IREN LL_USART_IsEnabledIrda
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1179 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPowerMode | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PowerMode
 | ) |  |

Configure IrDA Power Mode (Normal or Low Power)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 IRLP LL_USART_SetIrdaPowerMode
Parameters:
USARTx USART Instance
PowerMode This parameter can be one of the following values:
  • LL_USART_IRDA_POWER_NORMAL
  • LL_USART_IRDA_POWER_LOW
Return values:
None

Definition at line 1195 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetIrdaPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)

Note:
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetIrdaPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1225 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration functions related to Smartcard feature

Functions
Configuration functions related to Smartcard feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Function Documentation

__STATIC_INLINE void LL_USART_DisableSmartcard ( USART_TypeDef * USARTx )

Disable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_DisableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1312 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableSmartcardNACK ( USART_TypeDef * USARTx )

Disable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_DisableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1273 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcard ( USART_TypeDef * USARTx )

Enable Smartcard mode.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_EnableSmartcard
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1299 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableSmartcardNACK ( USART_TypeDef * USARTx )

Enable Smartcard NACK transmission.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_EnableSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1260 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime ( USART_TypeDef * USARTx )

Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_GetSmartcardGuardTime
Parameters:
USARTx USART Instance
Return values:
Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)

Definition at line 1383 of file stm32f1xx_ll_usart.h.

References USART_POSITION_GTPR_GT.

__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler ( USART_TypeDef * USARTx )

Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_GetSmartcardPrescaler
Parameters:
USARTx USART Instance
Return values:
Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)

Definition at line 1354 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard ( USART_TypeDef * USARTx )

Indicate if Smartcard mode is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 SCEN LL_USART_IsEnabledSmartcard
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1325 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK ( USART_TypeDef * USARTx )

Indicate if Smartcard NACK transmission is enabled.

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 NACK LL_USART_IsEnabledSmartcardNACK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1286 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetSmartcardGuardTime | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | GuardTime
 | ) |  |

Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR GT LL_USART_SetSmartcardGuardTime
Parameters:
USARTx | USART Instance
GuardTime | Value between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 1369 of file stm32f1xx_ll_usart.h.

References USART_POSITION_GTPR_GT.

__STATIC_INLINE void LL_USART_SetSmartcardPrescaler | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | PrescalerValue
 | ) |  |

Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)

Note:
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
GTPR PSC LL_USART_SetSmartcardPrescaler
Parameters:
USARTx | USART Instance
PrescalerValue | Value between Min_Data=0 and Max_Data=31
Return values:
None

Definition at line 1340 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration functions related to Half Duplex feature

Functions
Configuration functions related to Half Duplex feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableHalfDuplex ( USART_TypeDef * USARTx )

Disable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_DisableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1417 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableHalfDuplex ( USART_TypeDef * USARTx )

Enable Single Wire Half-Duplex mode.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_EnableHalfDuplex
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1404 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex ( USART_TypeDef * USARTx )

Indicate if Single Wire Half-Duplex mode is enabled.

Note:
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 HDSEL LL_USART_IsEnabledHalfDuplex
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1430 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration functions related to LIN feature

Functions
Configuration functions related to LIN feature
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableLIN ( USART_TypeDef * USARTx )

Disable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_DisableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1495 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableLIN ( USART_TypeDef * USARTx )

Enable LIN mode.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_EnableLIN
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1482 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen ( USART_TypeDef * USARTx )

Return LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_GetLINBrkDetectionLen
Parameters:
USARTx USART Instance
Return values:
Returned value can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B

Definition at line 1469 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN ( USART_TypeDef * USARTx )

Indicate if LIN mode is enabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_IsEnabledLIN
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1508 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen | ( | USART_TypeDef * | USARTx,
 |  | uint32_t | LINBDLength
 | ) |  |

Set LIN Break Detection Length.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDL LL_USART_SetLINBrkDetectionLen
Parameters:
USARTx USART Instance
LINBDLength This parameter can be one of the following values:
  • LL_USART_LINBREAK_DETECT_10B
  • LL_USART_LINBREAK_DETECT_11B
Return values:
None

Definition at line 1454 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Advanced Configurations services

Functions
Advanced Configurations services
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Function Documentation

__STATIC_INLINE void LL_USART_ConfigAsyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)

Note:
In UART mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Asynchronous Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigAsyncMode
CR2 CLKEN LL_USART_ConfigAsyncMode
CR3 SCEN LL_USART_ConfigAsyncMode
CR3 IREN LL_USART_ConfigAsyncMode
CR3 HDSEL LL_USART_ConfigAsyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1546 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Half Duplex Mode.

Note:
In Half Duplex mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register, This function also sets the UART/USART in Half Duplex mode.
Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not Half-Duplex mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Set HDSEL in CR3 using LL_USART_EnableHalfDuplex() function
Other remaining configurations items related to Half Duplex Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigHalfDuplexMode
CR2 CLKEN LL_USART_ConfigHalfDuplexMode
CR3 HDSEL LL_USART_ConfigHalfDuplexMode
CR3 SCEN LL_USART_ConfigHalfDuplexMode
CR3 IREN LL_USART_ConfigHalfDuplexMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1660 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigIrdaMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Irda Mode.

Note:
In IRDA mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the UART/USART in IRDA mode (IREN bit).
Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not IrDA feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set IREN in CR3 using LL_USART_EnableIrda() function
Other remaining configurations items related to Irda Mode (as Baud Rate, Word length, Power mode, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigIrdaMode
CR2 CLKEN LL_USART_ConfigIrdaMode
CR2 STOP LL_USART_ConfigIrdaMode
CR3 SCEN LL_USART_ConfigIrdaMode
CR3 HDSEL LL_USART_ConfigIrdaMode
CR3 IREN LL_USART_ConfigIrdaMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1743 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigLINMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in LIN Mode.

Note:
In LIN mode, the following bits must be kept cleared:
  • STOP and CLKEN bits in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also set the UART/USART in LIN mode.
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set LINEN in CR2 using LL_USART_EnableLIN() function
Other remaining configurations items related to LIN Mode (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 CLKEN LL_USART_ConfigLINMode
CR2 STOP LL_USART_ConfigLINMode
CR2 LINEN LL_USART_ConfigLINMode
CR3 IREN LL_USART_ConfigLINMode
CR3 SCEN LL_USART_ConfigLINMode
CR3 HDSEL LL_USART_ConfigLINMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1622 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigMultiProcessMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).

Note:
In MultiProcessor mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • CLKEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear CLKEN in CR2 using LL_USART_DisableSCLKOutput() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
Other remaining configurations items related to Multi processor Mode (as Baud Rate, Wake Up Method, Node address, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigMultiProcessMode
CR2 CLKEN LL_USART_ConfigMultiProcessMode
CR3 SCEN LL_USART_ConfigMultiProcessMode
CR3 HDSEL LL_USART_ConfigMultiProcessMode
CR3 IREN LL_USART_ConfigMultiProcessMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1781 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSmartcardMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Smartcard Mode.

Note:
In Smartcard mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also configures Stop bits to 1.5 bits and sets the USART in Smartcard mode (SCEN bit). Clock Output is also enabled (CLKEN).
Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not Smartcard feature is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Configure STOP in CR2 using LL_USART_SetStopBitsLength() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
  • Set SCEN in CR3 using LL_USART_EnableSmartcard() function
Other remaining configurations items related to Smartcard Mode (as Baud Rate, Word length, Parity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSmartcardMode
CR2 STOP LL_USART_ConfigSmartcardMode
CR2 CLKEN LL_USART_ConfigSmartcardMode
CR3 HDSEL LL_USART_ConfigSmartcardMode
CR3 SCEN LL_USART_ConfigSmartcardMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1700 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ConfigSyncMode ( USART_TypeDef * USARTx )

Perform basic configuration of USART for enabling use in Synchronous Mode.

Note:
In Synchronous mode, the following bits must be kept cleared:
  • LINEN bit in the USART_CR2 register,
  • SCEN bit in the USART_CR3 register,
  • IREN bit in the USART_CR3 register,
  • HDSEL bit in the USART_CR3 register. This function also sets the USART in Synchronous mode.
Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not Synchronous mode is supported by the USARTx instance.
Call of this function is equivalent to following function call sequence :
  • Clear LINEN in CR2 using LL_USART_DisableLIN() function
  • Clear IREN in CR3 using LL_USART_DisableIrda() function
  • Clear SCEN in CR3 using LL_USART_DisableSmartcard() function
  • Clear HDSEL in CR3 using LL_USART_DisableHalfDuplex() function
  • Set CLKEN in CR2 using LL_USART_EnableSCLKOutput() function
Other remaining configurations items related to Synchronous Mode (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using dedicated functions
Reference Manual to LL API cross reference:
CR2 LINEN LL_USART_ConfigSyncMode
CR2 CLKEN LL_USART_ConfigSyncMode
CR3 SCEN LL_USART_ConfigSyncMode
CR3 IREN LL_USART_ConfigSyncMode
CR3 HDSEL LL_USART_ConfigSyncMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1582 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLAG_Management

Functions
FLAG_Management
USART Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE (USART_TypeDef *USARTx)
Check if the USART Read Data Register Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE (USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RXNE (USART_TypeDef *USARTx)
Clear RX Not Empty Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.

Function Documentation

__STATIC_INLINE void LL_USART_ClearFlag_FE ( USART_TypeDef * USARTx )

Clear Framing Error Flag.

Note:
Clearing this flag is done by a read access to the USARTx_SR register followed by a read access to the USARTx_DR register.
Please also consider that when clearing this flag, other flags as PE, NE, ORE, IDLE would also be cleared.
Reference Manual to LL API cross reference:
SR FE LL_USART_ClearFlag_FE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1963 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_IDLE ( USART_TypeDef * USARTx )

Clear IDLE line detected Flag.

Note:
Clearing this flag is done by a read access to the USARTx_SR register followed by a read access to the USARTx_DR register.
Please also consider that when clearing this flag, other flags as PE, NE, FE, ORE would also be cleared.
Reference Manual to LL API cross reference:
SR IDLE LL_USART_ClearFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2020 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_LBD ( USART_TypeDef * USARTx )

Clear LIN Break Detection Flag.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
SR LBD LL_USART_ClearFlag_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2059 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_nCTS ( USART_TypeDef * USARTx )

Clear CTS Interrupt Flag.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
SR CTS LL_USART_ClearFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2072 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_NE ( USART_TypeDef * USARTx )

Clear Noise detected Flag.

Note:
Clearing this flag is done by a read access to the USARTx_SR register followed by a read access to the USARTx_DR register.
Please also consider that when clearing this flag, other flags as PE, FE, ORE, IDLE would also be cleared.
Reference Manual to LL API cross reference:
SR NF LL_USART_ClearFlag_NE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1982 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_ORE ( USART_TypeDef * USARTx )

Clear OverRun Error Flag.

Note:
Clearing this flag is done by a read access to the USARTx_SR register followed by a read access to the USARTx_DR register.
Please also consider that when clearing this flag, other flags as PE, NE, FE, IDLE would also be cleared.
Reference Manual to LL API cross reference:
SR ORE LL_USART_ClearFlag_ORE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2001 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_PE ( USART_TypeDef * USARTx )

Clear Parity Error Flag.

Note:
Clearing this flag is done by a read access to the USARTx_SR register followed by a read access to the USARTx_DR register.
Please also consider that when clearing this flag, other flags as NE, FE, ORE, IDLE would also be cleared.
Reference Manual to LL API cross reference:
SR PE LL_USART_ClearFlag_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 1944 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_RXNE ( USART_TypeDef * USARTx )

Clear RX Not Empty Flag.

Reference Manual to LL API cross reference:
SR RXNE LL_USART_ClearFlag_RXNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2046 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_ClearFlag_TC ( USART_TypeDef * USARTx )

Clear Transmission Complete Flag.

Reference Manual to LL API cross reference:
SR TC LL_USART_ClearFlag_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2035 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE ( USART_TypeDef * USARTx )

Check if the USART Framing Error Flag is set or not.

Reference Manual to LL API cross reference:
SR FE LL_USART_IsActiveFlag_FE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1815 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE ( USART_TypeDef * USARTx )

Check if the USART IDLE line detected Flag is set or not.

Reference Manual to LL API cross reference:
SR IDLE LL_USART_IsActiveFlag_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1848 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD ( USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Flag is set or not.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
SR LBD LL_USART_IsActiveFlag_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1894 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS ( USART_TypeDef * USARTx )

Check if the USART CTS Flag is set or not.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
SR CTS LL_USART_IsActiveFlag_nCTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1907 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE ( USART_TypeDef * USARTx )

Check if the USART Noise error detected Flag is set or not.

Reference Manual to LL API cross reference:
SR NF LL_USART_IsActiveFlag_NE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1826 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE ( USART_TypeDef * USARTx )

Check if the USART OverRun Error Flag is set or not.

Reference Manual to LL API cross reference:
SR ORE LL_USART_IsActiveFlag_ORE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1837 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE ( USART_TypeDef * USARTx )

Check if the USART Parity Error Flag is set or not.

Reference Manual to LL API cross reference:
SR PE LL_USART_IsActiveFlag_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1804 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU ( USART_TypeDef * USARTx )

Check if the USART Receive Wake Up from mute mode Flag is set or not.

Reference Manual to LL API cross reference:
CR1 RWU LL_USART_IsActiveFlag_RWU
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1929 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE ( USART_TypeDef * USARTx )

Check if the USART Read Data Register Not Empty Flag is set or not.

Reference Manual to LL API cross reference:
SR RXNE LL_USART_IsActiveFlag_RXNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1859 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK ( USART_TypeDef * USARTx )

Check if the USART Send Break Flag is set or not.

Reference Manual to LL API cross reference:
CR1 SBK LL_USART_IsActiveFlag_SBK
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1918 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC ( USART_TypeDef * USARTx )

Check if the USART Transmission Complete Flag is set or not.

Reference Manual to LL API cross reference:
SR TC LL_USART_IsActiveFlag_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1870 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE ( USART_TypeDef * USARTx )

Check if the USART Transmit Data Register Empty Flag is set or not.

Reference Manual to LL API cross reference:
SR TXE LL_USART_IsActiveFlag_TXE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 1881 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IT_Management

Functions
IT_Management
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE (USART_TypeDef *USARTx)
Enable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE (USART_TypeDef *USARTx)
Enable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE (USART_TypeDef *USARTx)
Disable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE (USART_TypeDef *USARTx)
Disable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE (USART_TypeDef *USARTx)
Check if the USART RX Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE (USART_TypeDef *USARTx)
Check if the USART TX Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.

Function Documentation

__STATIC_INLINE void LL_USART_DisableIT_CTS ( USART_TypeDef * USARTx )

Disable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_DisableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2272 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_ERROR ( USART_TypeDef * USARTx )

Disable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_DisableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2259 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_IDLE ( USART_TypeDef * USARTx )

Disable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_DisableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2187 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_LBD ( USART_TypeDef * USARTx )

Disable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_DisableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2244 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_PE ( USART_TypeDef * USARTx )

Disable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_DisableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2231 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_RXNE ( USART_TypeDef * USARTx )

Disable RX Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_USART_DisableIT_RXNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2198 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TC ( USART_TypeDef * USARTx )

Disable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_DisableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2209 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableIT_TXE ( USART_TypeDef * USARTx )

Disable TX Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_USART_DisableIT_TXE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2220 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_CTS ( USART_TypeDef * USARTx )

Enable CTS Interrupt.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_EnableIT_CTS
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2176 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_ERROR ( USART_TypeDef * USARTx )

Enable Error Interrupt.

Note:
When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). 0: Interrupt is inhibited 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
Reference Manual to LL API cross reference:
CR3 EIE LL_USART_EnableIT_ERROR
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2163 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_IDLE ( USART_TypeDef * USARTx )

Enable IDLE Interrupt.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_EnableIT_IDLE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2091 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_LBD ( USART_TypeDef * USARTx )

Enable LIN Break Detection Interrupt.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_EnableIT_LBD
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2148 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_PE ( USART_TypeDef * USARTx )

Enable Parity Error Interrupt.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_EnableIT_PE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2135 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_RXNE ( USART_TypeDef * USARTx )

Enable RX Not Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_USART_EnableIT_RXNE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2102 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TC ( USART_TypeDef * USARTx )

Enable Transmission Complete Interrupt.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_EnableIT_TC
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2113 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableIT_TXE ( USART_TypeDef * USARTx )

Enable TX Empty Interrupt.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_USART_EnableIT_TXE
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2124 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS ( USART_TypeDef * USARTx )

Check if the USART CTS Interrupt is enabled or disabled.

Note:
Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not Hardware Flow control feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR3 CTSIE LL_USART_IsEnabledIT_CTS
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2364 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR ( USART_TypeDef * USARTx )

Check if the USART Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR3 EIE LL_USART_IsEnabledIT_ERROR
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2351 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE ( USART_TypeDef * USARTx )

Check if the USART IDLE Interrupt source is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2283 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD ( USART_TypeDef * USARTx )

Check if the USART LIN Break Detection Interrupt is enabled or disabled.

Note:
Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not LIN feature is supported by the USARTx instance.
Reference Manual to LL API cross reference:
CR2 LBDIE LL_USART_IsEnabledIT_LBD
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2340 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE ( USART_TypeDef * USARTx )

Check if the USART Parity Error Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 PEIE LL_USART_IsEnabledIT_PE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2327 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE ( USART_TypeDef * USARTx )

Check if the USART RX Not Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2294 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC ( USART_TypeDef * USARTx )

Check if the USART Transmission Complete Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TCIE LL_USART_IsEnabledIT_TC
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2305 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE ( USART_TypeDef * USARTx )

Check if the USART TX Empty Interrupt is enabled or disabled.

Reference Manual to LL API cross reference:
CR1 TXEIE LL_USART_IsEnabledIT_TXE
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2316 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA_Management

Functions
DMA_Management
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (USART_TypeDef *USARTx)
Get the data register address used for DMA transfer.

Function Documentation

__STATIC_INLINE void LL_USART_DisableDMAReq_RX ( USART_TypeDef * USARTx )

Disable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_DisableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2394 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_DisableDMAReq_TX ( USART_TypeDef * USARTx )

Disable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_DisableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2427 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr ( USART_TypeDef * USARTx )

Get the data register address used for DMA transfer.

Reference Manual to LL API cross reference:
DR DR LL_USART_DMA_GetRegAddr
Note:
Address of Data Register is valid for both Transmit and Receive transfers.
Parameters:
USARTx USART Instance
Return values:
Address of data register

Definition at line 2450 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_RX ( USART_TypeDef * USARTx )

Enable DMA Mode for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_EnableDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2383 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_EnableDMAReq_TX ( USART_TypeDef * USARTx )

Enable DMA Mode for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_EnableDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2416 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX ( USART_TypeDef * USARTx )

Check if DMA Mode is enabled for reception.

Reference Manual to LL API cross reference:
CR3 DMAR LL_USART_IsEnabledDMAReq_RX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2405 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX ( USART_TypeDef * USARTx )

Check if DMA Mode is enabled for transmission.

Reference Manual to LL API cross reference:
CR3 DMAT LL_USART_IsEnabledDMAReq_TX
Parameters:
USARTx USART Instance
Return values:
State of bit (1 or 0).

Definition at line 2438 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data_Management

Functions
Data_Management
USART Exported Functions

Functions

__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)

Function Documentation

__STATIC_INLINE uint8_t LL_USART_ReceiveData8 ( USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 8 bits)

Reference Manual to LL API cross reference:
DR DR LL_USART_ReceiveData8
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0xFF

Definition at line 2470 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE uint16_t LL_USART_ReceiveData9 ( USART_TypeDef * USARTx )

Read Receiver Data register (Receive Data value, 9 bits)

Reference Manual to LL API cross reference:
DR DR LL_USART_ReceiveData9
Parameters:
USARTx USART Instance
Return values:
Value between Min_Data=0x00 and Max_Data=0x1FF

Definition at line 2481 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData8 | ( | USART_TypeDef * | USARTx,
 |  | uint8_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 8 bits)

Reference Manual to LL API cross reference:
DR DR LL_USART_TransmitData8
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0xFF
Return values:
None

Definition at line 2493 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_TransmitData9 | ( | USART_TypeDef * | USARTx,
 |  | uint16_t | Value
 | ) |  |

Write in Transmitter Data Register (Transmit Data value, 9 bits)

Reference Manual to LL API cross reference:
DR DR LL_USART_TransmitData9
Parameters:
USARTx | USART Instance
Value | between Min_Data=0x00 and Max_Data=0x1FF
Return values:
None

Definition at line 2505 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Execution

Functions
Execution
USART Exported Functions

Functions

__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in Mute mode.
__STATIC_INLINE void | LL_USART_RequestExitMuteMode (USART_TypeDef *USARTx)
Put USART in Active mode.

Function Documentation

__STATIC_INLINE void LL_USART_RequestBreakSending ( USART_TypeDef * USARTx )

Request Break sending.

Reference Manual to LL API cross reference:
CR1 SBK LL_USART_RequestBreakSending
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2524 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestEnterMuteMode ( USART_TypeDef * USARTx )

Put USART in Mute mode.

Reference Manual to LL API cross reference:
CR1 RWU LL_USART_RequestEnterMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2535 of file stm32f1xx_ll_usart.h.

__STATIC_INLINE void LL_USART_RequestExitMuteMode ( USART_TypeDef * USARTx )

Put USART in Active mode.

Reference Manual to LL API cross reference:
CR1 RWU LL_USART_RequestExitMuteMode
Parameters:
USARTx USART Instance
Return values:
None

Definition at line 2546 of file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
USART Exported Functions

Functions

ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Function Documentation

ErrorStatus LL_USART_ClockInit | ( | USART_TypeDef * | USARTx,
 |  | LL_USART_ClockInitTypeDef * | USART_ClockInitStruct
 | ) |  |

Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Parameters:
USARTx USART Instance
USART_ClockInitStruct,: pointer to a LL_USART_ClockInitTypeDef structure that contains the Clock configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 362 of file stm32f1xx_ll_usart.c.

References assert_param, LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, IS_LL_USART_CLOCKOUTPUT, IS_LL_USART_CLOCKPHASE, IS_LL_USART_CLOCKPOLARITY, IS_LL_USART_LASTBITCLKOUTPUT, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_DisableSCLKOutput(), and LL_USART_IsEnabled().

void LL_USART_ClockStructInit ( LL_USART_ClockInitTypeDef * USART_ClockInitStruct )

Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Parameters:
USART_ClockInitStruct,: pointer to a LL_USART_ClockInitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 421 of file stm32f1xx_ll_usart.c.

References LL_USART_ClockInitTypeDef::ClockOutput, LL_USART_ClockInitTypeDef::ClockPhase, LL_USART_ClockInitTypeDef::ClockPolarity, LL_USART_ClockInitTypeDef::LastBitClockPulse, LL_USART_CLOCK_DISABLE, LL_USART_LASTCLKPULSE_NO_OUTPUT, LL_USART_PHASE_1EDGE, and LL_USART_POLARITY_LOW.

ErrorStatus LL_USART_DeInit ( USART_TypeDef * USARTx )

De-initialize USART registers (Registers restored to their default values).

Parameters:
USARTx USART Instance
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are de-initialized
  • ERROR: USART registers are not de-initialized

Definition at line 139 of file stm32f1xx_ll_usart.c.

References assert_param, LL_APB1_GRP1_ForceReset(), LL_APB1_GRP1_PERIPH_USART2, LL_APB1_GRP1_PERIPH_USART3, LL_APB1_GRP1_ReleaseReset(), LL_APB2_GRP1_ForceReset(), LL_APB2_GRP1_PERIPH_USART1, and LL_APB2_GRP1_ReleaseReset().

ErrorStatus LL_USART_Init | ( | USART_TypeDef * | USARTx,
 |  | LL_USART_InitTypeDef * | USART_InitStruct
 | ) |  |

Initialize USART registers according to the specified parameters in USART_InitStruct.

Note:
As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
Parameters:
USARTx USART Instance
USART_InitStruct,: pointer to a LL_USART_InitTypeDef structure that contains the configuration information for the specified USART peripheral.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: USART registers are initialized according to USART_InitStruct content
  • ERROR: Problem occurred during USART Registers initialization

Definition at line 213 of file stm32f1xx_ll_usart.c.

References assert_param, LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, IS_LL_USART_BAUDRATE, IS_LL_USART_DATAWIDTH, IS_LL_USART_DIRECTION, IS_LL_USART_HWCONTROL, IS_LL_USART_OVERSAMPLING, IS_LL_USART_PARITY, IS_LL_USART_STOPBITS, LL_RCC_GetSystemClocksFreq(), LL_RCC_PERIPH_FREQUENCY_NO, LL_USART_IsEnabled(), LL_USART_SetBaudRate(), LL_USART_SetHWFlowCtrl(), LL_USART_SetStopBitsLength(), LL_USART_InitTypeDef::Parity, LL_RCC_ClocksTypeDef::PCLK1_Frequency, LL_RCC_ClocksTypeDef::PCLK2_Frequency, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

void LL_USART_StructInit ( LL_USART_InitTypeDef * USART_InitStruct )

Set each LL_USART_InitTypeDef field to default value.

Parameters:
USART_InitStruct,: pointer to a LL_USART_InitTypeDef structure whose fields will be set to default values.
Return values:
None

Definition at line 336 of file stm32f1xx_ll_usart.c.

References LL_USART_InitTypeDef::BaudRate, LL_USART_InitTypeDef::DataWidth, LL_USART_InitTypeDef::HardwareFlowControl, LL_USART_DATAWIDTH_8B, LL_USART_DIRECTION_TX_RX, LL_USART_HWCONTROL_NONE, LL_USART_PARITY_NONE, LL_USART_STOPBITS_1, LL_USART_InitTypeDef::Parity, LL_USART_InitTypeDef::StopBits, and LL_USART_InitTypeDef::TransferDirection.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UTILS Private functions

Functions
UTILS Private functions
UTILS

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_SetFlashLatency (uint32_t Frequency)
Update number of Flash wait states in line with new frequency and current voltage range.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.

Function Documentation

static ErrorStatus UTILS_EnablePLLAndSwitchSystem | ( | uint32_t | SYSCLK_Frequency,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  | [static]

Function to enable PLL and switch system clock to PLL.

Parameters:
SYSCLK_Frequency | SYSCLK frequency
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: No problem to switch system to PLL
  • ERROR: Problem to switch system to PLL

Definition at line 536 of file stm32f1xx_ll_utils.c.

References __LL_RCC_CALC_HCLK_FREQ, LL_UTILS_ClkInitTypeDef::AHBCLKDivider, LL_UTILS_ClkInitTypeDef::APB1CLKDivider, LL_UTILS_ClkInitTypeDef::APB2CLKDivider, assert_param, IS_LL_UTILS_APB1_DIV, IS_LL_UTILS_APB2_DIV, IS_LL_UTILS_SYSCLK_DIV, LL_RCC_GetSysClkSource(), LL_RCC_PLL_Enable(), LL_RCC_PLL_IsReady(), LL_RCC_SetAHBPrescaler(), LL_RCC_SetAPB1Prescaler(), LL_RCC_SetAPB2Prescaler(), LL_RCC_SetSysClkSource(), LL_RCC_SYS_CLKSOURCE_PLL, LL_RCC_SYS_CLKSOURCE_STATUS_PLL, LL_SetSystemCoreClock(), and UTILS_SetFlashLatency().

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static uint32_t UTILS_GetPLLOutputFrequency | ( | uint32_t | PLL_InputFrequency,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct
 | ) |  | [static]

Function to check that PLL can be modified.

Parameters:
PLL_InputFrequency | PLL input frequency (in Hz)
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
Return values:
PLL output frequency (in Hz)

Definition at line 470 of file stm32f1xx_ll_utils.c.

References __LL_RCC_CALC_PLLCLK_FREQ, assert_param, IS_LL_UTILS_PLL_FREQUENCY, IS_LL_UTILS_PLLMUL_VALUE, LL_UTILS_PLLInitTypeDef::PLLMul, and LL_UTILS_PLLInitTypeDef::Prediv.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static ErrorStatus UTILS_PLL_IsBusy ( void ) [static]

Function to check that PLL can be modified.

Return values:
An ErrorStatus enumeration value:
  • SUCCESS: PLL modification can be done
  • ERROR: PLL is busy

Definition at line 496 of file stm32f1xx_ll_utils.c.

References LL_RCC_PLL_IsReady().

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

static ErrorStatus UTILS_SetFlashLatency ( uint32_t Frequency ) [static]

Update number of Flash wait states in line with new frequency and current voltage range.

Parameters:
Frequency SYSCLK frequency
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Latency has been modified
  • ERROR: Latency cannot be modified

Definition at line 422 of file stm32f1xx_ll_utils.c.

References LL_FLASH_GetLatency(), LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_SetLatency(), UTILS_LATENCY1_FREQ, and UTILS_LATENCY2_FREQ.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UTILS Private Constants

Defines
UTILS Private Constants
UTILS

Defines

#define | UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY
#define | UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN
#define | UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX
#define | UTILS_LATENCY1_FREQ 24000000U
#define | UTILS_LATENCY2_FREQ 48000000U
#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.

Define Documentation

#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE

Flash size data register base address.

Definition at line 88 of file stm32f1xx_ll_utils.h.

Referenced by LL_GetFlashSize().

#define LL_MAX_DELAY 0xFFFFFFFFU

Definition at line 78 of file stm32f1xx_ll_utils.h.

Referenced by LL_mDelay().

#define UID_BASE_ADDRESS UID_BASE

Unique device ID register base address.

Definition at line 83 of file stm32f1xx_ll_utils.h.

Referenced by LL_GetUID_Word0(), LL_GetUID_Word1(), and LL_GetUID_Word2().

#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX

Frequency max for HSE frequency, in Hz

Definition at line 67 of file stm32f1xx_ll_utils.c.

#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN

Frequency min for HSE frequency, in Hz

Definition at line 66 of file stm32f1xx_ll_utils.c.

#define UTILS_LATENCY1_FREQ 24000000U

SYSCLK frequency to set FLASH latency 1

Definition at line 71 of file stm32f1xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_LATENCY2_FREQ 48000000U

SYSCLK frequency to set FLASH latency 2

Definition at line 72 of file stm32f1xx_ll_utils.c.

Referenced by UTILS_SetFlashLatency().

#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY

Frequency max for PLL output, in Hz

Definition at line 63 of file stm32f1xx_ll_utils.c.

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STM32F103xB HAL User Manual: UTILS Private Macros

Defines
UTILS Private Macros
UTILS

Defines

#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLMUL_VALUE(__VALUE__)
#define | IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Define Documentation

#define IS_LL_UTILS_APB1_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB1_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))

Definition at line 93 of file stm32f1xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_APB2_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_APB2_DIV_1) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))

Definition at line 99 of file stm32f1xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

#define IS_LL_UTILS_HSE_BYPASS ( __STATE__ )
Value:
(((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))

Definition at line 147 of file stm32f1xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_HSE_FREQUENCY ( __FREQUENCY__ ) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Definition at line 150 of file stm32f1xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE().

#define IS_LL_UTILS_PLL_FREQUENCY ( __VALUE__ ) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)

Definition at line 144 of file stm32f1xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PLLMUL_VALUE ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_PLL_MUL_2) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
                                          || ((__VALUE__) == LL_RCC_PLL_MUL_16))

Definition at line 114 of file stm32f1xx_ll_utils.c.

Referenced by UTILS_GetPLLOutputFrequency().

#define IS_LL_UTILS_PREDIV_VALUE ( __VALUE__ ) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))

Definition at line 141 of file stm32f1xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), and LL_PLL_ConfigSystemClock_HSI().

#define IS_LL_UTILS_SYSCLK_DIV ( __VALUE__ )
Value:
(((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))

Definition at line 83 of file stm32f1xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_UTILS_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_PLLInitTypeDef Struct Reference
UTILS Exported structures

UTILS PLL structure definition. More...

#include <stm32f1xx_ll_utils.h>

Data Fields

uint32_t | PLLMul
uint32_t | Prediv

Detailed Description

UTILS PLL structure definition.

Definition at line 108 of file stm32f1xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_PLLInitTypeDef::PLLMul

Multiplication factor for PLL VCO input clock. This parameter can be a value of PLL Multiplicator factor

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 110 of file stm32f1xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

uint32_t LL_UTILS_PLLInitTypeDef::Prediv

Division factor for HSE used as PLL clock source. This parameter can be a value of PREDIV Division factor

This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS().

Definition at line 116 of file stm32f1xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), and UTILS_GetPLLOutputFrequency().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_utils.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LL_UTILS_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
LL_UTILS_ClkInitTypeDef Struct Reference
UTILS Exported structures

UTILS System, AHB and APB buses clock configuration structure definition. More...

#include <stm32f1xx_ll_utils.h>

Data Fields

uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

UTILS System, AHB and APB buses clock configuration structure definition.

Definition at line 126 of file stm32f1xx_ll_utils.h.

Field Documentation

uint32_t LL_UTILS_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB prescaler

This feature can be modified afterwards using unitary function LL_RCC_SetAHBPrescaler().

Definition at line 128 of file stm32f1xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB low-speed prescaler (APB1)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB1Prescaler().

Definition at line 134 of file stm32f1xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

uint32_t LL_UTILS_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB high-speed prescaler (APB2)

This feature can be modified afterwards using unitary function LL_RCC_SetAPB2Prescaler().

Definition at line 140 of file stm32f1xx_ll_utils.h.

Referenced by UTILS_EnablePLLAndSwitchSystem().

The documentation for this struct was generated from the following file:
  • stm32f1xx_ll_utils.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: HSE Bypass activation

Defines
HSE Bypass activation
UTILS Exported Constants

Defines

#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U

Define Documentation

#define LL_UTILS_HSEBYPASS_OFF 0x00000000U

HSE Bypass is not enabled

Definition at line 160 of file stm32f1xx_ll_utils.h.

#define LL_UTILS_HSEBYPASS_ON 0x00000001U

HSE Bypass is enabled

Definition at line 161 of file stm32f1xx_ll_utils.h.

Referenced by LL_PLL_ConfigSystemClock_HSE().

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DEVICE ELECTRONIC SIGNATURE

Functions
DEVICE ELECTRONIC SIGNATURE
UTILS Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.

Function Documentation

__STATIC_INLINE uint32_t LL_GetFlashSize ( void )

Get Flash memory size.

Note:
This bitfield indicates the size of the device Flash memory expressed in Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
Return values:
FLASH_SIZE[15:0],: Flash memory size

Definition at line 214 of file stm32f1xx_ll_utils.h.

References FLASHSIZE_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word0 ( void )

Get Word0 of the unique device identifier (UID based on 96 bits)

Return values:
UID[31:0]

Definition at line 185 of file stm32f1xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word1 ( void )

Get Word1 of the unique device identifier (UID based on 96 bits)

Return values:
UID[63:32]

Definition at line 194 of file stm32f1xx_ll_utils.h.

References UID_BASE_ADDRESS.

__STATIC_INLINE uint32_t LL_GetUID_Word2 ( void )

Get Word2 of the unique device identifier (UID based on 96 bits)

Return values:
UID[95:64]

Definition at line 203 of file stm32f1xx_ll_utils.h.

References UID_BASE_ADDRESS.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DELAY

Functions
DELAY
UTILS Exported Functions

Functions

void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.

Function Documentation

void LL_Init1msTick ( uint32_t HCLKFrequency )

This function configures the Cortex-M SysTick source to have 1ms time base.

Note:
When a RTOS is used, it is recommended to avoid changing the Systick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
HCLKFrequency HCLK frequency in Hz
Note:
HCLK frequency can be calculated thanks to RCC helper macro or function LL_RCC_GetSystemClocksFreq
Return values:
None

Definition at line 186 of file stm32f1xx_ll_utils.c.

References LL_InitTick().

__STATIC_INLINE void LL_InitTick | ( | uint32_t | HCLKFrequency,
 |  | uint32_t | Ticks
 | ) |  |

This function configures the Cortex-M SysTick source of the time base.

Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Note:
When a RTOS is used, it is recommended to avoid changing the SysTick configuration by calling this function, for a delay use rather osDelay RTOS service.
Parameters:
Ticks Number of ticks
Return values:
None

Definition at line 236 of file stm32f1xx_ll_utils.h.

Referenced by LL_Init1msTick().

void LL_mDelay ( uint32_t Delay )

This function provides accurate delay (in milliseconds) based on SysTick counter flag.

Note:
When a RTOS is used, it is recommended to avoid using blocking delay and use rather osDelay service.
To respect 1ms timebase, user should call LL_Init1msTick function which will configure Systick to 1ms
Parameters:
Delay specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 202 of file stm32f1xx_ll_utils.c.

References LL_MAX_DELAY.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SYSTEM

Functions
SYSTEM
UTILS Exported Functions

System Configuration functions. More...

Functions

void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

System Configuration functions.

 ===============================================================================
           ##### System Configuration functions #####
 ===============================================================================
    [..]
         System, AHB and APB buses clocks configuration

         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.

Function Documentation

ErrorStatus LL_PLL_ConfigSystemClock_HSE | ( | uint32_t | HSEFrequency,
 |  | uint32_t | HSEBypass,
 |  | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with HSE as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
  • PREDIV: Set to 2 for few devices
  • PLLMUL: The application software must set correctly the PLL multiplication factor to not exceed UTILS_PLL_OUTPUT_MAX
FLASH latency can be modified through this function.
Parameters:
HSEFrequency | Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
HSEBypass This parameter can be one of the following values:
  • LL_UTILS_HSEBYPASS_ON
  • LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 348 of file stm32f1xx_ll_utils.c.

References assert_param, IS_LL_UTILS_HSE_BYPASS, IS_LL_UTILS_HSE_FREQUENCY, IS_LL_UTILS_PREDIV_VALUE, LL_RCC_HSE_DisableBypass(), LL_RCC_HSE_Enable(), LL_RCC_HSE_EnableBypass(), LL_RCC_HSE_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLMul, LL_UTILS_PLLInitTypeDef::Prediv, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

ErrorStatus LL_PLL_ConfigSystemClock_HSI | ( | LL_UTILS_PLLInitTypeDef * | UTILS_PLLInitStruct,
 |  | LL_UTILS_ClkInitTypeDef * | UTILS_ClkInitStruct
 | ) |  |

This function configures system clock with HSI as clock source of the PLL.

Note:
The application need to ensure that PLL is disabled.
Function is based on the following formula:
  • PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
  • PREDIV: Set to 2 for few devices
  • PLLMUL: The application software must set correctly the PLL multiplication factor to not exceed 72MHz
FLASH latency can be modified through this function.
Parameters:
UTILS_PLLInitStruct | pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct | pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.
Return values:
An ErrorStatus enumeration value:
  • SUCCESS: Max frequency configuration done
  • ERROR: Max frequency configuration not done

Definition at line 283 of file stm32f1xx_ll_utils.c.

References assert_param, HSI_VALUE, IS_LL_UTILS_PREDIV_VALUE, LL_RCC_HSI_Enable(), LL_RCC_HSI_IsReady(), LL_RCC_PLL_ConfigDomain_SYS(), LL_RCC_PLLSOURCE_HSI_DIV_2, LL_RCC_PREDIV_DIV_2, LL_UTILS_PLLInitTypeDef::PLLMul, LL_UTILS_PLLInitTypeDef::Prediv, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

void LL_SetSystemCoreClock ( uint32_t HCLKFrequency )

This function sets directly SystemCoreClock CMSIS variable.

Note:
Variable can be calculated also through SystemCoreClockUpdate function.
Parameters:
HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
Return values:
None

Definition at line 260 of file stm32f1xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: WWDG

Modules
WWDG
STM32F1xx_LL_Driver

Modules

WWDG Exported Constants
WWDG Exported Macros
WWDG Exported Functions

Reference Manual to LL API cross reference

The following table provide a mapping between the registers and bits, as they appears inside product reference manual, and the functions provided by the Low Layer interface.

This table gives the correspondance for WWDG registers.

Register | Bit | Function
CFR | EWI | LL_WWDG_EnableIT_EWKUP
 |  | LL_WWDG_IsEnabledIT_EWKUP
 | W | LL_WWDG_GetWindow
 |  | LL_WWDG_SetWindow
 | WDGTB | LL_WWDG_GetPrescaler
 |  | LL_WWDG_SetPrescaler
CR | T | LL_WWDG_GetCounter
 |  | LL_WWDG_SetCounter
 | WDGA | LL_WWDG_Enable
 |  | LL_WWDG_IsEnabled
SR | EWIF | LL_WWDG_ClearFlag_EWKUP
 |  | LL_WWDG_IsActiveFlag_EWKUP
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STM32F103xB HAL User Manual: IT Defines

Defines
IT Defines
WWDG Exported Constants

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions. More...

Defines

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Detailed Description

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

Define Documentation

#define LL_WWDG_CFR_EWI WWDG_CFR_EWI

Definition at line 77 of file stm32f1xx_ll_wwdg.h.

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STM32F103xB HAL User Manual: PRESCALER

Defines
PRESCALER
WWDG Exported Constants

Defines

#define | LL_WWDG_PRESCALER_1 0x00000000U
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)

Define Documentation

#define LL_WWDG_PRESCALER_1 0x00000000U

WWDG counter clock = (PCLK1/4096)/1

Definition at line 85 of file stm32f1xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 86 of file stm32f1xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 87 of file stm32f1xx_ll_wwdg.h.

#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)

WWDG counter clock = (PCLK1/4096)/8

Definition at line 88 of file stm32f1xx_ll_wwdg.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Common Write and read registers macros

Defines
Common Write and read registers macros
WWDG Exported Macros

Defines

#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Define Documentation

#define LL_WWDG_ReadReg | ( | __INSTANCE__,
 |  | __REG__
 | ) | READ_REG(__INSTANCE__->__REG__)

Read a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be read
Return values:
Register value

Definition at line 119 of file stm32f1xx_ll_wwdg.h.

#define LL_WWDG_WriteReg | ( | __INSTANCE__,
 |  | __REG__,
 |  | __VALUE__
 | ) | WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

Write a value in WWDG register.

Parameters:
__INSTANCE__ | WWDG Instance
__REG__ | Register to be written
__VALUE__ | Value to be written in the register
Return values:
None

Definition at line 111 of file stm32f1xx_ll_wwdg.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Configuration

Functions
Configuration
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)

Function Documentation

__STATIC_INLINE void LL_WWDG_Enable ( WWDG_TypeDef * WWDGx )

Enable Window Watchdog.

The watchdog is always disabled after a reset.

Note:
It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_Enable
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 147 of file stm32f1xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetCounter ( WWDG_TypeDef * WWDGx )

Return current Watchdog Counter Value (7 bits counter value)

Reference Manual to LL API cross reference:
CR T LL_WWDG_GetCounter
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Counter value

Definition at line 185 of file stm32f1xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler ( WWDG_TypeDef * WWDGx )

Return current Watchdog Prescaler Value.

Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_GetPrescaler
Parameters:
WWDGx WWDG Instance
Return values:
Returned value can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8

Definition at line 218 of file stm32f1xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_GetWindow ( WWDG_TypeDef * WWDGx )

Return current Watchdog Window Value (7 bits value)

Reference Manual to LL API cross reference:
CFR W LL_WWDG_GetWindow
Parameters:
WWDGx WWDG Instance
Return values:
7 bit Watchdog Window value

Definition at line 250 of file stm32f1xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabled ( WWDG_TypeDef * WWDGx )

Checks if Window Watchdog is enabled.

Reference Manual to LL API cross reference:
CR WDGA LL_WWDG_IsEnabled
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 158 of file stm32f1xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetCounter | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Counter
 | ) |  |

Set the Watchdog counter value to provided value (7-bits T[6:0])

Note:
When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset This counter is decremented every (4096 x 2expWDGTB) PCLK cycles A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
Reference Manual to LL API cross reference:
CR T LL_WWDG_SetCounter
Parameters:
WWDGx | WWDG Instance
Counter | 0..0x7F (7 bit counter value)
Return values:
None

Definition at line 174 of file stm32f1xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetPrescaler | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Prescaler
 | ) |  |

Set the time base of the prescaler (WDGTB).

Note:
Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter is decremented every (4096 x 2expWDGTB) PCLK cycles
Reference Manual to LL API cross reference:
CFR WDGTB LL_WWDG_SetPrescaler
Parameters:
WWDGx WWDG Instance
Prescaler This parameter can be one of the following values:
  • LL_WWDG_PRESCALER_1
  • LL_WWDG_PRESCALER_2
  • LL_WWDG_PRESCALER_4
  • LL_WWDG_PRESCALER_8
Return values:
None

Definition at line 203 of file stm32f1xx_ll_wwdg.h.

__STATIC_INLINE void LL_WWDG_SetWindow | ( | WWDG_TypeDef * | WWDGx,
 |  | uint32_t | Window
 | ) |  |

Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).

Note:
This window value defines when write in the WWDG_CR register to program Watchdog counter is allowed. Watchdog counter value update must occur only when the counter value is lower than the Watchdog window register value. Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value (in the control register) is refreshed before the downcounter has reached the watchdog window register value. Physically is possible to set the Window lower then 0x40 but it is not recommended. To generate an immediate reset, it is possible to set the Counter lower than 0x40.
Reference Manual to LL API cross reference:
CFR W LL_WWDG_SetWindow
Parameters:
WWDGx | WWDG Instance
Window | 0x00..0x7F (7 bit Window value)
Return values:
None

Definition at line 239 of file stm32f1xx_ll_wwdg.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLAG_Management

Functions
FLAG_Management
WWDG Exported Functions

Functions

__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Function Documentation

__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Clear WWDG Early Wakeup Interrupt Flag (EWIF)

Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_ClearFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 282 of file stm32f1xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP ( WWDG_TypeDef * WWDGx )

Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.

Note:
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
Reference Manual to LL API cross reference:
SR EWIF LL_WWDG_IsActiveFlag_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 271 of file stm32f1xx_ll_wwdg.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IT_Management

Functions
IT_Management
WWDG Exported Functions

Functions

__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Function Documentation

__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP ( WWDG_TypeDef * WWDGx )

Enable the Early Wakeup Interrupt.

Note:
When set, an interrupt occurs whenever the counter reaches value 0x40. This interrupt is only cleared by hardware after a reset
Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_EnableIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
None

Definition at line 302 of file stm32f1xx_ll_wwdg.h.

__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP ( WWDG_TypeDef * WWDGx )

Check if Early Wakeup Interrupt is enabled.

Reference Manual to LL API cross reference:
CFR EWI LL_WWDG_IsEnabledIT_EWKUP
Parameters:
WWDGx WWDG Instance
Return values:
State of bit (1 or 0).

Definition at line 313 of file stm32f1xx_ll_wwdg.h.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: HAL Private Constants

Defines
HAL Private Constants
HAL

Defines

#define | __STM32F1xx_HAL_VERSION_MAIN (0x01U)
STM32F1xx HAL Driver version number.
#define | __STM32F1xx_HAL_VERSION_SUB1 (0x00U)
#define | __STM32F1xx_HAL_VERSION_SUB2 (0x05U)
#define | __STM32F1xx_HAL_VERSION_RC (0x00U)
#define | __STM32F1xx_HAL_VERSION
#define | IDCODE_DEVID_MASK 0x00000FFFU

Define Documentation

#define __STM32F1xx_HAL_VERSION
Value:
((__STM32F1xx_HAL_VERSION_MAIN << 24)\
                                        |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
                                        |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
                                        |(__STM32F1xx_HAL_VERSION_RC))

Definition at line 80 of file stm32f1xx_hal.c.

Referenced by HAL_GetHalVersion().

#define __STM32F1xx_HAL_VERSION_MAIN (0x01U)

STM32F1xx HAL Driver version number.

[31:24] main version

Definition at line 76 of file stm32f1xx_hal.c.

#define __STM32F1xx_HAL_VERSION_RC (0x00U)

[7:0] release candidate

Definition at line 79 of file stm32f1xx_hal.c.

#define __STM32F1xx_HAL_VERSION_SUB1 (0x00U)

[23:16] sub1 version

Definition at line 77 of file stm32f1xx_hal.c.

#define __STM32F1xx_HAL_VERSION_SUB2 (0x05U)

[15:8] sub2 version

Definition at line 78 of file stm32f1xx_hal.c.

#define IDCODE_DEVID_MASK 0x00000FFFU

Definition at line 85 of file stm32f1xx_hal.c.

Referenced by HAL_GetDEVID().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: HAL Private Variables

Variables
HAL Private Variables
HAL

Variables

__IO uint32_t uwTick

Variable Documentation

__IO uint32_t uwTick

Definition at line 97 of file stm32f1xx_hal.c.

Referenced by HAL_GetTick(), and HAL_IncTick().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization Functions

Functions
Initialization and de-initialization Functions
HAL Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..]  This section provides functions allowing to:
      (+) Initializes the Flash interface, the NVIC allocation and initial clock
          configuration. It initializes the source of time base also when timeout
          is needed and the backup domain when enabled.
      (+) de-Initializes common part of the HAL.
      (+) Configure The time base source to have 1ms time base with a dedicated
          Tick interrupt priority.
        (++) Systick timer is used by default as source of time base, but user
             can eventually implement his proper time base source (a general purpose
             timer for example or other time source), keeping in mind that Time base
             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
             handled in milliseconds basis.
        (++) Time base configuration function (HAL_InitTick ()) is called automatically
             at the beginning of the program after reset by HAL_Init() or at any time
             when clock is configured, by HAL_RCC_ClockConfig().
        (++) Source of time base is configured  to generate interrupts at regular
             time intervals. Care must be taken if HAL_Delay() is called from a
             peripheral ISR process, the Tick interrupt line must have higher priority
            (numerically lower) than the peripheral interrupt. Otherwise the caller
            ISR process will be blocked.
       (++) functions affecting time base configurations are declared as __weak
             to make  override possible  in case of other  implementations in user file.

Function Documentation

HAL_StatusTypeDef HAL_DeInit ( void )

This function de-Initializes common part of the HAL and stops the source of time base.

Note:
This function is optional.
Return values:
HAL status

Definition at line 191 of file stm32f1xx_hal.c.

References __HAL_RCC_APB1_FORCE_RESET, __HAL_RCC_APB1_RELEASE_RESET, __HAL_RCC_APB2_FORCE_RESET, __HAL_RCC_APB2_RELEASE_RESET, and HAL_MspDeInit().

HAL_StatusTypeDef HAL_Init ( void )

This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch.

Configures the SysTick to generate an interrupt each 1 millisecond, which is clocked by the HSI (at this stage, the clock is not yet configured and thus the system is running from the internal HSI at 16 MHz). Set NVIC Group Priority to 4. Calls the HAL_MspInit() callback function defined in user file "stm32f1xx_hal_msp.c" to do the global low level hardware initialization

Note:
SysTick is used as time base for the HAL_Delay() function, the application need to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation.
Return values:
HAL status

Definition at line 158 of file stm32f1xx_hal.c.

References __HAL_FLASH_PREFETCH_BUFFER_ENABLE, HAL_InitTick(), HAL_MspInit(), HAL_NVIC_SetPriorityGrouping(), NVIC_PRIORITYGROUP_4, and TICK_INT_PRIORITY.

HAL_StatusTypeDef HAL_InitTick ( uint32_t TickPriority )

This function configures the source of the time base.

The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note:
This function is called automatically at the beginning of program after reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if HAL_Delay() is called from a peripheral ISR process, The the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters:
TickPriority,: Tick interrupt priority.
Return values:
HAL status

Definition at line 250 of file stm32f1xx_hal.c.

References HAL_NVIC_SetPriority(), and HAL_SYSTICK_Config().

Referenced by HAL_Init(), and HAL_RCC_ClockConfig().

void HAL_MspDeInit ( void )

DeInitializes the MSP.

Return values:
None

Definition at line 227 of file stm32f1xx_hal.c.

Referenced by HAL_DeInit().

void HAL_MspInit ( void )

Initializes the MSP.

Return values:
None

Definition at line 216 of file stm32f1xx_hal.c.

Referenced by HAL_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: HAL Control functions

Functions
HAL Control functions
HAL Exported Functions

HAL Control functions. More...

Functions

__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_GetUID (uint32_t *UID)
Return the unique device identifier (UID based on 96 bits)

Detailed Description

HAL Control functions.

 ===============================================================================
                      ##### HAL Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Provide a tick value in millisecond
      (+) Provide a blocking delay in millisecond
      (+) Suspend the time base source interrupt
      (+) Resume the time base source interrupt
      (+) Get the HAL API driver version
      (+) Get the device identifier
      (+) Get the device revision identifier
      (+) Enable/Disable Debug module during SLEEP mode
      (+) Enable/Disable Debug module during STOP mode
      (+) Enable/Disable Debug module during STANDBY mode

Function Documentation

void HAL_DBGMCU_DisableDBGSleepMode ( void )

Disable the Debug Module during SLEEP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).

Refer to errata sheet of these devices for more details.

Return values:
None

Definition at line 434 of file stm32f1xx_hal.c.

void HAL_DBGMCU_DisableDBGStandbyMode ( void )

Disable the Debug Module during STANDBY mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).

Refer to errata sheet of these devices for more details.

Return values:
None

Definition at line 512 of file stm32f1xx_hal.c.

void HAL_DBGMCU_DisableDBGStopMode ( void )

Disable the Debug Module during STOP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).

Refer to errata sheet of these devices for more details.

Return values:
None

Definition at line 480 of file stm32f1xx_hal.c.

void HAL_DBGMCU_EnableDBGSleepMode ( void )

Enable the Debug Module during SLEEP mode.

Return values:
None

Definition at line 418 of file stm32f1xx_hal.c.

void HAL_DBGMCU_EnableDBGStandbyMode ( void )

Enable the Debug Module during STANDBY mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).

Refer to errata sheet of these devices for more details.

Return values:
None

Definition at line 496 of file stm32f1xx_hal.c.

void HAL_DBGMCU_EnableDBGStopMode ( void )

Enable the Debug Module during STOP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).

Refer to errata sheet of these devices for more details. Note: On all STM32F1 devices: If the system tick timer interrupt is enabled during the Stop mode debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup the system from Stop mode. Workaround: To debug the Stop mode, disable the system tick timer interrupt. Refer to errata sheet of these devices for more details. Note: On all STM32F1 devices: If the system tick timer interrupt is enabled during the Stop mode debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup the system from Stop mode. Workaround: To debug the Stop mode, disable the system tick timer interrupt. Refer to errata sheet of these devices for more details.

Return values:
None

Definition at line 464 of file stm32f1xx_hal.c.

void HAL_Delay ( __IO uint32_t Delay )

This function provides minimum delay (in milliseconds) based on variable incremented.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where uwTick is incremented.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters:
Delay,: specifies the delay time length, in milliseconds.
Return values:
None

Definition at line 325 of file stm32f1xx_hal.c.

References HAL_GetTick().

Referenced by HAL_RCC_OscConfig().

uint32_t HAL_GetDEVID ( void )

Returns the device identifier.

Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode). Refer to errata sheet of these devices for more details.

Return values:
Device identifier

Definition at line 409 of file stm32f1xx_hal.c.

References IDCODE_DEVID_MASK.

uint32_t HAL_GetHalVersion ( void )

Returns the HAL revision.

Return values:
version : 0xXYZR (8bits for each decimal, R for RC)

Definition at line 377 of file stm32f1xx_hal.c.

References __STM32F1xx_HAL_VERSION.

uint32_t HAL_GetREVID ( void )

Returns the device revision identifier.

Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode). Refer to errata sheet of these devices for more details.

Return values:
Device revision identifier

Definition at line 393 of file stm32f1xx_hal.c.

uint32_t HAL_GetTick ( void )

Provides a tick value in millisecond.

Note:
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
tick value

Definition at line 309 of file stm32f1xx_hal.c.

References uwTick.

Referenced by ADC_ConversionStop_Disable(), ADC_Enable(), FLASH_WaitForLastOperation(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_CAN_Init(), HAL_CAN_Receive(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_WakeUp(), HAL_Delay(), HAL_DMA_PollForTransfer(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), HAL_IWDG_Init(), HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_PeriphCLKConfig(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_WaitForSynchro(), HAL_RTCEx_PollForTamper1Event(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Transmit(), HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_UART_Receive(), HAL_UART_Transmit(), HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), IRDA_WaitOnFlagUntilTimeout(), RTC_EnterInitMode(), RTC_ExitInitMode(), SMARTCARD_WaitOnFlagUntilTimeout(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_WaitFlagStateUntilTimeout(), UART_WaitOnFlagUntilTimeout(), and USART_WaitOnFlagUntilTimeout().

void HAL_GetUID ( uint32_t * UID )

Return the unique device identifier (UID based on 96 bits)

Parameters:
UID,: pointer to 3 words array.
Return values:
Device identifier

Definition at line 522 of file stm32f1xx_hal.c.

void HAL_IncTick ( void )

This function is called to increment a global variable "uwTick" used as application time base.

Note:
In the default implementation, this variable is incremented each 1ms in Systick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 298 of file stm32f1xx_hal.c.

References uwTick.

void HAL_ResumeTick ( void )

Resume Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_ResumeTick() is called, the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 367 of file stm32f1xx_hal.c.

void HAL_SuspendTick ( void )

Suspend Tick increment.

Note:
In the default implementation , SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once HAL_SuspendTick() is called, the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values:
None

Definition at line 351 of file stm32f1xx_hal.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Freeze Unfreeze Peripherals in Debug mode

Defines
Freeze Unfreeze Peripherals in Debug mode
HAL Exported Macros

Freeze/Unfreeze Peripherals in Debug mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode). More...

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
TIM2 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
TIM3 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
TIM4 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
WWDG Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
IWDG Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
I2C1 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
I2C2 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#define | __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
CAN1 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
TIM1 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)

Detailed Description

Freeze/Unfreeze Peripherals in Debug mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).

Refer to errata sheet of these devices for more details.

Define Documentation

#define __HAL_DBGMCU_FREEZE_CAN1 ( ) SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)

CAN1 Peripherals Debug mode.

Definition at line 177 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT ( ) SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)

I2C1 Peripherals Debug mode.

Definition at line 162 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT ( ) SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)

I2C2 Peripherals Debug mode.

Definition at line 169 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_FREEZE_IWDG ( ) SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)

IWDG Peripherals Debug mode.

Definition at line 156 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM1 ( ) SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)

TIM1 Peripherals Debug mode.

Definition at line 194 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM2 ( ) SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)

TIM2 Peripherals Debug mode.

Definition at line 82 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM3 ( ) SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)

TIM3 Peripherals Debug mode.

Definition at line 88 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_FREEZE_TIM4 ( ) SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)

TIM4 Peripherals Debug mode.

Definition at line 95 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_FREEZE_WWDG ( ) SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)

WWDG Peripherals Debug mode.

Definition at line 150 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_CAN1 ( ) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)

Definition at line 178 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT ( ) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)

Definition at line 163 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT ( ) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)

Definition at line 170 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_IWDG ( ) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)

Definition at line 157 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM1 ( ) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)

Definition at line 195 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM2 ( ) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)

Definition at line 83 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM3 ( ) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)

Definition at line 89 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_TIM4 ( ) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)

Definition at line 96 of file stm32f1xx_hal.h.

#define __HAL_DBGMCU_UNFREEZE_WWDG ( ) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)

Definition at line 151 of file stm32f1xx_hal.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC conversion cycles

Defines
ADC conversion cycles
ADC Private Constants

Defines

#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U

Define Documentation

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U

Definition at line 405 of file stm32f1xx_hal_adc.h.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U

Definition at line 403 of file stm32f1xx_hal_adc.h.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U

Definition at line 410 of file stm32f1xx_hal_adc.h.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U

Definition at line 406 of file stm32f1xx_hal_adc.h.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U

Definition at line 407 of file stm32f1xx_hal_adc.h.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U

Definition at line 408 of file stm32f1xx_hal_adc.h.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U

Definition at line 409 of file stm32f1xx_hal_adc.h.

#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U

Definition at line 404 of file stm32f1xx_hal_adc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC sampling times all channels

Defines
ADC sampling times all channels
ADC Private Constants

Defines

#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0
#define | ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
#define | ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define | ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
#define | ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define | ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
#define | ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define | ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
#define | ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define | ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)

Define Documentation

#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)

Definition at line 453 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)

Definition at line 444 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U

Definition at line 451 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U

Definition at line 442 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)

Definition at line 458 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)

Definition at line 449 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)

Definition at line 454 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)

Definition at line 445 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)

Definition at line 455 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)

Definition at line 446 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)

Definition at line 456 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)

Definition at line 447 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)

Definition at line 457 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)

Definition at line 448 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)

Definition at line 452 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)

Definition at line 443 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0
Value:
(ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
      ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )

Definition at line 438 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1
Value:
(ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
      ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )

Definition at line 430 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2
Value:
(ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
      ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )

Definition at line 422 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0
Value:
(ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 |     \
      ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 |     \
      ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)

Definition at line 434 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1
Value:
(ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 |     \
      ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 |     \
      ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)

Definition at line 426 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2
Value:
(ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 |     \
      ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 |     \
      ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)

Definition at line 418 of file stm32f1xx_hal_adc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Private Constants

Modules | Defines
ADC Private Constants
ADC

Modules

ADC conversion cycles
ADC sampling times all channels

Defines

#define | ADC_ENABLE_TIMEOUT 2U
#define | ADC_DISABLE_TIMEOUT 2U
#define | ADC_STAB_DELAY_US 1U
#define | ADC_TEMPSENSOR_DELAY_US 10U
#define | ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )

Define Documentation

#define ADC_DISABLE_TIMEOUT 2U

Definition at line 304 of file stm32f1xx_hal_adc.c.

Referenced by ADC_ConversionStop_Disable().

#define ADC_ENABLE_TIMEOUT 2U

Definition at line 303 of file stm32f1xx_hal_adc.c.

Referenced by ADC_Enable().

#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )

Definition at line 464 of file stm32f1xx_hal_adc.h.

#define ADC_STAB_DELAY_US 1U

Definition at line 309 of file stm32f1xx_hal_adc.c.

Referenced by ADC_Enable().

#define ADC_TEMPSENSOR_DELAY_US 10U

Definition at line 314 of file stm32f1xx_hal_adc.c.

Referenced by HAL_ADC_ConfigChannel().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Private Functions

Functions
ADC Private Functions
ADC

Functions

HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_ConversionStop_Disable (ADC_HandleTypeDef *hadc)
Stop ADC conversion and disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.
void | ADC_StabilizationTime (uint32_t DelayUs)

Function Documentation

HAL_StatusTypeDef ADC_ConversionStop_Disable ( ADC_HandleTypeDef * hadc )

Stop ADC conversion and disable the selected ADC.

Note:
Prerequisite condition to use this function: ADC conversions must be stopped to disable the ADC.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1989 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_DISABLE, ADC_DISABLE_TIMEOUT, ADC_IS_ENABLE, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), and HAL_ADCEx_MultiModeStop_DMA().

void ADC_DMAConvCplt ( DMA_HandleTypeDef * hdma )

DMA transfer complete callback.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 2027 of file stm32f1xx_hal_adc.c.

References ADC_IS_SOFTWARE_START_REGULAR, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_ConvCpltCallback(), HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::State, and __DMA_HandleTypeDef::XferErrorCallback.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_DMAError ( DMA_HandleTypeDef * hdma )

DMA error callback.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 2084 of file stm32f1xx_hal_adc.c.

References ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ErrorCallback(), HAL_ADC_STATE_ERROR_DMA, and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_DMAHalfConvCplt ( DMA_HandleTypeDef * hdma )

DMA half transfer complete callback.

Parameters:
hdma,: pointer to DMA handle.
Return values:
None

Definition at line 2070 of file stm32f1xx_hal_adc.c.

References HAL_ADC_ConvHalfCpltCallback().

Referenced by HAL_ADC_Start_DMA(), and HAL_ADCEx_MultiModeStart_DMA().

HAL_StatusTypeDef ADC_Enable ( ADC_HandleTypeDef * hadc )

Enable the selected ADC.

Note:
Prerequisite condition to use this function: ADC must be disabled and voltage regulator must be enabled (done into HAL_ADC_Init()).
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1934 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_ENABLE, ADC_ENABLE_TIMEOUT, ADC_IS_ENABLE, ADC_STAB_DELAY_US, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_GetTick(), and ADC_HandleTypeDef::State.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

void ADC_StabilizationTime ( uint32_t DelayUs )
Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization/de-initialization functions

Functions
Initialization/de-initialization functions
ADC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the ADC.
      (+) De-initialize the ADC.

Function Documentation

HAL_StatusTypeDef HAL_ADC_DeInit ( ADC_HandleTypeDef * hadc )

Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.

If needed, the example code can be copied and uncommented into function HAL_ADC_MspDeInit().

Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 575 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_ConversionStop_Disable(), ADC_FLAG_AWD, ADC_FLAG_EOC, ADC_FLAG_JEOC, ADC_FLAG_JSTRT, ADC_FLAG_STRT, assert_param, HAL_ADC_MspDeInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_RESET, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Init ( ADC_HandleTypeDef * hadc )

Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".

Note:
As prerequisite, ADC clock must be configured at RCC top level (clock source APB2). See commented example code below that can be copied and uncommented into HAL_ADC_MspInit().
Possibility to update parameters on the fly: This function initializes the ADC MSP (HAL_ADC_MspInit()) only when coming from ADC state reset. Following calls to this function can be used to reconfigure some parameters of ADC_InitTypeDef structure on the fly, without modifying MSP configuration. If ADC MSP has to be modified again, HAL_ADC_DeInit() must be called before HAL_ADC_Init(). The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_InitTypeDef".
This function configures the ADC within 2 scopes: scope of entire ADC and scope of regular group. For parameters details, see comments of structure "ADC_InitTypeDef".
Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 374 of file stm32f1xx_hal_adc.c.

References ADC_CFGR_EXTSEL, ADC_CLEAR_ERRORCODE, ADC_ConversionStop_Disable(), ADC_CR1_DISCONTINUOUS_NUM, ADC_CR1_SCAN_SET, ADC_CR2_CONTINUOUS, ADC_SCAN_DISABLE, ADC_SCAN_ENABLE, ADC_SQR1_L_SHIFT, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_InitTypeDef::DataAlign, ADC_InitTypeDef::DiscontinuousConvMode, ADC_HandleTypeDef::ErrorCode, ADC_InitTypeDef::ExternalTrigConv, HAL_ADC_ERROR_INTERNAL, HAL_ADC_MspInit(), HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_RESET, ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_DATA_ALIGN, IS_ADC_EXTTRIG, IS_ADC_REGULAR_DISCONT_NUMBER, IS_ADC_REGULAR_NB_CONV, IS_ADC_SCAN_MODE, ADC_HandleTypeDef::Lock, ADC_InitTypeDef::NbrOfConversion, ADC_InitTypeDef::NbrOfDiscConversion, ADC_InitTypeDef::ScanConvMode, and ADC_HandleTypeDef::State.

void HAL_ADC_MspDeInit ( ADC_HandleTypeDef * hadc )

DeInitializes the ADC MSP.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 727 of file stm32f1xx_hal_adc.c.

Referenced by HAL_ADC_DeInit().

void HAL_ADC_MspInit ( ADC_HandleTypeDef * hadc )

Initializes the ADC MSP.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 713 of file stm32f1xx_hal_adc.c.

Referenced by HAL_ADC_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
ADC Exported Functions

Input and Output operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non blocking mode (ADC conversion with interruption or transfer by DMA)

Detailed Description

Input and Output operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of regular group.
      (+) Stop conversion of regular group.
      (+) Poll for conversion complete on regular group.
      (+) Poll for conversion event.
      (+) Get result of regular channel conversion.
      (+) Start conversion of regular group and enable interruptions.
      (+) Stop conversion of regular group and disable interruptions.
      (+) Handle ADC interrupt request
      (+) Start conversion of regular group and enable DMA transfer.
      (+) Stop conversion of regular group and disable ADC DMA transfer.

Function Documentation

void HAL_ADC_ConvCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion complete callback in non blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1611 of file stm32f1xx_hal_adc.c.

Referenced by ADC_DMAConvCplt(), and HAL_ADC_IRQHandler().

void HAL_ADC_ConvHalfCpltCallback ( ADC_HandleTypeDef * hadc )

Conversion DMA half-transfer callback in non blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1625 of file stm32f1xx_hal_adc.c.

Referenced by ADC_DMAHalfConvCplt().

void HAL_ADC_ErrorCallback ( ADC_HandleTypeDef * hadc )

ADC error callback in non blocking mode (ADC conversion with interruption or transfer by DMA)

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1654 of file stm32f1xx_hal_adc.c.

Referenced by ADC_DMAError().

uint32_t HAL_ADC_GetValue ( ADC_HandleTypeDef * hadc )

Get ADC regular group conversion result.

Note:
Reading register DR automatically clears ADC flag EOC (ADC group regular end of unitary conversion).
This function does not clear ADC flag EOS (ADC group regular end of sequence conversion). Occurrence of flag EOS rising:
  • If sequencer is composed of 1 rank, flag EOS is equivalent to flag EOC.
  • If sequencer is composed of several ranks, during the scan sequence flag EOC only is raised, at the end of the scan sequence both flags EOC and EOS are raised. To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADC_PollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
Parameters:
hadc,: ADC handle
Return values:
ADC group regular conversion data

Definition at line 1479 of file stm32f1xx_hal_adc.c.

References assert_param, and ADC_HandleTypeDef::Instance.

void HAL_ADC_IRQHandler ( ADC_HandleTypeDef * hadc )

Handles ADC interrupt request.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1496 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_DISABLE_IT, __HAL_ADC_GET_FLAG, __HAL_ADC_GET_IT_SOURCE, ADC_FLAG_AWD, ADC_FLAG_EOC, ADC_FLAG_JEOC, ADC_FLAG_JSTRT, ADC_FLAG_STRT, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_AWD, ADC_IT_EOC, ADC_IT_JEOC, assert_param, ADC_InitTypeDef::ContinuousConvMode, HAL_ADC_ConvCpltCallback(), HAL_ADC_LevelOutOfWindowCallback(), HAL_ADC_STATE_AWD1, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADCEx_InjectedConvCpltCallback(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, IS_ADC_REGULAR_NB_CONV, ADC_InitTypeDef::NbrOfConversion, and ADC_HandleTypeDef::State.

void HAL_ADC_LevelOutOfWindowCallback ( ADC_HandleTypeDef * hadc )

Analog watchdog callback in non blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1639 of file stm32f1xx_hal_adc.c.

Referenced by HAL_ADC_IRQHandler().

HAL_StatusTypeDef HAL_ADC_PollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for regular group conversion to be completed.

Note:
This function cannot be used in a particular setup: ADC configured in DMA mode. In this case, DMA resets the flag EOC and polling cannot be performed on each conversion.
On STM32F1 devices, limitation in case of sequencer enabled (several ranks selected): polling cannot be done on each conversion inside the sequence. In this case, polling is replaced by wait for maximum conversion time.
Parameters:
hadc,: ADC handle
Timeout,: Timeout value in millisecond.
Return values:
HAL status

Definition at line 925 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CONVCYCLES_MAX_RANGE, ADC_FLAG_EOC, ADC_FLAG_STRT, ADC_IS_SOFTWARE_START_REGULAR, assert_param, ADC_InitTypeDef::ContinuousConvMode, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), HAL_RCCEx_GetPeriphCLKFreq(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, RCC_PERIPHCLK_ADC, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_PollForEvent | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | EventType,
 |  | uint32_t | Timeout
 | ) |  |

Poll for conversion event.

Parameters:
hadc,: ADC handle
EventType,: the ADC event type. This parameter can be one of the following values:
  • ADC_AWD_EVENT: ADC Analog watchdog event.
Timeout,: Timeout value in millisecond.
Return values:
HAL status

Definition at line 1056 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_GET_FLAG, ADC_FLAG_AWD, assert_param, HAL_ADC_STATE_AWD1, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), ADC_HandleTypeDef::Instance, IS_ADC_EVENT_TYPE, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start ( ADC_HandleTypeDef * hadc )

Enables ADC, starts conversion of regular group.

Interruptions enabled in this function: None.

Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 768 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_EOC, ADC_IS_SOFTWARE_START_REGULAR, ADC_MULTIMODE_AUTO_INJECTED, ADC_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Start_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enables ADC, starts conversion of regular group and transfers result through DMA.

Interruptions enabled in this function:

  • DMA transfer complete
  • DMA half transfer Each of these interruptions has its dedicated callback function.
    Note:
    For devices with several ADCs: This function is for single-ADC mode only. For multimode, use the dedicated MultimodeStart function.
    On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending on devices) have DMA capability. ADC2 converted data can be transferred in dual ADC mode using DMA of ADC1 (ADC master in multimode). In case of using ADC1 with DMA on a device featuring 2 ADC instances: ADC1 conversion register DR contains ADC1 conversion result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last conversion result (ADC1 register DR bits 16 to 27). Therefore, to have DMA transferring the conversion results of ADC1 only, DMA must be configured to transfer size: half word.
    Parameters:
    hadc,: ADC handle
    pData,: The destination Buffer address.
    Length,: The length of data to be transferred from ADC peripheral to memory.
    Return values:
    None

Definition at line 1273 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_IS_SOFTWARE_START_REGULAR, ADC_MULTIMODE_AUTO_INJECTED, ADC_MULTIMODE_IS_ENABLE, ADC_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, HAL_DMA_Start_IT(), ADC_HandleTypeDef::Instance, ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADC_Start_IT ( ADC_HandleTypeDef * hadc )

Enables ADC, starts conversion of regular group with interruption.

Interruptions enabled in this function:

  • EOC (end of conversion of regular group) Each of these interruptions has its dedicated callback function.
    Parameters:
    hadc,: ADC handle
    Return values:
    HAL status

Definition at line 1105 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_EOC, ADC_IS_SOFTWARE_START_REGULAR, ADC_IT_EOC, ADC_MULTIMODE_AUTO_INJECTED, ADC_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::ErrorCode, HAL_ADC_ERROR_DMA, HAL_ADC_ERROR_OVR, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_OVR, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 881 of file stm32f1xx_hal_adc.c.

References ADC_ConversionStop_Disable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.

Note:
: ADC peripheral disable is forcing stop of potential conversion on injected group. If injected group is under use, it should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
For devices with several ADCs: This function is for single-ADC mode only. For multimode, use the dedicated MultimodeStop function.
On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending on devices) have DMA capability.
Parameters:
hadc,: ADC handle
Return values:
HAL status.

Definition at line 1414 of file stm32f1xx_hal_adc.c.

References ADC_ConversionStop_Disable(), ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADC_Stop_IT ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 1216 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop_Disable(), ADC_IT_EOC, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
ADC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures the the selected channel to be linked to the regular group.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.

Detailed Description

Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on regular group
      (+) Configure the analog watchdog

Function Documentation

HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_AnalogWDGConfTypeDef * | AnalogWDGConfig
 | ) |  |

Configures the analog watchdog.

Note:
Analog watchdog thresholds can be modified while ADC conversion is on going. In this case, some constraints must be taken into account: the programmed threshold values are effective from the next ADC EOC (end of unitary conversion). Considering that registers write delay may happen due to bus activity, this might cause an uncertainty on the effective timing of the new programmed threshold values.
Parameters:
hadc,: ADC handle
AnalogWDGConfig,: Structure of ADC analog watchdog configuration
Return values:
HAL status

Definition at line 1812 of file stm32f1xx_hal_adc.c.

References __HAL_ADC_DISABLE_IT, __HAL_ADC_ENABLE_IT, ADC_ANALOGWATCHDOG_SINGLE_INJEC, ADC_ANALOGWATCHDOG_SINGLE_REG, ADC_ANALOGWATCHDOG_SINGLE_REGINJEC, ADC_IT_AWD, assert_param, ADC_AnalogWDGConfTypeDef::Channel, ADC_AnalogWDGConfTypeDef::HighThreshold, ADC_HandleTypeDef::Instance, IS_ADC_ANALOG_WATCHDOG_MODE, IS_ADC_CHANNEL, IS_ADC_RANGE, ADC_AnalogWDGConfTypeDef::ITMode, ADC_AnalogWDGConfTypeDef::LowThreshold, and ADC_AnalogWDGConfTypeDef::WatchdogMode.

HAL_StatusTypeDef HAL_ADC_ConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_ChannelConfTypeDef * | sConfig
 | ) |  |

Configures the the selected channel to be linked to the regular group.

Note:
In case of usage of internal measurement channels: Vbat/VrefInt/TempSensor. These internal paths can be be disabled using function HAL_ADC_DeInit().
Possibility to update parameters on the fly: This function initializes channel into regular group, following calls to this function can be used to reconfigure some parameters of structure "ADC_ChannelConfTypeDef" on the fly, without reseting the ADC. The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_ChannelConfTypeDef".
Parameters:
hadc,: ADC handle
sConfig,: Structure of ADC channel for regular group.
Return values:
HAL status

Definition at line 1702 of file stm32f1xx_hal_adc.c.

References ADC_CHANNEL_10, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VREFINT, ADC_SMPR1, ADC_SMPR2, ADC_SQR1_RK, ADC_SQR2_RK, ADC_SQR3_RK, ADC_TEMPSENSOR_DELAY_US, assert_param, ADC_ChannelConfTypeDef::Channel, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_REGULAR_RANK, IS_ADC_SAMPLE_TIME, ADC_ChannelConfTypeDef::Rank, ADC_ChannelConfTypeDef::SamplingTime, and ADC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
ADC Exported Functions

Peripheral State functions. More...

Functions

uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.

Detailed Description

Peripheral State functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions to get in run-time the status of the
    peripheral.
      (+) Check the ADC state
      (+) Check the ADC error code

Function Documentation

uint32_t HAL_ADC_GetError ( ADC_HandleTypeDef * hadc )

Return the ADC error code.

Parameters:
hadc,: ADC handle
Return values:
ADC Error Code

Definition at line 1910 of file stm32f1xx_hal_adc.c.

References ADC_HandleTypeDef::ErrorCode.

uint32_t HAL_ADC_GetState ( ADC_HandleTypeDef * hadc )

return the ADC state

Parameters:
hadc,: ADC handle
Return values:
HAL state

Definition at line 1899 of file stm32f1xx_hal_adc.c.

References ADC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Exported Types

Data Structures | Defines
ADC Exported Types
ADC

Data Structures

struct | ADC_InitTypeDef
Structure definition of ADC and regular group initialization. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
ADC Configuration analog watchdog definition. More...
struct | ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET 0x00000000U
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY 0x00000001U
#define | HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U
#define | HAL_ADC_STATE_TIMEOUT 0x00000004U
#define | HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U
#define | HAL_ADC_STATE_ERROR_CONFIG 0x00000020U
#define | HAL_ADC_STATE_ERROR_DMA 0x00000040U
#define | HAL_ADC_STATE_REG_BUSY 0x00000100U
#define | HAL_ADC_STATE_REG_EOC 0x00000200U
#define | HAL_ADC_STATE_REG_OVR 0x00000400U
#define | HAL_ADC_STATE_REG_EOSMP 0x00000800U
#define | HAL_ADC_STATE_INJ_BUSY 0x00001000U
#define | HAL_ADC_STATE_INJ_EOC 0x00002000U
#define | HAL_ADC_STATE_INJ_JQOVF 0x00004000U
#define | HAL_ADC_STATE_AWD1 0x00010000U
#define | HAL_ADC_STATE_AWD2 0x00020000U
#define | HAL_ADC_STATE_AWD3 0x00040000U
#define | HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U

Define Documentation

#define HAL_ADC_STATE_AWD1 0x00010000U

Out-of-window occurrence of analog watchdog 1

Definition at line 181 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define HAL_ADC_STATE_AWD2 0x00020000U

Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2

Definition at line 182 of file stm32f1xx_hal_adc.h.

#define HAL_ADC_STATE_AWD3 0x00040000U

Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3

Definition at line 183 of file stm32f1xx_hal_adc.h.

#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U

ADC is busy to internal process (initialization, calibration)

Definition at line 159 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), and HAL_ADCEx_Calibration_Start().

#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U

Configuration error occurrence

Definition at line 164 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), HAL_ADC_Init(), HAL_ADC_PollForConversion(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_ERROR_DMA 0x00000040U

DMA error occurrence

Definition at line 165 of file stm32f1xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), ADC_DMAError(), HAL_ADC_Stop_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U

Internal error occurrence

Definition at line 163 of file stm32f1xx_hal_adc.h.

Referenced by ADC_ConversionStop_Disable(), ADC_DMAConvCplt(), ADC_Enable(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADCEx_Calibration_Start(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_INJ_BUSY 0x00001000U

A conversion on group injected is ongoing or can occur (either by auto-injection mode, external trigger, low power auto power-on, multimode ADC master control)

Definition at line 175 of file stm32f1xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_INJ_EOC 0x00002000U

Conversion data available on group injected

Definition at line 177 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U

Not available on STM32F1 device: Injected queue overflow occurrence

Definition at line 178 of file stm32f1xx_hal_adc.h.

#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U

ADC in multimode slave state, controlled by another ADC master (

Definition at line 186 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_READY 0x00000001U

ADC peripheral ready for use

Definition at line 158 of file stm32f1xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_REG_BUSY 0x00000100U

A conversion on group regular is ongoing or can occur (either by continuous mode, external trigger, low power auto power-on, multimode ADC master control)

Definition at line 168 of file stm32f1xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define HAL_ADC_STATE_REG_EOC 0x00000200U

Conversion data available on group regular

Definition at line 170 of file stm32f1xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define HAL_ADC_STATE_REG_EOSMP 0x00000800U

Not available on STM32F1 device: End Of Sampling flag raised

Definition at line 172 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_STATE_REG_OVR 0x00000400U

Not available on STM32F1 device: Overrun occurrence

Definition at line 171 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_STATE_RESET 0x00000000U

HAL ADC state machine: ADC states definition (bitfields)

ADC not yet initialized or disabled

Definition at line 157 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), and HAL_ADC_Init().

#define HAL_ADC_STATE_TIMEOUT 0x00000004U

TimeOut occurrence

Definition at line 160 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), and HAL_ADCEx_InjectedPollForConversion().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InitTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC and regular group initialization. More...

#include <stm32f1xx_hal_adc.h>

Data Fields

uint32_t | DataAlign
uint32_t | ScanConvMode
uint32_t | ContinuousConvMode
uint32_t | NbrOfConversion
uint32_t | DiscontinuousConvMode
uint32_t | NbrOfDiscConversion
uint32_t | ExternalTrigConv

Detailed Description

Structure definition of ADC and regular group initialization.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
  • Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. ADC can be either disabled or enabled without conversion on going on regular group.

Definition at line 69 of file stm32f1xx_hal_adc.h.

Field Documentation

uint32_t ADC_InitTypeDef::ContinuousConvMode

Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, after the selected trigger occurred (software start or external trigger). This parameter can be set to ENABLE or DISABLE.

Definition at line 85 of file stm32f1xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

uint32_t ADC_InitTypeDef::DataAlign

Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). This parameter can be a value of ADC data alignment

Definition at line 71 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::DiscontinuousConvMode

Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE.

Definition at line 91 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ExternalTrigConv

Selects the external event used to trigger the conversion start of regular group. If set to ADC_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of ADC External trigger selection for regular group

Definition at line 98 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::NbrOfConversion

Specifies the number of ranks that will be converted within the regular group sequencer. To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16.

Definition at line 88 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

uint32_t ADC_InitTypeDef::NbrOfDiscConversion

Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. This parameter must be a number between Min_Data = 1 and Max_Data = 8.

Definition at line 95 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

uint32_t ADC_InitTypeDef::ScanConvMode

Configures the sequencer of regular and injected groups. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). Scan direction is upward: from rank1 to rank 'n'. This parameter can be a value of ADC scan mode Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1) or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the the last conversion of the sequence. All previous conversions would be overwritten by the last one. Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten.

Definition at line 74 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_adc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC_ChannelConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_ChannelConfTypeDef Struct Reference
ADC Exported Types

Structure definition of ADC channel for regular group. More...

#include <stm32f1xx_hal_adc.h>

Data Fields

uint32_t | Channel
uint32_t | Rank
uint32_t | SamplingTime

Detailed Description

Structure definition of ADC channel for regular group.

Note:
The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. ADC can be either disabled or enabled without conversion on going on regular group.

Definition at line 109 of file stm32f1xx_hal_adc.h.

Field Documentation

uint32_t ADC_ChannelConfTypeDef::Channel

Specifies the channel to configure into ADC regular group. This parameter can be a value of ADC channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details.

Definition at line 111 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::Rank

Specifies the rank in the regular group sequencer This parameter can be a value of ADC rank into regular group Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted)

Definition at line 118 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

uint32_t ADC_ChannelConfTypeDef::SamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of ADC sampling times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min).

Definition at line 121 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_adc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC_AnalogWDGConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_AnalogWDGConfTypeDef Struct Reference
ADC Exported Types

ADC Configuration analog watchdog definition. More...

#include <stm32f1xx_hal_adc.h>

Data Fields

uint32_t | WatchdogMode
uint32_t | Channel
uint32_t | ITMode
uint32_t | HighThreshold
uint32_t | LowThreshold
uint32_t | WatchdogNumber

Detailed Description

ADC Configuration analog watchdog definition.

Note:
The setting of these parameters with function is conditioned to ADC state. ADC state can be either disabled or enabled without conversion on going on regular and injected groups.

Definition at line 137 of file stm32f1xx_hal_adc.h.

Field Documentation

uint32_t ADC_AnalogWDGConfTypeDef::Channel

Selects which ADC channel to monitor by analog watchdog. This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) This parameter can be a value of ADC channels.

Definition at line 141 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::HighThreshold

Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF.

Definition at line 146 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::ITMode

Specifies whether the analog watchdog is configured in interrupt or polling mode. This parameter can be set to ENABLE or DISABLE

Definition at line 144 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::LowThreshold

Configures the ADC analog watchdog High threshold value. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF.

Definition at line 148 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogMode

Configures the ADC analog watchdog mode: single/all channels, regular/injected group. This parameter can be a value of ADC analog watchdog mode.

Definition at line 139 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

uint32_t ADC_AnalogWDGConfTypeDef::WatchdogNumber

Reserved for future use, can be set to 0

Definition at line 150 of file stm32f1xx_hal_adc.h.

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_adc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_HandleTypeDef Struct Reference
ADC Exported Types

ADC handle Structure definition. More...

#include <stm32f1xx_hal_adc.h>

Data Fields

ADC_TypeDef * | Instance
ADC_InitTypeDef Init
DMA_HandleTypeDef * DMA_Handle
HAL_LockTypeDef | Lock
__IO uint32_t | State
__IO uint32_t | ErrorCode

Detailed Description

ADC handle Structure definition.

Definition at line 192 of file stm32f1xx_hal_adc.h.

Field Documentation

DMA_HandleTypeDef* ADC_HandleTypeDef::DMA_Handle

Pointer DMA Handler

Definition at line 198 of file stm32f1xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Start_DMA(), HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

__IO uint32_t ADC_HandleTypeDef::ErrorCode

ADC Error code

Definition at line 204 of file stm32f1xx_hal_adc.h.

Referenced by ADC_ConversionStop_Disable(), ADC_DMAError(), ADC_Enable(), HAL_ADC_GetError(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

ADC_InitTypeDef ADC_HandleTypeDef::Init

ADC required parameters

Definition at line 196 of file stm32f1xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

ADC_TypeDef* ADC_HandleTypeDef::Instance

Register base address

Definition at line 194 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

HAL_LockTypeDef ADC_HandleTypeDef::Lock

ADC locking object

Definition at line 200 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

__IO uint32_t ADC_HandleTypeDef::State

ADC communication state (bitmap of ADC states)

Definition at line 202 of file stm32f1xx_hal_adc.h.

Referenced by ADC_ConversionStop_Disable(), ADC_DMAConvCplt(), ADC_DMAError(), ADC_Enable(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetState(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_adc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Error Code

Defines
ADC Error Code
ADC Exported Constants

Defines

#define | HAL_ADC_ERROR_NONE 0x00U
#define | HAL_ADC_ERROR_INTERNAL 0x01U
#define | HAL_ADC_ERROR_OVR 0x02U
#define | HAL_ADC_ERROR_DMA 0x04U

Define Documentation

#define HAL_ADC_ERROR_DMA 0x04U

DMA transfer error

Definition at line 225 of file stm32f1xx_hal_adc.h.

Referenced by ADC_DMAError(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define HAL_ADC_ERROR_INTERNAL 0x01U

ADC IP internal error: if problem of clocking, enable/disable, erroneous state

Definition at line 222 of file stm32f1xx_hal_adc.h.

Referenced by ADC_ConversionStop_Disable(), ADC_Enable(), and HAL_ADC_Init().

#define HAL_ADC_ERROR_NONE 0x00U

No error

Definition at line 221 of file stm32f1xx_hal_adc.h.

#define HAL_ADC_ERROR_OVR 0x02U

Overrun error

Definition at line 224 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC data alignment

Defines
ADC data alignment
ADC Exported Constants

Defines

#define | ADC_DATAALIGN_RIGHT 0x00000000U
#define | ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)

Define Documentation

#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)

Definition at line 236 of file stm32f1xx_hal_adc.h.

#define ADC_DATAALIGN_RIGHT 0x00000000U

Definition at line 235 of file stm32f1xx_hal_adc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC scan mode

Defines
ADC scan mode
ADC Exported Constants

Defines

#define | ADC_SCAN_DISABLE 0x00000000U
#define | ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)

Define Documentation

#define ADC_SCAN_DISABLE 0x00000000U

Definition at line 247 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)

Definition at line 248 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC external trigger enable for regular group

Defines
ADC external trigger enable for regular group
ADC Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)

Define Documentation

#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U

Definition at line 256 of file stm32f1xx_hal_adc.h.

#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)

Definition at line 257 of file stm32f1xx_hal_adc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC channels

Defines
ADC channels
ADC Exported Constants

Defines

#define | ADC_CHANNEL_0 0x00000000U
#define | ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
#define | ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
#define | ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
#define | ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
#define | ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 ))
#define | ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 ))
#define | ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
#define | ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
#define | ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */

Define Documentation

#define ADC_CHANNEL_0 0x00000000U

Definition at line 267 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))

Definition at line 268 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 ))

Definition at line 277 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))

Definition at line 278 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 ))

Definition at line 279 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))

Definition at line 280 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))

Definition at line 281 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))

Definition at line 282 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))

Definition at line 283 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))

Definition at line 284 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))

Definition at line 269 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))

Definition at line 270 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))

Definition at line 271 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))

Definition at line 272 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))

Definition at line 273 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))

Definition at line 274 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))

Definition at line 275 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))

Definition at line 276 of file stm32f1xx_hal_adc.h.

#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */

Definition at line 286 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */

Definition at line 287 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC sampling times

Defines
ADC sampling times
ADC Exported Constants

Defines

#define | ADC_SAMPLETIME_1CYCLE_5 0x00000000U
#define | ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0))
#define | ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 ))
#define | ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))
#define | ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 ))
#define | ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0))
#define | ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 ))
#define | ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))

Define Documentation

#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 ))

Sampling time 13.5 ADC clock cycles

Definition at line 297 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U

Sampling time 1.5 ADC clock cycle

Definition at line 295 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))

Sampling time 239.5 ADC clock cycles

Definition at line 302 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))

Sampling time 28.5 ADC clock cycles

Definition at line 298 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 ))

Sampling time 41.5 ADC clock cycles

Definition at line 299 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0))

Sampling time 55.5 ADC clock cycles

Definition at line 300 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 ))

Sampling time 71.5 ADC clock cycles

Definition at line 301 of file stm32f1xx_hal_adc.h.

#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0))

Sampling time 7.5 ADC clock cycles

Definition at line 296 of file stm32f1xx_hal_adc.h.

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STM32F103xB HAL User Manual: ADC rank into regular group

Defines
ADC rank into regular group
ADC Exported Constants

Defines

#define | ADC_REGULAR_RANK_1 0x00000001U
#define | ADC_REGULAR_RANK_2 0x00000002U
#define | ADC_REGULAR_RANK_3 0x00000003U
#define | ADC_REGULAR_RANK_4 0x00000004U
#define | ADC_REGULAR_RANK_5 0x00000005U
#define | ADC_REGULAR_RANK_6 0x00000006U
#define | ADC_REGULAR_RANK_7 0x00000007U
#define | ADC_REGULAR_RANK_8 0x00000008U
#define | ADC_REGULAR_RANK_9 0x00000009U
#define | ADC_REGULAR_RANK_10 0x0000000AU
#define | ADC_REGULAR_RANK_11 0x0000000BU
#define | ADC_REGULAR_RANK_12 0x0000000CU
#define | ADC_REGULAR_RANK_13 0x0000000DU
#define | ADC_REGULAR_RANK_14 0x0000000EU
#define | ADC_REGULAR_RANK_15 0x0000000FU
#define | ADC_REGULAR_RANK_16 0x00000010U

Define Documentation

#define ADC_REGULAR_RANK_1 0x00000001U

Definition at line 310 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_10 0x0000000AU

Definition at line 319 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_11 0x0000000BU

Definition at line 320 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_12 0x0000000CU

Definition at line 321 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_13 0x0000000DU

Definition at line 322 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_14 0x0000000EU

Definition at line 323 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_15 0x0000000FU

Definition at line 324 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_16 0x00000010U

Definition at line 325 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_2 0x00000002U

Definition at line 311 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_3 0x00000003U

Definition at line 312 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_4 0x00000004U

Definition at line 313 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_5 0x00000005U

Definition at line 314 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_6 0x00000006U

Definition at line 315 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_7 0x00000007U

Definition at line 316 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_8 0x00000008U

Definition at line 317 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_RANK_9 0x00000009U

Definition at line 318 of file stm32f1xx_hal_adc.h.

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STM32F103xB HAL User Manual: ADC analog watchdog mode

Defines
ADC analog watchdog mode
ADC Exported Constants

Defines

#define | ADC_ANALOGWATCHDOG_NONE 0x00000000U
#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))

Define Documentation

#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)

Definition at line 338 of file stm32f1xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)

Definition at line 337 of file stm32f1xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))

Definition at line 339 of file stm32f1xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_NONE 0x00000000U

Definition at line 333 of file stm32f1xx_hal_adc.h.

#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))

Definition at line 335 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))

Definition at line 334 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))

Definition at line 336 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC conversion group

Defines
ADC conversion group
ADC Exported Constants

Defines

#define | ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
#define | ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
#define | ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))

Define Documentation

#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))

Definition at line 348 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))

Definition at line 347 of file stm32f1xx_hal_adc.h.

#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))

Definition at line 349 of file stm32f1xx_hal_adc.h.

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STM32F103xB HAL User Manual: ADC Event type

Defines
ADC Event type
ADC Exported Constants

Defines

#define | ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define | ADC_AWD1_EVENT ADC_AWD_EVENT

Define Documentation

#define ADC_AWD1_EVENT ADC_AWD_EVENT

ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs

Definition at line 359 of file stm32f1xx_hal_adc.h.

#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)

ADC Analog watchdog event

Definition at line 357 of file stm32f1xx_hal_adc.h.

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STM32F103xB HAL User Manual: ADC interrupts definition

Defines
ADC interrupts definition
ADC Exported Constants

Defines

#define | ADC_IT_EOC ADC_CR1_EOCIE
#define | ADC_IT_JEOC ADC_CR1_JEOCIE
#define | ADC_IT_AWD ADC_CR1_AWDIE

Define Documentation

#define ADC_IT_AWD ADC_CR1_AWDIE

ADC Analog watchdog interrupt source

Definition at line 369 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADC_IRQHandler().

#define ADC_IT_EOC ADC_CR1_EOCIE

ADC End of Regular Conversion interrupt source

Definition at line 367 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADC_Start_IT(), and HAL_ADC_Stop_IT().

#define ADC_IT_JEOC ADC_CR1_JEOCIE

ADC End of Injected Conversion interrupt source

Definition at line 368 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_InjectedStop_IT().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC flags definition

Defines
ADC flags definition
ADC Exported Constants

Defines

#define | ADC_FLAG_STRT ADC_SR_STRT
#define | ADC_FLAG_JSTRT ADC_SR_JSTRT
#define | ADC_FLAG_EOC ADC_SR_EOC
#define | ADC_FLAG_JEOC ADC_SR_JEOC
#define | ADC_FLAG_AWD ADC_SR_AWD

Define Documentation

#define ADC_FLAG_AWD ADC_SR_AWD

ADC Analog watchdog flag

Definition at line 381 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define ADC_FLAG_EOC ADC_SR_EOC

ADC End of Regular conversion flag

Definition at line 379 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_FLAG_JEOC ADC_SR_JEOC

ADC End of Injected conversion flag

Definition at line 380 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_FLAG_JSTRT ADC_SR_JSTRT

ADC Injected group start flag

Definition at line 378 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_FLAG_STRT ADC_SR_STRT

ADC Regular group start flag

Definition at line 377 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), and HAL_ADC_PollForConversion().

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STM32F103xB HAL User Manual: ADC Exported Macros

Defines
ADC Exported Macros
ADC

Defines

#define | __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
Enable the ADC peripheral.
#define | __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
Disable the ADC peripheral.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Enable the ADC end of conversion interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Disable the ADC end of conversion interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected ADC's flag status.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
Clear the ADC's pending flags.
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.

Define Documentation

#define __HAL_ADC_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))

Clear the ADC's pending flags.

Parameters:
__HANDLE__,: ADC handle
__FLAG__,: ADC flag This parameter can be any combination of the following values:
  • ADC_FLAG_STRT: ADC Regular group start flag
  • ADC_FLAG_JSTRT: ADC Injected group start flag
  • ADC_FLAG_EOC: ADC End of Regular conversion flag
  • ADC_FLAG_JEOC: ADC End of Injected conversion flag
  • ADC_FLAG_AWD: ADC Analog watchdog flag
Return values:
None

Definition at line 560 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define __HAL_ADC_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))

Disable the ADC peripheral.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 496 of file stm32f1xx_hal_adc.h.

Referenced by ADC_ConversionStop_Disable().

#define __HAL_ADC_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))

Disable the ADC end of conversion interrupt.

Parameters:
__HANDLE__,: ADC handle
__INTERRUPT__,: ADC Interrupt This parameter can be any combination of the following values:
  • ADC_IT_EOC: ADC End of Regular Conversion interrupt source
  • ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
  • ADC_IT_AWD: ADC Analog watchdog interrupt source
Return values:
None

Definition at line 520 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_IRQHandler(), HAL_ADC_Stop_IT(), and HAL_ADCEx_InjectedStop_IT().

#define __HAL_ADC_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))

Enable the ADC peripheral.

Note:
ADC enable requires a delay for ADC stabilization time (refer to device datasheet, parameter tSTAB)
On STM32F1, if ADC is already enabled this macro trigs a conversion SW start on regular group.
Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 488 of file stm32f1xx_hal_adc.h.

Referenced by ADC_Enable().

#define __HAL_ADC_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))

Enable the ADC end of conversion interrupt.

Parameters:
__HANDLE__,: ADC handle
__INTERRUPT__,: ADC Interrupt This parameter can be any combination of the following values:
  • ADC_IT_EOC: ADC End of Regular Conversion interrupt source
  • ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
  • ADC_IT_AWD: ADC Analog watchdog interrupt source
Return values:
None

Definition at line 508 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_Start_IT(), and HAL_ADCEx_InjectedStart_IT().

#define __HAL_ADC_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Get the selected ADC's flag status.

Parameters:
__HANDLE__,: ADC handle
__FLAG__,: ADC flag This parameter can be any combination of the following values:
  • ADC_FLAG_STRT: ADC Regular group start flag
  • ADC_FLAG_JSTRT: ADC Injected group start flag
  • ADC_FLAG_EOC: ADC End of Regular conversion flag
  • ADC_FLAG_JEOC: ADC End of Injected conversion flag
  • ADC_FLAG_AWD: ADC Analog watchdog flag
Return values:
None

Definition at line 546 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), and HAL_ADC_PollForEvent().

#define __HAL_ADC_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified ADC interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: ADC handle
__INTERRUPT__,: ADC interrupt source to check This parameter can be any combination of the following values:
  • ADC_IT_EOC: ADC End of Regular Conversion interrupt source
  • ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
  • ADC_IT_AWD: ADC Analog watchdog interrupt source
Return values:
None

Definition at line 532 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler().

#define __HAL_ADC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

Reset ADC handle state.

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 567 of file stm32f1xx_hal_adc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC range verification

Defines
ADC range verification
ADC Private Macros

For a unique ADC resolution: 12 bits. More...

Defines

#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)

Detailed Description

For a unique ADC resolution: 12 bits.

Define Documentation

#define IS_ADC_RANGE ( ADC_VALUE ) ((ADC_VALUE) <= 0x0FFFU)

Definition at line 828 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), and HAL_ADCEx_InjectedConfigChannel().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC regular nb conv verification

Defines
ADC regular nb conv verification
ADC Private Macros

Defines

#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))

Define Documentation

#define IS_ADC_REGULAR_NB_CONV ( LENGTH ) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))

Definition at line 836 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init(), and HAL_ADC_IRQHandler().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC regular discontinuous mode number verification

Defines
ADC regular discontinuous mode number verification
ADC Private Macros

Defines

#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))

Define Documentation

#define IS_ADC_REGULAR_DISCONT_NUMBER ( NUMBER ) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))

Definition at line 844 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Private Macros

Modules | Defines
ADC Private Macros
ADC

Modules

ADC range verification

For a unique ADC resolution: 12 bits.

ADC regular nb conv verification
ADC regular discontinuous mode number verification

Defines

#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clears and sets specific bits of the handle State.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to error code: "no error")
#define | ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
Set ADC number of conversions into regular channel sequence length.
#define | ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
Set the ADC's sample time for channel numbers between 10 and 18.
#define | ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
Set the ADC's sample time for channel numbers between 0 and 9.
#define | ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
Set the selected regular channel rank for rank between 1 and 6.
#define | ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
Set the selected regular channel rank for rank between 7 and 12.
#define | ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
Set the selected regular channel rank for rank between 13 and 16.
#define | ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
Set the injected sequence length.
#define | ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
Set the selected injected channel rank Note: on STM32F1 devices, channel rank position in JSQR register is depending on total number of ranks selected into injected sequencer (ranks sequence starting from 4-JL)
#define | ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
Enable ADC continuous conversion mode.
#define | ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
Configures the number of discontinuous conversions for the regular group channels.
#define | ADC_CR1_SCAN_SET(_SCAN_MODE_)
Enable ADC scan mode to convert multiple ranks with sequencer.
#define | ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)
Get the maximum ADC conversion cycles on all channels.
#define | IS_ADC_DATA_ALIGN(ALIGN)
#define | IS_ADC_SCAN_MODE(SCAN_MODE)
#define | IS_ADC_EXTTRIG_EDGE(EDGE)
#define | IS_ADC_CHANNEL(CHANNEL)
#define | IS_ADC_SAMPLE_TIME(TIME)
#define | IS_ADC_REGULAR_RANK(CHANNEL)
#define | IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)
#define | IS_ADC_CONVERSION_GROUP(CONVERSION)
#define | IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)

Define Documentation

#define ADC_CLEAR_ERRORCODE ( __HANDLE__ ) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

Clear ADC error code (set it to error code: "no error")

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 623 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_DeInit(), HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_CONVCYCLES_MAX_RANGE ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&                     \
       (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ?                     \
                                                                                \
          (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ?               \
               ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5)   \
          :                                                                                                      \
          ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) ||               \
            ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET)  &&               \
             (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ?               \
               ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
     )

Get the maximum ADC conversion cycles on all channels.

Returns the selected sampling time + conversion time (12.5 ADC clock cycles) Approximation of sampling time within 4 ranges, returns the highest value: below 7.5 cycles {1.5 cycle; 7.5 cycles}, between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles} between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles} equal to 239.5 cycles Unit: ADC clock cycles

Parameters:
__HANDLE__,: ADC handle
Return values:
ADC conversion cycles on all channels

Definition at line 740 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_PollForConversion(), and HAL_ADCEx_InjectedPollForConversion().

#define ADC_CR1_DISCONTINUOUS_NUM ( _NBR_DISCONTINUOUS_CONV_ ) (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)

Configures the number of discontinuous conversions for the regular group channels.

Parameters:
_NBR_DISCONTINUOUS_CONV_,: Number of discontinuous conversions.
Return values:
None

Definition at line 713 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_CR1_SCAN_SET ( _SCAN_MODE_ )
Value:
(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)           \
   )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE)                                   \
  )

Enable ADC scan mode to convert multiple ranks with sequencer.

Parameters:
_SCAN_MODE_,: Scan conversion mode.
Return values:
None

Definition at line 723 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_CR2_CONTINUOUS ( _CONTINUOUS_MODE_ ) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)

Enable ADC continuous conversion mode.

Parameters:
_CONTINUOUS_MODE_,: Continuous mode.
Return values:
None

Definition at line 705 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_IS_ENABLE ( __HANDLE__ )
Value:
((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON )           \
   ) ? SET : RESET)

Verification of ADC state: enabled or disabled.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (ADC enabled) or RESET (ADC disabled)

Definition at line 587 of file stm32f1xx_hal_adc.h.

Referenced by ADC_ConversionStop_Disable(), ADC_Enable(), HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_MultiModeConfigChannel().

#define ADC_IS_SOFTWARE_START_INJECTED ( __HANDLE__ ) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)

Test if conversion trigger of injected group is software start or external trigger.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 606 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_IRQHandler(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define ADC_IS_SOFTWARE_START_REGULAR ( __HANDLE__ ) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)

Test if conversion trigger of regular group is software start or external trigger.

Parameters:
__HANDLE__,: ADC handle
Return values:
SET (software start) or RESET (external trigger)

Definition at line 597 of file stm32f1xx_hal_adc.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedPollForConversion(), and HAL_ADCEx_MultiModeStart_DMA().

#define ADC_JSQR_JL_SHIFT ( _JSQR_JL_ ) (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)

Set the injected sequence length.

Parameters:
_JSQR_JL_,: Sequence length.
Return values:
None

Definition at line 684 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_JSQR_RK_JL | ( | _CHANNELNB_,
 |  | _RANKNB_,
 |  | _JSQR_JL_
 | ) | ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))

Set the selected injected channel rank Note: on STM32F1 devices, channel rank position in JSQR register is depending on total number of ranks selected into injected sequencer (ranks sequence starting from 4-JL)

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
_JSQR_JL_,: Sequence length.
Return values:
None

Definition at line 697 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_SMPR1 | ( | _SAMPLETIME_,
 |  | _CHANNELNB_
 | ) | ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))

Set the ADC's sample time for channel numbers between 10 and 18.

Parameters:
_SAMPLETIME_,: Sample time parameter.
_CHANNELNB_,: Channel number.
Return values:
None

Definition at line 640 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SMPR2 | ( | _SAMPLETIME_,
 |  | _CHANNELNB_
 | ) | ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))

Set the ADC's sample time for channel numbers between 0 and 9.

Parameters:
_SAMPLETIME_,: Sample time parameter.
_CHANNELNB_,: Channel number.
Return values:
None

Definition at line 649 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define ADC_SQR1_L_SHIFT ( _NbrOfConversion_ ) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)

Set ADC number of conversions into regular channel sequence length.

Parameters:
_NbrOfConversion_,: Regular channel sequence length
Return values:
None

Definition at line 631 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define ADC_SQR1_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))

Set the selected regular channel rank for rank between 13 and 16.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
Return values:
None

Definition at line 676 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR2_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))

Set the selected regular channel rank for rank between 7 and 12.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
Return values:
None

Definition at line 667 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_SQR3_RK | ( | _CHANNELNB_,
 |  | _RANKNB_
 | ) | ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))

Set the selected regular channel rank for rank between 1 and 6.

Parameters:
_CHANNELNB_,: Channel number.
_RANKNB_,: Rank number.
Return values:
None

Definition at line 658 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define ADC_STATE_CLR_SET MODIFY_REG

Simultaneously clears and sets specific bits of the handle State.

Note:
: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), the first parameter is the ADC handle State, the second parameter is the bit field to clear, the third and last parameter is the bit field to set.
Return values:
None

Definition at line 616 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define IS_ADC_ANALOG_WATCHDOG_MODE ( WATCHDOG )
Value:
(((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )

Definition at line 809 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig().

#define IS_ADC_CHANNEL ( CHANNEL )
Value:
(((CHANNEL) == ADC_CHANNEL_0)           || \
                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
                                 ((CHANNEL) == ADC_CHANNEL_16)          || \
                                 ((CHANNEL) == ADC_CHANNEL_17)            )

Definition at line 764 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_CONVERSION_GROUP ( CONVERSION )
Value:
(((CONVERSION) == ADC_REGULAR_GROUP)         || \
                                             ((CONVERSION) == ADC_INJECTED_GROUP)        || \
                                             ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)  )

Definition at line 817 of file stm32f1xx_hal_adc.h.

#define IS_ADC_DATA_ALIGN ( ALIGN )
Value:
(((ALIGN) == ADC_DATAALIGN_RIGHT) || \
                                  ((ALIGN) == ADC_DATAALIGN_LEFT)    )

Definition at line 755 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EVENT_TYPE ( EVENT ) ((EVENT) == ADC_AWD_EVENT)

Definition at line 821 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_PollForEvent().

#define IS_ADC_EXTTRIG_EDGE ( EDGE )
Value:
(((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)  || \
                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  )

Definition at line 761 of file stm32f1xx_hal_adc.h.

#define IS_ADC_REGULAR_RANK ( CHANNEL )
Value:
(((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_10) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_11) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_12) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_13) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_14) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_15) || \
                                      ((CHANNEL) == ADC_REGULAR_RANK_16)   )

Definition at line 792 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel().

#define IS_ADC_SAMPLE_TIME ( TIME )
Value:
(((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
                                  ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
                                  ((TIME) == ADC_SAMPLETIME_13CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_28CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_41CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_55CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_71CYCLES_5)  || \
                                  ((TIME) == ADC_SAMPLETIME_239CYCLES_5)   )

Definition at line 783 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_ConfigChannel(), and HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_SCAN_MODE ( SCAN_MODE )
Value:
(((SCAN_MODE) == ADC_SCAN_DISABLE) || \
                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)    )

Definition at line 758 of file stm32f1xx_hal_adc.h.

Referenced by HAL_ADC_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Extended Internal HAL driver trigger selection for regular group

Defines
ADC Extended Internal HAL driver trigger selection for regular group
ADCEx Private Constants

Defines

#define | ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U
#define | ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0))
#define | ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 ))
#define | ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
#define | ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
#define | ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Define Documentation

#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))

Definition at line 331 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Definition at line 332 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))

Definition at line 313 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U

Definition at line 308 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0))

Definition at line 309 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))

Definition at line 310 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 ))

Definition at line 311 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))

Definition at line 312 of file stm32f1xx_hal_adc_ex.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Extended Internal HAL driver trigger selection for injected group

Defines
ADC Extended Internal HAL driver trigger selection for injected group
ADCEx Private Constants

Defines

#define | ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
#define | ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 ))
#define | ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
#define | ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
#define | ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0))
#define | ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Define Documentation

#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0))

Definition at line 367 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U

Definition at line 366 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Definition at line 368 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))

Definition at line 349 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))

Definition at line 346 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))

Definition at line 345 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 ))

Definition at line 347 of file stm32f1xx_hal_adc_ex.h.

#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))

Definition at line 348 of file stm32f1xx_hal_adc_ex.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADCEx Private Constants

Modules | Defines
ADCEx Private Constants
ADCEx

Modules

ADC Extended Internal HAL driver trigger selection for regular group
ADC Extended Internal HAL driver trigger selection for injected group

Defines

#define | ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U
#define | ADC_CALIBRATION_TIMEOUT 10U
#define | ADC_TEMPSENSOR_DELAY_US 10U

Define Documentation

#define ADC_CALIBRATION_TIMEOUT 10U

Definition at line 88 of file stm32f1xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start().

#define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U

Definition at line 80 of file stm32f1xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_Calibration_Start().

#define ADC_TEMPSENSOR_DELAY_US 10U

Definition at line 93 of file stm32f1xx_hal_adc_ex.c.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Extended Extended IO operation functions

Functions
Extended Extended IO operation functions
ADCEx Exported Functions

Extended Extended Input and Output operation functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Returns the last ADC Master&Slave regular conversions results data in the selected multi mode.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.

Detailed Description

Extended Extended Input and Output operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Start conversion of injected group.
      (+) Stop conversion of injected group.
      (+) Poll for conversion complete on injected group.
      (+) Get result of injected channel conversion.
      (+) Start conversion of injected group and enable interruptions.
      (+) Stop conversion of injected group and disable interruptions.

      (+) Start multimode and enable DMA transfer.
      (+) Stop multimode and disable ADC DMA transfer.
      (+) Get result of multimode conversion.

      (+) Perform the ADC self-calibration for single or differential ending.
      (+) Get calibration factors for single or differential ending.
      (+) Set calibration factors for single or differential ending.

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_Calibration_Start ( ADC_HandleTypeDef * hadc )

Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).

During calibration process, ADC is enabled. ADC is let enabled at the completion of this function.

Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 144 of file stm32f1xx_hal_adc_ex.c.

References ADC_CALIBRATION_TIMEOUT, ADC_ConversionStop_Disable(), ADC_Enable(), ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_GetTick(), HAL_RCCEx_GetPeriphCLKFreq(), ADC_HandleTypeDef::Instance, RCC_PERIPHCLK_ADC, and ADC_HandleTypeDef::State.

void HAL_ADCEx_InjectedConvCpltCallback ( ADC_HandleTypeDef * hadc )

Injected conversion complete callback in non blocking mode.

Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 996 of file stm32f1xx_hal_adc_ex.c.

Referenced by HAL_ADC_IRQHandler().

uint32_t HAL_ADCEx_InjectedGetValue | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | InjectedRank
 | ) |  |

Get ADC injected group conversion result.

Note:
Reading register JDRx automatically clears ADC flag JEOC (ADC group injected end of unitary conversion).
This function does not clear ADC flag JEOS (ADC group injected end of sequence conversion) Occurrence of flag JEOS rising:
  • If sequencer is composed of 1 rank, flag JEOS is equivalent to flag JEOC.
  • If sequencer is composed of several ranks, during the scan sequence flag JEOC only is raised, at the end of the scan sequence both flags JEOC and EOS are raised. Flag JEOS must not be cleared by this function because it would not be compliant with low power features (feature low power auto-wait, not available on all STM32 families). To clear this flag, either use function: in programming model IT: HAL_ADC_IRQHandler(), in programming model polling: HAL_ADCEx_InjectedPollForConversion() or __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
Parameters:
hadc,: ADC handle
InjectedRank,: the converted ADC injected rank. This parameter can be one of the following values:
  • ADC_INJECTED_RANK_1: Injected Channel1 selected
  • ADC_INJECTED_RANK_2: Injected Channel2 selected
  • ADC_INJECTED_RANK_3: Injected Channel3 selected
  • ADC_INJECTED_RANK_4: Injected Channel4 selected
Return values:
ADC group injected conversion data

Definition at line 927 of file stm32f1xx_hal_adc_ex.c.

References ADC_INJECTED_RANK_1, ADC_INJECTED_RANK_2, ADC_INJECTED_RANK_3, ADC_INJECTED_RANK_4, assert_param, ADC_HandleTypeDef::Instance, and IS_ADC_INJECTED_RANK.

HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t | Timeout
 | ) |  |

Wait for injected group conversion to be completed.

Parameters:
hadc,: ADC handle
Timeout,: Timeout value in millisecond.
Return values:
HAL status

Definition at line 402 of file stm32f1xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CONVCYCLES_MAX_RANGE, ADC_FLAG_EOC, ADC_FLAG_JEOC, ADC_FLAG_JSTRT, ADC_IS_SOFTWARE_START_INJECTED, ADC_IS_SOFTWARE_START_REGULAR, assert_param, ADC_InitTypeDef::ContinuousConvMode, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_TIMEOUT, HAL_GetTick(), HAL_RCCEx_GetPeriphCLKFreq(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, RCC_PERIPHCLK_ADC, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart ( ADC_HandleTypeDef * hadc )

Enables ADC, starts conversion of injected group.

Interruptions enabled in this function: None.

Parameters:
hadc,: ADC handle
Return values:
HAL status

Definition at line 250 of file stm32f1xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_JEOC, ADC_IS_SOFTWARE_START_INJECTED, ADC_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT ( ADC_HandleTypeDef * hadc )

Enables ADC, starts conversion of injected group with interruption.

  • JEOC (end of conversion of injected group) Each of these interruptions has its dedicated callback function.
    Parameters:
    hadc,: ADC handle
    Return values:
    HAL status.

Definition at line 520 of file stm32f1xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, __HAL_ADC_ENABLE_IT, ADC_CLEAR_ERRORCODE, ADC_Enable(), ADC_FLAG_JEOC, ADC_IS_SOFTWARE_START_INJECTED, ADC_IT_JEOC, ADC_NONMULTIMODE_OR_MULTIMODEMASTER, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
In case of auto-injection mode, HAL_ADC_Stop must be used.
Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 349 of file stm32f1xx_hal_adc_ex.c.

References ADC_ConversionStop_Disable(), ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT ( ADC_HandleTypeDef * hadc )

Stop conversion of injected channels, disable interruption of end-of-conversion.

Disable ADC peripheral if no regular conversion is on going.

Note:
If ADC must be disabled and if conversion is on going on regular group, function HAL_ADC_Stop must be used to stop both injected and regular groups, and disable the ADC.
If injected group mode auto-injection is enabled, function HAL_ADC_Stop must be used.
Parameters:
hadc,: ADC handle
Return values:
None

Definition at line 619 of file stm32f1xx_hal_adc_ex.c.

References __HAL_ADC_DISABLE_IT, ADC_ConversionStop_Disable(), ADC_IT_JEOC, ADC_STATE_CLR_SET, assert_param, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

uint32_t HAL_ADCEx_MultiModeGetValue ( ADC_HandleTypeDef * hadc )

Returns the last ADC Master&Slave regular conversions results data in the selected multi mode.

Parameters:
hadc,: ADC handle of ADC master (handle of ADC slave must not be used)
Return values:
The converted data value.

Definition at line 964 of file stm32f1xx_hal_adc_ex.c.

References assert_param, and ADC_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA | ( | ADC_HandleTypeDef * | hadc,
 |  | uint32_t * | pData,
 |  | uint32_t | Length
 | ) |  |

Enables ADC, starts conversion of regular group and transfers result through DMA.

Multimode must have been previously configured using HAL_ADCEx_MultiModeConfigChannel() function. Interruptions enabled in this function:

  • DMA transfer complete
  • DMA half transfer Each of these interruptions has its dedicated callback function.
    Note:
    : On STM32F1 devices, ADC slave regular group must be configured with conversion trigger ADC_SOFTWARE_START.
    : ADC slave can be enabled preliminarily using single-mode HAL_ADC_Start() function.
    Parameters:
    hadc,: ADC handle of ADC master (handle of ADC slave must not be used)
    pData,: The destination Buffer address.
    Length,: The length of data to be transferred from ADC peripheral to memory.
    Return values:
    None

Definition at line 688 of file stm32f1xx_hal_adc_ex.c.

References __HAL_ADC_CLEAR_FLAG, ADC_CLEAR_ERRORCODE, ADC_DMAConvCplt(), ADC_DMAError(), ADC_DMAHalfConvCplt(), ADC_Enable(), ADC_FLAG_EOC, ADC_IS_SOFTWARE_START_REGULAR, ADC_MULTI_SLAVE, ADC_STATE_CLR_SET, assert_param, ADC_InitTypeDef::ContinuousConvMode, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_CONFIG, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_MULTIMODE_SLAVE, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_REG_EOC, HAL_DMA_Start_IT(), ADC_HandleTypeDef::Init, ADC_HandleTypeDef::Instance, ADC_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA ( ADC_HandleTypeDef * hadc )

Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.

Note:
Multimode is kept enabled after this function. To disable multimode (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
In case of DMA configured in circular mode, function HAL_ADC_Stop_DMA must be called after this function with handle of ADC slave, to properly disable the DMA channel.
Parameters:
hadc,: ADC handle of ADC master (handle of ADC slave must not be used)
Return values:
None

Definition at line 815 of file stm32f1xx_hal_adc_ex.c.

References ADC_ConversionStop_Disable(), ADC_MULTI_SLAVE, ADC_STATE_CLR_SET, assert_param, ADC_HandleTypeDef::DMA_Handle, HAL_ADC_STATE_ERROR_DMA, HAL_ADC_STATE_ERROR_INTERNAL, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY, HAL_ADC_STATE_REG_BUSY, HAL_DMA_Abort(), ADC_HandleTypeDef::Instance, and ADC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
ADCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures the ADC injected group and the selected channel to be linked to the injected group.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
             ##### Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure channels on injected group
      (+) Configure multimode

Function Documentation

HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_InjectionConfTypeDef * | sConfigInjected
 | ) |  |

Configures the ADC injected group and the selected channel to be linked to the injected group.

Note:
Possibility to update parameters on the fly: This function initializes injected group, following calls to this function can be used to reconfigure some parameters of structure "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. The setting of these parameters is conditioned to ADC state: this function must be called when ADC is not under conversion.
Parameters:
hadc,: ADC handle
sConfigInjected,: Structure of ADC injected group and ADC channel for injected group.
Return values:
None

Definition at line 1038 of file stm32f1xx_hal_adc_ex.c.

References ADC_CFGR_JEXTSEL, ADC_CHANNEL_10, ADC_CHANNEL_TEMPSENSOR, ADC_CHANNEL_VREFINT, ADC_INJECTED_RANK_1, ADC_INJECTED_SOFTWARE_START, ADC_IS_ENABLE, ADC_JSQR_JL_SHIFT, ADC_JSQR_RK_JL, ADC_SCAN_DISABLE, ADC_SMPR1, ADC_SMPR2, ADC_TEMPSENSOR_DELAY_US, assert_param, ADC_InjectionConfTypeDef::AutoInjectedConv, ADC_InjectionConfTypeDef::ExternalTrigInjecConv, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Init, ADC_InjectionConfTypeDef::InjectedChannel, ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode, ADC_InjectionConfTypeDef::InjectedNbrOfConversion, ADC_InjectionConfTypeDef::InjectedOffset, ADC_InjectionConfTypeDef::InjectedRank, ADC_InjectionConfTypeDef::InjectedSamplingTime, ADC_HandleTypeDef::Instance, IS_ADC_CHANNEL, IS_ADC_EXTTRIGINJEC, IS_ADC_INJECTED_NB_CONV, IS_ADC_INJECTED_RANK, IS_ADC_RANGE, IS_ADC_SAMPLE_TIME, ADC_InitTypeDef::ScanConvMode, and ADC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel | ( | ADC_HandleTypeDef * | hadc,
 |  | ADC_MultiModeTypeDef * | multimode
 | ) |  |

Enable ADC multimode and configure multimode parameters.

Note:
Possibility to update parameters on the fly: This function initializes multimode parameters, following calls to this function can be used to reconfigure some parameters of structure "ADC_MultiModeTypeDef" on the fly, without reseting the ADCs (both ADCs of the common group). The setting of these parameters is conditioned to ADC state. For parameters constraints, see comments of structure "ADC_MultiModeTypeDef".
To change back configuration from multimode to single mode, ADC must be reset (using function HAL_ADC_Init() ).
Parameters:
hadc,: ADC handle
multimode,: Structure of ADC multimode configuration
Return values:
HAL status

Definition at line 1299 of file stm32f1xx_hal_adc_ex.c.

References ADC_IS_ENABLE, ADC_MULTI_SLAVE, assert_param, HAL_ADC_STATE_ERROR_CONFIG, ADC_HandleTypeDef::Instance, IS_ADC_MODE, ADC_MultiModeTypeDef::Mode, and ADC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC_InjectionConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_InjectionConfTypeDef Struct Reference
ADCEx Exported Types

ADC Configuration injected Channel structure definition. More...

#include <stm32f1xx_hal_adc_ex.h>

Data Fields

uint32_t | InjectedChannel
uint32_t | InjectedRank
uint32_t | InjectedSamplingTime
uint32_t | InjectedOffset
uint32_t | InjectedNbrOfConversion
uint32_t | InjectedDiscontinuousConvMode
uint32_t | AutoInjectedConv
uint32_t | ExternalTrigInjecConv

Detailed Description

ADC Configuration injected Channel structure definition.

Note:
Parameters of this structure are shared within 2 scopes:
  • Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
  • Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. ADC state can be either:
  • For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
  • For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.

Definition at line 73 of file stm32f1xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_InjectionConfTypeDef::AutoInjectedConv

Enables or disables the selected ADC automatic injected group conversion after regular one This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. To maintain JAUTO always enabled, DMA must be configured in circular mode. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 110 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::ExternalTrigInjecConv

Selects the external event used to trigger the conversion start of injected group. If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. If set to external trigger source, triggering is on event rising edge. This parameter can be a value of ADCEx External trigger selection for injected group Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 118 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedChannel

Selection of ADC channel to configure This parameter can be a value of ADC channels Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor) Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger. It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel. Refer to errata sheet of these devices for more details.

Definition at line 75 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedDiscontinuousConvMode

Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 103 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedNbrOfConversion

Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set.

Definition at line 98 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedOffset

Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.

Definition at line 94 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedRank

Rank in the injected group sequencer This parameter must be a value of ADCEx rank into injected group Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted)

Definition at line 82 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

uint32_t ADC_InjectionConfTypeDef::InjectedSamplingTime

Sampling time value to be set for the selected channel. Unit: ADC clock cycles Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits). This parameter can be a value of ADC sampling times Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. Note: In case of usage of internal measurement channels (VrefInt/TempSensor), sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min).

Definition at line 85 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_adc_ex.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC_MultiModeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
ADC_MultiModeTypeDef Struct Reference
ADCEx Exported Types

Structure definition of ADC multimode. More...

#include <stm32f1xx_hal_adc_ex.h>

Data Fields

uint32_t Mode

Detailed Description

Structure definition of ADC multimode.

Note:
The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). State of ADCs of the common group must be: disabled.

Definition at line 134 of file stm32f1xx_hal_adc_ex.h.

Field Documentation

uint32_t ADC_MultiModeTypeDef::Mode

Configures the ADC to operate in independent or multi mode. This parameter can be a value of ADC Extended Dual ADC Mode Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2. Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode. Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters). The equivalences are:

  • Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
  • Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode).

Definition at line 136 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_adc_ex.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADCEx rank into injected group

Defines
ADCEx rank into injected group
ADCEx Exported Constants

Defines

#define | ADC_INJECTED_RANK_1 0x00000001U
#define | ADC_INJECTED_RANK_2 0x00000002U
#define | ADC_INJECTED_RANK_3 0x00000003U
#define | ADC_INJECTED_RANK_4 0x00000004U

Define Documentation

#define ADC_INJECTED_RANK_1 0x00000001U

Definition at line 164 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_2 0x00000002U

Definition at line 165 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_3 0x00000003U

Definition at line 166 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

#define ADC_INJECTED_RANK_4 0x00000004U

Definition at line 167 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedGetValue().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADCEx external trigger enable for injected group

Defines
ADCEx external trigger enable for injected group
ADCEx Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U

Definition at line 175 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)

Definition at line 176 of file stm32f1xx_hal_adc_ex.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC External trigger selection for regular group

Defines
ADC External trigger selection for regular group
ADCEx Exported Constants

Defines

#define | ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
#define | ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
#define | ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
#define | ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
#define | ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
#define | ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
#define | ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
#define | ADC_SOFTWARE_START ADC1_2_3_SWSTART

Define Documentation

#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11

Definition at line 193 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1

< List of external triggers with generic trigger name, independently of

< External triggers of regular group for ADC1&ADC2 only

Definition at line 188 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2

Definition at line 189 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3

< External triggers of regular group for all ADC instances

Definition at line 205 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2

Definition at line 190 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO

Definition at line 191 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4

Definition at line 192 of file stm32f1xx_hal_adc_ex.h.

#define ADC_SOFTWARE_START ADC1_2_3_SWSTART

Definition at line 221 of file stm32f1xx_hal_adc_ex.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADCEx External trigger selection for injected group

Defines
ADCEx External trigger selection for injected group
ADCEx Exported Constants

Defines

#define | ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
#define | ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
#define | ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
#define | ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
#define | ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
#define | ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
#define | ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART

Define Documentation

#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15

Definition at line 237 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4

< External triggers of injected group for all ADC instances

Definition at line 248 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO

Definition at line 249 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1

Definition at line 234 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO

< List of external triggers with generic trigger name, independently of

< External triggers of injected group for ADC1&ADC2 only

Definition at line 233 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4

Definition at line 235 of file stm32f1xx_hal_adc_ex.h.

#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO

Definition at line 236 of file stm32f1xx_hal_adc_ex.h.

#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART

Definition at line 265 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Extended Dual ADC Mode

Defines
ADC Extended Dual ADC Mode
ADCEx Exported Constants

Defines

#define | ADC_MODE_INDEPENDENT 0x00000000U
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0))
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 ))
#define | ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0))
#define | ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 ))
#define | ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0))
#define | ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ))
#define | ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0))
#define | ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 ))
#define | ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0))

Define Documentation

#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0))

ADC dual mode enabled: Alternate trigger mode, on group injected

Definition at line 283 of file stm32f1xx_hal_adc_ex.h.

#define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0))

ADC dual mode enabled: Injected simultaneous mode, on group injected

Definition at line 279 of file stm32f1xx_hal_adc_ex.h.

#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0))

ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices))

Definition at line 277 of file stm32f1xx_hal_adc_ex.h.

#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 ))

ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices))

Definition at line 278 of file stm32f1xx_hal_adc_ex.h.

#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0))

ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices))

Definition at line 281 of file stm32f1xx_hal_adc_ex.h.

#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 ))

ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices))

Definition at line 282 of file stm32f1xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ))

ADC dual mode enabled: Regular simultaneous mode, on group regular

Definition at line 280 of file stm32f1xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 ))

ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected

Definition at line 276 of file stm32f1xx_hal_adc_ex.h.

#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0))

ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected

Definition at line 275 of file stm32f1xx_hal_adc_ex.h.

#define ADC_MODE_INDEPENDENT 0x00000000U

ADC dual mode disabled (ADC independent mode)

Definition at line 274 of file stm32f1xx_hal_adc_ex.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADCEx injected nb conv verification

Defines
ADCEx injected nb conv verification
ADCEx Private Macro

Defines

#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))

Define Documentation

#define IS_ADC_INJECTED_NB_CONV ( LENGTH ) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))

Definition at line 534 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADCEx Private Macro

Modules | Defines
ADCEx Private Macro
ADCEx

Modules

ADCEx injected nb conv verification

Defines

#define | ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) (__EXT_TRIG_CONV__)
For devices with 3 ADCs: Defines the external trigger source for regular group according to ADC into common group ADC1&ADC2 or ADC3 (some triggers with same source have different value to be programmed into ADC EXTSEL bits of CR2 register).
#define | ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) (__EXT_TRIG_INJECTCONV__)
For devices with 3 ADCs: Defines the external trigger source for injected group according to ADC into common group ADC1&ADC2 or ADC3 (some triggers with same source have different value to be programmed into ADC JEXTSEL bits of CR2 register).
#define | ADC_MULTIMODE_IS_ENABLE(__HANDLE__)
Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
#define | ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
#define | ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)
Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
#define | ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
Set handle of the other ADC sharing the common multimode settings.
#define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ((__HANDLE_SLAVE__)->Instance = ADC2)
Set handle of the ADC slave associated to the ADC master On STM32F1 devices, ADC slave is always ADC2 (this can be different on other STM32 devices)
#define | IS_ADC_INJECTED_RANK(CHANNEL)
#define | IS_ADC_EXTTRIGINJEC_EDGE(EDGE)
#define | IS_ADC_EXTTRIG(REGTRIG)
#define | IS_ADC_EXTTRIGINJEC(REGTRIG)
#define | IS_ADC_MODE(MODE)

Define Documentation

#define ADC_CFGR_EXTSEL | ( | __HANDLE__,
 |  | __EXT_TRIG_CONV__
 | ) | (__EXT_TRIG_CONV__)

For devices with 3 ADCs: Defines the external trigger source for regular group according to ADC into common group ADC1&ADC2 or ADC3 (some triggers with same source have different value to be programmed into ADC EXTSEL bits of CR2 register).

For devices with 2 ADCs or less: this macro makes no change.

Parameters:
__HANDLE__,: ADC handle
__EXT_TRIG_CONV__,: External trigger selected for regular group.
Return values:
External trigger to be programmed into EXTSEL bits of CR2 register

Definition at line 413 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define ADC_CFGR_JEXTSEL | ( | __HANDLE__,
 |  | __EXT_TRIG_INJECTCONV__
 | ) | (__EXT_TRIG_INJECTCONV__)

For devices with 3 ADCs: Defines the external trigger source for injected group according to ADC into common group ADC1&ADC2 or ADC3 (some triggers with same source have different value to be programmed into ADC JEXTSEL bits of CR2 register).

For devices with 2 ADCs or less: this macro makes no change.

Parameters:
__HANDLE__,: ADC handle
__EXT_TRIG_INJECTCONV__,: External trigger selected for injected group.
Return values:
External trigger to be programmed into JEXTSEL bits of CR2 register

Definition at line 441 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define ADC_COMMON_ADC_OTHER | ( | __HANDLE__,
 |  | __HANDLE_OTHER_ADC__
 | ) | ((__HANDLE_OTHER_ADC__)->Instance = ADC2)

Set handle of the other ADC sharing the common multimode settings.

Parameters:
__HANDLE__,: ADC handle
__HANDLE_OTHER_ADC__,: other ADC handle
Return values:
None

Definition at line 507 of file stm32f1xx_hal_adc_ex.h.

#define ADC_MULTI_SLAVE | ( | __HANDLE_MASTER__,
 |  | __HANDLE_SLAVE__
 | ) | ((__HANDLE_SLAVE__)->Instance = ADC2)

Set handle of the ADC slave associated to the ADC master On STM32F1 devices, ADC slave is always ADC2 (this can be different on other STM32 devices)

Parameters:
__HANDLE_MASTER__,: ADC master handle
__HANDLE_SLAVE__,: ADC slave handle
Return values:
None

Definition at line 518 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeStart_DMA(), and HAL_ADCEx_MultiModeStop_DMA().

#define ADC_MULTIMODE_AUTO_INJECTED ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)  \
   )?                                                                          \
    (ADC1->CR1 & ADC_CR1_JAUTO)                                                \
    :                                                                          \
    (RESET)                                                                    \
  )

Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 488 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), and HAL_ADC_Start_IT().

#define ADC_MULTIMODE_IS_ENABLE ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)   \
  )?                                                                           \
   (ADC1->CR1 & ADC_CR1_DUALMOD)                                               \
   :                                                                           \
   (RESET)                                                                     \
 )

Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)

Parameters:
__HANDLE__,: ADC handle
Return values:
Multimode state: RESET if multimode is disabled, other value if multimode is enabled

Definition at line 452 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADC_Start_DMA().

#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER ( __HANDLE__ )
Value:
(( (((__HANDLE__)->Instance) == ADC2)                                        \
   )?                                                                          \
    ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET)                                   \
    :                                                                          \
    (!RESET)                                                                   \
  )

Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)

Parameters:
__HANDLE__,: ADC handle
Return values:
None

Definition at line 470 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADCEx_InjectedStart(), and HAL_ADCEx_InjectedStart_IT().

#define IS_ADC_EXTTRIG ( REGTRIG )
Value:
(((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
                                 ((REGTRIG) == ADC_SOFTWARE_START))

Definition at line 540 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADC_Init().

#define IS_ADC_EXTTRIGINJEC ( REGTRIG )
Value:
(((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
                                      ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))

Definition at line 585 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel().

#define IS_ADC_EXTTRIGINJEC_EDGE ( EDGE )
Value:
(((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)  || \
                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))

Definition at line 528 of file stm32f1xx_hal_adc_ex.h.

#define IS_ADC_INJECTED_RANK ( CHANNEL )
Value:
(((CHANNEL) == ADC_INJECTED_RANK_1) || \
                                       ((CHANNEL) == ADC_INJECTED_RANK_2) || \
                                       ((CHANNEL) == ADC_INJECTED_RANK_3) || \
                                       ((CHANNEL) == ADC_INJECTED_RANK_4))

Definition at line 523 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_InjectedConfigChannel(), and HAL_ADCEx_InjectedGetValue().

#define IS_ADC_MODE ( MODE )
Value:
(((MODE) == ADC_MODE_INDEPENDENT)                || \
                           ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)  || \
                           ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)    || \
                           ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
                           ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
                           ((MODE) == ADC_DUALMODE_INJECSIMULT)            || \
                           ((MODE) == ADC_DUALMODE_REGSIMULT)              || \
                           ((MODE) == ADC_DUALMODE_INTERLFAST)             || \
                           ((MODE) == ADC_DUALMODE_INTERLSLOW)             || \
                           ((MODE) == ADC_DUALMODE_ALTERTRIG) )

Definition at line 633 of file stm32f1xx_hal_adc_ex.h.

Referenced by HAL_ADCEx_MultiModeConfigChannel().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Private Constants

Defines
CAN Private Constants
CAN

Defines

#define | CAN_TIMEOUT_VALUE 10U
#define | TSR_REGISTER_INDEX 0x5U
#define | RF0R_REGISTER_INDEX 0x2U
#define | RF1R_REGISTER_INDEX 0x4U
#define | MSR_REGISTER_INDEX 0x1U
#define | ESR_REGISTER_INDEX 0x3U
#define | CAN_TSR_RQCP0_BIT_POSITION 0x00000000U
#define | CAN_TSR_RQCP1_BIT_POSITION 0x00000008U
#define | CAN_TSR_RQCP2_BIT_POSITION 0x00000010U
#define | CAN_TSR_TXOK0_BIT_POSITION 0x00000001U
#define | CAN_TSR_TXOK1_BIT_POSITION 0x00000009U
#define | CAN_TSR_TXOK2_BIT_POSITION 0x00000011U
#define | CAN_TSR_TME0_BIT_POSITION 0x0000001AU
#define | CAN_TSR_TME1_BIT_POSITION 0x0000001BU
#define | CAN_TSR_TME2_BIT_POSITION 0x0000001CU
#define | CAN_RF0R_FF0_BIT_POSITION 0x00000003U
#define | CAN_RF0R_FOV0_BIT_POSITION 0x00000004U
#define | CAN_RF1R_FF1_BIT_POSITION 0x00000003U
#define | CAN_RF1R_FOV1_BIT_POSITION 0x00000004U
#define | CAN_MSR_WKU_BIT_POSITION 0x00000003U
#define | CAN_MSR_SLAK_BIT_POSITION 0x00000001U
#define | CAN_MSR_SLAKI_BIT_POSITION 0x00000004U
#define | CAN_ESR_EWG_BIT_POSITION 0x00000000U
#define | CAN_ESR_EPV_BIT_POSITION 0x00000001U
#define | CAN_ESR_BOF_BIT_POSITION 0x00000002U
#define | CAN_FLAG_MASK 0x000000FFU
#define | CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define | CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define | CAN_TXMAILBOX_2 ((uint8_t)0x02)

Define Documentation

#define CAN_ESR_BOF_BIT_POSITION 0x00000002U

Definition at line 470 of file stm32f1xx_hal_can.h.

#define CAN_ESR_EPV_BIT_POSITION 0x00000001U

Definition at line 469 of file stm32f1xx_hal_can.h.

#define CAN_ESR_EWG_BIT_POSITION 0x00000000U

Definition at line 468 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_MASK 0x000000FFU

Definition at line 473 of file stm32f1xx_hal_can.h.

#define CAN_MSR_SLAK_BIT_POSITION 0x00000001U

Definition at line 464 of file stm32f1xx_hal_can.h.

#define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U

Definition at line 465 of file stm32f1xx_hal_can.h.

#define CAN_MSR_WKU_BIT_POSITION 0x00000003U

Definition at line 463 of file stm32f1xx_hal_can.h.

#define CAN_RF0R_FF0_BIT_POSITION 0x00000003U

Definition at line 456 of file stm32f1xx_hal_can.h.

#define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U

Definition at line 457 of file stm32f1xx_hal_can.h.

#define CAN_RF1R_FF1_BIT_POSITION 0x00000003U

Definition at line 459 of file stm32f1xx_hal_can.h.

#define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U

Definition at line 460 of file stm32f1xx_hal_can.h.

#define CAN_TIMEOUT_VALUE 10U

Definition at line 130 of file stm32f1xx_hal_can.c.

Referenced by HAL_CAN_Init(), HAL_CAN_Sleep(), and HAL_CAN_WakeUp().

#define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U

Definition at line 445 of file stm32f1xx_hal_can.h.

#define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U

Definition at line 446 of file stm32f1xx_hal_can.h.

#define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U

Definition at line 447 of file stm32f1xx_hal_can.h.

#define CAN_TSR_TME0_BIT_POSITION 0x0000001AU

Definition at line 451 of file stm32f1xx_hal_can.h.

#define CAN_TSR_TME1_BIT_POSITION 0x0000001BU

Definition at line 452 of file stm32f1xx_hal_can.h.

#define CAN_TSR_TME2_BIT_POSITION 0x0000001CU

Definition at line 453 of file stm32f1xx_hal_can.h.

#define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U

Definition at line 448 of file stm32f1xx_hal_can.h.

#define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U

Definition at line 449 of file stm32f1xx_hal_can.h.

#define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U

Definition at line 450 of file stm32f1xx_hal_can.h.

#define CAN_TXMAILBOX_0 ((uint8_t)0x00)

Definition at line 476 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define CAN_TXMAILBOX_1 ((uint8_t)0x01)

Definition at line 477 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define CAN_TXMAILBOX_2 ((uint8_t)0x02)

Definition at line 478 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define ESR_REGISTER_INDEX 0x3U

Definition at line 441 of file stm32f1xx_hal_can.h.

#define MSR_REGISTER_INDEX 0x1U

Definition at line 440 of file stm32f1xx_hal_can.h.

#define RF0R_REGISTER_INDEX 0x2U

Definition at line 438 of file stm32f1xx_hal_can.h.

#define RF1R_REGISTER_INDEX 0x4U

Definition at line 439 of file stm32f1xx_hal_can.h.

#define TSR_REGISTER_INDEX 0x5U

Definition at line 437 of file stm32f1xx_hal_can.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Private Functions

Functions
CAN Private Functions
CAN

Functions

static HAL_StatusTypeDef | CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
static HAL_StatusTypeDef | CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.

Function Documentation

static HAL_StatusTypeDef CAN_Receive_IT | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber
 | ) |  | [static]

Receives a correct CAN frame.

Parameters:
hcan,: Pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber,: Specify the FIFO number
Return values:
HAL status
None

Definition at line 1396 of file stm32f1xx_hal_can.c.

References __HAL_CAN_DISABLE_IT, __HAL_CAN_FIFO_RELEASE, CAN_FIFO0, CAN_FIFO1, CAN_ID_STD, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_FOV0, CAN_IT_FOV1, CAN_IT_LEC, CanRxMsgTypeDef::Data, CanRxMsgTypeDef::DLC, CanRxMsgTypeDef::ExtId, CanRxMsgTypeDef::FIFONumber, CanRxMsgTypeDef::FMI, HAL_CAN_RxCpltCallback(), HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, CanRxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, CAN_HandleTypeDef::pRxMsg, CanRxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanRxMsgTypeDef::StdId.

Referenced by HAL_CAN_IRQHandler().

static HAL_StatusTypeDef CAN_Transmit_IT ( CAN_HandleTypeDef * hcan ) [static]

Initiates and transmits a CAN frame message.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 1351 of file stm32f1xx_hal_can.c.

References __HAL_CAN_DISABLE_IT, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_LEC, CAN_IT_TME, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, HAL_CAN_TxCpltCallback(), and CAN_HandleTypeDef::State.

Referenced by HAL_CAN_IRQHandler().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CAN Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
Deinitializes the CANx peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initializes the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitializes the CAN MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize and configure the CAN.
      (+) De-initialize the CAN.

Function Documentation

HAL_StatusTypeDef HAL_CAN_ConfigFilter | ( | CAN_HandleTypeDef * | hcan,
 |  | CAN_FilterConfTypeDef * | sFilterConfig
 | ) |  |

Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
sFilterConfig,: pointer to a CAN_FilterConfTypeDef structure that contains the filter configuration information.
Return values:
None

Definition at line 366 of file stm32f1xx_hal_can.c.

References assert_param, CAN_FilterConfTypeDef::BankNumber, CAN_FILTER_FIFO0, CAN_FILTERMODE_IDMASK, CAN_FILTERSCALE_16BIT, CAN_FILTERSCALE_32BIT, CAN_FilterConfTypeDef::FilterActivation, CAN_FilterConfTypeDef::FilterFIFOAssignment, CAN_FilterConfTypeDef::FilterIdHigh, CAN_FilterConfTypeDef::FilterIdLow, CAN_FilterConfTypeDef::FilterMaskIdHigh, CAN_FilterConfTypeDef::FilterMaskIdLow, CAN_FilterConfTypeDef::FilterMode, CAN_FilterConfTypeDef::FilterNumber, CAN_FilterConfTypeDef::FilterScale, CAN_HandleTypeDef::Instance, IS_CAN_BANKNUMBER, IS_CAN_FILTER_FIFO, IS_CAN_FILTER_MODE, IS_CAN_FILTER_NUMBER, and IS_CAN_FILTER_SCALE.

HAL_StatusTypeDef HAL_CAN_DeInit ( CAN_HandleTypeDef * hcan )

Deinitializes the CANx peripheral registers to their default reset values.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 469 of file stm32f1xx_hal_can.c.

References assert_param, HAL_CAN_MspDeInit(), HAL_CAN_STATE_BUSY, HAL_CAN_STATE_RESET, CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Init ( CAN_HandleTypeDef * hcan )

Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 173 of file stm32f1xx_hal_can.c.

References CAN_InitTypeDef::ABOM, assert_param, CAN_InitTypeDef::AWUM, CAN_InitTypeDef::BS1, CAN_InitTypeDef::BS2, CAN_INITSTATUS_FAILED, CAN_INITSTATUS_SUCCESS, CAN_TIMEOUT_VALUE, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_NONE, HAL_CAN_MspInit(), HAL_CAN_STATE_BUSY, HAL_CAN_STATE_ERROR, HAL_CAN_STATE_READY, HAL_CAN_STATE_RESET, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Init, CAN_HandleTypeDef::Instance, IS_CAN_BS1, IS_CAN_BS2, IS_CAN_MODE, IS_CAN_PRESCALER, IS_CAN_SJW, CAN_HandleTypeDef::Lock, CAN_InitTypeDef::Mode, CAN_InitTypeDef::NART, CAN_InitTypeDef::Prescaler, CAN_InitTypeDef::RFLM, CAN_InitTypeDef::SJW, CAN_HandleTypeDef::State, CAN_InitTypeDef::TTCM, and CAN_InitTypeDef::TXFP.

void HAL_CAN_MspDeInit ( CAN_HandleTypeDef * hcan )

DeInitializes the CAN MSP.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 517 of file stm32f1xx_hal_can.c.

Referenced by HAL_CAN_DeInit().

void HAL_CAN_MspInit ( CAN_HandleTypeDef * hcan )

Initializes the CAN MSP.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 502 of file stm32f1xx_hal_can.c.

Referenced by HAL_CAN_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
CAN Exported Functions

I/O operation functions. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enters the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handles CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.

Detailed Description

I/O operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Transmit a CAN frame message.
      (+) Receive a CAN frame message.
      (+) Enter CAN peripheral in sleep mode.
      (+) Wake up the CAN peripheral from sleep mode.

Function Documentation

void HAL_CAN_ErrorCallback ( CAN_HandleTypeDef * hcan )

Error CAN callback.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1282 of file stm32f1xx_hal_can.c.

Referenced by HAL_CAN_IRQHandler().

void HAL_CAN_IRQHandler ( CAN_HandleTypeDef * hcan )

Handles CAN interrupt request.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1074 of file stm32f1xx_hal_can.c.

References __HAL_CAN_CLEAR_FLAG, __HAL_CAN_DISABLE_IT, __HAL_CAN_GET_FLAG, __HAL_CAN_GET_IT_SOURCE, __HAL_CAN_MSG_PENDING, __HAL_CAN_TRANSMIT_STATUS, CAN_FIFO0, CAN_FIFO1, CAN_FLAG_BOF, CAN_FLAG_EPV, CAN_FLAG_EWG, CAN_FLAG_FOV0, CAN_FLAG_FOV1, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_FOV0, CAN_IT_FOV1, CAN_IT_LEC, CAN_IT_TME, CAN_Receive_IT(), CAN_Transmit_IT(), CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_ACK, HAL_CAN_ERROR_BD, HAL_CAN_ERROR_BOF, HAL_CAN_ERROR_BR, HAL_CAN_ERROR_CRC, HAL_CAN_ERROR_EPV, HAL_CAN_ERROR_EWG, HAL_CAN_ERROR_FOR, HAL_CAN_ERROR_FOV0, HAL_CAN_ERROR_FOV1, HAL_CAN_ERROR_NONE, HAL_CAN_ERROR_STF, HAL_CAN_ErrorCallback(), HAL_CAN_STATE_READY, CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Receive | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber,
 |  | uint32_t | Timeout
 | ) |  |

Receives a correct CAN frame.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber,: FIFO Number value
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 791 of file stm32f1xx_hal_can.c.

References __HAL_CAN_FIFO_RELEASE, __HAL_CAN_MSG_PENDING, assert_param, CAN_FIFO0, CAN_FIFO1, CAN_ID_EXT, CAN_ID_STD, CAN_RTR_REMOTE, CanRxMsgTypeDef::Data, CanRxMsgTypeDef::DLC, CanRxMsgTypeDef::ExtId, CanRxMsgTypeDef::FIFONumber, CanRxMsgTypeDef::FMI, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CanRxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_FIFO, CAN_HandleTypeDef::pRxMsg, CanRxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanRxMsgTypeDef::StdId.

HAL_StatusTypeDef HAL_CAN_Receive_IT | ( | CAN_HandleTypeDef * | hcan,
 |  | uint8_t | FIFONumber
 | ) |  |

Receives a correct CAN frame.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
FIFONumber,: Specify the FIFO number
Return values:
HAL status

Definition at line 896 of file stm32f1xx_hal_can.c.

References __HAL_CAN_ENABLE_IT, assert_param, CAN_FIFO0, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_FMP0, CAN_IT_FMP1, CAN_IT_FOV0, CAN_IT_FOV1, CAN_IT_LEC, CAN_IT_TME, CAN_HandleTypeDef::ErrorCode, HAL_CAN_ERROR_NONE, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_READY, IS_CAN_FIFO, and CAN_HandleTypeDef::State.

void HAL_CAN_RxCpltCallback ( CAN_HandleTypeDef * hcan )

Transmission complete callback in non blocking mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1267 of file stm32f1xx_hal_can.c.

Referenced by CAN_Receive_IT().

HAL_StatusTypeDef HAL_CAN_Sleep ( CAN_HandleTypeDef * hcan )

Enters the Sleep (low power) mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status.

Definition at line 961 of file stm32f1xx_hal_can.c.

References CAN_TIMEOUT_VALUE, HAL_CAN_STATE_BUSY, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CAN_Transmit | ( | CAN_HandleTypeDef * | hcan,
 |  | uint32_t | Timeout
 | ) |  |

Initiates and transmits a CAN frame message.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Timeout,: Specify Timeout value
Return values:
HAL status

Definition at line 554 of file stm32f1xx_hal_can.c.

References __HAL_CAN_CANCEL_TRANSMIT, __HAL_CAN_TRANSMIT_STATUS, assert_param, CAN_ID_STD, CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, CAN_TXSTATUS_NOMAILBOX, CanTxMsgTypeDef::Data, CanTxMsgTypeDef::DLC, CanTxMsgTypeDef::ExtId, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_ERROR, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CanTxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_DLC, IS_CAN_EXTID, IS_CAN_IDTYPE, IS_CAN_RTR, IS_CAN_STDID, CAN_HandleTypeDef::pTxMsg, CanTxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanTxMsgTypeDef::StdId.

HAL_StatusTypeDef HAL_CAN_Transmit_IT ( CAN_HandleTypeDef * hcan )

Initiates and transmits a CAN frame message.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status

Definition at line 681 of file stm32f1xx_hal_can.c.

References __HAL_CAN_ENABLE_IT, assert_param, CAN_ID_STD, CAN_IT_BOF, CAN_IT_EPV, CAN_IT_ERR, CAN_IT_EWG, CAN_IT_LEC, CAN_IT_TME, CAN_TXMAILBOX_0, CAN_TXMAILBOX_1, CAN_TXMAILBOX_2, CAN_TXSTATUS_NOMAILBOX, CanTxMsgTypeDef::Data, CanTxMsgTypeDef::DLC, CAN_HandleTypeDef::ErrorCode, CanTxMsgTypeDef::ExtId, HAL_CAN_ERROR_NONE, HAL_CAN_STATE_BUSY_RX, HAL_CAN_STATE_BUSY_TX, HAL_CAN_STATE_BUSY_TX_RX, HAL_CAN_STATE_ERROR, CanTxMsgTypeDef::IDE, CAN_HandleTypeDef::Instance, IS_CAN_DLC, IS_CAN_EXTID, IS_CAN_IDTYPE, IS_CAN_RTR, IS_CAN_STDID, CAN_HandleTypeDef::pTxMsg, CanTxMsgTypeDef::RTR, CAN_HandleTypeDef::State, and CanTxMsgTypeDef::StdId.

void HAL_CAN_TxCpltCallback ( CAN_HandleTypeDef * hcan )

Transmission complete callback in non blocking mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
None

Definition at line 1252 of file stm32f1xx_hal_can.c.

Referenced by CAN_Transmit_IT().

HAL_StatusTypeDef HAL_CAN_WakeUp ( CAN_HandleTypeDef * hcan )

Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL status.

Definition at line 1022 of file stm32f1xx_hal_can.c.

References CAN_TIMEOUT_VALUE, HAL_CAN_STATE_BUSY, HAL_CAN_STATE_READY, HAL_CAN_STATE_TIMEOUT, HAL_GetTick(), CAN_HandleTypeDef::Instance, and CAN_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
CAN Exported Functions

CAN Peripheral State functions. More...

Functions

HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
return the CAN state
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.

Detailed Description

CAN Peripheral State functions.

  ==============================================================================
            ##### Peripheral State and Error functions #####
  ==============================================================================
    [..]
    This subsection provides functions allowing to :
      (+) Check the CAN state.
      (+) Check CAN Errors detected during interrupt process

Function Documentation

uint32_t HAL_CAN_GetError ( CAN_HandleTypeDef * hcan )

Return the CAN error code.

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
CAN Error Code

Definition at line 1329 of file stm32f1xx_hal_can.c.

References CAN_HandleTypeDef::ErrorCode.

HAL_CAN_StateTypeDef HAL_CAN_GetState ( CAN_HandleTypeDef * hcan )

return the CAN state

Parameters:
hcan,: pointer to a CAN_HandleTypeDef structure that contains the configuration information for the specified CAN.
Return values:
HAL state

Definition at line 1317 of file stm32f1xx_hal_can.c.

References CAN_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Exported Types

Data Structures | Enumerations
CAN Exported Types
CAN

Data Structures

struct | CAN_InitTypeDef
CAN init structure definition. More...
struct | CanTxMsgTypeDef
CAN Tx message structure definition. More...
struct | CanRxMsgTypeDef
CAN Rx message structure definition. More...
struct | CAN_HandleTypeDef
CAN handle Structure definition. More...

Enumerations

enum HAL_CAN_StateTypeDef {
HAL_CAN_STATE_RESET = 0x00U, HAL_CAN_STATE_READY = 0x01U, HAL_CAN_STATE_BUSY = 0x02U, HAL_CAN_STATE_BUSY_TX = 0x12U,
HAL_CAN_STATE_BUSY_RX = 0x22U, HAL_CAN_STATE_BUSY_TX_RX = 0x32U, HAL_CAN_STATE_TIMEOUT = 0x03U, HAL_CAN_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_CAN_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_CAN_STATE_RESET

CAN not yet initialized or disabled

HAL_CAN_STATE_READY

CAN initialized and ready for use

HAL_CAN_STATE_BUSY

CAN process is ongoing

HAL_CAN_STATE_BUSY_TX

CAN process is ongoing

HAL_CAN_STATE_BUSY_RX

CAN process is ongoing

HAL_CAN_STATE_BUSY_TX_RX

CAN process is ongoing

HAL_CAN_STATE_TIMEOUT

CAN in Timeout state

HAL_CAN_STATE_ERROR

CAN error state

Definition at line 68 of file stm32f1xx_hal_can.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_InitTypeDef Struct Reference
CAN Exported Types

CAN init structure definition. More...

#include <stm32f1xx_hal_can.h>

Data Fields

uint32_t | Prescaler
uint32_t | Mode
uint32_t | SJW
uint32_t | BS1
uint32_t | BS2
uint32_t | TTCM
uint32_t | ABOM
uint32_t | AWUM
uint32_t | NART
uint32_t | RFLM
uint32_t | TXFP

Detailed Description

CAN init structure definition.

Definition at line 84 of file stm32f1xx_hal_can.h.

Field Documentation

uint32_t CAN_InitTypeDef::ABOM

Enable or disable the automatic bus-off management. This parameter can be set to ENABLE or DISABLE

Definition at line 106 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::AWUM

Enable or disable the automatic wake-up mode. This parameter can be set to ENABLE or DISABLE

Definition at line 109 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::BS1

Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of CAN Time Quantum in Bit Segment 1

Definition at line 97 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::BS2

Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of CAN Time Quantum in bit segment 2

Definition at line 100 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::Mode

Specifies the CAN operating mode. This parameter can be a value of CAN Operating Mode

Definition at line 89 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::NART

Enable or disable the non-automatic retransmission mode. This parameter can be set to ENABLE or DISABLE

Definition at line 112 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::Prescaler

Specifies the length of a time quantum. This parameter must be a number between Min_Data = 1 and Max_Data = 1024

Definition at line 86 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::RFLM

Enable or disable the receive FIFO Locked mode. This parameter can be set to ENABLE or DISABLE

Definition at line 115 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::SJW

Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of CAN Synchronization Jump Width

Definition at line 92 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::TTCM

Enable or disable the time triggered communication mode. This parameter can be set to ENABLE or DISABLE.

Definition at line 103 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

uint32_t CAN_InitTypeDef::TXFP

Enable or disable the transmit FIFO priority. This parameter can be set to ENABLE or DISABLE

Definition at line 118 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_can.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CanTxMsgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CanTxMsgTypeDef Struct Reference
CAN Exported Types

CAN Tx message structure definition. More...

#include <stm32f1xx_hal_can.h>

Data Fields

uint32_t | StdId
uint32_t | ExtId
uint32_t | IDE
uint32_t | RTR
uint32_t | DLC
uint8_t | Data [8]

Detailed Description

CAN Tx message structure definition.

Definition at line 125 of file stm32f1xx_hal_can.h.

Field Documentation

uint8_t CanTxMsgTypeDef::Data[8]

Contains the data to be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF

Definition at line 142 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::DLC

Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8

Definition at line 139 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::ExtId

Specifies the extended identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF

Definition at line 130 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::IDE

Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of CAN Identifier Type

Definition at line 133 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::RTR

Specifies the type of frame for the message that will be transmitted. This parameter can be a value of CAN Remote Transmission Request

Definition at line 136 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

uint32_t CanTxMsgTypeDef::StdId

Specifies the standard identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF

Definition at line 127 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_can.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CanRxMsgTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CanRxMsgTypeDef Struct Reference
CAN Exported Types

CAN Rx message structure definition. More...

#include <stm32f1xx_hal_can.h>

Data Fields

uint32_t | StdId
uint32_t | ExtId
uint32_t | IDE
uint32_t | RTR
uint32_t | DLC
uint8_t | Data [8]
uint32_t | FMI
uint32_t | FIFONumber

Detailed Description

CAN Rx message structure definition.

Definition at line 150 of file stm32f1xx_hal_can.h.

Field Documentation

uint8_t CanRxMsgTypeDef::Data[8]

Contains the data to be received. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF

Definition at line 167 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::DLC

Specifies the length of the frame that will be received. This parameter must be a number between Min_Data = 0 and Max_Data = 8

Definition at line 164 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::ExtId

Specifies the extended identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF

Definition at line 155 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::FIFONumber

Specifies the receive FIFO number. This parameter can be CAN_FIFO0 or CAN_FIFO1

Definition at line 173 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::FMI

Specifies the index of the filter the message stored in the mailbox passes through. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF

Definition at line 170 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::IDE

Specifies the type of identifier for the message that will be received. This parameter can be a value of CAN Identifier Type

Definition at line 158 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::RTR

Specifies the type of frame for the received message. This parameter can be a value of CAN Remote Transmission Request

Definition at line 161 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

uint32_t CanRxMsgTypeDef::StdId

Specifies the standard identifier. This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF

Definition at line 152 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_can.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_HandleTypeDef Struct Reference
CAN Exported Types

CAN handle Structure definition. More...

#include <stm32f1xx_hal_can.h>

Data Fields

CAN_TypeDef * | Instance
CAN_InitTypeDef Init
CanTxMsgTypeDef * pTxMsg
CanRxMsgTypeDef * pRxMsg
__IO HAL_CAN_StateTypeDef | State
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode

Detailed Description

CAN handle Structure definition.

Definition at line 181 of file stm32f1xx_hal_can.h.

Field Documentation

__IO uint32_t CAN_HandleTypeDef::ErrorCode

CAN Error code

Definition at line 195 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_GetError(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

CAN_InitTypeDef CAN_HandleTypeDef::Init

CAN required parameters

Definition at line 185 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

CAN_TypeDef* CAN_HandleTypeDef::Instance

Register base address

Definition at line 183 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_ConfigFilter(), HAL_CAN_DeInit(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), and HAL_CAN_WakeUp().

HAL_LockTypeDef CAN_HandleTypeDef::Lock

CAN locking object

Definition at line 193 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

CanRxMsgTypeDef* CAN_HandleTypeDef::pRxMsg

Pointer to reception structure

Definition at line 189 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

CanTxMsgTypeDef* CAN_HandleTypeDef::pTxMsg

Pointer to transmit structure

Definition at line 187 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

__IO HAL_CAN_StateTypeDef CAN_HandleTypeDef::State

CAN communication state

Definition at line 191 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_DeInit(), HAL_CAN_GetState(), HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), HAL_CAN_Receive_IT(), HAL_CAN_Sleep(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), and HAL_CAN_WakeUp().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_can.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Error Code

Defines
CAN Error Code
CAN Exported Constants

Defines

#define | HAL_CAN_ERROR_NONE 0x00U
#define | HAL_CAN_ERROR_EWG 0x01U
#define | HAL_CAN_ERROR_EPV 0x02U
#define | HAL_CAN_ERROR_BOF 0x04U
#define | HAL_CAN_ERROR_STF 0x08U
#define | HAL_CAN_ERROR_FOR 0x10U
#define | HAL_CAN_ERROR_ACK 0x20U
#define | HAL_CAN_ERROR_BR 0x40U
#define | HAL_CAN_ERROR_BD 0x80U
#define | HAL_CAN_ERROR_CRC 0x100U
#define | HAL_CAN_ERROR_FOV0 0x200U
#define | HAL_CAN_ERROR_FOV1 0x400U

Define Documentation

#define HAL_CAN_ERROR_ACK 0x20U

Acknowledgment error

Definition at line 217 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BD 0x80U

LEC dominant

Definition at line 219 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BOF 0x04U

BOF error

Definition at line 214 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_BR 0x40U

Bit recessive

Definition at line 218 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_CRC 0x100U

LEC transfer error

Definition at line 220 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_EPV 0x02U

EPV error

Definition at line 213 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_EWG 0x01U

EWG error

Definition at line 212 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_FOR 0x10U

Form error

Definition at line 216 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_FOV0 0x200U

FIFO0 overrun error

Definition at line 221 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_FOV1 0x400U

FIFO1 overrun error

Definition at line 222 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define HAL_CAN_ERROR_NONE 0x00U

No error

Definition at line 211 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define HAL_CAN_ERROR_STF 0x08U

Stuff error

Definition at line 215 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

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STM32F103xB HAL User Manual: CAN initialization Status

Defines
CAN initialization Status
CAN Exported Constants

Defines

#define | CAN_INITSTATUS_FAILED 0x00000000U
#define | CAN_INITSTATUS_SUCCESS 0x00000001U

Define Documentation

#define CAN_INITSTATUS_FAILED 0x00000000U

CAN initialization failed

Definition at line 230 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define CAN_INITSTATUS_SUCCESS 0x00000001U

CAN initialization OK

Definition at line 231 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Operating Mode

Defines
CAN Operating Mode
CAN Exported Constants

Defines

#define | CAN_MODE_NORMAL 0x00000000U
#define | CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)
#define | CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)
#define | CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))

Define Documentation

#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)

Loopback mode

Definition at line 240 of file stm32f1xx_hal_can.h.

#define CAN_MODE_NORMAL 0x00000000U

Normal mode

Definition at line 239 of file stm32f1xx_hal_can.h.

#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)

Silent mode

Definition at line 241 of file stm32f1xx_hal_can.h.

#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))

Loopback combined with silent mode

Definition at line 242 of file stm32f1xx_hal_can.h.

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STM32F103xB HAL User Manual: CAN Synchronization Jump Width

Defines
CAN Synchronization Jump Width
CAN Exported Constants

Defines

#define | CAN_SJW_1TQ 0x00000000U
#define | CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)
#define | CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)
#define | CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)

Define Documentation

#define CAN_SJW_1TQ 0x00000000U

1 time quantum

Definition at line 250 of file stm32f1xx_hal_can.h.

#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)

2 time quantum

Definition at line 251 of file stm32f1xx_hal_can.h.

#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)

3 time quantum

Definition at line 252 of file stm32f1xx_hal_can.h.

#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)

4 time quantum

Definition at line 253 of file stm32f1xx_hal_can.h.

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STM32F103xB HAL User Manual: CAN Time Quantum in Bit Segment 1

Defines
CAN Time Quantum in Bit Segment 1
CAN Exported Constants

Defines

#define | CAN_BS1_1TQ 0x00000000U
#define | CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)
#define | CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)
#define | CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)
#define | CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)
#define | CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))
#define | CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))
#define | CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))
#define | CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)

Define Documentation

#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))

10 time quantum

Definition at line 270 of file stm32f1xx_hal_can.h.

#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))

11 time quantum

Definition at line 271 of file stm32f1xx_hal_can.h.

#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

12 time quantum

Definition at line 272 of file stm32f1xx_hal_can.h.

#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))

13 time quantum

Definition at line 273 of file stm32f1xx_hal_can.h.

#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))

14 time quantum

Definition at line 274 of file stm32f1xx_hal_can.h.

#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))

15 time quantum

Definition at line 275 of file stm32f1xx_hal_can.h.

#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)

16 time quantum

Definition at line 276 of file stm32f1xx_hal_can.h.

#define CAN_BS1_1TQ 0x00000000U

1 time quantum

Definition at line 261 of file stm32f1xx_hal_can.h.

#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)

2 time quantum

Definition at line 262 of file stm32f1xx_hal_can.h.

#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)

3 time quantum

Definition at line 263 of file stm32f1xx_hal_can.h.

#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

4 time quantum

Definition at line 264 of file stm32f1xx_hal_can.h.

#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)

5 time quantum

Definition at line 265 of file stm32f1xx_hal_can.h.

#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))

6 time quantum

Definition at line 266 of file stm32f1xx_hal_can.h.

#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))

7 time quantum

Definition at line 267 of file stm32f1xx_hal_can.h.

#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))

8 time quantum

Definition at line 268 of file stm32f1xx_hal_can.h.

#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)

9 time quantum

Definition at line 269 of file stm32f1xx_hal_can.h.

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STM32F103xB HAL User Manual: CAN Time Quantum in bit segment 2

Defines
CAN Time Quantum in bit segment 2
CAN Exported Constants

Defines

#define | CAN_BS2_1TQ 0x00000000U
#define | CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)
#define | CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)
#define | CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))
#define | CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)
#define | CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))
#define | CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))
#define | CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)

Define Documentation

#define CAN_BS2_1TQ 0x00000000U

1 time quantum

Definition at line 284 of file stm32f1xx_hal_can.h.

#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)

2 time quantum

Definition at line 285 of file stm32f1xx_hal_can.h.

#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)

3 time quantum

Definition at line 286 of file stm32f1xx_hal_can.h.

#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))

4 time quantum

Definition at line 287 of file stm32f1xx_hal_can.h.

#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)

5 time quantum

Definition at line 288 of file stm32f1xx_hal_can.h.

#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))

6 time quantum

Definition at line 289 of file stm32f1xx_hal_can.h.

#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))

7 time quantum

Definition at line 290 of file stm32f1xx_hal_can.h.

#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)

8 time quantum

Definition at line 291 of file stm32f1xx_hal_can.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Filter Mode

Defines
CAN Filter Mode
CAN Exported Constants

Defines

#define | CAN_FILTERMODE_IDMASK ((uint8_t)0x00)
#define | CAN_FILTERMODE_IDLIST ((uint8_t)0x01)

Define Documentation

#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01)

Identifier list mode

Definition at line 300 of file stm32f1xx_hal_can.h.

#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00)

Identifier mask mode

Definition at line 299 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Filter Scale

Defines
CAN Filter Scale
CAN Exported Constants

Defines

#define | CAN_FILTERSCALE_16BIT ((uint8_t)0x00)
#define | CAN_FILTERSCALE_32BIT ((uint8_t)0x01)

Define Documentation

#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00)

Two 16-bit filters

Definition at line 308 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01)

One 32-bit filter

Definition at line 309 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Filter FIFO

Defines
CAN Filter FIFO
CAN Exported Constants

Defines

#define | CAN_FILTER_FIFO0 ((uint8_t)0x00)
#define | CAN_FILTER_FIFO1 ((uint8_t)0x01)

Define Documentation

#define CAN_FILTER_FIFO0 ((uint8_t)0x00)

Filter FIFO 0 assignment for filter x

Definition at line 317 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define CAN_FILTER_FIFO1 ((uint8_t)0x01)

Filter FIFO 1 assignment for filter x

Definition at line 318 of file stm32f1xx_hal_can.h.

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STM32F103xB HAL User Manual: CAN Identifier Type

Defines
CAN Identifier Type
CAN Exported Constants

Defines

#define | CAN_ID_STD 0x00000000U
#define | CAN_ID_EXT 0x00000004U

Define Documentation

#define CAN_ID_EXT 0x00000004U

Extended Id

Definition at line 327 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Receive().

#define CAN_ID_STD 0x00000000U

Standard Id

Definition at line 326 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_Receive(), HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Remote Transmission Request

Defines
CAN Remote Transmission Request
CAN Exported Constants

Defines

#define | CAN_RTR_DATA 0x00000000U
#define | CAN_RTR_REMOTE 0x00000002U

Define Documentation

#define CAN_RTR_DATA 0x00000000U

Data frame

Definition at line 335 of file stm32f1xx_hal_can.h.

#define CAN_RTR_REMOTE 0x00000002U

Remote frame

Definition at line 336 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Receive().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Transmit Constants

Defines
CAN Transmit Constants
CAN Exported Constants

Defines

#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04)

Define Documentation

#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04)

CAN cell did not provide CAN_TxStatus_NoMailBox

Definition at line 344 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Receive FIFO Number

Defines
CAN Receive FIFO Number
CAN Exported Constants

Defines

#define | CAN_FIFO0 ((uint8_t)0x00)
#define | CAN_FIFO1 ((uint8_t)0x01)

Define Documentation

#define CAN_FIFO0 ((uint8_t)0x00)

CAN FIFO 0 used to receive

Definition at line 352 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive(), and HAL_CAN_Receive_IT().

#define CAN_FIFO1 ((uint8_t)0x01)

CAN FIFO 1 used to receive

Definition at line 353 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Flags

Defines
CAN Flags
CAN Exported Constants

Defines

#define | CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))
#define | CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION))
#define | CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION))
#define | CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION))
#define | CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION))
#define | CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))
#define | CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION))
#define | CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION))
#define | CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION))
#define | CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION))
#define | CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION))
#define | CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION))
#define | CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION))
#define | CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION))
#define | CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION))
#define | CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION))
#define | CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION))
#define | CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION))
#define | CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION))

Define Documentation

#define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION))

Bus-Off flag

Definition at line 395 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION))

Error passive flag

Definition at line 394 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION))

Error warning flag

Definition at line 393 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION))

FIFO 0 Full flag

Definition at line 378 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION))

FIFO 1 Full flag

Definition at line 381 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION))

FIFO 0 Overrun flag

Definition at line 379 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION))

FIFO 1 Overrun flag

Definition at line 382 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))

Request MailBox0 flag

Definition at line 367 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION))

Request MailBox1 flag

Definition at line 368 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION))

Request MailBox2 flag

Definition at line 369 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION))

Sleep acknowledge flag

Definition at line 386 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION))

Sleep acknowledge flag

Definition at line 387 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION))

Transmit mailbox 0 empty flag

Definition at line 373 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION))

Transmit mailbox 0 empty flag

Definition at line 374 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION))

Transmit mailbox 0 empty flag

Definition at line 375 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION))

Transmission OK MailBox0 flag

Definition at line 370 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION))

Transmission OK MailBox1 flag

Definition at line 371 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))

Transmission OK MailBox2 flag

Definition at line 372 of file stm32f1xx_hal_can.h.

#define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION))

Wake up flag

Definition at line 385 of file stm32f1xx_hal_can.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Interrupts

Defines
CAN Interrupts
CAN Exported Constants

Defines

#define | CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)
#define | CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)
#define | CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)
#define | CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)
#define | CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)
#define | CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)
#define | CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)
#define | CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)
#define | CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)
#define | CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)
#define | CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)
#define | CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)
#define | CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)
#define | CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)

Define Documentation

#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)

Bus-off interrupt

Definition at line 421 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)

Error passive interrupt

Definition at line 420 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)

Error Interrupt

Definition at line 423 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)

Error warning interrupt

Definition at line 419 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)

FIFO 0 full interrupt

Definition at line 408 of file stm32f1xx_hal_can.h.

#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)

FIFO 1 full interrupt

Definition at line 411 of file stm32f1xx_hal_can.h.

#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)

FIFO 0 message pending interrupt

Definition at line 407 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)

FIFO 1 message pending interrupt

Definition at line 410 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)

FIFO 0 overrun interrupt

Definition at line 409 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)

FIFO 1 overrun interrupt

Definition at line 412 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), HAL_CAN_IRQHandler(), and HAL_CAN_Receive_IT().

#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)

Last error code interrupt

Definition at line 422 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)

Sleep acknowledge interrupt

Definition at line 416 of file stm32f1xx_hal_can.h.

#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)

Transmit mailbox empty interrupt

Definition at line 404 of file stm32f1xx_hal_can.h.

Referenced by CAN_Transmit_IT(), HAL_CAN_IRQHandler(), HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)

Wake-up interrupt

Definition at line 415 of file stm32f1xx_hal_can.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Exported Macros

Defines
CAN Exported Macros
CAN

Defines

#define | __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
Reset CAN handle state.
#define | __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable the specified CAN interrupts.
#define | __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable the specified CAN interrupts.
#define | __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__)
Return the number of pending received messages.
#define | __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified CAN flag is set or not.
#define | __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified CAN pending flag.
#define | __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check if the specified CAN interrupt source is enabled or disabled.
#define | __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)
Check the transmission status of a CAN Frame.
#define | __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__)
Release the specified receive FIFO.
#define | __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)
Cancel a transmit request.
#define | __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__)
Enable or disables the DBG Freeze for CAN.

Define Documentation

#define __HAL_CAN_CANCEL_TRANSMIT | ( | __HANDLE__,
 |  | __TRANSMITMAILBOX__
 | ) |
Value:
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
 ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))

Cancel a transmit request.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__TRANSMITMAILBOX__,: the number of the mailbox that is used for transmission.
Return values:
None.

Definition at line 660 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit().

#define __HAL_CAN_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)

Clear the specified CAN pending flag.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • CAN_TSR_RQCP0: Request MailBox0 Flag
  • CAN_TSR_RQCP1: Request MailBox1 Flag
  • CAN_TSR_RQCP2: Request MailBox2 Flag
  • CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
  • CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
  • CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
  • CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
  • CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
  • CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
  • CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
  • CAN_FLAG_FF0: FIFO 0 Full Flag
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
  • CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
  • CAN_FLAG_FF1: FIFO 1 Full Flag
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
  • CAN_FLAG_WKU: Wake up Flag
  • CAN_FLAG_SLAKI: Sleep acknowledge Flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 606 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_DBG_FREEZE | ( | __HANDLE__,
 |  | __NEWSTATE__
 | ) |
Value:
(((__NEWSTATE__) == ENABLE)? \
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))

Enable or disables the DBG Freeze for CAN.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__NEWSTATE__,: new state of the CAN peripheral. This parameter can be: ENABLE (CAN reception/transmission is frozen during debug. Reception FIFOs can still be accessed/controlled normally) or DISABLE (CAN is working during debug).
Return values:
None

Definition at line 674 of file stm32f1xx_hal_can.h.

#define __HAL_CAN_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

Disable the specified CAN interrupts.

Parameters:
__HANDLE__,: CAN handle.
__INTERRUPT__,: CAN Interrupt. This parameter can be one of the following values:
  • CAN_IT_TME: Transmit mailbox empty interrupt enable
  • CAN_IT_FMP0: FIFO 0 message pending interrupt
  • CAN_IT_FF0 : FIFO 0 full interrupt
  • CAN_IT_FOV0: FIFO 0 overrun interrupt
  • CAN_IT_FMP1: FIFO 1 message pending interrupt
  • CAN_IT_FF1 : FIFO 1 full interrupt
  • CAN_IT_FOV1: FIFO 1 overrun interrupt
  • CAN_IT_WKU : Wake-up interrupt
  • CAN_IT_SLK : Sleep acknowledge interrupt
  • CAN_IT_EWG : Error warning interrupt
  • CAN_IT_EPV : Error passive interrupt
  • CAN_IT_BOF : Bus-off interrupt
  • CAN_IT_LEC : Last error code interrupt
  • CAN_IT_ERR : Error Interrupt
Return values:
None.

Definition at line 538 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), CAN_Transmit_IT(), and HAL_CAN_IRQHandler().

#define __HAL_CAN_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

Enable the specified CAN interrupts.

Parameters:
__HANDLE__,: CAN handle.
__INTERRUPT__,: CAN Interrupt. This parameter can be one of the following values:
  • CAN_IT_TME: Transmit mailbox empty interrupt enable
  • CAN_IT_FMP0: FIFO 0 message pending interrupt
  • CAN_IT_FF0 : FIFO 0 full interrupt
  • CAN_IT_FOV0: FIFO 0 overrun interrupt
  • CAN_IT_FMP1: FIFO 1 message pending interrupt
  • CAN_IT_FF1 : FIFO 1 full interrupt
  • CAN_IT_FOV1: FIFO 1 overrun interrupt
  • CAN_IT_WKU : Wake-up interrupt
  • CAN_IT_SLK : Sleep acknowledge interrupt
  • CAN_IT_EWG : Error warning interrupt
  • CAN_IT_EPV : Error passive interrupt
  • CAN_IT_BOF : Bus-off interrupt
  • CAN_IT_LEC : Last error code interrupt
  • CAN_IT_ERR : Error Interrupt
Return values:
None.

Definition at line 515 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Receive_IT(), and HAL_CAN_Transmit_IT().

#define __HAL_CAN_FIFO_RELEASE | ( | __HANDLE__,
 |  | __FIFONUMBER__
 | ) |
Value:
(((__FIFONUMBER__) == CAN_FIFO0)? \
((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))

Release the specified receive FIFO.

Parameters:
__HANDLE__,: CAN handle.
__FIFONUMBER__,: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
Return values:
None.

Definition at line 651 of file stm32f1xx_hal_can.h.

Referenced by CAN_Receive_IT(), and HAL_CAN_Receive().

#define __HAL_CAN_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))

Check whether the specified CAN flag is set or not.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • CAN_TSR_RQCP0: Request MailBox0 Flag
  • CAN_TSR_RQCP1: Request MailBox1 Flag
  • CAN_TSR_RQCP2: Request MailBox2 Flag
  • CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
  • CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
  • CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
  • CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
  • CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
  • CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
  • CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
  • CAN_FLAG_FF0: FIFO 0 Full Flag
  • CAN_FLAG_FOV0: FIFO 0 Overrun Flag
  • CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
  • CAN_FLAG_FF1: FIFO 1 Full Flag
  • CAN_FLAG_FOV1: FIFO 1 Overrun Flag
  • CAN_FLAG_WKU: Wake up Flag
  • CAN_FLAG_SLAK: Sleep acknowledge Flag
  • CAN_FLAG_SLAKI: Sleep acknowledge Flag
  • CAN_FLAG_EWG: Error Warning Flag
  • CAN_FLAG_EPV: Error Passive Flag
  • CAN_FLAG_BOF: Bus-Off Flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 576 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check if the specified CAN interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__INTERRUPT__,: specifies the CAN interrupt source to check. This parameter can be one of the following values:
  • CAN_IT_TME: Transmit mailbox empty interrupt enable
  • CAN_IT_FMP0: FIFO 0 message pending interrupt
  • CAN_IT_FF0 : FIFO 0 full interrupt
  • CAN_IT_FOV0: FIFO 0 overrun interrupt
  • CAN_IT_FMP1: FIFO 1 message pending interrupt
  • CAN_IT_FF1 : FIFO 1 full interrupt
  • CAN_IT_FOV1: FIFO 1 overrun interrupt
  • CAN_IT_WKU : Wake-up interrupt
  • CAN_IT_SLK : Sleep acknowledge interrupt
  • CAN_IT_EWG : Error warning interrupt
  • CAN_IT_EPV : Error passive interrupt
  • CAN_IT_BOF : Bus-off interrupt
  • CAN_IT_LEC : Last error code interrupt
  • CAN_IT_ERR : Error Interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 632 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler().

#define __HAL_CAN_MSG_PENDING | ( | __HANDLE__,
 |  | __FIFONUMBER__
 | ) |
Value:
(((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))

Return the number of pending received messages.

Parameters:
__HANDLE__,: CAN handle.
__FIFONUMBER__,: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
Return values:
The number of pending message.

Definition at line 546 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), and HAL_CAN_Receive().

#define __HAL_CAN_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)

Reset CAN handle state.

Parameters:
__HANDLE__,: CAN handle.
Return values:
None

Definition at line 492 of file stm32f1xx_hal_can.h.

#define __HAL_CAN_TRANSMIT_STATUS | ( | __HANDLE__,
 |  | __TRANSMITMAILBOX__
 | ) |
Value:
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))

Check the transmission status of a CAN Frame.

Parameters:
__HANDLE__,: specifies the CAN Handle.
__TRANSMITMAILBOX__,: the number of the mailbox that is used for transmission.
Return values:
The new status of transmission (TRUE or FALSE).

Definition at line 640 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_IRQHandler(), and HAL_CAN_Transmit().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Private Macros

Defines
CAN Private Macros
CAN

Defines

#define | IS_CAN_MODE(MODE)
#define | IS_CAN_SJW(SJW)
#define | IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define | IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define | IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define | IS_CAN_FILTER_MODE(MODE)
#define | IS_CAN_FILTER_SCALE(SCALE)
#define | IS_CAN_FILTER_FIFO(FIFO)
#define | IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define | IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define | IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU)
#define | IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
#define | IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define | IS_CAN_IDTYPE(IDTYPE)
#define | IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define | IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Define Documentation

#define IS_CAN_BANKNUMBER ( BANKNUMBER ) ((BANKNUMBER) <= 28U)

Definition at line 758 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_BS1 ( BS1 ) ((BS1) <= CAN_BS1_16TQ)

Definition at line 748 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_BS2 ( BS2 ) ((BS2) <= CAN_BS2_8TQ)

Definition at line 749 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_DLC ( DLC ) ((DLC) <= ((uint8_t)0x08))

Definition at line 763 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_EXTID ( EXTID ) ((EXTID) <= 0x1FFFFFFFU)

Definition at line 762 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_FIFO ( FIFO ) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Definition at line 768 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Receive(), and HAL_CAN_Receive_IT().

#define IS_CAN_FILTER_FIFO ( FIFO )
Value:
(((FIFO) == CAN_FILTER_FIFO0) || \
                                  ((FIFO) == CAN_FILTER_FIFO1))

Definition at line 756 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_MODE ( MODE )
Value:
(((MODE) == CAN_FILTERMODE_IDMASK) || \
                                  ((MODE) == CAN_FILTERMODE_IDLIST))

Definition at line 752 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_FILTER_SCALE ( SCALE )
Value:
(((SCALE) == CAN_FILTERSCALE_16BIT) || \
                                    ((SCALE) == CAN_FILTERSCALE_32BIT))

Definition at line 754 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_ConfigFilter().

#define IS_CAN_IDTYPE ( IDTYPE )
Value:
(((IDTYPE) == CAN_ID_STD) || \
                                ((IDTYPE) == CAN_ID_EXT))

Definition at line 765 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_MODE ( MODE )
Value:
(((MODE) == CAN_MODE_NORMAL) || \
                           ((MODE) == CAN_MODE_LOOPBACK)|| \
                           ((MODE) == CAN_MODE_SILENT) || \
                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))

Definition at line 742 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_PRESCALER ( PRESCALER ) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))

Definition at line 750 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_RTR ( RTR ) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))

Definition at line 767 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_SJW ( SJW )
Value:
(((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))

Definition at line 746 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Init().

#define IS_CAN_STDID ( STDID ) ((STDID) <= 0x00007FFU)

Definition at line 761 of file stm32f1xx_hal_can.h.

Referenced by HAL_CAN_Transmit(), and HAL_CAN_Transmit_IT().

#define IS_CAN_TRANSMITMAILBOX ( TRANSMITMAILBOX ) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))

Definition at line 760 of file stm32f1xx_hal_can.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN Extended Private Macros

Defines
CAN Extended Private Macros
CANEx

Defines

#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13U)

Define Documentation

#define IS_CAN_FILTER_NUMBER ( NUMBER ) ((NUMBER) <= 13U)

Definition at line 122 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CAN_FilterConfTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CAN_FilterConfTypeDef Struct Reference
CANEx

CAN filter configuration structure definition. More...

#include <stm32f1xx_hal_can_ex.h>

Data Fields

uint32_t | FilterIdHigh
uint32_t | FilterIdLow
uint32_t | FilterMaskIdHigh
uint32_t | FilterMaskIdLow
uint32_t | FilterFIFOAssignment
uint32_t | FilterNumber
uint32_t | FilterMode
uint32_t | FilterScale
uint32_t | FilterActivation
uint32_t | BankNumber

Detailed Description

CAN filter configuration structure definition.

Definition at line 69 of file stm32f1xx_hal_can_ex.h.

Field Documentation

uint32_t CAN_FilterConfTypeDef::BankNumber

Select the start slave bank filter This parameter must be a number between Min_Data = 0 and Max_Data = 28.

Definition at line 107 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterActivation

Enable or disable the filter. This parameter can be set to ENABLE or DISABLE.

Definition at line 104 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterFIFOAssignment

Specifies the FIFO (0 or 1) which will be assigned to the filter. This parameter can be a value of CAN Filter FIFO

Definition at line 89 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterIdHigh

Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 71 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterIdLow

Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 75 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMaskIdHigh

Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 79 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMaskIdLow

Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 84 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterMode

Specifies the filter mode to be initialized. This parameter can be a value of CAN Filter Mode

Definition at line 98 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterNumber

Specifies the filter which will be initialized. This parameter must be a number between Min_Data = 0 and Max_Data = 13.

Definition at line 95 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

uint32_t CAN_FilterConfTypeDef::FilterScale

Specifies the filter scale. This parameter can be a value of CAN Filter Scale

Definition at line 101 of file stm32f1xx_hal_can_ex.h.

Referenced by HAL_CAN_ConfigFilter().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_can_ex.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CORTEX Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
              ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]
      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
      Systick functionalities

Function Documentation

void HAL_NVIC_DisableIRQ ( IRQn_Type IRQn )

Disables a device specific interrupt in the NVIC interrupt controller.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
Return values:
None

Definition at line 221 of file stm32f1xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_EnableIRQ ( IRQn_Type IRQn )

Enables a device specific interrupt in the NVIC interrupt controller.

Note:
To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() function should be called before.
Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
Return values:
None

Definition at line 205 of file stm32f1xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_SetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PreemptPriority,
 |  | uint32_t | SubPriority
 | ) |  |

Sets the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))
PreemptPriority,: The preemption priority for the IRQn channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority
SubPriority,: the subpriority level for the IRQ channel. This parameter can be a value between 0 and 15 A lower priority value indicates a higher priority.
Return values:
None

Definition at line 183 of file stm32f1xx_hal_cortex.c.

References assert_param, IS_NVIC_PREEMPTION_PRIORITY, and IS_NVIC_SUB_PRIORITY.

Referenced by HAL_InitTick().

void HAL_NVIC_SetPriorityGrouping ( uint32_t PriorityGroup )

Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.

Parameters:
PriorityGroup,: The priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 0 bits for subpriority
Note:
When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. The pending IRQ priority will be managed only by the subpriority.
Return values:
None

Definition at line 161 of file stm32f1xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

Referenced by HAL_Init().

void HAL_NVIC_SystemReset ( void )

Initiates a system reset request to reset the MCU.

Return values:
None

Definition at line 234 of file stm32f1xx_hal_cortex.c.

Referenced by HAL_FLASH_OB_Launch().

uint32_t HAL_SYSTICK_Config ( uint32_t TicksNumb )

Initializes the System Timer and its interrupt, and starts the System Tick Timer.

Counter is in free running mode to generate periodic interrupts.

Parameters:
TicksNumb,: Specifies the ticks Number of ticks between two interrupts.
Return values:
status,: - 0 Function succeeded.
  • 1 Function failed.

Definition at line 247 of file stm32f1xx_hal_cortex.c.

Referenced by HAL_InitTick().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CORTEX Exported Functions

Cortex control functions. More...

Functions

uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.

Detailed Description

Cortex control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]
      This subsection provides a set of functions allowing to control the CORTEX
      (NVIC, SYSTICK, MPU) functionalities.

Function Documentation

void HAL_NVIC_ClearPendingIRQ ( IRQn_Type IRQn )

Clears the pending bit of an external interrupt.

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
Return values:
None

Definition at line 438 of file stm32f1xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetActive ( IRQn_Type IRQn )

Gets active interrupt ( reads the active register in NVIC and returns the active bit).

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 455 of file stm32f1xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

uint32_t HAL_NVIC_GetPendingIRQ ( IRQn_Type IRQn )

Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).

Parameters:
IRQn External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
Return values:
status,: - 0 Interrupt status is not pending.
  • 1 Interrupt status is pending.

Definition at line 422 of file stm32f1xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_NVIC_GetPriority | ( | IRQn_Type | IRQn,
 |  | uint32_t | PriorityGroup,
 |  | uint32_t * | pPreemptPriority,
 |  | uint32_t * | pSubPriority
 | ) |  |

Gets the priority of an interrupt.

Parameters:
IRQn,: External interrupt number. This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
PriorityGroup,: the priority grouping bits length. This parameter can be one of the following values:
  • NVIC_PRIORITYGROUP_0: 0 bits for preemption priority 4 bits for subpriority
  • NVIC_PRIORITYGROUP_1: 1 bits for preemption priority 3 bits for subpriority
  • NVIC_PRIORITYGROUP_2: 2 bits for preemption priority 2 bits for subpriority
  • NVIC_PRIORITYGROUP_3: 3 bits for preemption priority 1 bits for subpriority
  • NVIC_PRIORITYGROUP_4: 4 bits for preemption priority 0 bits for subpriority
pPreemptPriority,: Pointer on the Preemptive priority value (starting from 0).
pSubPriority,: Pointer on the Subpriority value (starting from 0).
Return values:
None

Definition at line 389 of file stm32f1xx_hal_cortex.c.

References assert_param, and IS_NVIC_PRIORITY_GROUP.

uint32_t HAL_NVIC_GetPriorityGrouping ( void )

Gets the priority grouping field from the NVIC Interrupt Controller.

Return values:
Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)

Definition at line 362 of file stm32f1xx_hal_cortex.c.

void HAL_NVIC_SetPendingIRQ ( IRQn_Type IRQn )

Sets Pending bit of an external interrupt.

Parameters:
IRQn External interrupt number This parameter can be an enumerator of IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
Return values:
None

Definition at line 404 of file stm32f1xx_hal_cortex.c.

References assert_param, and IS_NVIC_DEVICE_IRQ.

void HAL_SYSTICK_Callback ( void )

SYSTICK callback.

Return values:
None

Definition at line 499 of file stm32f1xx_hal_cortex.c.

Referenced by HAL_SYSTICK_IRQHandler().

void HAL_SYSTICK_CLKSourceConfig ( uint32_t CLKSource )

Configures the SysTick clock source.

Parameters:
CLKSource,: specifies the SysTick clock source. This parameter can be one of the following values:
  • SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
  • SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
Return values:
None

Definition at line 472 of file stm32f1xx_hal_cortex.c.

References assert_param, IS_SYSTICK_CLK_SOURCE, and SYSTICK_CLKSOURCE_HCLK.

void HAL_SYSTICK_IRQHandler ( void )

This function handles SYSTICK interrupt request.

Return values:
None

Definition at line 490 of file stm32f1xx_hal_cortex.c.

References HAL_SYSTICK_Callback().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Cortex Exported Types

Cortex Exported Types
CORTEX
Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CORTEX Preemption Priority Group

Defines
CORTEX Preemption Priority Group
CORTEX Exported Constants

Defines

#define | NVIC_PRIORITYGROUP_0 0x00000007U
#define | NVIC_PRIORITYGROUP_1 0x00000006U
#define | NVIC_PRIORITYGROUP_2 0x00000005U
#define | NVIC_PRIORITYGROUP_3 0x00000004U
#define | NVIC_PRIORITYGROUP_4 0x00000003U

Define Documentation

#define NVIC_PRIORITYGROUP_0 0x00000007U

0 bits for pre-emption priority 4 bits for subpriority

Definition at line 108 of file stm32f1xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_1 0x00000006U

1 bits for pre-emption priority 3 bits for subpriority

Definition at line 110 of file stm32f1xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_2 0x00000005U

2 bits for pre-emption priority 2 bits for subpriority

Definition at line 112 of file stm32f1xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_3 0x00000004U

3 bits for pre-emption priority 1 bits for subpriority

Definition at line 114 of file stm32f1xx_hal_cortex.h.

#define NVIC_PRIORITYGROUP_4 0x00000003U

4 bits for pre-emption priority 0 bits for subpriority

Definition at line 116 of file stm32f1xx_hal_cortex.h.

Referenced by HAL_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CORTEX _SysTick clock source

Defines
CORTEX _SysTick clock source
CORTEX Exported Constants

Defines

#define | SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | SYSTICK_CLKSOURCE_HCLK 0x00000004U

Define Documentation

#define SYSTICK_CLKSOURCE_HCLK 0x00000004U

Definition at line 126 of file stm32f1xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U

Definition at line 125 of file stm32f1xx_hal_cortex.h.

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STM32F103xB HAL User Manual: CORTEX Private Macros

Defines
CORTEX Private Macros
CORTEX

Defines

#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)

Define Documentation

#define IS_NVIC_DEVICE_IRQ ( IRQ ) ((IRQ) >= (IRQn_Type)0x00U)

Definition at line 334 of file stm32f1xx_hal_cortex.h.

Referenced by HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetActive(), HAL_NVIC_GetPendingIRQ(), and HAL_NVIC_SetPendingIRQ().

#define IS_NVIC_PREEMPTION_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10U)

Definition at line 330 of file stm32f1xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_NVIC_PRIORITY_GROUP ( GROUP )
Value:
(((GROUP) == NVIC_PRIORITYGROUP_0) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
                                       ((GROUP) == NVIC_PRIORITYGROUP_4))

Definition at line 324 of file stm32f1xx_hal_cortex.h.

Referenced by HAL_NVIC_GetPriority(), and HAL_NVIC_SetPriorityGrouping().

#define IS_NVIC_SUB_PRIORITY ( PRIORITY ) ((PRIORITY) < 0x10U)

Definition at line 332 of file stm32f1xx_hal_cortex.h.

Referenced by HAL_NVIC_SetPriority().

#define IS_SYSTICK_CLK_SOURCE ( SOURCE )
Value:
(((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

Definition at line 336 of file stm32f1xx_hal_cortex.h.

Referenced by HAL_SYSTICK_CLKSourceConfig().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
CRC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initializes the CRC according to the specified parameters in the CRC_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
            ##### Initialization and de-initialization functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Initialize the CRC according to the specified parameters
          in the CRC_InitTypeDef and create the associated handle
      (+) DeInitialize the CRC peripheral
      (+) Initialize the CRC MSP
      (+) DeInitialize CRC MSP

Function Documentation

HAL_StatusTypeDef HAL_CRC_DeInit ( CRC_HandleTypeDef * hcrc )

DeInitializes the CRC peripheral.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
Return values:
HAL status

Definition at line 145 of file stm32f1xx_hal_crc.c.

References __HAL_CRC_DR_RESET, assert_param, HAL_CRC_MspDeInit(), HAL_CRC_STATE_BUSY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_CRC_Init ( CRC_HandleTypeDef * hcrc )

Initializes the CRC according to the specified parameters in the CRC_InitTypeDef and creates the associated handle.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
Return values:
HAL status

Definition at line 112 of file stm32f1xx_hal_crc.c.

References assert_param, HAL_CRC_MspInit(), HAL_CRC_STATE_READY, HAL_CRC_STATE_RESET, CRC_HandleTypeDef::Instance, CRC_HandleTypeDef::Lock, and CRC_HandleTypeDef::State.

void HAL_CRC_MspDeInit ( CRC_HandleTypeDef * hcrc )

DeInitializes the CRC MSP.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
Return values:
None

Definition at line 199 of file stm32f1xx_hal_crc.c.

Referenced by HAL_CRC_DeInit().

void HAL_CRC_MspInit ( CRC_HandleTypeDef * hcrc )

Initializes the CRC MSP.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
Return values:
None

Definition at line 184 of file stm32f1xx_hal_crc.c.

Referenced by HAL_CRC_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
CRC Exported Functions

management functions. More...

Functions

uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer using combination of the previous CRC value and the new one.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer independently of the previous CRC value.

Detailed Description

management functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
      (+) Compute the 32-bit CRC value of 32-bit data buffer,
          using combination of the previous CRC value and the new one.
      (+) Compute the 32-bit CRC value of 32-bit data buffer,
          independently of the previous CRC value.

Function Documentation

uint32_t HAL_CRC_Accumulate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Computes the 32-bit CRC of 32-bit data buffer using combination of the previous CRC value and the new one.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
pBuffer,: pointer to the buffer containing the data to be computed
BufferLength,: length of the buffer to be computed (defined in word, 4 bytes)
Return values:
32-bit CRC

Definition at line 238 of file stm32f1xx_hal_crc.c.

References HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

uint32_t HAL_CRC_Calculate | ( | CRC_HandleTypeDef * | hcrc,
 |  | uint32_t | pBuffer[],
 |  | uint32_t | BufferLength
 | ) |  |

Computes the 32-bit CRC of 32-bit data buffer independently of the previous CRC value.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
pBuffer,: Pointer to the buffer containing the data to be computed
BufferLength,: Length of the buffer to be computed (defined in word, 4 bytes)
Return values:
32-bit CRC

Definition at line 273 of file stm32f1xx_hal_crc.c.

References __HAL_CRC_DR_RESET, HAL_CRC_STATE_BUSY, HAL_CRC_STATE_READY, CRC_HandleTypeDef::Instance, and CRC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
CRC Exported Functions

Peripheral State functions. More...

Functions

HAL_CRC_StateTypeDef HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Returns the CRC state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                      ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral.

Function Documentation

HAL_CRC_StateTypeDef HAL_CRC_GetState ( CRC_HandleTypeDef * hcrc )

Returns the CRC state.

Parameters:
hcrc,: pointer to a CRC_HandleTypeDef structure that contains the configuration information for CRC
Return values:
HAL state

Definition at line 326 of file stm32f1xx_hal_crc.c.

References CRC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CRC Exported Types

Data Structures | Enumerations
CRC Exported Types
CRC

Data Structures

struct CRC_HandleTypeDef
CRC handle Structure definition. More...

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}
CRC HAL State Structure definition. More...

Enumeration Type Documentation

enum HAL_CRC_StateTypeDef

CRC HAL State Structure definition.

Enumerator:
HAL_CRC_STATE_RESET

CRC not yet initialized or disabled

HAL_CRC_STATE_READY

CRC initialized and ready for use

HAL_CRC_STATE_BUSY

CRC internal process is ongoing

HAL_CRC_STATE_TIMEOUT

CRC timeout state

HAL_CRC_STATE_ERROR

CRC error state

Definition at line 66 of file stm32f1xx_hal_crc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CRC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
CRC_HandleTypeDef Struct Reference
CRC Exported Types

CRC handle Structure definition. More...

#include <stm32f1xx_hal_crc.h>

Data Fields

CRC_TypeDef * | Instance
HAL_LockTypeDef | Lock
__IO HAL_CRC_StateTypeDef | State

Detailed Description

CRC handle Structure definition.

Definition at line 79 of file stm32f1xx_hal_crc.h.

Field Documentation

CRC_TypeDef* CRC_HandleTypeDef::Instance

Register base address

Definition at line 81 of file stm32f1xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), and HAL_CRC_Init().

HAL_LockTypeDef CRC_HandleTypeDef::Lock

CRC locking object

Definition at line 83 of file stm32f1xx_hal_crc.h.

Referenced by HAL_CRC_Init().

__IO HAL_CRC_StateTypeDef CRC_HandleTypeDef::State

CRC communication state

Definition at line 85 of file stm32f1xx_hal_crc.h.

Referenced by HAL_CRC_Accumulate(), HAL_CRC_Calculate(), HAL_CRC_DeInit(), HAL_CRC_GetState(), and HAL_CRC_Init().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_crc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CRC Exported Macros

Defines
CRC Exported Macros
CRC

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET))
Resets CRC Data Register.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Stores a 8-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Returns the 8-bit data stored in the Independent Data(ID) register.

Define Documentation

#define __HAL_CRC_DR_RESET ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET))

Resets CRC Data Register.

Parameters:
__HANDLE__,: CRC handle
Return values:
None

Definition at line 111 of file stm32f1xx_hal_crc.h.

Referenced by HAL_CRC_Calculate(), and HAL_CRC_DeInit().

#define __HAL_CRC_GET_IDR ( __HANDLE__ ) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

Returns the 8-bit data stored in the Independent Data(ID) register.

Parameters:
__HANDLE__,: CRC handle
Return values:
8-bit value of the ID register

Definition at line 126 of file stm32f1xx_hal_crc.h.

#define __HAL_CRC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

Reset CRC handle state.

Parameters:
__HANDLE__,: CRC handle
Return values:
None

Definition at line 104 of file stm32f1xx_hal_crc.h.

#define __HAL_CRC_SET_IDR | ( | __HANDLE__,
 |  | __VALUE__
 | ) | (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))

Stores a 8-bit data in the Independent Data(ID) register.

Parameters:
__HANDLE__,: CRC handle
__VALUE__,: 8-bit value to be stored in the ID register
Return values:
None

Definition at line 119 of file stm32f1xx_hal_crc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DAC

DAC
STM32F1xx_HAL_Driver

DAC driver modules. More...

DAC driver modules.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DACEx

DACEx
STM32F1xx_HAL_Driver

DACEx driver module. More...

DACEx driver module.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Private Functions

Functions
DMA Private Functions
DMA

Functions

static void DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.

Function Documentation

static void DMA_SetConfig | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  | [static]

Sets the DMA Transfer parameter.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 864 of file stm32f1xx_hal_dma.c.

References __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, DMA_MEMORY_TO_PERIPH, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::Init, and __DMA_HandleTypeDef::Instance.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
DMA Exported Functions

Initialization and de-initialization functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
             ##### Initialization and de-initialization functions  #####
 ===============================================================================
    [..]
    This section provides functions allowing to initialize the DMA Channel source
    and destination addresses, incrementation and data sizes, transfer direction,
    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
    [..]
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
    reference manual.

Function Documentation

HAL_StatusTypeDef HAL_DMA_DeInit ( DMA_HandleTypeDef * hdma )

DeInitialize the DMA peripheral.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 245 of file stm32f1xx_hal_dma.c.

References __HAL_DMA_DISABLE, assert_param, __DMA_HandleTypeDef::ChannelIndex, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_RESET, __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Init ( DMA_HandleTypeDef * hdma )

Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 161 of file stm32f1xx_hal_dma.c.

References assert_param, __DMA_HandleTypeDef::ChannelIndex, DMA_InitTypeDef::Direction, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Init, __DMA_HandleTypeDef::Instance, IS_DMA_DIRECTION, IS_DMA_MEMORY_DATA_SIZE, IS_DMA_MEMORY_INC_STATE, IS_DMA_MODE, IS_DMA_PERIPHERAL_DATA_SIZE, IS_DMA_PERIPHERAL_INC_STATE, IS_DMA_PRIORITY, __DMA_HandleTypeDef::Lock, DMA_InitTypeDef::MemDataAlignment, DMA_InitTypeDef::MemInc, DMA_InitTypeDef::Mode, DMA_InitTypeDef::PeriphDataAlignment, DMA_InitTypeDef::PeriphInc, DMA_InitTypeDef::Priority, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Input and Output operation functions

Functions
Input and Output operation functions
DMA Exported Functions

Input and Output operation functions. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.

Detailed Description

Input and Output operation functions.

 ===============================================================================
                      #####  IO operation functions  #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Configure the source, destination address and data length and Start DMA transfer
      (+) Configure the source, destination address and data length and
          Start DMA transfer with interrupt
      (+) Abort DMA transfer
      (+) Poll for transfer complete
      (+) Handle DMA interrupt request

Function Documentation

HAL_StatusTypeDef HAL_DMA_Abort ( DMA_HandleTypeDef * hdma )

Abort the DMA Transfer.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 435 of file stm32f1xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __DMA_HandleTypeDef::ChannelIndex, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, HAL_DMA_STATE_READY, and __DMA_HandleTypeDef::State.

Referenced by HAL_ADC_Stop_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_IRDA_Abort(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortTransmit(), HAL_IRDA_DMAStop(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortTransmit(), HAL_SPI_Abort(), HAL_SPI_DMAStop(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_UART_Abort(), HAL_UART_AbortReceive(), HAL_UART_AbortTransmit(), HAL_UART_DMAStop(), HAL_USART_Abort(), and HAL_USART_DMAStop().

HAL_StatusTypeDef HAL_DMA_Abort_IT ( DMA_HandleTypeDef * hdma )

Aborts the DMA Transfer in Interrupt mode.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL status

Definition at line 463 of file stm32f1xx_hal_dma.c.

References __HAL_DMA_CLEAR_FLAG, __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __HAL_DMA_GET_GI_FLAG_INDEX, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), and I2C_ITError().

void HAL_DMA_IRQHandler ( DMA_HandleTypeDef * hdma )

Handles DMA interrupt request.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
None

Definition at line 609 of file stm32f1xx_hal_dma.c.

References __HAL_DMA_CLEAR_FLAG, __HAL_DMA_DISABLE_IT, __HAL_DMA_GET_HT_FLAG_INDEX, __HAL_DMA_GET_TC_FLAG_INDEX, __DMA_HandleTypeDef::ChannelIndex, DMA_FLAG_HT1, DMA_FLAG_TC1, DMA_FLAG_TE1, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_TE, HAL_DMA_STATE_READY, __DMA_HandleTypeDef::Instance, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_PollForTransfer | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | CompleteLevel,
 |  | uint32_t | Timeout
 | ) |  |

Polling for transfer complete.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CompleteLevel,: Specifies the DMA level complete.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 508 of file stm32f1xx_hal_dma.c.

References __HAL_DMA_CLEAR_FLAG, __HAL_DMA_GET_FLAG, __HAL_DMA_GET_HT_FLAG_INDEX, __HAL_DMA_GET_TC_FLAG_INDEX, __HAL_DMA_GET_TE_FLAG_INDEX, __DMA_HandleTypeDef::ChannelIndex, __DMA_HandleTypeDef::DmaBaseAddress, __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NO_XFER, HAL_DMA_ERROR_NOT_SUPPORTED, HAL_DMA_ERROR_TE, HAL_DMA_ERROR_TIMEOUT, HAL_DMA_FULL_TRANSFER, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, HAL_GetTick(), __DMA_HandleTypeDef::Instance, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_RegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID,
 |  | void(*)(DMA_HandleTypeDef *_hdma) | pCallback
 | ) |  |

Register callbacks.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CallbackID,: User Callback identifer a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
pCallback,: pointer to private callbacsk function which has pointer to a DMA_HandleTypeDef structure as parameter.
Return values:
HAL status

Definition at line 699 of file stm32f1xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_DMA_Start | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 338 of file stm32f1xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_ENABLE, assert_param, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, and __DMA_HandleTypeDef::State.

HAL_StatusTypeDef HAL_DMA_Start_IT | ( | DMA_HandleTypeDef * | hdma,
 |  | uint32_t | SrcAddress,
 |  | uint32_t | DstAddress,
 |  | uint32_t | DataLength
 | ) |  |

Start the DMA Transfer with interrupt enabled.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
SrcAddress,: The source memory Buffer address
DstAddress,: The destination memory Buffer address
DataLength,: The length of data to be transferred from source to destination
Return values:
HAL status

Definition at line 381 of file stm32f1xx_hal_dma.c.

References __HAL_DMA_DISABLE, __HAL_DMA_DISABLE_IT, __HAL_DMA_ENABLE, __HAL_DMA_ENABLE_IT, assert_param, DMA_IT_HT, DMA_IT_TC, DMA_IT_TE, DMA_SetConfig(), __DMA_HandleTypeDef::ErrorCode, HAL_DMA_ERROR_NONE, HAL_DMA_STATE_BUSY, HAL_DMA_STATE_READY, IS_DMA_BUFFER_SIZE, __DMA_HandleTypeDef::State, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

HAL_StatusTypeDef HAL_DMA_UnRegisterCallback | ( | DMA_HandleTypeDef * | hdma,
 |  | HAL_DMA_CallbackIDTypeDef | CallbackID
 | ) |  |

UnRegister callbacks.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
CallbackID,: User Callback identifer a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
Return values:
HAL status

Definition at line 750 of file stm32f1xx_hal_dma.c.

References HAL_DMA_STATE_READY, HAL_DMA_XFER_ABORT_CB_ID, HAL_DMA_XFER_ALL_CB_ID, HAL_DMA_XFER_CPLT_CB_ID, HAL_DMA_XFER_ERROR_CB_ID, HAL_DMA_XFER_HALFCPLT_CB_ID, __DMA_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
DMA Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA hande state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Check the DMA state
      (+) Get error code

Function Documentation

uint32_t HAL_DMA_GetError ( DMA_HandleTypeDef * hdma )

Return the DMA error code.

Parameters:
hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
DMA Error Code

Definition at line 838 of file stm32f1xx_hal_dma.c.

References __DMA_HandleTypeDef::ErrorCode.

HAL_DMA_StateTypeDef HAL_DMA_GetState ( DMA_HandleTypeDef * hdma )

Return the DMA hande state.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA Channel.
Return values:
HAL state

Definition at line 826 of file stm32f1xx_hal_dma.c.

References __DMA_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Exported Types

Data Structures | Typedefs | Enumerations
DMA Exported Types
DMA

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
HAL_DMA_XFER_ALL_CB_ID = 0x04U
}
HAL DMA Callback ID structure definition. More...

Typedef Documentation

typedef struct __DMA_HandleTypeDef DMA_HandleTypeDef

DMA handle Structure definition.

Enumeration Type Documentation

enum HAL_DMA_CallbackIDTypeDef

HAL DMA Callback ID structure definition.

Enumerator:
HAL_DMA_XFER_CPLT_CB_ID

Full transfer

HAL_DMA_XFER_HALFCPLT_CB_ID

Half transfer

HAL_DMA_XFER_ERROR_CB_ID

Error

HAL_DMA_XFER_ABORT_CB_ID

Abort

HAL_DMA_XFER_ALL_CB_ID

All

Definition at line 116 of file stm32f1xx_hal_dma.h.

enum HAL_DMA_LevelCompleteTypeDef

HAL DMA Error Code structure definition.

Enumerator:
HAL_DMA_FULL_TRANSFER

Full transfer

HAL_DMA_HALF_TRANSFER

Half Transfer

Definition at line 107 of file stm32f1xx_hal_dma.h.

enum HAL_DMA_StateTypeDef

HAL DMA State structures definition.

Enumerator:
HAL_DMA_STATE_RESET

DMA not yet initialized or disabled

HAL_DMA_STATE_READY

DMA initialized and ready for use

HAL_DMA_STATE_BUSY

DMA process is ongoing

HAL_DMA_STATE_TIMEOUT

DMA timeout state

Definition at line 96 of file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
DMA_InitTypeDef Struct Reference
DMA Exported Types

DMA Configuration Structure definition. More...

#include <stm32f1xx_hal_dma.h>

Data Fields

uint32_t | Direction
uint32_t | PeriphInc
uint32_t | MemInc
uint32_t | PeriphDataAlignment
uint32_t | MemDataAlignment
uint32_t | Mode
uint32_t | Priority

Detailed Description

DMA Configuration Structure definition.

Definition at line 66 of file stm32f1xx_hal_dma.h.

Field Documentation

uint32_t DMA_InitTypeDef::Direction

Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of DMA Data transfer direction

Definition at line 68 of file stm32f1xx_hal_dma.h.

Referenced by DMA_SetConfig(), and HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemDataAlignment

Specifies the Memory data width. This parameter can be a value of DMA Memory data size

Definition at line 81 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::MemInc

Specifies whether the memory address register should be incremented or not. This parameter can be a value of DMA Memory incremented mode

Definition at line 75 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Mode

Specifies the operation mode of the DMAy Channelx. This parameter can be a value of DMA mode

Note:
The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel

Definition at line 84 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphDataAlignment

Specifies the Peripheral data width. This parameter can be a value of DMA Peripheral data size

Definition at line 78 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::PeriphInc

Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of DMA Peripheral incremented mode

Definition at line 72 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

uint32_t DMA_InitTypeDef::Priority

Specifies the software priority for the DMAy Channelx. This parameter can be a value of DMA Priority level

Definition at line 89 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_dma.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: __DMA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__DMA_HandleTypeDef Struct Reference
DMA Exported Types

DMA handle Structure definition. More...

#include <stm32f1xx_hal_dma.h>

Data Fields

DMA_Channel_TypeDef * | Instance
DMA_InitTypeDef Init
HAL_LockTypeDef | Lock
HAL_DMA_StateTypeDef State
void * | Parent
void(* | XferCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferHalfCpltCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferErrorCallback )(struct __DMA_HandleTypeDef *hdma)
void(* | XferAbortCallback )(struct __DMA_HandleTypeDef *hdma)
__IO uint32_t | ErrorCode
DMA_TypeDef * | DmaBaseAddress
uint32_t | ChannelIndex

Detailed Description

DMA handle Structure definition.

Definition at line 129 of file stm32f1xx_hal_dma.h.

Field Documentation

uint32_t __DMA_HandleTypeDef::ChannelIndex

DMA Channel Index

Definition at line 153 of file stm32f1xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

DMA_TypeDef* __DMA_HandleTypeDef::DmaBaseAddress

DMA Channel Base Address

Definition at line 151 of file stm32f1xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_Abort(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

__IO uint32_t __DMA_HandleTypeDef::ErrorCode

DMA Error code

Definition at line 149 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetError(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

DMA_InitTypeDef __DMA_HandleTypeDef::Init

DMA communication parameters

Definition at line 133 of file stm32f1xx_hal_dma.h.

Referenced by DMA_SetConfig(), and HAL_DMA_Init().

DMA_Channel_TypeDef* __DMA_HandleTypeDef::Instance

Register base address

Definition at line 131 of file stm32f1xx_hal_dma.h.

Referenced by DMA_SetConfig(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), USART_DMAReceiveCplt(), and USART_DMATransmitCplt().

HAL_LockTypeDef __DMA_HandleTypeDef::Lock

DMA locking object

Definition at line 135 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

void* __DMA_HandleTypeDef::Parent

Parent object state

Definition at line 139 of file stm32f1xx_hal_dma.h.

HAL_DMA_StateTypeDef __DMA_HandleTypeDef::State

DMA transfer state

Definition at line 137 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_GetState(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_PollForTransfer(), HAL_DMA_RegisterCallback(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), and I2C_ITError().

void(* __DMA_HandleTypeDef::XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer abort callback

Definition at line 147 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Abort_IT(), HAL_DMA_Init(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), I2C_DMAAbort(), I2C_ITError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

void(* __DMA_HandleTypeDef::XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer complete callback

Definition at line 141 of file stm32f1xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)

DMA transfer error callback

Definition at line 145 of file stm32f1xx_hal_dma.h.

Referenced by ADC_DMAConvCplt(), HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

void(* __DMA_HandleTypeDef::XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)

DMA Half transfer complete callback

Definition at line 143 of file stm32f1xx_hal_dma.h.

Referenced by HAL_ADC_Start_DMA(), HAL_ADCEx_MultiModeStart_DMA(), HAL_DMA_Init(), HAL_DMA_IRQHandler(), HAL_DMA_RegisterCallback(), HAL_DMA_Start_IT(), HAL_DMA_UnRegisterCallback(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Transmit_DMA(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit_DMA(), HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), HAL_UART_Receive_DMA(), HAL_UART_Transmit_DMA(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_dma.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Error Code

Defines
DMA Error Code
DMA Exported Constants

Defines

#define | HAL_DMA_ERROR_NONE 0x00000000U
#define | HAL_DMA_ERROR_TE 0x00000001U
#define | HAL_DMA_ERROR_NO_XFER 0x00000004U
#define | HAL_DMA_ERROR_TIMEOUT 0x00000020U
#define | HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U

Define Documentation

#define HAL_DMA_ERROR_NO_XFER 0x00000004U

no ongoing transfer

Definition at line 171 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Abort_IT(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_NONE 0x00000000U

No error

Definition at line 169 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U

Not supported mode

Definition at line 173 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TE 0x00000001U

Transfer error

Definition at line 170 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define HAL_DMA_ERROR_TIMEOUT 0x00000020U

Timeout error

Definition at line 172 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_PollForTransfer().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Data transfer direction

Defines
DMA Data transfer direction
DMA Exported Constants

Defines

#define | DMA_PERIPH_TO_MEMORY 0x00000000U
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)

Define Documentation

#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)

Memory to memory direction

Definition at line 183 of file stm32f1xx_hal_dma.h.

#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)

Memory to peripheral direction

Definition at line 182 of file stm32f1xx_hal_dma.h.

Referenced by DMA_SetConfig().

#define DMA_PERIPH_TO_MEMORY 0x00000000U

Peripheral to memory direction

Definition at line 181 of file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Peripheral incremented mode

Defines
DMA Peripheral incremented mode
DMA Exported Constants

Defines

#define | DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)
#define | DMA_PINC_DISABLE 0x00000000U

Define Documentation

#define DMA_PINC_DISABLE 0x00000000U

Peripheral increment mode Disable

Definition at line 193 of file stm32f1xx_hal_dma.h.

#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)

Peripheral increment mode Enable

Definition at line 192 of file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Memory incremented mode

Defines
DMA Memory incremented mode
DMA Exported Constants

Defines

#define | DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)
#define | DMA_MINC_DISABLE 0x00000000U

Define Documentation

#define DMA_MINC_DISABLE 0x00000000U

Memory increment mode Disable

Definition at line 202 of file stm32f1xx_hal_dma.h.

#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)

Memory increment mode Enable

Definition at line 201 of file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Peripheral data size

Defines
DMA Peripheral data size
DMA Exported Constants

Defines

#define | DMA_PDATAALIGN_BYTE 0x00000000U
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)

Define Documentation

#define DMA_PDATAALIGN_BYTE 0x00000000U

Peripheral data alignment: Byte

Definition at line 210 of file stm32f1xx_hal_dma.h.

#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)

Peripheral data alignment: HalfWord

Definition at line 211 of file stm32f1xx_hal_dma.h.

#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)

Peripheral data alignment: Word

Definition at line 212 of file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Memory data size

Defines
DMA Memory data size
DMA Exported Constants

Defines

#define | DMA_MDATAALIGN_BYTE 0x00000000U
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)

Define Documentation

#define DMA_MDATAALIGN_BYTE 0x00000000U

Memory data alignment: Byte

Definition at line 220 of file stm32f1xx_hal_dma.h.

#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)

Memory data alignment: HalfWord

Definition at line 221 of file stm32f1xx_hal_dma.h.

#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)

Memory data alignment: Word

Definition at line 222 of file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA mode

Defines
DMA mode
DMA Exported Constants

Defines

#define | DMA_NORMAL 0x00000000U
#define | DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)

Define Documentation

#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)

Circular mode

Definition at line 231 of file stm32f1xx_hal_dma.h.

#define DMA_NORMAL 0x00000000U

Normal mode

Definition at line 230 of file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Priority level

Defines
DMA Priority level
DMA Exported Constants

Defines

#define | DMA_PRIORITY_LOW 0x00000000U
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)

Define Documentation

#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)

Priority level : High

Definition at line 241 of file stm32f1xx_hal_dma.h.

#define DMA_PRIORITY_LOW 0x00000000U

Priority level : Low

Definition at line 239 of file stm32f1xx_hal_dma.h.

#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)

Priority level : Medium

Definition at line 240 of file stm32f1xx_hal_dma.h.

#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)

Priority level : Very_High

Definition at line 242 of file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA interrupt enable definitions

Defines
DMA interrupt enable definitions
DMA Exported Constants

Defines

#define | DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)

Define Documentation

#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)

Definition at line 252 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)

Definition at line 251 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)

Definition at line 253 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA flag definitions

Defines
DMA flag definitions
DMA Exported Constants

Defines

#define | DMA_FLAG_GL1 0x00000001U
#define | DMA_FLAG_TC1 0x00000002U
#define | DMA_FLAG_HT1 0x00000004U
#define | DMA_FLAG_TE1 0x00000008U
#define | DMA_FLAG_GL2 0x00000010U
#define | DMA_FLAG_TC2 0x00000020U
#define | DMA_FLAG_HT2 0x00000040U
#define | DMA_FLAG_TE2 0x00000080U
#define | DMA_FLAG_GL3 0x00000100U
#define | DMA_FLAG_TC3 0x00000200U
#define | DMA_FLAG_HT3 0x00000400U
#define | DMA_FLAG_TE3 0x00000800U
#define | DMA_FLAG_GL4 0x00001000U
#define | DMA_FLAG_TC4 0x00002000U
#define | DMA_FLAG_HT4 0x00004000U
#define | DMA_FLAG_TE4 0x00008000U
#define | DMA_FLAG_GL5 0x00010000U
#define | DMA_FLAG_TC5 0x00020000U
#define | DMA_FLAG_HT5 0x00040000U
#define | DMA_FLAG_TE5 0x00080000U
#define | DMA_FLAG_GL6 0x00100000U
#define | DMA_FLAG_TC6 0x00200000U
#define | DMA_FLAG_HT6 0x00400000U
#define | DMA_FLAG_TE6 0x00800000U
#define | DMA_FLAG_GL7 0x01000000U
#define | DMA_FLAG_TC7 0x02000000U
#define | DMA_FLAG_HT7 0x04000000U
#define | DMA_FLAG_TE7 0x08000000U

Define Documentation

#define DMA_FLAG_GL1 0x00000001U

Definition at line 261 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_GL2 0x00000010U

Definition at line 265 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_GL3 0x00000100U

Definition at line 269 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_GL4 0x00001000U

Definition at line 273 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_GL5 0x00010000U

Definition at line 277 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_GL6 0x00100000U

Definition at line 281 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_GL7 0x01000000U

Definition at line 285 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_HT1 0x00000004U

Definition at line 263 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

#define DMA_FLAG_HT2 0x00000040U

Definition at line 267 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_HT3 0x00000400U

Definition at line 271 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_HT4 0x00004000U

Definition at line 275 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_HT5 0x00040000U

Definition at line 279 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_HT6 0x00400000U

Definition at line 283 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_HT7 0x04000000U

Definition at line 287 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TC1 0x00000002U

Definition at line 262 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

#define DMA_FLAG_TC2 0x00000020U

Definition at line 266 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TC3 0x00000200U

Definition at line 270 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TC4 0x00002000U

Definition at line 274 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TC5 0x00020000U

Definition at line 278 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TC6 0x00200000U

Definition at line 282 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TC7 0x02000000U

Definition at line 286 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TE1 0x00000008U

Definition at line 264 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_IRQHandler().

#define DMA_FLAG_TE2 0x00000080U

Definition at line 268 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TE3 0x00000800U

Definition at line 272 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TE4 0x00008000U

Definition at line 276 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TE5 0x00080000U

Definition at line 280 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TE6 0x00800000U

Definition at line 284 of file stm32f1xx_hal_dma.h.

#define DMA_FLAG_TE7 0x08000000U

Definition at line 288 of file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Exported Macros

Defines
DMA Exported Macros
DMA

Defines

#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
Disable the specified DMA Channel.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
Enables the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
Disable the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified DMA Channel interrupt is enabled or not.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Return the number of remaining data units in the current DMA Channel transfer.

Define Documentation

#define __HAL_DMA_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))

Disable the specified DMA Channel.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 321 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_DeInit(), HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define __HAL_DMA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))

Disable the specified DMA Channel interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 348 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Abort(), HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_Start_IT().

#define __HAL_DMA_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))

Enable the specified DMA Channel.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 314 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define __HAL_DMA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))

Enables the specified DMA Channel interrupts.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
None

Definition at line 336 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Start_IT().

#define __HAL_DMA_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNDTR)

Return the number of remaining data units in the current DMA Channel transfer.

Parameters:
__HANDLE__,: DMA handle
Return values:
The number of remaining data units in the current DMA Channel transfer.

Definition at line 367 of file stm32f1xx_hal_dma.h.

Referenced by I2C_Slave_STOPF().

#define __HAL_DMA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified DMA Channel interrupt is enabled or not.

Parameters:
__HANDLE__,: DMA handle
__INTERRUPT__,: specifies the DMA interrupt source to check. This parameter can be one of the following values:
  • DMA_IT_TC: Transfer complete interrupt mask
  • DMA_IT_HT: Half transfer complete interrupt mask
  • DMA_IT_TE: Transfer error interrupt mask
Return values:
The state of DMA_IT (SET or RESET).

Definition at line 360 of file stm32f1xx_hal_dma.h.

#define __HAL_DMA_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

Reset DMA handle state.

Parameters:
__HANDLE__,: DMA handle
Return values:
None

Definition at line 307 of file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Private Macros

Defines
DMA Private Macros
DMA

Defines

#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Define Documentation

#define IS_DMA_BUFFER_SIZE ( SIZE ) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))

Definition at line 431 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Start(), and HAL_DMA_Start_IT().

#define IS_DMA_DIRECTION ( DIRECTION )
Value:
(((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

Definition at line 427 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                       ((SIZE) == DMA_MDATAALIGN_WORD ))

Definition at line 443 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MEMORY_INC_STATE ( STATE )
Value:
(((STATE) == DMA_MINC_ENABLE)  || \
                                        ((STATE) == DMA_MINC_DISABLE))

Definition at line 436 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_MODE ( MODE )
Value:
(((MODE) == DMA_NORMAL )  || \
                           ((MODE) == DMA_CIRCULAR))

Definition at line 447 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_DATA_SIZE ( SIZE )
Value:
(((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                           ((SIZE) == DMA_PDATAALIGN_WORD))

Definition at line 439 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PERIPHERAL_INC_STATE ( STATE )
Value:
(((STATE) == DMA_PINC_ENABLE) || \
                                            ((STATE) == DMA_PINC_DISABLE))

Definition at line 433 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

#define IS_DMA_PRIORITY ( PRIORITY )
Value:
(((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

Definition at line 450 of file stm32f1xx_hal_dma.h.

Referenced by HAL_DMA_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA Low density and Medium density product devices

Defines
DMA Low density and Medium density product devices
DMA Extended Exported Macros

Defines

#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Returns the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
Clear the DMA Channel pending flags.

Define Documentation

#define __HAL_DMA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (DMA1->IFCR = (__FLAG__))

Clear the DMA Channel pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx: Transfer complete flag
  • DMA_FLAG_HTx: Half transfer complete flag
  • DMA_FLAG_TEx: Transfer error flag
  • DMA_FLAG_GLx: Global interrupt flag Where x can be 1_7 to select the DMA Channel flag.
Return values:
None

Definition at line 268 of file stm32f1xx_hal_dma_ex.h.

Referenced by HAL_DMA_Abort_IT(), HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define __HAL_DMA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (DMA1->ISR & (__FLAG__))

Get the DMA Channel pending flags.

Parameters:
__HANDLE__,: DMA handle
__FLAG__,: Get the specified flag. This parameter can be any combination of the following values:
  • DMA_FLAG_TCx: Transfer complete flag
  • DMA_FLAG_HTx: Half transfer complete flag
  • DMA_FLAG_TEx: Transfer error flag
  • DMA_FLAG_GLx: Global interrupt flag Where x can be 1_7 to select the DMA Channel flag.
Return values:
The state of FLAG (SET or RESET).

Definition at line 254 of file stm32f1xx_hal_dma_ex.h.

Referenced by HAL_DMA_PollForTransfer().

#define __HAL_DMA_GET_GI_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
   DMA_FLAG_GL7)

Return the current DMA Channel Global interrupt flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer error flag index.

Definition at line 232 of file stm32f1xx_hal_dma_ex.h.

Referenced by HAL_DMA_Abort_IT().

#define __HAL_DMA_GET_HT_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
   DMA_FLAG_HT7)

Return the current DMA Channel half transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified half transfer complete flag index.

Definition at line 204 of file stm32f1xx_hal_dma_ex.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define __HAL_DMA_GET_TC_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
   DMA_FLAG_TC7)

Returns the current DMA Channel transfer complete flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer complete flag index.

Definition at line 190 of file stm32f1xx_hal_dma_ex.h.

Referenced by HAL_DMA_IRQHandler(), and HAL_DMA_PollForTransfer().

#define __HAL_DMA_GET_TE_FLAG_INDEX ( __HANDLE__ )
Value:
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
   DMA_FLAG_TE7)

Return the current DMA Channel transfer error flag.

Parameters:
__HANDLE__,: DMA handle
Return values:
The specified transfer error flag index.

Definition at line 218 of file stm32f1xx_hal_dma_ex.h.

Referenced by HAL_DMA_PollForTransfer().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH Private Constants

Defines
FLASH Private Constants
FLASH

Defines

#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */

Define Documentation

#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */

Definition at line 60 of file stm32f1xx_hal_flash.h.

Referenced by FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), HAL_FLASH_Program(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_OBErase().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH Private Macros

Defines
FLASH Private Macros
FLASH

Defines

#define | IS_FLASH_TYPEPROGRAM(VALUE)
#define | IS_FLASH_LATENCY(__LATENCY__)

Define Documentation

#define IS_FLASH_LATENCY ( __LATENCY__ )
Value:
(((__LATENCY__) == FLASH_LATENCY_0) || \
                                       ((__LATENCY__) == FLASH_LATENCY_1) || \
                                       ((__LATENCY__) == FLASH_LATENCY_2))

Definition at line 74 of file stm32f1xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_FLASH_TYPEPROGRAM ( VALUE )
Value:
(((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
                                      ((VALUE) == FLASH_TYPEPROGRAM_WORD)     || \
                                      ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))

Definition at line 69 of file stm32f1xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH Private Variables

Variables
FLASH Private Variables
FLASH

Variables

FLASH_ProcessTypeDef pFlash
FLASH_ProcessTypeDef pFlash

Variable Documentation

FLASH_ProcessTypeDef pFlash

Definition at line 139 of file stm32f1xx_hal_flash.c.

FLASH_ProcessTypeDef pFlash

Definition at line 139 of file stm32f1xx_hal_flash.c.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH Private Functions

Functions
FLASH Private Functions
FLASH

Functions

static void | FLASH_Program_HalfWord (uint32_t Address, uint16_t Data)
Program a half-word (16-bit) at a specified address.
static void | FLASH_SetErrorCode (void)
Set the specific FLASH error flag.
void | FLASH_PageErase (uint32_t PageAddress)
Erase the specified FLASH memory page.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Function Documentation

void FLASH_PageErase ( uint32_t PageAddress )

Erase the specified FLASH memory page.

Parameters:
PageAddress FLASH page to erase The value of this parameter depend on device used within the same series
Return values:
None

Definition at line 1103 of file stm32f1xx_hal_flash_ex.c.

References FLASH_ProcessTypeDef::ErrorCode, and HAL_FLASH_ERROR_NONE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static void FLASH_Program_HalfWord | ( | uint32_t | Address,
 |  | uint16_t | Data
 | ) |  | [static]

Program a half-word (16-bit) at a specified address.

Parameters:
Address | specify the address to be programmed.
Data | specify the data to be programmed.
Return values:
None

Definition at line 812 of file stm32f1xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode, and HAL_FLASH_ERROR_NONE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

static void FLASH_SetErrorCode ( void ) [static]

Set the specific FLASH error flag.

Return values:
None

Definition at line 929 of file stm32f1xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::ErrorCode, FLASH_FLAG_OPTVERR, FLASH_FLAG_PGERR, FLASH_FLAG_WRPERR, HAL_FLASH_ERROR_OPTV, HAL_FLASH_ERROR_PROG, and HAL_FLASH_ERROR_WRP.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

HAL_StatusTypeDef FLASH_WaitForLastOperation ( uint32_t Timeout )

Wait for a FLASH operation to complete.

Parameters:
Timeout maximum flash operation timeout
Return values:
HAL Status

Definition at line 841 of file stm32f1xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_GET_FLAG, FLASH_FLAG_BSY, FLASH_FLAG_EOP, FLASH_FLAG_OPTVERR, FLASH_FLAG_PGERR, FLASH_FLAG_WRPERR, FLASH_SetErrorCode(), and HAL_GetTick().

Referenced by FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), HAL_FLASH_Program(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_OBErase().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Programming operation functions

Functions
Programming operation functions
FLASH Exported Functions

Programming operation functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.

Detailed Description

Programming operation functions.

Function Documentation

          void HAL_FLASH_EndOfOperationCallback
          (
          uint32_t
          ReturnValue )

FLASH end of operation interrupt callback.

Parameters:

ReturnValue,: The value saved in this parameter depends on the ongoing procedure

  • Mass Erase: No return value expected
    •

  • Pages Erase: Address of the page which has been erased (if 0xFFFFFFFF, it means that all the selected pages have been erased)
    •

  • Program: Address which was selected for data program
    •

Return values:

none

Definition at line 624 of file stm32f1xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

          void HAL_FLASH_IRQHandler
          (
          void
           )

This function handles FLASH interrupt request.

Return values:

None

Definition at line 350 of file stm32f1xx_hal_flash.c.

References __HAL_FLASH_CLEAR_FLAG, __HAL_FLASH_DISABLE_IT, __HAL_FLASH_GET_FLAG, FLASH_ProcessTypeDef::Address, FLASH_ProcessTypeDef::Data, FLASH_ProcessTypeDef::DataRemaining, FLASH_FLAG_EOP, FLASH_FLAG_PGERR, FLASH_FLAG_WRPERR, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_PAGE_SIZE, FLASH_PageErase(), FLASH_PROC_MASSERASE, FLASH_PROC_NONE, FLASH_PROC_PAGEERASE, FLASH_PROC_PROGRAMHALFWORD, FLASH_PROC_PROGRAMWORD, FLASH_Program_HalfWord(), FLASH_SetErrorCode(), HAL_FLASH_EndOfOperationCallback(), HAL_FLASH_OperationErrorCallback(), and FLASH_ProcessTypeDef::ProcedureOnGoing.

          void HAL_FLASH_OperationErrorCallback
          (
          uint32_t
          ReturnValue )

FLASH operation error interrupt callback.

Parameters:

ReturnValue,: The value saved in this parameter depends on the ongoing procedure

  • Mass Erase: No return value expected
    •

  • Pages Erase: Address of the page which returned an error
    •

  • Program: Address which was selected for data program
    •

Return values:

none

Definition at line 642 of file stm32f1xx_hal_flash.c.

Referenced by HAL_FLASH_IRQHandler().

HAL_StatusTypeDef HAL_FLASH_Program | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program halfword, word or double word at a specified address.

Note:
The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface The function HAL_FLASH_Lock() should be called after to lock the FLASH interface

If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.

FLASH should be previously erased before new programmation (only exception to this is when 0x0000 is programmed)

Parameters:

TypeProgram,: Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program

Address,: Specifies the address to be programmed.

Data,: Specifies the data to be programmed

Return values:

HAL_StatusTypeDef HAL Status

Definition at line 186 of file stm32f1xx_hal_flash.c.

References assert_param, FLASH_Program_HalfWord(), FLASH_TIMEOUT_VALUE, FLASH_TYPEPROGRAM_HALFWORD, FLASH_TYPEPROGRAM_WORD, FLASH_WaitForLastOperation(), IS_FLASH_PROGRAM_ADDRESS, and IS_FLASH_TYPEPROGRAM.

HAL_StatusTypeDef HAL_FLASH_Program_IT | ( | uint32_t | TypeProgram,
 |  | uint32_t | Address,
 |  | uint64_t | Data
 | ) |  |

Program halfword, word or double word at a specified address with interrupt enabled.

Note:
The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface The function HAL_FLASH_Lock() should be called after to lock the FLASH interface

If an erase and a program operations are requested simultaneously, the erase operation is performed before the program one.

Parameters:

TypeProgram,: Indicate the way to program at a specified address. This parameter can be a value of FLASH Type Program

Address,: Specifies the address to be programmed.

Data,: Specifies the data to be programmed

Return values:

HAL_StatusTypeDef HAL Status

Definition at line 285 of file stm32f1xx_hal_flash.c.

References __HAL_FLASH_ENABLE_IT, FLASH_ProcessTypeDef::Address, assert_param, FLASH_ProcessTypeDef::Data, FLASH_ProcessTypeDef::DataRemaining, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_PROC_NONE, FLASH_PROC_PROGRAMDOUBLEWORD, FLASH_PROC_PROGRAMHALFWORD, FLASH_PROC_PROGRAMWORD, FLASH_Program_HalfWord(), FLASH_TYPEPROGRAM_HALFWORD, FLASH_TYPEPROGRAM_WORD, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_TYPEPROGRAM, and FLASH_ProcessTypeDef::ProcedureOnGoing.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by
  doxygen
 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
FLASH Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    memory operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASH_Lock ( void )

Locks the FLASH control register access.

Return values:
HAL Status

Definition at line 708 of file stm32f1xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Launch ( void )

Launch the option byte loading.

Note:
This function will reset automatically the MCU.
Return values:
HAL Status

Definition at line 758 of file stm32f1xx_hal_flash.c.

References HAL_NVIC_SystemReset().

HAL_StatusTypeDef HAL_FLASH_OB_Lock ( void )

Lock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 745 of file stm32f1xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_OB_Unlock ( void )

Unlock the FLASH Option Control Registers access.

Return values:
HAL Status

Definition at line 725 of file stm32f1xx_hal_flash.c.

HAL_StatusTypeDef HAL_FLASH_Unlock ( void )

Unlock the FLASH control register access.

Return values:
HAL Status

Definition at line 675 of file stm32f1xx_hal_flash.c.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral errors functions

Functions
Peripheral errors functions
FLASH Exported Functions

Peripheral errors functions. More...

Functions

uint32_t HAL_FLASH_GetError (void)
Get the specific FLASH error flag.

Detailed Description

Peripheral errors functions.

 ===============================================================================
                      ##### Peripheral Errors functions #####
 ===============================================================================
    [..]
    This subsection permit to get in run-time errors of  the FLASH peripheral.

Function Documentation

uint32_t HAL_FLASH_GetError ( void )

Get the specific FLASH error flag.

Return values:
FLASH_ErrorCode The returned value can be: FLASH Error Codes

Definition at line 789 of file stm32f1xx_hal_flash.c.

References FLASH_ProcessTypeDef::ErrorCode.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH Exported Types

Data Structures | Enumerations
FLASH Exported Types
FLASH

Data Structures

struct FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0U, FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_MASSERASE = 2U, FLASH_PROC_PROGRAMHALFWORD = 3U,
FLASH_PROC_PROGRAMWORD = 4U, FLASH_PROC_PROGRAMDOUBLEWORD = 5U
}
FLASH Procedure structure definition. More...

Enumeration Type Documentation

enum FLASH_ProcedureTypeDef

FLASH Procedure structure definition.

Enumerator:
FLASH_PROC_NONE
FLASH_PROC_PAGEERASE
FLASH_PROC_MASSERASE
FLASH_PROC_PROGRAMHALFWORD
FLASH_PROC_PROGRAMWORD
FLASH_PROC_PROGRAMDOUBLEWORD

Definition at line 93 of file stm32f1xx_hal_flash.h.

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STM32F103xB HAL User Manual: FLASH_ProcessTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_ProcessTypeDef Struct Reference
FLASH Exported Types

FLASH handle Structure definition. More...

#include <stm32f1xx_hal_flash.h>

Data Fields

__IO FLASH_ProcedureTypeDef | ProcedureOnGoing
__IO uint32_t | DataRemaining
__IO uint32_t | Address
__IO uint64_t | Data
HAL_LockTypeDef | Lock
__IO uint32_t | ErrorCode

Detailed Description

FLASH handle Structure definition.

Definition at line 106 of file stm32f1xx_hal_flash.h.

Field Documentation

__IO uint32_t FLASH_ProcessTypeDef::Address

Internal variable to save address selected for program or erase

Definition at line 112 of file stm32f1xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

__IO uint64_t FLASH_ProcessTypeDef::Data

Internal variable to save data to be programmed

Definition at line 114 of file stm32f1xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASH_Program_IT().

__IO uint32_t FLASH_ProcessTypeDef::DataRemaining

Internal variable to save the remaining pages to erase or half-word to program in IT context

Definition at line 110 of file stm32f1xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

__IO uint32_t FLASH_ProcessTypeDef::ErrorCode

FLASH error code This parameter can be a value of FLASH Error Codes

Definition at line 118 of file stm32f1xx_hal_flash.h.

Referenced by FLASH_MassErase(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), FLASH_PageErase(), FLASH_Program_HalfWord(), FLASH_SetErrorCode(), HAL_FLASH_GetError(), and HAL_FLASHEx_OBErase().

HAL_LockTypeDef FLASH_ProcessTypeDef::Lock

FLASH locking object

Definition at line 116 of file stm32f1xx_hal_flash.h.

__IO FLASH_ProcedureTypeDef FLASH_ProcessTypeDef::ProcedureOnGoing

Internal variable to indicate which procedure is ongoing or not in IT context

Definition at line 108 of file stm32f1xx_hal_flash.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_flash.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH Error Codes

Defines
FLASH Error Codes
FLASH Exported Constants

Defines

#define | HAL_FLASH_ERROR_NONE 0x00U
#define | HAL_FLASH_ERROR_PROG 0x01U
#define | HAL_FLASH_ERROR_WRP 0x02U
#define | HAL_FLASH_ERROR_OPTV 0x04U

Define Documentation

#define HAL_FLASH_ERROR_NONE 0x00U

No error

Definition at line 135 of file stm32f1xx_hal_flash.h.

Referenced by FLASH_MassErase(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), FLASH_PageErase(), FLASH_Program_HalfWord(), and HAL_FLASHEx_OBErase().

#define HAL_FLASH_ERROR_OPTV 0x04U

Option validity error

Definition at line 138 of file stm32f1xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_PROG 0x01U

Programming error

Definition at line 136 of file stm32f1xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

#define HAL_FLASH_ERROR_WRP 0x02U

Write protection error

Definition at line 137 of file stm32f1xx_hal_flash.h.

Referenced by FLASH_SetErrorCode().

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STM32F103xB HAL User Manual: FLASH Type Program

Defines
FLASH Type Program
FLASH Exported Constants

Defines

#define | FLASH_TYPEPROGRAM_HALFWORD 0x01U
#define | FLASH_TYPEPROGRAM_WORD 0x02U
#define | FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U

Define Documentation

#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U

Program a double word (64-bit) at a specified address

Definition at line 149 of file stm32f1xx_hal_flash.h.

#define FLASH_TYPEPROGRAM_HALFWORD 0x01U

Program a half-word (16-bit) at a specified address.

Definition at line 147 of file stm32f1xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

#define FLASH_TYPEPROGRAM_WORD 0x02U

Program a word (32-bit) at a specified address.

Definition at line 148 of file stm32f1xx_hal_flash.h.

Referenced by HAL_FLASH_Program(), and HAL_FLASH_Program_IT().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Constants

Defines

#define | FLASH_LATENCY_0 0x00000000U
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

Define Documentation

#define FLASH_LATENCY_0 0x00000000U

FLASH Zero Latency cycle

Definition at line 159 of file stm32f1xx_hal_flash.h.

Referenced by HAL_RCC_GetClockConfig().

#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0

FLASH One Latency cycle

Definition at line 160 of file stm32f1xx_hal_flash.h.

#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

FLASH Two Latency cycles

Definition at line 161 of file stm32f1xx_hal_flash.h.

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STM32F103xB HAL User Manual: FLASH Half Cycle

Defines
FLASH Half Cycle
FLASH Exported Macros

macros to handle FLASH half cycle More...

Defines

#define | __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
Enable the FLASH half cycle access.
#define | __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
Disable the FLASH half cycle access.

Detailed Description

macros to handle FLASH half cycle

Define Documentation

#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE ( ) (FLASH->ACR &= (~FLASH_ACR_HLFCYA))

Disable the FLASH half cycle access.

Note:
half cycle access can only be used with a low-frequency clock of less than 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
Return values:
None

Definition at line 208 of file stm32f1xx_hal_flash.h.

#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE ( ) (FLASH->ACR |= FLASH_ACR_HLFCYA)

Enable the FLASH half cycle access.

Note:
half cycle access can only be used with a low-frequency clock of less than 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
Return values:
None

Definition at line 200 of file stm32f1xx_hal_flash.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH Latency

Defines
FLASH Latency
FLASH Exported Macros

macros to handle FLASH Latency More...

Defines

#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.

Detailed Description

macros to handle FLASH Latency

Define Documentation

#define __HAL_FLASH_GET_LATENCY ( ) (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))

Get the FLASH Latency.

Return values:
FLASH Latency The value of this parameter depend on device used within the same series

Definition at line 234 of file stm32f1xx_hal_flash.h.

#define __HAL_FLASH_SET_LATENCY ( __LATENCY__ ) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))

Set the FLASH Latency.

Parameters:
__LATENCY__ FLASH Latency The value of this parameter depend on device used within the same series
Return values:
None

Definition at line 226 of file stm32f1xx_hal_flash.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASH Prefetch

Defines
FLASH Prefetch
FLASH Exported Macros

macros to handle FLASH Prefetch buffer More...

Defines

#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
Disable the FLASH prefetch buffer.

Detailed Description

macros to handle FLASH Prefetch buffer

Define Documentation

#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE ( ) (FLASH->ACR &= (~FLASH_ACR_PRFTBE))

Disable the FLASH prefetch buffer.

Return values:
None

Definition at line 255 of file stm32f1xx_hal_flash.h.

#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE ( ) (FLASH->ACR |= FLASH_ACR_PRFTBE)

Enable the FLASH prefetch buffer.

Return values:
None

Definition at line 249 of file stm32f1xx_hal_flash.h.

Referenced by HAL_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASHEx Private Constants

Defines
FLASHEx Private Constants
FLASHEx

Defines

#define | FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos
#define | FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos
#define | FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos
#define | FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
#define | OBR_REG_INDEX 1U
#define | SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))

Define Documentation

#define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos

Definition at line 94 of file stm32f1xx_hal_flash_ex.c.

Referenced by FLASH_OB_GetUser().

#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos

Definition at line 95 of file stm32f1xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetUserData().

#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos

Definition at line 96 of file stm32f1xx_hal_flash_ex.c.

Referenced by HAL_FLASHEx_OBGetUserData().

#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U

Definition at line 61 of file stm32f1xx_hal_flash_ex.h.

#define OBR_REG_INDEX 1U

Definition at line 62 of file stm32f1xx_hal_flash_ex.h.

#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))

Definition at line 63 of file stm32f1xx_hal_flash_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASHEx Private Macros

Defines
FLASHEx Private Macros
FLASHEx

Defines

#define | IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define | IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
#define | IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
#define | IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
#define | IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)
#define | IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#define | IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS)

Define Documentation

#define IS_FLASH_BANK ( BANK ) (((BANK) == FLASH_BANK_1))

Definition at line 134 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_MassErase().

#define IS_FLASH_NB_PAGES | ( | ADDRESS,
 |  | NBPAGES
 | ) |
Value:
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
                                           (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
                                           ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))

Definition at line 101 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_PROGRAM_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
                                           ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
                                           ((ADDRESS) <= 0x0800FFFF) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
                                           ((ADDRESS) <= 0x08007FFF) :  ((ADDRESS) <= 0x08003FFFU)))))

Definition at line 146 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_FLASH_TYPEERASE ( VALUE ) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))

Definition at line 73 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define IS_OB_DATA_ADDRESS ( ADDRESS ) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))

Definition at line 81 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_ProgramData().

#define IS_OB_IWDG_SOURCE ( SOURCE ) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

Definition at line 83 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_RDP_LEVEL ( LEVEL ) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))

Definition at line 79 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_RDP_LevelConfig().

#define IS_OB_STDBY_SOURCE ( SOURCE ) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))

Definition at line 87 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_STOP_SOURCE ( SOURCE ) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))

Definition at line 85 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define IS_OB_WRP ( PAGE ) (((PAGE) != 0x0000000U))

Definition at line 127 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define IS_OPTIONBYTE ( VALUE ) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))

Definition at line 75 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define IS_WRPSTATE ( VALUE ) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))

Definition at line 77 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASHEx Private Functions

Functions
FLASHEx Private Functions
FLASHEx

Functions

static void | FLASH_MassErase (uint32_t Banks)
Full erase of FLASH memory Bank.
void | FLASH_PageErase (uint32_t PageAddress)
Erase the specified FLASH memory page.
static HAL_StatusTypeDef | FLASH_OB_EnableWRP (uint32_t WriteProtectPage)
Enable the write protection of the desired pages.
static HAL_StatusTypeDef | FLASH_OB_DisableWRP (uint32_t WriteProtectPage)
Disable the write protection of the desired pages.
static HAL_StatusTypeDef | FLASH_OB_RDP_LevelConfig (uint8_t ReadProtectLevel)
Set the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint8_t UserConfig)
Program the FLASH User Option Byte.
static HAL_StatusTypeDef | FLASH_OB_ProgramData (uint32_t Address, uint8_t Data)
Programs a half word at a specified Option Byte Data address.
static uint32_t | FLASH_OB_GetWRP (void)
Return the FLASH Write Protection Option Bytes value.
static uint32_t | FLASH_OB_GetRDP (void)
Returns the FLASH Read Protection level.
static uint8_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.

Function Documentation

static void FLASH_MassErase ( uint32_t Banks ) [static]

Full erase of FLASH memory Bank.

Parameters:
Banks Banks to be erased This parameter can be one of the following values:
  • FLASH_BANK_1 Bank1 to be erased
Return values:
None

Definition at line 613 of file stm32f1xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, HAL_FLASH_ERROR_NONE, and IS_FLASH_BANK.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

static HAL_StatusTypeDef FLASH_OB_DisableWRP ( uint32_t WriteProtectPage ) [static]

Disable the write protection of the desired pages.

Note:
An option byte erase is done automatically in this function.
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase the flash page i if debug features are connected or boot code is executed in RAM, even if nWRPi = 1
Parameters:
WriteProtectPage specifies the page(s) to be write unprotected. The value of this parameter depend on device used within the same series
Return values:
HAL status

Definition at line 781 of file stm32f1xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_GetWRP(), FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, HAL_FLASHEx_OBErase(), IS_OB_WRP, OB_WRP_PAGES0TO31MASK, OB_WRP_PAGES32TO63MASK, OB_WRP_PAGES64TO95MASK, and OB_WRP_PAGES96TO127MASK.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_EnableWRP ( uint32_t WriteProtectPage ) [static]

Enable the write protection of the desired pages.

Note:
An option byte erase is done automatically in this function.
When the memory read protection level is selected (RDP level = 1), it is not possible to program or erase the flash page i if debug features are connected or boot code is executed in RAM, even if nWRPi = 1
Parameters:
WriteProtectPage specifies the page(s) to be write protected. The value of this parameter depend on device used within the same series
Return values:
HAL status

Definition at line 658 of file stm32f1xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_GetWRP(), FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, HAL_FLASHEx_OBErase(), IS_OB_WRP, OB_WRP_PAGES0TO31MASK, OB_WRP_PAGES32TO63MASK, OB_WRP_PAGES64TO95MASK, and OB_WRP_PAGES96TO127MASK.

Referenced by HAL_FLASHEx_OBProgram().

static uint32_t FLASH_OB_GetRDP ( void ) [static]

Returns the FLASH Read Protection level.

Return values:
FLASH RDP level This parameter can be one of the following values:
  • OB_RDP_LEVEL_0 No protection
  • OB_RDP_LEVEL_1 Read protection of the memory

Definition at line 1048 of file stm32f1xx_hal_flash_ex.c.

References OB_RDP_LEVEL_0, and OB_RDP_LEVEL_1.

Referenced by HAL_FLASHEx_OBErase(), and HAL_FLASHEx_OBGetConfig().

static uint8_t FLASH_OB_GetUser ( void ) [static]

Return the FLASH User Option Byte value.

Return values:
The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2), FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG .

Definition at line 1074 of file stm32f1xx_hal_flash_ex.c.

References FLASH_POSITION_IWDGSW_BIT.

Referenced by HAL_FLASHEx_OBGetConfig().

static uint32_t FLASH_OB_GetWRP ( void ) [static]

Return the FLASH Write Protection Option Bytes value.

Return values:
The FLASH Write Protection Option Bytes value

Definition at line 1035 of file stm32f1xx_hal_flash_ex.c.

Referenced by FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), and HAL_FLASHEx_OBGetConfig().

static HAL_StatusTypeDef FLASH_OB_ProgramData | ( | uint32_t | Address,
 |  | uint8_t | Data
 | ) |  | [static]

Programs a half word at a specified Option Byte Data address.

Note:
The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes (system reset will occur) Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
Parameters:
Address | specifies the address to be programmed. This parameter can be 0x1FFFF804 or 0x1FFFF806.
Data | specifies the data to be programmed.
Return values:
HAL status

Definition at line 1002 of file stm32f1xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, and IS_OB_DATA_ADDRESS.

Referenced by HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig ( uint8_t ReadProtectLevel ) [static]

Set the read protection level.

Parameters:
ReadProtectLevel specifies the read protection level. This parameter can be one of the following values:
  • OB_RDP_LEVEL_0 No protection
  • OB_RDP_LEVEL_1 Read protection of the memory
Return values:
HAL status

Definition at line 900 of file stm32f1xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, and IS_OB_RDP_LEVEL.

Referenced by HAL_FLASHEx_OBErase(), and HAL_FLASHEx_OBProgram().

static HAL_StatusTypeDef FLASH_OB_UserConfig ( uint8_t UserConfig ) [static]

Program the FLASH User Option Byte.

Note:
Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
Parameters:
UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2), FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4). And BFBF2(Bit5) for STM32F101xG and STM32F103xG .
Return values:
HAL status

Definition at line 951 of file stm32f1xx_hal_flash_ex.c.

References assert_param, FLASH_ProcessTypeDef::ErrorCode, FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, IS_OB_IWDG_SOURCE, IS_OB_STDBY_SOURCE, IS_OB_STOP_SOURCE, OB_IWDG_SW, OB_STDBY_NO_RST, and OB_STOP_NO_RST.

Referenced by HAL_FLASHEx_OBProgram().

void FLASH_PageErase ( uint32_t PageAddress )

Erase the specified FLASH memory page.

Parameters:
PageAddress FLASH page to erase The value of this parameter depend on device used within the same series
Return values:
None

Definition at line 1103 of file stm32f1xx_hal_flash_ex.c.

References FLASH_ProcessTypeDef::ErrorCode, and HAL_FLASH_ERROR_NONE.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASHEx Memory Erasing functions

Functions
FLASHEx Memory Erasing functions
FLASHEx Exported Functions

FLASH Memory Erasing functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.

Detailed Description

FLASH Memory Erasing functions.

  ==============================================================================
                ##### FLASH Erasing Programming functions #####
  ==============================================================================

    [..] The FLASH Memory Erasing functions, includes the following functions:
    (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
    (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
        is called with parameter 0xFFFFFFFF

    [..] Any operation of erase should follow these steps:
    (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
        program memory access.
    (#) Call the desired function to erase page.
    (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
       (recommended to protect the FLASH memory against possible unwanted operation).

Function Documentation

HAL_StatusTypeDef HAL_FLASHEx_Erase | ( | FLASH_EraseInitTypeDef * | pEraseInit,
 |  | uint32_t * | PageError
 | ) |  |

Perform a mass erase or erase the specified FLASH memory pages.

Note:
To correctly run this function, the HAL_FLASH_Unlock() function must be called before. Call the HAL_FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation)
Parameters:
[in] | pEraseInit | pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
[out] | PageError | pointer to variable that contains the configuration information on faulty page in case of error (0xFFFFFFFF means that all the pages have been correctly erased)
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 177 of file stm32f1xx_hal_flash_ex.c.

References assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_BANK_1, FLASH_MassErase(), FLASH_PAGE_SIZE, FLASH_PageErase(), FLASH_TIMEOUT_VALUE, FLASH_TYPEERASE_MASSERASE, FLASH_WaitForLastOperation(), IS_FLASH_NB_PAGES, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_EraseInitTypeDef::PageAddress, and FLASH_EraseInitTypeDef::TypeErase.

HAL_StatusTypeDef HAL_FLASHEx_Erase_IT ( FLASH_EraseInitTypeDef * pEraseInit )

Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.

Note:
To correctly run this function, the HAL_FLASH_Unlock() function must be called before. Call the HAL_FLASH_Lock() to disable the flash memory access (recommended to protect the FLASH memory against possible unwanted operation)
Parameters:
pEraseInit pointer to an FLASH_EraseInitTypeDef structure that contains the configuration information for the erasing.
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 337 of file stm32f1xx_hal_flash_ex.c.

References __HAL_FLASH_ENABLE_IT, FLASH_ProcessTypeDef::Address, assert_param, FLASH_EraseInitTypeDef::Banks, FLASH_ProcessTypeDef::DataRemaining, FLASH_IT_EOP, FLASH_IT_ERR, FLASH_MassErase(), FLASH_PageErase(), FLASH_PROC_MASSERASE, FLASH_PROC_NONE, FLASH_PROC_PAGEERASE, FLASH_TYPEERASE_MASSERASE, IS_FLASH_NB_PAGES, IS_FLASH_PROGRAM_ADDRESS, IS_FLASH_TYPEERASE, FLASH_EraseInitTypeDef::NbPages, FLASH_EraseInitTypeDef::PageAddress, FLASH_ProcessTypeDef::ProcedureOnGoing, and FLASH_EraseInitTypeDef::TypeErase.

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STM32F103xB HAL User Manual: Option Bytes Programming functions

Functions
Option Bytes Programming functions
FLASHEx Exported Functions

Option Bytes Programming functions. More...

Functions

HAL_StatusTypeDef | HAL_FLASHEx_OBErase (void)
Erases the FLASH option bytes.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
uint32_t | HAL_FLASHEx_OBGetUserData (uint32_t DATAAdress)
Get the Option byte user data.

Detailed Description

Option Bytes Programming functions.

  ==============================================================================
                ##### Option Bytes Programming functions #####
  ==============================================================================
    [..]
    This subsection provides a set of functions allowing to control the FLASH
    option bytes operations.

Function Documentation

HAL_StatusTypeDef HAL_FLASHEx_OBErase ( void )

Erases the FLASH option bytes.

Note:
This functions erases all option bytes except the Read protection (RDP). The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes (system reset will occur)
Return values:
HAL status

Definition at line 415 of file stm32f1xx_hal_flash_ex.c.

References FLASH_ProcessTypeDef::ErrorCode, FLASH_OB_GetRDP(), FLASH_OB_RDP_LevelConfig(), FLASH_TIMEOUT_VALUE, FLASH_WaitForLastOperation(), HAL_FLASH_ERROR_NONE, and OB_RDP_LEVEL_0.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

void HAL_FLASHEx_OBGetConfig ( FLASH_OBProgramInitTypeDef * pOBInit )

Get the Option byte configuration.

Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
None

Definition at line 545 of file stm32f1xx_hal_flash_ex.c.

References FLASH_OB_GetRDP(), FLASH_OB_GetUser(), FLASH_OB_GetWRP(), OPTIONBYTE_RDP, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::USERConfig, and FLASH_OBProgramInitTypeDef::WRPPage.

uint32_t HAL_FLASHEx_OBGetUserData ( uint32_t DATAAdress )

Get the Option byte user data.

Parameters:
DATAAdress Address of the option byte DATA This parameter can be one of the following values:
  • OB_DATA_ADDRESS_DATA0
  • OB_DATA_ADDRESS_DATA1
Return values:
Value programmed in USER data

Definition at line 567 of file stm32f1xx_hal_flash_ex.c.

References FLASH_POSITION_OB_USERDATA0_BIT, FLASH_POSITION_OB_USERDATA1_BIT, and OB_DATA_ADDRESS_DATA0.

HAL_StatusTypeDef HAL_FLASHEx_OBProgram ( FLASH_OBProgramInitTypeDef * pOBInit )

Program option bytes.

Note:
The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface The function HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes The function HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes (system reset will occur)
Parameters:
pOBInit pointer to an FLASH_OBInitStruct structure that contains the configuration information for the programming.
Return values:
HAL_StatusTypeDef HAL Status

Definition at line 464 of file stm32f1xx_hal_flash_ex.c.

References assert_param, FLASH_OBProgramInitTypeDef::DATAAddress, FLASH_OBProgramInitTypeDef::DATAData, FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), IS_OPTIONBYTE, IS_WRPSTATE, OB_WRPSTATE_ENABLE, OPTIONBYTE_DATA, OPTIONBYTE_RDP, OPTIONBYTE_USER, OPTIONBYTE_WRP, FLASH_OBProgramInitTypeDef::OptionType, FLASH_OBProgramInitTypeDef::RDPLevel, FLASH_OBProgramInitTypeDef::USERConfig, FLASH_OBProgramInitTypeDef::WRPPage, and FLASH_OBProgramInitTypeDef::WRPState.

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STM32F103xB HAL User Manual: FLASH_EraseInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_EraseInitTypeDef Struct Reference
FLASHEx Exported Types

FLASH Erase structure definition. More...

#include <stm32f1xx_hal_flash_ex.h>

Data Fields

uint32_t | TypeErase
uint32_t | Banks
uint32_t | PageAddress
uint32_t | NbPages

Detailed Description

FLASH Erase structure definition.

Definition at line 188 of file stm32f1xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_EraseInitTypeDef::Banks

Select banks to erase when Mass erase is enabled. This parameter must be a value of Banks

Definition at line 193 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::NbPages

NbPages: Number of pagess to be erased. This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)

Definition at line 200 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::PageAddress

PageAdress: Initial FLASH page address to erase when mass erase is disabled This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END (x = 1 or 2 depending on devices)

Definition at line 196 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

uint32_t FLASH_EraseInitTypeDef::TypeErase

TypeErase: Mass erase or page erase. This parameter can be a value of Type Erase

Definition at line 190 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_flash_ex.h
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STM32F103xB HAL User Manual: FLASH_OBProgramInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
FLASH_OBProgramInitTypeDef Struct Reference
FLASHEx Exported Types

FLASH Options bytes program structure definition. More...

#include <stm32f1xx_hal_flash_ex.h>

Data Fields

uint32_t | OptionType
uint32_t | WRPState
uint32_t | WRPPage
uint32_t | Banks
uint8_t | RDPLevel
uint8_t | USERConfig
uint32_t | DATAAddress
uint8_t | DATAData

Detailed Description

FLASH Options bytes program structure definition.

Definition at line 208 of file stm32f1xx_hal_flash_ex.h.

Field Documentation

uint32_t FLASH_OBProgramInitTypeDef::Banks

Select banks for WRP activation/deactivation of all sectors. This parameter must be a value of Banks

Definition at line 219 of file stm32f1xx_hal_flash_ex.h.

uint32_t FLASH_OBProgramInitTypeDef::DATAAddress

DATAAddress: Address of the option byte DATA to be programmed This parameter can be a value of Option Byte Data Address

Definition at line 237 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

uint8_t FLASH_OBProgramInitTypeDef::DATAData

DATAData: Data to be stored in the option byte DATA This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 240 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::OptionType

OptionType: Option byte to be configured. This parameter can be a value of Option Bytes Type

Definition at line 210 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint8_t FLASH_OBProgramInitTypeDef::RDPLevel

RDPLevel: Set the read protection level.. This parameter can be a value of Option Byte Read Protection

Definition at line 222 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint8_t FLASH_OBProgramInitTypeDef::USERConfig

USERConfig: Program the FLASH User Option Byte: IWDG / STOP / STDBY This parameter can be a combination of Option Byte IWatchdog, Option Byte nRST STOP, Option Byte nRST STDBY

Definition at line 231 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPPage

WRPPage: specifies the page(s) to be write protected This parameter can be a value of Option Bytes Write Protection

Definition at line 216 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

uint32_t FLASH_OBProgramInitTypeDef::WRPState

WRPState: Write protection activation or deactivation. This parameter can be a value of Option Byte WRP State

Definition at line 213 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_flash_ex.h
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STM32F103xB HAL User Manual: Page Size

Defines
Page Size
FLASH Constants

Defines

#define FLASH_PAGE_SIZE 0x400U

Define Documentation

#define FLASH_PAGE_SIZE 0x400U

Definition at line 261 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASH_IRQHandler(), and HAL_FLASHEx_Erase().

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STM32F103xB HAL User Manual: Type Erase

Defines
Type Erase
FLASH Constants

Defines

#define | FLASH_TYPEERASE_PAGES 0x00U
#define | FLASH_TYPEERASE_MASSERASE 0x02U

Define Documentation

#define FLASH_TYPEERASE_MASSERASE 0x02U

Flash mass erase activation

Definition at line 279 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase(), and HAL_FLASHEx_Erase_IT().

#define FLASH_TYPEERASE_PAGES 0x00U

Pages erase only

Definition at line 278 of file stm32f1xx_hal_flash_ex.h.

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STM32F103xB HAL User Manual: Banks

Defines
Banks
FLASH Constants

Defines

#define FLASH_BANK_1 1U

Define Documentation

#define FLASH_BANK_1 1U

Bank 1

Definition at line 294 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_Erase().

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STM32F103xB HAL User Manual: Flag definition

Defines
Flag definition
FLASH Constants

Flag definition. More...

Defines

#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_PGERR FLASH_SR_PGERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR))

Detailed Description

Flag definition.

Define Documentation

#define FLASH_FLAG_BSY FLASH_SR_BSY

FLASH Busy flag

Definition at line 548 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_WaitForLastOperation().

#define FLASH_FLAG_EOP FLASH_SR_EOP

FLASH End of Operation flag

Definition at line 551 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR))

Option Byte Error

Definition at line 554 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_SetErrorCode(), and FLASH_WaitForLastOperation().

#define FLASH_FLAG_PGERR FLASH_SR_PGERR

FLASH Programming error flag

Definition at line 549 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR

FLASH Write protected error flag

Definition at line 550 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

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STM32F103xB HAL User Manual: Interrupt definition

Defines
Interrupt definition
FLASH Constants

FLASH Interrupt definition. More...

Defines

#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_ERR FLASH_CR_ERRIE

Detailed Description

FLASH Interrupt definition.

Define Documentation

#define FLASH_IT_EOP FLASH_CR_EOPIE

End of FLASH Operation Interrupt source

Definition at line 575 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define FLASH_IT_ERR FLASH_CR_ERRIE

Error Interrupt source

Definition at line 576 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASH_IRQHandler(), HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Option Bytes Type

Defines
Option Bytes Type
Option Byte Constants

Defines

#define | OPTIONBYTE_WRP 0x01U
#define | OPTIONBYTE_RDP 0x02U
#define | OPTIONBYTE_USER 0x04U
#define | OPTIONBYTE_DATA 0x08U

Define Documentation

#define OPTIONBYTE_DATA 0x08U

DATA option byte configuration

Definition at line 314 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_RDP 0x02U

RDP option byte configuration

Definition at line 312 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_USER 0x04U

USER option byte configuration

Definition at line 313 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

#define OPTIONBYTE_WRP 0x01U

WRP option byte configuration

Definition at line 311 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetConfig(), and HAL_FLASHEx_OBProgram().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Option Byte WRP State

Defines
Option Byte WRP State
Option Byte Constants

Defines

#define | OB_WRPSTATE_DISABLE 0x00U
#define | OB_WRPSTATE_ENABLE 0x01U

Define Documentation

#define OB_WRPSTATE_DISABLE 0x00U

Disable the write protection of the desired pages

Definition at line 323 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRPSTATE_ENABLE 0x01U

Enable the write protection of the desired pagess

Definition at line 324 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBProgram().

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STM32F103xB HAL User Manual: Option Bytes Write Protection

Defines
Option Bytes Write Protection
Option Byte Constants

Defines

#define | OB_WRP_PAGES0TO3 0x00000001U
#define | OB_WRP_PAGES4TO7 0x00000002U
#define | OB_WRP_PAGES8TO11 0x00000004U
#define | OB_WRP_PAGES12TO15 0x00000008U
#define | OB_WRP_PAGES16TO19 0x00000010U
#define | OB_WRP_PAGES20TO23 0x00000020U
#define | OB_WRP_PAGES24TO27 0x00000040U
#define | OB_WRP_PAGES28TO31 0x00000080U
#define | OB_WRP_PAGES32TO35 0x00000100U
#define | OB_WRP_PAGES36TO39 0x00000200U
#define | OB_WRP_PAGES40TO43 0x00000400U
#define | OB_WRP_PAGES44TO47 0x00000800U
#define | OB_WRP_PAGES48TO51 0x00001000U
#define | OB_WRP_PAGES52TO55 0x00002000U
#define | OB_WRP_PAGES56TO59 0x00004000U
#define | OB_WRP_PAGES60TO63 0x00008000U
#define | OB_WRP_PAGES64TO67 0x00010000U
#define | OB_WRP_PAGES68TO71 0x00020000U
#define | OB_WRP_PAGES72TO75 0x00040000U
#define | OB_WRP_PAGES76TO79 0x00080000U
#define | OB_WRP_PAGES80TO83 0x00100000U
#define | OB_WRP_PAGES84TO87 0x00200000U
#define | OB_WRP_PAGES88TO91 0x00400000U
#define | OB_WRP_PAGES92TO95 0x00800000U
#define | OB_WRP_PAGES96TO99 0x01000000U
#define | OB_WRP_PAGES100TO103 0x02000000U
#define | OB_WRP_PAGES104TO107 0x04000000U
#define | OB_WRP_PAGES108TO111 0x08000000U
#define | OB_WRP_PAGES112TO115 0x10000000U
#define | OB_WRP_PAGES116TO119 0x20000000U
#define | OB_WRP_PAGES120TO123 0x40000000U
#define | OB_WRP_PAGES124TO127 0x80000000U
#define | OB_WRP_ALLPAGES 0xFFFFFFFFU
#define | OB_WRP_PAGES0TO31MASK 0x000000FFU
#define | OB_WRP_PAGES32TO63MASK 0x0000FF00U
#define | OB_WRP_PAGES64TO95MASK 0x00FF0000U
#define | OB_WRP_PAGES96TO127MASK 0xFF000000U

Define Documentation

#define OB_WRP_ALLPAGES 0xFFFFFFFFU

Write protection of all Pages

Definition at line 419 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES0TO3 0x00000001U

Write protection of page 0 to 3

Definition at line 337 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES0TO31MASK 0x000000FFU

Definition at line 428 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define OB_WRP_PAGES100TO103 0x02000000U

Write protection of page 100 to 103

Definition at line 367 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES104TO107 0x04000000U

Write protection of page 104 to 107

Definition at line 368 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES108TO111 0x08000000U

Write protection of page 108 to 111

Definition at line 369 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES112TO115 0x10000000U

Write protection of page 112 to 115

Definition at line 370 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES116TO119 0x20000000U

Write protection of page 115 to 119

Definition at line 371 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES120TO123 0x40000000U

Write protection of page 120 to 123

Definition at line 372 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES124TO127 0x80000000U

Write protection of page 124 to 127

Definition at line 373 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES12TO15 0x00000008U

Write protection of page 12 to 15

Definition at line 340 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES16TO19 0x00000010U

Write protection of page 16 to 19

Definition at line 341 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES20TO23 0x00000020U

Write protection of page 20 to 23

Definition at line 342 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES24TO27 0x00000040U

Write protection of page 24 to 27

Definition at line 343 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES28TO31 0x00000080U

Write protection of page 28 to 31

Definition at line 344 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES32TO35 0x00000100U

Write protection of page 32 to 35

Definition at line 350 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES32TO63MASK 0x0000FF00U

Definition at line 429 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define OB_WRP_PAGES36TO39 0x00000200U

Write protection of page 36 to 39

Definition at line 351 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES40TO43 0x00000400U

Write protection of page 40 to 43

Definition at line 352 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES44TO47 0x00000800U

Write protection of page 44 to 47

Definition at line 353 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES48TO51 0x00001000U

Write protection of page 48 to 51

Definition at line 354 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES4TO7 0x00000002U

Write protection of page 4 to 7

Definition at line 338 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES52TO55 0x00002000U

Write protection of page 52 to 55

Definition at line 355 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES56TO59 0x00004000U

Write protection of page 56 to 59

Definition at line 356 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES60TO63 0x00008000U

Write protection of page 60 to 63

Definition at line 357 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES64TO67 0x00010000U

Write protection of page 64 to 67

Definition at line 358 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES64TO95MASK 0x00FF0000U

Definition at line 430 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define OB_WRP_PAGES68TO71 0x00020000U

Write protection of page 68 to 71

Definition at line 359 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES72TO75 0x00040000U

Write protection of page 72 to 75

Definition at line 360 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES76TO79 0x00080000U

Write protection of page 76 to 79

Definition at line 361 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES80TO83 0x00100000U

Write protection of page 80 to 83

Definition at line 362 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES84TO87 0x00200000U

Write protection of page 84 to 87

Definition at line 363 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES88TO91 0x00400000U

Write protection of page 88 to 91

Definition at line 364 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES8TO11 0x00000004U

Write protection of page 8 to 11

Definition at line 339 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES92TO95 0x00800000U

Write protection of page 92 to 95

Definition at line 365 of file stm32f1xx_hal_flash_ex.h.

#define OB_WRP_PAGES96TO127MASK 0xFF000000U

Definition at line 431 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_DisableWRP(), and FLASH_OB_EnableWRP().

#define OB_WRP_PAGES96TO99 0x01000000U

Write protection of page 96 to 99

Definition at line 366 of file stm32f1xx_hal_flash_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Option Byte Read Protection

Defines
Option Byte Read Protection
Option Byte Constants

Defines

#define | OB_RDP_LEVEL_0 ((uint8_t)0xA5)
#define | OB_RDP_LEVEL_1 ((uint8_t)0x00)

Define Documentation

#define OB_RDP_LEVEL_0 ((uint8_t)0xA5)

Definition at line 465 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP(), and HAL_FLASHEx_OBErase().

#define OB_RDP_LEVEL_1 ((uint8_t)0x00)

Definition at line 466 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_GetRDP().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Option Byte IWatchdog

Defines
Option Byte IWatchdog
Option Byte Constants

Defines

#define | OB_IWDG_SW ((uint16_t)0x0001)
#define | OB_IWDG_HW ((uint16_t)0x0000)

Define Documentation

#define OB_IWDG_HW ((uint16_t)0x0000)

Hardware IWDG selected

Definition at line 475 of file stm32f1xx_hal_flash_ex.h.

#define OB_IWDG_SW ((uint16_t)0x0001)

Software IWDG selected

Definition at line 474 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Option Byte nRST STOP

Defines
Option Byte nRST STOP
Option Byte Constants

Defines

#define | OB_STOP_NO_RST ((uint16_t)0x0002)
#define | OB_STOP_RST ((uint16_t)0x0000)

Define Documentation

#define OB_STOP_NO_RST ((uint16_t)0x0002)

No reset generated when entering in STOP

Definition at line 483 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_STOP_RST ((uint16_t)0x0000)

Reset generated when entering in STOP

Definition at line 484 of file stm32f1xx_hal_flash_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Option Byte nRST STDBY

Defines
Option Byte nRST STDBY
Option Byte Constants

Defines

#define | OB_STDBY_NO_RST ((uint16_t)0x0004)
#define | OB_STDBY_RST ((uint16_t)0x0000)

Define Documentation

#define OB_STDBY_NO_RST ((uint16_t)0x0004)

No reset generated when entering in STANDBY

Definition at line 492 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_OB_UserConfig().

#define OB_STDBY_RST ((uint16_t)0x0000)

Reset generated when entering in STANDBY

Definition at line 493 of file stm32f1xx_hal_flash_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Option Byte Data Address

Defines
Option Byte Data Address
Option Byte Constants

Defines

#define | OB_DATA_ADDRESS_DATA0 0x1FFFF804U
#define | OB_DATA_ADDRESS_DATA1 0x1FFFF806U

Define Documentation

#define OB_DATA_ADDRESS_DATA0 0x1FFFF804U

Definition at line 512 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASHEx_OBGetUserData().

#define OB_DATA_ADDRESS_DATA1 0x1FFFF806U

Definition at line 513 of file stm32f1xx_hal_flash_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Interrupt

Defines
Interrupt
FLASHEx Exported Macros

macros to handle FLASH interrupts More...

Defines

#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
Get the specified FLASH flag status.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the specified FLASH flag.

Detailed Description

macros to handle FLASH interrupts

Define Documentation

#define __HAL_FLASH_CLEAR_FLAG ( __FLAG__ )
Value:
do { \
                          /* Clear FLASH_FLAG_OPTVERR flag */ \
                          if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
                          { \
                            CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
                          } \
                          else { \
                            /* Clear Flag in Bank1 */ \
                            FLASH->SR  = (__FLAG__); \
                          } \
                    } while(0U)

Clear the specified FLASH flag.

Parameters:
__FLAG__ specifies the FLASH flags to clear. This parameter can be any combination of the following values:
  • FLASH_FLAG_EOP FLASH End of Operation flag
  • FLASH_FLAG_WRPERR FLASH Write protected error flag
  • FLASH_FLAG_PGERR FLASH Programming error flag
  • FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
Return values:
none

Definition at line 737 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

#define __HAL_FLASH_DISABLE_IT ( __INTERRUPT__ ) (FLASH->CR &= ~(__INTERRUPT__))

Disable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP End of FLASH Operation Interrupt
  • FLASH_IT_ERR Error Interrupt
Return values:
none

Definition at line 711 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASH_IRQHandler().

#define __HAL_FLASH_ENABLE_IT ( __INTERRUPT__ ) (FLASH->CR |= (__INTERRUPT__))

Enable the specified FLASH interrupt.

Parameters:
__INTERRUPT__ FLASH interrupt This parameter can be any combination of the following values:
  • FLASH_IT_EOP End of FLASH Operation Interrupt
  • FLASH_IT_ERR Error Interrupt
Return values:
none

Definition at line 701 of file stm32f1xx_hal_flash_ex.h.

Referenced by HAL_FLASH_Program_IT(), and HAL_FLASHEx_Erase_IT().

#define __HAL_FLASH_GET_FLAG ( __FLAG__ )
Value:
(((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
                                            (FLASH->OBR & FLASH_OBR_OPTERR) : \
                                            (FLASH->SR & (__FLAG__)))

Get the specified FLASH flag status.

Parameters:
__FLAG__ specifies the FLASH flag to check. This parameter can be one of the following values:
  • FLASH_FLAG_EOP FLASH End of Operation flag
  • FLASH_FLAG_WRPERR FLASH Write protected error flag
  • FLASH_FLAG_PGERR FLASH Programming error flag
  • FLASH_FLAG_BSY FLASH Busy flag
  • FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
Return values:
The new state of __FLAG__ (SET or RESET).

Definition at line 724 of file stm32f1xx_hal_flash_ex.h.

Referenced by FLASH_SetErrorCode(), FLASH_WaitForLastOperation(), and HAL_FLASH_IRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
GPIO Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
  [..]
    This section provides functions allowing to initialize and de-initialize the GPIOs
    to be ready for use.

Function Documentation

void HAL_GPIO_DeInit | ( | GPIO_TypeDef * | GPIOx,
 |  | uint32_t | GPIO_Pin
 | ) |  |

De-initializes the GPIOx peripheral registers to their default reset values.

Parameters:
GPIOx,: where x can be (A..G depending on device used) to select the GPIO peripheral
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
Return values:
None

Definition at line 367 of file stm32f1xx_hal_gpio.c.

References assert_param, GPIO_GET_INDEX, GPIO_PIN_8, and IS_GPIO_PIN.

void HAL_GPIO_Init | ( | GPIO_TypeDef * | GPIOx,
 |  | GPIO_InitTypeDef * | GPIO_Init
 | ) |  |

Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.

Parameters:
GPIOx,: where x can be (A..G depending on device used) to select the GPIO peripheral
GPIO_Init,: pointer to a GPIO_InitTypeDef structure that contains the configuration information for the specified GPIO peripheral.
Return values:
None

Definition at line 196 of file stm32f1xx_hal_gpio.c.

References __HAL_RCC_AFIO_CLK_ENABLE, assert_param, EXTI_MODE, FALLING_EDGE, GPIO_CR_CNF_AF_OUTPUT_OD, GPIO_CR_CNF_AF_OUTPUT_PP, GPIO_CR_CNF_ANALOG, GPIO_CR_CNF_GP_OUTPUT_OD, GPIO_CR_CNF_GP_OUTPUT_PP, GPIO_CR_CNF_INPUT_FLOATING, GPIO_CR_CNF_INPUT_PU_PD, GPIO_CR_MODE_INPUT, GPIO_GET_INDEX, GPIO_MODE_AF_OD, GPIO_MODE_AF_PP, GPIO_MODE_ANALOG, GPIO_MODE_EVT, GPIO_MODE_EVT_FALLING, GPIO_MODE_EVT_RISING, GPIO_MODE_EVT_RISING_FALLING, GPIO_MODE_INPUT, GPIO_MODE_IT, GPIO_MODE_IT_FALLING, GPIO_MODE_IT_RISING, GPIO_MODE_IT_RISING_FALLING, GPIO_MODE_OUTPUT_OD, GPIO_MODE_OUTPUT_PP, GPIO_NOPULL, GPIO_NUMBER, GPIO_PIN_8, GPIO_PULLUP, IS_GPIO_MODE, IS_GPIO_PIN, IS_GPIO_PULL, IS_GPIO_SPEED, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, RISING_EDGE, and GPIO_InitTypeDef::Speed.

Referenced by HAL_RCC_MCOConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
GPIO Exported Functions

GPIO Read and Write. More...

Functions

GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
This function handles EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callbacks.

Detailed Description

GPIO Read and Write.

 ===============================================================================
                       ##### IO operation functions #####
 ===============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the GPIOs.

Function Documentation

void HAL_GPIO_EXTI_Callback ( uint16_t GPIO_Pin )

EXTI line detection callbacks.

Parameters:
GPIO_Pin,: Specifies the pins connected EXTI line
Return values:
None

Definition at line 571 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_EXTI_IRQHandler().

void HAL_GPIO_EXTI_IRQHandler ( uint16_t GPIO_Pin )

This function handles EXTI interrupt request.

Parameters:
GPIO_Pin,: Specifies the pins connected EXTI line
Return values:
None

Definition at line 556 of file stm32f1xx_hal_gpio.c.

References __HAL_GPIO_EXTI_CLEAR_IT, __HAL_GPIO_EXTI_GET_IT, and HAL_GPIO_EXTI_Callback().

HAL_StatusTypeDef HAL_GPIO_LockPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Locks GPIO Pins configuration registers.

Note:
The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence has been applied on a port bit, it is no longer possible to modify the value of the port bit until the next reset.
Parameters:
GPIOx,: where x can be (A..G depending on device used) to select the GPIO peripheral
GPIO_Pin,: specifies the port bit to be locked. This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
Return values:
None

Definition at line 522 of file stm32f1xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

GPIO_PinState HAL_GPIO_ReadPin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Reads the specified input port pin.

Parameters:
GPIOx,: where x can be (A..G depending on device used) to select the GPIO peripheral
GPIO_Pin,: specifies the port bit to read. This parameter can be GPIO_PIN_x where x can be (0..15).
Return values:
The input port pin value.

Definition at line 448 of file stm32f1xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, GPIO_PIN_SET, and IS_GPIO_PIN.

void HAL_GPIO_TogglePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin
 | ) |  |

Toggles the specified GPIO pin.

Parameters:
GPIOx,: where x can be (A..G depending on device used) to select the GPIO peripheral
GPIO_Pin,: Specifies the pins to be toggled.
Return values:
None

Definition at line 504 of file stm32f1xx_hal_gpio.c.

References assert_param, and IS_GPIO_PIN.

void HAL_GPIO_WritePin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | GPIO_Pin,
 |  | GPIO_PinState | PinState
 | ) |  |

Sets or clears the selected data port bit.

Note:
This function uses GPIOx_BSRR register to allow atomic read/modify accesses. In this way, there is no risk of an IRQ occurring between the read and the modify access.
Parameters:
GPIOx,: where x can be (A..G depending on device used) to select the GPIO peripheral
GPIO_Pin,: specifies the port bit to be written. This parameter can be one of GPIO_PIN_x where x can be (0..15).
PinState,: specifies the value to be written to the selected bit. This parameter can be one of the GPIO_PinState enum values:
  • GPIO_BIT_RESET: to clear the port pin
  • GPIO_BIT_SET: to set the port pin
Return values:
None

Definition at line 482 of file stm32f1xx_hal_gpio.c.

References assert_param, GPIO_PIN_RESET, IS_GPIO_PIN, and IS_GPIO_PIN_ACTION.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO Exported Types

Data Structures | Enumerations
GPIO Exported Types
GPIO

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Enumeration Type Documentation

enum GPIO_PinState

GPIO Bit SET and Bit RESET enumeration.

Enumerator:
GPIO_PIN_RESET
GPIO_PIN_SET

Definition at line 83 of file stm32f1xx_hal_gpio.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
GPIO_InitTypeDef Struct Reference
GPIO Exported Types

GPIO Init structure definition. More...

#include <stm32f1xx_hal_gpio.h>

Data Fields

uint32_t | Pin
uint32_t | Mode
uint32_t | Pull
uint32_t | Speed

Detailed Description

GPIO Init structure definition.

Definition at line 65 of file stm32f1xx_hal_gpio.h.

Field Documentation

uint32_t GPIO_InitTypeDef::Mode

Specifies the operating mode for the selected pins. This parameter can be a value of GPIO mode define

Definition at line 70 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pin

Specifies the GPIO pins to be configured. This parameter can be any value of GPIO pins define

Definition at line 67 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Pull

Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of GPIO pull define

Definition at line 73 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

uint32_t GPIO_InitTypeDef::Speed

Specifies the speed for the selected pins. This parameter can be a value of GPIO speed define

Definition at line 76 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_gpio.h
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STM32F103xB HAL User Manual: GPIO pins define

Defines
GPIO pins define
GPIO Exported Constants

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */

Define Documentation

#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */

Definition at line 101 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */

Definition at line 102 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */

Definition at line 111 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */

Definition at line 112 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */

Definition at line 113 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */

Definition at line 114 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */

Definition at line 115 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */

Definition at line 116 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */

Definition at line 103 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */

Definition at line 104 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */

Definition at line 105 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */

Definition at line 106 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */

Definition at line 107 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */

Definition at line 108 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */

Definition at line 109 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */

Definition at line 110 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */

Definition at line 117 of file stm32f1xx_hal_gpio.h.

#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */

Definition at line 119 of file stm32f1xx_hal_gpio.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO mode define

Defines
GPIO mode define
GPIO Exported Constants

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ. More...

Defines

#define | GPIO_MODE_INPUT 0x00000000U
#define | GPIO_MODE_OUTPUT_PP 0x00000001U
#define | GPIO_MODE_OUTPUT_OD 0x00000011U
#define | GPIO_MODE_AF_PP 0x00000002U
#define | GPIO_MODE_AF_OD 0x00000012U
#define | GPIO_MODE_AF_INPUT GPIO_MODE_INPUT
#define | GPIO_MODE_ANALOG 0x00000003U
#define | GPIO_MODE_IT_RISING 0x10110000U
#define | GPIO_MODE_IT_FALLING 0x10210000U
#define | GPIO_MODE_IT_RISING_FALLING 0x10310000U
#define | GPIO_MODE_EVT_RISING 0x10120000U
#define | GPIO_MODE_EVT_FALLING 0x10220000U
#define | GPIO_MODE_EVT_RISING_FALLING 0x10320000U

Detailed Description

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

  • X : GPIO mode or EXTI Mode
  • y : External IT or Event trigger detection
  • z : IO configuration on External IT or Event
  • Y : Output type (Push Pull or Open Drain)
  • Z : IO Direction mode (Input, Output, Alternate or Analog)

Define Documentation

#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT

Alternate Function Input Mode

Definition at line 139 of file stm32f1xx_hal_gpio.h.

#define GPIO_MODE_AF_OD 0x00000012U

Alternate Function Open Drain Mode

Definition at line 138 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_AF_PP 0x00000002U

Alternate Function Push Pull Mode

Definition at line 137 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

#define GPIO_MODE_ANALOG 0x00000003U

Analog Mode

Definition at line 141 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_EVT_FALLING 0x10220000U

External Event Mode with Falling edge trigger detection

Definition at line 148 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_EVT_RISING 0x10120000U

External Event Mode with Rising edge trigger detection

Definition at line 147 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U

External Event Mode with Rising/Falling edge trigger detection

Definition at line 149 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_INPUT 0x00000000U

Input Floating Mode

Definition at line 134 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT_FALLING 0x10210000U

External Interrupt Mode with Falling edge trigger detection

Definition at line 144 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT_RISING 0x10110000U

External Interrupt Mode with Rising edge trigger detection

Definition at line 143 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT_RISING_FALLING 0x10310000U

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 145 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_OUTPUT_OD 0x00000011U

Output Open Drain Mode

Definition at line 136 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_OUTPUT_PP 0x00000001U

Output Push Pull Mode

Definition at line 135 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO speed define

Defines
GPIO speed define
GPIO Exported Constants

GPIO Output Maximum frequency. More...

Defines

#define | GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1)
#define | GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0)
#define | GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0)

Detailed Description

GPIO Output Maximum frequency.

Define Documentation

#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0)

High speed

Definition at line 161 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_RCC_MCOConfig().

#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1)

Low speed

Definition at line 159 of file stm32f1xx_hal_gpio.h.

#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0)

Medium speed

Definition at line 160 of file stm32f1xx_hal_gpio.h.

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STM32F103xB HAL User Manual: GPIO pull define

Defines
GPIO pull define
GPIO Exported Constants

GPIO Pull-Up or Pull-Down Activation. More...

Defines

#define | GPIO_NOPULL 0x00000000U
#define | GPIO_PULLUP 0x00000001U
#define | GPIO_PULLDOWN 0x00000002U

Detailed Description

GPIO Pull-Up or Pull-Down Activation.

Define Documentation

#define GPIO_NOPULL 0x00000000U

No Pull-up or Pull-down activation

Definition at line 171 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init(), and HAL_RCC_MCOConfig().

#define GPIO_PULLDOWN 0x00000002U

Pull-down activation

Definition at line 173 of file stm32f1xx_hal_gpio.h.

#define GPIO_PULLUP 0x00000001U

Pull-up activation

Definition at line 172 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

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STM32F103xB HAL User Manual: GPIO Exported Macros

Defines
GPIO Exported Macros
GPIO

Defines

#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_GPIO_EXTI_CLEAR_FLAG ( __EXTI_LINE__ ) (EXTI->PR = (__EXTI_LINE__))

Clears the EXTI's line pending flags.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines flags to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 201 of file stm32f1xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_CLEAR_IT ( __EXTI_LINE__ ) (EXTI->PR = (__EXTI_LINE__))

Clears the EXTI's line pending bits.

Parameters:
__EXTI_LINE__,: specifies the EXTI lines to clear. This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
Return values:
None

Definition at line 217 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

#define __HAL_GPIO_EXTI_GENERATE_SWIT ( __EXTI_LINE__ ) (EXTI->SWIER |= (__EXTI_LINE__))

Generates a Software interrupt on selected EXTI line.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
None

Definition at line 225 of file stm32f1xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_FLAG ( __EXTI_LINE__ ) (EXTI->PR & (__EXTI_LINE__))

Checks whether the specified EXTI line flag is set or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line flag to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 193 of file stm32f1xx_hal_gpio.h.

#define __HAL_GPIO_EXTI_GET_IT ( __EXTI_LINE__ ) (EXTI->PR & (__EXTI_LINE__))

Checks whether the specified EXTI line is asserted or not.

Parameters:
__EXTI_LINE__,: specifies the EXTI line to check. This parameter can be GPIO_PIN_x where x can be(0..15)
Return values:
The new state of __EXTI_LINE__ (SET or RESET).

Definition at line 209 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_EXTI_IRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO Private Constants

Defines
GPIO Private Constants
GPIO

Defines

#define | GPIO_MODE 0x00000003U
#define | EXTI_MODE 0x10000000U
#define | GPIO_MODE_IT 0x00010000U
#define | GPIO_MODE_EVT 0x00020000U
#define | RISING_EDGE 0x00100000U
#define | FALLING_EDGE 0x00200000U
#define | GPIO_OUTPUT_TYPE 0x00000010U
#define | GPIO_NUMBER 16U
#define | GPIO_CR_MODE_INPUT 0x00000000U
#define | GPIO_CR_CNF_ANALOG 0x00000000U
#define | GPIO_CR_CNF_INPUT_FLOATING 0x00000004U
#define | GPIO_CR_CNF_INPUT_PU_PD 0x00000008U
#define | GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U
#define | GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U
#define | GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U
#define | GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU

Define Documentation

#define EXTI_MODE 0x10000000U

Definition at line 142 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define FALLING_EDGE 0x00200000U

Definition at line 146 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU

11: Alternate function output Open-drain

Definition at line 159 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U

10: Alternate function output Push-pull

Definition at line 158 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_CR_CNF_ANALOG 0x00000000U

00: Analog mode

Definition at line 153 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U

01: General purpose output Open-drain

Definition at line 157 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U

00: General purpose output push-pull

Definition at line 156 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004U

01: Floating input (reset state)

Definition at line 154 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008U

10: Input with pull-up / pull-down

Definition at line 155 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_CR_MODE_INPUT 0x00000000U

00: Input mode (reset state)

Definition at line 152 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE 0x00000003U

Definition at line 141 of file stm32f1xx_hal_gpio.c.

#define GPIO_MODE_EVT 0x00020000U

Definition at line 144 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_MODE_IT 0x00010000U

Definition at line 143 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_NUMBER 16U

Definition at line 149 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

#define GPIO_OUTPUT_TYPE 0x00000010U

Definition at line 147 of file stm32f1xx_hal_gpio.c.

#define RISING_EDGE 0x00100000U

Definition at line 145 of file stm32f1xx_hal_gpio.c.

Referenced by HAL_GPIO_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO Private Macros

Defines
GPIO Private Macros
GPIO

Defines

#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)
#define | IS_GPIO_PULL(PULL)

Define Documentation

#define IS_GPIO_MODE ( MODE )
Value:
(((MODE) == GPIO_MODE_INPUT)              ||\
                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
                            ((MODE) == GPIO_MODE_AF_PP)              ||\
                            ((MODE) == GPIO_MODE_AF_OD)              ||\
                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
                            ((MODE) == GPIO_MODE_ANALOG))

Definition at line 283 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_PIN ( PIN ) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))

Definition at line 282 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), and HAL_GPIO_WritePin().

#define IS_GPIO_PIN_ACTION ( ACTION ) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

Definition at line 281 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_WritePin().

#define IS_GPIO_PULL ( PULL )
Value:
(((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
                            ((PULL) == GPIO_PULLDOWN))

Definition at line 297 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

#define IS_GPIO_SPEED ( SPEED )
Value:
(((SPEED) == GPIO_SPEED_FREQ_LOW) || \
                              ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))

Definition at line 295 of file stm32f1xx_hal_gpio.h.

Referenced by HAL_GPIO_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO Private Functions

GPIO Private Functions
GPIO
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Extended features functions

Functions
Extended features functions
GPIOEx Exported Functions

Extended features functions. More...

Functions

void | HAL_GPIOEx_ConfigEventout (uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
void | HAL_GPIOEx_EnableEventout (void)
Enables the Event Output.
void | HAL_GPIOEx_DisableEventout (void)
Disables the Event Output.

Detailed Description

Extended features functions.

  ==============================================================================
                 ##### Extended features functions #####
  ==============================================================================
    [..]  This section provides functions allowing to:
    (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
    (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
    (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()

Function Documentation

void HAL_GPIOEx_ConfigEventout | ( | uint32_t | GPIO_PortSource,
 |  | uint32_t | GPIO_PinSource
 | ) |  |

Configures the port and pin on which the EVENTOUT Cortex signal will be connected.

Parameters:
GPIO_PortSource | Select the port used to output the Cortex EVENTOUT signal. This parameter can be a value of EVENTOUT Port.
GPIO_PinSource | Select the pin used to output the Cortex EVENTOUT signal. This parameter can be a value of EVENTOUT Pin.
Return values:
None

Definition at line 99 of file stm32f1xx_hal_gpio_ex.c.

References assert_param, IS_AFIO_EVENTOUT_PIN, and IS_AFIO_EVENTOUT_PORT.

void HAL_GPIOEx_DisableEventout ( void )

Disables the Event Output.

Return values:
None

Definition at line 122 of file stm32f1xx_hal_gpio_ex.c.

void HAL_GPIOEx_EnableEventout ( void )

Enables the Event Output.

Return values:
None

Definition at line 113 of file stm32f1xx_hal_gpio_ex.c.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: EVENTOUT Pin

Defines
EVENTOUT Pin
EVENTOUT Cortex Configuration

Defines

#define | AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0
#define | AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1
#define | AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2
#define | AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3
#define | AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4
#define | AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5
#define | AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6
#define | AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7
#define | AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8
#define | AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9
#define | AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10
#define | AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11
#define | AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12
#define | AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13
#define | AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14
#define | AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15
#define | IS_AFIO_EVENTOUT_PIN(__PIN__)

Define Documentation

#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0

EVENTOUT on pin 0

Definition at line 74 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1

EVENTOUT on pin 1

Definition at line 75 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10

EVENTOUT on pin 10

Definition at line 84 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11

EVENTOUT on pin 11

Definition at line 85 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12

EVENTOUT on pin 12

Definition at line 86 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13

EVENTOUT on pin 13

Definition at line 87 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14

EVENTOUT on pin 14

Definition at line 88 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15

EVENTOUT on pin 15

Definition at line 89 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2

EVENTOUT on pin 2

Definition at line 76 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3

EVENTOUT on pin 3

Definition at line 77 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4

EVENTOUT on pin 4

Definition at line 78 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5

EVENTOUT on pin 5

Definition at line 79 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6

EVENTOUT on pin 6

Definition at line 80 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7

EVENTOUT on pin 7

Definition at line 81 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8

EVENTOUT on pin 8

Definition at line 82 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9

EVENTOUT on pin 9

Definition at line 83 of file stm32f1xx_hal_gpio_ex.h.

#define IS_AFIO_EVENTOUT_PIN ( __PIN__ )
Value:
(((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
                                       ((__PIN__) == AFIO_EVENTOUT_PIN_15))

Definition at line 91 of file stm32f1xx_hal_gpio_ex.h.

Referenced by HAL_GPIOEx_ConfigEventout().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: EVENTOUT Port

Defines
EVENTOUT Port
EVENTOUT Cortex Configuration

Defines

#define | AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA
#define | AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB
#define | AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC
#define | AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD
#define | AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE
#define | IS_AFIO_EVENTOUT_PORT(__PORT__)

Define Documentation

#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA

EVENTOUT on port A

Definition at line 115 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB

EVENTOUT on port B

Definition at line 116 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC

EVENTOUT on port C

Definition at line 117 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD

EVENTOUT on port D

Definition at line 118 of file stm32f1xx_hal_gpio_ex.h.

#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE

EVENTOUT on port E

Definition at line 119 of file stm32f1xx_hal_gpio_ex.h.

#define IS_AFIO_EVENTOUT_PORT ( __PORT__ )
Value:
(((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
                                         ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
                                         ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
                                         ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
                                         ((__PORT__) == AFIO_EVENTOUT_PORT_E))

Definition at line 121 of file stm32f1xx_hal_gpio_ex.h.

Referenced by HAL_GPIOEx_ConfigEventout().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Alternate Function Remapping

Defines
Alternate Function Remapping
GPIOEx Exported Constants

This section propose definition to remap the alternate function to some other port/pins. More...

Defines

#define | __HAL_AFIO_REMAP_SPI1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
#define | __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
#define | __HAL_AFIO_REMAP_I2C1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
Enable the remapping of I2C1 alternate function SCL and SDA.
#define | __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
Disable the remapping of I2C1 alternate function SCL and SDA.
#define | __HAL_AFIO_REMAP_USART1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
Enable the remapping of USART1 alternate function TX and RX.
#define | __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
Disable the remapping of USART1 alternate function TX and RX.
#define | __HAL_AFIO_REMAP_USART2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
#define | __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
#define | __HAL_AFIO_REMAP_USART3_ENABLE()
Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
#define | __HAL_AFIO_REMAP_USART3_PARTIAL()
Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
#define | __HAL_AFIO_REMAP_USART3_DISABLE()
Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
#define | __HAL_AFIO_REMAP_TIM1_ENABLE()
Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
#define | __HAL_AFIO_REMAP_TIM1_PARTIAL()
Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
#define | __HAL_AFIO_REMAP_TIM1_DISABLE()
Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
#define | __HAL_AFIO_REMAP_TIM2_ENABLE()
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
#define | __HAL_AFIO_REMAP_TIM2_PARTIAL_2()
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
#define | __HAL_AFIO_REMAP_TIM2_PARTIAL_1()
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
#define | __HAL_AFIO_REMAP_TIM2_DISABLE()
Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
#define | __HAL_AFIO_REMAP_TIM3_ENABLE()
Enable the remapping of TIM3 alternate function channels 1 to 4.
#define | __HAL_AFIO_REMAP_TIM3_PARTIAL()
Enable the remapping of TIM3 alternate function channels 1 to 4.
#define | __HAL_AFIO_REMAP_TIM3_DISABLE()
Disable the remapping of TIM3 alternate function channels 1 to 4.
#define | __HAL_AFIO_REMAP_TIM4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
Enable the remapping of TIM4 alternate function channels 1 to 4.
#define | __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
Disable the remapping of TIM4 alternate function channels 1 to 4.
#define | __HAL_AFIO_REMAP_CAN1_1()
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
#define | __HAL_AFIO_REMAP_CAN1_2()
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
#define | __HAL_AFIO_REMAP_CAN1_3()
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
#define | __HAL_AFIO_REMAP_PD01_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
Enable the remapping of PD0 and PD1.
#define | __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
Disable the remapping of PD0 and PD1.
#define | __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
#define | __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
#define | __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
#define | __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
#define | __HAL_AFIO_REMAP_SWJ_ENABLE()
Enable the Serial wire JTAG configuration.
#define | __HAL_AFIO_REMAP_SWJ_NONJTRST()
Enable the Serial wire JTAG configuration.
#define | __HAL_AFIO_REMAP_SWJ_NOJTAG()
Enable the Serial wire JTAG configuration.
#define | __HAL_AFIO_REMAP_SWJ_DISABLE()
Disable the Serial wire JTAG configuration.

Detailed Description

This section propose definition to remap the alternate function to some other port/pins.

Define Documentation

#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE ( ) CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)

Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).

Note:
DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
Return values:
None

Definition at line 465 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE ( ) SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)

Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).

Note:
ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
Return values:
None

Definition at line 458 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE ( ) CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)

Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).

Note:
DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
Return values:
None

Definition at line 479 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE ( ) SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)

Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).

Note:
ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
Return values:
None

Definition at line 472 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_CAN1_1 ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);         \
                                        SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);    \
                                      }while(0U)

Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.

Note:
CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
Return values:
None

Definition at line 337 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_CAN1_2 ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);         \
                                        SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);    \
                                      }while(0U)

Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.

Note:
CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
Return values:
None

Definition at line 346 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_CAN1_3 ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);                 \
                                       SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);       \
                                     }while(0U)

Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.

Note:
CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
Return values:
None

Definition at line 355 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_I2C1_DISABLE ( ) CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)

Disable the remapping of I2C1 alternate function SCL and SDA.

Note:
DISABLE: No remap (SCL/PB6, SDA/PB7)
Return values:
None

Definition at line 165 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_I2C1_ENABLE ( ) SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)

Enable the remapping of I2C1 alternate function SCL and SDA.

Note:
ENABLE: Remap (SCL/PB8, SDA/PB9)
Return values:
None

Definition at line 158 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_PD01_DISABLE ( ) CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)

Disable the remapping of PD0 and PD1.

When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping).

Note:
DISABLE: No remapping of PD0 and PD1
Return values:
None

Definition at line 378 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_PD01_ENABLE ( ) SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)

Enable the remapping of PD0 and PD1.

When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping).

Note:
ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
Return values:
None

Definition at line 368 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_SPI1_DISABLE ( ) CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)

Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.

Note:
DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
Return values:
None

Definition at line 151 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_SPI1_ENABLE ( ) SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)

Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.

Note:
ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
Return values:
None

Definition at line 144 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_SWJ_DISABLE ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG);         \
                                            SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);   \
                                          }while(0U)

Disable the Serial wire JTAG configuration.

Note:
DISABLE: JTAG-DP Disabled and SW-DP Disabled
Return values:
None

Definition at line 547 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_SWJ_ENABLE ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG);         \
                                           SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);     \
                                         }while(0U)

Enable the Serial wire JTAG configuration.

Note:
ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
Return values:
None

Definition at line 520 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_SWJ_NOJTAG ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG);           \
                                            SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); \
                                          }while(0U)

Enable the Serial wire JTAG configuration.

Note:
NOJTAG: JTAG-DP Disabled and SW-DP Enabled
Return values:
None

Definition at line 538 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_SWJ_NONJTRST ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG);         \
                                              SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);  \
                                            }while(0U)

Enable the Serial wire JTAG configuration.

Note:
NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
Return values:
None

Definition at line 529 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM1_DISABLE ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);       \
                                            SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP); \
                                          }while(0U)

Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)

Note:
DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
Return values:
None

Definition at line 244 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM1_ENABLE ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);         \
                                            SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP); \
                                          }while(0U)

Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)

Note:
ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
Return values:
None

Definition at line 226 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM1_PARTIAL ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);            \
                                             SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP); \
                                           }while(0U)

Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)

Note:
PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
Return values:
None

Definition at line 235 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM2_DISABLE ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);         \
                                            SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);   \
                                          }while(0U)

Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)

Note:
DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
Return values:
None

Definition at line 280 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM2_ENABLE ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);         \
                                            SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP); \
                                          }while(0U)

Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)

Note:
ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
Return values:
None

Definition at line 253 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1 ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);             \
                                               SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1); \
                                             }while(0U)

Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)

Note:
PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
Return values:
None

Definition at line 271 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2 ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);             \
                                               SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2); \
                                             }while(0U)

Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)

Note:
PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
Return values:
None

Definition at line 262 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM3_DISABLE ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);           \
                                              SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);     \
                                            }while(0U)

Disable the remapping of TIM3 alternate function channels 1 to 4.

Note:
DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
TIM3_ETR on PE0 is not re-mapped.
Return values:
None

Definition at line 310 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM3_ENABLE ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);         \
                                            SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP); \
                                          }while(0U)

Enable the remapping of TIM3 alternate function channels 1 to 4.

Note:
ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
TIM3_ETR on PE0 is not re-mapped.
Return values:
None

Definition at line 290 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM3_PARTIAL ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);            \
                                               SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP); \
                                             }while(0U)

Enable the remapping of TIM3 alternate function channels 1 to 4.

Note:
PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
TIM3_ETR on PE0 is not re-mapped.
Return values:
None

Definition at line 300 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM4_DISABLE ( ) CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)

Disable the remapping of TIM4 alternate function channels 1 to 4.

Note:
DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
TIM4_ETR on PE0 is not re-mapped.
Return values:
None

Definition at line 328 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_TIM4_ENABLE ( ) SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)

Enable the remapping of TIM4 alternate function channels 1 to 4.

Note:
ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
TIM4_ETR on PE0 is not re-mapped.
Return values:
None

Definition at line 320 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_USART1_DISABLE ( ) CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)

Disable the remapping of USART1 alternate function TX and RX.

Note:
DISABLE: No remap (TX/PA9, RX/PA10)
Return values:
None

Definition at line 179 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_USART1_ENABLE ( ) SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)

Enable the remapping of USART1 alternate function TX and RX.

Note:
ENABLE: Remap (TX/PB6, RX/PB7)
Return values:
None

Definition at line 172 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_USART2_DISABLE ( ) CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)

Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.

Note:
DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
Return values:
None

Definition at line 193 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_USART2_ENABLE ( ) SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)

Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.

Note:
ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
Return values:
None

Definition at line 186 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_USART3_DISABLE ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);       \
                                              SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP); \
                                            }while(0U)

Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.

Note:
DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
Return values:
None

Definition at line 217 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_USART3_ENABLE ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);            \
                                              SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);    \
                                            }while(0U)

Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.

Note:
ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
Return values:
None

Definition at line 200 of file stm32f1xx_hal_gpio_ex.h.

#define __HAL_AFIO_REMAP_USART3_PARTIAL ( )
Value:
do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);            \
                                              SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP); \
                                            }while(0U)

Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.

Note:
PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
Return values:
None

Definition at line 208 of file stm32f1xx_hal_gpio_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIOEx Private Macros

Defines
GPIOEx Private Macros
GPIOEx

Defines

#define GPIO_GET_INDEX(__GPIOx__)

Define Documentation

#define GPIO_GET_INDEX ( __GPIOx__ )
Value:
(((__GPIOx__) == (GPIOA))? 0U :\
                                   ((__GPIOx__) == (GPIOB))? 1U :\
                                   ((__GPIOx__) == (GPIOC))? 2U :\
                                   ((__GPIOx__) == (GPIOD))? 3U :4U)

Definition at line 873 of file stm32f1xx_hal_gpio_ex.h.

Referenced by HAL_GPIO_DeInit(), and HAL_GPIO_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
I2C Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitializes the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
I2C MSP Init.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
I2C MSP DeInit.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the I2Cx peripheral:

      (+) User must Implement HAL_I2C_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).

      (+) Call the function HAL_I2C_Init() to configure the selected device with
          the selected configuration:
        (++) Communication Speed
        (++) Duty cycle
        (++) Addressing mode
        (++) Own Address 1
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
          of the selected I2Cx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_I2C_DeInit ( I2C_HandleTypeDef * hi2c )

DeInitializes the I2C peripheral.

Parameters:
hi2c,: pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 453 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspDeInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_RESET, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_Init ( I2C_HandleTypeDef * hi2c )

Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.

Parameters:
hi2c,: pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 371 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_ENABLE, I2C_InitTypeDef::AddressingMode, assert_param, I2C_InitTypeDef::ClockSpeed, I2C_InitTypeDef::DualAddressMode, I2C_InitTypeDef::DutyCycle, I2C_HandleTypeDef::ErrorCode, I2C_InitTypeDef::GeneralCallMode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MspInit(), HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_RESET, HAL_RCC_GetPCLK1Freq(), I2C_FREQRANGE, I2C_RISE_TIME, I2C_SPEED, I2C_STATE_NONE, I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, IS_I2C_ADDRESSING_MODE, IS_I2C_CLOCK_SPEED, IS_I2C_DUAL_ADDRESS, IS_I2C_DUTY_CYCLE, IS_I2C_GENERAL_CALL, IS_I2C_NO_STRETCH, IS_I2C_OWN_ADDRESS1, IS_I2C_OWN_ADDRESS2, I2C_HandleTypeDef::Lock, I2C_HandleTypeDef::Mode, I2C_InitTypeDef::NoStretchMode, I2C_InitTypeDef::OwnAddress1, I2C_InitTypeDef::OwnAddress2, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

void HAL_I2C_MspDeInit ( I2C_HandleTypeDef * hi2c )

I2C MSP DeInit.

Parameters:
hi2c,: pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 504 of file stm32f1xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit().

void HAL_I2C_MspInit ( I2C_HandleTypeDef * hi2c )

I2C MSP Init.

Parameters:
hi2c,: pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
None

Definition at line 489 of file stm32f1xx_hal_i2c.c.

Referenced by HAL_I2C_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
I2C Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) HAL_I2C_Master_Transmit()
        (++) HAL_I2C_Master_Receive()
        (++) HAL_I2C_Slave_Transmit()
        (++) HAL_I2C_Slave_Receive()
        (++) HAL_I2C_Mem_Write()
        (++) HAL_I2C_Mem_Read()
        (++) HAL_I2C_IsDeviceReady()

    (#) No-Blocking mode functions with Interrupt are :
        (++) HAL_I2C_Master_Transmit_IT()
        (++) HAL_I2C_Master_Receive_IT()
        (++) HAL_I2C_Slave_Transmit_IT()
        (++) HAL_I2C_Slave_Receive_IT()
        (++) HAL_I2C_Master_Sequential_Transmit_IT()
        (++) HAL_I2C_Master_Sequential_Receive_IT()
        (++) HAL_I2C_Slave_Sequential_Transmit_IT()
        (++) HAL_I2C_Slave_Sequential_Receive_IT()
        (++) HAL_I2C_Mem_Write_IT()
        (++) HAL_I2C_Mem_Read_IT()

    (#) No-Blocking mode functions with DMA are :
        (++) HAL_I2C_Master_Transmit_DMA()
        (++) HAL_I2C_Master_Receive_DMA()
        (++) HAL_I2C_Slave_Transmit_DMA()
        (++) HAL_I2C_Slave_Receive_DMA()
        (++) HAL_I2C_Mem_Write_DMA()
        (++) HAL_I2C_Mem_Read_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_I2C_MemTxCpltCallback()
        (++) HAL_I2C_MemRxCpltCallback()
        (++) HAL_I2C_MasterTxCpltCallback()
        (++) HAL_I2C_MasterRxCpltCallback()
        (++) HAL_I2C_SlaveTxCpltCallback()
        (++) HAL_I2C_SlaveRxCpltCallback()
        (++) HAL_I2C_ErrorCallback()
        (++) HAL_I2C_AbortCpltCallback()

Function Documentation

void HAL_I2C_AbortCpltCallback ( I2C_HandleTypeDef * hi2c )

I2C abort callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3742 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_DMAAbort(), and I2C_ITError().

void HAL_I2C_AddrCallback | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t | TransferDirection,
 |  | uint16_t | AddrMatchCode
 | ) |  |

Slave Address Match callback.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
TransferDirection | Master request Transfer Direction (Write/Read), value of I2C XferOptions definition
AddrMatchCode | Address Match Code
Return values:
None

Definition at line 3660 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_Slave_ADDR().

HAL_StatusTypeDef HAL_I2C_DisableListen_IT ( I2C_HandleTypeDef * hi2c )

Disable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 1926 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_MODE_NONE, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_IT_ERR, I2C_IT_EVT, I2C_STATE_MSK, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

HAL_StatusTypeDef HAL_I2C_EnableListen_IT ( I2C_HandleTypeDef * hi2c )

Enable the Address listen mode with Interrupt.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 1893 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_IT_ERR, I2C_IT_EVT, I2C_HandleTypeDef::Instance, and I2C_HandleTypeDef::State.

void HAL_I2C_ER_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C error interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3518 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_ARLO, HAL_I2C_ERROR_BERR, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_OVR, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_FLAG_AF, I2C_FLAG_ARLO, I2C_FLAG_BERR, I2C_FLAG_OVR, I2C_IT_ERR, I2C_ITError(), I2C_Slave_AF(), I2C_STATE_SLAVE_BUSY_TX, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

void HAL_I2C_ErrorCallback ( I2C_HandleTypeDef * hi2c )

I2C error callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3726 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_DMAAbort(), I2C_DMAError(), I2C_DMAXferCplt(), and I2C_ITError().

void HAL_I2C_EV_IRQHandler ( I2C_HandleTypeDef * hi2c )

This function handles I2C event interrupt request.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3412 of file stm32f1xx_hal_i2c.c.

References HAL_I2C_MODE_MASTER, HAL_I2C_MODE_MEM, I2C_FLAG_ADD10, I2C_FLAG_ADDR, I2C_FLAG_BTF, I2C_FLAG_RXNE, I2C_FLAG_SB, I2C_FLAG_STOPF, I2C_FLAG_TRA, I2C_FLAG_TXE, I2C_IT_BUF, I2C_IT_EVT, I2C_Master_ADD10(), I2C_Master_ADDR(), I2C_Master_SB(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_ADDR(), I2C_Slave_STOPF(), I2C_SlaveReceive_BTF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_BTF(), I2C_SlaveTransmit_TXE(), I2C_HandleTypeDef::Instance, and I2C_HandleTypeDef::Mode.

HAL_StatusTypeDef HAL_I2C_IsDeviceReady | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Trials,
 |  | uint32_t | Timeout
 | ) |  |

Checks if target device is ready for communication.

Note:
This function is used with Memory devices
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
Trials | Number of trials
Timeout | Timeout duration
Return values:
HAL status

Definition at line 3289 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_CLEAR_FLAG, __HAL_I2C_ENABLE, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_STATE_BUSY, HAL_I2C_STATE_READY, HAL_I2C_STATE_TIMEOUT, I2C_7BIT_ADD_WRITE, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_BUSY, I2C_FLAG_SB, I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

void HAL_I2C_ListenCpltCallback ( I2C_HandleTypeDef * hi2c )

Listen Complete callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3678 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_ITError(), I2C_Slave_AF(), and I2C_Slave_STOPF().

HAL_StatusTypeDef HAL_I2C_Master_Abort_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress
 | ) |  |

Abort a master I2C process communication with Interrupt.

Note:
This abort can be called only if state is ready
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
Return values:
HAL status

Definition at line 2198 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_ABORT, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_ITError(), I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

HAL_StatusTypeDef HAL_I2C_Master_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 724 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_MasterRequestRead(), I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2081 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::Devaddress, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMAXferCplt(), I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1316 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::Devaddress, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in master mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C XferOptions definition
Return values:
HAL status

Definition at line 1502 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::Devaddress, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_MASTER_BUSY_TX, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C XferOptions definition
Return values:
HAL status

Definition at line 1399 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::Devaddress, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_STATE_MASTER_BUSY_RX, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 592 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_MasterRequestWrite(), I2C_NO_OPTION_FRAME, I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1963 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::Devaddress, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMAXferCplt(), I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1239 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::Devaddress, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MASTER, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

void HAL_I2C_MasterRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3611 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_DMAXferCplt(), I2C_MasterReceive_BTF(), and I2C_MasterReceive_RXNE().

void HAL_I2C_MasterTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Master Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3595 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_MasterTransmit_BTF(), and I2C_MasterTransmit_TXE().

HAL_StatusTypeDef HAL_I2C_Mem_Read | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2570 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_NO_OPTION_FRAME, I2C_RequestMemoryRead(), I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Reads an amount of data in non-blocking mode with DMA from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be read
Return values:
HAL status

Definition at line 3129 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMAXferCplt(), I2C_FLAG_BUSY, I2C_IT_ERR, I2C_NO_OPTION_FRAME, I2C_RequestMemoryRead(), I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Read_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Read an amount of data in non-blocking mode with Interrupt from a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2919 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::Devaddress, I2C_HandleTypeDef::ErrorCode, I2C_HandleTypeDef::EventCount, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Memaddress, I2C_HandleTypeDef::MemaddSize, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 2437 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_FLAG_BUSY, I2C_NO_OPTION_FRAME, I2C_RequestMemoryWrite(), I2C_TIMEOUT_BUSY_FLAG, I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with DMA to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 3009 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMAXferCplt(), I2C_FLAG_BUSY, I2C_IT_ERR, I2C_NO_OPTION_FRAME, I2C_RequestMemoryWrite(), I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_TIMEOUT_FLAG, I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Mem_Write_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Write an amount of data in non-blocking mode with Interrupt to a specific memory address.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2834 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, assert_param, I2C_HandleTypeDef::Devaddress, I2C_HandleTypeDef::ErrorCode, I2C_HandleTypeDef::EventCount, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, IS_I2C_MEMADD_SIZE, I2C_HandleTypeDef::Memaddress, I2C_HandleTypeDef::MemaddSize, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

void HAL_I2C_MemRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3710 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_DMAXferCplt(), I2C_MasterReceive_BTF(), and I2C_MasterReceive_RXNE().

void HAL_I2C_MemTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Memory Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3694 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_MasterTransmit_BTF(), and I2C_MasterTransmit_TXE().

HAL_StatusTypeDef HAL_I2C_Slave_Receive | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 1112 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_CLEAR_STOPFLAG, __HAL_I2C_ENABLE, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_ADDR, I2C_FLAG_BTF, I2C_NO_OPTION_FRAME, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2339 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_DMAError(), I2C_DMAXferCplt(), I2C_FLAG_BUSY, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1683 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C XferOptions definition
Return values:
HAL status

Definition at line 1831 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | XferOptions
 | ) |  |

Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt.

Note:
This interface allow to manage repeated start condition when a direction change during transfer
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
pData | Pointer to data buffer
Size | Amount of data to be sent
XferOptions | Options of Transfer, value of I2C XferOptions definition
Return values:
HAL status

Definition at line 1765 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, assert_param, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_HandleTypeDef::Instance, IS_I2C_TRANSFER_OPTIONS_REQUEST, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Timeout | Timeout duration
Return values:
HAL status

Definition at line 983 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, __HAL_I2C_CLEAR_FLAG, __HAL_I2C_ENABLE, __HAL_I2C_GET_FLAG, I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_ADDRESSINGMODE_10BIT, I2C_FLAG_ADDR, I2C_FLAG_AF, I2C_FLAG_BTF, I2C_NO_OPTION_FRAME, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with DMA.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 2244 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmatx, I2C_DMAError(), I2C_DMAXferCplt(), I2C_FLAG_BUSY, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, I2C_HandleTypeDef::XferCount, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, __DMA_HandleTypeDef::XferHalfCpltCallback, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
pData | Pointer to data buffer
Size | Amount of data to be sent
Return values:
HAL status

Definition at line 1603 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE, __HAL_I2C_ENABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FLAG_BUSY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_TIMEOUT_BUSY_FLAG, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

void HAL_I2C_SlaveRxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Rx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3642 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_Slave_STOPF(), and I2C_SlaveReceive_RXNE().

void HAL_I2C_SlaveTxCpltCallback ( I2C_HandleTypeDef * hi2c )

Slave Tx Transfer completed callback.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
None

Definition at line 3626 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_Slave_AF(), and I2C_SlaveTransmit_TXE().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State, Mode and Error functions

Functions
Peripheral State, Mode and Error functions
I2C Exported Functions

Peripheral State and Errors functions. More...

Functions

HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Return the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Peripheral State and Errors functions.

 ===============================================================================
            ##### Peripheral State, Mode and Error functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

uint32_t HAL_I2C_GetError ( I2C_HandleTypeDef * hi2c )

Return the I2C error code.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
I2C Error Code

Definition at line 3800 of file stm32f1xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode.

HAL_I2C_ModeTypeDef HAL_I2C_GetMode ( I2C_HandleTypeDef * hi2c )

Return the I2C Master, Slave, Memory or no mode.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL mode

Definition at line 3789 of file stm32f1xx_hal_i2c.c.

References I2C_HandleTypeDef::Mode.

HAL_I2C_StateTypeDef HAL_I2C_GetState ( I2C_HandleTypeDef * hi2c )

Return the I2C handle state.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL state

Definition at line 3777 of file stm32f1xx_hal_i2c.c.

References I2C_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Exported Functions

Modules | Functions
I2C Exported Functions
I2C

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State, Mode and Error functions

Peripheral State and Errors functions.

Functions

static HAL_StatusTypeDef | I2C_MasterTransmit_TXE (I2C_HandleTypeDef *hi2c)
Handle TXE flag for Master.
static HAL_StatusTypeDef | I2C_MasterTransmit_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Master transmitter.
static HAL_StatusTypeDef | I2C_MasterReceive_RXNE (I2C_HandleTypeDef *hi2c)
Handle RXNE flag for Master.
static HAL_StatusTypeDef | I2C_MasterReceive_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Master receiver.
static HAL_StatusTypeDef | I2C_Master_SB (I2C_HandleTypeDef *hi2c)
Handle SB flag for Master.
static HAL_StatusTypeDef | I2C_Master_ADD10 (I2C_HandleTypeDef *hi2c)
Handle ADD10 flag for Master.
static HAL_StatusTypeDef | I2C_Master_ADDR (I2C_HandleTypeDef *hi2c)
Handle ADDR flag for Master.
static HAL_StatusTypeDef | I2C_SlaveTransmit_TXE (I2C_HandleTypeDef *hi2c)
Handle TXE flag for Slave.
static HAL_StatusTypeDef | I2C_SlaveTransmit_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Slave transmitter.
static HAL_StatusTypeDef | I2C_SlaveReceive_RXNE (I2C_HandleTypeDef *hi2c)
Handle RXNE flag for Slave.
static HAL_StatusTypeDef | I2C_SlaveReceive_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Slave receiver.
static HAL_StatusTypeDef | I2C_Slave_ADDR (I2C_HandleTypeDef *hi2c)
Handle ADD flag for Slave.
static HAL_StatusTypeDef | I2C_Slave_STOPF (I2C_HandleTypeDef *hi2c)
Handle STOPF flag for Slave.
static HAL_StatusTypeDef | I2C_Slave_AF (I2C_HandleTypeDef *hi2c)
static void | I2C_ITError (I2C_HandleTypeDef *hi2c)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_MasterRequestWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
static HAL_StatusTypeDef | I2C_MasterRequestRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address for read request.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static void | I2C_DMAXferCplt (DMA_HandleTypeDef *hdma)
DMA I2C process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnMasterAddressFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for Master addressing phase.
static HAL_StatusTypeDef | I2C_WaitOnTXEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXE flag.
static HAL_StatusTypeDef | I2C_WaitOnBTFFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of BTF flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c)
This function handles Acknowledge failed detection during an I2C Communication.

Function Documentation

static void I2C_DMAAbort ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication abort callback (To be called at end of DMA Abort procedure).

Parameters:
hdma,: DMA handle.
Return values:
None

Definition at line 5262 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE, I2C_HandleTypeDef::ErrorCode, HAL_I2C_AbortCpltCallback(), HAL_I2C_ERROR_NONE, HAL_I2C_ErrorCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_HandleTypeDef::hdmatx, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, and I2C_HandleTypeDef::XferCount.

Referenced by I2C_ITError().

static void I2C_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C communication error callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 5239 of file stm32f1xx_hal_i2c.c.

References I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_DMA, HAL_I2C_ErrorCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static void I2C_DMAXferCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA I2C process complete callback.

Parameters:
hdma DMA handle
Return values:
None

Definition at line 5175 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_ENABLE_IT, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_NONE, HAL_I2C_ErrorCallback(), HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_MODE_SLAVE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_IT_ERR, I2C_IT_EVT, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive_DMA(), and HAL_I2C_Slave_Transmit_DMA().

static HAL_StatusTypeDef I2C_IsAcknowledgeFailed ( I2C_HandleTypeDef * hi2c ) [static]

This function handles Acknowledge failed detection during an I2C Communication.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Return values:
HAL status

Definition at line 5543 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

static void I2C_ITError ( I2C_HandleTypeDef * hi2c ) [static]

I2C interrupts error process.

Parameters:
hi2c I2C handle.
Return values:
None

Definition at line 4647 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_DMA_STATE_READY, HAL_I2C_AbortCpltCallback(), HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ErrorCallback(), HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_ABORT, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_HandleTypeDef::hdmatx, I2C_DMAAbort(), I2C_FLAG_RXNE, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, __DMA_HandleTypeDef::State, I2C_HandleTypeDef::State, __DMA_HandleTypeDef::XferAbortCallback, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_Master_Abort_IT(), and I2C_Slave_STOPF().

static HAL_StatusTypeDef I2C_Master_ADD10 ( I2C_HandleTypeDef * hi2c ) [static]

Handle ADD10 flag for Master.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4203 of file stm32f1xx_hal_i2c.c.

References I2C_HandleTypeDef::Devaddress, I2C_10BIT_ADDRESS, and I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_Master_ADDR ( I2C_HandleTypeDef * hi2c ) [static]

Handle ADDR flag for Master.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4217 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::EventCount, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_RX, I2C_ADDRESSINGMODE_10BIT, I2C_FIRST_AND_LAST_FRAME, I2C_LAST_FRAME, I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, I2C_STATE_MASTER_BUSY_RX, I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_Master_SB ( I2C_HandleTypeDef * hi2c ) [static]

Handle SB flag for Master.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4151 of file stm32f1xx_hal_i2c.c.

References I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::Devaddress, I2C_HandleTypeDef::EventCount, HAL_I2C_MODE_MEM, HAL_I2C_STATE_BUSY_TX, I2C_10BIT_HEADER_READ, I2C_10BIT_HEADER_WRITE, I2C_7BIT_ADD_READ, I2C_7BIT_ADD_WRITE, I2C_ADDRESSINGMODE_7BIT, I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_MasterReceive_BTF ( I2C_HandleTypeDef * hi2c ) [static]

Handle BTF flag for Master receiver.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4066 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_IT_ERR, I2C_IT_EVT, I2C_LAST_FRAME, I2C_NEXT_FRAME, I2C_NO_OPTION_FRAME, I2C_STATE_MASTER_BUSY_RX, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_MasterReceive_RXNE ( I2C_HandleTypeDef * hi2c ) [static]

Handle RXNE flag for Master.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3989 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_MasterRxCpltCallback(), HAL_I2C_MemRxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_READY, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_NEXT_FRAME, I2C_STATE_MASTER_BUSY_RX, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_MasterRequestRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address for read request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4850 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_10BIT_ADDRESS, I2C_10BIT_HEADER_READ, I2C_10BIT_HEADER_WRITE, I2C_7BIT_ADD_READ, I2C_ADDRESSINGMODE_7BIT, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADD10, I2C_FLAG_ADDR, I2C_FLAG_SB, I2C_NO_OPTION_FRAME, I2C_STATE_MASTER_BUSY_TX, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Master_Receive().

static HAL_StatusTypeDef I2C_MasterRequestWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]
Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address: The device 7 bits address value in datasheet must be shift at right before call interface
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4774 of file stm32f1xx_hal_i2c.c.

References I2C_InitTypeDef::AddressingMode, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_10BIT_ADDRESS, I2C_10BIT_HEADER_WRITE, I2C_7BIT_ADD_WRITE, I2C_ADDRESSINGMODE_7BIT, I2C_FIRST_AND_LAST_FRAME, I2C_FIRST_FRAME, I2C_FLAG_ADD10, I2C_FLAG_ADDR, I2C_FLAG_SB, I2C_NO_OPTION_FRAME, I2C_STATE_MASTER_BUSY_RX, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_HandleTypeDef::Init, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_Master_Transmit().

static HAL_StatusTypeDef I2C_MasterTransmit_BTF ( I2C_HandleTypeDef * hi2c ) [static]

Handle BTF flag for Master transmitter.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3928 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_LAST_FRAME, I2C_NO_OPTION_FRAME, I2C_STATE_MASTER_BUSY_TX, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_MasterTransmit_TXE ( I2C_HandleTypeDef * hi2c ) [static]

Handle TXE flag for Master.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 3815 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, I2C_HandleTypeDef::EventCount, HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MemTxCpltCallback(), HAL_I2C_MODE_MEM, HAL_I2C_MODE_NONE, HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_LAST_FRAME, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_NO_OPTION_FRAME, I2C_STATE_MASTER_BUSY_TX, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Memaddress, I2C_HandleTypeDef::MemaddSize, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, I2C_HandleTypeDef::XferOptions, and I2C_HandleTypeDef::XferSize.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_RequestMemoryRead | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for read request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5048 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_7BIT_ADD_READ, I2C_7BIT_ADD_WRITE, I2C_FLAG_ADDR, I2C_FLAG_SB, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), and I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Read(), and HAL_I2C_Mem_Read_DMA().

static HAL_StatusTypeDef I2C_RequestMemoryWrite | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint16_t | DevAddress,
 |  | uint16_t | MemAddress,
 |  | uint16_t | MemAddSize,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Master sends target device address followed by internal memory address for write request.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
DevAddress | Target device address
MemAddress | Internal memory address
MemAddSize | Size of internal memory address
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 4958 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_ADDRFLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, I2C_7BIT_ADD_WRITE, I2C_FLAG_ADDR, I2C_FLAG_SB, I2C_MEM_ADD_LSB, I2C_MEM_ADD_MSB, I2C_MEMADD_SIZE_8BIT, I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnTXEFlagUntilTimeout(), and I2C_HandleTypeDef::Instance.

Referenced by HAL_I2C_Mem_Write(), and HAL_I2C_Mem_Write_DMA().

static HAL_StatusTypeDef I2C_Slave_ADDR ( I2C_HandleTypeDef * hi2c ) [static]

Handle ADD flag for Slave.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4467 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, HAL_I2C_AddrCallback(), I2C_DIRECTION_RECEIVE, I2C_DIRECTION_TRANSMIT, I2C_FLAG_DUALF, I2C_FLAG_TRA, I2C_HandleTypeDef::Init, I2C_InitTypeDef::OwnAddress1, and I2C_InitTypeDef::OwnAddress2.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_Slave_AF ( I2C_HandleTypeDef * hi2c ) [static]
Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4587 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_DISABLE_IT, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_TX, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_FIRST_AND_LAST_FRAME, I2C_FLAG_AF, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_LAST_FRAME, I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_STATE_SLAVE_BUSY_TX, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_ER_IRQHandler().

static HAL_StatusTypeDef I2C_Slave_STOPF ( I2C_HandleTypeDef * hi2c ) [static]

Handle STOPF flag for Slave.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4499 of file stm32f1xx_hal_i2c.c.

References __HAL_DMA_GET_COUNTER, __HAL_I2C_CLEAR_STOPFLAG, __HAL_I2C_DISABLE_IT, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_I2C_ERROR_AF, HAL_I2C_ERROR_NONE, HAL_I2C_ListenCpltCallback(), HAL_I2C_MODE_NONE, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_STATE_BUSY_RX, HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, HAL_I2C_STATE_READY, I2C_HandleTypeDef::hdmarx, I2C_HandleTypeDef::hdmatx, I2C_FLAG_BTF, I2C_FLAG_RXNE, I2C_IT_BUF, I2C_IT_ERR, I2C_IT_EVT, I2C_ITError(), I2C_NO_OPTION_FRAME, I2C_STATE_NONE, I2C_STATE_SLAVE_BUSY_RX, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, I2C_HandleTypeDef::XferCount, and I2C_HandleTypeDef::XferOptions.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_SlaveReceive_BTF ( I2C_HandleTypeDef * hi2c ) [static]

Handle BTF flag for Slave receiver.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4450 of file stm32f1xx_hal_i2c.c.

References I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_SlaveReceive_RXNE ( I2C_HandleTypeDef * hi2c ) [static]

Handle RXNE flag for Slave.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4417 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_SlaveRxCpltCallback(), HAL_I2C_STATE_BUSY_RX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_IT_BUF, I2C_STATE_SLAVE_BUSY_RX, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_SlaveTransmit_BTF ( I2C_HandleTypeDef * hi2c ) [static]

Handle BTF flag for Slave transmitter.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4400 of file stm32f1xx_hal_i2c.c.

References I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_SlaveTransmit_TXE ( I2C_HandleTypeDef * hi2c ) [static]

Handle TXE flag for Slave.

Parameters:
hi2c Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Return values:
HAL status

Definition at line 4367 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_DISABLE_IT, HAL_I2C_SlaveTxCpltCallback(), HAL_I2C_STATE_BUSY_TX_LISTEN, HAL_I2C_STATE_LISTEN, I2C_IT_BUF, I2C_STATE_SLAVE_BUSY_TX, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::pBuffPtr, I2C_HandleTypeDef::PreviousState, I2C_HandleTypeDef::State, and I2C_HandleTypeDef::XferCount.

Referenced by HAL_I2C_EV_IRQHandler().

static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of BTF flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5430 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_BTF, I2C_IsAcknowledgeFailed(), I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), and HAL_I2C_Mem_Write().

static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Flag | specifies the I2C flag to check.
Status | The new Flag status (SET or RESET).
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5311 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, HAL_GetTick(), HAL_I2C_MODE_NONE, HAL_I2C_STATE_READY, I2C_STATE_NONE, I2C_HandleTypeDef::Mode, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Flag,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for Master addressing phase.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for I2C module
Flag | specifies the I2C flag to check.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5345 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_AF, HAL_I2C_STATE_READY, I2C_FLAG_AF, I2C_STATE_NONE, I2C_HandleTypeDef::Instance, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of RXNE flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5501 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_CLEAR_FLAG, __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_NONE, HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_RXNE, I2C_FLAG_STOPF, I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Mem_Read(), and HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of STOP flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5467 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_STOPF, I2C_IsAcknowledgeFailed(), I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Slave_Receive().

static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout | ( | I2C_HandleTypeDef * | hi2c,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

This function handles I2C Communication Timeout for specific usage of TXE flag.

Parameters:
hi2c | Pointer to a I2C_HandleTypeDef structure that contains the configuration information for the specified I2C.
Timeout | Timeout duration
Tickstart | Tick start value
Return values:
HAL status

Definition at line 5393 of file stm32f1xx_hal_i2c.c.

References __HAL_I2C_GET_FLAG, I2C_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_I2C_ERROR_TIMEOUT, HAL_I2C_STATE_READY, I2C_FLAG_TXE, I2C_IsAcknowledgeFailed(), I2C_STATE_NONE, I2C_HandleTypeDef::PreviousState, and I2C_HandleTypeDef::State.

Referenced by HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Transmit(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Exported Types

Data Structures | Enumerations
I2C Exported Types
I2C

Data Structures

struct | I2C_InitTypeDef
I2C Configuration Structure definition. More...
struct | I2C_HandleTypeDef
I2C handle Structure definition. More...

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
HAL State structure definition. More...
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }
HAL Mode structure definition. More...

Enumeration Type Documentation

enum HAL_I2C_ModeTypeDef

HAL Mode structure definition.

Note:
HAL I2C Mode value coding follow below described bitmap : b7 (not used) x : Should be set to 0 b6 0 : None 1 : Memory (HAL I2C communication is in Memory Mode) b5 0 : None 1 : Slave (HAL I2C communication is in Slave Mode) b4 0 : None 1 : Master (HAL I2C communication is in Master Mode) b3-b2-b1-b0 (not used) xxxx : Should be set to 0000
Enumerator:
HAL_I2C_MODE_NONE

No I2C communication on going

HAL_I2C_MODE_MASTER

I2C communication is in Master Mode

HAL_I2C_MODE_SLAVE

I2C communication is in Slave Mode

HAL_I2C_MODE_MEM

I2C communication is in Memory Mode

Definition at line 154 of file stm32f1xx_hal_i2c.h.

enum HAL_I2C_StateTypeDef

HAL State structure definition.

Note:
HAL I2C State value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : Abort (Abort user request on going) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) b4 (not used) x : Should be set to 0 b3 0 : Ready or Busy (No Listen mode ongoing) 1 : Listen (IP in Address Listen Mode) b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
Enumerator:
HAL_I2C_STATE_RESET

Peripheral is not yet Initialized

HAL_I2C_STATE_READY

Peripheral Initialized and ready for use

HAL_I2C_STATE_BUSY

An internal process is ongoing

HAL_I2C_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX

Data Reception process is ongoing

HAL_I2C_STATE_LISTEN

Address Listen Mode is ongoing

HAL_I2C_STATE_BUSY_TX_LISTEN

Address Listen Mode and Data Transmission process is ongoing

HAL_I2C_STATE_BUSY_RX_LISTEN

Address Listen Mode and Data Reception process is ongoing

HAL_I2C_STATE_ABORT

Abort user request ongoing

HAL_I2C_STATE_TIMEOUT

Timeout state

HAL_I2C_STATE_ERROR

Error

Definition at line 119 of file stm32f1xx_hal_i2c.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_InitTypeDef Struct Reference
I2C Exported Types

I2C Configuration Structure definition. More...

#include <stm32f1xx_hal_i2c.h>

Data Fields

uint32_t | ClockSpeed
uint32_t | DutyCycle
uint32_t | OwnAddress1
uint32_t | AddressingMode
uint32_t | DualAddressMode
uint32_t | OwnAddress2
uint32_t | GeneralCallMode
uint32_t | NoStretchMode

Detailed Description

I2C Configuration Structure definition.

Definition at line 65 of file stm32f1xx_hal_i2c.h.

Field Documentation

uint32_t I2C_InitTypeDef::AddressingMode

Specifies if 7-bit or 10-bit addressing mode is selected. This parameter can be a value of I2C addressing mode

Definition at line 76 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), I2C_Master_ADDR(), I2C_Master_SB(), I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

uint32_t I2C_InitTypeDef::ClockSpeed

Specifies the clock frequency. This parameter must be set to a value lower than 400kHz

Definition at line 67 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::DualAddressMode

Specifies if dual addressing mode is selected. This parameter can be a value of I2C dual addressing mode

Definition at line 79 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::DutyCycle

Specifies the I2C fast mode duty cycle. This parameter can be a value of I2C duty cycle in fast mode

Definition at line 70 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::GeneralCallMode

Specifies if general call mode is selected. This parameter can be a value of I2C general call addressing mode

Definition at line 85 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::NoStretchMode

Specifies if nostretch mode is selected. This parameter can be a value of I2C nostretch mode

Definition at line 88 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

uint32_t I2C_InitTypeDef::OwnAddress1

Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.

Definition at line 73 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), and I2C_Slave_ADDR().

uint32_t I2C_InitTypeDef::OwnAddress2

Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address.

Definition at line 82 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), and I2C_Slave_ADDR().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_i2c.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
I2C_HandleTypeDef Struct Reference
I2C Exported Types

I2C handle Structure definition. More...

#include <stm32f1xx_hal_i2c.h>

Data Fields

I2C_TypeDef * | Instance
I2C_InitTypeDef Init
uint8_t * | pBuffPtr
uint16_t | XferSize
__IO uint16_t | XferCount
__IO uint32_t | XferOptions
__IO uint32_t | PreviousState
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_I2C_StateTypeDef | State
__IO HAL_I2C_ModeTypeDef | Mode
__IO uint32_t | ErrorCode
__IO uint32_t | Devaddress
__IO uint32_t | Memaddress
__IO uint32_t | MemaddSize
__IO uint32_t | EventCount

Detailed Description

I2C handle Structure definition.

Definition at line 166 of file stm32f1xx_hal_i2c.h.

Field Documentation

__IO uint32_t I2C_HandleTypeDef::Devaddress

I2C Target device address

Definition at line 195 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), I2C_Master_ADD10(), and I2C_Master_SB().

__IO uint32_t I2C_HandleTypeDef::ErrorCode

I2C Error code

Definition at line 193 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetError(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMAXferCplt(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_STOPF(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

__IO uint32_t I2C_HandleTypeDef::EventCount

I2C Event counter

Definition at line 201 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), I2C_Master_ADDR(), I2C_Master_SB(), and I2C_MasterTransmit_TXE().

DMA_HandleTypeDef* I2C_HandleTypeDef::hdmarx

I2C Rx DMA handle parameters

Definition at line 185 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive_DMA(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Slave_Receive_DMA(), I2C_DMAAbort(), I2C_ITError(), and I2C_Slave_STOPF().

DMA_HandleTypeDef* I2C_HandleTypeDef::hdmatx

I2C Tx DMA handle parameters

Definition at line 183 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Transmit_DMA(), I2C_DMAAbort(), I2C_ITError(), and I2C_Slave_STOPF().

I2C_InitTypeDef I2C_HandleTypeDef::Init

I2C communication parameters

Definition at line 170 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init(), HAL_I2C_Slave_Transmit(), I2C_Master_ADDR(), I2C_Master_SB(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), and I2C_Slave_ADDR().

I2C_TypeDef* I2C_HandleTypeDef::Instance

I2C registers base address

Definition at line 168 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMAXferCplt(), I2C_ITError(), I2C_Master_ADD10(), I2C_Master_ADDR(), I2C_Master_SB(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_BTF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_BTF(), I2C_SlaveTransmit_TXE(), and I2C_WaitOnMasterAddressFlagUntilTimeout().

HAL_LockTypeDef I2C_HandleTypeDef::Lock

I2C locking object

Definition at line 187 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

__IO uint32_t I2C_HandleTypeDef::Memaddress

I2C Target memory address

Definition at line 197 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), and I2C_MasterTransmit_TXE().

__IO uint32_t I2C_HandleTypeDef::MemaddSize

I2C Target memory address size

Definition at line 199 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), and I2C_MasterTransmit_TXE().

__IO HAL_I2C_ModeTypeDef I2C_HandleTypeDef::Mode

I2C communication mode

Definition at line 191 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_ER_IRQHandler(), HAL_I2C_EV_IRQHandler(), HAL_I2C_GetMode(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMAXferCplt(), I2C_ITError(), I2C_Master_ADDR(), I2C_Master_SB(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), I2C_Slave_STOPF(), and I2C_WaitOnFlagUntilTimeout().

uint8_t* I2C_HandleTypeDef::pBuffPtr

Pointer to I2C transfer buffer

Definition at line 172 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITError(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_STOPF(), I2C_SlaveReceive_BTF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_BTF(), and I2C_SlaveTransmit_TXE().

__IO uint32_t I2C_HandleTypeDef::PreviousState

I2C communication Previous state and mode context for internal usage

Definition at line 180 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_Master_ADDR(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_TXE(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

__IO HAL_I2C_StateTypeDef I2C_HandleTypeDef::State

I2C communication state

Definition at line 189 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_ER_IRQHandler(), HAL_I2C_GetState(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMAXferCplt(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_Master_ADDR(), I2C_Master_SB(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_TXE(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

__IO uint16_t I2C_HandleTypeDef::XferCount

I2C transfer counter

Definition at line 176 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAAbort(), I2C_DMAError(), I2C_DMAXferCplt(), I2C_Master_ADDR(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_STOPF(), I2C_SlaveReceive_BTF(), I2C_SlaveReceive_RXNE(), I2C_SlaveTransmit_BTF(), and I2C_SlaveTransmit_TXE().

__IO uint32_t I2C_HandleTypeDef::XferOptions

I2C transfer options

Definition at line 178 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITError(), I2C_Master_ADDR(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), and I2C_Slave_STOPF().

uint16_t I2C_HandleTypeDef::XferSize

I2C transfer size

Definition at line 174 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), and I2C_MasterTransmit_TXE().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_i2c.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Error Code

Defines
I2C Error Code
I2C Exported Constants

I2C Error Code. More...

Defines

#define | HAL_I2C_ERROR_NONE 0x00000000U
#define | HAL_I2C_ERROR_BERR 0x00000001U
#define | HAL_I2C_ERROR_ARLO 0x00000002U
#define | HAL_I2C_ERROR_AF 0x00000004U
#define | HAL_I2C_ERROR_OVR 0x00000008U
#define | HAL_I2C_ERROR_DMA 0x00000010U
#define | HAL_I2C_ERROR_TIMEOUT 0x00000020U

Detailed Description

I2C Error Code.

Define Documentation

#define HAL_I2C_ERROR_AF 0x00000004U

AF error

Definition at line 221 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), I2C_RequestMemoryWrite(), I2C_Slave_STOPF(), and I2C_WaitOnMasterAddressFlagUntilTimeout().

#define HAL_I2C_ERROR_ARLO 0x00000002U

ARLO error

Definition at line 220 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_BERR 0x00000001U

BERR error

Definition at line 219 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_DMA 0x00000010U

DMA transfer error

Definition at line 223 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_DMAError().

#define HAL_I2C_ERROR_NONE 0x00000000U

No error

Definition at line 218 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAAbort(), I2C_DMAXferCplt(), I2C_ITError(), I2C_Slave_STOPF(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define HAL_I2C_ERROR_OVR 0x00000008U

OVR error

Definition at line 222 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define HAL_I2C_ERROR_TIMEOUT 0x00000020U

Timeout Error

Definition at line 224 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Receive(), HAL_I2C_Mem_Read(), HAL_I2C_Slave_Receive(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C duty cycle in fast mode

Defines
I2C duty cycle in fast mode
I2C Exported Constants

Defines

#define | I2C_DUTYCYCLE_2 0x00000000U
#define | I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY

Define Documentation

#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY

Definition at line 233 of file stm32f1xx_hal_i2c.h.

#define I2C_DUTYCYCLE_2 0x00000000U

Definition at line 232 of file stm32f1xx_hal_i2c.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C addressing mode

Defines
I2C addressing mode
I2C Exported Constants

Defines

#define | I2C_ADDRESSINGMODE_7BIT 0x00004000U
#define | I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)

Define Documentation

#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)

Definition at line 242 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Transmit(), and I2C_Master_ADDR().

#define I2C_ADDRESSINGMODE_7BIT 0x00004000U

Definition at line 241 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_Master_SB(), I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C dual addressing mode

Defines
I2C dual addressing mode
I2C Exported Constants

Defines

#define | I2C_DUALADDRESS_DISABLE 0x00000000U
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL

Define Documentation

#define I2C_DUALADDRESS_DISABLE 0x00000000U

Definition at line 250 of file stm32f1xx_hal_i2c.h.

#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL

Definition at line 251 of file stm32f1xx_hal_i2c.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C general call addressing mode

Defines
I2C general call addressing mode
I2C Exported Constants

Defines

#define | I2C_GENERALCALL_DISABLE 0x00000000U
#define | I2C_GENERALCALL_ENABLE I2C_CR1_ENGC

Define Documentation

#define I2C_GENERALCALL_DISABLE 0x00000000U

Definition at line 259 of file stm32f1xx_hal_i2c.h.

#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC

Definition at line 260 of file stm32f1xx_hal_i2c.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C nostretch mode

Defines
I2C nostretch mode
I2C Exported Constants

Defines

#define | I2C_NOSTRETCH_DISABLE 0x00000000U
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Define Documentation

#define I2C_NOSTRETCH_DISABLE 0x00000000U

Definition at line 268 of file stm32f1xx_hal_i2c.h.

#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH

Definition at line 269 of file stm32f1xx_hal_i2c.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Memory Address Size

Defines
I2C Memory Address Size
I2C Exported Constants

Defines

#define | I2C_MEMADD_SIZE_8BIT 0x00000001U
#define | I2C_MEMADD_SIZE_16BIT 0x00000010U

Define Documentation

#define I2C_MEMADD_SIZE_16BIT 0x00000010U

Definition at line 278 of file stm32f1xx_hal_i2c.h.

#define I2C_MEMADD_SIZE_8BIT 0x00000001U

Definition at line 277 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_MasterTransmit_TXE(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C XferDirection definition

Defines
I2C XferDirection definition
I2C Exported Constants

Defines

#define | I2C_DIRECTION_RECEIVE 0x00000000U
#define | I2C_DIRECTION_TRANSMIT 0x00000001U

Define Documentation

#define I2C_DIRECTION_RECEIVE 0x00000000U

Definition at line 286 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_Slave_ADDR().

#define I2C_DIRECTION_TRANSMIT 0x00000001U

Definition at line 287 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_Slave_ADDR().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C XferOptions definition

Defines
I2C XferOptions definition
I2C Exported Constants

Defines

#define | I2C_FIRST_FRAME 0x00000001U
#define | I2C_NEXT_FRAME 0x00000002U
#define | I2C_FIRST_AND_LAST_FRAME 0x00000004U
#define | I2C_LAST_FRAME 0x00000008U

Define Documentation

#define I2C_FIRST_AND_LAST_FRAME 0x00000004U

Definition at line 297 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), I2C_Master_ADDR(), I2C_MasterReceive_BTF(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), and I2C_Slave_AF().

#define I2C_FIRST_FRAME 0x00000001U

Definition at line 295 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

#define I2C_LAST_FRAME 0x00000008U

Definition at line 298 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_Master_ADDR(), I2C_MasterReceive_BTF(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), and I2C_Slave_AF().

#define I2C_NEXT_FRAME 0x00000002U

Definition at line 296 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_Master_ADDR(), I2C_MasterReceive_BTF(), and I2C_MasterReceive_RXNE().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Interrupt configuration definition

Defines
I2C Interrupt configuration definition
I2C Exported Constants

Defines

#define | I2C_IT_BUF I2C_CR2_ITBUFEN
#define | I2C_IT_EVT I2C_CR2_ITEVTEN
#define | I2C_IT_ERR I2C_CR2_ITERREN

Define Documentation

#define I2C_IT_BUF I2C_CR2_ITBUFEN

Definition at line 306 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_IT(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_RXNE(), and I2C_SlaveTransmit_TXE().

#define I2C_IT_ERR I2C_CR2_ITERREN

Definition at line 308 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_ER_IRQHandler(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAXferCplt(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), and I2C_Slave_STOPF().

#define I2C_IT_EVT I2C_CR2_ITEVTEN

Definition at line 307 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_EnableListen_IT(), HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_DMAXferCplt(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), and I2C_Slave_STOPF().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Flag definition

Defines
I2C Flag definition
I2C Exported Constants

Defines

#define | I2C_FLAG_SMBALERT 0x00018000U
#define | I2C_FLAG_TIMEOUT 0x00014000U
#define | I2C_FLAG_PECERR 0x00011000U
#define | I2C_FLAG_OVR 0x00010800U
#define | I2C_FLAG_AF 0x00010400U
#define | I2C_FLAG_ARLO 0x00010200U
#define | I2C_FLAG_BERR 0x00010100U
#define | I2C_FLAG_TXE 0x00010080U
#define | I2C_FLAG_RXNE 0x00010040U
#define | I2C_FLAG_STOPF 0x00010010U
#define | I2C_FLAG_ADD10 0x00010008U
#define | I2C_FLAG_BTF 0x00010004U
#define | I2C_FLAG_ADDR 0x00010002U
#define | I2C_FLAG_SB 0x00010001U
#define | I2C_FLAG_DUALF 0x00100080U
#define | I2C_FLAG_SMBHOST 0x00100040U
#define | I2C_FLAG_SMBDEFAULT 0x00100020U
#define | I2C_FLAG_GENCALL 0x00100010U
#define | I2C_FLAG_TRA 0x00100004U
#define | I2C_FLAG_BUSY 0x00100002U
#define | I2C_FLAG_MSL 0x00100001U

Define Documentation

#define I2C_FLAG_ADD10 0x00010008U

Definition at line 326 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

#define I2C_FLAG_ADDR 0x00010002U

Definition at line 328 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_AF 0x00010400U

Definition at line 320 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_Slave_AF(), and I2C_WaitOnMasterAddressFlagUntilTimeout().

#define I2C_FLAG_ARLO 0x00010200U

Definition at line 321 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BERR 0x00010100U

Definition at line 322 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_BTF 0x00010004U

Definition at line 327 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Write(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Transmit(), I2C_Slave_STOPF(), and I2C_WaitOnBTFFlagUntilTimeout().

#define I2C_FLAG_BUSY 0x00100002U

Definition at line 335 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), and HAL_I2C_Slave_Transmit_IT().

#define I2C_FLAG_DUALF 0x00100080U

Definition at line 330 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_Slave_ADDR().

#define I2C_FLAG_GENCALL 0x00100010U

Definition at line 333 of file stm32f1xx_hal_i2c.h.

#define I2C_FLAG_MSL 0x00100001U

Definition at line 336 of file stm32f1xx_hal_i2c.h.

#define I2C_FLAG_OVR 0x00010800U

Definition at line 319 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler().

#define I2C_FLAG_PECERR 0x00011000U

Definition at line 318 of file stm32f1xx_hal_i2c.h.

#define I2C_FLAG_RXNE 0x00010040U

Definition at line 324 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), I2C_ITError(), I2C_Slave_STOPF(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define I2C_FLAG_SB 0x00010001U

Definition at line 329 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), HAL_I2C_IsDeviceReady(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_FLAG_SMBALERT 0x00018000U

Definition at line 316 of file stm32f1xx_hal_i2c.h.

#define I2C_FLAG_SMBDEFAULT 0x00100020U

Definition at line 332 of file stm32f1xx_hal_i2c.h.

#define I2C_FLAG_SMBHOST 0x00100040U

Definition at line 331 of file stm32f1xx_hal_i2c.h.

#define I2C_FLAG_STOPF 0x00010010U

Definition at line 325 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), I2C_WaitOnRXNEFlagUntilTimeout(), and I2C_WaitOnSTOPFlagUntilTimeout().

#define I2C_FLAG_TIMEOUT 0x00014000U

Definition at line 317 of file stm32f1xx_hal_i2c.h.

#define I2C_FLAG_TRA 0x00100004U

Definition at line 334 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), and I2C_Slave_ADDR().

#define I2C_FLAG_TXE 0x00010080U

Definition at line 323 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EV_IRQHandler(), and I2C_WaitOnTXEFlagUntilTimeout().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Exported Macros

Defines
I2C Exported Macros
I2C

Defines

#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified I2C interrupts.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2C interrupt source is enabled or disabled.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)
Checks whether the specified I2C flag is set or not.
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
#define | __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)
Clears the I2C ADDR pending flag.
#define | __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)
Clears the I2C STOPF pending flag.
#define | __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
Enable the I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
Disable the I2C peripheral.

Define Documentation

#define __HAL_I2C_CLEAR_ADDRFLAG ( __HANDLE__ )
Value:
do{                                           \
    __IO uint32_t tmpreg = 0x00U;               \
    tmpreg = (__HANDLE__)->Instance->SR1;       \
    tmpreg = (__HANDLE__)->Instance->SR2;       \
    UNUSED(tmpreg);                             \
  } while(0U)

Clears the I2C ADDR pending flag.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
Return values:
None

Definition at line 435 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Transmit(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), I2C_Master_ADDR(), I2C_MasterRequestRead(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define __HAL_I2C_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))

Clears the I2C pending flags which are cleared by writing 0 in a specific bit.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
__FLAG__,: specifies the flag to clear. This parameter can be any combination of the following values:
  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
  • I2C_FLAG_BERR: Bus error flag
Return values:
None

Definition at line 428 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_ER_IRQHandler(), HAL_I2C_IsDeviceReady(), HAL_I2C_Slave_Transmit(), I2C_IsAcknowledgeFailed(), I2C_Slave_AF(), I2C_WaitOnMasterAddressFlagUntilTimeout(), and I2C_WaitOnRXNEFlagUntilTimeout().

#define __HAL_I2C_CLEAR_STOPFLAG ( __HANDLE__ )
Value:
do{                                           \
    __IO uint32_t tmpreg = 0x00U;               \
    tmpreg = (__HANDLE__)->Instance->SR1;       \
    (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;  \
    UNUSED(tmpreg);                             \
  } while(0U)

Clears the I2C STOPF pending flag.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
Return values:
None

Definition at line 448 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Slave_Receive(), and I2C_Slave_STOPF().

#define __HAL_I2C_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)

Disable the I2C peripheral.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
Return values:
None

Definition at line 468 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), I2C_DMAAbort(), and I2C_ITError().

#define __HAL_I2C_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))

Definition at line 368 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_DisableListen_IT(), HAL_I2C_Master_Abort_IT(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_SlaveReceive_RXNE(), and I2C_SlaveTransmit_TXE().

#define __HAL_I2C_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)

Enable the I2C peripheral.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
Return values:
None

Definition at line 461 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Init(), HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), and HAL_I2C_Slave_Transmit_IT().

#define __HAL_I2C_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))

Enable or disable the specified I2C interrupts.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
__INTERRUPT__,: specifies the interrupt source to enable or disable. This parameter can be one of the following values:
  • I2C_IT_BUF: Buffer interrupt enable
  • I2C_IT_EVT: Event interrupt enable
  • I2C_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 367 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_EnableListen_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), and I2C_DMAXferCplt().

#define __HAL_I2C_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) |
Value:
((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
                                                 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))

Checks whether the specified I2C flag is set or not.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • I2C_FLAG_SMBALERT: SMBus Alert flag
  • I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
  • I2C_FLAG_PECERR: PEC error in reception flag
  • I2C_FLAG_OVR: Overrun/Underrun flag
  • I2C_FLAG_AF: Acknowledge failure flag
  • I2C_FLAG_ARLO: Arbitration lost flag
  • I2C_FLAG_BERR: Bus error flag
  • I2C_FLAG_TXE: Data register empty flag
  • I2C_FLAG_RXNE: Data register not empty flag
  • I2C_FLAG_STOPF: Stop detection flag
  • I2C_FLAG_ADD10: 10-bit header sent flag
  • I2C_FLAG_BTF: Byte transfer finished flag
  • I2C_FLAG_ADDR: Address sent flag Address matched flag
  • I2C_FLAG_SB: Start bit flag
  • I2C_FLAG_DUALF: Dual flag
  • I2C_FLAG_SMBHOST: SMBus host header
  • I2C_FLAG_SMBDEFAULT: SMBus default header
  • I2C_FLAG_GENCALL: General call header flag
  • I2C_FLAG_TRA: Transmitter/Receiver flag
  • I2C_FLAG_BUSY: Bus busy flag
  • I2C_FLAG_MSL: Master/Slave flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 411 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_Slave_ADDR(), I2C_Slave_STOPF(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

#define __HAL_I2C_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks if the specified I2C interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
__INTERRUPT__,: specifies the I2C interrupt source to check. This parameter can be one of the following values:
  • I2C_IT_BUF: Buffer interrupt enable
  • I2C_IT_EVT: Event interrupt enable
  • I2C_IT_ERR: Error interrupt enable
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 380 of file stm32f1xx_hal_i2c.h.

#define __HAL_I2C_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)

Reset I2C handle state.

Parameters:
__HANDLE__,: specifies the I2C Handle. This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
Return values:
None

Definition at line 355 of file stm32f1xx_hal_i2c.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Private Constants

Defines
I2C Private Constants
I2C

Defines

#define I2C_FLAG_MASK 0x0000FFFFU

Define Documentation

#define I2C_FLAG_MASK 0x0000FFFFU

Definition at line 566 of file stm32f1xx_hal_i2c.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Private macros to check input parameters

Defines
I2C Private macros to check input parameters
I2C Private Macros

Defines

#define | IS_I2C_DUTY_CYCLE(CYCLE)
#define | IS_I2C_ADDRESSING_MODE(ADDRESS)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)

Define Documentation

#define IS_I2C_ADDRESSING_MODE ( ADDRESS )
Value:
(((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))

Definition at line 599 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_CLOCK_SPEED ( SPEED ) (((SPEED) > 0) && ((SPEED) <= 400000U))

Definition at line 609 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

Definition at line 601 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_DUTY_CYCLE ( CYCLE )
Value:
(((CYCLE) == I2C_DUTYCYCLE_2) || \
                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))

Definition at line 597 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
                                   ((CALL) == I2C_GENERALCALL_ENABLE))

Definition at line 603 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_MEMADD_SIZE ( SIZE )
Value:
(((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))

Definition at line 607 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), and HAL_I2C_Mem_Write_IT().

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
                                    ((STRETCH) == I2C_NOSTRETCH_ENABLE))

Definition at line 605 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS1 ( ADDRESS1 ) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)

Definition at line 610 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_OWN_ADDRESS2 ( ADDRESS2 ) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)

Definition at line 611 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define IS_I2C_TRANSFER_OPTIONS_REQUEST ( REQUEST )
Value:
(((REQUEST) == I2C_FIRST_FRAME)              || \
                                                       ((REQUEST) == I2C_NEXT_FRAME)               || \
                                                       ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
                                                       ((REQUEST) == I2C_LAST_FRAME))

Definition at line 612 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), and HAL_I2C_Slave_Sequential_Transmit_IT().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Private Macros

Modules | Defines
I2C Private Macros
I2C

Modules

I2C Private macros to check input parameters

Defines

#define | I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
#define | I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
#define | I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
#define | I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
#define | I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)
#define | I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define | I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
#define | I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
#define | I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Define Documentation

#define I2C_10BIT_ADDRESS ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 587 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_Master_ADD10(), I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

#define I2C_10BIT_HEADER_READ ( __ADDRESS__ ) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))

Definition at line 589 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_Master_SB(), and I2C_MasterRequestRead().

#define I2C_10BIT_HEADER_WRITE ( __ADDRESS__ ) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))

Definition at line 588 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_Master_SB(), I2C_MasterRequestRead(), and I2C_MasterRequestWrite().

#define I2C_7BIT_ADD_READ ( __ADDRESS__ ) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))

Definition at line 585 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_Master_SB(), I2C_MasterRequestRead(), and I2C_RequestMemoryRead().

#define I2C_7BIT_ADD_WRITE ( __ADDRESS__ ) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))

Definition at line 584 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_IsDeviceReady(), I2C_Master_SB(), I2C_MasterRequestWrite(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_FREQRANGE ( __PCLK__ ) ((__PCLK__)/1000000U)

Definition at line 576 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

Definition at line 592 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_MasterTransmit_TXE(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_MEM_ADD_MSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))

Definition at line 591 of file stm32f1xx_hal_i2c.h.

Referenced by I2C_MasterTransmit_TXE(), I2C_RequestMemoryRead(), and I2C_RequestMemoryWrite().

#define I2C_RISE_TIME | ( | __FREQRANGE__,
 |  | __SPEED__
 | ) | (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))

Definition at line 577 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define I2C_SPEED | ( | __PCLK__,
 |  | __SPEED__,
 |  | __DUTYCYCLE__
 | ) |
Value:
(((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))

Definition at line 580 of file stm32f1xx_hal_i2c.h.

Referenced by HAL_I2C_Init().

#define I2C_SPEED_FAST | ( | __PCLK__,
 |  | __SPEED__,
 |  | __DUTYCYCLE__
 | ) | (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))

Definition at line 579 of file stm32f1xx_hal_i2c.h.

#define I2C_SPEED_STANDARD | ( | __PCLK__,
 |  | __SPEED__
 | ) | (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))

Definition at line 578 of file stm32f1xx_hal_i2c.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C Private Functions

I2C Private Functions
I2C
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2C_Private_Define

Defines
I2C_Private_Define
I2C

Defines

#define | I2C_TIMEOUT_FLAG 35U
#define | I2C_TIMEOUT_BUSY_FLAG 25U
#define | I2C_NO_OPTION_FRAME 0xFFFF0000U
#define | I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY)))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Define Documentation

#define I2C_NO_OPTION_FRAME 0xFFFF0000U

XferOptions default value

Definition at line 269 of file stm32f1xx_hal_i2c.c.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_ITError(), I2C_Master_ADDR(), I2C_MasterReceive_BTF(), I2C_MasterRequestRead(), I2C_MasterRequestWrite(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), and I2C_Slave_STOPF().

#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))

Master Busy RX, combinaison of State LSB and Mode enum

Definition at line 275 of file stm32f1xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Sequential_Transmit_IT(), I2C_Master_ADDR(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), and I2C_MasterRequestWrite().

#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))

Master Busy TX, combinaison of State LSB and Mode enum

Definition at line 274 of file stm32f1xx_hal_i2c.c.

Referenced by HAL_I2C_Master_Sequential_Receive_IT(), I2C_MasterRequestRead(), I2C_MasterTransmit_BTF(), and I2C_MasterTransmit_TXE().

#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY)))

Mask State define, keep only RX and TX bits

Definition at line 272 of file stm32f1xx_hal_i2c.c.

Referenced by HAL_I2C_DisableListen_IT().

#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))

Default Value

Definition at line 273 of file stm32f1xx_hal_i2c.c.

Referenced by HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Master_Abort_IT(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), HAL_I2C_Slave_Transmit_IT(), I2C_IsAcknowledgeFailed(), I2C_ITError(), I2C_MasterReceive_BTF(), I2C_MasterReceive_RXNE(), I2C_MasterTransmit_BTF(), I2C_MasterTransmit_TXE(), I2C_Slave_AF(), I2C_Slave_STOPF(), I2C_WaitOnBTFFlagUntilTimeout(), I2C_WaitOnFlagUntilTimeout(), I2C_WaitOnMasterAddressFlagUntilTimeout(), I2C_WaitOnRXNEFlagUntilTimeout(), I2C_WaitOnSTOPFlagUntilTimeout(), and I2C_WaitOnTXEFlagUntilTimeout().

#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Slave Busy RX, combinaison of State LSB and Mode enum

Definition at line 277 of file stm32f1xx_hal_i2c.c.

Referenced by I2C_Slave_STOPF(), and I2C_SlaveReceive_RXNE().

#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Slave Busy TX, combinaison of State LSB and Mode enum

Definition at line 276 of file stm32f1xx_hal_i2c.c.

Referenced by HAL_I2C_ER_IRQHandler(), I2C_Slave_AF(), and I2C_SlaveTransmit_TXE().

#define I2C_TIMEOUT_BUSY_FLAG 25U

Timeout 25 ms

Definition at line 268 of file stm32f1xx_hal_i2c.c.

Referenced by HAL_I2C_IsDeviceReady(), HAL_I2C_Master_Receive(), HAL_I2C_Master_Receive_DMA(), HAL_I2C_Master_Receive_IT(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Master_Transmit(), HAL_I2C_Master_Transmit_DMA(), HAL_I2C_Master_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Receive_DMA(), HAL_I2C_Slave_Receive_IT(), HAL_I2C_Slave_Transmit_DMA(), and HAL_I2C_Slave_Transmit_IT().

#define I2C_TIMEOUT_FLAG 35U

Timeout 35 ms

Definition at line 267 of file stm32f1xx_hal_i2c.c.

Referenced by HAL_I2C_Mem_Read_DMA(), and HAL_I2C_Mem_Write_DMA().

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IrDA Initialization and de-initialization functions

Functions
IrDA Initialization and de-initialization functions
IrDA Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitializes the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
IRDA MSP Init.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
IRDA MSP DeInit.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
            ##### Initialization and Configuration functions #####
  ==============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in IrDA mode.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) BaudRate
        (++) WordLength
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
             Depending on the frame length defined by the M bit (8-bits or 9-bits),
             please refer to Reference manual for possible IRDA frame formats.
        (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
             not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
             specification specifies a minimum of 10 ms delay between transmission and
             reception (IrDA is a half duplex protocol).
        (++) Mode: Receiver/transmitter modes
        (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
    [..]
    The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
    are available in reference manual).

Function Documentation

HAL_StatusTypeDef HAL_IRDA_DeInit ( IRDA_HandleTypeDef * hirda )

DeInitializes the IRDA peripheral.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 303 of file stm32f1xx_hal_irda.c.

References __HAL_IRDA_DISABLE, assert_param, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspDeInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_Init ( IRDA_HandleTypeDef * hirda )

Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 244 of file stm32f1xx_hal_irda.c.

References __HAL_IRDA_DISABLE, __HAL_IRDA_ENABLE, assert_param, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_MspInit(), HAL_IRDA_STATE_BUSY, HAL_IRDA_STATE_READY, HAL_IRDA_STATE_RESET, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_SetConfig(), IRDA_InitTypeDef::IrDAMode, IRDA_HandleTypeDef::Lock, IRDA_InitTypeDef::Prescaler, and IRDA_HandleTypeDef::RxState.

void HAL_IRDA_MspDeInit ( IRDA_HandleTypeDef * hirda )

IRDA MSP DeInit.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 353 of file stm32f1xx_hal_irda.c.

Referenced by HAL_IRDA_DeInit().

void HAL_IRDA_MspInit ( IRDA_HandleTypeDef * hirda )

IRDA MSP Init.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 338 of file stm32f1xx_hal_irda.c.

Referenced by HAL_IRDA_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
IrDA Exported Functions

IRDA Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stops the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
This function handles IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer complete callbacks.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callbacks.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer complete callbacks.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callbacks.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callbacks.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Transmit Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort ReceiveComplete callback.

Detailed Description

IRDA Transmit and Receive functions.

  ==============================================================================
                         ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the IRDA data transfers.
    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
    While receiving data, transmission should be avoided as the data to be transmitted
    could be corrupted.

    (#) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode: The communication is performed using Interrupts
             or DMA, these APIs return the HAL status.
             The end of the data processing will be indicated through the
             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
             will be executed respectively at the end of the transmit or Receive process
             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication
             error is detected

    (#) Blocking mode APIs are:
        (++) HAL_IRDA_Transmit()
        (++) HAL_IRDA_Receive()

    (#) Non Blocking mode APIs with Interrupt are:
        (++) HAL_IRDA_Transmit_IT()
        (++) HAL_IRDA_Receive_IT()
        (++) HAL_IRDA_IRQHandler()

    (#) Non Blocking mode functions with DMA are:
        (++) HAL_IRDA_Transmit_DMA()
        (++) HAL_IRDA_Receive_DMA()
        (++) HAL_IRDA_DMAPause()
        (++) HAL_IRDA_DMAResume()
        (++) HAL_IRDA_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_IRDA_TxHalfCpltCallback()
        (++) HAL_IRDA_TxCpltCallback()
        (++) HAL_IRDA_RxHalfCpltCallback()
        (++) HAL_IRDA_RxCpltCallback()
        (++) HAL_IRDA_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_IRDA_Abort ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (blocking mode).

Parameters:
hirda IRDA handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 945 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Abort_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing transfers (Interrupt mode).

Parameters:
hirda IRDA handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1096 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Complete callback.

Parameters:
hirda IRDA handle.
Return values:
None

Definition at line 1542 of file stm32f1xx_hal_irda.c.

Referenced by HAL_IRDA_Abort_IT(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

HAL_StatusTypeDef HAL_IRDA_AbortReceive ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hirda IRDA handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1051 of file stm32f1xx_hal_irda.c.

References HAL_DMA_Abort(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hirda IRDA handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1283 of file stm32f1xx_hal_irda.c.

References HAL_DMA_Abort_IT(), HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_DMARxOnlyAbortCallback(), IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortReceiveCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort ReceiveComplete callback.

Parameters:
hirda IRDA handle.
Return values:
None

Definition at line 1572 of file stm32f1xx_hal_irda.c.

Referenced by HAL_IRDA_AbortReceive_IT(), and IRDA_DMARxOnlyAbortCallback().

HAL_StatusTypeDef HAL_IRDA_AbortTransmit ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hirda IRDA handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1009 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT ( IRDA_HandleTypeDef * hirda )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hirda IRDA handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1218 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_DMATxOnlyAbortCallback(), IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_IRDA_AbortTransmitCpltCallback ( IRDA_HandleTypeDef * hirda )

IRDA Abort Transmit Complete callback.

Parameters:
hirda IRDA handle.
Return values:
None

Definition at line 1557 of file stm32f1xx_hal_irda.c.

Referenced by HAL_IRDA_AbortTransmit_IT(), and IRDA_DMATxOnlyAbortCallback().

HAL_StatusTypeDef HAL_IRDA_DMAPause ( IRDA_HandleTypeDef * hirda )

Pauses the DMA Transfer.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 820 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAResume ( IRDA_HandleTypeDef * hirda )

Resumes the DMA Transfer.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 857 of file stm32f1xx_hal_irda.c.

References __HAL_IRDA_CLEAR_OREFLAG, IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_IRDA_DMAStop ( IRDA_HandleTypeDef * hirda )

Stops the DMA Transfer.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 893 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), and IRDA_HandleTypeDef::RxState.

void HAL_IRDA_ErrorCallback ( IRDA_HandleTypeDef * hirda )

IRDA error callbacks.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1528 of file stm32f1xx_hal_irda.c.

Referenced by HAL_IRDA_IRQHandler(), IRDA_DMAAbortOnError(), and IRDA_DMAError().

void HAL_IRDA_IRQHandler ( IRDA_HandleTypeDef * hirda )

This function handles IRDA interrupt request.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1341 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_IRDA_ERROR_FE, HAL_IRDA_ERROR_NE, HAL_IRDA_ERROR_NONE, HAL_IRDA_ERROR_ORE, HAL_IRDA_ERROR_PE, HAL_IRDA_ErrorCallback(), IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_DMAAbortOnError(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_Receive_IT(), IRDA_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_IRDA_Receive | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 513 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_RXNE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::RxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Receive_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Note:
When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
Return values:
HAL status

Definition at line 753 of file stm32f1xx_hal_irda.c.

References __HAL_IRDA_CLEAR_OREFLAG, IRDA_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMAReceiveHalfCplt(), IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Receive_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 640 of file stm32f1xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, IRDA_HandleTypeDef::ErrorCode, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::RxXferSize.

void HAL_IRDA_RxCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Transfer complete callbacks.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1498 of file stm32f1xx_hal_irda.c.

Referenced by IRDA_DMAReceiveCplt(), and IRDA_Receive_IT().

void HAL_IRDA_RxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Rx Half Transfer complete callbacks.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1513 of file stm32f1xx_hal_irda.c.

Referenced by IRDA_DMAReceiveHalfCplt().

HAL_StatusTypeDef HAL_IRDA_Transmit | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Sends an amount of data in blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Specify timeout value
Return values:
HAL status

Definition at line 431 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_FLAG_TC, IRDA_FLAG_TXE, IRDA_PARITY_NONE, IRDA_WaitOnFlagUntilTimeout(), IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, and IRDA_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_IRDA_Transmit_DMA | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Sends an amount of data in non blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 688 of file stm32f1xx_hal_irda.c.

References __HAL_IRDA_CLEAR_FLAG, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::Instance, IRDA_DMAError(), IRDA_DMATransmitCplt(), IRDA_DMATransmitHalfCplt(), IRDA_FLAG_TC, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, IRDA_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_IRDA_Transmit_IT | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Sends an amount of data in non blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 599 of file stm32f1xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_BUSY_TX, HAL_IRDA_STATE_READY, IRDA_IT_TXE, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, and IRDA_HandleTypeDef::TxXferSize.

void HAL_IRDA_TxCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Transfer complete callbacks.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 1468 of file stm32f1xx_hal_irda.c.

Referenced by IRDA_DMATransmitCplt(), and IRDA_EndTransmit_IT().

void HAL_IRDA_TxHalfCpltCallback ( IRDA_HandleTypeDef * hirda )

Tx Half Transfer completed callbacks.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1483 of file stm32f1xx_hal_irda.c.

Referenced by IRDA_DMATransmitHalfCplt().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
IrDA Exported Functions

IRDA State and Errors functions. More...

Functions

HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Returns the IRDA state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA error code.

Detailed Description

IRDA State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of IrDA
    communication process and also return Peripheral Errors occurred during communication process
     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
     (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.

Function Documentation

uint32_t HAL_IRDA_GetError ( IRDA_HandleTypeDef * hirda )

Return the IRDA error code.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
IRDA Error Code

Definition at line 1624 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode.

HAL_IRDA_StateTypeDef HAL_IRDA_GetState ( IRDA_HandleTypeDef * hirda )

Returns the IRDA state.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL state

Definition at line 1609 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, and IRDA_HandleTypeDef::RxState.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IrDA Exported Functions

Modules | Functions
IrDA Exported Functions
IRDA

Modules

IrDA Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

IRDA Transmit and Receive functions.

Peripheral State and Errors functions

IRDA State and Errors functions.

Functions

static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receives an amount of data in non blocking mode.
static void | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configures the IRDA peripheral.

Function Documentation

static void IRDA_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1816 of file stm32f1xx_hal_irda.c.

References HAL_IRDA_ErrorCallback(), IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1718 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_ERROR_DMA, HAL_IRDA_ErrorCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Instance, IRDA_EndRxTransfer(), IRDA_EndTxTransfer(), IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Receive_DMA(), and HAL_IRDA_Transmit_DMA().

static void IRDA_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1679 of file stm32f1xx_hal_irda.c.

References HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_READY, __DMA_HandleTypeDef::Instance, IRDA_HandleTypeDef::Instance, IRDA_HandleTypeDef::RxState, and IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMAReceiveHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1707 of file stm32f1xx_hal_irda.c.

References HAL_IRDA_RxHalfCpltCallback().

Referenced by HAL_IRDA_Receive_DMA().

static void IRDA_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1871 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1930 of file stm32f1xx_hal_irda.c.

References HAL_IRDA_AbortReceiveCpltCallback(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::RxState, and IRDA_HandleTypeDef::RxXferCount.

Referenced by HAL_IRDA_AbortReceive_IT().

static void IRDA_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA transmit process complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1639 of file stm32f1xx_hal_irda.c.

References __HAL_IRDA_ENABLE_IT, HAL_IRDA_TxCpltCallback(), __DMA_HandleTypeDef::Instance, IRDA_HandleTypeDef::Instance, IRDA_IT_TC, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATransmitHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA receive process half complete callback.

Parameters:
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1667 of file stm32f1xx_hal_irda.c.

References HAL_IRDA_TxHalfCpltCallback().

Referenced by HAL_IRDA_Transmit_DMA().

static void IRDA_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1833 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::ErrorCode, IRDA_HandleTypeDef::gState, HAL_IRDA_AbortCpltCallback(), HAL_IRDA_ERROR_NONE, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::hdmarx, IRDA_HandleTypeDef::hdmatx, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, IRDA_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_IRDA_Abort_IT().

static void IRDA_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1909 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_AbortTransmitCpltCallback(), HAL_IRDA_STATE_READY, and IRDA_HandleTypeDef::TxXferCount.

Referenced by HAL_IRDA_AbortTransmit_IT().

static void IRDA_EndRxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).

Parameters:
hirda,: IRDA handle.
Return values:
None

Definition at line 1800 of file stm32f1xx_hal_irda.c.

References HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), and IRDA_DMAError().

static HAL_StatusTypeDef IRDA_EndTransmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Wraps up transmission in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1996 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, HAL_IRDA_TxCpltCallback(), and IRDA_HandleTypeDef::Instance.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_EndTxTransfer ( IRDA_HandleTypeDef * hirda ) [static]

End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).

Parameters:
hirda,: IRDA handle.
Return values:
None

Definition at line 1786 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_READY, and IRDA_HandleTypeDef::Instance.

Referenced by HAL_IRDA_DMAStop(), and IRDA_DMAError().

static HAL_StatusTypeDef IRDA_Receive_IT ( IRDA_HandleTypeDef * hirda ) [static]

Receives an amount of data in non blocking mode.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 2014 of file stm32f1xx_hal_irda.c.

References __HAL_IRDA_DISABLE_IT, HAL_IRDA_RxCpltCallback(), HAL_IRDA_STATE_BUSY_RX, HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_IT_ERR, IRDA_IT_PE, IRDA_IT_RXNE, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pRxBuffPtr, IRDA_HandleTypeDef::RxState, IRDA_HandleTypeDef::RxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static void IRDA_SetConfig ( IRDA_HandleTypeDef * hirda ) [static]

Configures the IRDA peripheral.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
None

Definition at line 2080 of file stm32f1xx_hal_irda.c.

References assert_param, IRDA_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_BRR, IRDA_InitTypeDef::IrDAMode, IS_IRDA_BAUDRATE, IS_IRDA_MODE, IS_IRDA_PARITY, IS_IRDA_POWERMODE, IS_IRDA_WORD_LENGTH, IRDA_InitTypeDef::Mode, IRDA_InitTypeDef::Parity, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_Init().

static HAL_StatusTypeDef IRDA_Transmit_IT ( IRDA_HandleTypeDef * hirda ) [static]

Send an amount of data in non blocking mode.

Parameters:
hirda,: pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Return values:
HAL status

Definition at line 1949 of file stm32f1xx_hal_irda.c.

References IRDA_HandleTypeDef::gState, HAL_IRDA_STATE_BUSY_TX, IRDA_HandleTypeDef::Init, IRDA_HandleTypeDef::Instance, IRDA_PARITY_NONE, IRDA_WORDLENGTH_9B, IRDA_InitTypeDef::Parity, IRDA_HandleTypeDef::pTxBuffPtr, IRDA_HandleTypeDef::TxXferCount, and IRDA_InitTypeDef::WordLength.

Referenced by HAL_IRDA_IRQHandler().

static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout | ( | IRDA_HandleTypeDef * | hirda,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles IRDA Communication Timeout.

Parameters:
hirda,: Pointer to a IRDA_HandleTypeDef structure that contains the configuration information for the specified IRDA module.
Flag,: specifies the IRDA flag to check.
Status,: The new Flag status (SET or RESET).
Tickstart,: Tick start value
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1754 of file stm32f1xx_hal_irda.c.

References __HAL_IRDA_GET_FLAG, IRDA_HandleTypeDef::gState, HAL_GetTick(), HAL_IRDA_STATE_READY, IRDA_HandleTypeDef::Instance, and IRDA_HandleTypeDef::RxState.

Referenced by HAL_IRDA_Receive(), and HAL_IRDA_Transmit().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Exported Types

Data Structures | Enumerations
IRDA Exported Types
IRDA

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00U, HAL_IRDA_STATE_READY = 0x20U, HAL_IRDA_STATE_BUSY = 0x24U, HAL_IRDA_STATE_BUSY_TX = 0x21U,
HAL_IRDA_STATE_BUSY_RX = 0x22U, HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, HAL_IRDA_STATE_TIMEOUT = 0xA0U, HAL_IRDA_STATE_ERROR = 0xE0U
}
HAL IRDA State structures definition. More...

Enumeration Type Documentation

enum HAL_IRDA_StateTypeDef

HAL IRDA State structures definition.

Note:
HAL IRDA State value is a combination of 2 different substates: gState and RxState.
  • gState contains IRDA state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL IRDA Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_IRDA_STATE_RESET

Peripheral is not yet Initialized Value is allowed for gState and RxState

HAL_IRDA_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_IRDA_STATE_BUSY

An internal process is ongoing Value is allowed for gState only

HAL_IRDA_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_IRDA_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_IRDA_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_IRDA_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_IRDA_STATE_ERROR

Error Value is allowed for gState only

Definition at line 134 of file stm32f1xx_hal_irda.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_InitTypeDef Struct Reference
IRDA Exported Types

IRDA Init Structure definition. More...

#include <stm32f1xx_hal_irda.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | Parity
uint32_t | Mode
uint8_t | Prescaler
uint32_t | IrDAMode

Detailed Description

IRDA Init Structure definition.

Definition at line 65 of file stm32f1xx_hal_irda.h.

Field Documentation

uint32_t IRDA_InitTypeDef::BaudRate

This member configures the IRDA communication baud rate. The baud rate is computed using the following formula:

  • IntegerDivider = ((PCLKx) / (16 * (hirda->Init.BaudRate)))
  • FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5

Definition at line 67 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::IrDAMode

Specifies the IrDA mode This parameter can be a value of IRDA Low Power

Definition at line 91 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Init(), and IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of IRDA Transfer Mode

Definition at line 83 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_SetConfig().

uint32_t IRDA_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of IRDA Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 76 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

uint8_t IRDA_InitTypeDef::Prescaler

Specifies the Prescaler value prescaler value to be programmed in the IrDA low-power Baud Register, for defining pulse width on which burst acceptance/rejection will be decided. This value is used as divisor of system clock to achieve required pulse width.

Definition at line 86 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint32_t IRDA_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of IRDA Word Length

Definition at line 72 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_irda.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IRDA_HandleTypeDef Struct Reference
IRDA Exported Types

IRDA handle Structure definition. More...

#include <stm32f1xx_hal_irda.h>

Data Fields

USART_TypeDef * | Instance
IRDA_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_IRDA_StateTypeDef | gState
__IO HAL_IRDA_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

IRDA handle Structure definition.

Definition at line 158 of file stm32f1xx_hal_irda.h.

Field Documentation

__IO uint32_t IRDA_HandleTypeDef::ErrorCode

IRDA Error code

Definition at line 189 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_DeInit(), HAL_IRDA_GetError(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::gState

IRDA state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 182 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmarx

IRDA Rx DMA Handle parameters

Definition at line 178 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

DMA_HandleTypeDef* IRDA_HandleTypeDef::hdmatx

IRDA Tx DMA Handle parameters

Definition at line 176 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DMAStop(), HAL_IRDA_Transmit_DMA(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

IRDA_InitTypeDef IRDA_HandleTypeDef::Init

IRDA communication parameters

Definition at line 162 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Init(), HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), IRDA_SetConfig(), and IRDA_Transmit_IT().

USART_TypeDef* IRDA_HandleTypeDef::Instance

USART registers base address

Definition at line 160 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMATransmitCplt(), IRDA_EndRxTransfer(), IRDA_EndTransmit_IT(), IRDA_EndTxTransfer(), IRDA_Receive_IT(), IRDA_SetConfig(), IRDA_Transmit_IT(), and IRDA_WaitOnFlagUntilTimeout().

HAL_LockTypeDef IRDA_HandleTypeDef::Lock

Locking object

Definition at line 180 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

uint8_t* IRDA_HandleTypeDef::pRxBuffPtr

Pointer to IRDA Rx transfer Buffer

Definition at line 170 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

uint8_t* IRDA_HandleTypeDef::pTxBuffPtr

Pointer to IRDA Tx transfer Buffer

Definition at line 164 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), and IRDA_Transmit_IT().

__IO HAL_IRDA_StateTypeDef IRDA_HandleTypeDef::RxState

IRDA state information related to Rx operations. This parameter can be a value of HAL_IRDA_StateTypeDef

Definition at line 186 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_DeInit(), HAL_IRDA_DMAPause(), HAL_IRDA_DMAResume(), HAL_IRDA_DMAStop(), HAL_IRDA_GetState(), HAL_IRDA_Init(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), IRDA_EndRxTransfer(), IRDA_Receive_IT(), and IRDA_WaitOnFlagUntilTimeout().

__IO uint16_t IRDA_HandleTypeDef::RxXferCount

IRDA Rx Transfer Counter

Definition at line 174 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortReceive(), HAL_IRDA_AbortReceive_IT(), HAL_IRDA_Receive(), HAL_IRDA_Receive_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMAReceiveCplt(), IRDA_DMARxAbortCallback(), IRDA_DMARxOnlyAbortCallback(), IRDA_DMATxAbortCallback(), and IRDA_Receive_IT().

uint16_t IRDA_HandleTypeDef::RxXferSize

IRDA Rx Transfer size

Definition at line 172 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), and HAL_IRDA_Receive_IT().

__IO uint16_t IRDA_HandleTypeDef::TxXferCount

IRDA Tx Transfer Counter

Definition at line 168 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_AbortTransmit(), HAL_IRDA_AbortTransmit_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMAAbortOnError(), IRDA_DMAError(), IRDA_DMARxAbortCallback(), IRDA_DMATransmitCplt(), IRDA_DMATxAbortCallback(), IRDA_DMATxOnlyAbortCallback(), and IRDA_Transmit_IT().

uint16_t IRDA_HandleTypeDef::TxXferSize

IRDA Tx Transfer size

Definition at line 166 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), and HAL_IRDA_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_irda.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Error Code

Defines
IRDA Error Code
IRDA Exported constants

Defines

#define | HAL_IRDA_ERROR_NONE 0x00000000U
#define | HAL_IRDA_ERROR_PE 0x00000001U
#define | HAL_IRDA_ERROR_NE 0x00000002U
#define | HAL_IRDA_ERROR_FE 0x00000004U
#define | HAL_IRDA_ERROR_ORE 0x00000008U
#define | HAL_IRDA_ERROR_DMA 0x00000010U

Define Documentation

#define HAL_IRDA_ERROR_DMA 0x00000010U

DMA transfer error

Definition at line 208 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_DMAError().

#define HAL_IRDA_ERROR_FE 0x00000004U

Frame error

Definition at line 206 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NE 0x00000002U

Noise error

Definition at line 205 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_NONE 0x00000000U

No error

Definition at line 203 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Abort(), HAL_IRDA_Abort_IT(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IRDA_IRQHandler(), HAL_IRDA_Receive(), HAL_IRDA_Receive_DMA(), HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit(), HAL_IRDA_Transmit_DMA(), HAL_IRDA_Transmit_IT(), IRDA_DMARxAbortCallback(), and IRDA_DMATxAbortCallback().

#define HAL_IRDA_ERROR_ORE 0x00000008U

Overrun error

Definition at line 207 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

#define HAL_IRDA_ERROR_PE 0x00000001U

Parity error

Definition at line 204 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_IRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Word Length

Defines
IRDA Word Length
IRDA Exported constants

Defines

#define | IRDA_WORDLENGTH_8B 0x00000000U
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define IRDA_WORDLENGTH_8B 0x00000000U

Definition at line 216 of file stm32f1xx_hal_irda.h.

#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Definition at line 217 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Parity

Defines
IRDA Parity
IRDA Exported constants

Defines

#define | IRDA_PARITY_NONE 0x00000000U
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 226 of file stm32f1xx_hal_irda.h.

#define IRDA_PARITY_NONE 0x00000000U

Definition at line 225 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive(), HAL_IRDA_Transmit(), IRDA_Receive_IT(), and IRDA_Transmit_IT().

#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 227 of file stm32f1xx_hal_irda.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Transfer Mode

Defines
IRDA Transfer Mode
IRDA Exported constants

Defines

#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 235 of file stm32f1xx_hal_irda.h.

#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 236 of file stm32f1xx_hal_irda.h.

#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 237 of file stm32f1xx_hal_irda.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Low Power

Defines
IRDA Low Power
IRDA Exported constants

Defines

#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define | IRDA_POWERMODE_NORMAL 0x00000000U

Define Documentation

#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)

Definition at line 245 of file stm32f1xx_hal_irda.h.

#define IRDA_POWERMODE_NORMAL 0x00000000U

Definition at line 246 of file stm32f1xx_hal_irda.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Flags

Defines
IRDA Flags
IRDA Exported constants

Elements values convention: 0xXXXX. More...

Defines

#define | IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define | IRDA_FLAG_TC ((uint32_t)USART_SR_TC)
#define | IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define | IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define | IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define | IRDA_FLAG_NE ((uint32_t)USART_SR_NE)
#define | IRDA_FLAG_FE ((uint32_t)USART_SR_FE)
#define | IRDA_FLAG_PE ((uint32_t)USART_SR_PE)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the SR register

Define Documentation

#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE)

Definition at line 262 of file stm32f1xx_hal_irda.h.

#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE)

Definition at line 259 of file stm32f1xx_hal_irda.h.

#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE)

Definition at line 261 of file stm32f1xx_hal_irda.h.

#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE)

Definition at line 260 of file stm32f1xx_hal_irda.h.

#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE)

Definition at line 263 of file stm32f1xx_hal_irda.h.

#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE)

Definition at line 258 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive().

#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC)

Definition at line 257 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit(), and HAL_IRDA_Transmit_DMA().

#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE)

Definition at line 256 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Interrupt Definitions

Defines
IRDA Interrupt Definitions
IRDA Exported constants

Elements values convention: 0xY000XXXX. More...

Defines

#define | IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Detailed Description

Elements values convention: 0xY000XXXX.

  • XXXX : Interrupt mask in the XX register
  • Y : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register

Define Documentation

#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))

Definition at line 285 of file stm32f1xx_hal_irda.h.

#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Definition at line 286 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))

Definition at line 281 of file stm32f1xx_hal_irda.h.

#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))

Definition at line 283 of file stm32f1xx_hal_irda.h.

#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))

Definition at line 277 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))

Definition at line 280 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_IT(), and IRDA_Receive_IT().

#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))

Definition at line 279 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_DMATransmitCplt().

#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))

Definition at line 278 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_IT().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Exported Macros

Defines
IRDA Exported Macros
IRDA

Defines

#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle gstate & RxState.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flush the IRDA DR register.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
Disable UART/USART associated to IRDA Handle.

Define Documentation

#define __HAL_IRDA_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)

Clear the IRDA FE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 374 of file stm32f1xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the specified IRDA pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • IRDA_FLAG_TC: Transmission Complete flag.
  • IRDA_FLAG_RXNE: Receive data register not empty flag.
Note:
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register followed by a read operation to USART_DR register.
RXNE flag can be also cleared by a read to the USART_DR register.
TC flag can be also cleared by software sequence: a read operation to USART_SR register followed by a write operation to USART_DR register.
TXE flag is cleared only by a write to the USART_DR register.

Definition at line 354 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Transmit_DMA().

#define __HAL_IRDA_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)

Clear the IRDA IDLE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 395 of file stm32f1xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)

Clear the IRDA NE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 381 of file stm32f1xx_hal_irda.h.

#define __HAL_IRDA_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)

Clear the IRDA ORE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 388 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_DMAResume(), and HAL_IRDA_Receive_DMA().

#define __HAL_IRDA_CLEAR_PEFLAG ( __HANDLE__ )
Value:
do{                                             \
    __IO uint32_t tmpreg = 0x00U;               \
    tmpreg = (__HANDLE__)->Instance->SR;        \
    tmpreg = (__HANDLE__)->Instance->DR;        \
    UNUSED(tmpreg);                             \
  } while(0U)

Clear the IRDA PE pending flag.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 361 of file stm32f1xx_hal_irda.h.

#define __HAL_IRDA_DISABLE ( __HANDLE__ ) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))

Disable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 459 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_DeInit(), and HAL_IRDA_Init().

#define __HAL_IRDA_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
                                                           (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))

Disable the specified IRDA interrupt.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
__INTERRUPT__,: specifies the IRDA interrupt source to disable. This parameter can be one of the following values:
  • IRDA_IT_TXE: Transmit Data Register empty interrupt
  • IRDA_IT_TC: Transmission complete interrupt
  • IRDA_IT_RXNE: Receive Data register not empty interrupt
  • IRDA_IT_IDLE: Idle line detection interrupt
  • IRDA_IT_PE: Parity Error interrupt
  • IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)

Definition at line 426 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_Receive_IT().

#define __HAL_IRDA_ENABLE ( __HANDLE__ ) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))

Enable UART/USART associated to IRDA Handle.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 452 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Init().

#define __HAL_IRDA_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
                                                           (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))

Enable the specified IRDA interrupt.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
__INTERRUPT__,: specifies the IRDA interrupt source to enable. This parameter can be one of the following values:
  • IRDA_IT_TXE: Transmit Data Register empty interrupt
  • IRDA_IT_TC: Transmission complete interrupt
  • IRDA_IT_RXNE: Receive Data register not empty interrupt
  • IRDA_IT_IDLE: Idle line detection interrupt
  • IRDA_IT_PE: Parity Error interrupt
  • IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)

Definition at line 410 of file stm32f1xx_hal_irda.h.

Referenced by HAL_IRDA_Receive_IT(), HAL_IRDA_Transmit_IT(), and IRDA_DMATransmitCplt().

#define __HAL_IRDA_FLUSH_DRREGISTER ( __HANDLE__ ) ((__HANDLE__)->Instance->DR)

Flush the IRDA DR register.

Parameters:
__HANDLE__,: specifies the USART Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 315 of file stm32f1xx_hal_irda.h.

#define __HAL_IRDA_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified IRDA flag is set or not.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • IRDA_FLAG_TXE: Transmit data register empty flag
  • IRDA_FLAG_TC: Transmission Complete flag
  • IRDA_FLAG_RXNE: Receive data register not empty flag
  • IRDA_FLAG_IDLE: Idle Line detection flag
  • IRDA_FLAG_ORE: OverRun Error flag
  • IRDA_FLAG_NE: Noise Error flag
  • IRDA_FLAG_FE: Framing Error flag
  • IRDA_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 333 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_WaitOnFlagUntilTimeout().

#define __HAL_IRDA_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
(((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))

Check whether the specified IRDA interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
__IT__,: specifies the IRDA interrupt source to check. This parameter can be one of the following values:
  • IRDA_IT_TXE: Transmit Data Register empty interrupt
  • IRDA_IT_TC: Transmission complete interrupt
  • IRDA_IT_RXNE: Receive Data register not empty interrupt
  • IRDA_IT_IDLE: Idle line detection interrupt
  • IRDA_IT_ERR: Error interrupt
  • IRDA_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 444 of file stm32f1xx_hal_irda.h.

#define __HAL_IRDA_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
                                                     } while(0U)

Reset IRDA handle gstate & RxState.

Parameters:
__HANDLE__,: specifies the IRDA Handle. IRDA Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 305 of file stm32f1xx_hal_irda.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Private Constants

Defines
IRDA Private Constants
IRDA

Defines

#define | IRDA_IT_MASK 0x0000FFFFU
IRDA interruptions flag mask.
#define | IRDA_CR1_REG_INDEX 1U
#define | IRDA_CR2_REG_INDEX 2U
#define | IRDA_CR3_REG_INDEX 3U

Define Documentation

#define IRDA_CR1_REG_INDEX 1U

Definition at line 542 of file stm32f1xx_hal_irda.h.

#define IRDA_CR2_REG_INDEX 2U

Definition at line 543 of file stm32f1xx_hal_irda.h.

#define IRDA_CR3_REG_INDEX 3U

Definition at line 544 of file stm32f1xx_hal_irda.h.

#define IRDA_IT_MASK 0x0000FFFFU

IRDA interruptions flag mask.

Definition at line 540 of file stm32f1xx_hal_irda.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Private Macros

Defines
IRDA Private Macros
IRDA

Defines

#define | IS_IRDA_WORD_LENGTH(LENGTH)
#define | IS_IRDA_PARITY(PARITY)
#define | IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
#define | IS_IRDA_POWERMODE(MODE)
#define | IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
#define | IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
#define | IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | IRDA_BRR(_PCLK_, _BAUD_)

Define Documentation

#define IRDA_BRR | ( | _PCLK_,
 |  | _BAUD_
 | ) |
Value:
(((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
                                             (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
                                             (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))

Definition at line 568 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IRDA_DIV | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*25U)/(4U*(_BAUD_)))

Definition at line 563 of file stm32f1xx_hal_irda.h.

#define IRDA_DIVFRAQ | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)

Definition at line 565 of file stm32f1xx_hal_irda.h.

#define IRDA_DIVMANT | ( | _PCLK_,
 |  | _BAUD_
 | ) | (IRDA_DIV((_PCLK_), (_BAUD_))/100U)

Definition at line 564 of file stm32f1xx_hal_irda.h.

#define IS_IRDA_BAUDRATE ( BAUDRATE ) ((BAUDRATE) < 115201U)

Definition at line 561 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_MODE ( MODE ) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))

Definition at line 558 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_PARITY ( PARITY )
Value:
(((PARITY) == IRDA_PARITY_NONE) || \
                                ((PARITY) == IRDA_PARITY_EVEN) || \
                                ((PARITY) == IRDA_PARITY_ODD))

Definition at line 555 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_POWERMODE ( MODE )
Value:
(((MODE) == IRDA_POWERMODE_LOWPOWER) || \
                                 ((MODE) == IRDA_POWERMODE_NORMAL))

Definition at line 559 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_SetConfig().

#define IS_IRDA_WORD_LENGTH ( LENGTH )
Value:
(((LENGTH) == IRDA_WORDLENGTH_8B) || \
                                     ((LENGTH) == IRDA_WORDLENGTH_9B))

Definition at line 553 of file stm32f1xx_hal_irda.h.

Referenced by IRDA_SetConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Private Functions

IRDA Private Functions
IRDA
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG Private Defines

Defines
IWDG Private Defines
IWDG

Defines

#define HAL_IWDG_DEFAULT_TIMEOUT 48U

Define Documentation

#define HAL_IWDG_DEFAULT_TIMEOUT 48U

Definition at line 125 of file stm32f1xx_hal_iwdg.c.

Referenced by HAL_IWDG_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_InitTypeDef Struct Reference
IWDG Exported Types

IWDG Init structure definition. More...

#include <stm32f1xx_hal_iwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Reload

Detailed Description

IWDG Init structure definition.

Definition at line 65 of file stm32f1xx_hal_iwdg.h.

Field Documentation

uint32_t IWDG_InitTypeDef::Prescaler

Select the prescaler of the IWDG. This parameter can be a value of IWDG Prescaler

Definition at line 67 of file stm32f1xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

uint32_t IWDG_InitTypeDef::Reload

Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF

Definition at line 70 of file stm32f1xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_iwdg.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
IWDG_HandleTypeDef Struct Reference
IWDG Exported Types

IWDG Handle Structure definition. More...

#include <stm32f1xx_hal_iwdg.h>

Data Fields

IWDG_TypeDef * Instance
IWDG_InitTypeDef Init

Detailed Description

IWDG Handle Structure definition.

Definition at line 78 of file stm32f1xx_hal_iwdg.h.

Field Documentation

IWDG_InitTypeDef IWDG_HandleTypeDef::Init

IWDG required parameters

Definition at line 82 of file stm32f1xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

IWDG_TypeDef* IWDG_HandleTypeDef::Instance

Register base address

Definition at line 80 of file stm32f1xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_iwdg.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG Prescaler

Defines
IWDG Prescaler
IWDG Exported Constants

Defines

#define | IWDG_PRESCALER_4 0x00000000U
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

Define Documentation

#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)

IWDG prescaler set to 128

Definition at line 103 of file stm32f1xx_hal_iwdg.h.

#define IWDG_PRESCALER_16 IWDG_PR_PR_1

IWDG prescaler set to 16

Definition at line 100 of file stm32f1xx_hal_iwdg.h.

#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)

IWDG prescaler set to 256

Definition at line 104 of file stm32f1xx_hal_iwdg.h.

#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)

IWDG prescaler set to 32

Definition at line 101 of file stm32f1xx_hal_iwdg.h.

#define IWDG_PRESCALER_4 0x00000000U

IWDG prescaler set to 4

Definition at line 98 of file stm32f1xx_hal_iwdg.h.

#define IWDG_PRESCALER_64 IWDG_PR_PR_2

IWDG prescaler set to 64

Definition at line 102 of file stm32f1xx_hal_iwdg.h.

#define IWDG_PRESCALER_8 IWDG_PR_PR_0

IWDG prescaler set to 8

Definition at line 99 of file stm32f1xx_hal_iwdg.h.

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STM32F103xB HAL User Manual: IWDG Exported Macros

Defines
IWDG Exported Macros
IWDG

Defines

#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR & IWDG_RLR registers disabled).

Define Documentation

#define __HAL_IWDG_RELOAD_COUNTER ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

Reload IWDG counter with value defined in the reload register (write access to IWDG_PR & IWDG_RLR registers disabled).

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 132 of file stm32f1xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init(), and HAL_IWDG_Refresh().

#define __HAL_IWDG_START ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

Enable the IWDG peripheral.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 124 of file stm32f1xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and Start functions

Functions
Initialization and Start functions
IWDG Exported Functions

Initialization and Start functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Detailed Description

Initialization and Start functions.

 ===============================================================================
          ##### Initialization and Start functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Initialize the IWDG according to the specified parameters in the
          IWDG_InitTypeDef of associated handle.
      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
          is reloaded in order to exit function with correct time base.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Init ( IWDG_HandleTypeDef * hiwdg )

Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.

Before exiting function, watchdog is refreshed in order to have correct time base.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 164 of file stm32f1xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER, __HAL_IWDG_START, assert_param, HAL_GetTick(), HAL_IWDG_DEFAULT_TIMEOUT, IWDG_HandleTypeDef::Init, IWDG_HandleTypeDef::Instance, IS_IWDG_PRESCALER, IS_IWDG_RELOAD, IWDG_ENABLE_WRITE_ACCESS, IWDG_InitTypeDef::Prescaler, and IWDG_InitTypeDef::Reload.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
IWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IO operation functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]  This section provides functions allowing to:
      (+) Refresh the IWDG.

Function Documentation

HAL_StatusTypeDef HAL_IWDG_Refresh ( IWDG_HandleTypeDef * hiwdg )

Refresh the IWDG.

Parameters:
hiwdg pointer to a IWDG_HandleTypeDef structure that contains the configuration information for the specified IWDG module.
Return values:
HAL status

Definition at line 232 of file stm32f1xx_hal_iwdg.c.

References __HAL_IWDG_RELOAD_COUNTER.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG Private Constants

Defines
IWDG Private Constants
IWDG

Defines

#define | IWDG_KEY_RELOAD 0x0000AAAAU
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCU
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U

Define Documentation

#define IWDG_KEY_ENABLE 0x0000CCCCU

IWDG Peripheral Enable

Definition at line 174 of file stm32f1xx_hal_iwdg.h.

#define IWDG_KEY_RELOAD 0x0000AAAAU

IWDG Key Register BitMask.

IWDG Reload Counter Enable

Definition at line 173 of file stm32f1xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U

IWDG KR Write Access Disable

Definition at line 176 of file stm32f1xx_hal_iwdg.h.

#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U

IWDG KR Write Access Enable

Definition at line 175 of file stm32f1xx_hal_iwdg.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG Private Macros

Defines
IWDG Private Macros
IWDG

Defines

#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR and IWDG_RLR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR and IWDG_RLR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.

Define Documentation

#define IS_IWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == IWDG_PRESCALER_4)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
                                               ((__PRESCALER__) == IWDG_PRESCALER_256))

Check IWDG prescaler value.

Parameters:
__PRESCALER__ IWDG prescaler value
Return values:
None

Definition at line 206 of file stm32f1xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IS_IWDG_RELOAD ( __RELOAD__ ) ((__RELOAD__) <= IWDG_RLR_RL)

Check IWDG reload value.

Parameters:
__RELOAD__ IWDG reload value
Return values:
None

Definition at line 219 of file stm32f1xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

#define IWDG_DISABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

Disable write access to IWDG_PR and IWDG_RLR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 199 of file stm32f1xx_hal_iwdg.h.

#define IWDG_ENABLE_WRITE_ACCESS ( __HANDLE__ ) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

Enable write access to IWDG_PR and IWDG_RLR registers.

Parameters:
__HANDLE__ IWDG handle
Return values:
None

Definition at line 192 of file stm32f1xx_hal_iwdg.h.

Referenced by HAL_IWDG_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PCD Instance definition

Defines
PCD Instance definition
PCD Private Macros

Defines

#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE

Define Documentation

#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE

Definition at line 824 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PCD Private Macros

Modules | Defines
PCD Private Macros
PCD

Modules

PCD Instance definition

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
#define | PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2U)= (uint16_t)(wRegValue))
#define | PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2U))
#define | USB_EP0StartXfer USB_EPStartXfer
#define | PCD_SET_EPTYPE(USBx, bEpNum, wType)
sets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
gets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_FreeUserBuffer(USBx, bEpNum, bDir)
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | PCD_GET_DB_DIR(USBx, bEpNum)
gets direction of the double buffered endpoint
#define | PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState)
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | PCD_SET_EP_RX_STATUS(USBx, bEpNum, wState)
sets the status for rx transfer (bits STAT_TX[1:0])
#define | PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx)
sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
#define | PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])
#define | PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
#define | PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
sets directly the VALID tx/rx-status into the endpoint register
#define | PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
#define | PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum)
checks stall condition in an endpoint.
#define | PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum)
#define | PCD_SET_EP_KIND(USBx, bEpNum)
set & clear EP_KIND bit.
#define | PCD_CLEAR_EP_KIND(USBx, bEpNum)
#define | PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly STATUS_OUT bit in the endpoint register.
#define | PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly EP_KIND bit in the endpoint register.
#define | PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)
#define | PCD_RX_DTOG(USBx, bEpNum)
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_TX_DTOG(USBx, bEpNum)
#define | PCD_CLEAR_RX_DTOG(USBx, bEpNum)
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_CLEAR_TX_DTOG(USBx, bEpNum)
#define | PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr)
Sets address in an endpoint register.
#define | PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
#define | PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U)*2U+ ((uint32_t)(USBx) + 0x400U)))
#define | PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+2U)*2U+ ((uint32_t)(USBx) + 0x400U)))
#define | PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+4U)*2U+ ((uint32_t)(USBx) + 0x400U)))
#define | PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+6U)*2U+ ((uint32_t)(USBx) + 0x400U)))
#define | PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount)
#define | PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
sets address of the tx/rx buffer.
#define | PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
#define | PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets address of the tx/rx buffer.
#define | PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_CALC_BLK32(dwReg, wCount, wNBlocks)
Sets counter of rx buffer with no.
#define | PCD_CALC_BLK2(dwReg, wCount, wNBlocks)
#define | PCD_SET_EP_CNT_RX_REG(dwReg, wCount)
#define | PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount)
#define | PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
sets counter for the tx/rx buffer.
#define | PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3FFU)
gets counter of the tx buffer.
#define | PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3FFU)
#define | PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
Sets buffer 0/1 address in a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
#define | PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr)
Sets addresses in a double buffer endpoint.
#define | PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
Gets buffer 0/1 rx/tx counter for double buffering.
#define | PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))

Define Documentation

#define PCD_CALC_BLK2 | ( | dwReg,
 |  | wCount,
 |  | wNBlocks
 | ) |
Value:
{\
    (wNBlocks) = (wCount) >> 1U;\
    if(((wCount) & 0x01U) != 0U)\
    {                                                  \
      (wNBlocks)++;\
    }                                                  \
    *pdwReg = (uint16_t)((wNBlocks) << 10U);\
  }/* PCD_CALC_BLK2 */

Definition at line 699 of file stm32f1xx_hal_pcd.h.

#define PCD_CALC_BLK32 | ( | dwReg,
 |  | wCount,
 |  | wNBlocks
 | ) |
Value:
{\
    (wNBlocks) = (wCount) >> 5U;\
    if(((wCount) & 0x1FU) == 0U)\
    {                                                  \
      (wNBlocks)--;\
    }                                                  \
    *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | 0x8000U); \
  }/* PCD_CALC_BLK32 */

Sets counter of rx buffer with no.

of blocks.

Parameters:
dwReg,: Register
wCount,: Counter.
wNBlocks,: no. of Blocks.
Return values:
None

Definition at line 690 of file stm32f1xx_hal_pcd.h.

#define PCD_CLEAR_EP_DBUF | ( | USBx,
 |  | bEpNum
 | ) | PCD_CLEAR_EP_KIND((USBx), (bEpNum))

Definition at line 603 of file stm32f1xx_hal_pcd.h.

#define PCD_CLEAR_EP_KIND | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
                                (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))

Definition at line 584 of file stm32f1xx_hal_pcd.h.

#define PCD_CLEAR_OUT_STATUS | ( | USBx,
 |  | bEpNum
 | ) | PCD_CLEAR_EP_KIND((USBx), (bEpNum))

Definition at line 594 of file stm32f1xx_hal_pcd.h.

#define PCD_CLEAR_RX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0U)\
                                         {                                                              \
                                           PCD_RX_DTOG((USBx), (bEpNum));                               \
                                         }

Clears DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
None

Definition at line 633 of file stm32f1xx_hal_pcd.h.

#define PCD_CLEAR_RX_EP_CTR | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum),\
                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))

Clears bit CTR_RX / CTR_TX in the endpoint register.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
None

Definition at line 611 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_CLEAR_TX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0U)\
                                         {                                                              \
                                            PCD_TX_DTOG((USBx), (bEpNum));                              \
                                         }

Definition at line 637 of file stm32f1xx_hal_pcd.h.

#define PCD_CLEAR_TX_EP_CTR | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum),\
                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))

Definition at line 613 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_EP_RX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+4U)*2U+ ((uint32_t)(USBx) + 0x400U)))

Definition at line 656 of file stm32f1xx_hal_pcd.h.

#define PCD_EP_RX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+6U)*2U+ ((uint32_t)(USBx) + 0x400U)))

Definition at line 657 of file stm32f1xx_hal_pcd.h.

#define PCD_EP_TX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U)*2U+ ((uint32_t)(USBx) + 0x400U)))

Definition at line 654 of file stm32f1xx_hal_pcd.h.

#define PCD_EP_TX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+2U)*2U+ ((uint32_t)(USBx) + 0x400U)))

Definition at line 655 of file stm32f1xx_hal_pcd.h.

#define PCD_FreeUserBuffer | ( | USBx,
 |  | bEpNum,
 |  | bDir
 | ) |
Value:
{\
  if ((bDir) == PCD_EP_DBUF_OUT)\
  { /* OUT double buffered endpoint */\
    PCD_TX_DTOG((USBx), (bEpNum));\
  }\
  else if ((bDir) == PCD_EP_DBUF_IN)\
  { /* IN double buffered endpoint */\
    PCD_RX_DTOG((USBx), (bEpNum));\
  }\
}

free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
bDir,: Direction
Return values:
None

Definition at line 435 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_DB_DIR | ( | USBx,
 |  | bEpNum
 | ) |
Value:
{\
  if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
    return(PCD_EP_DBUF_OUT);\
  else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
    return(PCD_EP_DBUF_IN);\
  else\
    return(PCD_EP_DBUF_ERR);\
}

gets direction of the double buffered endpoint

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
EP_DBUF_OUT,EP_DBUF_IN,EP_DBUF_ERR if the endpoint counter not yet programmed.

Definition at line 454 of file stm32f1xx_hal_pcd.h.

#define PCD_GET_ENDPOINT | ( | USBx,
 |  | bEpNum
 | ) | (*(&(USBx)->EP0R + (bEpNum) * 2U))

Definition at line 404 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))

Definition at line 652 of file stm32f1xx_hal_pcd.h.

#define PCD_GET_EP_DBUF0_ADDR | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))

Gets buffer 0/1 address of a double buffer endpoint.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
None

Definition at line 773 of file stm32f1xx_hal_pcd.h.

#define PCD_GET_EP_DBUF0_CNT | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))

Gets buffer 0/1 rx/tx counter for double buffering.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
None

Definition at line 816 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_DBUF1_ADDR | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))

Definition at line 774 of file stm32f1xx_hal_pcd.h.

#define PCD_GET_EP_DBUF1_CNT | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))

Definition at line 817 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_RX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))

Definition at line 681 of file stm32f1xx_hal_pcd.h.

#define PCD_GET_EP_RX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3FFU)

Definition at line 742 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_RX_STALL_STATUS | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
                                   == USB_EP_RX_STALL)

Definition at line 573 of file stm32f1xx_hal_pcd.h.

#define PCD_GET_EP_RX_STATUS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)

Definition at line 554 of file stm32f1xx_hal_pcd.h.

#define PCD_GET_EP_TX_ADDRESS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))

Gets address of the tx/rx buffer.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
address of the buffer.

Definition at line 680 of file stm32f1xx_hal_pcd.h.

#define PCD_GET_EP_TX_CNT | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3FFU)

gets counter of the tx buffer.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
Counter value

Definition at line 741 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_GET_EP_TX_STALL_STATUS | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
                                   == USB_EP_TX_STALL)

checks stall condition in an endpoint.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
TRUE = endpoint in stall condition.

Definition at line 571 of file stm32f1xx_hal_pcd.h.

#define PCD_GET_EP_TX_STATUS | ( | USBx,
 |  | bEpNum
 | ) | ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)

gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
status

Definition at line 553 of file stm32f1xx_hal_pcd.h.

#define PCD_GET_EPTYPE | ( | USBx,
 |  | bEpNum
 | ) | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)

gets the type in the endpoint register(bits EP_TYPE[1:0])

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
Endpoint Type

Definition at line 425 of file stm32f1xx_hal_pcd.h.

#define PCD_MAX | ( | a,
 |  | b
 | ) | (((a) > (b)) ? (a) : (b))

Definition at line 106 of file stm32f1xx_hal_pcd.c.

#define PCD_MIN | ( | a,
 |  | b
 | ) | (((a) < (b)) ? (a) : (b))

Definition at line 105 of file stm32f1xx_hal_pcd.c.

#define PCD_RX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))

Toggles DTOG_RX / DTOG_TX bit in the endpoint register.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
None

Definition at line 622 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_ENDPOINT | ( | USBx,
 |  | bEpNum,
 |  | wRegValue
 | ) | (*(&(USBx)->EP0R + (bEpNum) * 2U)= (uint16_t)(wRegValue))

Definition at line 401 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | bAddr
 | ) |
Value:
PCD_SET_ENDPOINT((USBx), (bEpNum),\
    USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))

Sets address in an endpoint register.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
bAddr,: Address.
Return values:
None

Definition at line 649 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_CNT_RX_REG | ( | dwReg,
 |  | wCount
 | ) |
Value:
{\
    uint16_t wNBlocks;\
    if((wCount) > 62U)                                \
    {                                                \
      PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);     \
    }                                                \
    else                                             \
    {                                                \
      PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);      \
    }                                                \
  }/* PCD_SET_EP_CNT_RX_REG */

Definition at line 708 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_DBUF | ( | USBx,
 |  | bEpNum
 | ) | PCD_SET_EP_KIND((USBx), (bEpNum))

Sets/clears directly EP_KIND bit in the endpoint register.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
None

Definition at line 602 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_DBUF0_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf0Addr
 | ) | {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}

Sets buffer 0/1 address in a double buffer endpoint.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
wBuf0Addr,: buffer 0 address.
Return values:
Counter value

Definition at line 751 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_DBUF0_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
{ \
    if((bDir) == PCD_EP_DBUF_OUT)\
      /* OUT endpoint */ \
    {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
    else if((bDir) == PCD_EP_DBUF_IN)\
      /* IN endpoint */ \
      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount);  \
  } /* SetEPDblBuf0Count*/

Gets buffer 0/1 address of a double buffer endpoint.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
bDir,: endpoint dir EP_DBUF_OUT = OUT EP_DBUF_IN = IN
wCount,: Counter value
Return values:
None

Definition at line 785 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_DBUF1_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf1Addr
 | ) | {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}

Definition at line 752 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_DBUF1_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
{ \
    if((bDir) == PCD_EP_DBUF_OUT)\
    {/* OUT endpoint */                                       \
      PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));           \
    }                                                         \
    else if((bDir) == PCD_EP_DBUF_IN)\
    {/* IN endpoint */                                        \
      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
    }                                                         \
  } /* SetEPDblBuf1Count */

Definition at line 794 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_DBUF_ADDR | ( | USBx,
 |  | bEpNum,
 |  | wBuf0Addr,
 |  | wBuf1Addr
 | ) |
Value:
{ \
    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
  } /* PCD_SET_EP_DBUF_ADDR */

Sets addresses in a double buffer endpoint.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
wBuf0Addr,: buffer 0 address.
wBuf1Addr = buffer 1 address.
Return values:
None

Definition at line 762 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_DBUF_CNT | ( | USBx,
 |  | bEpNum,
 |  | bDir,
 |  | wCount
 | ) |
Value:
{\
    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
  } /* PCD_SET_EP_DBUF_CNT  */

Definition at line 805 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_KIND | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))

set & clear EP_KIND bit.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
None

Definition at line 582 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_RX_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | wAddr
 | ) | (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))

Definition at line 672 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_RX_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) |
Value:
{\
    uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
  }

Definition at line 659 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_SET_EP_RX_DBUF0_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) |
Value:
{\
    uint32_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
  }

Definition at line 720 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_RX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wState
 | ) |
Value:
{\
    register uint16_t _wRegVal;   \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
    /* toggle first bit ? */  \
    if((USB_EPRX_DTOG1 & (wState))!= 0U) \
    {                                                                             \
      _wRegVal ^= USB_EPRX_DTOG1;  \
    }                                                                             \
    /* toggle second bit ? */  \
    if((USB_EPRX_DTOG2 & (wState))!= 0U) \
    {                                                                             \
      _wRegVal ^= USB_EPRX_DTOG2;  \
    }                                                                             \
    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
  } /* PCD_SET_EP_RX_STATUS */

sets the status for rx transfer (bits STAT_TX[1:0])

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
wState,: new state
Return values:
None

Definition at line 494 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_SET_EP_RX_VALID | ( | USBx,
 |  | bEpNum
 | ) | (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))

Definition at line 563 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_TX_ADDRESS | ( | USBx,
 |  | bEpNum,
 |  | wAddr
 | ) | (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))

sets address of the tx/rx buffer.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
wAddr,: address to be set (must be word aligned).
Return values:
None

Definition at line 671 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_TX_CNT | ( | USBx,
 |  | bEpNum,
 |  | wCount
 | ) | (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))

sets counter for the tx/rx buffer.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
wCount,: Counter value.
Return values:
None

Definition at line 732 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_TX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wState
 | ) |
Value:
{ register uint16_t _wRegVal;\
   \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
   /* toggle first bit ? */     \
   if((USB_EPTX_DTOG1 & (wState))!= 0U)\
   {                                                                            \
     _wRegVal ^= USB_EPTX_DTOG1;        \
   }                                                                            \
   /* toggle second bit ?  */         \
   if((USB_EPTX_DTOG2 & (wState))!= 0U)      \
   {                                                                            \
     _wRegVal ^= USB_EPTX_DTOG2;        \
   }                                                                            \
   PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\
  } /* PCD_SET_EP_TX_STATUS */

sets the status for tx transfer (bits STAT_TX[1:0]).

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
wState,: new state
Return values:
None

Definition at line 471 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_TX_VALID | ( | USBx,
 |  | bEpNum
 | ) | (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))

sets directly the VALID tx/rx-status into the endpoint register

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
None

Definition at line 562 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EP_TXRX_STATUS | ( | USBx,
 |  | bEpNum,
 |  | wStaterx,
 |  | wStatetx
 | ) |
Value:
{\
    register uint32_t _wRegVal;   \
    \
    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
    /* toggle first bit ? */  \
    if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
    {                                                                                    \
      _wRegVal ^= USB_EPRX_DTOG1;  \
    }                                                                                    \
    /* toggle second bit ? */  \
    if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
    {                                                                                    \
      _wRegVal ^= USB_EPRX_DTOG2;  \
    }                                                                                    \
    /* toggle first bit ? */     \
    if((USB_EPTX_DTOG1 & (wStatetx))!= 0U)      \
    {                                                                                    \
      _wRegVal ^= USB_EPTX_DTOG1;        \
    }                                                                                    \
    /* toggle second bit ?  */         \
    if((USB_EPTX_DTOG2 & (wStatetx))!= 0U)      \
    {                                                                                    \
      _wRegVal ^= USB_EPTX_DTOG2;        \
    }                                                                                    \
    PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX);    \
  } /* PCD_SET_EP_TXRX_STATUS */

sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
wStaterx,: new state.
wStatetx,: new state.
Return values:
None

Definition at line 519 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_EPTYPE | ( | USBx,
 |  | bEpNum,
 |  | wType
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum),\
                                           ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))

sets the type in the endpoint register(bits EP_TYPE[1:0])

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
wType,: Endpoint Type.
Return values:
None

Definition at line 416 of file stm32f1xx_hal_pcd.h.

#define PCD_SET_OUT_STATUS | ( | USBx,
 |  | bEpNum
 | ) | PCD_SET_EP_KIND((USBx), (bEpNum))

Sets/clears directly STATUS_OUT bit in the endpoint register.

Parameters:
USBx,: USB peripheral instance register address.
bEpNum,: Endpoint Number.
Return values:
None

Definition at line 593 of file stm32f1xx_hal_pcd.h.

#define PCD_TX_DTOG | ( | USBx,
 |  | bEpNum
 | ) |
Value:
(PCD_SET_ENDPOINT((USBx), (bEpNum), \
                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))

Definition at line 624 of file stm32f1xx_hal_pcd.h.

#define USB_EP0StartXfer USB_EPStartXfer

Definition at line 407 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Receive(), and HAL_PCD_EP_Transmit().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PCD Private Functions

Functions
PCD Private Functions
PCD

Functions

static HAL_StatusTypeDef PCD_EP_ISR_Handler (PCD_HandleTypeDef *hpcd)
This function handles PCD Endpoint interrupt request.

Function Documentation

static HAL_StatusTypeDef PCD_EP_ISR_Handler ( PCD_HandleTypeDef * hpcd ) [static]

This function handles PCD Endpoint interrupt request.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1205 of file stm32f1xx_hal_pcd.c.

References HAL_PCD_DataInStageCallback(), HAL_PCD_DataOutStageCallback(), HAL_PCD_EP_Receive(), HAL_PCD_EP_Transmit(), HAL_PCD_SetupStageCallback(), PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, PCD_HandleTypeDef::OUT_ep, PCD_CLEAR_RX_EP_CTR, PCD_CLEAR_TX_EP_CTR, PCD_ENDP0, PCD_EP_DBUF_IN, PCD_EP_DBUF_OUT, PCD_FreeUserBuffer, PCD_GET_ENDPOINT, PCD_GET_EP_DBUF0_CNT, PCD_GET_EP_DBUF1_CNT, PCD_GET_EP_RX_CNT, PCD_GET_EP_TX_CNT, PCD_SET_EP_RX_CNT, PCD_SET_EP_RX_STATUS, PCD_HandleTypeDef::Setup, and PCD_HandleTypeDef::USB_Address.

Referenced by HAL_PCD_IRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PCD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
            ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:

Function Documentation

HAL_StatusTypeDef HAL_PCD_DeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes the PCD peripheral.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 224 of file stm32f1xx_hal_pcd.c.

References HAL_PCD_MspDeInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_RESET, HAL_PCD_Stop(), and PCD_HandleTypeDef::State.

HAL_StatusTypeDef HAL_PCD_Init ( PCD_HandleTypeDef * hpcd )

Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 150 of file stm32f1xx_hal_pcd.c.

References __HAL_PCD_DISABLE, assert_param, HAL_PCD_MspInit(), HAL_PCD_STATE_BUSY, HAL_PCD_STATE_READY, HAL_PCD_STATE_RESET, PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Init, PCD_HandleTypeDef::Instance, IS_PCD_ALL_INSTANCE, PCD_HandleTypeDef::Lock, PCD_HandleTypeDef::OUT_ep, PCD_HandleTypeDef::State, and PCD_HandleTypeDef::USB_Address.

void HAL_PCD_MspDeInit ( PCD_HandleTypeDef * hpcd )

DeInitializes PCD MSP.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 264 of file stm32f1xx_hal_pcd.c.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_MspInit ( PCD_HandleTypeDef * hpcd )

Initializes the PCD MSP.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 250 of file stm32f1xx_hal_pcd.c.

Referenced by HAL_PCD_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
PCD Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data out stage callbacks.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callbacks.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callbacks.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callbacks.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callbacks.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callbacks.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callbacks.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callbacks.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callbacks.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callbacks.

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the PCD data
    transfers.

Function Documentation

void HAL_PCD_ConnectCallback ( PCD_HandleTypeDef * hpcd )

Connection event callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 773 of file stm32f1xx_hal_pcd.c.

void HAL_PCD_DataInStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data IN stage callbacks.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 657 of file stm32f1xx_hal_pcd.c.

Referenced by PCD_EP_ISR_Handler().

void HAL_PCD_DataOutStageCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Data out stage callbacks.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 641 of file stm32f1xx_hal_pcd.c.

Referenced by PCD_EP_ISR_Handler().

void HAL_PCD_DisconnectCallback ( PCD_HandleTypeDef * hpcd )

Disconnection event callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 787 of file stm32f1xx_hal_pcd.c.

void HAL_PCD_IRQHandler ( PCD_HandleTypeDef * hpcd )

This function handles PCD interrupt request.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 571 of file stm32f1xx_hal_pcd.c.

References __HAL_PCD_CLEAR_FLAG, __HAL_PCD_GET_FLAG, HAL_PCD_ResetCallback(), HAL_PCD_ResumeCallback(), HAL_PCD_SetAddress(), HAL_PCD_SOFCallback(), HAL_PCD_SuspendCallback(), PCD_HandleTypeDef::Instance, and PCD_EP_ISR_Handler().

void HAL_PCD_ISOINIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO IN callbacks.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 758 of file stm32f1xx_hal_pcd.c.

void HAL_PCD_ISOOUTIncompleteCallback | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | epnum
 | ) |  |

Incomplete ISO OUT callbacks.

Parameters:
hpcd,: PCD handle
epnum,: endpoint number
Return values:
None

Definition at line 742 of file stm32f1xx_hal_pcd.c.

void HAL_PCD_ResetCallback ( PCD_HandleTypeDef * hpcd )

USB Reset callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 699 of file stm32f1xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_ResumeCallback ( PCD_HandleTypeDef * hpcd )

Resume event callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 727 of file stm32f1xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

void HAL_PCD_SetupStageCallback ( PCD_HandleTypeDef * hpcd )

Setup stage callback.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 671 of file stm32f1xx_hal_pcd.c.

Referenced by PCD_EP_ISR_Handler().

void HAL_PCD_SOFCallback ( PCD_HandleTypeDef * hpcd )

USB Start Of Frame callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 685 of file stm32f1xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

HAL_StatusTypeDef HAL_PCD_Start ( PCD_HandleTypeDef * hpcd )

Start The USB Device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 297 of file stm32f1xx_hal_pcd.c.

References __HAL_PCD_ENABLE, HAL_PCDEx_SetConnectionState(), and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_Stop ( PCD_HandleTypeDef * hpcd )

Stop The USB Device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 312 of file stm32f1xx_hal_pcd.c.

References __HAL_PCD_DISABLE, and PCD_HandleTypeDef::Instance.

Referenced by HAL_PCD_DeInit().

void HAL_PCD_SuspendCallback ( PCD_HandleTypeDef * hpcd )

Suspend event callbacks.

Parameters:
hpcd,: PCD handle
Return values:
None

Definition at line 713 of file stm32f1xx_hal_pcd.c.

Referenced by HAL_PCD_IRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCD Exported Functions

management functions More...

Functions

HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling.

Detailed Description

management functions

 ===============================================================================
                      ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the PCD data
    transfers.

Function Documentation

HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1088 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup ( PCD_HandleTypeDef * hpcd )

HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 1098 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevConnect ( PCD_HandleTypeDef * hpcd )

Connect the USB device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 820 of file stm32f1xx_hal_pcd.c.

References HAL_PCDEx_SetConnectionState(), and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_DevDisconnect ( PCD_HandleTypeDef * hpcd )

Disconnect the USB device.

Parameters:
hpcd,: PCD handle
Return values:
HAL status

Definition at line 834 of file stm32f1xx_hal_pcd.c.

References HAL_PCDEx_SetConnectionState(), and PCD_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_PCD_EP_Close | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Deactivate an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 896 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_ClrStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Clear a STALL condition over in an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1035 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Flush | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Flush an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1065 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance.

uint16_t HAL_PCD_EP_GetRxCount | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Get Received Data Size.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
Data Size

Definition at line 958 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Open | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint16_t | ep_mps,
 |  | uint8_t | ep_type
 | ) |  |

Open and configure an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
ep_mps,: endpoint max packet size
ep_type,: endpoint type
Return values:
HAL status

Definition at line 865 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::OUT_ep.

HAL_StatusTypeDef HAL_PCD_EP_Receive | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Receive an amount of data.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
pBuf,: pointer to the reception buffer
len,: amount of data to be received
Return values:
HAL status

Definition at line 927 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance, PCD_HandleTypeDef::OUT_ep, and USB_EP0StartXfer.

Referenced by PCD_EP_ISR_Handler().

HAL_StatusTypeDef HAL_PCD_EP_SetStall | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr
 | ) |  |

Set a STALL condition over an endpoint.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
Return values:
HAL status

Definition at line 1001 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, PCD_HandleTypeDef::OUT_ep, and PCD_HandleTypeDef::Setup.

HAL_StatusTypeDef HAL_PCD_EP_Transmit | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | ep_addr,
 |  | uint8_t * | pBuf,
 |  | uint32_t | len
 | ) |  |

Send an amount of data.

Parameters:
hpcd,: PCD handle
ep_addr,: endpoint address
pBuf,: pointer to the transmission buffer
len,: amount of data to be sent
Return values:
HAL status

Definition at line 970 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::Instance, and USB_EP0StartXfer.

Referenced by PCD_EP_ISR_Handler().

HAL_StatusTypeDef HAL_PCD_SetAddress | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | address
 | ) |  |

Set the USB Device address.

Parameters:
hpcd,: PCD handle
address,: new device address
Return values:
HAL status

Definition at line 849 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::Instance, and PCD_HandleTypeDef::USB_Address.

Referenced by HAL_PCD_IRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
PCD Exported Functions

Peripheral State functions. More...

Functions

PCD_StateTypeDef HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                      ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

PCD_StateTypeDef HAL_PCD_GetState ( PCD_HandleTypeDef * hpcd )

Return the PCD state.

Parameters:
hpcd,: PCD handle
Return values:
HAL state

Definition at line 1126 of file stm32f1xx_hal_pcd.c.

References PCD_HandleTypeDef::State.

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STM32F103xB HAL User Manual: PCD Exported Types

Data Structures | Typedefs | Enumerations
PCD Exported Types
PCD

Data Structures

struct | PCD_HandleTypeDef
PCD Handle Structure definition. More...

Typedefs

typedef USB_TypeDef | PCD_TypeDef
typedef USB_CfgTypeDef | PCD_InitTypeDef
typedef USB_EPTypeDef | PCD_EPTypeDef

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00U, HAL_PCD_STATE_READY = 0x01U, HAL_PCD_STATE_ERROR = 0x02U, HAL_PCD_STATE_BUSY = 0x03U,
HAL_PCD_STATE_TIMEOUT = 0x04U
}
PCD State structure definition. More...
enum | PCD_EP_DBUF_DIR { PCD_EP_DBUF_OUT, PCD_EP_DBUF_IN, PCD_EP_DBUF_ERR }
PCD double buffered endpoint direction. More...
enum | PCD_EP_BUF_NUM { PCD_EP_NOBUF, PCD_EP_BUF0, PCD_EP_BUF1 }
PCD endpoint buffer number. More...

Typedef Documentation

typedef USB_EPTypeDef PCD_EPTypeDef

Definition at line 110 of file stm32f1xx_hal_pcd.h.

typedef USB_CfgTypeDef PCD_InitTypeDef

Definition at line 109 of file stm32f1xx_hal_pcd.h.

typedef USB_TypeDef PCD_TypeDef

Definition at line 108 of file stm32f1xx_hal_pcd.h.

Enumeration Type Documentation

enum PCD_EP_BUF_NUM

PCD endpoint buffer number.

Enumerator:
PCD_EP_NOBUF
PCD_EP_BUF0
PCD_EP_BUF1

Definition at line 93 of file stm32f1xx_hal_pcd.h.

enum PCD_EP_DBUF_DIR

PCD double buffered endpoint direction.

Enumerator:
PCD_EP_DBUF_OUT
PCD_EP_DBUF_IN
PCD_EP_DBUF_ERR

Definition at line 83 of file stm32f1xx_hal_pcd.h.

enum PCD_StateTypeDef

PCD State structure definition.

Enumerator:
HAL_PCD_STATE_RESET
HAL_PCD_STATE_READY
HAL_PCD_STATE_ERROR
HAL_PCD_STATE_BUSY
HAL_PCD_STATE_TIMEOUT

Definition at line 70 of file stm32f1xx_hal_pcd.h.

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STM32F103xB HAL User Manual: PCD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PCD_HandleTypeDef Struct Reference
PCD Exported Types

PCD Handle Structure definition. More...

#include <stm32f1xx_hal_pcd.h>

Data Fields

PCD_TypeDef * Instance
PCD_InitTypeDef Init
__IO uint8_t | USB_Address
PCD_EPTypeDef | IN_ep [15U]
PCD_EPTypeDef | OUT_ep [15U]
HAL_LockTypeDef | Lock
__IO PCD_StateTypeDef | State
uint32_t | Setup [12U]
void * | pData

Detailed Description

PCD Handle Structure definition.

Definition at line 116 of file stm32f1xx_hal_pcd.h.

Field Documentation

PCD_EPTypeDef PCD_HandleTypeDef::IN_ep[15U]

IN endpoint parameters

Definition at line 121 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Open(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

PCD_InitTypeDef PCD_HandleTypeDef::Init

PCD required parameters

Definition at line 119 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

PCD_TypeDef* PCD_HandleTypeDef::Instance

Register base address

Definition at line 118 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_ActivateRemoteWakeup(), HAL_PCD_DeActivateRemoteWakeup(), HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_Flush(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_EP_Transmit(), HAL_PCD_Init(), HAL_PCD_IRQHandler(), HAL_PCD_SetAddress(), HAL_PCD_Start(), HAL_PCD_Stop(), and PCD_EP_ISR_Handler().

HAL_LockTypeDef PCD_HandleTypeDef::Lock

PCD peripheral status

Definition at line 123 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_Init().

PCD_EPTypeDef PCD_HandleTypeDef::OUT_ep[15U]

OUT endpoint parameters

Definition at line 122 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_EP_Close(), HAL_PCD_EP_ClrStall(), HAL_PCD_EP_GetRxCount(), HAL_PCD_EP_Open(), HAL_PCD_EP_Receive(), HAL_PCD_EP_SetStall(), HAL_PCD_Init(), HAL_PCDEx_PMAConfig(), and PCD_EP_ISR_Handler().

void* PCD_HandleTypeDef::pData

Pointer to upper stack Handler

Definition at line 126 of file stm32f1xx_hal_pcd.h.

uint32_t PCD_HandleTypeDef::Setup[12U]

Setup packet buffer

Definition at line 125 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_EP_SetStall(), and PCD_EP_ISR_Handler().

__IO PCD_StateTypeDef PCD_HandleTypeDef::State

PCD communication state

Definition at line 124 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_DeInit(), HAL_PCD_GetState(), and HAL_PCD_Init().

__IO uint8_t PCD_HandleTypeDef::USB_Address

USB Address: not used by USB OTG FS

Definition at line 120 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), HAL_PCD_SetAddress(), and PCD_EP_ISR_Handler().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_pcd.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PCD Speed

Defines
PCD Speed
PCD Exported Constants

Defines

#define | PCD_SPEED_HIGH 0U /* Not Supported */
#define | PCD_SPEED_HIGH_IN_FULL 1U /* Not Supported */
#define | PCD_SPEED_FULL 2U

Define Documentation

#define PCD_SPEED_FULL 2U

Definition at line 146 of file stm32f1xx_hal_pcd.h.

#define PCD_SPEED_HIGH 0U /* Not Supported */

Definition at line 144 of file stm32f1xx_hal_pcd.h.

#define PCD_SPEED_HIGH_IN_FULL 1U /* Not Supported */

Definition at line 145 of file stm32f1xx_hal_pcd.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PCD PHY Module

Defines
PCD PHY Module
PCD Exported Constants

Defines

#define PCD_PHY_EMBEDDED 2U

Define Documentation

#define PCD_PHY_EMBEDDED 2U

Definition at line 154 of file stm32f1xx_hal_pcd.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Turnaround Timeout Value

Defines
Turnaround Timeout Value
PCD Exported Constants

Defines

#define USBD_FS_TRDT_VALUE 5U

Define Documentation

#define USBD_FS_TRDT_VALUE 5U

Definition at line 163 of file stm32f1xx_hal_pcd.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PCD Exported Macros

Defines
PCD Exported Macros
PCD

macros to handle interrupts and specific clock configurations More...

Defines

#define | __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
#define | __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
#define | __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()

Detailed Description

macros to handle interrupts and specific clock configurations

Define Documentation

#define __HAL_PCD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))

Definition at line 226 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_PCD_DISABLE ( __HANDLE__ ) USB_DisableGlobalInt ((__HANDLE__)->Instance)

Definition at line 224 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_Init(), and HAL_PCD_Stop().

#define __HAL_PCD_ENABLE ( __HANDLE__ ) USB_EnableGlobalInt ((__HANDLE__)->Instance)

Definition at line 223 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_Start().

#define __HAL_PCD_GET_FLAG | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

Definition at line 225 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCD_IRQHandler().

#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG ( ) EXTI->PR = USB_WAKEUP_EXTI_LINE

Definition at line 231 of file stm32f1xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT ( ) EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)

Definition at line 229 of file stm32f1xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE ( )
Value:
do{                                        \
                            EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);  \
                            EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
                          } while(0U)

Definition at line 239 of file stm32f1xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT ( ) EXTI->IMR |= USB_WAKEUP_EXTI_LINE

Definition at line 228 of file stm32f1xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE ( )
Value:
do{                                        \
                            EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
                            EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;    \
                          } while(0U)

Definition at line 233 of file stm32f1xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do{                                        \
                            EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
                            EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
                            EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;    \
                            EXTI->FTSR |= USB_WAKEUP_EXTI_LINE;    \
                          } while(0U)

Definition at line 245 of file stm32f1xx_hal_pcd.h.

#define __HAL_USB_WAKEUP_EXTI_GET_FLAG ( ) EXTI->PR & (USB_WAKEUP_EXTI_LINE)

Definition at line 230 of file stm32f1xx_hal_pcd.h.

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STM32F103xB HAL User Manual: USB EXTI line interrupt

Defines
USB EXTI line interrupt
PCD Private Constants

Defines

#define USB_WAKEUP_EXTI_LINE 0x00040000U

Define Documentation

#define USB_WAKEUP_EXTI_LINE 0x00040000U

External interrupt line 18 Connected to the USB EXTI Line

Definition at line 349 of file stm32f1xx_hal_pcd.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PCD EP0 MPS

Defines
PCD EP0 MPS
PCD Private Constants

Defines

#define | PCD_EP0MPS_64 DEP0CTL_MPS_64
#define | PCD_EP0MPS_32 DEP0CTL_MPS_32
#define | PCD_EP0MPS_16 DEP0CTL_MPS_16
#define | PCD_EP0MPS_08 DEP0CTL_MPS_8

Define Documentation

#define PCD_EP0MPS_08 DEP0CTL_MPS_8

Definition at line 362 of file stm32f1xx_hal_pcd.h.

#define PCD_EP0MPS_16 DEP0CTL_MPS_16

Definition at line 361 of file stm32f1xx_hal_pcd.h.

#define PCD_EP0MPS_32 DEP0CTL_MPS_32

Definition at line 360 of file stm32f1xx_hal_pcd.h.

#define PCD_EP0MPS_64 DEP0CTL_MPS_64

Definition at line 359 of file stm32f1xx_hal_pcd.h.

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STM32F103xB HAL User Manual: PCD ENDP

Defines
PCD ENDP
PCD Private Constants

Defines

#define | PCD_ENDP0 ((uint8_t)0)
#define | PCD_ENDP1 ((uint8_t)1)
#define | PCD_ENDP2 ((uint8_t)2)
#define | PCD_ENDP3 ((uint8_t)3)
#define | PCD_ENDP4 ((uint8_t)4)
#define | PCD_ENDP5 ((uint8_t)5)
#define | PCD_ENDP6 ((uint8_t)6)
#define | PCD_ENDP7 ((uint8_t)7)

Define Documentation

#define PCD_ENDP0 ((uint8_t)0)

Definition at line 370 of file stm32f1xx_hal_pcd.h.

Referenced by PCD_EP_ISR_Handler().

#define PCD_ENDP1 ((uint8_t)1)

Definition at line 371 of file stm32f1xx_hal_pcd.h.

#define PCD_ENDP2 ((uint8_t)2)

Definition at line 372 of file stm32f1xx_hal_pcd.h.

#define PCD_ENDP3 ((uint8_t)3)

Definition at line 373 of file stm32f1xx_hal_pcd.h.

#define PCD_ENDP4 ((uint8_t)4)

Definition at line 374 of file stm32f1xx_hal_pcd.h.

#define PCD_ENDP5 ((uint8_t)5)

Definition at line 375 of file stm32f1xx_hal_pcd.h.

#define PCD_ENDP6 ((uint8_t)6)

Definition at line 376 of file stm32f1xx_hal_pcd.h.

#define PCD_ENDP7 ((uint8_t)7)

Definition at line 377 of file stm32f1xx_hal_pcd.h.

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STM32F103xB HAL User Manual: PCD Endpoint Kind

Defines
PCD Endpoint Kind
PCD Private Constants

Defines

#define | PCD_SNG_BUF 0U
#define | PCD_DBL_BUF 1U

Define Documentation

#define PCD_DBL_BUF 1U

Definition at line 386 of file stm32f1xx_hal_pcd.h.

#define PCD_SNG_BUF 0U

Definition at line 385 of file stm32f1xx_hal_pcd.h.

Referenced by HAL_PCDEx_PMAConfig().

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STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PCDEx Exported Functions

PCDEx control functions. More...

Functions

HAL_StatusTypeDef HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.

Detailed Description

PCDEx control functions.

 ===============================================================================
              ##### Extended Peripheral Control functions #####
 ===============================================================================
    [..]  This section provides functions allowing to:
      (+) Update FIFO (USB_OTG_FS)
      (+) Update PMA configuration (USB)

Function Documentation

HAL_StatusTypeDef HAL_PCDEx_PMAConfig | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint16_t | ep_addr,
 |  | uint16_t | ep_kind,
 |  | uint32_t | pmaadress
 | ) |  |

Configure PMA for EP.

Parameters:
hpcd : Device instance
ep_addr,: endpoint address
ep_kind,: endpoint Kind USB_SNG_BUF: Single Buffer used USB_DBL_BUF: Double Buffer used
pmaadress,: EP address in The PMA: In case of single buffer endpoint this parameter is 16-bit value providing the address in PMA allocated to endpoint. In case of double buffer endpoint this parameter is a 32-bit value providing the endpoint buffer 0 address in the LSB part of 32-bit value and endpoint buffer 1 address in the MSB part of 32-bit value.
Return values:
HAL status

Definition at line 165 of file stm32f1xx_hal_pcd_ex.c.

References PCD_HandleTypeDef::IN_ep, PCD_HandleTypeDef::OUT_ep, and PCD_SNG_BUF.

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STM32F103xB HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
PCDEx Exported Functions

Manage device connection state. More...

Functions

__weak void HAL_PCDEx_SetConnectionState (PCD_HandleTypeDef *hpcd, uint8_t state)
Software Device Connection, this function is not required by USB OTG FS peripheral, it is used only by USB Device FS peripheral.

Detailed Description

Manage device connection state.

Function Documentation

void HAL_PCDEx_SetConnectionState | ( | PCD_HandleTypeDef * | hpcd,
 |  | uint8_t | state
 | ) |  |

Software Device Connection, this function is not required by USB OTG FS peripheral, it is used only by USB Device FS peripheral.

Parameters:
hpcd,: PCD handle
state,: connection state (0 : disconnected / 1: connected)
Return values:
None

Definition at line 219 of file stm32f1xx_hal_pcd_ex.c.

Referenced by HAL_PCD_DevConnect(), HAL_PCD_DevDisconnect(), and HAL_PCD_Start().

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STM32F103xB HAL User Manual: PWR PVD Mode Mask

Defines
PWR PVD Mode Mask
PWR Private Constants

Defines

#define | PVD_MODE_IT 0x00010000U
#define | PVD_MODE_EVT 0x00020000U
#define | PVD_RISING_EDGE 0x00000001U
#define | PVD_FALLING_EDGE 0x00000002U

Define Documentation

#define PVD_FALLING_EDGE 0x00000002U

Definition at line 71 of file stm32f1xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_EVT 0x00020000U

Definition at line 69 of file stm32f1xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_MODE_IT 0x00010000U

Definition at line 68 of file stm32f1xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

#define PVD_RISING_EDGE 0x00000001U

Definition at line 70 of file stm32f1xx_hal_pwr.c.

Referenced by HAL_PWR_ConfigPVD().

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STM32F103xB HAL User Manual: PWR Register alias address

Defines
PWR Register alias address
PWR Private Constants

Defines

#define | PWR_OFFSET (PWR_BASE - PERIPH_BASE)
#define | PWR_CR_OFFSET 0x00U
#define | PWR_CSR_OFFSET 0x04U
#define | PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
#define | PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)

Define Documentation

#define PWR_CR_OFFSET 0x00U

Definition at line 82 of file stm32f1xx_hal_pwr.c.

#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)

Definition at line 84 of file stm32f1xx_hal_pwr.c.

#define PWR_CSR_OFFSET 0x04U

Definition at line 83 of file stm32f1xx_hal_pwr.c.

#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)

Definition at line 85 of file stm32f1xx_hal_pwr.c.

#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)

Definition at line 81 of file stm32f1xx_hal_pwr.c.

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STM32F103xB HAL User Manual: PWR CR Register alias address

Defines
PWR CR Register alias address
PWR Private Constants

Defines

#define | LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
#define | CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))
#define | DBP_BIT_NUMBER PWR_CR_DBP_Pos
#define | CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))
#define | PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
#define | CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))

Define Documentation

#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))

Definition at line 100 of file stm32f1xx_hal_pwr.c.

Referenced by HAL_PWR_DisableBkUpAccess(), and HAL_PWR_EnableBkUpAccess().

#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))

Definition at line 96 of file stm32f1xx_hal_pwr.c.

#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))

Definition at line 104 of file stm32f1xx_hal_pwr.c.

Referenced by HAL_PWR_DisablePVD(), and HAL_PWR_EnablePVD().

#define DBP_BIT_NUMBER PWR_CR_DBP_Pos

Definition at line 99 of file stm32f1xx_hal_pwr.c.

#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos

Definition at line 95 of file stm32f1xx_hal_pwr.c.

#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos

Definition at line 103 of file stm32f1xx_hal_pwr.c.

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STM32F103xB HAL User Manual: PWR CSR Register alias address

Defines
PWR CSR Register alias address
PWR Private Constants

Defines

#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))

Define Documentation

#define CSR_EWUP_BB ( VAL ) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))

Definition at line 116 of file stm32f1xx_hal_pwr.c.

Referenced by HAL_PWR_DisableWakeUpPin(), and HAL_PWR_EnableWakeUpPin().

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STM32F103xB HAL User Manual: PWR Private Constants

Modules | Defines
PWR Private Constants
PWR

Modules

PWR PVD Mode Mask
PWR Register alias address
PWR CR Register alias address
PWR CSR Register alias address

Defines

#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000)

Define Documentation

#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000)

External interrupt line 16 Connected to the PVD EXTI Line

Definition at line 87 of file stm32f1xx_hal_pwr.h.

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STM32F103xB HAL User Manual: PWR Private Functions

Functions
PWR Private Functions
PWR

brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) More...

Functions

static void PWR_OverloadWfe (void)

Detailed Description

brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)

Function Documentation

static __NOINLINE void PWR_OverloadWfe ( void ) [static]

Definition at line 135 of file stm32f1xx_hal_pwr.c.

Referenced by HAL_PWR_EnterSTOPMode().

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STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
PWR Exported Functions

Initialization and de-initialization functions. More...

Functions

void | HAL_PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers ).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers).

Detailed Description

Initialization and de-initialization functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      After reset, the backup domain (RTC registers, RTC backup data
      registers) is protected against possible unwanted
      write accesses.
      To enable access to the RTC Domain and RTC registers, proceed as follows:
        (+) Enable the Power Controller (PWR) APB1 interface clock using the
            __HAL_RCC_PWR_CLK_ENABLE() macro.
        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.

Function Documentation

void HAL_PWR_DeInit ( void )

Deinitializes the PWR peripheral registers to their default reset values.

Return values:
None

Definition at line 174 of file stm32f1xx_hal_pwr.c.

References __HAL_RCC_PWR_FORCE_RESET, and __HAL_RCC_PWR_RELEASE_RESET.

void HAL_PWR_DisableBkUpAccess ( void )

Disables access to the backup domain (RTC registers, RTC backup data registers).

Note:
If the HSE divided by 128 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 200 of file stm32f1xx_hal_pwr.c.

References CR_DBP_BB.

void HAL_PWR_EnableBkUpAccess ( void )

Enables access to the backup domain (RTC registers, RTC backup data registers ).

Note:
If the HSE divided by 128 is used as the RTC clock, the Backup Domain Access should be kept enabled.
Return values:
None

Definition at line 187 of file stm32f1xx_hal_pwr.c.

References CR_DBP_BB.

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STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
PWR Exported Functions

Low Power modes configuration functions. More...

Functions

void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinx)
Enables the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M3 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M3 SEVONPEND bit.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

Low Power modes configuration functions.

 ===============================================================================
                 ##### Peripheral Control functions #####
 ===============================================================================

    *** PVD configuration ***
    =========================
    [..]
      (+) The PVD is used to monitor the VDD power supply by comparing it to a
          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).

      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
          than the PVD threshold. This event is internally connected to the EXTI
          line16 and can generate an interrupt if enabled. This is done through
          __HAL_PVD_EXTI_ENABLE_IT() macro.
      (+) The PVD is stopped in Standby mode.

    *** WakeUp pin configuration ***
    ================================
    [..]
      (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
          forced in input pull-down configuration and is active on rising edges.
      (+) There is one WakeUp pin:
          WakeUp Pin 1 on PA.00.

    [..]

    *** Low Power modes configuration ***
    =====================================
     [..]
      The device features 3 low-power modes:
      (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
                      NVIC, SysTick, etc. are kept running
      (+) Stop mode: All clocks are stopped
      (+) Standby mode: 1.8V domain powered off

   *** Sleep mode ***
   ==================
    [..]
      (+) Entry:
          The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
              functions with
          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction

      (+) Exit:
        (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
             controller (NVIC) can wake up the device from Sleep mode.
        (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
           (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
           (+++) Any EXTI Line (Internal or External) configured in Event mode

   *** Stop mode ***
   =================
    [..]
      The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
      clock gating. The voltage regulator can be configured either in normal or low-power mode.
      In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
      oscillators are disabled. SRAM and register contents are preserved.
      In Stop mode, all I/O pins keep the same state as in Run mode.

      (+) Entry:
           The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
             function with:
          (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
          (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
          (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
          (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
      (+) Exit:
          (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
          (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.

   *** Standby mode ***
   ====================
     [..]
      The Standby mode allows to achieve the lowest power consumption. It is based on the
      Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
      consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
      switched off. SRAM and register contents are lost except for registers in the Backup domain
      and Standby circuitry

      (+) Entry:
        (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
      (+) Exit:
        (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
             NRSTpin, IWDG Reset

   *** Auto-wakeup (AWU) from low-power mode ***
       =============================================
       [..]

       (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
           without depending on an external interrupt (Auto-wakeup mode).

       (+) RTC auto-wakeup (AWU) from the Stop and Standby modes

           (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
                configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.

   *** PWR Workarounds linked to Silicon Limitation ***
       ====================================================
       [..]
       Below the list of all silicon limitations known on STM32F1xx prouct.

       (#)Workarounds Implemented inside PWR HAL Driver
          (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function

Function Documentation

void HAL_PWR_ConfigPVD ( PWR_PVDTypeDef * sConfigPVD )

Configures the voltage threshold detected by the Power Voltage Detector(PVD).

Parameters:
sConfigPVD,: pointer to an PWR_PVDTypeDef structure that contains the configuration information for the PVD.
Note:
Refer to the electrical characteristics of your device datasheet for more details about the voltage threshold corresponding to each detection level.
Return values:
None

Definition at line 334 of file stm32f1xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_DISABLE_EVENT, __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_DISABLE_IT, __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_EVENT, __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE, __HAL_PWR_PVD_EXTI_ENABLE_IT, __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE, assert_param, IS_PWR_PVD_LEVEL, IS_PWR_PVD_MODE, PWR_PVDTypeDef::Mode, PVD_FALLING_EDGE, PVD_MODE_EVT, PVD_MODE_IT, PVD_RISING_EDGE, and PWR_PVDTypeDef::PVDLevel.

void HAL_PWR_DisablePVD ( void )

Disables the Power Voltage Detector(PVD).

Return values:
None

Definition at line 387 of file stm32f1xx_hal_pwr.c.

References CR_PVDE_BB.

void HAL_PWR_DisableSEVOnPend ( void )

Disables CORTEX M3 SEVONPEND bit.

Note:
Clears SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 582 of file stm32f1xx_hal_pwr.c.

void HAL_PWR_DisableSleepOnExit ( void )

Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.

Note:
Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over.
Return values:
None

Definition at line 556 of file stm32f1xx_hal_pwr.c.

void HAL_PWR_DisableWakeUpPin ( uint32_t WakeUpPinx )

Disables the WakeUp PINx functionality.

Parameters:
WakeUpPinx,: Specifies the Power Wake-Up pin to disable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1
Return values:
None

Definition at line 415 of file stm32f1xx_hal_pwr.c.

References assert_param, CSR_EWUP_BB, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnablePVD ( void )

Enables the Power Voltage Detector(PVD).

Return values:
None

Definition at line 377 of file stm32f1xx_hal_pwr.c.

References CR_PVDE_BB.

void HAL_PWR_EnableSEVOnPend ( void )

Enables CORTEX M3 SEVONPEND bit.

Note:
Sets SEVONPEND bit of SCR register. When this bit is set, this causes WFE to wake up when an interrupt moves from inactive to pended.
Return values:
None

Definition at line 569 of file stm32f1xx_hal_pwr.c.

void HAL_PWR_EnableSleepOnExit ( void )

Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.

Note:
Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor re-enters SLEEP mode when an interruption handling is over. Setting this bit is useful when the processor is expected to run only on interruptions handling.
Return values:
None

Definition at line 543 of file stm32f1xx_hal_pwr.c.

void HAL_PWR_EnableWakeUpPin ( uint32_t WakeUpPinx )

Enables the WakeUp PINx functionality.

Parameters:
WakeUpPinx,: Specifies the Power Wake-Up pin to enable. This parameter can be one of the following values:
  • PWR_WAKEUP_PIN1
Return values:
None

Definition at line 400 of file stm32f1xx_hal_pwr.c.

References assert_param, CSR_EWUP_BB, and IS_PWR_WAKEUP_PIN.

void HAL_PWR_EnterSLEEPMode | ( | uint32_t | Regulator,
 |  | uint8_t | SLEEPEntry
 | ) |  |

Enters Sleep mode.

Note:
In Sleep mode, all I/O pins keep the same state as in Run mode.
Parameters:
Regulator,: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software
SLEEPEntry,: Specifies if SLEEP mode is entered with WFI or WFE instruction. When WFI entry is used, tick interrupt have to be disabled if not desired as the interrupt wake up source. This parameter can be one of the following values:
  • PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  • PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
Return values:
None

Definition at line 435 of file stm32f1xx_hal_pwr.c.

References assert_param, IS_PWR_SLEEP_ENTRY, and PWR_SLEEPENTRY_WFI.

void HAL_PWR_EnterSTANDBYMode ( void )

Enters Standby mode.

Note:
In Standby mode, all I/O pins are high impedance except for:
  • Reset pad (still available)
  • TAMPER pin if configured for tamper or calibration out.
  • WKUP pin (PA0) if enabled.
Return values:
None

Definition at line 518 of file stm32f1xx_hal_pwr.c.

void HAL_PWR_EnterSTOPMode | ( | uint32_t | Regulator,
 |  | uint8_t | STOPEntry
 | ) |  |

Enters Stop mode.

Note:
In Stop mode, all I/O pins keep the same state as in Run mode.
When exiting Stop mode by using an interrupt or a wakeup event, HSI RC oscillator is selected as system clock.
When the voltage regulator operates in low power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.
Parameters:
Regulator,: Specifies the regulator state in Stop mode. This parameter can be one of the following values:
  • PWR_MAINREGULATOR_ON: Stop mode with regulator ON
  • PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
STOPEntry,: Specifies if Stop mode in entered with WFI or WFE instruction. This parameter can be one of the following values:
  • PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
  • PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
Return values:
None

Definition at line 478 of file stm32f1xx_hal_pwr.c.

References assert_param, IS_PWR_REGULATOR, IS_PWR_STOP_ENTRY, PWR_OverloadWfe(), and PWR_STOPENTRY_WFI.

void HAL_PWR_PVD_IRQHandler ( void )

This function handles the PWR PVD interrupt request.

Note:
This API should be called under the PVD_IRQHandler().
Return values:
None

Definition at line 595 of file stm32f1xx_hal_pwr.c.

References __HAL_PWR_PVD_EXTI_CLEAR_FLAG, __HAL_PWR_PVD_EXTI_GET_FLAG, and HAL_PWR_PVDCallback().

void HAL_PWR_PVDCallback ( void )

PWR PVD interrupt callback.

Return values:
None

Definition at line 612 of file stm32f1xx_hal_pwr.c.

Referenced by HAL_PWR_PVD_IRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR_PVDTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
PWR_PVDTypeDef Struct Reference
PWR Exported Types

PWR PVD configuration structure definition. More...

#include <stm32f1xx_hal_pwr.h>

Data Fields

uint32_t | PVDLevel
uint32_t | Mode

Detailed Description

PWR PVD configuration structure definition.

Definition at line 66 of file stm32f1xx_hal_pwr.h.

Field Documentation

uint32_t PWR_PVDTypeDef::Mode

Mode: Specifies the operating mode for the selected pins. This parameter can be a value of PWR PVD Mode

Definition at line 71 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

uint32_t PWR_PVDTypeDef::PVDLevel

PVDLevel: Specifies the PVD detection level. This parameter can be a value of PWR PVD detection level

Definition at line 68 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_pwr.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR PVD detection level

Defines
PWR PVD detection level
PWR Exported Constants

Defines

#define | PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
#define | PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
#define | PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
#define | PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
#define | PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
#define | PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
#define | PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
#define | PWR_PVDLEVEL_7 PWR_CR_PLS_2V9

Define Documentation

#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2

Definition at line 103 of file stm32f1xx_hal_pwr.h.

#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3

Definition at line 104 of file stm32f1xx_hal_pwr.h.

#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4

Definition at line 105 of file stm32f1xx_hal_pwr.h.

#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5

Definition at line 106 of file stm32f1xx_hal_pwr.h.

#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6

Definition at line 107 of file stm32f1xx_hal_pwr.h.

#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7

Definition at line 108 of file stm32f1xx_hal_pwr.h.

#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8

Definition at line 109 of file stm32f1xx_hal_pwr.h.

#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9

Definition at line 110 of file stm32f1xx_hal_pwr.h.

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STM32F103xB HAL User Manual: PWR PVD Mode

Defines
PWR PVD Mode
PWR Exported Constants

Defines

#define | PWR_PVD_MODE_NORMAL 0x00000000U
#define | PWR_PVD_MODE_IT_RISING 0x00010001U
#define | PWR_PVD_MODE_IT_FALLING 0x00010002U
#define | PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U
#define | PWR_PVD_MODE_EVENT_RISING 0x00020001U
#define | PWR_PVD_MODE_EVENT_FALLING 0x00020002U
#define | PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U

Define Documentation

#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U

Event Mode with Falling edge trigger detection

Definition at line 124 of file stm32f1xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING 0x00020001U

Event Mode with Rising edge trigger detection

Definition at line 123 of file stm32f1xx_hal_pwr.h.

#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U

Event Mode with Rising/Falling edge trigger detection

Definition at line 125 of file stm32f1xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_FALLING 0x00010002U

External Interrupt Mode with Falling edge trigger detection

Definition at line 121 of file stm32f1xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING 0x00010001U

External Interrupt Mode with Rising edge trigger detection

Definition at line 120 of file stm32f1xx_hal_pwr.h.

#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U

External Interrupt Mode with Rising/Falling edge trigger detection

Definition at line 122 of file stm32f1xx_hal_pwr.h.

#define PWR_PVD_MODE_NORMAL 0x00000000U

basic mode is used

Definition at line 119 of file stm32f1xx_hal_pwr.h.

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STM32F103xB HAL User Manual: PWR WakeUp Pins

Defines
PWR WakeUp Pins
PWR Exported Constants

Defines

#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP

Define Documentation

#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP

Definition at line 136 of file stm32f1xx_hal_pwr.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR Regulator state in SLEEP/STOP mode

Defines
PWR Regulator state in SLEEP/STOP mode
PWR Exported Constants

Defines

#define | PWR_MAINREGULATOR_ON 0x00000000U
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS

Define Documentation

#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS

Definition at line 146 of file stm32f1xx_hal_pwr.h.

#define PWR_MAINREGULATOR_ON 0x00000000U

Definition at line 145 of file stm32f1xx_hal_pwr.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR SLEEP mode entry

Defines
PWR SLEEP mode entry
PWR Exported Constants

Defines

#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

Define Documentation

#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)

Definition at line 156 of file stm32f1xx_hal_pwr.h.

#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)

Definition at line 155 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR STOP mode entry

Defines
PWR STOP mode entry
PWR Exported Constants

Defines

#define | PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02)

Define Documentation

#define PWR_STOPENTRY_WFE ((uint8_t)0x02)

Definition at line 166 of file stm32f1xx_hal_pwr.h.

#define PWR_STOPENTRY_WFI ((uint8_t)0x01)

Definition at line 165 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR Flag

Defines
PWR Flag
PWR Exported Constants

Defines

#define | PWR_FLAG_WU PWR_CSR_WUF
#define | PWR_FLAG_SB PWR_CSR_SBF
#define | PWR_FLAG_PVDO PWR_CSR_PVDO

Define Documentation

#define PWR_FLAG_PVDO PWR_CSR_PVDO

Definition at line 177 of file stm32f1xx_hal_pwr.h.

#define PWR_FLAG_SB PWR_CSR_SBF

Definition at line 176 of file stm32f1xx_hal_pwr.h.

#define PWR_FLAG_WU PWR_CSR_WUF

Definition at line 175 of file stm32f1xx_hal_pwr.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR Exported Macros

Defines
PWR Exported Macros
PWR

Defines

#define | __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
Check PWR flag is set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
Clear the PWR's pending flags.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
Enable interrupt on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
Disable interrupt on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
Enable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
Disable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
PVD EXTI line configuration: set falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
PVD EXTI line configuration: set rising edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
PVD EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
Check whether the specified PVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Clear the PVD EXTI flag.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
Generate a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_PWR_CLEAR_FLAG ( __FLAG__ ) SET_BIT(PWR->CR, ((__FLAG__) << 2))

Clear the PWR's pending flags.

Parameters:
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • PWR_FLAG_WU: Wake Up flag
  • PWR_FLAG_SB: StandBy flag

Definition at line 216 of file stm32f1xx_hal_pwr.h.

#define __HAL_PWR_GET_FLAG ( __FLAG__ ) ((PWR->CSR & (__FLAG__)) == (__FLAG__))

Check PWR flag is set or not.

Parameters:
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event was received from the WKUP pin or from the RTC alarm An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high.
  • PWR_FLAG_SB: StandBy flag. This flag indicates that the system was resumed from StandBy mode.
  • PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 208 of file stm32f1xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG ( ) (EXTI->PR = (PWR_EXTI_LINE_PVD))

Clear the PVD EXTI flag.

Return values:
None.

Definition at line 295 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_PVD_IRQHandler().

#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)

Disable event on PVD Exti Line 16.

Return values:
None.

Definition at line 240 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 254 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)

Disable interrupt on PVD Exti Line 16.

Return values:
None.

Definition at line 228 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)

Disable the PVD Extended Interrupt Rising Trigger.

This parameter can be:

Return values:
None.

Definition at line 268 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE ( ) __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();

Disable the PVD Extended Interrupt Rising & Falling Trigger.

This parameter can be:

Return values:
None.

Definition at line 281 of file stm32f1xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)

Enable event on PVD Exti Line 16.

Return values:
None.

Definition at line 234 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)

PVD EXTI line configuration: set falling edge trigger.

Return values:
None.

Definition at line 247 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)

Enable interrupt on PVD Exti Line 16.

Return values:
None.

Definition at line 222 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)

PVD EXTI line configuration: set rising edge trigger.

Return values:
None.

Definition at line 261 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE ( ) __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();

PVD EXTI line configuration: set rising & falling edge trigger.

Return values:
None.

Definition at line 274 of file stm32f1xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)

Generate a Software interrupt on selected EXTI line.

Return values:
None.

Definition at line 301 of file stm32f1xx_hal_pwr.h.

#define __HAL_PWR_PVD_EXTI_GET_FLAG ( ) (EXTI->PR & (PWR_EXTI_LINE_PVD))

Check whether the specified PVD EXTI interrupt flag is set or not.

Return values:
EXTI PVD Line Status.

Definition at line 289 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_PVD_IRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR Private Macros

Defines
PWR Private Macros
PWR

Defines

#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Define Documentation

#define IS_PWR_PVD_LEVEL ( LEVEL )
Value:
(((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))

Definition at line 310 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_PVD_MODE ( MODE )
Value:
(((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
                              ((MODE) == PWR_PVD_MODE_NORMAL))

Definition at line 316 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_ConfigPVD().

#define IS_PWR_REGULATOR ( REGULATOR )
Value:
(((REGULATOR) == PWR_MAINREGULATOR_ON) || \
                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

Definition at line 323 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

#define IS_PWR_SLEEP_ENTRY ( ENTRY ) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))

Definition at line 326 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSLEEPMode().

#define IS_PWR_STOP_ENTRY ( ENTRY ) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Definition at line 328 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_EnterSTOPMode().

#define IS_PWR_WAKEUP_PIN ( PIN ) (((PIN) == PWR_WAKEUP_PIN1))

Definition at line 321 of file stm32f1xx_hal_pwr.h.

Referenced by HAL_PWR_DisableWakeUpPin(), and HAL_PWR_EnableWakeUpPin().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC Timeout

Defines
RCC Timeout
RCC Private Constants

Defines

#define | RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define | CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Define Documentation

#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */

Definition at line 1222 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

Definition at line 1223 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 1224 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 1225 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

Definition at line 1226 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */

Definition at line 1219 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

Definition at line 1221 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Register offsets

Defines
Register offsets
RCC Private Constants

Defines

#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define | RCC_CR_OFFSET 0x00U
#define | RCC_CFGR_OFFSET 0x04U
#define | RCC_CIR_OFFSET 0x08U
#define | RCC_BDCR_OFFSET 0x20U
#define | RCC_CSR_OFFSET 0x24U

Define Documentation

#define RCC_BDCR_OFFSET 0x20U

Definition at line 1239 of file stm32f1xx_hal_rcc.h.

#define RCC_CFGR_OFFSET 0x04U

Definition at line 1237 of file stm32f1xx_hal_rcc.h.

#define RCC_CIR_OFFSET 0x08U

Definition at line 1238 of file stm32f1xx_hal_rcc.h.

#define RCC_CR_OFFSET 0x00U

Definition at line 1236 of file stm32f1xx_hal_rcc.h.

#define RCC_CSR_OFFSET 0x24U

Definition at line 1240 of file stm32f1xx_hal_rcc.h.

#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)

Definition at line 1235 of file stm32f1xx_hal_rcc.h.

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STM32F103xB HAL User Manual: BitAddress AliasRegion

Defines
BitAddress AliasRegion
RCC Private Constants

RCC registers bit address in the alias region. More...

Defines

#define | RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
#define | RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
#define | RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
#define | RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
#define | RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
#define | RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
#define | RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
#define | RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
#define | RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
#define | RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
#define | RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
#define | RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
#define | RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
#define | RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
#define | RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
#define | RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
#define | RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
#define | RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
#define | RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
#define | RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
#define | RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
#define | RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
#define | RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
#define | RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
#define | RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))

Detailed Description

RCC registers bit address in the alias region.

Define Documentation

#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))

Definition at line 1294 of file stm32f1xx_hal_rcc.h.

#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))

Definition at line 1286 of file stm32f1xx_hal_rcc.h.

#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))

Definition at line 1282 of file stm32f1xx_hal_rcc.h.

#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)

Definition at line 1253 of file stm32f1xx_hal_rcc.h.

#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))

Definition at line 1290 of file stm32f1xx_hal_rcc.h.

#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos

Definition at line 1293 of file stm32f1xx_hal_rcc.h.

#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)

Definition at line 1251 of file stm32f1xx_hal_rcc.h.

#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)

Definition at line 1252 of file stm32f1xx_hal_rcc.h.

#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))

Definition at line 1265 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_DisableCSS(), and HAL_RCC_EnableCSS().

#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))

Definition at line 1262 of file stm32f1xx_hal_rcc.h.

#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))

Definition at line 1259 of file stm32f1xx_hal_rcc.h.

#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)

Definition at line 1250 of file stm32f1xx_hal_rcc.h.

#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))

Definition at line 1268 of file stm32f1xx_hal_rcc.h.

#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))

Definition at line 1273 of file stm32f1xx_hal_rcc.h.

#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)

Definition at line 1254 of file stm32f1xx_hal_rcc.h.

#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))

Definition at line 1277 of file stm32f1xx_hal_rcc.h.

#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos

Definition at line 1264 of file stm32f1xx_hal_rcc.h.

#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos

Definition at line 1261 of file stm32f1xx_hal_rcc.h.

#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos

Definition at line 1258 of file stm32f1xx_hal_rcc.h.

#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos

Definition at line 1285 of file stm32f1xx_hal_rcc.h.

#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos

Definition at line 1281 of file stm32f1xx_hal_rcc.h.

#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos

Definition at line 1272 of file stm32f1xx_hal_rcc.h.

#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos

Definition at line 1267 of file stm32f1xx_hal_rcc.h.

#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos

Definition at line 1276 of file stm32f1xx_hal_rcc.h.

#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos

Definition at line 1289 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC Private Constants

Modules | Defines
RCC Private Constants
RCC

Modules

RCC Timeout
Register offsets
BitAddress AliasRegion

RCC registers bit address in the alias region.

Defines

#define | RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
#define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
#define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
#define | CR_REG_INDEX ((uint8_t)1)
#define | BDCR_REG_INDEX ((uint8_t)2)
#define | CSR_REG_INDEX ((uint8_t)3)
#define | RCC_FLAG_MASK ((uint8_t)0x1F)

Define Documentation

#define BDCR_REG_INDEX ((uint8_t)2)

Definition at line 1311 of file stm32f1xx_hal_rcc.h.

#define CR_REG_INDEX ((uint8_t)1)

Definition at line 1310 of file stm32f1xx_hal_rcc.h.

#define CSR_REG_INDEX ((uint8_t)3)

Definition at line 1312 of file stm32f1xx_hal_rcc.h.

#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))

Definition at line 1304 of file stm32f1xx_hal_rcc.h.

#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))

Definition at line 1307 of file stm32f1xx_hal_rcc.h.

#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))

Definition at line 1301 of file stm32f1xx_hal_rcc.h.

#define RCC_FLAG_MASK ((uint8_t)0x1F)

Definition at line 1314 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Alias define maintained for legacy

Defines
Alias define maintained for legacy
RCC Private Macros

Defines

#define | __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
#define | __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
#define | __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
#define | __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET

Define Documentation

#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE

Definition at line 1326 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE

Definition at line 1327 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET

Definition at line 1328 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET

Definition at line 1329 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC Private Macros

Modules | Defines
RCC Private Macros
RCC

Modules

Alias define maintained for legacy

Defines

#define | MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_CLOCKTYPE(CLK)
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__)
#define | IS_RCC_HCLK(__HCLK__)
#define | IS_RCC_PCLK(__PCLK__)
#define | IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
#define | IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)

Define Documentation

#define IS_RCC_CALIBRATION_VALUE ( __VALUE__ ) ((__VALUE__) <= 0x1FU)

Definition at line 1346 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_CLOCKTYPE ( CLK )
Value:
((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
                               (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
                               (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
                               (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))

Definition at line 1351 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HCLK ( __HCLK__ )
Value:
(((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
                               ((__HCLK__) == RCC_SYSCLK_DIV512))

Definition at line 1361 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_HSE ( __HSE__ )
Value:
(((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
                             ((__HSE__) == RCC_HSE_BYPASS))

Definition at line 1341 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_HSI ( __HSI__ ) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))

Definition at line 1345 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSE ( __LSE__ )
Value:
(((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
                             ((__LSE__) == RCC_LSE_BYPASS))

Definition at line 1343 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_LSI ( __LSI__ ) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))

Definition at line 1347 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO ( __MCO__ ) ((__MCO__) == RCC_MCO)

Definition at line 1369 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_MCODIV ( __DIV__ ) (((__DIV__) == RCC_MCODIV_1))

Definition at line 1370 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_OSCILLATORTYPE ( __OSCILLATOR__ )
Value:
(((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))

Definition at line 1336 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PCLK ( __PCLK__ )
Value:
(((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
                               ((__PCLK__) == RCC_HCLK_DIV16))

Definition at line 1366 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_PLL ( __PLL__ )
Value:
(((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
                             ((__PLL__) == RCC_PLL_ON))

Definition at line 1348 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_PLLSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))

Definition at line 1334 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_RTCCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
                                          ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))

Definition at line 1371 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_SYSCLKSOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))

Definition at line 1355 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define IS_RCC_SYSCLKSOURCE_STATUS ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
                                                ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))

Definition at line 1358 of file stm32f1xx_hal_rcc.h.

#define MCO1_CLK_ENABLE ( ) __HAL_RCC_GPIOA_CLK_ENABLE()

Definition at line 107 of file stm32f1xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_GPIO_PORT GPIOA

Definition at line 108 of file stm32f1xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

#define MCO1_PIN GPIO_PIN_8

Definition at line 109 of file stm32f1xx_hal_rcc.c.

Referenced by HAL_RCC_MCOConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC Private Variables

RCC Private Variables
RCC
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RCC Exported Functions

Initialization and Configuration functions. More...

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Detailed Description

Initialization and Configuration functions.

  ===============================================================================
           ##### Initialization and de-initialization functions #####
  ===============================================================================
    [..]
      This section provides functions allowing to configure the internal/external oscillators
      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
      and APB2).

    [..] Internal/external clock and PLL configuration
      (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
          the PLL as System clock source.
      (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
          clock source.

      (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x)  crystal oscillator used directly or
          through the PLL as System clock source. Can be used also as RTC clock source.

      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

      (#) PLL (clocked by HSI or HSE), featuring different output clocks:
        (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)

      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
          and if a HSE clock failure occurs(HSE used directly or through PLL as System
          clock source), the System clocks automatically switched to HSI and an interrupt
          is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
          (Non-Maskable Interrupt) exception vector.

      (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
          HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x

    [..] System, AHB and APB buses clocks configuration
      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
          HSE and PLL.
          The AHB clock (HCLK) is derived from System clock through configurable
          prescaler and used to clock the CPU, memory and peripherals mapped
          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
          from AHB clock through configurable prescalers and used to clock
          the peripherals mapped on these buses. You can use
          "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
              divided by 128.
          (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
              to work correctly. This clock is derived of the main PLL through PLL Multiplier.
          (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
          (+@) IWDG clock which is always the LSI clock.

      (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
          For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
          Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.

Function Documentation

HAL_StatusTypeDef HAL_RCC_ClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t | FLatency
 | ) |  |

Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters:
RCC_ClkInitStruct | pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency | FLASH Latency The value of this parameter depend on device used within the same series
Note:
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this function
The HSI is used (enabled by hardware) as system clock source after start-up from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after start-up delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use HAL_RCC_GetClockConfig() function to know which clock is currently used as system clock source.
Return values:
HAL status

Definition at line 707 of file stm32f1xx_hal_rcc.c.

References __HAL_FLASH_SET_LATENCY, __HAL_RCC_GET_FLAG, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_SYSCLK_CONFIG, RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, CLOCKSWITCH_TIMEOUT_VALUE, RCC_ClkInitTypeDef::ClockType, HAL_GetTick(), HAL_InitTick(), HAL_RCC_GetSysClockFreq(), IS_FLASH_LATENCY, IS_RCC_CLOCKTYPE, IS_RCC_HCLK, IS_RCC_PCLK, IS_RCC_SYSCLKSOURCE, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_PLLRDY, RCC_SYSCLKSOURCE_HSE, RCC_SYSCLKSOURCE_PLLCLK, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, RCC_SYSCLKSOURCE_STATUS_PLLCLK, RCC_ClkInitTypeDef::SYSCLKSource, and TICK_INT_PRIORITY.

void HAL_RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE and PLL OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS and MCO1 OFF
  • All interrupts disabled
This function does not modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Return values:
None

Definition at line 217 of file stm32f1xx_hal_rcc.c.

References HSI_VALUE.

HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters:
RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.
Note:
The PLL is not disabled when used as system clock.
The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Return values:
HAL status

Definition at line 261 of file stm32f1xx_hal_rcc.c.

References __HAL_RCC_GET_FLAG, __HAL_RCC_GET_PLL_OSCSOURCE, __HAL_RCC_GET_SYSCLK_SOURCE, __HAL_RCC_HSE_CONFIG, __HAL_RCC_HSE_PREDIV_CONFIG, __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST, __HAL_RCC_HSI_DISABLE, __HAL_RCC_HSI_ENABLE, __HAL_RCC_LSE_CONFIG, __HAL_RCC_LSI_DISABLE, __HAL_RCC_LSI_ENABLE, __HAL_RCC_PLL_CONFIG, __HAL_RCC_PLL_DISABLE, __HAL_RCC_PLL_ENABLE, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, assert_param, HAL_Delay(), HAL_GetTick(), HSE_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSEPredivValue, RCC_OscInitTypeDef::HSEState, HSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, IS_RCC_CALIBRATION_VALUE, IS_RCC_HSE, IS_RCC_HSE_PREDIV, IS_RCC_HSI, IS_RCC_LSE, IS_RCC_LSI, IS_RCC_OSCILLATORTYPE, IS_RCC_PLL, IS_RCC_PLL_MUL, IS_RCC_PLLSOURCE, RCC_OscInitTypeDef::LSEState, LSI_TIMEOUT_VALUE, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, PLL_TIMEOUT_VALUE, RCC_PLLInitTypeDef::PLLMUL, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_HSERDY, RCC_FLAG_HSIRDY, RCC_FLAG_LSERDY, RCC_FLAG_LSIRDY, RCC_FLAG_PLLRDY, RCC_HSE_OFF, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_OFF, RCC_LSE_TIMEOUT_VALUE, RCC_LSI_OFF, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_NONE, RCC_PLL_ON, RCC_PLLSOURCE_HSE, RCC_PLLSOURCE_HSI_DIV2, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, and RCC_SYSCLKSOURCE_STATUS_PLLCLK.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCC Exported Functions

RCC clocks control functions. More...

Functions

void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO pin.
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC clocks control functions.

  ===============================================================================
                  ##### Peripheral Control functions #####
  ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.

Function Documentation

void HAL_RCC_CSSCallback ( void )

RCC Clock Security System interrupt callback.

Return values:
none

Definition at line 1258 of file stm32f1xx_hal_rcc.c.

Referenced by HAL_RCC_NMI_IRQHandler().

void HAL_RCC_DisableCSS ( void )

Disables the Clock Security System.

Return values:
None

Definition at line 942 of file stm32f1xx_hal_rcc.c.

References RCC_CR_CSSON_BB.

void HAL_RCC_EnableCSS ( void )

Enables the Clock Security System.

Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
Return values:
None

Definition at line 933 of file stm32f1xx_hal_rcc.c.

References RCC_CR_CSSON_BB.

void HAL_RCC_GetClockConfig | ( | RCC_ClkInitTypeDef * | RCC_ClkInitStruct,
 |  | uint32_t * | pFLatency
 | ) |  |

Get the RCC_ClkInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_ClkInitStruct | pointer to an RCC_ClkInitTypeDef structure that contains the current clock configuration.
pFLatency | Pointer on the Flash Latency.
Return values:
None

Definition at line 1206 of file stm32f1xx_hal_rcc.c.

References RCC_ClkInitTypeDef::AHBCLKDivider, RCC_ClkInitTypeDef::APB1CLKDivider, RCC_ClkInitTypeDef::APB2CLKDivider, assert_param, RCC_ClkInitTypeDef::ClockType, FLASH_LATENCY_0, RCC_CLOCKTYPE_HCLK, RCC_CLOCKTYPE_PCLK1, RCC_CLOCKTYPE_PCLK2, RCC_CLOCKTYPE_SYSCLK, and RCC_ClkInitTypeDef::SYSCLKSource.

uint32_t HAL_RCC_GetHCLKFreq ( void )

Returns the HCLK frequency.

Note:
Each time HCLK changes, this function must be called to update the right HCLK value. Otherwise, any configuration based on this function will be incorrect.
The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated within this function
Return values:
HCLK frequency

Definition at line 1070 of file stm32f1xx_hal_rcc.c.

Referenced by HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq().

void HAL_RCC_GetOscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Configures the RCC_OscInitStruct according to the internal RCC configuration registers.

Parameters:
RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
Return values:
None

Definition at line 1106 of file stm32f1xx_hal_rcc.c.

References __HAL_RCC_HSE_GET_PREDIV, assert_param, RCC_OscInitTypeDef::HSEPredivValue, RCC_OscInitTypeDef::HSEState, RCC_OscInitTypeDef::HSICalibrationValue, RCC_OscInitTypeDef::HSIState, RCC_OscInitTypeDef::LSEState, RCC_OscInitTypeDef::LSIState, RCC_OscInitTypeDef::OscillatorType, RCC_OscInitTypeDef::PLL, RCC_PLLInitTypeDef::PLLMUL, RCC_PLLInitTypeDef::PLLSource, RCC_PLLInitTypeDef::PLLState, RCC_HSE_BYPASS, RCC_HSE_OFF, RCC_HSE_ON, RCC_HSI_OFF, RCC_HSI_ON, RCC_LSE_BYPASS, RCC_LSE_OFF, RCC_LSE_ON, RCC_LSI_OFF, RCC_LSI_ON, RCC_OSCILLATORTYPE_HSE, RCC_OSCILLATORTYPE_HSI, RCC_OSCILLATORTYPE_LSE, RCC_OSCILLATORTYPE_LSI, RCC_PLL_OFF, and RCC_PLL_ON.

uint32_t HAL_RCC_GetPCLK1Freq ( void )

Returns the PCLK1 frequency.

Note:
Each time PCLK1 changes, this function must be called to update the right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK1 frequency

Definition at line 1081 of file stm32f1xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by HAL_I2C_Init(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetPCLK2Freq ( void )

Returns the PCLK2 frequency.

Note:
Each time PCLK2 changes, this function must be called to update the right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
Return values:
PCLK2 frequency

Definition at line 1093 of file stm32f1xx_hal_rcc.c.

References HAL_RCC_GetHCLKFreq().

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), IRDA_SetConfig(), SMARTCARD_SetConfig(), UART_SetConfig(), and USART_SetConfig().

uint32_t HAL_RCC_GetSysClockFreq ( void )

Returns the SYSCLK frequency.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns a value based on HSE_VALUE divided by PREDIV factor(**)
If SYSCLK source is PLL, function returns a value based on HSE_VALUE divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
(*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value 8 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
This function can be used by the user application to compute the baud-rate for the communication peripherals or configure other parameters.
Each time SYSCLK changes, this function must be called to update the right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
Return values:
SYSCLK frequency

Definition at line 976 of file stm32f1xx_hal_rcc.c.

References HSE_VALUE, HSI_VALUE, RCC_PLLSOURCE_HSI_DIV2, RCC_SYSCLKSOURCE_STATUS_HSE, RCC_SYSCLKSOURCE_STATUS_HSI, and RCC_SYSCLKSOURCE_STATUS_PLLCLK.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

void HAL_RCC_MCOConfig | ( | uint32_t | RCC_MCOx,
 |  | uint32_t | RCC_MCOSource,
 |  | uint32_t | RCC_MCODiv
 | ) |  |

Selects the clock source to output on MCO pin.

Note:
MCO pin should be configured in alternate function mode.
Parameters:
RCC_MCOx specifies the output direction for the clock source. This parameter can be one of the following values:
  • RCC_MCO1 Clock source to output on MCO1 pin(PA8).
RCC_MCOSource specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
  • RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
  • RCC_MCO1SOURCE_HSI HSI selected as MCO clock
  • RCC_MCO1SOURCE_HSE HSE selected as MCO clock
RCC_MCODiv specifies the MCO DIV. This parameter can be one of the following values:
  • RCC_MCODIV_1 no division applied to MCO clock
Return values:
None

Definition at line 900 of file stm32f1xx_hal_rcc.c.

References __HAL_RCC_MCO1_CONFIG, assert_param, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_SPEED_FREQ_HIGH, HAL_GPIO_Init(), IS_RCC_MCO, IS_RCC_MCO1SOURCE, IS_RCC_MCODIV, MCO1_CLK_ENABLE, MCO1_GPIO_PORT, MCO1_PIN, GPIO_InitTypeDef::Mode, GPIO_InitTypeDef::Pin, GPIO_InitTypeDef::Pull, and GPIO_InitTypeDef::Speed.

void HAL_RCC_NMI_IRQHandler ( void )

This function handles the RCC CSS interrupt request.

Note:
This API should be called under the NMI_Handler().
Return values:
None

Definition at line 1241 of file stm32f1xx_hal_rcc.c.

References __HAL_RCC_CLEAR_IT, __HAL_RCC_GET_IT, HAL_RCC_CSSCallback(), and RCC_IT_CSS.

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STM32F103xB HAL User Manual: RCC_PLLInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PLLInitTypeDef Struct Reference
RCC Exported Types

RCC PLL configuration structure definition. More...

#include <stm32f1xx_hal_rcc.h>

Data Fields

uint32_t | PLLState
uint32_t | PLLSource
uint32_t | PLLMUL

Detailed Description

RCC PLL configuration structure definition.

Definition at line 66 of file stm32f1xx_hal_rcc.h.

Field Documentation

uint32_t RCC_PLLInitTypeDef::PLLMUL

PLLMUL: Multiplication factor for PLL VCO input clock This parameter must be a value of PLL Multiplication Factor

Definition at line 74 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLSource

PLLSource: PLL entry clock source. This parameter must be a value of PLL Clock Source

Definition at line 71 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_PLLInitTypeDef::PLLState

PLLState: The new state of the PLL. This parameter can be a value of PLL Config

Definition at line 68 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_rcc.h
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STM32F103xB HAL User Manual: RCC_ClkInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_ClkInitTypeDef Struct Reference
RCC Exported Types

RCC System, AHB and APB busses clock configuration structure definition. More...

#include <stm32f1xx_hal_rcc.h>

Data Fields

uint32_t | ClockType
uint32_t | SYSCLKSource
uint32_t | AHBCLKDivider
uint32_t | APB1CLKDivider
uint32_t | APB2CLKDivider

Detailed Description

RCC System, AHB and APB busses clock configuration structure definition.

Definition at line 81 of file stm32f1xx_hal_rcc.h.

Field Documentation

uint32_t RCC_ClkInitTypeDef::AHBCLKDivider

The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB Clock Source

Definition at line 89 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB1CLKDivider

The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1 APB2 Clock Source

Definition at line 92 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::APB2CLKDivider

The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB1 APB2 Clock Source

Definition at line 95 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::ClockType

The clock to be configured. This parameter can be a value of System Clock Type

Definition at line 83 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

uint32_t RCC_ClkInitTypeDef::SYSCLKSource

The clock source (SYSCLKS) used as system clock. This parameter can be a value of System Clock Source

Definition at line 86 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_rcc.h
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STM32F103xB HAL User Manual: PLL Clock Source

Defines
PLL Clock Source
RCC Exported Constants

Defines

#define | RCC_PLLSOURCE_HSI_DIV2 0x00000000U
#define | RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC

Define Documentation

#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC

HSE clock selected as PLL entry clock source

Definition at line 113 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U

HSI clock divided by 2 selected as PLL entry clock source

Definition at line 112 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCC_OscConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

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STM32F103xB HAL User Manual: Oscillator Type

Defines
Oscillator Type
RCC Exported Constants

Defines

#define | RCC_OSCILLATORTYPE_NONE 0x00000000U
#define | RCC_OSCILLATORTYPE_HSE 0x00000001U
#define | RCC_OSCILLATORTYPE_HSI 0x00000002U
#define | RCC_OSCILLATORTYPE_LSE 0x00000004U
#define | RCC_OSCILLATORTYPE_LSI 0x00000008U

Define Documentation

#define RCC_OSCILLATORTYPE_HSE 0x00000001U

Definition at line 123 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_HSI 0x00000002U

Definition at line 124 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSE 0x00000004U

Definition at line 125 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_LSI 0x00000008U

Definition at line 126 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_OSCILLATORTYPE_NONE 0x00000000U

Definition at line 122 of file stm32f1xx_hal_rcc.h.

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STM32F103xB HAL User Manual: HSE Config

Defines
HSE Config
RCC Exported Constants

Defines

#define | RCC_HSE_OFF 0x00000000U
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

Define Documentation

#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

External clock source for HSE clock

Definition at line 136 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_HSE_OFF 0x00000000U

HSE clock deactivation

Definition at line 134 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSE_ON RCC_CR_HSEON

HSE clock activation

Definition at line 135 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

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STM32F103xB HAL User Manual: LSE Config

Defines
LSE Config
RCC Exported Constants

Defines

#define | RCC_LSE_OFF 0x00000000U
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

Define Documentation

#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

External clock source for LSE clock

Definition at line 146 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_LSE_OFF 0x00000000U

LSE clock deactivation

Definition at line 144 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSE_ON RCC_BDCR_LSEON

LSE clock activation

Definition at line 145 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

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STM32F103xB HAL User Manual: HSI Config

Defines
HSI Config
RCC Exported Constants

Defines

#define | RCC_HSI_OFF 0x00000000U
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */

Define Documentation

#define RCC_HSI_OFF 0x00000000U

HSI clock deactivation

Definition at line 155 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSI_ON RCC_CR_HSION

HSI clock activation

Definition at line 156 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */

Definition at line 158 of file stm32f1xx_hal_rcc.h.

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STM32F103xB HAL User Manual: LSI Config

Defines
LSI Config
RCC Exported Constants

Defines

#define | RCC_LSI_OFF 0x00000000U
#define | RCC_LSI_ON RCC_CSR_LSION

Define Documentation

#define RCC_LSI_OFF 0x00000000U

LSI clock deactivation

Definition at line 167 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

#define RCC_LSI_ON RCC_CSR_LSION

LSI clock activation

Definition at line 168 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

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STM32F103xB HAL User Manual: PLL Config

Defines
PLL Config
RCC Exported Constants

Defines

#define | RCC_PLL_NONE 0x00000000U
#define | RCC_PLL_OFF 0x00000001U
#define | RCC_PLL_ON 0x00000002U

Define Documentation

#define RCC_PLL_NONE 0x00000000U

PLL is not configured

Definition at line 177 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_PLL_OFF 0x00000001U

PLL deactivation

Definition at line 178 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig().

#define RCC_PLL_ON 0x00000002U

PLL activation

Definition at line 179 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

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STM32F103xB HAL User Manual: System Clock Type

Defines
System Clock Type
RCC Exported Constants

Defines

#define | RCC_CLOCKTYPE_SYSCLK 0x00000001U
#define | RCC_CLOCKTYPE_HCLK 0x00000002U
#define | RCC_CLOCKTYPE_PCLK1 0x00000004U
#define | RCC_CLOCKTYPE_PCLK2 0x00000008U

Define Documentation

#define RCC_CLOCKTYPE_HCLK 0x00000002U

HCLK to configure

Definition at line 189 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK1 0x00000004U

PCLK1 to configure

Definition at line 190 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_PCLK2 0x00000008U

PCLK2 to configure

Definition at line 191 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

#define RCC_CLOCKTYPE_SYSCLK 0x00000001U

SYSCLK to configure

Definition at line 188 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_GetClockConfig().

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STM32F103xB HAL User Manual: System Clock Source

Defines
System Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

HSE selected as system clock

Definition at line 201 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

HSI selected as system clock

Definition at line 200 of file stm32f1xx_hal_rcc.h.

#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

PLL selected as system clock

Definition at line 202 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

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STM32F103xB HAL User Manual: System Clock Source Status

Defines
System Clock Source Status
RCC Exported Constants

Defines

#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

Define Documentation

#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

HSE used as system clock

Definition at line 212 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

HSI used as system clock

Definition at line 211 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

PLL used as system clock

Definition at line 213 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_GetSysClockFreq(), and HAL_RCC_OscConfig().

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STM32F103xB HAL User Manual: AHB Clock Source

Defines
AHB Clock Source
RCC Exported Constants

Defines

#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

Define Documentation

#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1

SYSCLK not divided

Definition at line 222 of file stm32f1xx_hal_rcc.h.

#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128

SYSCLK divided by 128

Definition at line 228 of file stm32f1xx_hal_rcc.h.

#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16

SYSCLK divided by 16

Definition at line 226 of file stm32f1xx_hal_rcc.h.

#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2

SYSCLK divided by 2

Definition at line 223 of file stm32f1xx_hal_rcc.h.

#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256

SYSCLK divided by 256

Definition at line 229 of file stm32f1xx_hal_rcc.h.

#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4

SYSCLK divided by 4

Definition at line 224 of file stm32f1xx_hal_rcc.h.

#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

SYSCLK divided by 512

Definition at line 230 of file stm32f1xx_hal_rcc.h.

#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64

SYSCLK divided by 64

Definition at line 227 of file stm32f1xx_hal_rcc.h.

#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8

SYSCLK divided by 8

Definition at line 225 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB1 APB2 Clock Source

Defines
APB1 APB2 Clock Source
RCC Exported Constants

Defines

#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

Define Documentation

#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1

HCLK not divided

Definition at line 239 of file stm32f1xx_hal_rcc.h.

#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

HCLK divided by 16

Definition at line 243 of file stm32f1xx_hal_rcc.h.

#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2

HCLK divided by 2

Definition at line 240 of file stm32f1xx_hal_rcc.h.

#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4

HCLK divided by 4

Definition at line 241 of file stm32f1xx_hal_rcc.h.

#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8

HCLK divided by 8

Definition at line 242 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC Clock Source

Defines
RTC Clock Source
RCC Exported Constants

Defines

#define | RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
#define | RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE

Define Documentation

#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE

HSE oscillator clock divided by 128 used as RTC clock

Definition at line 255 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE

LSE oscillator clock used as RTC clock

Definition at line 253 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI

LSI oscillator clock used as RTC clock

Definition at line 254 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U

No clock

Definition at line 252 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: MCO Index

Defines
MCO Index
RCC Exported Constants

Defines

#define | RCC_MCO1 0x00000000U
#define | RCC_MCO RCC_MCO1

Define Documentation

#define RCC_MCO RCC_MCO1

MCO1 to be compliant with other families with 2 MCOs

Definition at line 265 of file stm32f1xx_hal_rcc.h.

#define RCC_MCO1 0x00000000U

Definition at line 264 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: MCO Clock Prescaler

Defines
MCO Clock Prescaler
RCC Exported Constants

Defines

#define RCC_MCODIV_1 0x00000000U

Define Documentation

#define RCC_MCODIV_1 0x00000000U

Definition at line 274 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Interrupts

Defines
Interrupts
RCC Exported Constants

Defines

#define | RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)
#define | RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)
#define | RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)
#define | RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)
#define | RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)
#define | RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)

Define Documentation

#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)

Clock Security System Interrupt flag

Definition at line 288 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)

HSE Ready Interrupt flag

Definition at line 286 of file stm32f1xx_hal_rcc.h.

#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)

HSI Ready Interrupt flag

Definition at line 285 of file stm32f1xx_hal_rcc.h.

#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)

LSE Ready Interrupt flag

Definition at line 284 of file stm32f1xx_hal_rcc.h.

#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)

LSI Ready Interrupt flag

Definition at line 283 of file stm32f1xx_hal_rcc.h.

#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)

PLL Ready Interrupt flag

Definition at line 287 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Flags

Defines
Flags
RCC Exported Constants

Elements values convention: XXXYYYYYb. More...

Defines

#define | RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos))
#define | RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos))
#define | RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos))
#define | RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos))
#define | RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))
#define | RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos))
#define | RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))
#define | RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos))
#define | RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos))
#define | RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos))
#define | RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos))

Detailed Description

Elements values convention: XXXYYYYYb.

  • YYYYY : Flag position in the register
  • XXX : Register index
    • 001: CR register
    • 010: BDCR register
    • 011: CSR register

Define Documentation

#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos))

External High Speed clock ready flag

Definition at line 304 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos))

Internal High Speed clock ready flag

Definition at line 303 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos))

Independent Watchdog reset flag

Definition at line 312 of file stm32f1xx_hal_rcc.h.

#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos))

Low-Power reset flag

Definition at line 314 of file stm32f1xx_hal_rcc.h.

#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos))

External Low Speed oscillator Ready

Definition at line 317 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos))

Internal Low Speed oscillator Ready

Definition at line 308 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))

PIN reset flag

Definition at line 309 of file stm32f1xx_hal_rcc.h.

#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos))

PLL clock ready flag

Definition at line 305 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos))

POR/PDR reset flag

Definition at line 310 of file stm32f1xx_hal_rcc.h.

#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))

Software Reset flag

Definition at line 311 of file stm32f1xx_hal_rcc.h.

#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos))

Window watchdog reset flag

Definition at line 313 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Clock Enable Disable

Defines
Peripheral Clock Enable Disable
RCC Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Defines

#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_SRAM_CLK_ENABLE()
#define | __HAL_RCC_FLITF_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
#define | __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
#define | __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))

Detailed Description

Enable or disable the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRC_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))

Definition at line 375 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_CRC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 364 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))

Definition at line 372 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_DMA1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 340 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_FLITF_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))

Definition at line 374 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_FLITF_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 356 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SRAM_CLK_DISABLE ( ) (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))

Definition at line 373 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SRAM_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 348 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: AHB Peripheral Clock Enable Disable Status

Defines
AHB Peripheral Clock Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the AHB peripheral clock. More...

Defines

#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
#define | __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
#define | __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
#define | __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
#define | __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)

Detailed Description

Get the enable or disable status of the AHB peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CRC_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)

Definition at line 396 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_CRC_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)

Definition at line 395 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)

Definition at line 390 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_DMA1_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)

Definition at line 389 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_FLITF_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)

Definition at line 394 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_FLITF_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)

Definition at line 393 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SRAM_IS_CLK_DISABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)

Definition at line 392 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SRAM_IS_CLK_ENABLED ( ) ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)

Definition at line 391 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB1 Clock Enable Disable

Defines
APB1 Clock Enable Disable
RCC Exported Macros

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Defines

#define | __HAL_RCC_TIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_BKP_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define | __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define | __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
#define | __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_BKP_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))

Definition at line 471 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_BKP_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 449 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

Definition at line 469 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_I2C1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 441 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_PWR_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

Definition at line 472 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PWR_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 457 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_TIM2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))

Definition at line 465 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 409 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))

Definition at line 466 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 417 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

Definition at line 468 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 433 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

Definition at line 467 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_WWDG_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 425 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB1 Peripheral Clock Enable Disable Status

Defines
APB1 Peripheral Clock Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define | __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
#define | __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

Detailed Description

Get the enable or disable status of the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_BKP_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)

Definition at line 497 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_BKP_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)

Definition at line 496 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)

Definition at line 495 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_I2C1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)

Definition at line 494 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_PWR_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

Definition at line 499 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_PWR_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)

Definition at line 498 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)

Definition at line 487 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)

Definition at line 486 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)

Definition at line 489 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM3_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)

Definition at line 488 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)

Definition at line 493 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)

Definition at line 492 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)

Definition at line 491 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_WWDG_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)

Definition at line 490 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB2 Clock Enable Disable

Defines
APB2 Clock Enable Disable
RCC Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Defines

#define | __HAL_RCC_AFIO_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_ADC1_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
#define | __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

Definition at line 589 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_ADC1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 552 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_AFIO_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))

Definition at line 584 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_AFIO_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 512 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_GPIO_Init().

#define __HAL_RCC_GPIOA_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))

Definition at line 585 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 520 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))

Definition at line 586 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 528 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))

Definition at line 587 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 536 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))

Definition at line 588 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 544 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

Definition at line 592 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SPI1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 568 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

Definition at line 591 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 560 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

Definition at line 593 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */\
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 576 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB2 Peripheral Clock Enable Disable Status

Defines
APB2 Peripheral Clock Enable Disable Status
RCC Exported Macros

Get the enable or disable status of the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
#define | __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
#define | __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define | __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)

Detailed Description

Get the enable or disable status of the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)

Definition at line 618 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_ADC1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)

Definition at line 617 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_AFIO_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)

Definition at line 608 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_AFIO_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)

Definition at line 607 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)

Definition at line 610 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)

Definition at line 609 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)

Definition at line 612 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)

Definition at line 611 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)

Definition at line 614 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)

Definition at line 613 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)

Definition at line 616 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)

Definition at line 615 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)

Definition at line 622 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SPI1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)

Definition at line 621 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)

Definition at line 620 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)

Definition at line 619 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)

Definition at line 624 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)

Definition at line 623 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB1 Force Release Reset

Defines
APB1 Force Release Reset
RCC Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
#define | __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
#define | __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_APB1_FORCE_RESET ( ) (RCC->APB2RSTR = 0xFFFFFFFFU)

Definition at line 634 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB1_RELEASE_RESET ( ) (RCC->APB1RSTR = 0x00)

Definition at line 644 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_BKP_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))

Definition at line 641 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_BKP_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))

Definition at line 651 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_I2C1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))

Definition at line 639 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_I2C1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))

Definition at line 649 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_PWR_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))

Definition at line 642 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_PWR_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))

Definition at line 652 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_PWR_DeInit().

#define __HAL_RCC_TIM2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))

Definition at line 635 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))

Definition at line 645 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM3_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))

Definition at line 636 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM3_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))

Definition at line 646 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))

Definition at line 638 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))

Definition at line 648 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_WWDG_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))

Definition at line 637 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_WWDG_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))

Definition at line 647 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB2 Force Release Reset

Defines
APB2 Force Release Reset
RCC Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
#define | __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
#define | __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
#define | __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
#define | __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
#define | __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_ADC1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))

Definition at line 668 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_ADC1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))

Definition at line 680 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_AFIO_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))

Definition at line 663 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_AFIO_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))

Definition at line 675 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_APB2_FORCE_RESET ( ) (RCC->APB2RSTR = 0xFFFFFFFFU)

Definition at line 662 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_APB2_RELEASE_RESET ( ) (RCC->APB2RSTR = 0x00)

Definition at line 674 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_DeInit().

#define __HAL_RCC_GPIOA_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))

Definition at line 664 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOA_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))

Definition at line 676 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))

Definition at line 665 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOB_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))

Definition at line 677 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))

Definition at line 666 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOC_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))

Definition at line 678 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))

Definition at line 667 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GPIOD_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))

Definition at line 679 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SPI1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))

Definition at line 671 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_SPI1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))

Definition at line 683 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))

Definition at line 670 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_TIM1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))

Definition at line 682 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART1_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))

Definition at line 672 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_USART1_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))

Definition at line 684 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: HSI Configuration

Defines
HSI Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Define Documentation

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( _HSICALIBRATIONVALUE_ ) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))

Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
_HSICALIBRATIONVALUE_ specifies the calibration trimming value. (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between 0 and 0x1F.

Definition at line 714 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_DISABLE ( ) (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)

Definition at line 705 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_HSI_ENABLE ( ) (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)

Macros to enable or disable the Internal High Speed oscillator (HSI).

Note:
The HSI is stopped by hardware when entering STOP and STANDBY modes.
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Definition at line 704 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LSI Configuration

Defines
LSI Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Macro to enable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Macro to disable the Internal Low Speed oscillator (LSI).

Define Documentation

#define __HAL_RCC_LSI_DISABLE ( ) (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)

Macro to disable the Internal Low Speed oscillator (LSI).

Note:
LSI can not be disabled if the IWDG is running.
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Definition at line 737 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_LSI_ENABLE ( ) (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)

Macro to enable the Internal Low Speed oscillator (LSI).

Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.

Definition at line 730 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: HSE Configuration

Defines
HSE Configuration
RCC Exported Macros

Defines

#define __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).

Define Documentation

#define __HAL_RCC_HSE_CONFIG ( __STATE__ )
Value:
do{                                                     \
                      if ((__STATE__) == RCC_HSE_ON)                        \
                      {                                                     \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
                      }                                                     \
                      else if ((__STATE__) == RCC_HSE_OFF)                  \
                      {                                                     \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
                      }                                                     \
                      else if ((__STATE__) == RCC_HSE_BYPASS)               \
                      {                                                     \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
                      }                                                     \
                      else                                                  \
                      {                                                     \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
                      }                                                     \
                    }while(0U)

Macro to configure the External High Speed oscillator (HSE).

Note:
Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. User should request a transition to HSE Off first and then HSE On or HSE Bypass.
After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).
The HSE is stopped by hardware when entering STOP and STANDBY modes.
This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.
Parameters:
__STATE__ specifies the new state of the HSE. This parameter can be one of the following values:
  • RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
  • RCC_HSE_ON turn ON the HSE oscillator
  • RCC_HSE_BYPASS HSE oscillator bypassed with external clock

Definition at line 769 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: LSE Configuration

Defines
LSE Configuration
RCC Exported Macros

Defines

#define __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).

Define Documentation

#define __HAL_RCC_LSE_CONFIG ( __STATE__ )
Value:
do{                                                     \
                      if ((__STATE__) == RCC_LSE_ON)                        \
                      {                                                     \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
                      }                                                     \
                      else if ((__STATE__) == RCC_LSE_OFF)                  \
                      {                                                     \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
                      }                                                     \
                      else if ((__STATE__) == RCC_LSE_BYPASS)               \
                      {                                                     \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                  \
                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
                      }                                                     \
                      else                                                  \
                      {                                                     \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
                      }                                                     \
                    }while(0U)

Macro to configure the External Low Speed oscillator (LSE).

Note:
Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
__STATE__ specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON turn ON the LSE oscillator.
  • RCC_LSE_BYPASS LSE oscillator bypassed with external clock.

Definition at line 817 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PLL Configuration

Defines
PLL Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Macro to enable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
Macro to disable the main PLL.
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
Macro to configure the main PLL clock source and multiplication factors.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Get oscillator clock selected as PLL input clock.

Define Documentation

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))

Get oscillator clock selected as PLL input clock.

Return values:
The clock source used for PLL entry. The returned value can be one of the following:
  • RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock

Definition at line 900 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_CONFIG | ( | __RCC_PLLSOURCE__,
 |  | __PLLMUL__
 | ) | MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))

Macro to configure the main PLL clock source and multiplication factors.

Note:
This function must be used only when the main PLL is disabled.
Parameters:
__RCC_PLLSOURCE__ specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
  • RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
__PLLMUL__ specifies the multiplication factor for PLL VCO output clock This parameter can be one of the following values:
  • RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
  • RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
  • RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
  • RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
  • RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
  • RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
  • RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
  • RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
  • RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
  • RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
  • RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
  • RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
  • RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9

Definition at line 891 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_DISABLE ( ) (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)

Macro to disable the main PLL.

Note:
The main PLL can not be disabled if it is used as system clock source

Definition at line 859 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

#define __HAL_RCC_PLL_ENABLE ( ) (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)

Macro to enable the main PLL.

Note:
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL is disabled by hardware when entering STOP and STANDBY modes.

Definition at line 854 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_OscConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Get Clock source

Defines
Get Clock source
RCC Exported Macros

Defines

#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Macro to get the clock source used as system clock.

Define Documentation

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))

Macro to get the clock source used as system clock.

Return values:
The clock source used as system clock. The returned value can be one of the following:
  • RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
  • RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock

Definition at line 928 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), and HAL_RCC_OscConfig().

#define __HAL_RCC_SYSCLK_CONFIG ( __SYSCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters:
__SYSCLKSOURCE__ specifies the system clock source. This parameter can be one of the following values:
  • RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
  • RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.

Definition at line 918 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC Extended MCOx Clock Config

Defines
RCC Extended MCOx Clock Config
RCC Exported Macros

Defines

#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
Macro to configure the MCO clock.

Define Documentation

#define __HAL_RCC_MCO1_CONFIG | ( | __MCOCLKSOURCE__,
 |  | __MCODIV__
 | ) | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))

Macro to configure the MCO clock.

Parameters:
__MCOCLKSOURCE__ specifies the MCO clock source. This parameter can be one of the following values:
  • RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
  • RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
  • RCC_MCO1SOURCE_HSI HSI selected as MCO clock
  • RCC_MCO1SOURCE_HSE HSE selected as MCO clock
  • RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
__MCODIV__ specifies the MCO clock prescaler. This parameter can be one of the following values:
  • RCC_MCODIV_1 No division applied on MCO clock source

Definition at line 970 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_MCOConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC RTC Clock Configuration

Defines
RCC RTC Clock Configuration
RCC Exported Macros

Defines

#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Macro to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Macro to get the RTC clock source.
#define | __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Macro to enable the the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
Macro to disable the the RTC clock.
#define | __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Macro to force the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Macros to release the Backup domain reset.

Define Documentation

#define __HAL_RCC_BACKUPRESET_FORCE ( ) (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)

Macro to force the Backup domain reset.

Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_BDCR register.

Definition at line 1029 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_BACKUPRESET_RELEASE ( ) (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)

Macros to release the Backup domain reset.

Definition at line 1033 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_RTC_SOURCE ( ) (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))

Macro to get the RTC clock source.

Return values:
The clock source can be one of the following values:
  • RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
  • RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock

Definition at line 1013 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig().

#define __HAL_RCC_RTC_CONFIG ( __RTC_CLKSOURCE__ ) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))

Macro to configure the RTC clock (RTCCLK).

Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by a Power On Reset (POR).
Parameters:
__RTC_CLKSOURCE__ specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
  • RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
  • RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
  • RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).

Definition at line 1004 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_RTC_DISABLE ( ) (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)

Macro to disable the the RTC clock.

Note:
These macros must be used only after the RTC clock source was selected.

Definition at line 1023 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_RTC_ENABLE ( ) (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)

Macro to enable the the RTC clock.

Note:
These macros must be used only after the RTC clock source was selected.

Definition at line 1018 of file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Flags Interrupts Management

Defines
Flags Interrupts Management
RCC Exported Macros

macros to manage the specified RCC Flags and interrupts. More...

Defines

#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Clear the RCC's interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check RCC flag is set or not.

Detailed Description

macros to manage the specified RCC Flags and interrupts.

Define Documentation

#define __HAL_RCC_CLEAR_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))

Clear the RCC's interrupt pending bits.

Parameters:
__INTERRUPT__ specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt.
  • RCC_IT_LSERDY LSE ready interrupt.
  • RCC_IT_HSIRDY HSI ready interrupt.
  • RCC_IT_HSERDY HSE ready interrupt.
  • RCC_IT_PLLRDY Main PLL ready interrupt.
  • RCC_IT_CSS Clock Security System interrupt

Definition at line 1097 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

#define __HAL_RCC_CLEAR_RESET_FLAGS ( ) (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)

Set RMVF bit to clear the reset flags.

The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST

Definition at line 1123 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_DISABLE_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))

Disable RCC interrupt.

Parameters:
__INTERRUPT__ specifies the RCC interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY main PLL ready interrupt

Definition at line 1078 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_ENABLE_IT ( __INTERRUPT__ ) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))

Enable RCC interrupt.

Parameters:
__INTERRUPT__ specifies the RCC interrupt sources to be enabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt
  • RCC_IT_LSERDY LSE ready interrupt
  • RCC_IT_HSIRDY HSI ready interrupt
  • RCC_IT_HSERDY HSE ready interrupt
  • RCC_IT_PLLRDY main PLL ready interrupt

Definition at line 1060 of file stm32f1xx_hal_rcc.h.

#define __HAL_RCC_GET_FLAG ( __FLAG__ )
Value:
(((((__FLAG__) >> 5U) == CR_REG_INDEX)?   RCC->CR   : \
                                      ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
                                                                              RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))

Check RCC flag is set or not.

Parameters:
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY HSI oscillator clock ready.
  • RCC_FLAG_HSERDY HSE oscillator clock ready.
  • RCC_FLAG_PLLRDY Main PLL clock ready.
  • RCC_FLAG_LSERDY LSE oscillator clock ready.
  • RCC_FLAG_LSIRDY LSI oscillator clock ready.
  • RCC_FLAG_PINRST Pin reset.
  • RCC_FLAG_PORRST POR/PDR reset.
  • RCC_FLAG_SFTRST Software reset.
  • RCC_FLAG_IWDGRST Independent Watchdog reset.
  • RCC_FLAG_WWDGRST Window Watchdog reset.
  • RCC_FLAG_LPWRRST Low Power reset.
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1148 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_ClockConfig(), HAL_RCC_OscConfig(), and HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_IT ( __INTERRUPT__ ) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))

Check the RCC's interrupt has occurred or not.

Parameters:
__INTERRUPT__ specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSIRDY LSI ready interrupt.
  • RCC_IT_LSERDY LSE ready interrupt.
  • RCC_IT_HSIRDY HSI ready interrupt.
  • RCC_IT_HSERDY HSE ready interrupt.
  • RCC_IT_PLLRDY Main PLL ready interrupt.
  • RCC_IT_CSS Clock Security System interrupt
Return values:
The new state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 1117 of file stm32f1xx_hal_rcc.h.

Referenced by HAL_RCC_NMI_IRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCCEx Private Constants

Defines
RCCEx Private Constants
RCCEx

Defines

#define CR_REG_INDEX ((uint8_t)1)

Define Documentation

#define CR_REG_INDEX ((uint8_t)1)

Definition at line 76 of file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCCEx Private Macros

Defines
RCCEx Private Macros
RCCEx

Defines

#define | IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
#define | IS_RCC_PLL_MUL(__MUL__)
#define | IS_RCC_MCO1SOURCE(__SOURCE__)
#define | IS_RCC_ADCPLLCLK_DIV(__ADCCLK__)
#define | IS_RCC_PERIPHCLOCK(__SELECTION__)
#define | IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))

Define Documentation

#define IS_RCC_ADCPLLCLK_DIV ( __ADCCLK__ )
Value:
(((__ADCCLK__) == RCC_ADCPCLK2_DIV2)  || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4)   || \
                                          ((__ADCCLK__) == RCC_ADCPCLK2_DIV6)  || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))

Definition at line 134 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_HSE_PREDIV ( __DIV__ ) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))

Definition at line 103 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_MCO1SOURCE ( __SOURCE__ )
Value:
(((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK)  || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
                                    || ((__SOURCE__) == RCC_MCO1SOURCE_HSE)     || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
                                    || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))

Definition at line 128 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_MCOConfig().

#define IS_RCC_PERIPHCLOCK ( __SELECTION__ )
Value:
((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)  || \
                (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))

Definition at line 192 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define IS_RCC_PLL_MUL ( __MUL__ )
Value:
(((__MUL__) == RCC_PLL_MUL2)  || ((__MUL__) == RCC_PLL_MUL3)  || \
                                 ((__MUL__) == RCC_PLL_MUL4)  || ((__MUL__) == RCC_PLL_MUL5)  || \
                                 ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL7)  || \
                                 ((__MUL__) == RCC_PLL_MUL8)  || ((__MUL__) == RCC_PLL_MUL9)  || \
                                 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
                                 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
                                 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
                                 ((__MUL__) == RCC_PLL_MUL16))

Definition at line 119 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_OscConfig().

#define IS_RCC_USBPLLCLK_DIV ( __USBCLK__ ) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))

Definition at line 208 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RCCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the PeriphClkInit according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Returns the peripheral clock frequency.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
                ##### Extended Peripheral Control functions  #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the RCC Clocks
    frequencies.
    [..]
    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
        select the RTC clock source; in this case the Backup domain will be reset in
        order to modify the RTC Clock source, as consequence RTC registers (including
        the backup registers) are set to their reset values.

Function Documentation

void HAL_RCCEx_GetPeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Get the PeriphClkInit according to the internal RCC configuration registers.

Parameters:
PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
Return values:
None

Definition at line 312 of file stm32f1xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC_SOURCE, __HAL_RCC_GET_RTC_SOURCE, __HAL_RCC_GET_USB_SOURCE, RCC_PeriphCLKInitTypeDef::AdcClockSelection, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USB, RCC_PeriphCLKInitTypeDef::RTCClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

uint32_t HAL_RCCEx_GetPeriphCLKFreq ( uint32_t PeriphClk )

Returns the peripheral clock frequency.

Note:
Returns 0 if peripheral clock is unknown
Parameters:
PeriphClk Peripheral clock identifier This parameter can be one of the following values:
  • RCC_PERIPHCLK_RTC RTC peripheral clock
  • RCC_PERIPHCLK_ADC ADC peripheral clock
Return values:
Frequency in Hz (0: means that no available frequency for the peripheral)

Definition at line 405 of file stm32f1xx_hal_rcc_ex.c.

References __HAL_RCC_GET_ADC_SOURCE, __HAL_RCC_GET_USB_SOURCE, assert_param, HAL_RCC_GetPCLK2Freq(), HAL_RCC_GetSysClockFreq(), HSE_VALUE, HSI_VALUE, IS_RCC_PERIPHCLOCK, LSE_VALUE, LSI_VALUE, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USB, RCC_PLLSOURCE_HSI_DIV2, RCC_RTCCLKSOURCE_HSE_DIV128, RCC_RTCCLKSOURCE_LSE, RCC_RTCCLKSOURCE_LSI, and RCC_USBCLKSOURCE_PLL.

Referenced by HAL_ADC_PollForConversion(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), and HAL_RTC_Init().

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig ( RCC_PeriphCLKInitTypeDef * PeriphClkInit )

Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.

Parameters:
PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that contains the configuration information for the Extended Peripherals clocks(RTC clock).
Note:
Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) are set to their reset values.
In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to manually disable it.
Return values:
HAL status

Definition at line 118 of file stm32f1xx_hal_rcc_ex.c.

References __HAL_RCC_ADC_CONFIG, __HAL_RCC_BACKUPRESET_FORCE, __HAL_RCC_BACKUPRESET_RELEASE, __HAL_RCC_GET_FLAG, __HAL_RCC_PWR_CLK_DISABLE, __HAL_RCC_PWR_CLK_ENABLE, __HAL_RCC_PWR_IS_CLK_DISABLED, __HAL_RCC_RTC_CONFIG, __HAL_RCC_USB_CONFIG, RCC_PeriphCLKInitTypeDef::AdcClockSelection, assert_param, HAL_GetTick(), IS_RCC_ADCPLLCLK_DIV, IS_RCC_PERIPHCLOCK, IS_RCC_RTCCLKSOURCE, IS_RCC_USBPLLCLK_DIV, RCC_PeriphCLKInitTypeDef::PeriphClockSelection, RCC_DBP_TIMEOUT_VALUE, RCC_FLAG_LSERDY, RCC_LSE_TIMEOUT_VALUE, RCC_PERIPHCLK_ADC, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USB, RCC_PeriphCLKInitTypeDef::RTCClockSelection, and RCC_PeriphCLKInitTypeDef::UsbClockSelection.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC_OscInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_OscInitTypeDef Struct Reference
RCCEx Exported Types

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...

#include <stm32f1xx_hal_rcc_ex.h>

Data Fields

uint32_t | OscillatorType
uint32_t | HSEState
uint32_t | HSEPredivValue
uint32_t | LSEState
uint32_t | HSIState
uint32_t | HSICalibrationValue
uint32_t | LSIState
RCC_PLLInitTypeDef PLL

Detailed Description

RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.

Definition at line 246 of file stm32f1xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_OscInitTypeDef::HSEPredivValue

The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) This parameter can be a value of HSE Prediv1 Factor

Definition at line 259 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSEState

The new state of the HSE. This parameter can be a value of HSE Config

Definition at line 256 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSICalibrationValue

The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F

Definition at line 268 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::HSIState

The new state of the HSI. This parameter can be a value of HSI Config

Definition at line 265 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSEState

The new state of the LSE. This parameter can be a value of LSE Config

Definition at line 262 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::LSIState

The new state of the LSI. This parameter can be a value of LSI Config

Definition at line 271 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

uint32_t RCC_OscInitTypeDef::OscillatorType

The oscillators to be configured. This parameter can be a value of Oscillator Type

Definition at line 248 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

RCC_PLLInitTypeDef RCC_OscInitTypeDef::PLL

PLL structure parameters

Definition at line 274 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig(), and HAL_RCC_OscConfig().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_rcc_ex.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC_PeriphCLKInitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RCC_PeriphCLKInitTypeDef Struct Reference
RCCEx Exported Types

RCC extended clocks structure definition. More...

#include <stm32f1xx_hal_rcc_ex.h>

Data Fields

uint32_t | PeriphClockSelection
uint32_t | RTCClockSelection
uint32_t | AdcClockSelection
uint32_t | UsbClockSelection

Detailed Description

RCC extended clocks structure definition.

Definition at line 301 of file stm32f1xx_hal_rcc_ex.h.

Field Documentation

uint32_t RCC_PeriphCLKInitTypeDef::AdcClockSelection

ADC clock source This parameter can be a value of ADC Prescaler

Definition at line 309 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::PeriphClockSelection

The Extended Clock to be configured. This parameter can be a value of Periph Clock Selection

Definition at line 303 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::RTCClockSelection

specifies the RTC clock source. This parameter can be a value of RTC Clock Source

Definition at line 306 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

uint32_t RCC_PeriphCLKInitTypeDef::UsbClockSelection

USB clock source This parameter can be a value of USB Prescaler

Definition at line 330 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_PeriphCLKConfig().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_rcc_ex.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Periph Clock Selection

Defines
Periph Clock Selection
RCCEx Exported Constants

Defines

#define | RCC_PERIPHCLK_RTC 0x00000001U
#define | RCC_PERIPHCLK_ADC 0x00000002U
#define | RCC_PERIPHCLK_USB 0x00000010U

Define Documentation

#define RCC_PERIPHCLK_ADC 0x00000002U

Definition at line 350 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_ADC_PollForConversion(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedPollForConversion(), HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

#define RCC_PERIPHCLK_RTC 0x00000001U

Definition at line 349 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), and HAL_RTC_Init().

#define RCC_PERIPHCLK_USB 0x00000010U

Definition at line 359 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), HAL_RCCEx_GetPeriphCLKFreq(), and HAL_RCCEx_PeriphCLKConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Prescaler

Defines
ADC Prescaler
RCCEx Exported Constants

Defines

#define | RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
#define | RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
#define | RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
#define | RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8

Define Documentation

#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2

Definition at line 369 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4

Definition at line 370 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6

Definition at line 371 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8

Definition at line 372 of file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USB Prescaler

Defines
USB Prescaler
RCCEx Exported Constants

Defines

#define | RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
#define | RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U

Define Documentation

#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE

Definition at line 412 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U

Definition at line 413 of file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: HSE Prediv1 Factor

Defines
HSE Prediv1 Factor
RCCEx Exported Constants

Defines

#define | RCC_HSE_PREDIV_DIV1 0x00000000U
#define | RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE

Define Documentation

#define RCC_HSE_PREDIV_DIV1 0x00000000U

Definition at line 469 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE

Definition at line 489 of file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PLL Multiplication Factor

Defines
PLL Multiplication Factor
RCCEx Exported Constants

Defines

#define | RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
#define | RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
#define | RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
#define | RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
#define | RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
#define | RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
#define | RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
#define | RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
#define | RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
#define | RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
#define | RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
#define | RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
#define | RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
#define | RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
#define | RCC_PLL_MUL16 RCC_CFGR_PLLMULL16

Define Documentation

#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10

Definition at line 571 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11

Definition at line 572 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12

Definition at line 573 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13

Definition at line 574 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14

Definition at line 575 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15

Definition at line 576 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16

Definition at line 577 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2

Definition at line 559 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3

Definition at line 560 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4

Definition at line 562 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5

Definition at line 563 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6

Definition at line 564 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7

Definition at line 565 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8

Definition at line 566 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9

Definition at line 567 of file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: MCO1 Clock Source

Defines
MCO1 Clock Source
RCCEx Exported Constants

Defines

#define | RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
#define | RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
#define | RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
#define | RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
#define | RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)

Define Documentation

#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)

Definition at line 590 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)

Definition at line 589 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)

Definition at line 587 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)

Definition at line 591 of file stm32f1xx_hal_rcc_ex.h.

#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)

Definition at line 588 of file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Clock Enable Disable

Peripheral Clock Enable Disable
RCCEx Exported Macros

Enable or disable the AHB1 peripheral clock. More...

Enable or disable the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: AHB1 Peripheral Clock Enable Disable Status

AHB1 Peripheral Clock Enable Disable Status
RCCEx Exported Macros

Get the enable or disable status of the AHB1 peripheral clock. More...

Get the enable or disable status of the AHB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB1 Clock Enable Disable

Defines
APB1 Clock Enable Disable
RCCEx Exported Macros

Enable or disable the Low Speed APB (APB1) peripheral clock. More...

Defines

#define | __HAL_RCC_CAN1_CLK_ENABLE()
#define | __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define | __HAL_RCC_USB_CLK_ENABLE()
#define | __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))

Detailed Description

Enable or disable the Low Speed APB (APB1) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CAN1_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))

Definition at line 807 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 799 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

Definition at line 849 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 838 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

Definition at line 847 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 822 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))

Definition at line 846 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 814 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))

Definition at line 848 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 830 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_CLK_DISABLE ( ) (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))

Definition at line 862 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 854 of file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB1 Peripheral Clock Enable Disable Status

Defines
APB1 Peripheral Clock Enable Disable Status
RCCEx Exported Macros

Get the enable or disable status of the APB1 peripheral clock. More...

Defines

#define | __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#define | __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
#define | __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)

Detailed Description

Get the enable or disable status of the APB1 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_CAN1_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)

Definition at line 1094 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)

Definition at line 1093 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)

Definition at line 1107 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)

Definition at line 1106 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)

Definition at line 1103 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)

Definition at line 1102 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)

Definition at line 1101 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)

Definition at line 1100 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)

Definition at line 1105 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)

Definition at line 1104 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_IS_CLK_DISABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)

Definition at line 1112 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_IS_CLK_ENABLED ( ) ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)

Definition at line 1111 of file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB2 Clock Enable Disable

Defines
APB2 Clock Enable Disable
RCCEx Exported Macros

Enable or disable the High Speed APB (APB2) peripheral clock. More...

Defines

#define | __HAL_RCC_ADC2_CLK_ENABLE()
#define | __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))

Detailed Description

Enable or disable the High Speed APB (APB2) peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC2_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))

Definition at line 1193 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1185 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_CLK_DISABLE ( ) (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))

Definition at line 1238 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )
Value:
do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
                                        UNUSED(tmpreg); \
                                      } while(0U)

Definition at line 1230 of file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB2 Peripheral Clock Enable Disable Status

Defines
APB2 Peripheral Clock Enable Disable Status
RCCEx Exported Macros

Get the enable or disable status of the APB2 peripheral clock. More...

Defines

#define | __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
#define | __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)

Detailed Description

Get the enable or disable status of the APB2 peripheral clock.

Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Define Documentation

#define __HAL_RCC_ADC2_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)

Definition at line 1351 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)

Definition at line 1350 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_DISABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)

Definition at line 1366 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)

Definition at line 1365 of file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: APB1 Force Release Reset

Defines
APB1 Force Release Reset
RCCEx Exported Macros

Force or release APB1 peripheral reset. More...

Defines

#define | __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
#define | __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
#define | __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
#define | __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))

Detailed Description

Force or release APB1 peripheral reset.

Define Documentation

#define __HAL_RCC_CAN1_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))

Definition at line 1429 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_CAN1_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))

Definition at line 1431 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))

Definition at line 1441 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_I2C2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))

Definition at line 1446 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))

Definition at line 1439 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_SPI2_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))

Definition at line 1444 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))

Definition at line 1438 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_TIM4_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))

Definition at line 1443 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))

Definition at line 1440 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USART3_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))

Definition at line 1445 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_FORCE_RESET ( ) (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))

Definition at line 1451 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_USB_RELEASE_RESET ( ) (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))

Definition at line 1452 of file stm32f1xx_hal_rcc_ex.h.

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STM32F103xB HAL User Manual: APB2 Force Release Reset

Defines
APB2 Force Release Reset
RCCEx Exported Macros

Force or release APB2 peripheral reset. More...

Defines

#define | __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
#define | __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
#define | __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
#define | __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))

Detailed Description

Force or release APB2 peripheral reset.

Define Documentation

#define __HAL_RCC_ADC2_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))

Definition at line 1532 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_ADC2_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))

Definition at line 1534 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_FORCE_RESET ( ) (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))

Definition at line 1551 of file stm32f1xx_hal_rcc_ex.h.

#define __HAL_RCC_GPIOE_RELEASE_RESET ( ) (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))

Definition at line 1553 of file stm32f1xx_hal_rcc_ex.h.

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STM32F103xB HAL User Manual: HSE Configuration

Defines
HSE Configuration
RCCEx Exported Macros

Defines

#define | __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
#define | __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
Macro to get prediv1 factor for PLL.

Define Documentation

#define __HAL_RCC_HSE_GET_PREDIV ( ) READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)

Macro to get prediv1 factor for PLL.

Definition at line 1635 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_GetOscConfig().

#define __HAL_RCC_HSE_PREDIV_CONFIG ( __HSE_PREDIV_VALUE__ ) MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))

Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.

Note:
Predivision factor can not be changed if PLL is used as system clock In this case, you have to select another source of the system clock, disable the PLL and then change the HSE predivision factor.
Parameters:
__HSE_PREDIV_VALUE__ specifies the division value applied to HSE. This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.

Definition at line 1619 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCC_OscConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Configuration

Defines
Peripheral Configuration
RCCEx Exported Macros

Macros to configure clock source of different peripherals. More...

Defines

#define | __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
Macro to configure the USB clock.
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
Macro to get the USB clock (USBCLK).
#define | __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
Macro to configure the ADCx clock (x=1 to 3 depending on devices).
#define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).

Detailed Description

Macros to configure clock source of different peripherals.

Define Documentation

#define __HAL_RCC_ADC_CONFIG ( __ADCCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))

Macro to configure the ADCx clock (x=1 to 3 depending on devices).

Parameters:
__ADCCLKSOURCE__ specifies the ADC clock source. This parameter can be one of the following values:
  • RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
  • RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
  • RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
  • RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock

Definition at line 1739 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

#define __HAL_RCC_GET_ADC_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))

Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).

Return values:
The clock source can be one of the following values:
  • RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
  • RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
  • RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
  • RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock

Definition at line 1749 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_GET_USB_SOURCE ( ) ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))

Macro to get the USB clock (USBCLK).

Return values:
The clock source can be one of the following values:
  • RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
  • RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock

Definition at line 1707 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_GetPeriphCLKConfig(), and HAL_RCCEx_GetPeriphCLKFreq().

#define __HAL_RCC_USB_CONFIG ( __USBCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))

Macro to configure the USB clock.

Parameters:
__USBCLKSOURCE__ specifies the USB clock source. This parameter can be one of the following values:
  • RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
  • RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock

Definition at line 1699 of file stm32f1xx_hal_rcc_ex.h.

Referenced by HAL_RCCEx_PeriphCLKConfig().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Default Timeout Value

Defines
Default Timeout Value
RTC Private Constants

Defines

#define RTC_TIMEOUT_VALUE 1000U

Define Documentation

#define RTC_TIMEOUT_VALUE 1000U

Definition at line 86 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_WaitForSynchro(), RTC_EnterInitMode(), and RTC_ExitInitMode().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC EXTI Line event

Defines
RTC EXTI Line event
RTC Private Constants

Defines

#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17)

Define Documentation

#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17)

External interrupt line 17 Connected to the RTC Alarm event

Definition at line 94 of file stm32f1xx_hal_rtc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC Private Constants

Modules | Defines
RTC Private Constants
RTC

Modules

Default Timeout Value
RTC EXTI Line event

Defines

#define | RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF
#define | RTC_ALARM_RESETVALUE 0xFFFFFFFFU

Define Documentation

#define RTC_ALARM_RESETVALUE 0xFFFFFFFFU

Definition at line 174 of file stm32f1xx_hal_rtc.c.

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

#define RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF

Definition at line 173 of file stm32f1xx_hal_rtc.c.

Referenced by HAL_RTC_DeactivateAlarm().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC Private Macros

Defines
RTC Private Macros
RTC

Defines

#define | IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define | IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
#define | IS_RTC_CALIB_OUTPUT(__OUTPUT__)

Define Documentation

#define IS_RTC_ALARM ( ALARM ) ((ALARM) == RTC_ALARM_A)

Definition at line 69 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

#define IS_RTC_ASYNCH_PREDIV ( PREDIV ) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND))

Definition at line 61 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_CALIB_OUTPUT ( __OUTPUT__ )
Value:
(((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \
                                         ((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \
                                         ((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \
                                         ((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND))

Definition at line 70 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define IS_RTC_DATE ( DATE ) (((DATE) >= 1U) && ((DATE) <= 31U))

Definition at line 68 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_FORMAT ( FORMAT ) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))

Definition at line 65 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

#define IS_RTC_HOUR24 ( HOUR ) ((HOUR) <= 23U)

Definition at line 62 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MINUTES ( MINUTES ) ((MINUTES) <= 59U)

Definition at line 63 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_MONTH ( MONTH ) (((MONTH) >= 1U) && ((MONTH) <= 12U))

Definition at line 67 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

#define IS_RTC_SECONDS ( SECONDS ) ((SECONDS) <= 59U)

Definition at line 64 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

#define IS_RTC_YEAR ( YEAR ) ((YEAR) <= 99U)

Definition at line 66 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_SetDate().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC Private Functions

Functions
RTC Private Functions
RTC

Functions

static uint32_t | RTC_ReadTimeCounter (RTC_HandleTypeDef *hrtc)
Read the time counter available in RTC_CNT registers.
static HAL_StatusTypeDef | RTC_WriteTimeCounter (RTC_HandleTypeDef *hrtc, uint32_t TimeCounter)
Write the time counter in RTC_CNT registers.
static uint32_t | RTC_ReadAlarmCounter (RTC_HandleTypeDef *hrtc)
Read the time counter available in RTC_ALR registers.
static HAL_StatusTypeDef | RTC_WriteAlarmCounter (RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter)
Write the time counter in RTC_ALR registers.
static HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enters the RTC Initialization mode.
static HAL_StatusTypeDef | RTC_ExitInitMode (RTC_HandleTypeDef *hrtc)
Exit the RTC Initialization mode.
static uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
static uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Converts from 2 digit BCD to Binary.
static uint8_t | RTC_IsLeapYear (uint16_t nYear)
Check whether the passed year is Leap or not.
static void | RTC_DateUpdate (RTC_HandleTypeDef *hrtc, uint32_t DayElapsed)
Updates date when time is 23:59:59.
static uint8_t | RTC_WeekDayNum (uint32_t nYear, uint8_t nMonth, uint8_t nDay)
Determines the week number, the day number and the week day number.

Function Documentation

static uint8_t RTC_Bcd2ToByte ( uint8_t Value ) [static]

Converts from 2 digit BCD to Binary.

Parameters:
Value,: BCD value to be converted
Return values:
Converted word

Definition at line 1535 of file stm32f1xx_hal_rtc.c.

Referenced by HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

static uint8_t RTC_ByteToBcd2 ( uint8_t Value ) [static]

Converts a 2 digit decimal to BCD format.

Parameters:
Value,: Byte to be converted
Return values:
Converted byte

Definition at line 1517 of file stm32f1xx_hal_rtc.c.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), and HAL_RTC_GetTime().

static void RTC_DateUpdate | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | DayElapsed
 | ) |  | [static]

Updates date when time is 23:59:59.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
DayElapsed,: Number of days elapsed from last date update
Return values:
None

Definition at line 1549 of file stm32f1xx_hal_rtc.c.

References RTC_DateTypeDef::Date, RTC_HandleTypeDef::DateToUpdate, RTC_DateTypeDef::Month, RTC_IsLeapYear(), RTC_WeekDayNum(), RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

Referenced by HAL_RTC_GetTime().

static HAL_StatusTypeDef RTC_EnterInitMode ( RTC_HandleTypeDef * hrtc ) [static]

Enters the RTC Initialization mode.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1465 of file stm32f1xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_DISABLE, HAL_GetTick(), RTC_HandleTypeDef::Instance, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), RTC_WriteAlarmCounter(), and RTC_WriteTimeCounter().

static HAL_StatusTypeDef RTC_ExitInitMode ( RTC_HandleTypeDef * hrtc ) [static]

Exit the RTC Initialization mode.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1492 of file stm32f1xx_hal_rtc.c.

References __HAL_RTC_WRITEPROTECTION_ENABLE, HAL_GetTick(), RTC_HandleTypeDef::Instance, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), RTC_WriteAlarmCounter(), and RTC_WriteTimeCounter().

static uint8_t RTC_IsLeapYear ( uint16_t nYear ) [static]

Check whether the passed year is Leap or not.

Parameters:
nYear year to check
Return values:
1,: leap year 0: not leap year

Definition at line 1644 of file stm32f1xx_hal_rtc.c.

Referenced by RTC_DateUpdate().

static uint32_t RTC_ReadAlarmCounter ( RTC_HandleTypeDef * hrtc ) [static]

Read the time counter available in RTC_ALR registers.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
Time counter

Definition at line 1416 of file stm32f1xx_hal_rtc.c.

References RTC_HandleTypeDef::Instance.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

static uint32_t RTC_ReadTimeCounter ( RTC_HandleTypeDef * hrtc ) [static]

Read the time counter available in RTC_CNT registers.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
Time counter

Definition at line 1354 of file stm32f1xx_hal_rtc.c.

References RTC_HandleTypeDef::Instance.

Referenced by HAL_RTC_GetTime(), and HAL_RTC_SetDate().

static uint8_t RTC_WeekDayNum | ( | uint32_t | nYear,
 |  | uint8_t | nMonth,
 |  | uint8_t | nDay
 | ) |  | [static]

Determines the week number, the day number and the week day number.

Parameters:
nYear | year to check
nMonth | Month to check
nDay | Day to check
Note:
Day is calculated with hypothesis that year > 2000
Return values:
Value which can take one of the following parameters:
  • RTC_WEEKDAY_MONDAY
  • RTC_WEEKDAY_TUESDAY
  • RTC_WEEKDAY_WEDNESDAY
  • RTC_WEEKDAY_THURSDAY
  • RTC_WEEKDAY_FRIDAY
  • RTC_WEEKDAY_SATURDAY
  • RTC_WEEKDAY_SUNDAY

Definition at line 1681 of file stm32f1xx_hal_rtc.c.

Referenced by HAL_RTC_SetDate(), and RTC_DateUpdate().

static HAL_StatusTypeDef RTC_WriteAlarmCounter | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | AlarmCounter
 | ) |  | [static]

Write the time counter in RTC_ALR registers.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
AlarmCounter,: Counter to write in RTC_ALR registers
Return values:
HAL status

Definition at line 1433 of file stm32f1xx_hal_rtc.c.

References RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_ExitInitMode().

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

static HAL_StatusTypeDef RTC_WriteTimeCounter | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | TimeCounter
 | ) |  | [static]

Write the time counter in RTC_CNT registers.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
TimeCounter,: Counter to write in RTC_CNT registers
Return values:
HAL status

Definition at line 1384 of file stm32f1xx_hal_rtc.c.

References RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), and RTC_ExitInitMode().

Referenced by HAL_RTC_GetTime(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
RTC Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initializes the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initializes the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
   [..] This section provides functions allowing to initialize and configure the
         RTC Prescaler (Asynchronous), disable RTC registers Write protection,
         enter and exit the RTC initialization mode,
         RTC registers synchronization check and reference clock detection enable.
         (#) The RTC Prescaler should be programmed to generate the RTC 1Hz time base.
         (#) All RTC registers are Write protected. Writing to the RTC registers
             is enabled by setting the CNF bit in the RTC_CRL register.
         (#) To read the calendar after wakeup from low power modes (Standby or Stop)
             the software must first wait for the RSF bit (Register Synchronized Flag)
             in the RTC_CRL register to be set by hardware.
             The HAL_RTC_WaitForSynchro() function implements the above software
             sequence (RSF clear and RSF check).

Function Documentation

HAL_StatusTypeDef HAL_RTC_DeInit ( RTC_HandleTypeDef * hrtc )

DeInitializes the RTC peripheral.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Note:
This function does not reset the RTC Backup Data registers.
Return values:
HAL status

Definition at line 357 of file stm32f1xx_hal_rtc.c.

References assert_param, HAL_RTC_MspDeInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_RESET, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Instance, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_FLAG_RSF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_Init ( RTC_HandleTypeDef * hrtc )

Initializes the RTC peripheral.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 244 of file stm32f1xx_hal_rtc.c.

References assert_param, RTC_InitTypeDef::AsynchPrediv, RTC_DateTypeDef::Date, RTC_HandleTypeDef::DateToUpdate, HAL_RCCEx_GetPeriphCLKFreq(), HAL_RTC_MspInit(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTC_STATE_RESET, HAL_RTC_WaitForSynchro(), RTC_HandleTypeDef::Init, RTC_HandleTypeDef::Instance, IS_RTC_ASYNCH_PREDIV, IS_RTC_CALIB_OUTPUT, RTC_HandleTypeDef::Lock, RTC_DateTypeDef::Month, RTC_InitTypeDef::OutPut, RCC_PERIPHCLK_RTC, RTC_AUTO_1_SECOND, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_FLAG_ALRAF, RTC_FLAG_OW, RTC_FLAG_SEC, RTC_MONTH_JANUARY, RTC_OUTPUTSOURCE_NONE, RTC_HandleTypeDef::State, and RTC_DateTypeDef::Year.

void HAL_RTC_MspDeInit ( RTC_HandleTypeDef * hrtc )

DeInitializes the RTC MSP.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 442 of file stm32f1xx_hal_rtc.c.

Referenced by HAL_RTC_DeInit().

void HAL_RTC_MspInit ( RTC_HandleTypeDef * hrtc )

Initializes the RTC MSP.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 427 of file stm32f1xx_hal_rtc.c.

Referenced by HAL_RTC_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Time and Date functions

Functions
Time and Date functions
RTC Exported Functions

RTC Time and Date functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Sets RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Gets RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Sets RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Gets RTC current date.

Detailed Description

RTC Time and Date functions.

 ===============================================================================
                 ##### RTC Time and Date functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Time and Date features

Function Documentation

HAL_StatusTypeDef HAL_RTC_GetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Gets RTC current date.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sDate,: Pointer to Date structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 804 of file stm32f1xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, RTC_HandleTypeDef::DateToUpdate, HAL_RTC_GetTime(), IS_RTC_FORMAT, RTC_DateTypeDef::Month, RTC_ByteToBcd2(), RTC_FORMAT_BIN, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_GetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Gets RTC current time.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTime,: Pointer to Time structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 579 of file stm32f1xx_hal_rtc.c.

References __HAL_RTC_OVERFLOW_GET_FLAG, assert_param, RTC_TimeTypeDef::Hours, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ALARM_RESETVALUE, RTC_ByteToBcd2(), RTC_DateUpdate(), RTC_FLAG_OW, RTC_FORMAT_BIN, RTC_ReadAlarmCounter(), RTC_ReadTimeCounter(), RTC_WriteAlarmCounter(), RTC_WriteTimeCounter(), and RTC_TimeTypeDef::Seconds.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

HAL_StatusTypeDef HAL_RTC_SetDate | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_DateTypeDef * | sDate,
 |  | uint32_t | Format
 | ) |  |

Sets RTC current date.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sDate,: Pointer to date structure
Format,: specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 690 of file stm32f1xx_hal_rtc.c.

References assert_param, RTC_DateTypeDef::Date, RTC_HandleTypeDef::DateToUpdate, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, IS_RTC_DATE, IS_RTC_FORMAT, IS_RTC_MONTH, IS_RTC_YEAR, RTC_DateTypeDef::Month, RTC_ALARM_RESETVALUE, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_ReadAlarmCounter(), RTC_ReadTimeCounter(), RTC_WeekDayNum(), RTC_WriteAlarmCounter(), RTC_WriteTimeCounter(), RTC_HandleTypeDef::State, RTC_DateTypeDef::WeekDay, and RTC_DateTypeDef::Year.

HAL_StatusTypeDef HAL_RTC_SetTime | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TimeTypeDef * | sTime,
 |  | uint32_t | Format
 | ) |  |

Sets RTC current time.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTime,: Pointer to Time structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 480 of file stm32f1xx_hal_rtc.c.

References assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_TimeTypeDef::Hours, RTC_HandleTypeDef::Instance, IS_RTC_FORMAT, IS_RTC_HOUR24, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_ALARM_RESETVALUE, RTC_Bcd2ToByte(), RTC_FLAG_OW, RTC_FLAG_SEC, RTC_FORMAT_BIN, RTC_ReadAlarmCounter(), RTC_WriteAlarmCounter(), RTC_WriteTimeCounter(), RTC_TimeTypeDef::Seconds, and RTC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Alarm functions

Functions
Alarm functions
RTC Exported Functions

RTC Alarm functions. More...

Functions

HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Gets the RTC Alarm value and masks.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactive the specified RTC Alarm.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmA Polling request.

Detailed Description

RTC Alarm functions.

 ===============================================================================
                 ##### RTC Alarm functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Alarm feature

Function Documentation

void HAL_RTC_AlarmAEventCallback ( RTC_HandleTypeDef * hrtc )

Alarm A callback.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1203 of file stm32f1xx_hal_rtc.c.

Referenced by HAL_RTC_AlarmIRQHandler().

void HAL_RTC_AlarmIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles Alarm interrupt request.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 1175 of file stm32f1xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_EXTI_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, __HAL_RTC_ALARM_GET_IT_SOURCE, HAL_RTC_AlarmAEventCallback(), HAL_RTC_STATE_READY, RTC_FLAG_ALRAF, RTC_IT_ALRA, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_DeactivateAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Alarm
 | ) |  |

Deactive the specified RTC Alarm.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: AlarmA
Return values:
HAL status

Definition at line 1108 of file stm32f1xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_DISABLE_IT, __HAL_RTC_ALARM_EXTI_DISABLE_IT, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_HandleTypeDef::Instance, IS_RTC_ALARM, RTC_ALARM_RESETVALUE_REGISTER, RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_FLAG_ALRAF, RTC_IT_ALRA, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_GetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Alarm,
 |  | uint32_t | Format
 | ) |  |

Gets the RTC Alarm value and masks.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Date structure
Alarm,: Specifies the Alarm. This parameter can be one of the following values:
  • RTC_ALARM_A: Alarm
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 1066 of file stm32f1xx_hal_rtc.c.

References RTC_AlarmTypeDef::AlarmTime, assert_param, RTC_TimeTypeDef::Hours, IS_RTC_ALARM, IS_RTC_FORMAT, RTC_TimeTypeDef::Minutes, RTC_ByteToBcd2(), RTC_FORMAT_BIN, RTC_ReadAlarmCounter(), and RTC_TimeTypeDef::Seconds.

HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles AlarmA Polling request.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 1219 of file stm32f1xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_ALRAF, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Sets the specified RTC Alarm.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Return values:
HAL status

Definition at line 869 of file stm32f1xx_hal_rtc.c.

References RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_RTC_GetTime(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_TimeTypeDef::Hours, IS_RTC_ALARM, IS_RTC_FORMAT, IS_RTC_HOUR24, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FORMAT_BIN, RTC_WriteAlarmCounter(), RTC_TimeTypeDef::Seconds, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTC_SetAlarm_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_AlarmTypeDef * | sAlarm,
 |  | uint32_t | Format
 | ) |  |

Sets the specified RTC Alarm with Interrupt.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sAlarm,: Pointer to Alarm structure
Format,: Specifies the format of the entered parameters. This parameter can be one of the following values:
  • RTC_FORMAT_BIN: Binary data format
  • RTC_FORMAT_BCD: BCD data format
Note:
The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
Return values:
HAL status

Definition at line 961 of file stm32f1xx_hal_rtc.c.

References __HAL_RTC_ALARM_CLEAR_FLAG, __HAL_RTC_ALARM_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_IT, __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE, RTC_AlarmTypeDef::Alarm, RTC_AlarmTypeDef::AlarmTime, assert_param, HAL_RTC_GetTime(), HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, RTC_TimeTypeDef::Hours, IS_RTC_ALARM, IS_RTC_FORMAT, IS_RTC_HOUR24, IS_RTC_MINUTES, IS_RTC_SECONDS, RTC_TimeTypeDef::Minutes, RTC_Bcd2ToByte(), RTC_FLAG_ALRAF, RTC_FORMAT_BIN, RTC_IT_ALRA, RTC_WriteAlarmCounter(), RTC_TimeTypeDef::Seconds, and RTC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
RTC Exported Functions

Peripheral State functions. More...

Functions

HAL_RTCStateTypeDef HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Returns the RTC state.

Detailed Description

Peripheral State functions.

 ===============================================================================
                     ##### Peripheral State functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Get RTC state

Function Documentation

HAL_RTCStateTypeDef HAL_RTC_GetState ( RTC_HandleTypeDef * hrtc )

Returns the RTC state.

Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL state

Definition at line 1274 of file stm32f1xx_hal_rtc.c.

References RTC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
RTC Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) are synchronized with RTC APB clock.

Detailed Description

Peripheral Control functions.

 ===============================================================================
                     ##### Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Wait for RTC Time and Date Synchronization

Function Documentation

HAL_StatusTypeDef HAL_RTC_WaitForSynchro ( RTC_HandleTypeDef * hrtc )

Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) are synchronized with RTC APB clock.

Note:
This function must be called before any read operation after an APB reset or an APB clock stop.
Parameters:
hrtc pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 1307 of file stm32f1xx_hal_rtc.c.

References HAL_GetTick(), RTC_HandleTypeDef::Instance, RTC_FLAG_RSF, and RTC_TIMEOUT_VALUE.

Referenced by HAL_RTC_DeInit(), and HAL_RTC_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC Exported Types

Data Structures | Enumerations
RTC Exported Types
RTC

Data Structures

struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_HandleTypeDef
Time Handle Structure definition. More...

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_RTCStateTypeDef

HAL State structures definition.

Enumerator:
HAL_RTC_STATE_RESET

RTC not yet initialized or disabled

HAL_RTC_STATE_READY

RTC initialized and ready for use

HAL_RTC_STATE_BUSY

RTC process is ongoing

HAL_RTC_STATE_TIMEOUT

RTC timeout state

HAL_RTC_STATE_ERROR

RTC error state

Definition at line 138 of file stm32f1xx_hal_rtc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC_TimeTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TimeTypeDef Struct Reference
RTC Exported Types

RTC Time structure definition. More...

#include <stm32f1xx_hal_rtc.h>

Data Fields

uint8_t | Hours
uint8_t | Minutes
uint8_t | Seconds

Detailed Description

RTC Time structure definition.

Definition at line 111 of file stm32f1xx_hal_rtc.h.

Field Documentation

uint8_t RTC_TimeTypeDef::Hours

Specifies the RTC Time Hour. This parameter must be a number between Min_Data = 0 and Max_Data = 23

Definition at line 113 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Minutes

Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 116 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

uint8_t RTC_TimeTypeDef::Seconds

Specifies the RTC Time Seconds. This parameter must be a number between Min_Data = 0 and Max_Data = 59

Definition at line 119 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), and HAL_RTC_SetTime().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_rtc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC_AlarmTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_AlarmTypeDef Struct Reference
RTC Exported Types

RTC Alarm structure definition. More...

#include <stm32f1xx_hal_rtc.h>

Data Fields

RTC_TimeTypeDef AlarmTime
uint32_t Alarm

Detailed Description

RTC Alarm structure definition.

Definition at line 127 of file stm32f1xx_hal_rtc.h.

Field Documentation

uint32_t RTC_AlarmTypeDef::Alarm

Specifies the alarm ID (only 1 alarm ID for STM32F1). This parameter can be a value of Alarms Definitions

Definition at line 131 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

RTC_TimeTypeDef RTC_AlarmTypeDef::AlarmTime

Specifies the RTC Alarm Time members

Definition at line 129 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_SetAlarm(), and HAL_RTC_SetAlarm_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_rtc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_InitTypeDef Struct Reference
RTC Exported Types

RTC Configuration Structure definition. More...

#include <stm32f1xx_hal_rtc.h>

Data Fields

uint32_t | AsynchPrediv
uint32_t | OutPut

Detailed Description

RTC Configuration Structure definition.

Definition at line 151 of file stm32f1xx_hal_rtc.h.

Field Documentation

uint32_t RTC_InitTypeDef::AsynchPrediv

Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF or RTC_AUTO_1_SECOND If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase

Definition at line 153 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

uint32_t RTC_InitTypeDef::OutPut

Specifies which signal will be routed to the RTC Tamper pin. This parameter can be a value of Output source to output on the Tamper pin

Definition at line 157 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_rtc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC_DateTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_DateTypeDef Struct Reference
RTC Exported Types

RTC Date structure definition. More...

#include <stm32f1xx_hal_rtc.h>

Data Fields

uint8_t | WeekDay
uint8_t | Month
uint8_t | Date
uint8_t | Year

Detailed Description

RTC Date structure definition.

Definition at line 165 of file stm32f1xx_hal_rtc.h.

Field Documentation

uint8_t RTC_DateTypeDef::Date

Specifies the RTC Date. This parameter must be a number between Min_Data = 1 and Max_Data = 31

Definition at line 173 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_Init(), HAL_RTC_SetDate(), and RTC_DateUpdate().

uint8_t RTC_DateTypeDef::Month

Specifies the RTC Date Month (in BCD format). This parameter can be a value of Month Definitions

Definition at line 170 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_Init(), HAL_RTC_SetDate(), and RTC_DateUpdate().

uint8_t RTC_DateTypeDef::WeekDay

Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate). This parameter can be a value of WeekDay Definitions

Definition at line 167 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_SetDate(), and RTC_DateUpdate().

uint8_t RTC_DateTypeDef::Year

Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99

Definition at line 176 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_Init(), HAL_RTC_SetDate(), and RTC_DateUpdate().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_rtc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_HandleTypeDef Struct Reference
RTC Exported Types

Time Handle Structure definition. More...

#include <stm32f1xx_hal_rtc.h>

Data Fields

RTC_TypeDef * | Instance
RTC_InitTypeDef Init
RTC_DateTypeDef DateToUpdate
HAL_LockTypeDef | Lock
__IO HAL_RTCStateTypeDef | State

Detailed Description

Time Handle Structure definition.

Definition at line 184 of file stm32f1xx_hal_rtc.h.

Field Documentation

RTC_DateTypeDef RTC_HandleTypeDef::DateToUpdate

Current date set by user and updated automatically

Definition at line 190 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetDate(), HAL_RTC_Init(), HAL_RTC_SetDate(), and RTC_DateUpdate().

RTC_InitTypeDef RTC_HandleTypeDef::Init

RTC required parameters

Definition at line 188 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

RTC_TypeDef* RTC_HandleTypeDef::Instance

Register base address

Definition at line 186 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_Init(), HAL_RTC_SetTime(), HAL_RTC_WaitForSynchro(), RTC_EnterInitMode(), RTC_ExitInitMode(), RTC_ReadAlarmCounter(), RTC_ReadTimeCounter(), RTC_WriteAlarmCounter(), and RTC_WriteTimeCounter().

HAL_LockTypeDef RTC_HandleTypeDef::Lock

RTC locking object

Definition at line 192 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

__IO HAL_RTCStateTypeDef RTC_HandleTypeDef::State

Time communication state

Definition at line 194 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetState(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_DeactivateSecond(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_PollForTamper1Event(), HAL_RTCEx_RTCIRQHandler(), HAL_RTCEx_SetSecond_IT(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_TamperIRQHandler().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_rtc.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Automatic calculation of prediv for 1sec timebase

Defines
Automatic calculation of prediv for 1sec timebase
RTC Exported Constants

Defines

#define RTC_AUTO_1_SECOND 0xFFFFFFFFU

Define Documentation

#define RTC_AUTO_1_SECOND 0xFFFFFFFFU

Definition at line 210 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Input Parameter Format

Defines
Input Parameter Format
RTC Exported Constants

Defines

#define | RTC_FORMAT_BIN 0x000000000U
#define | RTC_FORMAT_BCD 0x000000001U

Define Documentation

#define RTC_FORMAT_BCD 0x000000001U

Definition at line 220 of file stm32f1xx_hal_rtc.h.

#define RTC_FORMAT_BIN 0x000000000U

Definition at line 219 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), and HAL_RTC_SetTime().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Month Definitions

Defines
Month Definitions
RTC Exported Constants

Defines

#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)

Define Documentation

#define RTC_MONTH_APRIL ((uint8_t)0x04)

Definition at line 234 of file stm32f1xx_hal_rtc.h.

#define RTC_MONTH_AUGUST ((uint8_t)0x08)

Definition at line 238 of file stm32f1xx_hal_rtc.h.

#define RTC_MONTH_DECEMBER ((uint8_t)0x12)

Definition at line 242 of file stm32f1xx_hal_rtc.h.

#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)

Definition at line 232 of file stm32f1xx_hal_rtc.h.

#define RTC_MONTH_JANUARY ((uint8_t)0x01)

Definition at line 231 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define RTC_MONTH_JULY ((uint8_t)0x07)

Definition at line 237 of file stm32f1xx_hal_rtc.h.

#define RTC_MONTH_JUNE ((uint8_t)0x06)

Definition at line 236 of file stm32f1xx_hal_rtc.h.

#define RTC_MONTH_MARCH ((uint8_t)0x03)

Definition at line 233 of file stm32f1xx_hal_rtc.h.

#define RTC_MONTH_MAY ((uint8_t)0x05)

Definition at line 235 of file stm32f1xx_hal_rtc.h.

#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)

Definition at line 241 of file stm32f1xx_hal_rtc.h.

#define RTC_MONTH_OCTOBER ((uint8_t)0x10)

Definition at line 240 of file stm32f1xx_hal_rtc.h.

#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)

Definition at line 239 of file stm32f1xx_hal_rtc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: WeekDay Definitions

Defines
WeekDay Definitions
RTC Exported Constants

Defines

#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x00)

Define Documentation

#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)

Definition at line 255 of file stm32f1xx_hal_rtc.h.

#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)

Definition at line 251 of file stm32f1xx_hal_rtc.h.

#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)

Definition at line 256 of file stm32f1xx_hal_rtc.h.

#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x00)

Definition at line 257 of file stm32f1xx_hal_rtc.h.

#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)

Definition at line 254 of file stm32f1xx_hal_rtc.h.

#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)

Definition at line 252 of file stm32f1xx_hal_rtc.h.

#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)

Definition at line 253 of file stm32f1xx_hal_rtc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Alarms Definitions

Defines
Alarms Definitions
RTC Exported Constants

Defines

#define RTC_ALARM_A 0U

Define Documentation

#define RTC_ALARM_A 0U

Specify alarm ID (mainly for legacy purposes)

Definition at line 266 of file stm32f1xx_hal_rtc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Output source to output on the Tamper pin

Defines
Output source to output on the Tamper pin
RTC Exported Constants

Defines

#define | RTC_OUTPUTSOURCE_NONE 0x00000000U
#define | RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO
#define | RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE
#define | RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE)

Define Documentation

#define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE

Alarm pulse signal on the TAMPER pin

Definition at line 279 of file stm32f1xx_hal_rtc.h.

#define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO

RTC clock with a frequency divided by 64 on the TAMPER pin

Definition at line 278 of file stm32f1xx_hal_rtc.h.

#define RTC_OUTPUTSOURCE_NONE 0x00000000U

No output on the TAMPER pin

Definition at line 277 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_Init().

#define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE)

Second pulse signal on the TAMPER pin

Definition at line 280 of file stm32f1xx_hal_rtc.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Interrupts Definitions

Defines
Interrupts Definitions
RTC Exported Constants

Defines

#define | RTC_IT_OW RTC_CRH_OWIE
#define | RTC_IT_ALRA RTC_CRH_ALRIE
#define | RTC_IT_SEC RTC_CRH_SECIE
#define | RTC_IT_TAMP1 BKP_CSR_TPIE

Define Documentation

#define RTC_IT_ALRA RTC_CRH_ALRIE

Alarm interrupt

Definition at line 290 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), and HAL_RTC_SetAlarm_IT().

#define RTC_IT_OW RTC_CRH_OWIE

Overflow interrupt

Definition at line 289 of file stm32f1xx_hal_rtc.h.

#define RTC_IT_SEC RTC_CRH_SECIE

Second interrupt

Definition at line 291 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateSecond(), HAL_RTCEx_RTCIRQHandler(), and HAL_RTCEx_SetSecond_IT().

#define RTC_IT_TAMP1 BKP_CSR_TPIE

TAMPER Pin interrupt enable

Definition at line 292 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper_IT(), and HAL_RTCEx_TamperIRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Flags Definitions

Defines
Flags Definitions
RTC Exported Constants

Defines

#define | RTC_FLAG_RTOFF RTC_CRL_RTOFF
#define | RTC_FLAG_RSF RTC_CRL_RSF
#define | RTC_FLAG_OW RTC_CRL_OWF
#define | RTC_FLAG_ALRAF RTC_CRL_ALRF
#define | RTC_FLAG_SEC RTC_CRL_SECF
#define | RTC_FLAG_TAMP1F BKP_CSR_TEF

Define Documentation

#define RTC_FLAG_ALRAF RTC_CRL_ALRF

Alarm flag

Definition at line 303 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_Init(), HAL_RTC_PollForAlarmAEvent(), and HAL_RTC_SetAlarm_IT().

#define RTC_FLAG_OW RTC_CRL_OWF

Overflow flag

Definition at line 302 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetTime(), and HAL_RTCEx_RTCIRQHandler().

#define RTC_FLAG_RSF RTC_CRL_RSF

Registers Synchronized flag

Definition at line 301 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_DeInit(), and HAL_RTC_WaitForSynchro().

#define RTC_FLAG_RTOFF RTC_CRL_RTOFF

RTC Operation OFF flag

Definition at line 300 of file stm32f1xx_hal_rtc.h.

#define RTC_FLAG_SEC RTC_CRL_SECF

Second flag

Definition at line 304 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_Init(), HAL_RTC_SetTime(), and HAL_RTCEx_RTCIRQHandler().

#define RTC_FLAG_TAMP1F BKP_CSR_TEF

Tamper Interrupt Flag

Definition at line 305 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_PollForTamper1Event(), and HAL_RTCEx_TamperIRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC Exported Macros

Defines
RTC Exported Macros
RTC

Defines

#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on ALARM Exti Line 17.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
Disable interrupt on ALARM Exti Line 17.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
Enable event on ALARM Exti Line 17.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
Disable event on ALARM Exti Line 17.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
ALARM EXTI line configuration: set falling edge trigger.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
Disable the ALARM Extended Interrupt Falling Trigger.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
ALARM EXTI line configuration: set rising edge trigger.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
Disable the ALARM Extended Interrupt Rising Trigger.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
ALARM EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the ALARM Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT))
Check whether the specified ALARM EXTI interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT))
Clear the ALARM EXTI flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on selected EXTI line.

Define Documentation

#define __HAL_RTC_ALARM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)

Clear the RTC Alarm's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_ALRAF
Return values:
None

Definition at line 398 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), HAL_RTC_DeactivateAlarm(), HAL_RTC_PollForAlarmAEvent(), and HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))

Disable the RTC Alarm interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
Return values:
None

Definition at line 358 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm().

#define __HAL_RTC_ALARM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))

Enable the RTC Alarm interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RTC_IT_ALRA: Alarm A interrupt
Return values:
None

Definition at line 348 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG ( ) (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT))

Clear the ALARM EXTI flag.

Return values:
None.

Definition at line 483 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT ( ) CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)

Disable event on ALARM Exti Line 17.

Return values:
None.

Definition at line 422 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE ( ) CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)

Disable the ALARM Extended Interrupt Falling Trigger.

Return values:
None.

Definition at line 436 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_IT ( ) CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)

Disable interrupt on ALARM Exti Line 17.

Return values:
None.

Definition at line 410 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_DeactivateAlarm().

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE ( ) CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)

Disable the ALARM Extended Interrupt Rising Trigger.

This parameter can be:

Return values:
None.

Definition at line 450 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do{                                                             \
    __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();                 \
    __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();                \
  } while(0U)

Disable the ALARM Extended Interrupt Rising & Falling Trigger.

This parameter can be:

Return values:
None.

Definition at line 467 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT ( ) SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)

Enable event on ALARM Exti Line 17.

Return values:
None.

Definition at line 416 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE ( ) SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)

ALARM EXTI line configuration: set falling edge trigger.

Return values:
None.

Definition at line 429 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_ENABLE_IT ( ) SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)

Enable interrupt on ALARM Exti Line 17.

Return values:
None.

Definition at line 404 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE ( ) SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)

ALARM EXTI line configuration: set rising edge trigger.

Return values:
None.

Definition at line 443 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_SetAlarm_IT().

#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do{                                                            \
    __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();                 \
    __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();                \
  } while(0U)

ALARM EXTI line configuration: set rising & falling edge trigger.

Return values:
None.

Definition at line 456 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT ( ) SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT)

Generate a Software interrupt on selected EXTI line.

Return values:
None.

Definition at line 489 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_ALARM_EXTI_GET_FLAG ( ) (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT))

Check whether the specified ALARM EXTI interrupt flag is set or not.

Return values:
EXTI ALARM Line Status.

Definition at line 477 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC Alarm's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Alarm Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_ALRAF
Return values:
None

Definition at line 378 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler(), and HAL_RTC_PollForAlarmAEvent().

#define __HAL_RTC_ALARM_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET)

Check whether the specified RTC Alarm interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to check. This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
Return values:
None

Definition at line 388 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_ALARM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)

Check whether the specified RTC Alarm interrupt has been enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Alarm interrupt sources to be checked This parameter can be:
  • RTC_IT_ALRA: Alarm A interrupt
Return values:
None

Definition at line 368 of file stm32f1xx_hal_rtc.h.

Referenced by HAL_RTC_AlarmIRQHandler().

#define __HAL_RTC_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)

Reset RTC handle state.

Parameters:
__HANDLE__,: RTC handle.
Return values:
None

Definition at line 324 of file stm32f1xx_hal_rtc.h.

#define __HAL_RTC_WRITEPROTECTION_DISABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)

Disable the write protection for RTC registers.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 331 of file stm32f1xx_hal_rtc.h.

Referenced by RTC_EnterInitMode().

#define __HAL_RTC_WRITEPROTECTION_ENABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)

Enable the write protection for RTC registers.

Parameters:
__HANDLE__,: specifies the RTC handle.
Return values:
None

Definition at line 338 of file stm32f1xx_hal_rtc.h.

Referenced by RTC_ExitInitMode().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Alias define maintained for legacy

Defines
Alias define maintained for legacy
RTCEx Private Macros

Defines

#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler

Define Documentation

#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler

Definition at line 64 of file stm32f1xx_hal_rtc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Private macros to check input parameters

Defines
Private macros to check input parameters
RTCEx Private Macros

Defines

#define | IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1)
#define | IS_RTC_TAMPER_TRIGGER(__TRIGGER__)
#define | IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER)
#define | IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU)

Define Documentation

#define IS_RTC_BKP ( BKP ) ((BKP) <= (uint32_t)RTC_BKP_NUMBER)

Definition at line 81 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_BKUPRead(), and HAL_RTCEx_BKUPWrite().

#define IS_RTC_SMOOTH_CALIB_MINUS ( __VALUE__ ) ((__VALUE__) <= 0x0000007FU)

Definition at line 83 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSmoothCalib().

#define IS_RTC_TAMPER ( __TAMPER__ ) ((__TAMPER__) == RTC_TAMPER_1)

Definition at line 73 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

#define IS_RTC_TAMPER_TRIGGER ( __TRIGGER__ )
Value:
(((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
                                             ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))

Definition at line 75 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC Tamper functions

Functions
RTC Tamper functions
RTCEx Exported Functions

RTC Tamper functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivates Tamper.
void | HAL_RTCEx_TamperIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Tamper interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper1 Polling.

Detailed Description

RTC Tamper functions.

 ===============================================================================
                 ##### RTC Tamper functions #####
 ===============================================================================

 [..] This section provides functions allowing to configure Tamper feature

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Tamper
 | ) |  |

Deactivates Tamper.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Tamper,: Selected tamper pin. This parameter can be a value of Tamper Pins Definitions
Return values:
HAL status

Definition at line 193 of file stm32f1xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_DISABLE_IT, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, IS_RTC_TAMPER, RTC_FLAG_TAMP1F, RTC_IT_TAMP1, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | Timeout
 | ) |  |

This function handles Tamper1 Polling.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 275 of file stm32f1xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, HAL_GetTick(), HAL_RTC_STATE_READY, HAL_RTC_STATE_TIMEOUT, RTC_FLAG_TAMP1F, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetTamper | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Sets Tamper.

Note:
By calling this API we disable the tamper interrupt for all tampers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTamper,: Pointer to Tamper Structure.
Note:
Tamper can be enabled only if ASOE and CCO bit are reset
Return values:
HAL status

Definition at line 99 of file stm32f1xx_hal_rtc_ex.c.

References assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, IS_RTC_TAMPER, IS_RTC_TAMPER_TRIGGER, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, and RTC_TamperTypeDef::Trigger.

HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT | ( | RTC_HandleTypeDef * | hrtc,
 |  | RTC_TamperTypeDef * | sTamper
 | ) |  |

Sets Tamper with interrupt.

Note:
By calling this API we force the tamper interrupt for all tampers.
Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
sTamper,: Pointer to RTC Tamper.
Note:
Tamper can be enabled only if ASOE and CCO bit are reset
Return values:
HAL status

Definition at line 145 of file stm32f1xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_ENABLE_IT, assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, IS_RTC_TAMPER, IS_RTC_TAMPER_TRIGGER, RTC_IT_TAMP1, RTC_HandleTypeDef::State, RTC_TamperTypeDef::Tamper, and RTC_TamperTypeDef::Trigger.

void HAL_RTCEx_Tamper1EventCallback ( RTC_HandleTypeDef * hrtc )

Tamper 1 callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 259 of file stm32f1xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_TamperIRQHandler().

void HAL_RTCEx_TamperIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles Tamper interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 233 of file stm32f1xx_hal_rtc_ex.c.

References __HAL_RTC_TAMPER_CLEAR_FLAG, __HAL_RTC_TAMPER_GET_FLAG, __HAL_RTC_TAMPER_GET_IT_SOURCE, HAL_RTC_STATE_READY, HAL_RTCEx_Tamper1EventCallback(), RTC_FLAG_TAMP1F, RTC_IT_TAMP1, and RTC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC Second functions

Functions
RTC Second functions
RTCEx Exported Functions

RTC Second functions. More...

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetSecond_IT (RTC_HandleTypeDef *hrtc)
Sets Interrupt for second.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateSecond (RTC_HandleTypeDef *hrtc)
Deactivates Second.
void | HAL_RTCEx_RTCIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles second interrupt request.
__weak void | HAL_RTCEx_RTCEventCallback (RTC_HandleTypeDef *hrtc)
Second event callback.
__weak void | HAL_RTCEx_RTCEventErrorCallback (RTC_HandleTypeDef *hrtc)
Second event error callback.

Detailed Description

RTC Second functions.

 ===============================================================================
                 ##### RTC Second functions #####
 ===============================================================================

 [..] This section provides functions implementing second interupt handlers

Function Documentation

HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond ( RTC_HandleTypeDef * hrtc )

Deactivates Second.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 361 of file stm32f1xx_hal_rtc_ex.c.

References __HAL_RTC_SECOND_DISABLE_IT, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_IT_SEC, and RTC_HandleTypeDef::State.

void HAL_RTCEx_RTCEventCallback ( RTC_HandleTypeDef * hrtc )

Second event callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 431 of file stm32f1xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_RTCIRQHandler().

void HAL_RTCEx_RTCEventErrorCallback ( RTC_HandleTypeDef * hrtc )

Second event error callback.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 446 of file stm32f1xx_hal_rtc_ex.c.

Referenced by HAL_RTCEx_RTCIRQHandler().

void HAL_RTCEx_RTCIRQHandler ( RTC_HandleTypeDef * hrtc )

This function handles second interrupt request.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
None

Definition at line 391 of file stm32f1xx_hal_rtc_ex.c.

References __HAL_RTC_OVERFLOW_CLEAR_FLAG, __HAL_RTC_SECOND_CLEAR_FLAG, __HAL_RTC_SECOND_GET_FLAG, __HAL_RTC_SECOND_GET_IT_SOURCE, HAL_RTC_STATE_ERROR, HAL_RTC_STATE_READY, HAL_RTCEx_RTCEventCallback(), HAL_RTCEx_RTCEventErrorCallback(), RTC_FLAG_OW, RTC_FLAG_SEC, RTC_IT_SEC, and RTC_HandleTypeDef::State.

HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT ( RTC_HandleTypeDef * hrtc )

Sets Interrupt for second.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
Return values:
HAL status

Definition at line 331 of file stm32f1xx_hal_rtc_ex.c.

References __HAL_RTC_SECOND_ENABLE_IT, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, RTC_IT_SEC, and RTC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Extended Peripheral Control functions

Functions
Extended Peripheral Control functions
RTCEx Exported Functions

Extended Peripheral Control functions. More...

Functions

void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
Sets the Smooth calibration parameters.

Detailed Description

Extended Peripheral Control functions.

 ===============================================================================
              ##### Extension Peripheral Control functions #####
 ===============================================================================
    [..]
    This subsection provides functions allowing to
      (+) Writes a data in a specified RTC Backup data register
      (+) Read a data in a specified RTC Backup data register
      (+) Sets the Smooth calibration parameters.

Function Documentation

uint32_t HAL_RTCEx_BKUPRead | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister
 | ) |  |

Reads data from the specified RTC Backup data Register.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to specify the register (depending devices).
Return values:
Read value

Definition at line 508 of file stm32f1xx_hal_rtc_ex.c.

References assert_param, and IS_RTC_BKP.

void HAL_RTCEx_BKUPWrite | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | BackupRegister,
 |  | uint32_t | Data
 | ) |  |

Writes a data in a specified RTC Backup data register.

Parameters:
hrtc,: pointer to a RTC_HandleTypeDef structure that contains the configuration information for RTC.
BackupRegister,: RTC Backup data Register number. This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to specify the register (depending devices).
Data,: Data to be written in the specified RTC Backup data register.
Return values:
None

Definition at line 486 of file stm32f1xx_hal_rtc_ex.c.

References assert_param, and IS_RTC_BKP.

HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib | ( | RTC_HandleTypeDef * | hrtc,
 |  | uint32_t | SmoothCalibPeriod,
 |  | uint32_t | SmoothCalibPlusPulses,
 |  | uint32_t | SmouthCalibMinusPulsesValue
 | ) |  |

Sets the Smooth calibration parameters.

Parameters:
hrtc,: RTC handle
SmoothCalibPeriod,: Not used (only present for compatibility with another families)
SmoothCalibPlusPulses,: Not used (only present for compatibility with another families)
SmouthCalibMinusPulsesValue,: specifies the RTC Clock Calibration value. This parameter must be a number between 0 and 0x7F.
Return values:
HAL status

Definition at line 535 of file stm32f1xx_hal_rtc_ex.c.

References assert_param, HAL_RTC_STATE_BUSY, HAL_RTC_STATE_READY, IS_RTC_SMOOTH_CALIB_MINUS, and RTC_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC_TamperTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
RTC_TamperTypeDef Struct Reference
RTCEx Exported Types

RTC Tamper structure definition. More...

#include <stm32f1xx_hal_rtc_ex.h>

Data Fields

uint32_t | Tamper
uint32_t | Trigger

Detailed Description

RTC Tamper structure definition.

Definition at line 100 of file stm32f1xx_hal_rtc_ex.h.

Field Documentation

uint32_t RTC_TamperTypeDef::Tamper

Specifies the Tamper Pin. This parameter can be a value of Tamper Pins Definitions

Definition at line 102 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

uint32_t RTC_TamperTypeDef::Trigger

Specifies the Tamper Trigger. This parameter can be a value of Tamper Trigger Definitions

Definition at line 105 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper(), and HAL_RTCEx_SetTamper_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_rtc_ex.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Tamper Pins Definitions

Defines
Tamper Pins Definitions
RTCEx Exported Constants

Defines

#define RTC_TAMPER_1 BKP_CR_TPE

Define Documentation

#define RTC_TAMPER_1 BKP_CR_TPE

Select tamper to be enabled (mainly for legacy purposes)

Definition at line 122 of file stm32f1xx_hal_rtc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Tamper Trigger Definitions

Defines
Tamper Trigger Definitions
RTCEx Exported Constants

Defines

#define | RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL
#define | RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U

Define Documentation

#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U

A low level on the TAMPER pin resets all data backup registers (if TPE bit is set)

Definition at line 132 of file stm32f1xx_hal_rtc_ex.h.

#define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL

A high level on the TAMPER pin resets all data backup registers (if TPE bit is set)

Definition at line 131 of file stm32f1xx_hal_rtc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Backup Registers Definitions

Defines
Backup Registers Definitions
RTCEx Exported Constants

Defines

#define | RTC_BKP_DR1 0x00000001U
#define | RTC_BKP_DR2 0x00000002U
#define | RTC_BKP_DR3 0x00000003U
#define | RTC_BKP_DR4 0x00000004U
#define | RTC_BKP_DR5 0x00000005U
#define | RTC_BKP_DR6 0x00000006U
#define | RTC_BKP_DR7 0x00000007U
#define | RTC_BKP_DR8 0x00000008U
#define | RTC_BKP_DR9 0x00000009U
#define | RTC_BKP_DR10 0x0000000AU

Define Documentation

#define RTC_BKP_DR1 0x00000001U

Definition at line 142 of file stm32f1xx_hal_rtc_ex.h.

#define RTC_BKP_DR10 0x0000000AU

Definition at line 151 of file stm32f1xx_hal_rtc_ex.h.

#define RTC_BKP_DR2 0x00000002U

Definition at line 143 of file stm32f1xx_hal_rtc_ex.h.

#define RTC_BKP_DR3 0x00000003U

Definition at line 144 of file stm32f1xx_hal_rtc_ex.h.

#define RTC_BKP_DR4 0x00000004U

Definition at line 145 of file stm32f1xx_hal_rtc_ex.h.

#define RTC_BKP_DR5 0x00000005U

Definition at line 146 of file stm32f1xx_hal_rtc_ex.h.

#define RTC_BKP_DR6 0x00000006U

Definition at line 147 of file stm32f1xx_hal_rtc_ex.h.

#define RTC_BKP_DR7 0x00000007U

Definition at line 148 of file stm32f1xx_hal_rtc_ex.h.

#define RTC_BKP_DR8 0x00000008U

Definition at line 149 of file stm32f1xx_hal_rtc_ex.h.

#define RTC_BKP_DR9 0x00000009U

Definition at line 150 of file stm32f1xx_hal_rtc_ex.h.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTCEx Exported Macros

Defines
RTCEx Exported Macros
RTCEx

Defines

#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(BKP->CSR, (__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI)
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Enable the RTC Second interrupt.
#define | __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Disable the RTC Second interrupt.
#define | __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
Check whether the specified RTC Second interrupt has occurred or not.
#define | __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Second's flag status.
#define | __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
Clear the RTC Second's pending flags.
#define | __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Enable the RTC Overflow interrupt.
#define | __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Disable the RTC Overflow interrupt.
#define | __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET)
Check whether the specified RTC Overflow interrupt has occurred or not.
#define | __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Overflow's flag status.
#define | __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
Clear the RTC Overflow's pending flags.

Define Documentation

#define __HAL_RTC_OVERFLOW_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)

Clear the RTC Overflow's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Overflow Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_OW
Return values:
None

Definition at line 360 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_RTCIRQHandler().

#define __HAL_RTC_OVERFLOW_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))

Disable the RTC Overflow interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Overflow interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RTC_IT_OW: Overflow A interrupt
Return values:
None

Definition at line 330 of file stm32f1xx_hal_rtc_ex.h.

#define __HAL_RTC_OVERFLOW_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))

Enable the RTC Overflow interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Overflow interrupt sources to be enabled This parameter can be any combination of the following values:
  • RTC_IT_OW: Overflow A interrupt
Return values:
None

Definition at line 320 of file stm32f1xx_hal_rtc_ex.h.

#define __HAL_RTC_OVERFLOW_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC Overflow's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Overflow Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_OW
Return values:
None

Definition at line 350 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTC_GetTime().

#define __HAL_RTC_OVERFLOW_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET)

Check whether the specified RTC Overflow interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Overflow interrupt sources to be enabled or disabled. This parameter can be:
  • RTC_IT_OW: Overflow A interrupt
Return values:
None

Definition at line 340 of file stm32f1xx_hal_rtc_ex.h.

#define __HAL_RTC_SECOND_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)

Clear the RTC Second's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Second Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_SEC
Return values:
None

Definition at line 310 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_RTCIRQHandler().

#define __HAL_RTC_SECOND_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))

Disable the RTC Second interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Second interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RTC_IT_SEC: Second A interrupt
Return values:
None

Definition at line 280 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateSecond().

#define __HAL_RTC_SECOND_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))

Enable the RTC Second interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Second interrupt sources to be enabled This parameter can be any combination of the following values:
  • RTC_IT_SEC: Second A interrupt
Return values:
None

Definition at line 270 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetSecond_IT().

#define __HAL_RTC_SECOND_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC Second's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Second Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_SEC
Return values:
None

Definition at line 300 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_RTCIRQHandler().

#define __HAL_RTC_SECOND_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)

Check whether the specified RTC Second interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Second interrupt sources to be enabled or disabled. This parameter can be:
  • RTC_IT_SEC: Second A interrupt
Return values:
None

Definition at line 290 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_RTCIRQHandler().

#define __HAL_RTC_TAMPER_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI)

Clear the RTC Tamper's pending flags.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_TAMP1F
Return values:
None

Definition at line 260 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_PollForTamper1Event(), and HAL_RTCEx_TamperIRQHandler().

#define __HAL_RTC_TAMPER_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | CLEAR_BIT(BKP->CSR, (__INTERRUPT__))

Disable the RTC Tamper interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt sources to be disabled. This parameter can be any combination of the following values:
  • RTC_IT_TAMP1: Tamper A interrupt
Return values:
None

Definition at line 220 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_DeactivateTamper().

#define __HAL_RTC_TAMPER_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT(BKP->CSR, (__INTERRUPT__))

Enable the RTC Tamper interrupt.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt sources to be enabled This parameter can be any combination of the following values:
  • RTC_IT_TAMP1: Tamper A interrupt
Return values:
None

Definition at line 210 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_SetTamper_IT().

#define __HAL_RTC_TAMPER_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET)

Get the selected RTC Tamper's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__FLAG__,: specifies the RTC Tamper Flag sources to be enabled or disabled. This parameter can be:
  • RTC_FLAG_TAMP1F
Return values:
None

Definition at line 240 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_PollForTamper1Event(), and HAL_RTCEx_TamperIRQHandler().

#define __HAL_RTC_TAMPER_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET)

Get the selected RTC Tamper's flag status.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt sources to be checked. This parameter can be:
  • RTC_IT_TAMP1
Return values:
None

Definition at line 250 of file stm32f1xx_hal_rtc_ex.h.

#define __HAL_RTC_TAMPER_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET)

Check whether the specified RTC Tamper interrupt has been enabled or not.

Parameters:
__HANDLE__,: specifies the RTC handle.
__INTERRUPT__,: specifies the RTC Tamper interrupt sources to be checked. This parameter can be:
  • RTC_IT_TAMP1
Return values:
None

Definition at line 230 of file stm32f1xx_hal_rtc_ex.h.

Referenced by HAL_RTCEx_TamperIRQHandler().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SmartCard Initialization and de-initialization functions

Functions
SmartCard Initialization and de-initialization functions
SMARTCARD Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsc)
Initializes the SmartCard mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsc)
DeInitializes the USART SmartCard peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP Init.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP DeInit.
HAL_StatusTypeDef | HAL_SMARTCARD_ReInit (SMARTCARD_HandleTypeDef *hsc)

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
            ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USART
  in Smartcard mode.
  [..]
  The Smartcard interface is designed to support asynchronous protocol Smartcards as
  defined in the ISO 7816-3 standard.
  [..]
  The USART can provide a clock to the smartcard through the SCLK output.
  In smartcard mode, SCLK is not associated to the communication but is simply derived
  from the internal peripheral input clock through a 5-bit prescaler.
  [..]
  (+) For the Smartcard mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length => Should be 9 bits (8 bits + parity)
      (++) Stop Bit
      (++) Parity: => Should be enabled
      (++) USART polarity
      (++) USART phase
      (++) USART LastBit
      (++) Receiver/transmitter modes
      (++) Prescaler
      (++) GuardTime
      (++) NACKState: The Smartcard NACK state

     (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
        (++) Word Length = 9 Bits
        (++) 1.5 Stop Bit
        (++) Even parity
        (++) BaudRate = 12096 baud
        (++) Tx and Rx enabled
  [..]
  Please refer to the ISO 7816-3 specification for more details.

  [..]
   (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended
       to use 1.5 stop bits for both transmitting and receiving to avoid switching
       between the two configurations.
  [..]
    The HAL_SMARTCARD_Init() function follows the USART  SmartCard configuration
    procedure (details for the procedure are available in reference manual (RM0329)).

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_DeInit ( SMARTCARD_HandleTypeDef * hsc )

DeInitializes the USART SmartCard peripheral.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
HAL status

Definition at line 316 of file stm32f1xx_hal_smartcard.c.

References assert_param, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspDeInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_SMARTCARD_Init ( SMARTCARD_HandleTypeDef * hsc )

Initializes the SmartCard mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
HAL status

Definition at line 249 of file stm32f1xx_hal_smartcard.c.

References __HAL_SMARTCARD_ENABLE, assert_param, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, SMARTCARD_InitTypeDef::GuardTime, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_MspInit(), HAL_SMARTCARD_STATE_BUSY, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_STATE_RESET, SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::Lock, SMARTCARD_InitTypeDef::NACKState, SMARTCARD_InitTypeDef::Prescaler, SMARTCARD_HandleTypeDef::RxState, and SMARTCARD_SetConfig().

void HAL_SMARTCARD_MspDeInit ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD MSP DeInit.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 363 of file stm32f1xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_DeInit().

void HAL_SMARTCARD_MspInit ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD MSP Init.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 348 of file stm32f1xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Init().

HAL_StatusTypeDef HAL_SMARTCARD_ReInit ( SMARTCARD_HandleTypeDef * hsc )
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
SMARTCARD Exported Functions

SMARTCARD Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsc)
This function handles SMARTCARD interrupt request.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Tx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Rx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD error callbacks.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD Abort Transmit Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD Abort ReceiveComplete callback.

Detailed Description

SMARTCARD Transmit and Receive functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
   This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.

 [..]
    (#) Smartcard is a single wire half duplex communication protocol.
    The Smartcard interface is designed to support asynchronous protocol Smartcards as
    defined in the ISO 7816-3 standard.
    (#) The USART should be configured as:
       (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
       (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) Non Blocking mode: The communication is performed using Interrupts
           or DMA, These APIs return the HAL status.
           The end of the data processing will be indicated through the
           dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
           will be executed respectively at the end of the Transmit or Receive process
           The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected

    (#) Blocking mode APIs are :
        (++) HAL_SMARTCARD_Transmit()
        (++) HAL_SMARTCARD_Receive()

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_SMARTCARD_Transmit_IT()
        (++) HAL_SMARTCARD_Receive_IT()
        (++) HAL_SMARTCARD_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_SMARTCARD_Transmit_DMA()
        (++) HAL_SMARTCARD_Receive_DMA()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_SMARTCARD_TxCpltCallback()
        (++) HAL_SMARTCARD_RxCpltCallback()
        (++) HAL_SMARTCARD_ErrorCallback()

Function Documentation

HAL_StatusTypeDef HAL_SMARTCARD_Abort ( SMARTCARD_HandleTypeDef * hsc )

Abort ongoing transfers (blocking mode).

Parameters:
hsc SMARTCARD handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 784 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT ( SMARTCARD_HandleTypeDef * hsc )

Abort ongoing transfers (Interrupt mode).

Parameters:
hsc SMARTCARD handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 935 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortCpltCallback ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD Abort Complete callback.

Parameters:
hsc SMARTCARD handle.
Return values:
None

Definition at line 1350 of file stm32f1xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_Abort_IT(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive ( SMARTCARD_HandleTypeDef * hsc )

Abort ongoing Receive transfer (blocking mode).

Parameters:
hsc SMARTCARD handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 890 of file stm32f1xx_hal_smartcard.c.

References HAL_DMA_Abort(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT ( SMARTCARD_HandleTypeDef * hsc )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
hsc SMARTCARD handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1121 of file stm32f1xx_hal_smartcard.c.

References HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_DMARxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortReceiveCpltCallback ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD Abort ReceiveComplete callback.

Parameters:
hsc SMARTCARD handle.
Return values:
None

Definition at line 1380 of file stm32f1xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortReceive_IT(), and SMARTCARD_DMARxOnlyAbortCallback().

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit ( SMARTCARD_HandleTypeDef * hsc )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
hsc SMARTCARD handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 848 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT ( SMARTCARD_HandleTypeDef * hsc )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
hsc SMARTCARD handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1056 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SMARTCARD_AbortTransmitCpltCallback ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD Abort Transmit Complete callback.

Parameters:
hsc SMARTCARD handle.
Return values:
None

Definition at line 1365 of file stm32f1xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_AbortTransmit_IT(), and SMARTCARD_DMATxOnlyAbortCallback().

void HAL_SMARTCARD_ErrorCallback ( SMARTCARD_HandleTypeDef * hsc )

SMARTCARD error callbacks.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 1336 of file stm32f1xx_hal_smartcard.c.

Referenced by HAL_SMARTCARD_IRQHandler(), SMARTCARD_DMAAbortOnError(), and SMARTCARD_DMAError().

void HAL_SMARTCARD_IRQHandler ( SMARTCARD_HandleTypeDef * hsc )

This function handles SMARTCARD interrupt request.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 1179 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SMARTCARD_ERROR_FE, HAL_SMARTCARD_ERROR_NE, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_ERROR_ORE, HAL_SMARTCARD_ERROR_PE, HAL_SMARTCARD_ErrorCallback(), SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_DMAAbortOnError(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_FLAG_FE, SMARTCARD_FLAG_NE, SMARTCARD_FLAG_ORE, SMARTCARD_FLAG_PE, SMARTCARD_FLAG_TC, SMARTCARD_FLAG_TXE, SMARTCARD_Receive_IT(), SMARTCARD_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 501 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_FLAG_RXNE, and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be received
Note:
When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
Return values:
HAL status

Definition at line 714 of file stm32f1xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_OREFLAG, SMARTCARD_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferSize, SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be received
Return values:
HAL status

Definition at line 607 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_HandleTypeDef::RxXferSize.

void HAL_SMARTCARD_RxCpltCallback ( SMARTCARD_HandleTypeDef * hsc )

Rx Transfer completed callbacks.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 1321 of file stm32f1xx_hal_smartcard.c.

Referenced by SMARTCARD_DMAReceiveCplt(), and SMARTCARD_Receive_IT().

HAL_StatusTypeDef HAL_SMARTCARD_Transmit | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Send an amount of data in blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 438 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_FLAG_TC, SMARTCARD_FLAG_TXE, SMARTCARD_WaitOnFlagUntilTimeout(), SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 652 of file stm32f1xx_hal_smartcard.c.

References __HAL_SMARTCARD_CLEAR_FLAG, SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_DMAError(), SMARTCARD_DMATransmitCplt(), SMARTCARD_FLAG_TC, SMARTCARD_HandleTypeDef::TxXferCount, SMARTCARD_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Send an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 560 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_BUSY_TX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, SMARTCARD_HandleTypeDef::TxXferCount, and SMARTCARD_HandleTypeDef::TxXferSize.

void HAL_SMARTCARD_TxCpltCallback ( SMARTCARD_HandleTypeDef * hsc )

Tx Transfer completed callbacks.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 1306 of file stm32f1xx_hal_smartcard.c.

Referenced by SMARTCARD_EndTransmit_IT().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SMARTCARD Exported Functions

SMARTCARD State and Errors functions. More...

Functions

HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsc)
return the SMARTCARD state
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsc)
Return the SMARTCARD error code.

Detailed Description

SMARTCARD State and Errors functions.

 ===============================================================================
                ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SmartCard.
     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
     (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.

Function Documentation

uint32_t HAL_SMARTCARD_GetError ( SMARTCARD_HandleTypeDef * hsc )

Return the SMARTCARD error code.

Parameters:
hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD.
Return values:
SMARTCARD Error Code

Definition at line 1430 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode.

HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState ( SMARTCARD_HandleTypeDef * hsc )

return the SMARTCARD state

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
HAL state

Definition at line 1415 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, and SMARTCARD_HandleTypeDef::RxState.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Exported Functions

Modules | Functions
SMARTCARD Exported Functions
SMARTCARD

Modules

SmartCard Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

SMARTCARD Transmit and Receive functions.

Peripheral State and Errors functions

SMARTCARD State and Errors functions.

Functions

static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles SMARTCARD Communication Timeout.
static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsc)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsc)
End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc)
Receive an amount of data in non blocking mode.
static void | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc)
Configure the SMARTCARD peripheral.

Function Documentation

static void SMARTCARD_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1590 of file stm32f1xx_hal_smartcard.c.

References HAL_SMARTCARD_ErrorCallback(), SMARTCARD_HandleTypeDef::RxXferCount, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1491 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_ERROR_DMA, HAL_SMARTCARD_ErrorCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_BUSY_TX, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_EndRxTransfer(), SMARTCARD_EndTxTransfer(), and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1465 of file stm32f1xx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::RxState, and SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_Receive_DMA().

static void SMARTCARD_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1645 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1704 of file stm32f1xx_hal_smartcard.c.

References HAL_SMARTCARD_AbortReceiveCpltCallback(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::RxState, and SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_AbortReceive_IT().

static void SMARTCARD_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1445 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_Transmit_DMA().

static void SMARTCARD_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1607 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::ErrorCode, SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortCpltCallback(), HAL_SMARTCARD_ERROR_NONE, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::hdmarx, SMARTCARD_HandleTypeDef::hdmatx, SMARTCARD_HandleTypeDef::RxState, SMARTCARD_HandleTypeDef::RxXferCount, SMARTCARD_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SMARTCARD_Abort_IT().

static void SMARTCARD_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1683 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_AbortTransmitCpltCallback(), HAL_SMARTCARD_STATE_READY, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_AbortTransmit_IT().

static void SMARTCARD_EndRxTransfer ( SMARTCARD_HandleTypeDef * hsc ) [static]

End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).

Parameters:
hsc,: SMARTCARD handle.
Return values:
None

Definition at line 1572 of file stm32f1xx_hal_smartcard.c.

References HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_IRQHandler(), and SMARTCARD_DMAError().

static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT ( SMARTCARD_HandleTypeDef * hsmartcard ) [static]

Wraps up transmission in non blocking mode.

Parameters:
hsmartcard,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for the specified SMARTCARD module.
Return values:
HAL status

Definition at line 1757 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, HAL_SMARTCARD_TxCpltCallback(), and SMARTCARD_HandleTypeDef::Instance.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_EndTxTransfer ( SMARTCARD_HandleTypeDef * hsc ) [static]

End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).

Parameters:
hsc,: SMARTCARD handle.
Return values:
None

Definition at line 1557 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_READY, and SMARTCARD_HandleTypeDef::Instance.

Referenced by SMARTCARD_DMAError().

static HAL_StatusTypeDef SMARTCARD_Receive_IT ( SMARTCARD_HandleTypeDef * hsc ) [static]

Receive an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
HAL status

Definition at line 1779 of file stm32f1xx_hal_smartcard.c.

References HAL_SMARTCARD_RxCpltCallback(), HAL_SMARTCARD_STATE_BUSY_RX, HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pRxBuffPtr, SMARTCARD_HandleTypeDef::RxState, and SMARTCARD_HandleTypeDef::RxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static void SMARTCARD_SetConfig ( SMARTCARD_HandleTypeDef * hsc ) [static]

Configure the SMARTCARD peripheral.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
None

Definition at line 1821 of file stm32f1xx_hal_smartcard.c.

References assert_param, SMARTCARD_InitTypeDef::BaudRate, SMARTCARD_InitTypeDef::CLKLastBit, SMARTCARD_InitTypeDef::CLKPhase, SMARTCARD_InitTypeDef::CLKPolarity, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), SMARTCARD_HandleTypeDef::Init, SMARTCARD_HandleTypeDef::Instance, IS_SMARTCARD_BAUDRATE, IS_SMARTCARD_LASTBIT, IS_SMARTCARD_MODE, IS_SMARTCARD_NACK_STATE, IS_SMARTCARD_PARITY, IS_SMARTCARD_PHASE, IS_SMARTCARD_POLARITY, IS_SMARTCARD_STOPBITS, IS_SMARTCARD_WORD_LENGTH, SMARTCARD_InitTypeDef::Mode, SMARTCARD_InitTypeDef::NACKState, SMARTCARD_InitTypeDef::Parity, SMARTCARD_BRR, SMARTCARD_InitTypeDef::StopBits, and SMARTCARD_InitTypeDef::WordLength.

Referenced by HAL_SMARTCARD_Init().

static HAL_StatusTypeDef SMARTCARD_Transmit_IT ( SMARTCARD_HandleTypeDef * hsc ) [static]

Send an amount of data in non blocking mode.

Parameters:
hsc,: pointer to a SMARTCARD_HandleTypeDef structure that contains the configuration information for SMARTCARD module.
Return values:
HAL status

Definition at line 1723 of file stm32f1xx_hal_smartcard.c.

References SMARTCARD_HandleTypeDef::gState, HAL_SMARTCARD_STATE_BUSY_TX, SMARTCARD_HandleTypeDef::Instance, SMARTCARD_HandleTypeDef::pTxBuffPtr, and SMARTCARD_HandleTypeDef::TxXferCount.

Referenced by HAL_SMARTCARD_IRQHandler().

static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout | ( | SMARTCARD_HandleTypeDef * | hsc,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles SMARTCARD Communication Timeout.

Parameters:
hsc,: SMARTCARD handle
Flag,: specifies the SMARTCARD flag to check.
Status,: The new Flag status (SET or RESET).
Timeout,: Timeout duration
Tickstart,: tick start value
Return values:
HAL status

Definition at line 1525 of file stm32f1xx_hal_smartcard.c.

References __HAL_SMARTCARD_GET_FLAG, SMARTCARD_HandleTypeDef::gState, HAL_GetTick(), HAL_SMARTCARD_STATE_READY, SMARTCARD_HandleTypeDef::Instance, and SMARTCARD_HandleTypeDef::RxState.

Referenced by HAL_SMARTCARD_Receive(), and HAL_SMARTCARD_Transmit().

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Exported Types

Data Structures | Enumerations
SMARTCARD Exported Types
SMARTCARD

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00U, HAL_SMARTCARD_STATE_READY = 0x20U, HAL_SMARTCARD_STATE_BUSY = 0x24U, HAL_SMARTCARD_STATE_BUSY_TX = 0x21U,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, HAL_SMARTCARD_STATE_ERROR = 0xE0U
}
HAL SMARTCARD State structures definition. More...

Enumeration Type Documentation

enum HAL_SMARTCARD_StateTypeDef

HAL SMARTCARD State structures definition.

Note:
HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
  • gState contains SMARTCARD state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_SMARTCARD_STATE_RESET

Peripheral is not yet Initialized Value is allowed for gState and RxState

HAL_SMARTCARD_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_SMARTCARD_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_SMARTCARD_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_SMARTCARD_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_SMARTCARD_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_SMARTCARD_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_SMARTCARD_STATE_ERROR

Error Value is allowed for gState only

Definition at line 148 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_InitTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD Init Structure definition. More...

#include <stm32f1xx_hal_smartcard.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit
uint32_t | Prescaler
uint32_t | GuardTime
uint32_t | NACKState

Detailed Description

SMARTCARD Init Structure definition.

Definition at line 65 of file stm32f1xx_hal_smartcard.h.

Field Documentation

uint32_t SMARTCARD_InitTypeDef::BaudRate

This member configures the SmartCard communication baud rate. The baud rate is computed using the following formula:

  • IntegerDivider = ((PCLKx) / (16 * (hsmartcard->Init.BaudRate)))
  • FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5

Definition at line 67 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of SMARTCARD Last Bit

Definition at line 94 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of SMARTCARD Clock Phase

Definition at line 91 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of SMARTCARD Clock Polarity

Definition at line 88 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::GuardTime

Specifies the SmartCard Guard Time value in terms of number of baud clocks

Definition at line 103 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

uint32_t SMARTCARD_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of SMARTCARD Mode

Definition at line 85 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::NACKState

Specifies the SmartCard NACK Transmission state This parameter can be a value of SMARTCARD NACK State

Definition at line 105 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of SMARTCARD Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 78 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::Prescaler

Specifies the SmartCard Prescaler value used for dividing the system clock to provide the smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency. This parameter can be a value of SMARTCARD Prescaler

Definition at line 98 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

uint32_t SMARTCARD_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of SMARTCARD Number of Stop Bits

Definition at line 75 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

uint32_t SMARTCARD_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of SMARTCARD Word Length

Definition at line 72 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_smartcard.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SMARTCARD_HandleTypeDef Struct Reference
SMARTCARD Exported Types

SMARTCARD handle Structure definition. More...

#include <stm32f1xx_hal_smartcard.h>

Data Fields

USART_TypeDef * | Instance
SMARTCARD_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SMARTCARD_StateTypeDef | gState
__IO HAL_SMARTCARD_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

SMARTCARD handle Structure definition.

Definition at line 172 of file stm32f1xx_hal_smartcard.h.

Field Documentation

__IO uint32_t SMARTCARD_HandleTypeDef::ErrorCode

SmartCard Error code

Definition at line 203 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetError(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::gState

SmartCard state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 196 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmarx

SmartCard Rx DMA Handle parameters

Definition at line 192 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

DMA_HandleTypeDef* SMARTCARD_HandleTypeDef::hdmatx

SmartCard Tx DMA Handle parameters

Definition at line 190 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Transmit_DMA(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

SMARTCARD_InitTypeDef SMARTCARD_HandleTypeDef::Init

SmartCard communication parameters

Definition at line 176 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init(), and SMARTCARD_SetConfig().

USART_TypeDef* SMARTCARD_HandleTypeDef::Instance

USART registers base address

Definition at line 174 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMATransmitCplt(), SMARTCARD_EndRxTransfer(), SMARTCARD_EndTransmit_IT(), SMARTCARD_EndTxTransfer(), SMARTCARD_Receive_IT(), SMARTCARD_SetConfig(), SMARTCARD_Transmit_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

HAL_LockTypeDef SMARTCARD_HandleTypeDef::Lock

Locking object

Definition at line 194 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

uint8_t* SMARTCARD_HandleTypeDef::pRxBuffPtr

Pointer to SmartCard Rx transfer Buffer

Definition at line 184 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), and SMARTCARD_Receive_IT().

uint8_t* SMARTCARD_HandleTypeDef::pTxBuffPtr

Pointer to SmartCard Tx transfer Buffer

Definition at line 178 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), and SMARTCARD_Transmit_IT().

__IO HAL_SMARTCARD_StateTypeDef SMARTCARD_HandleTypeDef::RxState

SmartCard state information related to Rx operations. This parameter can be a value of HAL_SMARTCARD_StateTypeDef

Definition at line 200 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_GetState(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_EndRxTransfer(), SMARTCARD_Receive_IT(), and SMARTCARD_WaitOnFlagUntilTimeout().

__IO uint16_t SMARTCARD_HandleTypeDef::RxXferCount

SmartCard Rx Transfer Counter

Definition at line 188 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortReceive(), HAL_SMARTCARD_AbortReceive_IT(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMAReceiveCplt(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMARxOnlyAbortCallback(), SMARTCARD_DMATxAbortCallback(), and SMARTCARD_Receive_IT().

uint16_t SMARTCARD_HandleTypeDef::RxXferSize

SmartCard Rx Transfer size

Definition at line 186 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), and HAL_SMARTCARD_Receive_IT().

__IO uint16_t SMARTCARD_HandleTypeDef::TxXferCount

SmartCard Tx Transfer Counter

Definition at line 182 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_AbortTransmit(), HAL_SMARTCARD_AbortTransmit_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMAAbortOnError(), SMARTCARD_DMAError(), SMARTCARD_DMARxAbortCallback(), SMARTCARD_DMATransmitCplt(), SMARTCARD_DMATxAbortCallback(), SMARTCARD_DMATxOnlyAbortCallback(), and SMARTCARD_Transmit_IT().

uint16_t SMARTCARD_HandleTypeDef::TxXferSize

SmartCard Tx Transfer size

Definition at line 180 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), and HAL_SMARTCARD_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_smartcard.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Error Code

Defines
SMARTCARD Error Code
SMARTCARD Exported constants

Defines

#define | HAL_SMARTCARD_ERROR_NONE 0x00000000U
#define | HAL_SMARTCARD_ERROR_PE 0x00000001U
#define | HAL_SMARTCARD_ERROR_NE 0x00000002U
#define | HAL_SMARTCARD_ERROR_FE 0x00000004U
#define | HAL_SMARTCARD_ERROR_ORE 0x00000008U
#define | HAL_SMARTCARD_ERROR_DMA 0x00000010U

Define Documentation

#define HAL_SMARTCARD_ERROR_DMA 0x00000010U

DMA transfer error

Definition at line 223 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_DMAError().

#define HAL_SMARTCARD_ERROR_FE 0x00000004U

Frame error

Definition at line 221 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NE 0x00000002U

Noise error

Definition at line 220 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_NONE 0x00000000U

No error

Definition at line 218 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Abort(), HAL_SMARTCARD_Abort_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Receive(), HAL_SMARTCARD_Receive_DMA(), HAL_SMARTCARD_Receive_IT(), HAL_SMARTCARD_Transmit(), HAL_SMARTCARD_Transmit_DMA(), HAL_SMARTCARD_Transmit_IT(), SMARTCARD_DMARxAbortCallback(), and SMARTCARD_DMATxAbortCallback().

#define HAL_SMARTCARD_ERROR_ORE 0x00000008U

OverRun error

Definition at line 222 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define HAL_SMARTCARD_ERROR_PE 0x00000001U

Parity error

Definition at line 219 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Word Length

Defines
SMARTCARD Word Length
SMARTCARD Exported constants

Defines

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Definition at line 231 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Number of Stop Bits

Defines
SMARTCARD Number of Stop Bits
SMARTCARD Exported constants

Defines

#define | SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Define Documentation

#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)

Definition at line 239 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Definition at line 240 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Parity

Defines
SMARTCARD Parity
SMARTCARD Exported constants

Defines

#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 248 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 249 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Mode

Defines
SMARTCARD Mode
SMARTCARD Exported constants

Defines

#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 257 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 258 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 259 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Clock Polarity

Defines
SMARTCARD Clock Polarity
SMARTCARD Exported constants

Defines

#define | SMARTCARD_POLARITY_LOW 0x00000000U
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Definition at line 268 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_POLARITY_LOW 0x00000000U

Definition at line 267 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Clock Phase

Defines
SMARTCARD Clock Phase
SMARTCARD Exported constants

Defines

#define | SMARTCARD_PHASE_1EDGE 0x00000000U
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define SMARTCARD_PHASE_1EDGE 0x00000000U

Definition at line 276 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Definition at line 277 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Last Bit

Defines
SMARTCARD Last Bit
SMARTCARD Exported constants

Defines

#define | SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define SMARTCARD_LASTBIT_DISABLE 0x00000000U

Definition at line 285 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Definition at line 286 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD NACK State

Defines
SMARTCARD NACK State
SMARTCARD Exported constants

Defines

#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE 0x00000000U

Define Documentation

#define SMARTCARD_NACK_DISABLE 0x00000000U

Definition at line 295 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)

Definition at line 294 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD DMA requests

Defines
SMARTCARD DMA requests
SMARTCARD Exported constants

Defines

#define | SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
#define | SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)

Define Documentation

#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)

Definition at line 304 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)

Definition at line 303 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Prescaler

Defines
SMARTCARD Prescaler
SMARTCARD Exported constants

Defines

#define | SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU

Define Documentation

#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U

SYSCLK divided by 10

Definition at line 316 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U

SYSCLK divided by 12

Definition at line 317 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U

SYSCLK divided by 14

Definition at line 318 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U

SYSCLK divided by 16

Definition at line 319 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U

SYSCLK divided by 18

Definition at line 320 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U

SYSCLK divided by 2

Definition at line 312 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU

SYSCLK divided by 20

Definition at line 321 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU

SYSCLK divided by 22

Definition at line 322 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU

SYSCLK divided by 24

Definition at line 323 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU

SYSCLK divided by 26

Definition at line 324 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU

SYSCLK divided by 28

Definition at line 325 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU

SYSCLK divided by 30

Definition at line 326 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U

SYSCLK divided by 32

Definition at line 327 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U

SYSCLK divided by 34

Definition at line 328 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U

SYSCLK divided by 36

Definition at line 329 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U

SYSCLK divided by 38

Definition at line 330 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U

SYSCLK divided by 4

Definition at line 313 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U

SYSCLK divided by 40

Definition at line 331 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U

SYSCLK divided by 42

Definition at line 332 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U

SYSCLK divided by 44

Definition at line 333 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U

SYSCLK divided by 46

Definition at line 334 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U

SYSCLK divided by 48

Definition at line 335 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U

SYSCLK divided by 50

Definition at line 336 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU

SYSCLK divided by 52

Definition at line 337 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU

SYSCLK divided by 54

Definition at line 338 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU

SYSCLK divided by 56

Definition at line 339 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU

SYSCLK divided by 58

Definition at line 340 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U

SYSCLK divided by 6

Definition at line 314 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU

SYSCLK divided by 60

Definition at line 341 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU

SYSCLK divided by 62

Definition at line 342 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U

SYSCLK divided by 8

Definition at line 315 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Flags

Defines
SMARTCARD Flags
SMARTCARD Exported constants

Elements values convention: 0xXXXX. More...

Defines

#define | SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define | SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)
#define | SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define | SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define | SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define | SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE)
#define | SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE)
#define | SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the SR register

Define Documentation

#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE)

Definition at line 358 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE)

Definition at line 355 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE)

Definition at line 357 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE)

Definition at line 356 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE)

Definition at line 359 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler().

#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)

Definition at line 354 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive().

#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)

Definition at line 353 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), HAL_SMARTCARD_Transmit(), and HAL_SMARTCARD_Transmit_DMA().

#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)

Definition at line 352 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_IRQHandler(), and HAL_SMARTCARD_Transmit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Interrupts Definition

Defines
SMARTCARD Interrupts Definition
SMARTCARD Exported constants

Elements values convention: 0xY000XXXX. More...

Defines

#define | SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Detailed Description

Elements values convention: 0xY000XXXX.

  • XXXX : Interrupt mask in the XX register
  • Y : Interrupt source register (2bits)
    • 01: CR1 register
    • 11: CR3 register

Define Documentation

#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Definition at line 377 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))

Definition at line 376 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))

Definition at line 372 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))

Definition at line 375 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))

Definition at line 374 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))

Definition at line 373 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Exported Macros

Defines
SMARTCARD Exported Macros
SMARTCARD

Defines

#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle gstate & RxState.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flush the Smartcard DR register.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified Smartcard pending flags.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
Checks whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
Macros to enable the SmartCard DMA request.
#define | __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
Macros to disable the SmartCard DMA request.

Define Documentation

#define __HAL_SMARTCARD_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)

Clear the SMARTCARD FE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 457 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clear the specified Smartcard pending flags.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • SMARTCARD_FLAG_TC: Transmission Complete flag.
  • SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
Note:
PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun error) flags are cleared by software sequence: a read operation to USART_SR register followed by a read operation to USART_DR register.
RXNE flag can be also cleared by a read to the USART_DR register.
TC flag can be also cleared by software sequence: a read operation to USART_SR register followed by a write operation to USART_DR register.
TXE flag is cleared only by a write to the USART_DR register.

Definition at line 439 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Transmit_DMA().

#define __HAL_SMARTCARD_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)

Clear the SMARTCARD IDLE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 475 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)

Clear the SMARTCARD NE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 463 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)

Clear the SMARTCARD ORE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 469 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Receive_DMA().

#define __HAL_SMARTCARD_CLEAR_PEFLAG ( __HANDLE__ )
Value:
do{                                                \
    __IO uint32_t tmpreg = 0x00U;                    \
    tmpreg = (__HANDLE__)->Instance->SR;             \
    tmpreg = (__HANDLE__)->Instance->DR;             \
    UNUSED(tmpreg);                                  \
  } while(0U)

Clear the SMARTCARD PE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 445 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 531 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
                                                                 ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))

Disable the specified SmartCard interrupt.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
__INTERRUPT__,: specifies the SMARTCARD interrupt to disable. This parameter can be one of the following values:
  • SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
  • SMARTCARD_IT_TC: Transmission complete interrupt
  • SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
  • SMARTCARD_IT_IDLE: Idle line detection interrupt
  • SMARTCARD_IT_PE: Parity Error interrupt
  • SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overRun error)

Definition at line 504 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE | ( | __HANDLE__,
 |  | __REQUEST__
 | ) | ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))

Macros to disable the SmartCard DMA request.

Parameters:
__HANDLE__,: specifies the SmartCard Handle.
__REQUEST__,: specifies the SmartCard DMA request. This parameter can be one of the following values:
  • SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
  • SMARTCARD_DMAREQ_RX: SmartCard DMA receive request

Definition at line 549 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE | ( | __HANDLE__,
 |  | __REQUEST__
 | ) | ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))

Macros to enable the SmartCard DMA request.

Parameters:
__HANDLE__,: specifies the SmartCard Handle.
__REQUEST__,: specifies the SmartCard DMA request. This parameter can be one of the following values:
  • SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
  • SMARTCARD_DMAREQ_RX: SmartCard DMA receive request

Definition at line 540 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable the USART associated to the SMARTCARD Handle.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 525 of file stm32f1xx_hal_smartcard.h.

Referenced by HAL_SMARTCARD_Init().

#define __HAL_SMARTCARD_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
                                                                 ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))

Enable the specified SmartCard interrupt.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
__INTERRUPT__,: specifies the SMARTCARD interrupt to enable. This parameter can be one of the following values:
  • SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
  • SMARTCARD_IT_TC: Transmission complete interrupt
  • SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
  • SMARTCARD_IT_IDLE: Idle line detection interrupt
  • SMARTCARD_IT_PE: Parity Error interrupt
  • SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overRun error)

Definition at line 489 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_FLUSH_DRREGISTER ( __HANDLE__ ) ((__HANDLE__)->Instance->DR)

Flush the Smartcard DR register.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 404 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified Smartcard flag is set or not.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SMARTCARD_FLAG_TXE: Transmit data register empty flag
  • SMARTCARD_FLAG_TC: Transmission Complete flag
  • SMARTCARD_FLAG_RXNE: Receive data register not empty flag
  • SMARTCARD_FLAG_IDLE: Idle Line detection flag
  • SMARTCARD_FLAG_ORE: OverRun Error flag
  • SMARTCARD_FLAG_NE: Noise Error flag
  • SMARTCARD_FLAG_FE: Framing Error flag
  • SMARTCARD_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 421 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_WaitOnFlagUntilTimeout().

#define __HAL_SMARTCARD_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) | (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))

Checks whether the specified SmartCard interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the SmartCard Handle.
__IT__,: specifies the SMARTCARD interrupt source to check. This parameter can be one of the following values:
  • SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
  • SMARTCARD_IT_TC: Transmission complete interrupt
  • SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
  • SMARTCARD_IT_IDLE: Idle line detection interrupt
  • SMARTCARD_IT_ERR: Error interrupt
  • SMARTCARD_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 519 of file stm32f1xx_hal_smartcard.h.

#define __HAL_SMARTCARD_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                        \
                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
                                                          } while(0U)

Reset SMARTCARD handle gstate & RxState.

Parameters:
__HANDLE__,: specifies the SMARTCARD Handle. SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 395 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Private Constants

Defines
SMARTCARD Private Constants
SMARTCARD

Defines

#define | SMARTCARD_IT_MASK 0x0000FFFFU
SMARTCARD interruptions flag mask.
#define | SMARTCARD_CR1_REG_INDEX 1U
#define | SMARTCARD_CR3_REG_INDEX 3U

Define Documentation

#define SMARTCARD_CR1_REG_INDEX 1U

Definition at line 626 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_CR3_REG_INDEX 3U

Definition at line 627 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_IT_MASK 0x0000FFFFU

SMARTCARD interruptions flag mask.

Definition at line 624 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Private Macros

Defines
SMARTCARD Private Macros
SMARTCARD

Defines

#define | IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
#define | IS_SMARTCARD_STOPBITS(STOPBITS)
#define | IS_SMARTCARD_PARITY(PARITY)
#define | IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
#define | IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
#define | IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
#define | IS_SMARTCARD_LASTBIT(LASTBIT)
#define | IS_SMARTCARD_NACK_STATE(NACK)
#define | IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
#define | SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
#define | SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | SMARTCARD_BRR(_PCLK_, _BAUD_)

Define Documentation

#define IS_SMARTCARD_BAUDRATE ( BAUDRATE ) ((BAUDRATE) < 4500001U)

Definition at line 648 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_LASTBIT ( LASTBIT )
Value:
(((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
                                       ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))

Definition at line 644 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_MODE ( MODE ) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))

Definition at line 641 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_NACK_STATE ( NACK )
Value:
(((NACK) == SMARTCARD_NACK_ENABLE) || \
                                       ((NACK) == SMARTCARD_NACK_DISABLE))

Definition at line 646 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PARITY ( PARITY )
Value:
(((PARITY) == SMARTCARD_PARITY_EVEN) || \
                                     ((PARITY) == SMARTCARD_PARITY_ODD))

Definition at line 639 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_PHASE ( CPHA ) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))

Definition at line 643 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_POLARITY ( CPOL ) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))

Definition at line 642 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_STOPBITS ( STOPBITS )
Value:
(((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
                                         ((STOPBITS) == SMARTCARD_STOPBITS_1_5))

Definition at line 637 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define IS_SMARTCARD_WORD_LENGTH ( LENGTH ) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)

Definition at line 636 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define SMARTCARD_BRR | ( | _PCLK_,
 |  | _BAUD_
 | ) |
Value:
(((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
                                                  (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
                                                  (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))

Definition at line 655 of file stm32f1xx_hal_smartcard.h.

Referenced by SMARTCARD_SetConfig().

#define SMARTCARD_DIV | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*25U)/(4U*(_BAUD_)))

Definition at line 650 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_DIVFRAQ | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)

Definition at line 652 of file stm32f1xx_hal_smartcard.h.

#define SMARTCARD_DIVMANT | ( | _PCLK_,
 |  | _BAUD_
 | ) | (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)

Definition at line 651 of file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SMARTCARD Private Functions

SMARTCARD Private Functions
SMARTCARD
Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Private Constants

Defines
SPI Private Constants
SPI

Defines

#define | SPI_DEFAULT_TIMEOUT 100U
#define | SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */
#define | SPI_VALID_CRC_ERROR 1U /* CRC error is true */

Define Documentation

#define SPI_DEFAULT_TIMEOUT 100U

Definition at line 172 of file stm32f1xx_hal_spi.c.

Referenced by HAL_SPI_Abort(), SPI_AbortRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */

Definition at line 488 of file stm32f1xx_hal_spi.h.

#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */

Definition at line 489 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), and SPI_ISCRCErrorValid().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
SPI Exported Functions

Initialization and Configuration functions. More...

Functions

__weak HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialize the SPIx peripheral:

      (+) User must implement HAL_SPI_MspInit() function in which he configures
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).

      (+) Call the function HAL_SPI_Init() to configure the selected device with
          the selected configuration:
        (++) Mode
        (++) Direction
        (++) Data Size
        (++) Clock Polarity and Phase
        (++) NSS Management
        (++) BaudRate Prescaler
        (++) FirstBit
        (++) TIMode
        (++) CRC Calculation
        (++) CRC Polynomial if CRC enabled

      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
          of the selected SPIx peripheral.

Function Documentation

HAL_StatusTypeDef HAL_SPI_DeInit ( SPI_HandleTypeDef * hspi )

De Initialize the SPI peripheral.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 342 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_MspDeInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

HAL_StatusTypeDef HAL_SPI_Init ( SPI_HandleTypeDef * hspi )

Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.

Initializes the SPI according to the specified parameters in the SPI_InitTypeDef and create the associated handle.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
HAL status

Definition at line 263 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE, assert_param, SPI_InitTypeDef::BaudRatePrescaler, SPI_InitTypeDef::CLKPhase, SPI_InitTypeDef::CLKPolarity, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::CRCPolynomial, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, SPI_InitTypeDef::FirstBit, HAL_SPI_ERROR_NONE, HAL_SPI_MspInit(), HAL_SPI_STATE_BUSY, HAL_SPI_STATE_READY, HAL_SPI_STATE_RESET, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_BAUDRATE_PRESCALER, IS_SPI_CPHA, IS_SPI_CPOL, IS_SPI_CRC_CALCULATION, IS_SPI_CRC_POLYNOMIAL, IS_SPI_DATASIZE, IS_SPI_DIRECTION, IS_SPI_FIRST_BIT, IS_SPI_MODE, IS_SPI_NSS, __SPI_HandleTypeDef::Lock, SPI_InitTypeDef::Mode, SPI_InitTypeDef::NSS, SPI_CRCCALCULATION_DISABLE, SPI_CRCCALCULATION_ENABLE, __SPI_HandleTypeDef::State, and SPI_InitTypeDef::TIMode.

void HAL_SPI_MspDeInit ( SPI_HandleTypeDef * hspi )

De-Initialize the SPI MSP.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 391 of file stm32f1xx_hal_spi.c.

Referenced by HAL_SPI_DeInit().

void HAL_SPI_MspInit ( SPI_HandleTypeDef * hspi )

Initialize the SPI MSP.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 376 of file stm32f1xx_hal_spi.c.

Referenced by HAL_SPI_Init().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
SPI Exported Functions

Data transfers functions. More...

Functions

HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.

Detailed Description

Data transfers functions.

  ==============================================================================
                      ##### IO operation functions #####
 ===============================================================================
 [..]
    This subsection provides a set of functions allowing to manage the SPI
    data transfers.

    [..] The SPI supports master and slave mode :

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode: The communication is performed using Interrupts
            or DMA, These APIs return the HAL status.
            The end of the data processing will be indicated through the
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
            will be executed respectively at the end of the transmit or Receive process
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected

    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
        exist for 1Line (simplex) and 2Lines (full duplex) modes.

Function Documentation

HAL_StatusTypeDef HAL_SPI_Abort ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (blocking mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SPI Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application before starting new SPI receive process.
Return values:
HAL status

Definition at line 1635 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DEFAULT_TIMEOUT, SPI_FLAG_TXE, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Abort_IT ( SPI_HandleTypeDef * hspi )

Abort ongoing transfer (Interrupt mode).

Parameters:
hspi SPI handle.
Note:
This procedure could be used for aborting any ongoing transfer (Tx and Rx), started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable SPI Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application before starting new SPI receive process.
Return values:
HAL status

Definition at line 1731 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_DMARxAbortCallback(), SPI_DMATxAbortCallback(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_SPI_AbortCpltCallback ( SPI_HandleTypeDef * hspi )

SPI Abort Complete callback.

Parameters:
hspi SPI handle.
Return values:
None

Definition at line 2143 of file stm32f1xx_hal_spi.c.

Referenced by HAL_SPI_Abort_IT(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

HAL_StatusTypeDef HAL_SPI_DMAPause ( SPI_HandleTypeDef * hspi )

Pause the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1876 of file stm32f1xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAResume ( SPI_HandleTypeDef * hspi )

Resume the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1896 of file stm32f1xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_SPI_DMAStop ( SPI_HandleTypeDef * hspi )

Stop the DMA Transfer.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
HAL status

Definition at line 1916 of file stm32f1xx_hal_spi.c.

References HAL_DMA_Abort(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

void HAL_SPI_ErrorCallback ( SPI_HandleTypeDef * hspi )

SPI error callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2126 of file stm32f1xx_hal_spi.c.

Referenced by HAL_SPI_IRQHandler(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAAbortOnError(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_IRQHandler ( SPI_HandleTypeDef * hspi )

Handle SPI interrupt request.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for the specified SPI module.
Return values:
None

Definition at line 1947 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_MODFFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_SPI_ERROR_MODF, HAL_SPI_ERROR_NONE, HAL_SPI_ERROR_OVR, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxISR, SPI_DMAAbortOnError(), SPI_FLAG_MODF, SPI_FLAG_OVR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_SPI_Receive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 616 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DIRECTION_2LINES_RXONLY, SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_ISCRCErrorValid(), SPI_MODE_MASTER, SPI_RESET_CRC, SPI_VALID_CRC_ERROR, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Receive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Note:
When the CRC feature is enabled the pData Length must be Size + 1.
Parameters:
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1416 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_ENABLE, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_DMA(), __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAReceiveCplt(), SPI_MODE_MASTER, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Receive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1145 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TransmitReceive_IT(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_RX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

void HAL_SPI_RxCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2051 of file stm32f1xx_hal_spi.c.

Referenced by SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), and SPI_DMAReceiveCplt().

void HAL_SPI_RxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Rx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2096 of file stm32f1xx_hal_spi.c.

Referenced by SPI_DMAHalfReceiveCplt().

HAL_StatusTypeDef HAL_SPI_Transmit | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 446 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CheckFlag_BSY(), SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_FLAG_TXE, SPI_MODE_SLAVE, SPI_RESET_CRC, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_Transmit_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1323 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DMAError(), SPI_DMAHalfTransmitCplt(), SPI_DMATransmitCplt(), SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_SPI_Transmit_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Transmit an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pData,: pointer to data buffer
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1055 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_TX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES_OR_1LINE, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_1LINE_TX, SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_TXE, SPI_RESET_CRC, SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

HAL_StatusTypeDef HAL_SPI_TransmitReceive | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Transmit and Receive an amount of data in blocking mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size,: amount of data to be sent and received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 823 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_ENABLE, __HAL_SPI_GET_FLAG, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CheckFlag_BSY(), SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_16BIT, SPI_DIRECTION_2LINES, SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_FLAG_TXE, SPI_ISCRCErrorValid(), SPI_MODE_MASTER, SPI_MODE_SLAVE, SPI_RESET_CRC, SPI_VALID_CRC_ERROR, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with DMA.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Note:
When the CRC feature is enabled the pRxData Length must be Size + 1
Parameters:
Size,: amount of data to be sent
Return values:
HAL status

Definition at line 1513 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_ENABLE, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_2LINES, SPI_DMAError(), SPI_DMAHalfReceiveCplt(), SPI_DMAHalfTransmitReceiveCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_MODE_MASTER, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, __SPI_HandleTypeDef::TxXferSize, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

Referenced by HAL_SPI_Receive_DMA().

HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT | ( | SPI_HandleTypeDef * | hspi,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Transmit and Receive an amount of data in non-blocking mode with Interrupt.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
pTxData,: pointer to transmission data buffer
pRxData,: pointer to reception data buffer
Size,: amount of data to be sent and received
Return values:
HAL status

Definition at line 1237 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_ENABLE, __HAL_SPI_ENABLE_IT, assert_param, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::DataSize, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_BUSY_TX_RX, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, IS_SPI_DIRECTION_2LINES, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::RxXferSize, SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CRCCALCULATION_ENABLE, SPI_DATASIZE_8BIT, SPI_DIRECTION_2LINES, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxISR, __SPI_HandleTypeDef::TxXferCount, and __SPI_HandleTypeDef::TxXferSize.

Referenced by HAL_SPI_Receive_IT().

void HAL_SPI_TxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2036 of file stm32f1xx_hal_spi.c.

Referenced by SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

void HAL_SPI_TxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx Half Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2081 of file stm32f1xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitCplt().

void HAL_SPI_TxRxCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Transfer completed callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2066 of file stm32f1xx_hal_spi.c.

Referenced by SPI_CloseRxTx_ISR(), and SPI_DMATransmitReceiveCplt().

void HAL_SPI_TxRxHalfCpltCallback ( SPI_HandleTypeDef * hspi )

Tx and Rx Half Transfer callback.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2111 of file stm32f1xx_hal_spi.c.

Referenced by SPI_DMAHalfTransmitReceiveCplt().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
SPI Exported Functions

SPI control functions. More...

Functions

HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.

Detailed Description

SPI control functions.

 ===============================================================================
                      ##### Peripheral State and Errors functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to control the SPI.
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication

Function Documentation

uint32_t HAL_SPI_GetError ( SPI_HandleTypeDef * hspi )

Return the SPI error code.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI error code in bitmap format

Definition at line 2190 of file stm32f1xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode.

HAL_SPI_StateTypeDef HAL_SPI_GetState ( SPI_HandleTypeDef * hspi )

Return the SPI handle state.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
SPI state

Definition at line 2178 of file stm32f1xx_hal_spi.c.

References __SPI_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Exported Types

Data Structures | Typedefs | Enumerations
SPI Exported Types
SPI

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U
}
HAL SPI State structure definition. More...

Typedef Documentation

typedef struct __SPI_HandleTypeDef SPI_HandleTypeDef

SPI handle Structure definition.

Enumeration Type Documentation

enum HAL_SPI_StateTypeDef

HAL SPI State structure definition.

Enumerator:
HAL_SPI_STATE_RESET

Peripheral not Initialized

HAL_SPI_STATE_READY

Peripheral Initialized and ready for use

HAL_SPI_STATE_BUSY

an internal process is ongoing

HAL_SPI_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_SPI_STATE_BUSY_RX

Data Reception process is ongoing

HAL_SPI_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing

HAL_SPI_STATE_ERROR

SPI error state

Definition at line 108 of file stm32f1xx_hal_spi.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
SPI_InitTypeDef Struct Reference
SPI Exported Types

SPI Configuration Structure definition. More...

#include <stm32f1xx_hal_spi.h>

Data Fields

uint32_t | Mode
uint32_t | Direction
uint32_t | DataSize
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | NSS
uint32_t | BaudRatePrescaler
uint32_t | FirstBit
uint32_t | TIMode
uint32_t | CRCCalculation
uint32_t | CRCPolynomial

Detailed Description

SPI Configuration Structure definition.

Definition at line 65 of file stm32f1xx_hal_spi.h.

Field Documentation

uint32_t SPI_InitTypeDef::BaudRatePrescaler

Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of SPI BaudRate Prescaler

Note:
The communication clock is derived from the master clock. The slave clock does not need to be set.

Definition at line 86 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPhase

Specifies the clock active edge for the bit capture. This parameter can be a value of SPI Clock Phase

Definition at line 79 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CLKPolarity

Specifies the serial clock steady state. This parameter can be a value of SPI Clock Polarity

Definition at line 76 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::CRCCalculation

Specifies if the CRC calculation is enabled or not. This parameter can be a value of SPI CRC Calculation

Definition at line 98 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::CRCPolynomial

Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0 and Max_Data = 65535

Definition at line 101 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::DataSize

Specifies the SPI data size. This parameter can be a value of SPI Data Size

Definition at line 73 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), and HAL_SPI_TransmitReceive_IT().

uint32_t SPI_InitTypeDef::Direction

Specifies the SPI Directional mode state. This parameter can be a value of SPI Direction Mode

Definition at line 70 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::FirstBit

Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of SPI MSB LSB Transmission

Definition at line 92 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::Mode

Specifies the SPI operating mode. This parameter can be a value of SPI Mode

Definition at line 67 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_DMAReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

uint32_t SPI_InitTypeDef::NSS

Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of SPI Slave Select Management

Definition at line 82 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint32_t SPI_InitTypeDef::TIMode

Specifies if the TI mode is enabled or not. This parameter can be a value of SPI TI Mode

Definition at line 95 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_spi.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: __SPI_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
__SPI_HandleTypeDef Struct Reference
SPI Exported Types

SPI handle Structure definition. More...

#include <stm32f1xx_hal_spi.h>

Data Fields

SPI_TypeDef * | Instance
SPI_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
void(* | RxISR )(struct __SPI_HandleTypeDef *hspi)
void(* | TxISR )(struct __SPI_HandleTypeDef *hspi)
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_SPI_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

SPI handle Structure definition.

Definition at line 122 of file stm32f1xx_hal_spi.h.

Field Documentation

__IO uint32_t __SPI_HandleTypeDef::ErrorCode

SPI Error code

Definition at line 152 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_GetError(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_AbortRx_ISR(), SPI_CheckFlag_BSY(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmarx

SPI Rx DMA Handle parameters

Definition at line 146 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Receive_DMA(), HAL_SPI_TransmitReceive_DMA(), and SPI_DMARxAbortCallback().

DMA_HandleTypeDef* __SPI_HandleTypeDef::hdmatx

SPI Tx DMA Handle parameters

Definition at line 144 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DMAStop(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit_DMA(), HAL_SPI_TransmitReceive_DMA(), SPI_DMARxAbortCallback(), and SPI_DMATxAbortCallback().

SPI_InitTypeDef __SPI_HandleTypeDef::Init

SPI communication parameters

Definition at line 126 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFlagStateUntilTimeout().

SPI_TypeDef* __SPI_HandleTypeDef::Instance

SPI registers base address

Definition at line 124 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAPause(), HAL_SPI_DMAResume(), HAL_SPI_DMAStop(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), SPI_RxISR_8BITCRC(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFlagStateUntilTimeout().

HAL_LockTypeDef __SPI_HandleTypeDef::Lock

Locking object

Definition at line 148 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

uint8_t* __SPI_HandleTypeDef::pRxBuffPtr

Pointer to SPI Rx transfer Buffer

Definition at line 134 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint8_t* __SPI_HandleTypeDef::pTxBuffPtr

Pointer to SPI Tx transfer Buffer

Definition at line 128 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

void(* __SPI_HandleTypeDef::RxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Rx ISR

Definition at line 140 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

__IO uint16_t __SPI_HandleTypeDef::RxXferCount

SPI Rx Transfer Counter

Definition at line 138 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), and SPI_RxISR_8BIT().

uint16_t __SPI_HandleTypeDef::RxXferSize

SPI Rx Transfer size

Definition at line 136 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO HAL_SPI_StateTypeDef __SPI_HandleTypeDef::State

SPI communication state

Definition at line 150 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_DMAStop(), HAL_SPI_GetState(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAError(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

void(* __SPI_HandleTypeDef::TxISR)(struct __SPI_HandleTypeDef *hspi)

function pointer on Tx ISR

Definition at line 142 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

__IO uint16_t __SPI_HandleTypeDef::TxXferCount

SPI Tx Transfer Counter

Definition at line 132 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAAbortOnError(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

uint16_t __SPI_HandleTypeDef::TxXferSize

SPI Tx Transfer size

Definition at line 130 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_spi.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Error Code

Defines
SPI Error Code
SPI Exported Constants

Defines

#define | HAL_SPI_ERROR_NONE 0x00000000U
#define | HAL_SPI_ERROR_MODF 0x00000001U
#define | HAL_SPI_ERROR_CRC 0x00000002U
#define | HAL_SPI_ERROR_OVR 0x00000004U
#define | HAL_SPI_ERROR_FRE 0x00000008U
#define | HAL_SPI_ERROR_DMA 0x00000010U
#define | HAL_SPI_ERROR_FLAG 0x00000020U

Define Documentation

#define HAL_SPI_ERROR_CRC 0x00000002U

CRC error

Definition at line 170 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define HAL_SPI_ERROR_DMA 0x00000010U

DMA transfer error

Definition at line 173 of file stm32f1xx_hal_spi.h.

Referenced by SPI_DMAError().

#define HAL_SPI_ERROR_FLAG 0x00000020U

Flag: RXNE,TXE, BSY

Definition at line 174 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_AbortRx_ISR(), SPI_CheckFlag_BSY(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_FRE 0x00000008U

FRE error

Definition at line 172 of file stm32f1xx_hal_spi.h.

#define HAL_SPI_ERROR_MODF 0x00000001U

MODF error

Definition at line 169 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define HAL_SPI_ERROR_NONE 0x00000000U

No error

Definition at line 168 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), SPI_DMATransmitCplt(), SPI_DMATransmitReceiveCplt(), and SPI_DMATxAbortCallback().

#define HAL_SPI_ERROR_OVR 0x00000004U

OVR error

Definition at line 171 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Mode

Defines
SPI Mode
SPI Exported Constants

Defines

#define | SPI_MODE_SLAVE 0x00000000U
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Define Documentation

#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)

Definition at line 183 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_DMAReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_MODE_SLAVE 0x00000000U

Definition at line 182 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Direction Mode

Defines
SPI Direction Mode
SPI Exported Constants

Defines

#define | SPI_DIRECTION_2LINES 0x00000000U
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Define Documentation

#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE

Definition at line 193 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), SPI_CloseRx_ISR(), SPI_DMAReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_DIRECTION_2LINES 0x00000000U

Definition at line 191 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), and SPI_DMATransmitCplt().

#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY

Definition at line 192 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), SPI_CloseRx_ISR(), SPI_DMAReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Data Size

Defines
SPI Data Size
SPI Exported Constants

Defines

#define | SPI_DATASIZE_8BIT 0x00000000U
#define | SPI_DATASIZE_16BIT SPI_CR1_DFF

Define Documentation

#define SPI_DATASIZE_16BIT SPI_CR1_DFF

Definition at line 202 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), and HAL_SPI_TransmitReceive().

#define SPI_DATASIZE_8BIT 0x00000000U

Definition at line 201 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Clock Polarity

Defines
SPI Clock Polarity
SPI Exported Constants

Defines

#define | SPI_POLARITY_LOW 0x00000000U
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL

Define Documentation

#define SPI_POLARITY_HIGH SPI_CR1_CPOL

Definition at line 211 of file stm32f1xx_hal_spi.h.

#define SPI_POLARITY_LOW 0x00000000U

Definition at line 210 of file stm32f1xx_hal_spi.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Clock Phase

Defines
SPI Clock Phase
SPI Exported Constants

Defines

#define | SPI_PHASE_1EDGE 0x00000000U
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA

Define Documentation

#define SPI_PHASE_1EDGE 0x00000000U

Definition at line 219 of file stm32f1xx_hal_spi.h.

#define SPI_PHASE_2EDGE SPI_CR1_CPHA

Definition at line 220 of file stm32f1xx_hal_spi.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Slave Select Management

Defines
SPI Slave Select Management
SPI Exported Constants

Defines

#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT 0x00000000U
#define | SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))

Define Documentation

#define SPI_NSS_HARD_INPUT 0x00000000U

Definition at line 229 of file stm32f1xx_hal_spi.h.

#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))

Definition at line 230 of file stm32f1xx_hal_spi.h.

#define SPI_NSS_SOFT SPI_CR1_SSM

Definition at line 228 of file stm32f1xx_hal_spi.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI BaudRate Prescaler

Defines
SPI BaudRate Prescaler
SPI Exported Constants

Defines

#define | SPI_BAUDRATEPRESCALER_2 0x00000000U
#define | SPI_BAUDRATEPRESCALER_4 SPI_CR1_BR_0
#define | SPI_BAUDRATEPRESCALER_8 SPI_CR1_BR_1
#define | SPI_BAUDRATEPRESCALER_16 (uint32_t)(SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_32 SPI_CR1_BR_2
#define | SPI_BAUDRATEPRESCALER_64 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_128 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_256 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Define Documentation

#define SPI_BAUDRATEPRESCALER_128 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1)

Definition at line 244 of file stm32f1xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_16 (uint32_t)(SPI_CR1_BR_1 | SPI_CR1_BR_0)

Definition at line 241 of file stm32f1xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_2 0x00000000U

Definition at line 238 of file stm32f1xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_256 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)

Definition at line 245 of file stm32f1xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_32 SPI_CR1_BR_2

Definition at line 242 of file stm32f1xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_4 SPI_CR1_BR_0

Definition at line 239 of file stm32f1xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_64 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_0)

Definition at line 243 of file stm32f1xx_hal_spi.h.

#define SPI_BAUDRATEPRESCALER_8 SPI_CR1_BR_1

Definition at line 240 of file stm32f1xx_hal_spi.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI MSB LSB Transmission

Defines
SPI MSB LSB Transmission
SPI Exported Constants

Defines

#define | SPI_FIRSTBIT_MSB 0x00000000U
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Define Documentation

#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST

Definition at line 255 of file stm32f1xx_hal_spi.h.

#define SPI_FIRSTBIT_MSB 0x00000000U

Definition at line 254 of file stm32f1xx_hal_spi.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI TI Mode

Defines
SPI TI Mode
SPI Exported Constants

Defines

#define SPI_TIMODE_DISABLE 0x00000000U

Define Documentation

#define SPI_TIMODE_DISABLE 0x00000000U

Definition at line 263 of file stm32f1xx_hal_spi.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI CRC Calculation

Defines
SPI CRC Calculation
SPI Exported Constants

Defines

#define | SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Define Documentation

#define SPI_CRCCALCULATION_DISABLE 0x00000000U

Definition at line 271 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN

Definition at line 272 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init(), HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_8BIT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), SPI_RxISR_16BIT(), SPI_RxISR_8BIT(), SPI_TxISR_16BIT(), SPI_TxISR_8BIT(), and SPI_WaitFlagStateUntilTimeout().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Interrupt Definition

Defines
SPI Interrupt Definition
SPI Exported Constants

Defines

#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE

Define Documentation

#define SPI_IT_ERR SPI_CR2_ERRIE

Definition at line 282 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_RxISR_16BITCRC(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_RXNE SPI_CR2_RXNEIE

Definition at line 281 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_CloseRx_ISR(), SPI_RxISR_16BITCRC(), and SPI_WaitFlagStateUntilTimeout().

#define SPI_IT_TXE SPI_CR2_TXEIE

Definition at line 280 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive_IT(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseTx_ISR(), and SPI_WaitFlagStateUntilTimeout().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Flags Definition

Defines
SPI Flags Definition
SPI Exported Constants

Defines

#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */

Define Documentation

#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */

Definition at line 292 of file stm32f1xx_hal_spi.h.

Referenced by SPI_CheckFlag_BSY().

#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */

Definition at line 293 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */

Definition at line 294 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */

Definition at line 295 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */

Definition at line 290 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */

Definition at line 291 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_AbortRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), and SPI_DMATxAbortCallback().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Exported Macros

Defines
SPI Exported Macros
SPI

Defines

#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
Disable the SPI peripheral.

Define Documentation

#define __HAL_SPI_CLEAR_CRCERRFLAG ( __HANDLE__ ) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))

Clear the SPI CRCERR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 372 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_CLEAR_MODFFLAG ( __HANDLE__ )
Value:
do{                                                \
    __IO uint32_t tmpreg_modf = 0x00U;             \
    tmpreg_modf = (__HANDLE__)->Instance->SR;      \
    (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
    UNUSED(tmpreg_modf);                           \
  } while(0U)

Clear the SPI MODF pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 379 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler().

#define __HAL_SPI_CLEAR_OVRFLAG ( __HANDLE__ )
Value:
do{                                                \
    __IO uint32_t tmpreg_ovr = 0x00U;              \
    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
    UNUSED(tmpreg_ovr);                            \
  } while(0U)

Clear the SPI OVR pending flag.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 392 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_Abort_IT(), HAL_SPI_IRQHandler(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMARxAbortCallback(), and SPI_DMATransmitCplt().

#define __HAL_SPI_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))

Disable the SPI peripheral.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 413 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Abort(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Receive(), SPI_AbortRx_ISR(), SPI_AbortTx_ISR(), SPI_CloseRx_ISR(), SPI_DMAReceiveCplt(), SPI_DMARxAbortCallback(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))

Disable the specified SPI interrupts.

Parameters:
__HANDLE__,: specifies the SPI handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__,: specifies the interrupt source to disable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 338 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_IRQHandler(), SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), SPI_2linesTxISR_8BIT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_RxISR_16BITCRC(), and SPI_WaitFlagStateUntilTimeout().

#define __HAL_SPI_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)

Enable the SPI peripheral.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 406 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))

Enable the specified SPI interrupts.

Parameters:
__HANDLE__,: specifies the SPI handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__,: specifies the interrupt source to enable. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
None

Definition at line 326 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive_IT(), HAL_SPI_Transmit_IT(), and HAL_SPI_TransmitReceive_IT().

#define __HAL_SPI_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

Check whether the specified SPI flag is set or not.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • SPI_FLAG_RXNE: Receive buffer not empty flag
  • SPI_FLAG_TXE: Transmit buffer empty flag
  • SPI_FLAG_CRCERR: CRC error flag
  • SPI_FLAG_MODF: Mode fault flag
  • SPI_FLAG_OVR: Overrun flag
  • SPI_FLAG_BSY: Busy flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 365 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

#define __HAL_SPI_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Check whether the specified SPI interrupt source is enabled or not.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
__INTERRUPT__,: specifies the SPI interrupt source to check. This parameter can be one of the following values:
  • SPI_IT_TXE: Tx buffer empty interrupt enable
  • SPI_IT_RXNE: RX buffer not empty interrupt enable
  • SPI_IT_ERR: Error interrupt enable
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 350 of file stm32f1xx_hal_spi.h.

#define __HAL_SPI_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)

Reset SPI handle state.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 314 of file stm32f1xx_hal_spi.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Private Macros

Defines
SPI Private Macros
SPI

Defines

#define | SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))

Define Documentation

#define IS_SPI_BAUDRATE_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

Definition at line 545 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPHA ( CPHA )
Value:
(((CPHA) == SPI_PHASE_1EDGE) || \
                           ((CPHA) == SPI_PHASE_2EDGE))

Definition at line 538 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CPOL ( CPOL )
Value:
(((CPOL) == SPI_POLARITY_LOW) || \
                           ((CPOL) == SPI_POLARITY_HIGH))

Definition at line 535 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_CALCULATION ( CALCULATION )
Value:
(((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))

Definition at line 557 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_CRC_POLYNOMIAL ( POLYNOMIAL ) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))

Definition at line 560 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DATASIZE ( DATASIZE )
Value:
(((DATASIZE) == SPI_DATASIZE_16BIT) || \
                                   ((DATASIZE) == SPI_DATASIZE_8BIT))

Definition at line 532 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES)        || \
                                ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
                                ((MODE) == SPI_DIRECTION_1LINE))

Definition at line 523 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_DIRECTION_2LINES ( MODE ) ((MODE) == SPI_DIRECTION_2LINES)

Definition at line 527 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), and HAL_SPI_TransmitReceive_IT().

#define IS_SPI_DIRECTION_2LINES_OR_1LINE ( MODE )
Value:
(((MODE) == SPI_DIRECTION_2LINES)  || \
                                                ((MODE) == SPI_DIRECTION_1LINE))

Definition at line 529 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define IS_SPI_FIRST_BIT ( BIT )
Value:
(((BIT) == SPI_FIRSTBIT_MSB) || \
                               ((BIT) == SPI_FIRSTBIT_LSB))

Definition at line 554 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_MODE ( MODE )
Value:
(((MODE) == SPI_MODE_SLAVE) || \
                           ((MODE) == SPI_MODE_MASTER))

Definition at line 520 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define IS_SPI_NSS ( NSS )
Value:
(((NSS) == SPI_NSS_SOFT)       || \
                         ((NSS) == SPI_NSS_HARD_INPUT) || \
                         ((NSS) == SPI_NSS_HARD_OUTPUT))

Definition at line 541 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Init().

#define SPI_1LINE_RX ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))

Set the SPI receive-only mode.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 510 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), and HAL_SPI_Receive_IT().

#define SPI_1LINE_TX ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)

Set the SPI transmit-only mode.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 503 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), and HAL_SPI_Transmit_IT().

#define SPI_RESET_CRC ( __HANDLE__ )
Value:
do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)

Reset the CRC calculation of the SPI.

Parameters:
__HANDLE__,: specifies the SPI Handle. This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Return values:
None

Definition at line 517 of file stm32f1xx_hal_spi.h.

Referenced by HAL_SPI_Receive(), HAL_SPI_Receive_DMA(), HAL_SPI_Receive_IT(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt(), and SPI_WaitFlagStateUntilTimeout().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Private Functions

Functions
SPI Private Functions
SPI

Private functions. More...

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_CheckFlag_BSY (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle to check BSY flag before start a new transaction.
uint8_t | SPI_ISCRCErrorValid (SPI_HandleTypeDef *hspi)
Checks if encountered CRC error could be corresponding to wrongly detected errors according to SPI instance, Device type, and revision ID.

Detailed Description

Private functions.

Function Documentation

static void SPI_2linesRxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2674 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_16BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2708 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), and SPI_IT_RXNE.

Referenced by SPI_2linesRxISR_16BIT().

static void SPI_2linesRxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2580 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_2linesRxISR_8BITCRC(), SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesRxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Rx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2614 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRxTx_ISR(), SPI_IT_ERR, SPI_IT_RXNE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by SPI_2linesRxISR_8BIT().

static void SPI_2linesTxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 16-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2732 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static void SPI_2linesTxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Tx 8-bit handler for Transmit and Receive in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2641 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRxTx_ISR(), SPI_CRCCALCULATION_ENABLE, SPI_IT_TXE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_IT().

static HAL_StatusTypeDef SPI_CheckFlag_BSY | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle to check BSY flag before start a new transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Timeout,: Timeout duration
Tickstart,: tick start value
Return values:
HAL status

Definition at line 2978 of file stm32f1xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, SPI_FLAG_BSY, and SPI_WaitFlagStateUntilTimeout().

Referenced by HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CloseRxTx_ISR(), SPI_CloseTx_ISR(), SPI_DMATransmitCplt(), and SPI_DMATransmitReceiveCplt().

static void SPI_CloseRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3080 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, SPI_InitTypeDef::Mode, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES, SPI_DIRECTION_2LINES_RXONLY, SPI_FLAG_CRCERR, SPI_ISCRCErrorValid(), SPI_IT_ERR, SPI_IT_RXNE, SPI_MODE_MASTER, SPI_RESET_CRC, SPI_VALID_CRC_ERROR, and __SPI_HandleTypeDef::State.

Referenced by SPI_RxISR_16BIT(), SPI_RxISR_16BITCRC(), SPI_RxISR_8BIT(), and SPI_RxISR_8BITCRC().

static void SPI_CloseRxTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the RXTX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2995 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_BUSY_RX, HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_CheckFlag_BSY(), SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_FLAG_CRCERR, SPI_FLAG_TXE, SPI_ISCRCErrorValid(), SPI_IT_ERR, SPI_RESET_CRC, SPI_VALID_CRC_ERROR, and __SPI_HandleTypeDef::State.

Referenced by SPI_2linesRxISR_16BIT(), SPI_2linesRxISR_16BITCRC(), SPI_2linesRxISR_8BIT(), SPI_2linesRxISR_8BITCRC(), SPI_2linesTxISR_16BIT(), and SPI_2linesTxISR_8BIT().

static void SPI_CloseTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle the end of the TX transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3140 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_CheckFlag_BSY(), SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, SPI_FLAG_TXE, SPI_IT_ERR, SPI_IT_TXE, and __SPI_HandleTypeDef::State.

Referenced by SPI_TxISR_16BIT(), and SPI_TxISR_8BIT().

static void SPI_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2467 of file stm32f1xx_hal_spi.c.

References HAL_SPI_ErrorCallback(), __SPI_HandleTypeDef::RxXferCount, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_IRQHandler().

static void SPI_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI communication error callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2449 of file stm32f1xx_hal_spi.c.

References __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_DMA, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Instance, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), HAL_SPI_Transmit_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2423 of file stm32f1xx_hal_spi.c.

References HAL_SPI_RxHalfCpltCallback().

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAHalfTransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2410 of file stm32f1xx_hal_spi.c.

References HAL_SPI_TxHalfCpltCallback().

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMAHalfTransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI half transmit receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2436 of file stm32f1xx_hal_spi.c.

References HAL_SPI_TxRxHalfCpltCallback().

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2259 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_DISABLE, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_RxCpltCallback(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, __SPI_HandleTypeDef::RxXferCount, SPI_CRCCALCULATION_ENABLE, SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_ISCRCErrorValid(), SPI_MODE_MASTER, SPI_RESET_CRC, SPI_VALID_CRC_ERROR, SPI_WaitFlagStateUntilTimeout(), and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive_DMA(), and HAL_SPI_TransmitReceive_DMA().

static void SPI_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2536 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmarx, __SPI_HandleTypeDef::hdmatx, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, __SPI_HandleTypeDef::State, __SPI_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

static void SPI_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2215 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_OVRFLAG, SPI_InitTypeDef::Direction, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, SPI_CheckFlag_BSY(), SPI_DEFAULT_TIMEOUT, SPI_DIRECTION_2LINES, __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_DMA().

static void SPI_DMATransmitReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI transmit receive process complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2336 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_CLEAR_CRCERRFLAG, __HAL_SPI_GET_FLAG, SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_SPI_ERROR_CRC, HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_ErrorCallback(), HAL_SPI_STATE_READY, HAL_SPI_TxRxCpltCallback(), __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, __SPI_HandleTypeDef::RxXferCount, SPI_CheckFlag_BSY(), SPI_CRCCALCULATION_ENABLE, SPI_DEFAULT_TIMEOUT, SPI_FLAG_CRCERR, SPI_FLAG_RXNE, SPI_ISCRCErrorValid(), SPI_RESET_CRC, SPI_VALID_CRC_ERROR, SPI_WaitFlagStateUntilTimeout(), __SPI_HandleTypeDef::State, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_TransmitReceive_DMA().

static void SPI_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2484 of file stm32f1xx_hal_spi.c.

References HAL_SPI_AbortCpltCallback(), HAL_SPI_ERROR_FLAG, HAL_SPI_ERROR_NONE, HAL_SPI_STATE_READY, __SPI_HandleTypeDef::hdmatx, SPI_DEFAULT_TIMEOUT, SPI_FLAG_TXE, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_SPI_Abort_IT().

uint8_t SPI_ISCRCErrorValid ( SPI_HandleTypeDef * hspi )

Checks if encountered CRC error could be corresponding to wrongly detected errors according to SPI instance, Device type, and revision ID.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
static void SPI_RxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the 16-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2844 of file stm32f1xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_16BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_16BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 16-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2821 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE_IT, __SPI_HandleTypeDef::Instance, SPI_CloseRx_ISR(), SPI_IT_ERR, and SPI_IT_RXNE.

Referenced by SPI_RxISR_16BIT().

static void SPI_RxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the receive 8-bit in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2788 of file stm32f1xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pRxBuffPtr, __SPI_HandleTypeDef::RxISR, __SPI_HandleTypeDef::RxXferCount, SPI_CloseRx_ISR(), SPI_CRCCALCULATION_ENABLE, and SPI_RxISR_8BITCRC().

Referenced by HAL_SPI_Receive_IT().

static void SPI_RxISR_8BITCRC ( struct __SPI_HandleTypeDef * hspi ) [static]

Manage the CRC 8-bit receive in Interrupt context.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2768 of file stm32f1xx_hal_spi.c.

References __SPI_HandleTypeDef::Instance, and SPI_CloseRx_ISR().

Referenced by SPI_RxISR_8BIT().

static void SPI_TxISR_16BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 16-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2901 of file stm32f1xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static void SPI_TxISR_8BIT ( struct __SPI_HandleTypeDef * hspi ) [static]

Handle the data 8-bit transmit in Interrupt mode.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 2877 of file stm32f1xx_hal_spi.c.

References SPI_InitTypeDef::CRCCalculation, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, __SPI_HandleTypeDef::pTxBuffPtr, SPI_CloseTx_ISR(), SPI_CRCCALCULATION_ENABLE, and __SPI_HandleTypeDef::TxXferCount.

Referenced by HAL_SPI_Transmit_IT().

static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout | ( | SPI_HandleTypeDef * | hspi,
 |  | uint32_t | Flag,
 |  | uint32_t | State,
 |  | uint32_t | Timeout,
 |  | uint32_t | Tickstart
 | ) |  | [static]

Handle SPI Communication Timeout.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Flag,: SPI flag to check
State,: flag state to check
Timeout,: Timeout duration
Tickstart,: tick start value
Return values:
HAL status

Definition at line 2931 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE, __HAL_SPI_DISABLE_IT, SPI_InitTypeDef::CRCCalculation, SPI_InitTypeDef::Direction, HAL_GetTick(), HAL_SPI_STATE_READY, __SPI_HandleTypeDef::Init, __SPI_HandleTypeDef::Instance, SPI_InitTypeDef::Mode, SPI_CRCCALCULATION_ENABLE, SPI_DIRECTION_1LINE, SPI_DIRECTION_2LINES_RXONLY, SPI_IT_ERR, SPI_IT_RXNE, SPI_IT_TXE, SPI_MODE_MASTER, SPI_RESET_CRC, and __SPI_HandleTypeDef::State.

Referenced by HAL_SPI_Receive(), HAL_SPI_Transmit(), HAL_SPI_TransmitReceive(), SPI_CheckFlag_BSY(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Private Variables

Variables
SPI Private Variables
SPI

Variables

uint8_t uCRCErrorWorkaroundCheck = 0U

Variable Documentation

uint8_t uCRCErrorWorkaroundCheck = 0U

Definition at line 70 of file stm32f1xx_hal_spi_ex.c.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI

Modules | Functions
SPI
STM32F1xx_HAL_Driver

SPI HAL module driver. More...

Modules

SPI Private Constants
SPI Exported Functions
SPI Exported Types
SPI Exported Constants
SPI Exported Macros
SPI Private Macros
SPI Private Functions

Private functions.

SPI Private Variables

Functions

__weak uint8_t | SPI_ISCRCErrorValid (SPI_HandleTypeDef *hspi)
Checks if encountered CRC error could be corresponding to wrongly detected errors according to SPI instance, Device type, and revision ID.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx transaction.

Detailed Description

SPI HAL module driver.

Function Documentation

static void SPI_AbortRx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Tx or Rx transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3195 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE, __SPI_HandleTypeDef::ErrorCode, HAL_SPI_ERROR_FLAG, __SPI_HandleTypeDef::Instance, SPI_DEFAULT_TIMEOUT, and SPI_FLAG_TXE.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

static void SPI_AbortTx_ISR ( SPI_HandleTypeDef * hspi ) [static]

Handle abort a Tx or Rx transaction.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
None

Definition at line 3230 of file stm32f1xx_hal_spi.c.

References __HAL_SPI_DISABLE, and __SPI_HandleTypeDef::Instance.

Referenced by HAL_SPI_Abort(), and HAL_SPI_Abort_IT().

uint8_t SPI_ISCRCErrorValid ( SPI_HandleTypeDef * hspi )

Checks if encountered CRC error could be corresponding to wrongly detected errors according to SPI instance, Device type, and revision ID.

Parameters:
hspi,: pointer to a SPI_HandleTypeDef structure that contains the configuration information for SPI module.
Return values:
CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).

Definition at line 3246 of file stm32f1xx_hal_spi.c.

References SPI_VALID_CRC_ERROR.

Referenced by HAL_SPI_Receive(), HAL_SPI_TransmitReceive(), SPI_CloseRx_ISR(), SPI_CloseRxTx_ISR(), SPI_DMAReceiveCplt(), and SPI_DMATransmitReceiveCplt().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Private Functions

Functions
TIM Private Functions
TIM

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 4 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Time Slave configuration.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Function Documentation

void TIM_Base_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_Base_InitTypeDef * | Structure
 | ) |  |

Time Base configuration.

Parameters:
TIMx | : TIM periheral
Structure | : TIM Base configuration structure
Return values:
None

Definition at line 4557 of file stm32f1xx_hal_tim.c.

References TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Base_InitTypeDef::Period, TIM_Base_InitTypeDef::Prescaler, and TIM_Base_InitTypeDef::RepetitionCounter.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

void TIM_CCxChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelState
 | ) |  |

Enables or disables the TIM Capture Compare Channel x.

Parameters:
TIMx | to select the TIM peripheral
Channel : specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
ChannelState | : specifies the TIM Channel CCxE bit new state. This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
Return values:
None

Definition at line 5352 of file stm32f1xx_hal_tim.c.

References assert_param, and IS_TIM_CHANNELS.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

void TIM_DMACaptureCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Capture complete callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4495 of file stm32f1xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), and HAL_TIMEx_HallSensor_Start_DMA().

void TIM_DMADelayPulseCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Delay Pulse complete callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4463 of file stm32f1xx_hal_tim.c.

References TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::State, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, and TIM_DMA_ID_CC4.

Referenced by HAL_TIM_DMABurst_WriteStart(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

void TIM_DMAError ( DMA_HandleTypeDef * hdma )

TIM DMA error callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4449 of file stm32f1xx_hal_tim.c.

References HAL_TIM_ErrorCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

static void TIM_DMAPeriodElapsedCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Period Elapse complete callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4528 of file stm32f1xx_hal_tim.c.

References HAL_TIM_PeriodElapsedCallback(), HAL_TIM_STATE_READY, and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

static void TIM_DMATriggerCplt ( DMA_HandleTypeDef * hdma ) [static]

TIM DMA Trigger callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 4542 of file stm32f1xx_hal_tim.c.

References HAL_TIM_STATE_READY, HAL_TIM_TriggerCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

static void TIM_ETR_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ExtTRGPrescaler,
 |  | uint32_t | TIM_ExtTRGPolarity,
 |  | uint32_t | ExtTRGFilter
 | ) |  | [static]

Configures the TIMx External Trigger (ETR).

Parameters:
TIMx | to select the TIM peripheral
TIM_ExtTRGPrescaler : The external Trigger Prescaler. This parameter can be one of the following values:
  • TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
  • TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
  • TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
  • TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
TIM_ExtTRGPolarity : The external Trigger Polarity. This parameter can be one of the following values:
  • TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
  • TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
ExtTRGFilter | : External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values:
None

Definition at line 5322 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), and TIM_SlaveTimer_SetConfig().

static void TIM_ITRx_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint16_t | InputTriggerSource
 | ) |  | [static]

Selects the Input Trigger source.

Parameters:
TIMx to select the TIM peripheral
InputTriggerSource : The Input Trigger source. This parameter can be one of the following values:
  • TIM_TS_ITR0 : Internal Trigger 0
  • TIM_TS_ITR1 : Internal Trigger 1
  • TIM_TS_ITR2 : Internal Trigger 2
  • TIM_TS_ITR3 : Internal Trigger 3
  • TIM_TS_TI1F_ED : TI1 Edge Detector
  • TIM_TS_TI1FP1 : Filtered Timer Input 1
  • TIM_TS_TI2FP2 : Filtered Timer Input 2
  • TIM_TS_ETRF : External Trigger input
Return values:
None

Definition at line 5292 of file stm32f1xx_hal_tim.c.

References TIM_SLAVEMODE_EXTERNAL1.

Referenced by HAL_TIM_ConfigClockSource().

static void TIM_OC1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Time Ouput Compare 1 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | : The ouput configuration structure
Return values:
None

Definition at line 4606 of file stm32f1xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_1.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

void TIM_OC2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  |

Time Ouput Compare 2 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | : The ouput configuration structure
Return values:
None

Definition at line 4680 of file stm32f1xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_2.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_OC3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Time Ouput Compare 3 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | : The ouput configuration structure
Return values:
None

Definition at line 4756 of file stm32f1xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, IS_TIM_OCN_POLARITY, IS_TIM_OCNIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, and TIM_CHANNEL_3.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_OC4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | TIM_OC_InitTypeDef * | OC_Config
 | ) |  | [static]

Time Ouput Compare 4 configuration.

Parameters:
TIMx | to select the TIM peripheral
OC_Config | : The ouput configuration structure
Return values:
None

Definition at line 4830 of file stm32f1xx_hal_tim.c.

References assert_param, IS_TIM_OCIDLE_STATE, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, and TIM_OC_InitTypeDef::Pulse.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

static void TIM_SlaveTimer_SetConfig | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  | [static]

Time Slave configuration.

Parameters:
htim,: pointer to a TIM_HandleTypeDef structure that contains the configuration information for TIM module.
sSlaveConfig,: The slave configuration structure
Return values:
None

Definition at line 4890 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_TRIGGERFILTER, IS_TIM_TRIGGERPOLARITY, IS_TIM_TRIGGERPRESCALER, TIM_SlaveConfigTypeDef::SlaveMode, TIM_ETR_SetConfig(), TIM_TI1_ConfigInputStage(), TIM_TI2_ConfigInputStage(), TIM_TS_ETRF, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIM_TS_TI1F_ED, TIM_TS_TI1FP1, TIM_TS_TI2FP2, TIM_SlaveConfigTypeDef::TriggerFilter, TIM_SlaveConfigTypeDef::TriggerPolarity, and TIM_SlaveConfigTypeDef::TriggerPrescaler.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

static void TIM_TI1_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI1.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
TIM_ICFilter | : Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5079 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

void TIM_TI1_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  |

Configure the TI1 as Input.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
TIM_ICSelection : specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
  • TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
TIM_ICFilter | : Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 (on channel2 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5033 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

static void TIM_TI2_ConfigInputStage | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the Polarity and Filter for TI2.

Parameters:
TIMx | to select the TIM peripheral.
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
TIM_ICFilter | : Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None

Definition at line 5160 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_SlaveTimer_SetConfig().

static void TIM_TI2_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI2 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
TIM_ICSelection : specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
  • TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
TIM_ICFilter | : Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 (on channel1 path) is used as the input signal. Therefore CCMR1 must be protected against un-initialized filter and polarity values.

Definition at line 5121 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel(), and HAL_TIM_OnePulse_ConfigChannel().

static void TIM_TI3_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI3 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
TIM_ICSelection : specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
  • TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
TIM_ICFilter | : Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values:
None
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.

Definition at line 5202 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

static void TIM_TI4_SetConfig | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | TIM_ICPolarity,
 |  | uint32_t | TIM_ICSelection,
 |  | uint32_t | TIM_ICFilter
 | ) |  | [static]

Configure the TI4 as Input.

Parameters:
TIMx | to select the TIM peripheral
TIM_ICPolarity : The Input Polarity. This parameter can be one of the following values:
  • TIM_ICPOLARITY_RISING
  • TIM_ICPOLARITY_FALLING
TIM_ICSelection : specifies the input to be used. This parameter can be one of the following values:
  • TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
  • TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
  • TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
TIM_ICFilter | : Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Note:
TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 (on channel1 path) is used as the input signal. Therefore CCMR2 must be protected against un-initialized filter and polarity values.
Return values:
None

Definition at line 5249 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IC_ConfigChannel().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Time Base functions

Functions
Time Base functions
TIM Exported Functions

Time Base functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.

Detailed Description

Time Base functions.

  ==============================================================================
              ##### Time Base functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM base.
    (+) De-initialize the TIM base.
    (+) Start the Time Base.
    (+) Stop the Time Base.
    (+) Start the Time Base and enable interrupt.
    (+) Stop the Time Base and disable interrupt.
    (+) Start the Time Base and enable DMA transfer.
    (+) Stop the Time Base and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Base_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Base peripheral.

Parameters:
htim : TIM Base handle
Return values:
HAL status

Definition at line 246 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Base_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim : TIM Base handle
Return values:
HAL status

Definition at line 206 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_Base_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Base_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Base MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 287 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_Base_DeInit().

void HAL_TIM_Base_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Base MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 273 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_Base_Init().

HAL_StatusTypeDef HAL_TIM_Base_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 302 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Base generation in DMA mode.

Parameters:
htim | : TIM handle
pData | : The source Buffer address.
Length | : The length of data to be transferred from memory to peripheral.
Return values:
HAL status

Definition at line 389 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_DMA_ID_UPDATE, TIM_DMA_UPDATE, TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Base_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Base generation in interrupt mode.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 348 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 325 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in DMA mode.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 433 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_Base_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Base generation in interrupt mode.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 368 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, and TIM_IT_UPDATE.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Time Output Compare functions

Functions
Time Output Compare functions
TIM Exported Functions

Time Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.

Detailed Description

Time Output Compare functions.

  ==============================================================================
                  ##### Time Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Output Compare.
    (+) De-initialize the TIM Output Compare.
    (+) Start the Time Output Compare.
    (+) Stop the Time Output Compare.
    (+) Start the Time Output Compare and enable interrupt.
    (+) Stop the Time Output Compare and disable interrupt.
    (+) Start the Time Output Compare and enable DMA transfer.
    (+) Stop the Time Output Compare and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim : TIM Output Compare handle
Return values:
HAL status

Definition at line 522 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim : TIM Output Compare handle
Return values:
HAL status

Definition at line 482 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Output Compare MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 563 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_OC_DeInit().

void HAL_TIM_OC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Output Compare MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 549 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_OC_Init().

HAL_StatusTypeDef HAL_TIM_OC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 583 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode.

Parameters:
htim | : TIM Output Compare handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | : The source Buffer address.
Length | : The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 781 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_OC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim : TIM OC handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 647 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 615 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 898 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_OC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 713 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Time PWM functions

Functions
Time PWM functions
TIM Exported Functions

Time PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.

Detailed Description

Time PWM functions.

  ==============================================================================
                          ##### Time PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM PWM.
    (+) De-initialize the TIM PWM.
    (+) Start the Time PWM.
    (+) Stop the Time PWM.
    (+) Start the Time PWM and enable interrupt.
    (+) Stop the Time PWM and disable interrupt.
    (+) Start the Time PWM and enable DMA transfer.
    (+) Stop the Time PWM and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_PWM_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 1027 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_PWM_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_PWM_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 987 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_PWM_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_PWM_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM PWM MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 1068 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_PWM_DeInit().

void HAL_TIM_PWM_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM PWM MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 1054 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_PWM_Init().

HAL_StatusTypeDef HAL_TIM_PWM_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation.

Parameters:
htim : TIM handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1088 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode.

Parameters:
htim | : TIM handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | : The source Buffer address.
Length | : The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1289 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_PWM_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters:
htim : TIM handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1155 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation.

Parameters:
htim : TIM handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1120 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode.

Parameters:
htim : TIM handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1406 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters:
htim : TIM handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1221 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Time Input Capture functions

Functions
Time Input Capture functions
TIM Exported Functions

Time Input Capture functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.

Detailed Description

Time Input Capture functions.

  ==============================================================================
              ##### Time Input Capture functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
   (+) Initialize and configure the TIM Input Capture.
   (+) De-initialize the TIM Input Capture.
   (+) Start the Time Input Capture.
   (+) Stop the Time Input Capture.
   (+) Start the Time Input Capture and enable interrupt.
   (+) Stop the Time Input Capture and disable interrupt.
   (+) Start the Time Input Capture and enable DMA transfer.
   (+) Stop the Time Input Capture and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_IC_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM peripheral.

Parameters:
htim : TIM Input Capture handle
Return values:
HAL status

Definition at line 1535 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_IC_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_Init ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim : TIM Input Capture handle
Return values:
HAL status

Definition at line 1495 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_IC_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_IC_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Input Capture MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 1576 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IC_DeInit().

void HAL_TIM_IC_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Input Capture MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 1562 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IC_Init().

HAL_StatusTypeDef HAL_TIM_IC_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement.

Parameters:
htim : TIM Input Capture handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1596 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Input Capture measurement in DMA mode.

Parameters:
htim | : TIM Input Capture handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | : The destination Buffer address.
Length | : The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 1769 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_IC_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Input Capture measurement in interrupt mode.

Parameters:
htim : TIM Input Capture handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1648 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement.

Parameters:
htim : TIM handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1622 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, and TIM_CCxChannelCmd().

HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in DMA mode.

Parameters:
htim : TIM Input Capture handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1882 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIM_IC_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Input Capture measurement in interrupt mode.

Parameters:
htim : TIM handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1707 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Time One Pulse functions

Functions
Time One Pulse functions
TIM Exported Functions

Time One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.

Detailed Description

Time One Pulse functions.

  ==============================================================================
                        ##### Time One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM One Pulse.
    (+) De-initialize the TIM One Pulse.
    (+) Start the Time One Pulse.
    (+) Stop the Time One Pulse.
    (+) Start the Time One Pulse and enable interrupt.
    (+) Stop the Time One Pulse and disable interrupt.
    (+) Start the Time One Pulse and enable DMA transfer.
    (+) Stop the Time One Pulse and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM One Pulse.

Parameters:
htim : TIM One Pulse handle
Return values:
HAL status

Definition at line 2016 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_OnePulse_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_OnePulse_Init | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OnePulseMode
 | ) |  |

Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.

Parameters:
htim : TIM OnePulse handle
OnePulseMode : Select the One pulse mode. This parameter can be one of the following values:
  • TIM_OPMODE_SINGLE: Only one pulse will be generated.
  • TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
Return values:
HAL status

Definition at line 1969 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_OnePulse_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_OPM_MODE, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_OnePulse_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM One Pulse MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 2057 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_DeInit().

void HAL_TIM_OnePulse_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM One Pulse MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 2043 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_OnePulse_Init().

HAL_StatusTypeDef HAL_TIM_OnePulse_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2075 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2141 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channels to be disable This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2108 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 2180 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Time Encoder functions

Functions
Time Encoder functions
TIM Exported Functions

Time Encoder functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.

Detailed Description

Time Encoder functions.

  ==============================================================================
                          ##### Time Encoder functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure the TIM Encoder.
    (+) De-initialize the TIM Encoder.
    (+) Start the Time Encoder.
    (+) Stop the Time Encoder.
    (+) Start the Time Encoder and enable interrupt.
    (+) Stop the Time Encoder and disable interrupt.
    (+) Start the Time Encoder and enable DMA transfer.
    (+) Stop the Time Encoder and disable DMA transfer.

Function Documentation

HAL_StatusTypeDef HAL_TIM_Encoder_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Encoder interface.

Parameters:
htim : TIM Encoder handle
Return values:
HAL status

Definition at line 2333 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_Encoder_MspDeInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_Encoder_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_Encoder_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Encoder Interface and create the associated handle.

Parameters:
htim | : TIM Encoder Interface handle
sConfig | : TIM Encoder Interface configuration structure
Return values:
HAL status

Definition at line 2240 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_Base_InitTypeDef::CounterMode, TIM_Encoder_InitTypeDef::EncoderMode, HAL_TIM_Encoder_MspInit(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, TIM_Encoder_InitTypeDef::IC1Filter, TIM_Encoder_InitTypeDef::IC1Polarity, TIM_Encoder_InitTypeDef::IC1Prescaler, TIM_Encoder_InitTypeDef::IC1Selection, TIM_Encoder_InitTypeDef::IC2Filter, TIM_Encoder_InitTypeDef::IC2Polarity, TIM_Encoder_InitTypeDef::IC2Prescaler, TIM_Encoder_InitTypeDef::IC2Selection, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_ENCODER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::Lock, TIM_HandleTypeDef::State, and TIM_Base_SetConfig().

void HAL_TIM_Encoder_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Encoder Interface MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 2374 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_DeInit().

void HAL_TIM_Encoder_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Encoder Interface MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 2360 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_Encoder_Init().

HAL_StatusTypeDef HAL_TIM_Encoder_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2393 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData1,
 |  | uint32_t * | pData2,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Encoder Interface in DMA mode.

Parameters:
htim | : TIM Encoder Interface handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
pData1 | : The destination Buffer address for IC1.
pData2 | : The destination Buffer address for IC2.
Length | : The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 2581 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_ALL, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Encoder Interface in interrupt mode.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2479 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2435 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_CHANNEL_2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in DMA mode.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2698 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_DMA_CC1, and TIM_DMA_CC2.

HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Encoder Interface in interrupt mode.

Parameters:
htim : TIM Encoder Interface handle
Channel : TIM Channels to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
Return values:
HAL status

Definition at line 2527 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_IT_CC1, and TIM_IT_CC2.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM IRQ handler management

Functions
TIM IRQ handler management
TIM Exported Functions

IRQ handler management. More...

Functions

void HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.

Detailed Description

IRQ handler management.

  ==============================================================================
                        ##### IRQ handler management #####
  ==============================================================================
  [..]
    This section provides Timer IRQ handler function.

Function Documentation

void HAL_TIM_IRQHandler ( TIM_HandleTypeDef * htim )

This function handles TIM interrupts requests.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 2760 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_CLEAR_IT, __HAL_TIM_GET_FLAG, __HAL_TIM_GET_IT_SOURCE, TIM_HandleTypeDef::Channel, HAL_TIM_ACTIVE_CHANNEL_1, HAL_TIM_ACTIVE_CHANNEL_2, HAL_TIM_ACTIVE_CHANNEL_3, HAL_TIM_ACTIVE_CHANNEL_4, HAL_TIM_ACTIVE_CHANNEL_CLEARED, HAL_TIM_IC_CaptureCallback(), HAL_TIM_OC_DelayElapsedCallback(), HAL_TIM_PeriodElapsedCallback(), HAL_TIM_PWM_PulseFinishedCallback(), HAL_TIM_TriggerCallback(), HAL_TIMEx_BreakCallback(), HAL_TIMEx_CommutationCallback(), TIM_HandleTypeDef::Instance, TIM_FLAG_BREAK, TIM_FLAG_CC1, TIM_FLAG_CC2, TIM_FLAG_CC3, TIM_FLAG_CC4, TIM_FLAG_COM, TIM_FLAG_TRIGGER, TIM_FLAG_UPDATE, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4, TIM_IT_COM, TIM_IT_TRIGGER, and TIM_IT_UPDATE.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
TIM Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                   ##### Peripheral Control functions #####
  ==============================================================================
 [..]
   This section provides functions allowing to:
      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
      (+) Configure External Clock source.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master and the Slave synchronization.
      (+) Configure the DMA Burst Mode.

Function Documentation

HAL_StatusTypeDef HAL_TIM_ConfigClockSource | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClockConfigTypeDef * | sClockSourceConfig
 | ) |  |

Configures the clock source to be used.

Parameters:
htim | : TIM handle
sClockSourceConfig | : pointer to a TIM_ClockConfigTypeDef structure that contains the clock source information for the TIM peripheral.
Return values:
HAL status

Definition at line 3909 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_ClockConfigTypeDef::ClockFilter, TIM_ClockConfigTypeDef::ClockPolarity, TIM_ClockConfigTypeDef::ClockPrescaler, TIM_ClockConfigTypeDef::ClockSource, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CLOCKFILTER, IS_TIM_CLOCKPOLARITY, IS_TIM_CLOCKPRESCALER, IS_TIM_CLOCKSOURCE, TIM_HandleTypeDef::State, TIM_CLOCKSOURCE_ETRMODE1, TIM_CLOCKSOURCE_ETRMODE2, TIM_CLOCKSOURCE_INTERNAL, TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ITR1, TIM_CLOCKSOURCE_ITR2, TIM_CLOCKSOURCE_ITR3, TIM_CLOCKSOURCE_TI1, TIM_CLOCKSOURCE_TI1ED, TIM_CLOCKSOURCE_TI2, TIM_ETR_SetConfig(), TIM_ITRx_SetConfig(), TIM_SLAVEMODE_EXTERNAL1, TIM_TI1_ConfigInputStage(), and TIM_TI2_ConfigInputStage().

HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_ClearInputConfigTypeDef * | sClearInputConfig,
 |  | uint32_t | Channel
 | ) |  |

Configures the OCRef clear feature.

Parameters:
htim | : TIM handle
sClearInputConfig | : pointer to a TIM_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIM peripheral.
Channel : specifies the TIM Channel This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1
  • TIM_CHANNEL_2: TIM Channel 2
  • TIM_CHANNEL_3: TIM Channel 3
  • TIM_CHANNEL_4: TIM Channel 4
Return values:
HAL status

Definition at line 3788 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_ClearInputConfigTypeDef::ClearInputFilter, TIM_ClearInputConfigTypeDef::ClearInputPolarity, TIM_ClearInputConfigTypeDef::ClearInputPrescaler, TIM_ClearInputConfigTypeDef::ClearInputSource, TIM_ClearInputConfigTypeDef::ClearInputState, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CLEARINPUT_FILTER, IS_TIM_CLEARINPUT_POLARITY, IS_TIM_CLEARINPUT_PRESCALER, IS_TIM_CLEARINPUT_SOURCE, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_CLEARINPUTSOURCE_ETR, TIM_CLEARINPUTSOURCE_NONE, and TIM_ETR_SetConfig().

HAL_StatusTypeDef HAL_TIM_ConfigTI1Input | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | TI1_Selection
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters:
htim : TIM handle.
TI1_Selection : Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
  • TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values:
HAL status

Definition at line 4083 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, and IS_TIM_TI1SELECTION.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.

Parameters:
htim | : TIM handle
BurstBaseAddress : TIM Base address from where the DMA will starts the Data read This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc : TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | : The Buffer address.
BurstLength | : DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Return values:
HAL status

Definition at line 3547 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMACaptureCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stop the DMA burst reading.

Parameters:
htim | : TIM handle
BurstRequestSrc | : TIM DMA Request sources to disable.
Return values:
HAL status

Definition at line 3679 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstBaseAddress,
 |  | uint32_t | BurstRequestSrc,
 |  | uint32_t * | BurstBuffer,
 |  | uint32_t | BurstLength
 | ) |  |

Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.

Parameters:
htim | : TIM handle
BurstBaseAddress : TIM Base address from where the DMA will start the Data write This parameter can be one of the following values:
  • TIM_DMABASE_CR1
  • TIM_DMABASE_CR2
  • TIM_DMABASE_SMCR
  • TIM_DMABASE_DIER
  • TIM_DMABASE_SR
  • TIM_DMABASE_EGR
  • TIM_DMABASE_CCMR1
  • TIM_DMABASE_CCMR2
  • TIM_DMABASE_CCER
  • TIM_DMABASE_CNT
  • TIM_DMABASE_PSC
  • TIM_DMABASE_ARR
  • TIM_DMABASE_RCR
  • TIM_DMABASE_CCR1
  • TIM_DMABASE_CCR2
  • TIM_DMABASE_CCR3
  • TIM_DMABASE_CCR4
  • TIM_DMABASE_BDTR
  • TIM_DMABASE_DCR
BurstRequestSrc : TIM DMA Request sources This parameter can be one of the following values:
  • TIM_DMA_UPDATE: TIM update Interrupt source
  • TIM_DMA_CC1: TIM Capture Compare 1 DMA source
  • TIM_DMA_CC2: TIM Capture Compare 2 DMA source
  • TIM_DMA_CC3: TIM Capture Compare 3 DMA source
  • TIM_DMA_CC4: TIM Capture Compare 4 DMA source
  • TIM_DMA_COM: TIM Commutation DMA source
  • TIM_DMA_TRIGGER: TIM Trigger DMA source
BurstBuffer | : The Buffer address.
BurstLength | : DMA Burst length. This parameter can be one value between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
Return values:
HAL status

Definition at line 3324 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_DMA_BASE, IS_TIM_DMA_LENGTH, IS_TIM_DMA_SOURCE, TIM_HandleTypeDef::State, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, TIM_DMA_UPDATE, TIM_DMADelayPulseCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | BurstRequestSrc
 | ) |  |

Stops the TIM DMA Burst mode.

Parameters:
htim | : TIM handle
BurstRequestSrc | : TIM DMA Request sources to disable
Return values:
HAL status

Definition at line 3455 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, assert_param, HAL_DMA_Abort(), TIM_HandleTypeDef::hdma, IS_TIM_DMA_SOURCE, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_COM, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMA_ID_COMMUTATION, TIM_DMA_ID_TRIGGER, TIM_DMA_ID_UPDATE, TIM_DMA_TRIGGER, and TIM_DMA_UPDATE.

HAL_StatusTypeDef HAL_TIM_GenerateEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | EventSource
 | ) |  |

Generate a software event.

Parameters:
htim : TIM handle
EventSource : specifies the event source. This parameter can be one of the following values:
  • TIM_EVENTSOURCE_UPDATE: Timer update Event source
  • TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
  • TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
  • TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
  • TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
  • TIM_EVENTSOURCE_COM: Timer COM event source
  • TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
  • TIM_EVENTSOURCE_BREAK: Timer Break event source
Note:
TIM6 and TIM7 can only generate an update event.
TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
Return values:
HAL status

Definition at line 3751 of file stm32f1xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_EVENT_SOURCE, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_IC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.

Parameters:
htim | : TIM IC handle
sConfig | : TIM Input Capture configuration structure
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2992 of file stm32f1xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_IC_InitTypeDef::ICFilter, TIM_IC_InitTypeDef::ICPolarity, TIM_IC_InitTypeDef::ICPrescaler, TIM_IC_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, IS_TIM_IC_SELECTION, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TI3_SetConfig(), and TIM_TI4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | : TIM Output Compare handle
sConfig | : TIM Output Compare configuration structure
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 2923 of file stm32f1xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_OC_MODE, IS_TIM_OC_POLARITY, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OnePulse_InitTypeDef * | sConfig,
 |  | uint32_t | OutputChannel,
 |  | uint32_t | InputChannel
 | ) |  |

Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.

Parameters:
htim | : TIM One Pulse handle
sConfig | : TIM One Pulse configuration structure
OutputChannel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
InputChannel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 3188 of file stm32f1xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_OnePulse_InitTypeDef::ICFilter, TIM_OnePulse_InitTypeDef::ICPolarity, TIM_OnePulse_InitTypeDef::ICSelection, TIM_HandleTypeDef::Instance, IS_TIM_OPM_CHANNELS, TIM_OC_InitTypeDef::OCIdleState, TIM_OnePulse_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OnePulse_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OnePulse_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OnePulse_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OnePulse_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_OnePulse_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_SLAVEMODE_TRIGGER, TIM_TI1_SetConfig(), TIM_TI2_SetConfig(), TIM_TS_TI1FP1, and TIM_TS_TI2FP2.

HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_OC_InitTypeDef * | sConfig,
 |  | uint32_t | Channel
 | ) |  |

Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.

Parameters:
htim | : TIM handle
sConfig | : TIM PWM configuration structure
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 3088 of file stm32f1xx_hal_tim.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_CHANNELS, IS_TIM_FAST_STATE, IS_TIM_OC_POLARITY, IS_TIM_PWM_MODE, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCPolarity, TIM_HandleTypeDef::State, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t HAL_TIM_ReadCapturedValue | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters:
htim : TIM handle.
Channel : TIM Channels to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1 : TIM Channel 1 selected
  • TIM_CHANNEL_2 : TIM Channel 2 selected
  • TIM_CHANNEL_3 : TIM Channel 3 selected
  • TIM_CHANNEL_4 : TIM Channel 4 selected
Return values:
Captured value

Definition at line 4188 of file stm32f1xx_hal_tim.c.

References assert_param, TIM_HandleTypeDef::Instance, TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, and TIM_CHANNEL_4.

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode.

Parameters:
htim | : TIM handle.
sSlaveConfig | : pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4115 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_DISABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_SlaveConfigTypeDef * | sSlaveConfig
 | ) |  |

Configures the TIM in Slave mode in interrupt mode.

Parameters:
htim,: TIM handle.
sSlaveConfig,: pointer to a TIM_SlaveConfigTypeDef structure that contains the selected trigger (internal trigger input, filtered timer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values:
HAL status

Definition at line 4150 of file stm32f1xx_hal_tim.c.

References __HAL_TIM_DISABLE_DMA, __HAL_TIM_ENABLE_IT, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_SlaveConfigTypeDef::InputTrigger, TIM_HandleTypeDef::Instance, IS_TIM_SLAVE_MODE, IS_TIM_TRIGGER_SELECTION, TIM_SlaveConfigTypeDef::SlaveMode, TIM_HandleTypeDef::State, TIM_DMA_TRIGGER, TIM_IT_TRIGGER, and TIM_SlaveTimer_SetConfig().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Callbacks functions

Functions
TIM Callbacks functions
TIM Exported Functions

TIM Callbacks functions. More...

Functions

__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.

Detailed Description

TIM Callbacks functions.

  ==============================================================================
                        ##### TIM Callbacks functions #####
  ==============================================================================
 [..]
   This section provides TIM callback functions:
   (+) Timer Period elapsed callback
   (+) Timer Output Compare callback
   (+) Timer Input capture callback
   (+) Timer Trigger callback
   (+) Timer Error callback

Function Documentation

void HAL_TIM_ErrorCallback ( TIM_HandleTypeDef * htim )

Timer error callback in non blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 4344 of file stm32f1xx_hal_tim.c.

Referenced by TIM_DMAError().

void HAL_TIM_IC_CaptureCallback ( TIM_HandleTypeDef * htim )

Input Capture callback in non blocking mode.

Parameters:
htim : TIM IC handle
Return values:
None

Definition at line 4302 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMACaptureCplt().

void HAL_TIM_OC_DelayElapsedCallback ( TIM_HandleTypeDef * htim )

Output Compare callback in non blocking mode.

Parameters:
htim : TIM OC handle
Return values:
None

Definition at line 4289 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIM_PeriodElapsedCallback ( TIM_HandleTypeDef * htim )

Period elapsed callback in non blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 4275 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMAPeriodElapsedCplt().

void HAL_TIM_PWM_PulseFinishedCallback ( TIM_HandleTypeDef * htim )

PWM Pulse finished callback in non blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 4316 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMADelayPulseCplt().

void HAL_TIM_TriggerCallback ( TIM_HandleTypeDef * htim )

Hall Trigger detection callback in non blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 4330 of file stm32f1xx_hal_tim.c.

Referenced by HAL_TIM_IRQHandler(), and TIM_DMATriggerCplt().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State functions

Functions
Peripheral State functions
TIM Exported Functions

Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.

Detailed Description

Peripheral State functions.

  ==============================================================================
                        ##### Peripheral State functions #####
  ==============================================================================
    [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIM_Base_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Base state.

Parameters:
htim : TIM Base handle
Return values:
HAL state

Definition at line 4377 of file stm32f1xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Encoder Mode state.

Parameters:
htim : TIM Encoder handle
Return values:
HAL state

Definition at line 4427 of file stm32f1xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_IC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Input Capture state.

Parameters:
htim : TIM IC handle
Return values:
HAL state

Definition at line 4407 of file stm32f1xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OC_GetState ( TIM_HandleTypeDef * htim )

Return the TIM OC state.

Parameters:
htim : TIM Ouput Compare handle
Return values:
HAL state

Definition at line 4387 of file stm32f1xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState ( TIM_HandleTypeDef * htim )

Return the TIM One Pulse Mode state.

Parameters:
htim : TIM OPM handle
Return values:
HAL state

Definition at line 4417 of file stm32f1xx_hal_tim.c.

References TIM_HandleTypeDef::State.

HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState ( TIM_HandleTypeDef * htim )

Return the TIM PWM state.

Parameters:
htim : TIM handle
Return values:
HAL state

Definition at line 4397 of file stm32f1xx_hal_tim.c.

References TIM_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Exported Types

Data Structures | Enumerations
TIM Exported Types
TIM

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
TIM Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...

Enumeration Type Documentation

enum HAL_TIM_ActiveChannel

HAL Active channel structures definition.

Enumerator:
HAL_TIM_ACTIVE_CHANNEL_1

The active channel is 1

HAL_TIM_ACTIVE_CHANNEL_2

The active channel is 2

HAL_TIM_ACTIVE_CHANNEL_3

The active channel is 3

HAL_TIM_ACTIVE_CHANNEL_4

The active channel is 4

HAL_TIM_ACTIVE_CHANNEL_CLEARED

All active channels cleared

Definition at line 277 of file stm32f1xx_hal_tim.h.

enum HAL_TIM_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_TIM_STATE_RESET

Peripheral not yet initialized or disabled

HAL_TIM_STATE_READY

Peripheral Initialized and ready for use

HAL_TIM_STATE_BUSY

An internal process is ongoing

HAL_TIM_STATE_TIMEOUT

Timeout state

HAL_TIM_STATE_ERROR

Reception process is ongoing

Definition at line 265 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_Base_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Base_InitTypeDef Struct Reference
TIM Exported Types

TIM Time base Configuration Structure definition. More...

#include <stm32f1xx_hal_tim.h>

Data Fields

uint32_t | Prescaler
uint32_t | CounterMode
uint32_t | Period
uint32_t | ClockDivision
uint32_t | RepetitionCounter
uint32_t | AutoReloadPreload

Detailed Description

TIM Time base Configuration Structure definition.

Definition at line 64 of file stm32f1xx_hal_tim.h.

Field Documentation

uint32_t TIM_Base_InitTypeDef::AutoReloadPreload

Specifies the auto-reload preload. This parameter can be a value of TIM Auto-Reload Preload

Definition at line 88 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::ClockDivision

Specifies the clock division. This parameter can be a value of TIM ClockDivision

Definition at line 76 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::CounterMode

Specifies the counter mode. This parameter can be a value of TIM Counter Mode

Definition at line 69 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), HAL_TIMEx_HallSensor_Init(), and TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Period

Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

Definition at line 72 of file stm32f1xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::Prescaler

Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 66 of file stm32f1xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

uint32_t TIM_Base_InitTypeDef::RepetitionCounter

Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to:

  • the number of PWM periods in edge-aligned mode
  • the number of half PWM period in center-aligned mode This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
    Note:
    This parameter is valid only for TIM1 and TIM8.

Definition at line 79 of file stm32f1xx_hal_tim.h.

Referenced by TIM_Base_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_OC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OC_InitTypeDef Struct Reference
TIM Exported Types

TIM Output Compare Configuration Structure definition. More...

#include <stm32f1xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCFastMode
uint32_t | OCIdleState
uint32_t | OCNIdleState

Detailed Description

TIM Output Compare Configuration Structure definition.

Definition at line 95 of file stm32f1xx_hal_tim.h.

Field Documentation

uint32_t TIM_OC_InitTypeDef::OCFastMode

Specifies the Fast mode state. This parameter can be a value of TIM Output Fast State

Note:
This parameter is valid only in PWM1 and PWM2 mode.

Definition at line 110 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

uint32_t TIM_OC_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 115 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM modes

Definition at line 97 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 119 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 106 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

uint32_t TIM_OC_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 103 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

uint32_t TIM_OC_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 100 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), HAL_TIMEx_HallSensor_Init(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_OnePulse_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_OnePulse_InitTypeDef Struct Reference
TIM Exported Types

TIM One Pulse Mode Configuration Structure definition. More...

#include <stm32f1xx_hal_tim.h>

Data Fields

uint32_t | OCMode
uint32_t | Pulse
uint32_t | OCPolarity
uint32_t | OCNPolarity
uint32_t | OCIdleState
uint32_t | OCNIdleState
uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICFilter

Detailed Description

TIM One Pulse Mode Configuration Structure definition.

Definition at line 127 of file stm32f1xx_hal_tim.h.

Field Documentation

uint32_t TIM_OnePulse_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 156 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 150 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 153 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 142 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCMode

Specifies the TIM mode. This parameter can be a value of TIM Output Compare and PWM modes

Definition at line 129 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNIdleState

Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of TIM Complementary Output Compare Idle State

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 146 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCNPolarity

Specifies the complementary output polarity. This parameter can be a value of TIM Complementary Output Compare Polarity

Note:
This parameter is valid only for TIM1 and TIM8.

Definition at line 138 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::OCPolarity

Specifies the output polarity. This parameter can be a value of TIM Output Compare Polarity

Definition at line 135 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

uint32_t TIM_OnePulse_InitTypeDef::Pulse

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 132 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_IC_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_IC_InitTypeDef Struct Reference
TIM Exported Types

TIM Input Capture Configuration Structure definition. More...

#include <stm32f1xx_hal_tim.h>

Data Fields

uint32_t | ICPolarity
uint32_t | ICSelection
uint32_t | ICPrescaler
uint32_t | ICFilter

Detailed Description

TIM Input Capture Configuration Structure definition.

Definition at line 164 of file stm32f1xx_hal_tim.h.

Field Documentation

uint32_t TIM_IC_InitTypeDef::ICFilter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 175 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPolarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 166 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICPrescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 172 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

uint32_t TIM_IC_InitTypeDef::ICSelection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 169 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IC_ConfigChannel().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_Encoder_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_Encoder_InitTypeDef Struct Reference
TIM Exported Types

TIM Encoder Configuration Structure definition. More...

#include <stm32f1xx_hal_tim.h>

Data Fields

uint32_t | EncoderMode
uint32_t | IC1Polarity
uint32_t | IC1Selection
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | IC2Polarity
uint32_t | IC2Selection
uint32_t | IC2Prescaler
uint32_t | IC2Filter

Detailed Description

TIM Encoder Configuration Structure definition.

Definition at line 182 of file stm32f1xx_hal_tim.h.

Field Documentation

uint32_t TIM_Encoder_InitTypeDef::EncoderMode

Specifies the active edge of the input signal. This parameter can be a value of TIM Encoder Mode

Definition at line 184 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 196 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 187 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 193 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC1Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 190 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 208 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 199 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 205 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

uint32_t TIM_Encoder_InitTypeDef::IC2Selection

Specifies the input. This parameter can be a value of TIM Input Capture Selection

Definition at line 202 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_ClockConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClockConfigTypeDef Struct Reference
TIM Exported Types

TIM Clock Configuration Handle Structure definition. More...

#include <stm32f1xx_hal_tim.h>

Data Fields

uint32_t | ClockSource
uint32_t | ClockPolarity
uint32_t | ClockPrescaler
uint32_t | ClockFilter

Detailed Description

TIM Clock Configuration Handle Structure definition.

Definition at line 216 of file stm32f1xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClockConfigTypeDef::ClockFilter

TIM clock filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 224 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPolarity

TIM clock polarity This parameter can be a value of TIM Clock Polarity

Definition at line 220 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockPrescaler

TIM clock prescaler This parameter can be a value of TIM Clock Prescaler

Definition at line 222 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

uint32_t TIM_ClockConfigTypeDef::ClockSource

TIM clock sources This parameter can be a value of TIM Clock Source

Definition at line 218 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_ClearInputConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_ClearInputConfigTypeDef Struct Reference
TIM Exported Types

TIM Clear Input Configuration Handle Structure definition. More...

#include <stm32f1xx_hal_tim.h>

Data Fields

uint32_t | ClearInputState
uint32_t | ClearInputSource
uint32_t | ClearInputPolarity
uint32_t | ClearInputPrescaler
uint32_t | ClearInputFilter

Detailed Description

TIM Clear Input Configuration Handle Structure definition.

Definition at line 231 of file stm32f1xx_hal_tim.h.

Field Documentation

uint32_t TIM_ClearInputConfigTypeDef::ClearInputFilter

TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 241 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPolarity

TIM Clear Input polarity This parameter can be a value of TIM Clear Input Polarity

Definition at line 237 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputPrescaler

TIM Clear Input prescaler This parameter can be a value of TIM Clear Input Prescaler

Definition at line 239 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputSource

TIM clear Input sources This parameter can be a value of TIM ClearInput Source

Definition at line 235 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

uint32_t TIM_ClearInputConfigTypeDef::ClearInputState

TIM clear Input state This parameter can be ENABLE or DISABLE

Definition at line 233 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_SlaveConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_SlaveConfigTypeDef Struct Reference
TIM Exported Types

TIM Slave configuration Structure definition. More...

#include <stm32f1xx_hal_tim.h>

Data Fields

uint32_t | SlaveMode
uint32_t | InputTrigger
uint32_t | TriggerPolarity
uint32_t | TriggerPrescaler
uint32_t | TriggerFilter

Detailed Description

TIM Slave configuration Structure definition.

Definition at line 248 of file stm32f1xx_hal_tim.h.

Field Documentation

uint32_t TIM_SlaveConfigTypeDef::InputTrigger

Input Trigger source This parameter can be a value of TIM Trigger Selection

Definition at line 251 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::SlaveMode

Slave mode selection This parameter can be a value of TIM Slave Mode

Definition at line 249 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), and TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerFilter

Input trigger filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 257 of file stm32f1xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPolarity

Input Trigger polarity This parameter can be a value of TIM Trigger Polarity

Definition at line 253 of file stm32f1xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

uint32_t TIM_SlaveConfigTypeDef::TriggerPrescaler

Input trigger prescaler This parameter can be a value of TIM Trigger Prescaler

Definition at line 255 of file stm32f1xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HandleTypeDef Struct Reference
TIM Exported Types

TIM Time Base Handle Structure definition. More...

#include <stm32f1xx_hal_tim.h>

Data Fields

TIM_TypeDef * | Instance
TIM_Base_InitTypeDef Init
HAL_TIM_ActiveChannel Channel
DMA_HandleTypeDef * | hdma [7U]
HAL_LockTypeDef | Lock
__IO HAL_TIM_StateTypeDef | State

Detailed Description

TIM Time Base Handle Structure definition.

Definition at line 289 of file stm32f1xx_hal_tim.h.

Field Documentation

HAL_TIM_ActiveChannel TIM_HandleTypeDef::Channel

Active channel

Definition at line 293 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

DMA_HandleTypeDef* TIM_HandleTypeDef::hdma[7U]

DMA Handlers array This array is accessed by a TIM DMA Handle Index

Definition at line 294 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

TIM_Base_InitTypeDef TIM_HandleTypeDef::Init

TIM Time Base required parameters

Definition at line 292 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

TIM_TypeDef* TIM_HandleTypeDef::Instance

Register base address

Definition at line 291 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_SlaveTimer_SetConfig().

HAL_LockTypeDef TIM_HandleTypeDef::Lock

Locking object

Definition at line 296 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

__IO HAL_TIM_StateTypeDef TIM_HandleTypeDef::State

TIM operation state

Definition at line 297 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_GetState(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_GetState(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_GetState(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_GetState(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_GetState(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_GetState(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_GetState(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Stop_DMA(), TIM_DMACaptureCplt(), TIM_DMADelayPulseCplt(), TIM_DMAError(), TIM_DMAPeriodElapsedCplt(), TIM_DMATriggerCplt(), and TIMEx_DMACommutationCplt().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim.h
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STM32F103xB HAL User Manual: TIM Input Channel Polarity

Defines
TIM Input Channel Polarity
TIM Exported Constants

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Define Documentation

#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)

Polarity for TIx source

Definition at line 314 of file stm32f1xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)

Polarity for TIx source

Definition at line 313 of file stm32f1xx_hal_tim.h.

#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U

Polarity for TIx source

Definition at line 312 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM ETR Polarity

Defines
TIM ETR Polarity
TIM Exported Constants

Defines

#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U

Define Documentation

#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)

Polarity for ETR source

Definition at line 322 of file stm32f1xx_hal_tim.h.

#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U

Polarity for ETR source

Definition at line 323 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM ETR Prescaler

Defines
TIM ETR Prescaler
TIM Exported Constants

Defines

#define | TIM_ETRPRESCALER_DIV1 0x00000000U
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

Define Documentation

#define TIM_ETRPRESCALER_DIV1 0x00000000U

No prescaler is used

Definition at line 331 of file stm32f1xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)

ETR input source is divided by 2

Definition at line 332 of file stm32f1xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)

ETR input source is divided by 4

Definition at line 333 of file stm32f1xx_hal_tim.h.

#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)

ETR input source is divided by 8

Definition at line 334 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Counter Mode

Defines
TIM Counter Mode
TIM Exported Constants

Defines

#define | TIM_COUNTERMODE_UP 0x00000000U
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Define Documentation

#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0

Definition at line 344 of file stm32f1xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1

Definition at line 345 of file stm32f1xx_hal_tim.h.

#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS

Definition at line 346 of file stm32f1xx_hal_tim.h.

#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR

Definition at line 343 of file stm32f1xx_hal_tim.h.

#define TIM_COUNTERMODE_UP 0x00000000U

Definition at line 342 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM ClockDivision

Defines
TIM ClockDivision
TIM Exported Constants

Defines

#define | TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Define Documentation

#define TIM_CLOCKDIVISION_DIV1 0x00000000U

Definition at line 354 of file stm32f1xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)

Definition at line 355 of file stm32f1xx_hal_tim.h.

#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)

Definition at line 356 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Auto-Reload Preload

Defines
TIM Auto-Reload Preload
TIM Exported Constants

Defines

#define | TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U
#define | TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE)

Define Documentation

#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U

TIMx_ARR register is not buffered

Definition at line 364 of file stm32f1xx_hal_tim.h.

#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE)

TIMx_ARR register is buffered

Definition at line 365 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Output Compare and PWM modes

Defines
TIM Output Compare and PWM modes
TIM Exported Constants

Defines

#define | TIM_OCMODE_TIMING 0x00000000U
#define | TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)

Define Documentation

#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)

Definition at line 374 of file stm32f1xx_hal_tim.h.

#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)

Definition at line 379 of file stm32f1xx_hal_tim.h.

#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)

Definition at line 380 of file stm32f1xx_hal_tim.h.

#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)

Definition at line 375 of file stm32f1xx_hal_tim.h.

#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)

Definition at line 377 of file stm32f1xx_hal_tim.h.

#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)

Definition at line 378 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCMODE_TIMING 0x00000000U

Definition at line 373 of file stm32f1xx_hal_tim.h.

#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)

Definition at line 376 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Output Compare State

Defines
TIM Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)

Define Documentation

#define TIM_OUTPUTSTATE_DISABLE 0x00000000U

Definition at line 388 of file stm32f1xx_hal_tim.h.

#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)

Definition at line 389 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Output Fast State

Defines
TIM Output Fast State
TIM Exported Constants

Defines

#define | TIM_OCFAST_DISABLE 0x00000000U
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Define Documentation

#define TIM_OCFAST_DISABLE 0x00000000U

Definition at line 397 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)

Definition at line 398 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Complementary Output Compare State

Defines
TIM Complementary Output Compare State
TIM Exported Constants

Defines

#define | TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)

Define Documentation

#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U

Definition at line 406 of file stm32f1xx_hal_tim.h.

#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)

Definition at line 407 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Output Compare Polarity

Defines
TIM Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCPOLARITY_HIGH 0x00000000U
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Define Documentation

#define TIM_OCPOLARITY_HIGH 0x00000000U

Definition at line 415 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)

Definition at line 416 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Complementary Output Compare Polarity

Defines
TIM Complementary Output Compare Polarity
TIM Exported Constants

Defines

#define | TIM_OCNPOLARITY_HIGH 0x00000000U
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Define Documentation

#define TIM_OCNPOLARITY_HIGH 0x00000000U

Definition at line 424 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)

Definition at line 425 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Output Compare Idle State

Defines
TIM Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET 0x00000000U

Define Documentation

#define TIM_OCIDLESTATE_RESET 0x00000000U

Definition at line 434 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)

Definition at line 433 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Complementary Output Compare Idle State

Defines
TIM Complementary Output Compare Idle State
TIM Exported Constants

Defines

#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET 0x00000000U

Define Documentation

#define TIM_OCNIDLESTATE_RESET 0x00000000U

Definition at line 443 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)

Definition at line 442 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Channel

Defines
TIM Channel
TIM Exported Constants

Defines

#define | TIM_CHANNEL_1 0x00000000U
#define | TIM_CHANNEL_2 0x00000004U
#define | TIM_CHANNEL_3 0x00000008U
#define | TIM_CHANNEL_4 0x0000000CU
#define | TIM_CHANNEL_ALL 0x00000018U

Define Documentation

#define TIM_CHANNEL_1 0x00000000U

Definition at line 451 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC1_SetConfig().

#define TIM_CHANNEL_2 0x00000004U

Definition at line 452 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC2_SetConfig().

#define TIM_CHANNEL_3 0x00000008U

Definition at line 453 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), and TIM_OC3_SetConfig().

#define TIM_CHANNEL_4 0x0000000CU

Definition at line 454 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CHANNEL_ALL 0x00000018U

Definition at line 455 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_DMA().

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STM32F103xB HAL User Manual: TIM Input Capture Polarity

Defines
TIM Input Capture Polarity
TIM Exported Constants

Defines

#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Define Documentation

#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Definition at line 464 of file stm32f1xx_hal_tim.h.

#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Definition at line 463 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Input Capture Selection

Defines
TIM Input Capture Selection
TIM Exported Constants

Defines

#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

Define Documentation

#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively

Definition at line 472 of file stm32f1xx_hal_tim.h.

#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)

TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively

Definition at line 474 of file stm32f1xx_hal_tim.h.

#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)

TIM Input 1, 2, 3 or 4 is selected to be connected to TRC

Definition at line 476 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

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STM32F103xB HAL User Manual: TIM Input Capture Prescaler

Defines
TIM Input Capture Prescaler
TIM Exported Constants

Defines

#define | TIM_ICPSC_DIV1 0x00000000U
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Define Documentation

#define TIM_ICPSC_DIV1 0x00000000U

Capture performed each time an edge is detected on the capture input

Definition at line 484 of file stm32f1xx_hal_tim.h.

#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)

Capture performed once every 2 events

Definition at line 485 of file stm32f1xx_hal_tim.h.

#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)

Capture performed once every 4 events

Definition at line 486 of file stm32f1xx_hal_tim.h.

#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)

Capture performed once every 8 events

Definition at line 487 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM One Pulse Mode

Defines
TIM One Pulse Mode
TIM Exported Constants

Defines

#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE 0x00000000U

Define Documentation

#define TIM_OPMODE_REPETITIVE 0x00000000U

Definition at line 496 of file stm32f1xx_hal_tim.h.

#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)

Definition at line 495 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Encoder Mode

Defines
TIM Encoder Mode
TIM Exported Constants

Defines

#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Define Documentation

#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)

Definition at line 504 of file stm32f1xx_hal_tim.h.

#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)

Definition at line 506 of file stm32f1xx_hal_tim.h.

#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)

Definition at line 505 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Interrupt Definition

Defines
TIM Interrupt Definition
TIM Exported Constants

Defines

#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)

Define Documentation

#define TIM_IT_BREAK (TIM_DIER_BIE)

Definition at line 521 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC1 (TIM_DIER_CC1IE)

Definition at line 515 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC2 (TIM_DIER_CC2IE)

Definition at line 516 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC3 (TIM_DIER_CC3IE)

Definition at line 517 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_CC4 (TIM_DIER_CC4IE)

Definition at line 518 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_IRQHandler(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_PWMN_Start_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_IT_COM (TIM_DIER_COMIE)

Definition at line 519 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), and HAL_TIMEx_ConfigCommutationEvent_IT().

#define TIM_IT_TRIGGER (TIM_DIER_TIE)

Definition at line 520 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler(), HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_IT_UPDATE (TIM_DIER_UIE)

Definition at line 514 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop_IT(), and HAL_TIM_IRQHandler().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Commutation Source

Defines
TIM Commutation Source
TIM Exported Constants

Defines

#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE 0x00000000U

Define Documentation

#define TIM_COMMUTATION_SOFTWARE 0x00000000U

Definition at line 530 of file stm32f1xx_hal_tim.h.

#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)

Definition at line 529 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM DMA Sources

Defines
TIM DMA Sources
TIM Exported Constants

Defines

#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)

Define Documentation

#define TIM_DMA_CC1 (TIM_DIER_CC1DE)

Definition at line 540 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC2 (TIM_DIER_CC2DE)

Definition at line 541 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC3 (TIM_DIER_CC3DE)

Definition at line 542 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_CC4 (TIM_DIER_CC4DE)

Definition at line 543 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define TIM_DMA_COM (TIM_DIER_COMDE)

Definition at line 544 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

#define TIM_DMA_TRIGGER (TIM_DIER_TDE)

Definition at line 545 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define TIM_DMA_UPDATE (TIM_DIER_UDE)

Definition at line 539 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Event Source

Defines
TIM Event Source
TIM Exported Constants

Defines

#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG

Define Documentation

#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG

Definition at line 560 of file stm32f1xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G

Definition at line 554 of file stm32f1xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G

Definition at line 555 of file stm32f1xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G

Definition at line 556 of file stm32f1xx_hal_tim.h.

#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G

Definition at line 557 of file stm32f1xx_hal_tim.h.

#define TIM_EVENTSOURCE_COM TIM_EGR_COMG

Definition at line 558 of file stm32f1xx_hal_tim.h.

#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG

Definition at line 559 of file stm32f1xx_hal_tim.h.

#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG

Definition at line 553 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Flag Definition

Defines
TIM Flag Definition
TIM Exported Constants

Defines

#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Define Documentation

#define TIM_FLAG_BREAK (TIM_SR_BIF)

Definition at line 575 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1 (TIM_SR_CC1IF)

Definition at line 569 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)

Definition at line 576 of file stm32f1xx_hal_tim.h.

#define TIM_FLAG_CC2 (TIM_SR_CC2IF)

Definition at line 570 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)

Definition at line 577 of file stm32f1xx_hal_tim.h.

#define TIM_FLAG_CC3 (TIM_SR_CC3IF)

Definition at line 571 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)

Definition at line 578 of file stm32f1xx_hal_tim.h.

#define TIM_FLAG_CC4 (TIM_SR_CC4IF)

Definition at line 572 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)

Definition at line 579 of file stm32f1xx_hal_tim.h.

#define TIM_FLAG_COM (TIM_SR_COMIF)

Definition at line 573 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_TRIGGER (TIM_SR_TIF)

Definition at line 574 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define TIM_FLAG_UPDATE (TIM_SR_UIF)

Definition at line 568 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Clock Source

Defines
TIM Clock Source
TIM Exported Constants

Defines

#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)

Define Documentation

#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)

Definition at line 596 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)

Definition at line 587 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)

Definition at line 588 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)

Definition at line 589 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)

Definition at line 590 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)

Definition at line 591 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)

Definition at line 592 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)

Definition at line 594 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)

Definition at line 593 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)

Definition at line 595 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

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STM32F103xB HAL User Manual: TIM Clock Polarity

Defines
TIM Clock Polarity
TIM Exported Constants

Defines

#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIx clock sources

Definition at line 608 of file stm32f1xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIx clock sources

Definition at line 607 of file stm32f1xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx clock sources

Definition at line 604 of file stm32f1xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx clock sources

Definition at line 605 of file stm32f1xx_hal_tim.h.

#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIx clock sources

Definition at line 606 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Clock Prescaler

Defines
TIM Clock Prescaler
TIM Exported Constants

Defines

#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 616 of file stm32f1xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Clock: Capture performed once every 2 events.

Definition at line 617 of file stm32f1xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Clock: Capture performed once every 4 events.

Definition at line 618 of file stm32f1xx_hal_tim.h.

#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Clock: Capture performed once every 8 events.

Definition at line 619 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM ClearInput Source

Defines
TIM ClearInput Source
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTSOURCE_ETR 0x00000001U
#define | TIM_CLEARINPUTSOURCE_NONE 0x00000000U

Define Documentation

#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U

Definition at line 627 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U

Definition at line 628 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

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STM32F103xB HAL User Manual: TIM Clear Input Polarity

Defines
TIM Clear Input Polarity
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Define Documentation

#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx pin

Definition at line 636 of file stm32f1xx_hal_tim.h.

#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx pin

Definition at line 637 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Clear Input Prescaler

Defines
TIM Clear Input Prescaler
TIM Exported Constants

Defines

#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 645 of file stm32f1xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR pin: Capture performed once every 2 events.

Definition at line 646 of file stm32f1xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR pin: Capture performed once every 4 events.

Definition at line 647 of file stm32f1xx_hal_tim.h.

#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR pin: Capture performed once every 8 events.

Definition at line 648 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM OSSR Off State Selection for Run mode state

Defines
TIM OSSR Off State Selection for Run mode state
TIM Exported Constants

Defines

#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE 0x00000000U

Define Documentation

#define TIM_OSSR_DISABLE 0x00000000U

Definition at line 657 of file stm32f1xx_hal_tim.h.

#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)

Definition at line 656 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM OSSI Off State Selection for Idle mode state

Defines
TIM OSSI Off State Selection for Idle mode state
TIM Exported Constants

Defines

#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE 0x00000000U

Define Documentation

#define TIM_OSSI_DISABLE 0x00000000U

Definition at line 666 of file stm32f1xx_hal_tim.h.

#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)

Definition at line 665 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Lock level

Defines
TIM Lock level
TIM Exported Constants

Defines

#define | TIM_LOCKLEVEL_OFF 0x00000000U
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Define Documentation

#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)

Definition at line 675 of file stm32f1xx_hal_tim.h.

#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)

Definition at line 676 of file stm32f1xx_hal_tim.h.

#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)

Definition at line 677 of file stm32f1xx_hal_tim.h.

#define TIM_LOCKLEVEL_OFF 0x00000000U

Definition at line 674 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Break Input Enable Disable

Defines
TIM Break Input Enable Disable
TIM Exported Constants

Defines

#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE 0x00000000U

Define Documentation

#define TIM_BREAK_DISABLE 0x00000000U

Definition at line 686 of file stm32f1xx_hal_tim.h.

#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)

Definition at line 685 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Break Input Polarity

Defines
TIM Break Input Polarity
TIM Exported Constants

Defines

#define | TIM_BREAKPOLARITY_LOW 0x00000000U
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Define Documentation

#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)

Definition at line 695 of file stm32f1xx_hal_tim.h.

#define TIM_BREAKPOLARITY_LOW 0x00000000U

Definition at line 694 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Automatic Output Enable

Defines
TIM Automatic Output Enable
TIM Exported Constants

Defines

#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

Define Documentation

#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U

Definition at line 703 of file stm32f1xx_hal_tim.h.

#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)

Definition at line 702 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Master Mode Selection

Defines
TIM Master Mode Selection
TIM Exported Constants

Defines

#define | TIM_TRGO_RESET 0x00000000U
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Define Documentation

#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)

Definition at line 712 of file stm32f1xx_hal_tim.h.

#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 714 of file stm32f1xx_hal_tim.h.

#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)

Definition at line 715 of file stm32f1xx_hal_tim.h.

#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))

Definition at line 716 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))

Definition at line 717 of file stm32f1xx_hal_tim.h.

#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))

Definition at line 718 of file stm32f1xx_hal_tim.h.

#define TIM_TRGO_RESET 0x00000000U

Definition at line 711 of file stm32f1xx_hal_tim.h.

#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)

Definition at line 713 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Slave Mode

Defines
TIM Slave Mode
TIM Exported Constants

Defines

#define | TIM_SLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_RESET 0x00000004U
#define | TIM_SLAVEMODE_GATED 0x00000005U
#define | TIM_SLAVEMODE_TRIGGER 0x00000006U
#define | TIM_SLAVEMODE_EXTERNAL1 0x00000007U

Define Documentation

#define TIM_SLAVEMODE_DISABLE 0x00000000U

Definition at line 726 of file stm32f1xx_hal_tim.h.

#define TIM_SLAVEMODE_EXTERNAL1 0x00000007U

Definition at line 730 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource(), and TIM_ITRx_SetConfig().

#define TIM_SLAVEMODE_GATED 0x00000005U

Definition at line 728 of file stm32f1xx_hal_tim.h.

#define TIM_SLAVEMODE_RESET 0x00000004U

Definition at line 727 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init().

#define TIM_SLAVEMODE_TRIGGER 0x00000006U

Definition at line 729 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

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STM32F103xB HAL User Manual: TIM Master Slave Mode

Defines
TIM Master Slave Mode
TIM Exported Constants

Defines

#define | TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
#define | TIM_MASTERSLAVEMODE_DISABLE 0x00000000U

Define Documentation

#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U

Definition at line 739 of file stm32f1xx_hal_tim.h.

#define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U

Definition at line 738 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Trigger Selection

Defines
TIM Trigger Selection
TIM Exported Constants

Defines

#define | TIM_TS_ITR0 0x00000000U
#define | TIM_TS_ITR1 0x00000010U
#define | TIM_TS_ITR2 0x00000020U
#define | TIM_TS_ITR3 0x00000030U
#define | TIM_TS_TI1F_ED 0x00000040U
#define | TIM_TS_TI1FP1 0x00000050U
#define | TIM_TS_TI2FP2 0x00000060U
#define | TIM_TS_ETRF 0x00000070U
#define | TIM_TS_NONE 0x0000FFFFU

Define Documentation

#define TIM_TS_ETRF 0x00000070U

Definition at line 754 of file stm32f1xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR0 0x00000000U

Definition at line 747 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR1 0x00000010U

Definition at line 748 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR2 0x00000020U

Definition at line 749 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_ITR3 0x00000030U

Definition at line 750 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_NONE 0x0000FFFFU

Definition at line 755 of file stm32f1xx_hal_tim.h.

#define TIM_TS_TI1F_ED 0x00000040U

Definition at line 751 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_HallSensor_Init(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI1FP1 0x00000050U

Definition at line 752 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

#define TIM_TS_TI2FP2 0x00000060U

Definition at line 753 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel(), and TIM_SlaveTimer_SetConfig().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Trigger Polarity

Defines
TIM Trigger Polarity
TIM Exported Constants

Defines

#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Define Documentation

#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 767 of file stm32f1xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 766 of file stm32f1xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED

Polarity for ETRx trigger sources

Definition at line 763 of file stm32f1xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED

Polarity for ETRx trigger sources

Definition at line 764 of file stm32f1xx_hal_tim.h.

#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING

Polarity for TIxFPx or TI1_ED trigger sources

Definition at line 765 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM Trigger Prescaler

Defines
TIM Trigger Prescaler
TIM Exported Constants

Defines

#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Define Documentation

#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1

No prescaler is used

Definition at line 775 of file stm32f1xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2

Prescaler for External ETR Trigger: Capture performed once every 2 events.

Definition at line 776 of file stm32f1xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4

Prescaler for External ETR Trigger: Capture performed once every 4 events.

Definition at line 777 of file stm32f1xx_hal_tim.h.

#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8

Prescaler for External ETR Trigger: Capture performed once every 8 events.

Definition at line 778 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM TI1 Input Selection

Defines
TIM TI1 Input Selection
TIM Exported Constants

Defines

#define | TIM_TI1SELECTION_CH1 0x00000000U
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Define Documentation

#define TIM_TI1SELECTION_CH1 0x00000000U

Definition at line 786 of file stm32f1xx_hal_tim.h.

#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)

Definition at line 787 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM DMA Base Address

Defines
TIM DMA Base Address
TIM Exported Constants

Defines

#define | TIM_DMABASE_CR1 0x00000000U
#define | TIM_DMABASE_CR2 0x00000001U
#define | TIM_DMABASE_SMCR 0x00000002U
#define | TIM_DMABASE_DIER 0x00000003U
#define | TIM_DMABASE_SR 0x00000004U
#define | TIM_DMABASE_EGR 0x00000005U
#define | TIM_DMABASE_CCMR1 0x00000006U
#define | TIM_DMABASE_CCMR2 0x00000007U
#define | TIM_DMABASE_CCER 0x00000008U
#define | TIM_DMABASE_CNT 0x00000009U
#define | TIM_DMABASE_PSC 0x0000000AU
#define | TIM_DMABASE_ARR 0x0000000BU
#define | TIM_DMABASE_RCR 0x0000000CU
#define | TIM_DMABASE_CCR1 0x0000000DU
#define | TIM_DMABASE_CCR2 0x0000000EU
#define | TIM_DMABASE_CCR3 0x0000000FU
#define | TIM_DMABASE_CCR4 0x00000010U
#define | TIM_DMABASE_BDTR 0x00000011U
#define | TIM_DMABASE_DCR 0x00000012U

Define Documentation

#define TIM_DMABASE_ARR 0x0000000BU

Definition at line 806 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_BDTR 0x00000011U

Definition at line 812 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_CCER 0x00000008U

Definition at line 803 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_CCMR1 0x00000006U

Definition at line 801 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_CCMR2 0x00000007U

Definition at line 802 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_CCR1 0x0000000DU

Definition at line 808 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_CCR2 0x0000000EU

Definition at line 809 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_CCR3 0x0000000FU

Definition at line 810 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_CCR4 0x00000010U

Definition at line 811 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_CNT 0x00000009U

Definition at line 804 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_CR1 0x00000000U

Definition at line 795 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_CR2 0x00000001U

Definition at line 796 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_DCR 0x00000012U

Definition at line 813 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_DIER 0x00000003U

Definition at line 798 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_EGR 0x00000005U

Definition at line 800 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_PSC 0x0000000AU

Definition at line 805 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_RCR 0x0000000CU

Definition at line 807 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_SMCR 0x00000002U

Definition at line 797 of file stm32f1xx_hal_tim.h.

#define TIM_DMABASE_SR 0x00000004U

Definition at line 799 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM DMA Burst Length

Defines
TIM DMA Burst Length
TIM Exported Constants

Defines

#define | TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define | TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define | TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define | TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define | TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define | TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define | TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define | TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define | TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define | TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define | TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define | TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define | TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define | TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define | TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define | TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define | TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define | TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

Define Documentation

#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U

Definition at line 830 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U

Definition at line 831 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U

Definition at line 832 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U

Definition at line 833 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U

Definition at line 834 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U

Definition at line 835 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U

Definition at line 836 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U

Definition at line 837 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U

Definition at line 838 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U

Definition at line 821 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U

Definition at line 822 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U

Definition at line 823 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U

Definition at line 824 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U

Definition at line 825 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U

Definition at line 826 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U

Definition at line 827 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U

Definition at line 828 of file stm32f1xx_hal_tim.h.

#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U

Definition at line 829 of file stm32f1xx_hal_tim.h.

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STM32F103xB HAL User Manual: TIM DMA Handle Index

Defines
TIM DMA Handle Index
TIM Exported Constants

Defines

#define | TIM_DMA_ID_UPDATE ((uint16_t)0x0)
#define | TIM_DMA_ID_CC1 ((uint16_t)0x1)
#define | TIM_DMA_ID_CC2 ((uint16_t)0x2)
#define | TIM_DMA_ID_CC3 ((uint16_t)0x3)
#define | TIM_DMA_ID_CC4 ((uint16_t)0x4)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t)0x5)
#define | TIM_DMA_ID_TRIGGER ((uint16_t)0x6)

Define Documentation

#define TIM_DMA_ID_CC1 ((uint16_t)0x1)

Index of the DMA handle used for Capture/Compare 1 DMA requests

Definition at line 847 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC2 ((uint16_t)0x2)

Index of the DMA handle used for Capture/Compare 2 DMA requests

Definition at line 848 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC3 ((uint16_t)0x3)

Index of the DMA handle used for Capture/Compare 3 DMA requests

Definition at line 849 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_CC4 ((uint16_t)0x4)

Index of the DMA handle used for Capture/Compare 4 DMA requests

Definition at line 850 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_PWMN_Start_DMA(), TIM_DMACaptureCplt(), and TIM_DMADelayPulseCplt().

#define TIM_DMA_ID_COMMUTATION ((uint16_t)0x5)

Index of the DMA handle used for Commutation DMA requests

Definition at line 851 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

#define TIM_DMA_ID_TRIGGER ((uint16_t)0x6)

Index of the DMA handle used for Trigger DMA requests

Definition at line 852 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define TIM_DMA_ID_UPDATE ((uint16_t)0x0)

Index of the DMA handle used for Update DMA requests

Definition at line 846 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Capture/Compare Channel State

Defines
TIM Capture/Compare Channel State
TIM Exported Constants

Defines

#define | TIM_CCx_ENABLE 0x00000001U
#define | TIM_CCx_DISABLE 0x00000000U
#define | TIM_CCxN_ENABLE 0x00000004U
#define | TIM_CCxN_DISABLE 0x00000000U

Define Documentation

#define TIM_CCx_DISABLE 0x00000000U

Definition at line 861 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), and HAL_TIMEx_HallSensor_Stop_IT().

#define TIM_CCx_ENABLE 0x00000001U

Definition at line 860 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), and HAL_TIMEx_HallSensor_Start_IT().

#define TIM_CCxN_DISABLE 0x00000000U

Definition at line 863 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define TIM_CCxN_ENABLE 0x00000004U

Definition at line 862 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Private Constants

Defines
TIM Private Constants
TIM

Defines

#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Define Documentation

#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

Definition at line 879 of file stm32f1xx_hal_tim.h.

#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

Definition at line 880 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Private Macros

Defines
TIM Private Macros
TIM

Defines

#define | IS_TIM_COUNTER_MODE(MODE)
#define | IS_TIM_CLOCKDIVISION_DIV(DIV)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_PWM_MODE(MODE)
#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_FAST_STATE(STATE)
#define | IS_TIM_OC_POLARITY(POLARITY)
#define | IS_TIM_OCN_POLARITY(POLARITY)
#define | IS_TIM_OCIDLE_STATE(STATE)
#define | IS_TIM_OCNIDLE_STATE(STATE)
#define | IS_TIM_CHANNELS(CHANNEL)
#define | IS_TIM_OPM_CHANNELS(CHANNEL)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL)
#define | IS_TIM_IC_POLARITY(POLARITY)
#define | IS_TIM_IC_SELECTION(SELECTION)
#define | IS_TIM_IC_PRESCALER(PRESCALER)
#define | IS_TIM_OPM_MODE(MODE)
#define | IS_TIM_ENCODER_MODE(MODE)
#define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_CLOCKSOURCE(CLOCK)
#define | IS_TIM_CLOCKPOLARITY(POLARITY)
#define | IS_TIM_CLOCKPRESCALER(PRESCALER)
#define | IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_CLEARINPUT_SOURCE(SOURCE)
#define | IS_TIM_CLEARINPUT_POLARITY(POLARITY)
#define | IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)
#define | IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_OSSR_STATE(STATE)
#define | IS_TIM_OSSI_STATE(STATE)
#define | IS_TIM_LOCK_LEVEL(LEVEL)
#define | IS_TIM_BREAK_STATE(STATE)
#define | IS_TIM_BREAK_POLARITY(POLARITY)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define | IS_TIM_TRGO_SOURCE(SOURCE)
#define | IS_TIM_SLAVE_MODE(MODE)
#define | IS_TIM_MSM_STATE(STATE)
#define | IS_TIM_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION)
#define | IS_TIM_TRIGGERPOLARITY(POLARITY)
#define | IS_TIM_TRIGGERPRESCALER(PRESCALER)
#define | IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_TI1SELECTION(TI1SELECTION)
#define | IS_TIM_DMA_BASE(BASE)
#define | IS_TIM_DMA_LENGTH(LENGTH)
#define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
Set TIM IC prescaler.
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
Reset TIM IC prescaler.
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set TIM IC polarity.
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
Reset TIM IC polarity.

Define Documentation

#define IS_TIM_AUTOMATIC_OUTPUT_STATE ( STATE )
Value:
(((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                              ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))

Definition at line 1019 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_AUTORELOAD_PRELOAD ( PRELOAD )
Value:
(((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))

Definition at line 901 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_BREAK_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
                                         ((POLARITY) == TIM_BREAKPOLARITY_HIGH))

Definition at line 1016 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_BREAK_STATE ( STATE )
Value:
(((STATE) == TIM_BREAK_ENABLE) || \
                                   ((STATE) == TIM_BREAK_DISABLE))

Definition at line 1013 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                  ((CHANNEL) == TIM_CHANNEL_2) || \
                                  ((CHANNEL) == TIM_CHANNEL_3) || \
                                  ((CHANNEL) == TIM_CHANNEL_4) || \
                                  ((CHANNEL) == TIM_CHANNEL_ALL))

Definition at line 929 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), HAL_TIM_PWM_ConfigChannel(), and TIM_CCxChannelCmd().

#define IS_TIM_CLEARINPUT_FILTER ( ICFILTER ) ((ICFILTER) <= 0x0FU)

Definition at line 1000 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
                                              ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

Definition at line 992 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))

Definition at line 995 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLEARINPUT_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)      || \
                                          ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))

Definition at line 989 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigOCrefClear().

#define IS_TIM_CLOCKDIVISION_DIV ( DIV )
Value:
(((DIV) == TIM_CLOCKDIVISION_DIV1) || \
                                       ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
                                       ((DIV) == TIM_CLOCKDIVISION_DIV4))

Definition at line 897 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_CLOCKFILTER ( ICFILTER ) ((ICFILTER) <= 0x0FU)

Definition at line 987 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPOLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
                                        ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))

Definition at line 976 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKPRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))

Definition at line 982 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_CLOCKSOURCE ( CLOCK )
Value:
(((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))

Definition at line 965 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigClockSource().

#define IS_TIM_COMPLEMENTARY_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                                ((CHANNEL) == TIM_CHANNEL_2) || \
                                                ((CHANNEL) == TIM_CHANNEL_3))

Definition at line 938 of file stm32f1xx_hal_tim.h.

#define IS_TIM_COUNTER_MODE ( MODE )
Value:
(((MODE) == TIM_COUNTERMODE_UP)              || \
                                   ((MODE) == TIM_COUNTERMODE_DOWN)            || \
                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))

Definition at line 891 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Init(), HAL_TIM_Encoder_Init(), HAL_TIM_IC_Init(), HAL_TIM_OC_Init(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_Init(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_DMA_BASE ( BASE )
Value:
(((BASE) == TIM_DMABASE_CR1)   || \
                               ((BASE) == TIM_DMABASE_CR2)   || \
                               ((BASE) == TIM_DMABASE_SMCR)  || \
                               ((BASE) == TIM_DMABASE_DIER)  || \
                               ((BASE) == TIM_DMABASE_SR)    || \
                               ((BASE) == TIM_DMABASE_EGR)   || \
                               ((BASE) == TIM_DMABASE_CCMR1) || \
                               ((BASE) == TIM_DMABASE_CCMR2) || \
                               ((BASE) == TIM_DMABASE_CCER)  || \
                               ((BASE) == TIM_DMABASE_CNT)   || \
                               ((BASE) == TIM_DMABASE_PSC)   || \
                               ((BASE) == TIM_DMABASE_ARR)   || \
                               ((BASE) == TIM_DMABASE_RCR)   || \
                               ((BASE) == TIM_DMABASE_CCR1)  || \
                               ((BASE) == TIM_DMABASE_CCR2)  || \
                               ((BASE) == TIM_DMABASE_CCR3)  || \
                               ((BASE) == TIM_DMABASE_CCR4)  || \
                               ((BASE) == TIM_DMABASE_BDTR)  || \
                               ((BASE) == TIM_DMABASE_DCR))

Definition at line 1071 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_LENGTH ( LENGTH )
Value:
(((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
                                   ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))

Definition at line 1091 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), and HAL_TIM_DMABurst_WriteStart().

#define IS_TIM_DMA_SOURCE ( SOURCE ) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))

Definition at line 961 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIM_DMABurst_WriteStop().

#define IS_TIM_ENCODER_MODE ( MODE )
Value:
(((MODE) == TIM_ENCODERMODE_TI1) || \
                                   ((MODE) == TIM_ENCODERMODE_TI2) || \
                                   ((MODE) == TIM_ENCODERMODE_TI12))

Definition at line 957 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init().

#define IS_TIM_EVENT_SOURCE ( SOURCE ) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))

Definition at line 963 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_GenerateEvent().

#define IS_TIM_FAST_STATE ( STATE )
Value:
(((STATE) == TIM_OCFAST_DISABLE) || \
                                  ((STATE) == TIM_OCFAST_ENABLE))

Definition at line 914 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_IC_FILTER ( ICFILTER ) ((ICFILTER) <= 0x0FU)

Definition at line 1110 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_ICPOLARITY_RISING)   || \
                                      ((POLARITY) == TIM_ICPOLARITY_FALLING))

Definition at line 942 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_PRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_ICPSC_DIV1) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
                                        ((PRESCALER) == TIM_ICPSC_DIV8))

Definition at line 949 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), HAL_TIM_IC_ConfigChannel(), and HAL_TIMEx_HallSensor_Init().

#define IS_TIM_IC_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_ICSELECTION_DIRECTTI)   || \
                                        ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
                                        ((SELECTION) == TIM_ICSELECTION_TRC))

Definition at line 945 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Encoder_Init(), and HAL_TIM_IC_ConfigChannel().

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0) || \
                                                           ((SELECTION) == TIM_TS_ITR1) || \
                                                           ((SELECTION) == TIM_TS_ITR2) || \
                                                           ((SELECTION) == TIM_TS_ITR3) || \
                                                           ((SELECTION) == TIM_TS_NONE))

Definition at line 1049 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), and HAL_TIMEx_ConfigCommutationEvent_IT().

#define IS_TIM_LOCK_LEVEL ( LEVEL )
Value:
(((LEVEL) == TIM_LOCKLEVEL_OFF) || \
                                  ((LEVEL) == TIM_LOCKLEVEL_1)   || \
                                  ((LEVEL) == TIM_LOCKLEVEL_2)   || \
                                  ((LEVEL) == TIM_LOCKLEVEL_3))

Definition at line 1008 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_MSM_STATE ( STATE )
Value:
(((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
                                 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))

Definition at line 1037 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_OC_MODE ( MODE )
Value:
(((MODE) == TIM_OCMODE_TIMING)       || \
                          ((MODE) == TIM_OCMODE_ACTIVE)           || \
                          ((MODE) == TIM_OCMODE_INACTIVE)         || \
                          ((MODE) == TIM_OCMODE_TOGGLE)           || \
                          ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
                          ((MODE) == TIM_OCMODE_FORCED_INACTIVE))

Definition at line 907 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel().

#define IS_TIM_OC_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_OCPOLARITY_HIGH) || \
                                      ((POLARITY) == TIM_OCPOLARITY_LOW))

Definition at line 917 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OC_ConfigChannel(), and HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_OCIDLE_STATE ( STATE )
Value:
(((STATE) == TIM_OCIDLESTATE_SET) || \
                                    ((STATE) == TIM_OCIDLESTATE_RESET))

Definition at line 923 of file stm32f1xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), and TIM_OC4_SetConfig().

#define IS_TIM_OCN_POLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
                                       ((POLARITY) == TIM_OCNPOLARITY_LOW))

Definition at line 920 of file stm32f1xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OCNIDLE_STATE ( STATE )
Value:
(((STATE) == TIM_OCNIDLESTATE_SET) || \
                                     ((STATE) == TIM_OCNIDLESTATE_RESET))

Definition at line 926 of file stm32f1xx_hal_tim.h.

Referenced by TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), and TIM_OC3_SetConfig().

#define IS_TIM_OPM_CHANNELS ( CHANNEL )
Value:
(((CHANNEL) == TIM_CHANNEL_1) || \
                                      ((CHANNEL) == TIM_CHANNEL_2))

Definition at line 935 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_ConfigChannel().

#define IS_TIM_OPM_MODE ( MODE )
Value:
(((MODE) == TIM_OPMODE_SINGLE) || \
                               ((MODE) == TIM_OPMODE_REPETITIVE))

Definition at line 954 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OnePulse_Init().

#define IS_TIM_OSSI_STATE ( STATE )
Value:
(((STATE) == TIM_OSSI_ENABLE) || \
                                  ((STATE) == TIM_OSSI_DISABLE))

Definition at line 1005 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_OSSR_STATE ( STATE )
Value:
(((STATE) == TIM_OSSR_ENABLE) || \
                                  ((STATE) == TIM_OSSR_DISABLE))

Definition at line 1002 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

#define IS_TIM_PWM_MODE ( MODE )
Value:
(((MODE) == TIM_OCMODE_PWM1) || \
                               ((MODE) == TIM_OCMODE_PWM2))

Definition at line 904 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_PWM_ConfigChannel().

#define IS_TIM_SLAVE_MODE ( MODE )
Value:
(((MODE) == TIM_SLAVEMODE_DISABLE) || \
                                 ((MODE) == TIM_SLAVEMODE_GATED)   || \
                                 ((MODE) == TIM_SLAVEMODE_RESET)   || \
                                 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))

Definition at line 1031 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TI1SELECTION ( TI1SELECTION )
Value:
(((TI1SELECTION) == TIM_TI1SELECTION_CH1)            || \
                                             ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))

Definition at line 1068 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_ConfigTI1Input().

#define IS_TIM_TRGO_SOURCE ( SOURCE )
Value:
(((SOURCE) == TIM_TRGO_RESET)  || \
                                    ((SOURCE) == TIM_TRGO_ENABLE) || \
                                    ((SOURCE) == TIM_TRGO_UPDATE) || \
                                    ((SOURCE) == TIM_TRGO_OC1)    || \
                                    ((SOURCE) == TIM_TRGO_OC1REF) || \
                                    ((SOURCE) == TIM_TRGO_OC2REF) || \
                                    ((SOURCE) == TIM_TRGO_OC3REF) || \
                                    ((SOURCE) == TIM_TRGO_OC4REF))

Definition at line 1022 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

#define IS_TIM_TRIGGER_SELECTION ( SELECTION )
Value:
(((SELECTION) == TIM_TS_ITR0)    || \
                                             ((SELECTION) == TIM_TS_ITR1)    || \
                                             ((SELECTION) == TIM_TS_ITR2)    || \
                                             ((SELECTION) == TIM_TS_ITR3)    || \
                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
                                             ((SELECTION) == TIM_TS_TI1FP1)  || \
                                             ((SELECTION) == TIM_TS_TI2FP2)  || \
                                             ((SELECTION) == TIM_TS_ETRF))

Definition at line 1040 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_SlaveConfigSynchronization(), and HAL_TIM_SlaveConfigSynchronization_IT().

#define IS_TIM_TRIGGERFILTER ( ICFILTER ) ((ICFILTER) <= 0x0FU)

Definition at line 1066 of file stm32f1xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPOLARITY ( POLARITY )
Value:
(((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
                                              ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

Definition at line 1055 of file stm32f1xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define IS_TIM_TRIGGERPRESCALER ( PRESCALER )
Value:
(((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))

Definition at line 1061 of file stm32f1xx_hal_tim.h.

Referenced by TIM_SlaveTimer_SetConfig().

#define TIM_RESET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))

Reset TIM IC polarity.

Parameters:
__HANDLE__,: TIM handle
__CHANNEL__,: specifies TIM Channel
Return values:
None

Definition at line 1153 of file stm32f1xx_hal_tim.h.

#define TIM_RESET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))

Reset TIM IC prescaler.

Parameters:
__HANDLE__,: TIM handle
__CHANNEL__,: specifies TIM Channel
Return values:
None

Definition at line 1129 of file stm32f1xx_hal_tim.h.

#define TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))

Set TIM IC polarity.

Parameters:
__HANDLE__,: TIM handle
__CHANNEL__,: specifies TIM Channel
__POLARITY__,: specifies TIM Channel Polarity
Return values:
None

Definition at line 1142 of file stm32f1xx_hal_tim.h.

#define TIM_SET_ICPRESCALERVALUE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))

Set TIM IC prescaler.

Parameters:
__HANDLE__,: TIM handle
__CHANNEL__,: specifies TIM Channel
__ICPSC__,: specifies the prescaler value.
Return values:
None

Definition at line 1118 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Exported Macros

Defines
TIM Exported Macros
TIM

Defines

#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enables the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disables the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enables the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disables the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Checks whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks whether the specified TIM interrupt has occurred or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Sets the TIM active prescaler register value on update event.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
Gets the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Sets the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Gets the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Sets the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Gets the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Sets the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Gets the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Gets the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Sets the TIM Capture x input polarity on runtime.

Define Documentation

#define __HAL_TIM_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clears the specified TIM interrupt flag.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__FLAG__,: specifies the TIM interrupt flag to clear. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1351 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

Clear the TIM interrupt pending bits.

Parameters:
__HANDLE__,: TIM handle
__INTERRUPT__,: specifies the interrupt pending bit to clear.
Return values:
None

Definition at line 1367 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
                            { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
                            { \
                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
                            } \
                          } \
                        } while(0U)

Disable the TIM peripheral.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 1208 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_DeInit(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_DISABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

Disables the specified DMA request.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__DMA__,: specifies the TIM DMA request to disable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1309 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_DMA(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_OCN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_DMA().

#define __HAL_TIM_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

Disables the specified TIM interrupt.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__INTERRUPT__,: specifies the TIM interrupt source to disable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1277 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Stop_IT(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop_IT(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

Enable the TIM peripheral.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 1194 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_ENABLE_DMA | ( | __HANDLE__,
 |  | __DMA__
 | ) | ((__HANDLE__)->Instance->DIER |= (__DMA__))

Enables the specified DMA request.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__DMA__,: specifies the TIM DMA request to enable. This parameter can be one of the following values:
  • TIM_DMA_UPDATE: Update DMA request
  • TIM_DMA_CC1: Capture/Compare 1 DMA request
  • TIM_DMA_CC2: Capture/Compare 2 DMA request
  • TIM_DMA_CC3: Capture/Compare 3 DMA request
  • TIM_DMA_CC4: Capture/Compare 4 DMA request
  • TIM_DMA_COM: Commutation DMA request
  • TIM_DMA_TRIGGER: Trigger DMA request
Return values:
None

Definition at line 1293 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_DMA(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_IC_Start_DMA(), HAL_TIM_OC_Start_DMA(), HAL_TIM_PWM_Start_DMA(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_OCN_Start_DMA(), and HAL_TIMEx_PWMN_Start_DMA().

#define __HAL_TIM_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

Enables the specified TIM interrupt.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__INTERRUPT__,: specifies the TIM interrupt source to enable. This parameter can be one of the following values:
  • TIM_IT_UPDATE: Update interrupt
  • TIM_IT_CC1: Capture/Compare 1 interrupt
  • TIM_IT_CC2: Capture/Compare 2 interrupt
  • TIM_IT_CC3: Capture/Compare 3 interrupt
  • TIM_IT_CC4: Capture/Compare 4 interrupt
  • TIM_IT_COM: Commutation interrupt
  • TIM_IT_TRIGGER: Trigger interrupt
  • TIM_IT_BREAK: Break interrupt
Return values:
None

Definition at line 1260 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_Base_Start_IT(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_IC_Start_IT(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start_IT(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start_IT(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_GET_AUTORELOAD ( __HANDLE__ ) ((__HANDLE__)->Instance->ARR)

Gets the TIM Autoreload Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
@retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)

Definition at line 1450 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_GET_CLOCKDIVISION ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

Gets the TIM Clock Division value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
The clock division can be one of the following values:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT

Definition at line 1479 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_GET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))

Gets the TIM Capture Compare Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channel associated with the capture compare register This parameter can be one of the following values:
  • TIM_CHANNEL_1: get capture/compare 1 register value
  • TIM_CHANNEL_2: get capture/compare 2 register value
  • TIM_CHANNEL_3: get capture/compare 3 register value
  • TIM_CHANNEL_4: get capture/compare 4 register value
Return values:
16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)

Definition at line 1413 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_GET_COUNTER ( __HANDLE__ ) ((__HANDLE__)->Instance->CNT)

Gets the TIM Counter Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
Return values:
16-bit or 32-bit value of the timer counter register (TIMx_CNT)

Definition at line 1429 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

Checks whether the specified TIM interrupt flag is set or not.

Parameters:
__HANDLE__,: specifies the TIM Handle.
__FLAG__,: specifies the TIM interrupt flag to check. This parameter can be one of the following values:
  • TIM_FLAG_UPDATE: Update interrupt flag
  • TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  • TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  • TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  • TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  • TIM_FLAG_COM: Commutation interrupt flag
  • TIM_FLAG_TRIGGER: Trigger interrupt flag
  • TIM_FLAG_BREAK: Break interrupt flag
  • TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  • TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  • TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  • TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 1330 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_GET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)

Gets the TIM Input Capture prescaler on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: get input capture 1 prescaler value
  • TIM_CHANNEL_2: get input capture 2 prescaler value
  • TIM_CHANNEL_3: get input capture 3 prescaler value
  • TIM_CHANNEL_4: get input capture 4 prescaler value
Return values:
The input capture prescaler can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events

Definition at line 1521 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

Checks whether the specified TIM interrupt has occurred or not.

Parameters:
__HANDLE__,: TIM handle
__INTERRUPT__,: specifies the TIM interrupt source to check.
Return values:
The state of TIM_IT (SET or RESET).

Definition at line 1359 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_IRQHandler().

#define __HAL_TIM_IS_TIM_COUNTING_DOWN ( __HANDLE__ ) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))

Indicates whether or not the TIM Counter is used as downcounter.

Parameters:
__HANDLE__,: TIM handle.
Return values:
False (Counter used as upcounter) or True (Counter used as downcounter)
Note:
This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder mode.

Definition at line 1376 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_MOE_DISABLE ( __HANDLE__ )
Value:
do { \
                          if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
                          { \
                            if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
                            { \
                              (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
                            } \
                            } \
                        } while(0U)

Disable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled

Definition at line 1226 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_Stop(), HAL_TIM_OnePulse_Stop_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY ( __HANDLE__ ) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)

Disable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None
Note:
The Main Output Enable of a timer instance is disabled unconditionally

Definition at line 1243 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_MOE_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

Enable the TIM main Output.

Parameters:
__HANDLE__,: TIM handle
Return values:
None

Definition at line 1201 of file stm32f1xx_hal_tim.h.

Referenced by HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), and HAL_TIMEx_PWMN_Start_IT().

#define __HAL_TIM_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)

Reset TIM handle state.

Parameters:
__HANDLE__,: TIM handle.
Return values:
None

Definition at line 1187 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_SET_AUTORELOAD | ( | __HANDLE__,
 |  | __AUTORELOAD__
 | ) |
Value:
do{                                                    \
                              (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
                              (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
                          } while(0U)

Sets the TIM Autoreload Register value on runtime without calling another time any Init function.

Parameters:
__HANDLE__,: TIM handle.
__AUTORELOAD__,: specifies the Counter register new value.
Return values:
None

Definition at line 1439 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_SET_CAPTUREPOLARITY | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __POLARITY__
 | ) |
Value:
do{                                                                     \
          TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
          TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
        }while(0U)

Sets the TIM Capture x input polarity on runtime.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__POLARITY__,: Polarity for TIx source
  • TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  • TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
Note:
The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
Return values:
None

Definition at line 1568 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_SET_CLOCKDIVISION | ( | __HANDLE__,
 |  | __CKD__
 | ) |
Value:
do{                                                             \
                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \
                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
                          } while(0U)

Sets the TIM Clock Division value on runtime without calling another time any Init function.

Parameters:
__HANDLE__,: TIM handle.
__CKD__,: specifies the clock division value. This parameter can be one of the following value:
  • TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  • TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  • TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
Return values:
None

Definition at line 1464 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_SET_COMPARE | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __COMPARE__
 | ) | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))

Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__COMPARE__,: specifies the Capture Compare register new value.
Return values:
None

Definition at line 1399 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_SET_COUNTER | ( | __HANDLE__,
 |  | __COUNTER__
 | ) | ((__HANDLE__)->Instance->CNT = (__COUNTER__))

Sets the TIM Counter Register value on runtime.

Parameters:
__HANDLE__,: TIM handle.
__COUNTER__,: specifies the Counter register new value.
Return values:
None

Definition at line 1422 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_SET_ICPRESCALER | ( | __HANDLE__,
 |  | __CHANNEL__,
 |  | __ICPSC__
 | ) |
Value:
do{                                                    \
                              TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
                              TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
                          } while(0U)

Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__ : TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
__ICPSC__,: specifies the Input Capture4 prescaler new value. This parameter can be one of the following values:
  • TIM_ICPSC_DIV1: no prescaler
  • TIM_ICPSC_DIV2: capture is done once every 2 events
  • TIM_ICPSC_DIV4: capture is done once every 4 events
  • TIM_ICPSC_DIV8: capture is done once every 8 events
Return values:
None

Definition at line 1500 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_SET_PRESCALER | ( | __HANDLE__,
 |  | __PRESC__
 | ) | ((__HANDLE__)->Instance->PSC = (__PRESC__))

Sets the TIM active prescaler register value on update event.

Parameters:
__HANDLE__,: TIM handle.
__PRESC__,: specifies the active prescaler register new value.
Return values:
None

Definition at line 1384 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_URS_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))

Reset the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__,: TIM handle.
Note:
When the USR bit of the TIMx_CR1 register is reset, any of the following events generate an update interrupt or DMA request (if enabled): (+) Counter overflow/underflow (+) Setting the UG bit (+) Update generation through the slave mode controller
Return values:
None

Definition at line 1549 of file stm32f1xx_hal_tim.h.

#define __HAL_TIM_URS_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))

Set the Update Request Source (URS) bit of the TIMx_CR1 register.

Parameters:
__HANDLE__,: TIM handle.
Note:
When the USR bit of the TIMx_CR1 register is set, only counter overflow/underflow generates an update interrupt or DMA request (if enabled)
Return values:
None

Definition at line 1535 of file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIMEx Private Functions

Functions
TIMEx Private Functions
TIMEx

Functions

static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Function Documentation

static void TIM_CCxNChannelCmd | ( | TIM_TypeDef * | TIMx,
 |  | uint32_t | Channel,
 |  | uint32_t | ChannelNState
 | ) |  | [static]

Enables or disables the TIM Capture Compare Channel xN.

Parameters:
TIMx | to select the TIM peripheral
Channel : specifies the TIM Channel This parameter can be one of the following values:
  • TIM_Channel_1: TIM Channel 1
  • TIM_Channel_2: TIM Channel 2
  • TIM_Channel_3: TIM Channel 3
ChannelNState | : specifies the TIM Channel CCxNE bit new state. This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
Return values:
None

Definition at line 1831 of file stm32f1xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), and HAL_TIMEx_PWMN_Stop_IT().

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 1758 of file stm32f1xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Timer Hall Sensor functions

Functions
Timer Hall Sensor functions
TIMEx Exported Functions

Timer Hall Sensor functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.

Detailed Description

Timer Hall Sensor functions.

  ==============================================================================
                      ##### Timer Hall Sensor functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Initialize and configure TIM HAL Sensor.
    (+) De-initialize TIM HAL Sensor.
    (+) Start the Hall Sensor Interface.
    (+) Stop the Hall Sensor Interface.
    (+) Start the Hall Sensor Interface and enable interrupts.
    (+) Stop the Hall Sensor Interface and disable interrupts.
    (+) Start the Hall Sensor Interface and enable DMA transfers.
    (+) Stop the Hall Sensor Interface and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit ( TIM_HandleTypeDef * htim )

DeInitializes the TIM Hall Sensor interface.

Parameters:
htim : TIM Hall Sensor handle
Return values:
HAL status

Definition at line 246 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspDeInit(), TIM_HandleTypeDef::Instance, and TIM_HandleTypeDef::State.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_HallSensor_InitTypeDef * | sConfig
 | ) |  |

Initializes the TIM Hall Sensor Interface and create the associated handle.

Parameters:
htim | : TIM Encoder Interface handle
sConfig | : TIM Hall Sensor configuration structure
Return values:
HAL status

Definition at line 167 of file stm32f1xx_hal_tim_ex.c.

References assert_param, TIM_Base_InitTypeDef::AutoReloadPreload, TIM_Base_InitTypeDef::ClockDivision, TIM_HallSensor_InitTypeDef::Commutation_Delay, TIM_Base_InitTypeDef::CounterMode, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, HAL_TIM_STATE_RESET, HAL_TIMEx_HallSensor_MspInit(), TIM_HallSensor_InitTypeDef::IC1Filter, TIM_HallSensor_InitTypeDef::IC1Polarity, TIM_HallSensor_InitTypeDef::IC1Prescaler, TIM_HandleTypeDef::Init, TIM_HandleTypeDef::Instance, IS_TIM_AUTORELOAD_PRELOAD, IS_TIM_CLOCKDIVISION_DIV, IS_TIM_COUNTER_MODE, IS_TIM_IC_FILTER, IS_TIM_IC_POLARITY, IS_TIM_IC_PRESCALER, TIM_HandleTypeDef::Lock, TIM_OC_InitTypeDef::OCFastMode, TIM_OC_InitTypeDef::OCIdleState, TIM_OC_InitTypeDef::OCMode, TIM_OC_InitTypeDef::OCNIdleState, TIM_OC_InitTypeDef::OCNPolarity, TIM_OC_InitTypeDef::OCPolarity, TIM_OC_InitTypeDef::Pulse, TIM_HandleTypeDef::State, TIM_Base_SetConfig(), TIM_ICSELECTION_TRC, TIM_OC2_SetConfig(), TIM_OCFAST_DISABLE, TIM_OCIDLESTATE_RESET, TIM_OCMODE_PWM2, TIM_OCNIDLESTATE_RESET, TIM_OCNPOLARITY_HIGH, TIM_OCPOLARITY_HIGH, TIM_SLAVEMODE_RESET, TIM_TI1_SetConfig(), TIM_TRGO_OC2REF, and TIM_TS_TI1F_ED.

void HAL_TIMEx_HallSensor_MspDeInit ( TIM_HandleTypeDef * htim )

DeInitializes TIM Hall Sensor MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 287 of file stm32f1xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_DeInit().

void HAL_TIMEx_HallSensor_MspInit ( TIM_HandleTypeDef * htim )

Initializes the TIM Hall Sensor MSP.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 273 of file stm32f1xx_hal_tim_ex.c.

Referenced by HAL_TIMEx_HallSensor_Init().

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface.

Parameters:
htim : TIM Hall Sensor handle
Return values:
HAL status

Definition at line 301 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim | : TIM Hall Sensor handle
pData | : The destination Buffer address.
Length | : The length of data to be transferred from TIM peripheral to memory.
Return values:
HAL status

Definition at line 393 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, TIM_DMA_CC1, TIM_DMA_ID_CC1, TIM_DMACaptureCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT ( TIM_HandleTypeDef * htim )

Starts the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim : TIM Hall Sensor handle
Return values:
HAL status

Definition at line 343 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_ENABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop ( TIM_HandleTypeDef * htim )

Stops the TIM Hall sensor Interface.

Parameters:
htim : TIM Hall Sensor handle
Return values:
HAL status

Definition at line 322 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), and TIM_CHANNEL_1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in DMA mode.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 440 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_DMA_CC1.

HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT ( TIM_HandleTypeDef * htim )

Stops the TIM Hall Sensor Interface in interrupt mode.

Parameters:
htim : TIM handle
Return values:
HAL status

Definition at line 367 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, assert_param, TIM_HandleTypeDef::Instance, TIM_CCx_DISABLE, TIM_CCxChannelCmd(), TIM_CHANNEL_1, and TIM_IT_CC1.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Timer Complementary Output Compare functions

Functions
Timer Complementary Output Compare functions
TIMEx Exported Functions

Timer Complementary Output Compare functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary Output Compare functions.

  ==============================================================================
              ##### Timer Complementary Output Compare functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary Output Compare/PWM.
    (+) Stop the Complementary Output Compare/PWM.
    (+) Start the Complementary Output Compare/PWM and enable interrupts.
    (+) Stop the Complementary Output Compare/PWM and disable interrupts.
    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OCN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation on the complementary output.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 500 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim | : TIM Output Compare handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | : The source Buffer address.
Length | : The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 702 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM OC handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 560 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 530 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in DMA mode on the complementary output.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 817 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM Output Compare handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 627 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Timer Complementary PWM functions

Functions
Timer Complementary PWM functions
TIMEx Exported Functions

Timer Complementary PWM functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.

Detailed Description

Timer Complementary PWM functions.

  ==============================================================================
                 ##### Timer Complementary PWM functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary PWM.
    (+) Stop the Complementary PWM.
    (+) Start the Complementary PWM and enable interrupts.
    (+) Stop the Complementary PWM and disable interrupts.
    (+) Start the Complementary PWM and enable DMA transfers.
    (+) Stop the Complementary PWM and disable DMA transfers.
    (+) Start the Complementary Input Capture measurement.
    (+) Stop the Complementary Input Capture.
    (+) Start the Complementary Input Capture and enable interrupts.
    (+) Stop the Complementary Input Capture and disable interrupts.
    (+) Start the Complementary Input Capture and enable DMA transfers.
    (+) Stop the Complementary Input Capture and disable DMA transfers.
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 917 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel,
 |  | uint32_t * | pData,
 |  | uint16_t | Length
 | ) |  |

Starts the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim | : TIM handle
Channel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
pData | : The source Buffer address.
Length | : The length of data to be transferred from memory to TIM peripheral
Return values:
HAL status

Definition at line 1118 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_DMA, __HAL_TIM_MOE_ENABLE, assert_param, HAL_DMA_Start_IT(), HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, TIM_DMA_CC4, TIM_DMA_ID_CC1, TIM_DMA_ID_CC2, TIM_DMA_ID_CC3, TIM_DMA_ID_CC4, TIM_DMADelayPulseCplt(), TIM_DMAError(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Starts the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 976 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE, __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 946 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the TIM PWM signal generation in DMA mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1233 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_DMA, __HAL_TIM_MOE_DISABLE, assert_param, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, TIM_HandleTypeDef::State, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_DMA_CC1, TIM_DMA_CC2, TIM_DMA_CC3, and TIM_DMA_CC4.

HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | Channel
 | ) |  |

Stops the PWM signal generation in interrupt mode on the complementary output.

Parameters:
htim : TIM handle
Channel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
HAL status

Definition at line 1043 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, TIM_IT_BREAK, TIM_IT_CC1, TIM_IT_CC2, TIM_IT_CC3, and TIM_IT_CC4.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Timer Complementary One Pulse functions

Functions
Timer Complementary One Pulse functions
TIMEx Exported Functions

Timer Complementary One Pulse functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Detailed Description

Timer Complementary One Pulse functions.

  ==============================================================================
                ##### Timer Complementary One Pulse functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Start the Complementary One Pulse generation.
    (+) Stop the Complementary One Pulse.
    (+) Start the Complementary One Pulse and enable interrupts.
    (+) Stop the Complementary One Pulse and disable interrupts.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation on the complemetary output.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1320 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be enabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1374 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, __HAL_TIM_MOE_ENABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_ENABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation on the complementary output.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1345 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, and TIM_CCxNChannelCmd().

HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | OutputChannel
 | ) |  |

Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.

Parameters:
htim : TIM One Pulse handle
OutputChannel : TIM Channel to be disabled This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
Return values:
HAL status

Definition at line 1405 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_DISABLE, __HAL_TIM_DISABLE_IT, __HAL_TIM_MOE_DISABLE, assert_param, TIM_HandleTypeDef::Instance, TIM_CCxN_DISABLE, TIM_CCxNChannelCmd(), TIM_IT_CC1, and TIM_IT_CC2.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
TIMEx Exported Functions

Peripheral Control functions. More...

Functions

HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.

Detailed Description

Peripheral Control functions.

  ==============================================================================
                    ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Configure the commutation event in case of use of the Hall sensor interface.
      (+) Configure Complementary channels, break features and dead time.
      (+) Configure Master synchronization.

Function Documentation

HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_BreakDeadTimeConfigTypeDef * | sBreakDeadTimeConfig
 | ) |  |

Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).

Parameters:
htim | : TIM handle
sBreakDeadTimeConfig | : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that contains the BDTR Register configuration information for the TIM peripheral.
Return values:
HAL status

Definition at line 1626 of file stm32f1xx_hal_tim_ex.c.

References assert_param, TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput, TIM_BreakDeadTimeConfigTypeDef::BreakPolarity, TIM_BreakDeadTimeConfigTypeDef::BreakState, TIM_BreakDeadTimeConfigTypeDef::DeadTime, TIM_HandleTypeDef::Instance, IS_TIM_AUTOMATIC_OUTPUT_STATE, IS_TIM_BREAK_POLARITY, IS_TIM_BREAK_STATE, IS_TIM_DEADTIME, IS_TIM_LOCK_LEVEL, IS_TIM_OSSI_STATE, IS_TIM_OSSR_STATE, TIM_BreakDeadTimeConfigTypeDef::LockLevel, TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode, and TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence.

Note:
: this function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim : TIM handle
InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource : the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1480 of file stm32f1xx_hal_tim_ex.c.

References assert_param, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with DMA.

Note:
: this function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
: The user should configure the DMA in his own software, in This function only the COMDE bit is set
Parameters:
htim : TIM handle
InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource : the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1582 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_DMA, assert_param, TIM_HandleTypeDef::hdma, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_DMA_COM, TIM_DMA_ID_COMMUTATION, TIM_DMAError(), TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, TIM_TS_ITR3, TIMEx_DMACommutationCplt(), __DMA_HandleTypeDef::XferCpltCallback, and __DMA_HandleTypeDef::XferErrorCallback.

HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT | ( | TIM_HandleTypeDef * | htim,
 |  | uint32_t | InputTrigger,
 |  | uint32_t | CommutationSource
 | ) |  |

Configure the TIM commutation event sequence with interrupt.

Note:
: this function is mandatory to use the commutation event in order to update the configuration at each commutation detection on the TRGI input of the Timer, the typical use of this feature is with the use of another Timer(interface Timer) configured in Hall sensor interface, this interface Timer will generate the commutation at its TRGO output (connected to Timer used in this function) each time the TI1 of the Interface Timer detect a commutation at its input TI1.
Parameters:
htim : TIM handle
InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor This parameter can be one of the following values:
  • TIM_TS_ITR0: Internal trigger 0 selected
  • TIM_TS_ITR1: Internal trigger 1 selected
  • TIM_TS_ITR2: Internal trigger 2 selected
  • TIM_TS_ITR3: Internal trigger 3 selected
  • TIM_TS_NONE: No trigger is needed
CommutationSource : the Commutation Event source This parameter can be one of the following values:
  • TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
  • TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
Return values:
HAL status

Definition at line 1529 of file stm32f1xx_hal_tim_ex.c.

References __HAL_TIM_ENABLE_IT, assert_param, TIM_HandleTypeDef::Instance, IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION, TIM_IT_COM, TIM_TS_ITR0, TIM_TS_ITR1, TIM_TS_ITR2, and TIM_TS_ITR3.

HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization | ( | TIM_HandleTypeDef * | htim,
 |  | TIM_MasterConfigTypeDef * | sMasterConfig
 | ) |  |

Configures the TIM in master mode.

Parameters:
htim | : TIM handle.
sMasterConfig | : pointer to a TIM_MasterConfigTypeDef structure that contains the selected trigger output (TRGO) and the Master/Slave mode.
Return values:
HAL status

Definition at line 1677 of file stm32f1xx_hal_tim_ex.c.

References assert_param, HAL_TIM_STATE_BUSY, HAL_TIM_STATE_READY, TIM_HandleTypeDef::Instance, IS_TIM_MSM_STATE, IS_TIM_TRGO_SOURCE, TIM_MasterConfigTypeDef::MasterOutputTrigger, TIM_MasterConfigTypeDef::MasterSlaveMode, and TIM_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Extension Callbacks functions

Functions
Extension Callbacks functions
TIMEx Exported Functions

Extension Callbacks functions. More...

Functions

__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

Extension Callbacks functions.

  ==============================================================================
                    ##### Extension Callbacks functions #####
  ==============================================================================
  [..]
    This section provides Extension TIM callback functions:
    (+) Timer Commutation callback
    (+) Timer Break callback

Function Documentation

void HAL_TIMEx_BreakCallback ( TIM_HandleTypeDef * htim )

Hall Break detection callback in non blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 1744 of file stm32f1xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler().

void HAL_TIMEx_CommutationCallback ( TIM_HandleTypeDef * htim )

Hall commutation changed callback in non blocking mode.

Parameters:
htim : TIM handle
Return values:
None

Definition at line 1730 of file stm32f1xx_hal_tim_ex.c.

Referenced by HAL_TIM_IRQHandler(), and TIMEx_DMACommutationCplt().

void TIMEx_DMACommutationCplt ( DMA_HandleTypeDef * hdma )

TIM DMA Commutation callback.

Parameters:
hdma : pointer to DMA handle.
Return values:
None

Definition at line 1758 of file stm32f1xx_hal_tim_ex.c.

References HAL_TIM_STATE_READY, HAL_TIMEx_CommutationCallback(), and TIM_HandleTypeDef::State.

Referenced by HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_WriteStart(), and HAL_TIMEx_ConfigCommutationEvent_DMA().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Extension Peripheral State functions

Functions
Extension Peripheral State functions
TIMEx Exported Functions

Extension Peripheral State functions. More...

Functions

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.

Detailed Description

Extension Peripheral State functions.

  ==============================================================================
                ##### Extension Peripheral State functions #####
  ==============================================================================
  [..]
    This subsection permit to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState ( TIM_HandleTypeDef * htim )

Return the TIM Hall Sensor interface state.

Parameters:
htim : TIM Hall Sensor handle
Return values:
HAL state

Definition at line 1795 of file stm32f1xx_hal_tim_ex.c.

References TIM_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_HallSensor_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_HallSensor_InitTypeDef Struct Reference
TIMEx Exported Types

TIM Hall sensor Configuration Structure definition. More...

#include <stm32f1xx_hal_tim_ex.h>

Data Fields

uint32_t | IC1Polarity
uint32_t | IC1Prescaler
uint32_t | IC1Filter
uint32_t | Commutation_Delay

Detailed Description

TIM Hall sensor Configuration Structure definition.

Definition at line 67 of file stm32f1xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_HallSensor_InitTypeDef::Commutation_Delay

Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF

Definition at line 78 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Filter

Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF

Definition at line 76 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Polarity

Specifies the active edge of the input signal. This parameter can be a value of TIM Input Capture Polarity

Definition at line 70 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

uint32_t TIM_HallSensor_InitTypeDef::IC1Prescaler

Specifies the Input Capture Prescaler. This parameter can be a value of TIM Input Capture Prescaler

Definition at line 73 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_HallSensor_Init().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim_ex.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_BreakDeadTimeConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_BreakDeadTimeConfigTypeDef Struct Reference
TIMEx Exported Types

TIM Break and Dead time configuration Structure definition. More...

#include <stm32f1xx_hal_tim_ex.h>

Data Fields

uint32_t | OffStateRunMode
uint32_t | OffStateIDLEMode
uint32_t | LockLevel
uint32_t | DeadTime
uint32_t | BreakState
uint32_t | BreakPolarity
uint32_t | AutomaticOutput

Detailed Description

TIM Break and Dead time configuration Structure definition.

Definition at line 90 of file stm32f1xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput

TIM Automatic Output Enable state This parameter can be a value of TIM Automatic Output Enable

Definition at line 104 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakPolarity

TIM Break input polarity This parameter can be a value of TIM Break Input Polarity

Definition at line 102 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::BreakState

TIM Break State This parameter can be a value of TIM Break Input Enable Disable

Definition at line 100 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::DeadTime

TIM dead Time This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF

Definition at line 98 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::LockLevel

TIM Lock level This parameter can be a value of TIM Lock level

Definition at line 96 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode

TIM off state in IDLE mode This parameter can be a value of TIM OSSI Off State Selection for Idle mode state

Definition at line 94 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

uint32_t TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode

TIM off state in run mode This parameter can be a value of TIM OSSR Off State Selection for Run mode state

Definition at line 92 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim_ex.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM_MasterConfigTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
TIM_MasterConfigTypeDef Struct Reference
TIMEx Exported Types

TIM Master configuration Structure definition. More...

#include <stm32f1xx_hal_tim_ex.h>

Data Fields

uint32_t | MasterOutputTrigger
uint32_t | MasterSlaveMode

Detailed Description

TIM Master configuration Structure definition.

Definition at line 115 of file stm32f1xx_hal_tim_ex.h.

Field Documentation

uint32_t TIM_MasterConfigTypeDef::MasterOutputTrigger

Trigger output (TRGO) selection This parameter can be a value of TIM Master Mode Selection

Definition at line 116 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

uint32_t TIM_MasterConfigTypeDef::MasterSlaveMode

Master/slave mode selection This parameter can be a value of TIM Master Slave Mode

Definition at line 118 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_MasterConfigSynchronization().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_tim_ex.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIMEx Clock Filter

Defines
TIMEx Clock Filter
TIMEx Exported Constants

Defines

#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)

Define Documentation

#define IS_TIM_DEADTIME ( DEADTIME ) ((DEADTIME) <= 0xFFU)

BreakDead Time

Definition at line 137 of file stm32f1xx_hal_tim_ex.h.

Referenced by HAL_TIMEx_ConfigBreakDeadTime().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIMEx

Modules | Defines
TIMEx
STM32F1xx_HAL_Driver

TIM Extended HAL module driver. More...

Modules

TIMEx Private Functions
TIMEx Exported Functions
TIMEx Exported Types
TIMEx Exported Constants

Defines

#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Sets the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Resets the TIM Output compare preload.

Detailed Description

TIM Extended HAL module driver.

Define Documentation

#define __HAL_TIM_DISABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
         ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
         ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
         ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))

Resets the TIM Output compare preload.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
None

Definition at line 178 of file stm32f1xx_hal_tim_ex.h.

#define __HAL_TIM_ENABLE_OCxPRELOAD | ( | __HANDLE__,
 |  | __CHANNEL__
 | ) |
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
         ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
         ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
         ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))

Sets the TIM Output compare preload.

Parameters:
__HANDLE__,: TIM handle.
__CHANNEL__,: TIM Channels to be configured. This parameter can be one of the following values:
  • TIM_CHANNEL_1: TIM Channel 1 selected
  • TIM_CHANNEL_2: TIM Channel 2 selected
  • TIM_CHANNEL_3: TIM Channel 3 selected
  • TIM_CHANNEL_4: TIM Channel 4 selected
Return values:
None

Definition at line 161 of file stm32f1xx_hal_tim_ex.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
UART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initializes the Multi-Processor mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitializes the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
UART MSP Init.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
UART MSP DeInit.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
            ##### Initialization and Configuration functions #####
  ==============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
    in asynchronous mode.
      (+) For the asynchronous mode only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity: If the parity is enabled, then the MSB bit of the data written
             in the data register is transmitted but is changed by the parity bit.
             Depending on the frame length defined by the M bit (8-bits or 9-bits),
             please refer to Reference manual for possible UART frame formats.
        (++) Hardware flow control
        (++) Receiver/transmitter modes
        (++) Over Sampling Method
    [..]
    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
    configuration procedures (details for the procedures are available in reference manuals
    (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_Init ( UART_HandleTypeDef * huart )

Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 326 of file stm32f1xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_WORD_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_HandleTypeDef::RxState, UART_SetConfig(), and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_LIN_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | BreakDetectLength
 | ) |  |

Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
BreakDetectLength,: Specifies the LIN break detection length. This parameter can be one of the following values:
  • UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
  • UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
Return values:
HAL status

Definition at line 387 of file stm32f1xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_LIN_BREAK_DETECT_LENGTH, IS_UART_LIN_OVERSAMPLING, IS_UART_LIN_WORD_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_HandleTypeDef::RxState, UART_SetConfig(), and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_MultiProcessor_Init | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t | Address,
 |  | uint32_t | WakeUpMethod
 | ) |  |

Initializes the Multi-Processor mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Address,: USART address
WakeUpMethod,: specifies the USART wake-up method. This parameter can be one of the following values:
  • UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
  • UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
Return values:
HAL status

Definition at line 455 of file stm32f1xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_ADDRESS, IS_UART_WAKEUPMETHOD, IS_UART_WORD_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_HandleTypeDef::RxState, UART_SetConfig(), and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_DeInit ( UART_HandleTypeDef * huart )

DeInitializes the UART peripheral.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 519 of file stm32f1xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspDeInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_RESET, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_Init ( UART_HandleTypeDef * huart )

Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 261 of file stm32f1xx_hal_uart.c.

References __HAL_UART_DISABLE, __HAL_UART_ENABLE, assert_param, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_MspInit(), HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, HAL_UART_STATE_RESET, UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_HARDWARE_FLOW_CONTROL, IS_UART_WORD_LENGTH, UART_HandleTypeDef::Lock, UART_InitTypeDef::OverSampling, UART_HandleTypeDef::RxState, UART_HWCONTROL_NONE, UART_SetConfig(), and UART_InitTypeDef::WordLength.

void HAL_UART_MspDeInit ( UART_HandleTypeDef * huart )

UART MSP DeInit.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 566 of file stm32f1xx_hal_uart.c.

Referenced by HAL_UART_DeInit().

void HAL_UART_MspInit ( UART_HandleTypeDef * huart )

UART MSP Init.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 551 of file stm32f1xx_hal_uart.c.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
UART Exported Functions

UART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stops the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
This function handles UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callbacks.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callbacks.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callbacks.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callbacks.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callbacks.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.

Detailed Description

UART Transmit and Receive functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the UART asynchronous
    and Half duplex data transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode: The communication is performed in polling mode.
            The HAL status of all data processing is returned by the same function
            after finishing transfer.
       (++) Non blocking mode: The communication is performed using Interrupts
            or DMA, these APIs return the HAL status.
            The end of the data processing will be indicated through the
            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.
            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
            will be executed respectively at the end of the transmit or receive process.
            The HAL_UART_ErrorCallback() user callback will be executed when
            a communication error is detected.

    (#) Blocking mode APIs are:
        (++) HAL_UART_Transmit()
        (++) HAL_UART_Receive()

    (#) Non Blocking mode APIs with Interrupt are:
        (++) HAL_UART_Transmit_IT()
        (++) HAL_UART_Receive_IT()
        (++) HAL_UART_IRQHandler()

    (#) Non Blocking mode functions with DMA are:
        (++) HAL_UART_Transmit_DMA()
        (++) HAL_UART_Receive_DMA()
        (++) HAL_UART_DMAPause()
        (++) HAL_UART_DMAResume()
        (++) HAL_UART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
        (++) HAL_UART_TxHalfCpltCallback()
        (++) HAL_UART_TxCpltCallback()
        (++) HAL_UART_RxHalfCpltCallback()
        (++) HAL_UART_RxCpltCallback()
        (++) HAL_UART_ErrorCallback()

    [..]
      (@) In the Half duplex communication, it is forbidden to run the transmit
          and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
          can't be useful.

Function Documentation

HAL_StatusTypeDef HAL_UART_Abort ( UART_HandleTypeDef * huart )

Abort ongoing transfers (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1161 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Abort_IT ( UART_HandleTypeDef * huart )

Abort ongoing transfers (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1312 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1758 of file stm32f1xx_hal_uart.c.

Referenced by HAL_UART_Abort_IT(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

HAL_StatusTypeDef HAL_UART_AbortReceive ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1267 of file stm32f1xx_hal_uart.c.

References HAL_DMA_Abort(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortReceive_IT ( UART_HandleTypeDef * huart )

Abort ongoing Receive transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1499 of file stm32f1xx_hal_uart.c.

References HAL_DMA_Abort_IT(), HAL_UART_AbortReceiveCpltCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_DMARxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortReceiveCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Receive Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1787 of file stm32f1xx_hal_uart.c.

Referenced by HAL_UART_AbortReceive_IT(), and UART_DMARxOnlyAbortCallback().

HAL_StatusTypeDef HAL_UART_AbortTransmit ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (blocking mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1225 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_AbortTransmit_IT ( UART_HandleTypeDef * huart )

Abort ongoing Transmit transfer (Interrupt mode).

Parameters:
huart UART handle.
Note:
This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1434 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort_IT(), HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::TxXferCount, UART_DMATxOnlyAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_UART_AbortTransmitCpltCallback ( UART_HandleTypeDef * huart )

UART Abort Complete callback.

Parameters:
huart UART handle.
Return values:
None

Definition at line 1772 of file stm32f1xx_hal_uart.c.

Referenced by HAL_UART_AbortTransmit_IT(), and UART_DMATxOnlyAbortCallback().

HAL_StatusTypeDef HAL_UART_DMAPause ( UART_HandleTypeDef * huart )

Pauses the DMA Transfer.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1036 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAResume ( UART_HandleTypeDef * huart )

Resumes the DMA Transfer.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1073 of file stm32f1xx_hal_uart.c.

References __HAL_UART_CLEAR_OREFLAG, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

HAL_StatusTypeDef HAL_UART_DMAStop ( UART_HandleTypeDef * huart )

Stops the DMA Transfer.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1109 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_DMA_Abort(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_EndRxTransfer(), and UART_EndTxTransfer().

void HAL_UART_ErrorCallback ( UART_HandleTypeDef * huart )

UART error callbacks.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1744 of file stm32f1xx_hal_uart.c.

Referenced by HAL_UART_IRQHandler(), UART_DMAAbortOnError(), and UART_DMAError().

void HAL_UART_IRQHandler ( UART_HandleTypeDef * huart )

This function handles UART interrupt request.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1557 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_UART_ERROR_FE, HAL_UART_ERROR_NE, HAL_UART_ERROR_NONE, HAL_UART_ERROR_ORE, HAL_UART_ERROR_PE, HAL_UART_ErrorCallback(), UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_DMAAbortOnError(), UART_EndRxTransfer(), UART_EndTransmit_IT(), UART_Receive_IT(), UART_Transmit_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_UART_Receive | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 727 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, UART_FLAG_RXNE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Receive_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Note:
When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
Return values:
HAL status

Definition at line 969 of file stm32f1xx_hal_uart.c.

References __HAL_UART_CLEAR_OREFLAG, UART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferSize, UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Receive_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 856 of file stm32f1xx_hal_uart.c.

References __HAL_UART_ENABLE_IT, UART_HandleTypeDef::ErrorCode, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::RxXferSize, UART_IT_ERR, UART_IT_PE, and UART_IT_RXNE.

void HAL_UART_RxCpltCallback ( UART_HandleTypeDef * huart )

Rx Transfer completed callbacks.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1714 of file stm32f1xx_hal_uart.c.

Referenced by UART_DMAReceiveCplt(), and UART_Receive_IT().

void HAL_UART_RxHalfCpltCallback ( UART_HandleTypeDef * huart )

Rx Half Transfer completed callbacks.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1729 of file stm32f1xx_hal_uart.c.

Referenced by UART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_UART_Transmit | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Sends an amount of data in blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 645 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_FLAG_TC, UART_FLAG_TXE, UART_PARITY_NONE, UART_WaitOnFlagUntilTimeout(), UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_UART_Transmit_DMA | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Sends an amount of data in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 904 of file stm32f1xx_hal_uart.c.

References __HAL_UART_CLEAR_FLAG, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_DMA_Start_IT(), HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::Instance, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, UART_DMAError(), UART_DMATransmitCplt(), UART_DMATxHalfCplt(), UART_FLAG_TC, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_UART_Transmit_IT | ( | UART_HandleTypeDef * | huart,
 |  | uint8_t * | pData,
 |  | uint16_t | Size
 | ) |  |

Sends an amount of data in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
pData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 815 of file stm32f1xx_hal_uart.c.

References __HAL_UART_ENABLE_IT, UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_NONE, HAL_UART_STATE_BUSY_TX, HAL_UART_STATE_READY, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_HandleTypeDef::TxXferSize, and UART_IT_TXE.

void HAL_UART_TxCpltCallback ( UART_HandleTypeDef * huart )

Tx Transfer completed callbacks.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1684 of file stm32f1xx_hal_uart.c.

Referenced by UART_DMATransmitCplt(), and UART_EndTransmit_IT().

void HAL_UART_TxHalfCpltCallback ( UART_HandleTypeDef * huart )

Tx Half Transfer completed callbacks.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 1699 of file stm32f1xx_hal_uart.c.

Referenced by UART_DMATxHalfCplt().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral Control functions

Functions
Peripheral Control functions
UART Exported Functions

UART control functions. More...

Functions

HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmits break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enters the UART in mute mode.
HAL_StatusTypeDef | HAL_MultiProcessor_ExitMuteMode (UART_HandleTypeDef *huart)
Exits the UART mute mode: wake up software.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enables the UART transmitter and disables the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enables the UART receiver and disables the UART transmitter.

Detailed Description

UART control functions.

  ==============================================================================
                      ##### Peripheral Control functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to control the UART:
    (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
    (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
    (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
    (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode

Function Documentation

HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver ( UART_HandleTypeDef * huart )

Enables the UART receiver and disables the UART transmitter.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1942 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter ( UART_HandleTypeDef * huart )

Enables the UART transmitter and disables the UART receiver.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1907 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_LIN_SendBreak ( UART_HandleTypeDef * huart )

Transmits break characters.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1826 of file stm32f1xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode ( UART_HandleTypeDef * huart )

Enters the UART in mute mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1853 of file stm32f1xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode ( UART_HandleTypeDef * huart )

Exits the UART mute mode: wake up software.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 1880 of file stm32f1xx_hal_uart.c.

References assert_param, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
UART Exported Functions

UART State and Errors functions. More...

Functions

HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Returns the UART state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART error code.

Detailed Description

UART State and Errors functions.

  ==============================================================================
                 ##### Peripheral State and Errors functions #####
  ==============================================================================
 [..]
   This subsection provides a set of functions allowing to return the State of
   UART communication process, return Peripheral Errors occurred during communication
   process
   (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.

Function Documentation

uint32_t HAL_UART_GetError ( UART_HandleTypeDef * huart )

Return the UART error code.

Parameters:
huart : pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART.
Return values:
UART Error Code

Definition at line 2014 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode.

HAL_UART_StateTypeDef HAL_UART_GetState ( UART_HandleTypeDef * huart )

Returns the UART state.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL state

Definition at line 1999 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::gState, and UART_HandleTypeDef::RxState.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Exported Functions

Modules | Functions
UART Exported Functions
UART

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

UART Transmit and Receive functions.

Peripheral Control functions

UART control functions.

Peripheral State and Errors functions

UART State and Errors functions.

Functions

static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles UART Communication Timeout.
static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Sends an amount of data in non blocking mode.
static HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receives an amount of data in non blocking mode.
static void | UART_SetConfig (UART_HandleTypeDef *huart)
Configures the UART peripheral.

Function Documentation

static void UART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2206 of file stm32f1xx_hal_uart.c.

References HAL_UART_ErrorCallback(), UART_HandleTypeDef::RxXferCount, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_IRQHandler().

static void UART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA UART communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2108 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_ERROR_DMA, HAL_UART_ErrorCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, UART_EndRxTransfer(), and UART_EndTxTransfer().

Referenced by HAL_UART_Receive_DMA(), and HAL_UART_Transmit_DMA().

static void UART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2069 of file stm32f1xx_hal_uart.c.

References HAL_UART_RxCpltCallback(), HAL_UART_STATE_READY, __DMA_HandleTypeDef::Instance, UART_HandleTypeDef::Instance, UART_HandleTypeDef::RxState, and UART_HandleTypeDef::RxXferCount.

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2261 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2097 of file stm32f1xx_hal_uart.c.

References HAL_UART_RxHalfCpltCallback().

Referenced by HAL_UART_Receive_DMA().

static void UART_DMARxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2320 of file stm32f1xx_hal_uart.c.

References HAL_UART_AbortReceiveCpltCallback(), HAL_UART_STATE_READY, UART_HandleTypeDef::RxState, and UART_HandleTypeDef::RxXferCount.

Referenced by HAL_UART_AbortReceive_IT().

static void UART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 2028 of file stm32f1xx_hal_uart.c.

References HAL_UART_TxCpltCallback(), __DMA_HandleTypeDef::Instance, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2223 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::ErrorCode, UART_HandleTypeDef::gState, HAL_UART_AbortCpltCallback(), HAL_UART_ERROR_NONE, HAL_UART_STATE_READY, UART_HandleTypeDef::hdmarx, UART_HandleTypeDef::hdmatx, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_UART_Abort_IT().

static void UART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA UART transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 2057 of file stm32f1xx_hal_uart.c.

References HAL_UART_TxHalfCpltCallback().

Referenced by HAL_UART_Transmit_DMA().

static void UART_DMATxOnlyAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 2299 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_AbortTransmitCpltCallback(), HAL_UART_STATE_READY, and UART_HandleTypeDef::TxXferCount.

Referenced by HAL_UART_AbortTransmit_IT().

static void UART_EndRxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 2190 of file stm32f1xx_hal_uart.c.

References HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

Referenced by HAL_UART_DMAStop(), HAL_UART_IRQHandler(), and UART_DMAError().

static HAL_StatusTypeDef UART_EndTransmit_IT ( UART_HandleTypeDef * huart ) [static]

Wraps up transmission in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2386 of file stm32f1xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, UART_HandleTypeDef::gState, HAL_UART_STATE_READY, HAL_UART_TxCpltCallback(), and UART_IT_TC.

Referenced by HAL_UART_IRQHandler().

static void UART_EndTxTransfer ( UART_HandleTypeDef * huart ) [static]

End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).

Parameters:
huart,: UART handle.
Return values:
None

Definition at line 2176 of file stm32f1xx_hal_uart.c.

References UART_HandleTypeDef::gState, HAL_UART_STATE_READY, and UART_HandleTypeDef::Instance.

Referenced by HAL_UART_DMAStop(), and UART_DMAError().

static HAL_StatusTypeDef UART_Receive_IT ( UART_HandleTypeDef * huart ) [static]

Receives an amount of data in non blocking mode.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2404 of file stm32f1xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, HAL_UART_RxCpltCallback(), HAL_UART_STATE_BUSY_RX, HAL_UART_STATE_READY, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::pRxBuffPtr, UART_HandleTypeDef::RxState, UART_HandleTypeDef::RxXferCount, UART_IT_ERR, UART_IT_PE, UART_IT_RXNE, UART_PARITY_NONE, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

static void UART_SetConfig ( UART_HandleTypeDef * huart ) [static]

Configures the UART peripheral.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
None

Definition at line 2468 of file stm32f1xx_hal_uart.c.

References assert_param, UART_InitTypeDef::BaudRate, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), UART_InitTypeDef::HwFlowCtl, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, IS_UART_BAUDRATE, IS_UART_MODE, IS_UART_PARITY, IS_UART_STOPBITS, UART_InitTypeDef::Mode, UART_InitTypeDef::OverSampling, UART_InitTypeDef::Parity, UART_InitTypeDef::StopBits, UART_BRR_SAMPLING16, UART_BRR_SAMPLING8, and UART_InitTypeDef::WordLength.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

static HAL_StatusTypeDef UART_Transmit_IT ( UART_HandleTypeDef * huart ) [static]

Sends an amount of data in non blocking mode.

Parameters:
huart,: Pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Return values:
HAL status

Definition at line 2339 of file stm32f1xx_hal_uart.c.

References __HAL_UART_DISABLE_IT, __HAL_UART_ENABLE_IT, UART_HandleTypeDef::gState, HAL_UART_STATE_BUSY_TX, UART_HandleTypeDef::Init, UART_HandleTypeDef::Instance, UART_InitTypeDef::Parity, UART_HandleTypeDef::pTxBuffPtr, UART_HandleTypeDef::TxXferCount, UART_IT_TC, UART_IT_TXE, UART_PARITY_NONE, UART_WORDLENGTH_9B, and UART_InitTypeDef::WordLength.

Referenced by HAL_UART_IRQHandler().

static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout | ( | UART_HandleTypeDef * | huart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles UART Communication Timeout.

Parameters:
huart,: pointer to a UART_HandleTypeDef structure that contains the configuration information for the specified UART module.
Flag,: specifies the UART flag to check.
Status,: The new Flag status (SET or RESET).
Tickstart Tick start value
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 2143 of file stm32f1xx_hal_uart.c.

References __HAL_UART_GET_FLAG, UART_HandleTypeDef::gState, HAL_GetTick(), HAL_UART_STATE_READY, UART_HandleTypeDef::Instance, and UART_HandleTypeDef::RxState.

Referenced by HAL_UART_Receive(), and HAL_UART_Transmit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Exported Types

Data Structures | Enumerations
UART Exported Types
UART

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00U, HAL_UART_STATE_READY = 0x20U, HAL_UART_STATE_BUSY = 0x24U, HAL_UART_STATE_BUSY_TX = 0x21U,
HAL_UART_STATE_BUSY_RX = 0x22U, HAL_UART_STATE_BUSY_TX_RX = 0x23U, HAL_UART_STATE_TIMEOUT = 0xA0U, HAL_UART_STATE_ERROR = 0xE0U
}
HAL UART State structures definition. More...

Enumeration Type Documentation

enum HAL_UART_StateTypeDef

HAL UART State structures definition.

Note:
HAL UART State value is a combination of 2 different substates: gState and RxState.
  • gState contains UART state information related to global Handle management and also information related to Tx operations. gState value coding follow below described bitmap : b7-b6 Error information 00 : No Error 01 : (Not Used) 10 : Timeout 11 : Error b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized. HAL UART Init function already called) b4-b3 (not used) xx : Should be set to 00 b2 Intrinsic process state 0 : Ready 1 : Busy (IP busy with some configuration or internal operations) b1 (not used) x : Should be set to 0 b0 Tx state 0 : Ready (no Tx operation ongoing) 1 : Busy (Tx operation ongoing)
  • RxState contains information related to Rx operations. RxState value coding follow below described bitmap : b7-b6 (not used) xx : Should be set to 00 b5 IP initilisation status 0 : Reset (IP not initialized) 1 : Init done (IP not initialized) b4-b2 (not used) xxx : Should be set to 000 b1 Rx state 0 : Ready (no Rx operation ongoing) 1 : Busy (Rx operation ongoing) b0 (not used) x : Should be set to 0.
Enumerator:
HAL_UART_STATE_RESET

Peripheral is not yet Initialized Value is allowed for gState and RxState

HAL_UART_STATE_READY

Peripheral Initialized and ready for use Value is allowed for gState and RxState

HAL_UART_STATE_BUSY

an internal process is ongoing Value is allowed for gState only

HAL_UART_STATE_BUSY_TX

Data Transmission process is ongoing Value is allowed for gState only

HAL_UART_STATE_BUSY_RX

Data Reception process is ongoing Value is allowed for RxState only

HAL_UART_STATE_BUSY_TX_RX

Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. Value is result of combination (Or) between gState and RxState values

HAL_UART_STATE_TIMEOUT

Timeout state Value is allowed for gState only

HAL_UART_STATE_ERROR

Error Value is allowed for gState only

Definition at line 135 of file stm32f1xx_hal_uart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_InitTypeDef Struct Reference
UART Exported Types

UART Init Structure definition. More...

#include <stm32f1xx_hal_uart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | HwFlowCtl
uint32_t | OverSampling

Detailed Description

UART Init Structure definition.

Definition at line 65 of file stm32f1xx_hal_uart.h.

Field Documentation

uint32_t UART_InitTypeDef::BaudRate

This member configures the UART communication baud rate. The baud rate is computed using the following formula:

  • IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate)))
  • FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5

Definition at line 67 of file stm32f1xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::HwFlowCtl

Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of UART Hardware Flow Control

Definition at line 88 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of UART Transfer Mode

Definition at line 85 of file stm32f1xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::OverSampling

Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). This parameter can be a value of UART Over Sampling. This feature is only available on STM32F100xx family, so OverSampling parameter should always be set to 16.

Definition at line 91 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Init(), and UART_SetConfig().

uint32_t UART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of UART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 78 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

uint32_t UART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of UART Number of Stop Bits

Definition at line 75 of file stm32f1xx_hal_uart.h.

Referenced by UART_SetConfig().

uint32_t UART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of UART Word Length

Definition at line 72 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_uart.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
UART_HandleTypeDef Struct Reference
UART Exported Types

UART handle Structure definition. More...

#include <stm32f1xx_hal_uart.h>

Data Fields

USART_TypeDef * | Instance
UART_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_UART_StateTypeDef | gState
__IO HAL_UART_StateTypeDef | RxState
__IO uint32_t | ErrorCode

Detailed Description

UART handle Structure definition.

Definition at line 159 of file stm32f1xx_hal_uart.h.

Field Documentation

__IO uint32_t UART_HandleTypeDef::ErrorCode

UART Error code

Definition at line 190 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_DeInit(), HAL_UART_GetError(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAError(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::gState

UART state information related to global Handle management and also related to Tx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 183 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_EnterMuteMode(), HAL_MultiProcessor_ExitMuteMode(), HAL_MultiProcessor_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), UART_EndTransmit_IT(), UART_EndTxTransfer(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmarx

UART Rx DMA Handle parameters

Definition at line 179 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DMAStop(), HAL_UART_IRQHandler(), HAL_UART_Receive_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

DMA_HandleTypeDef* UART_HandleTypeDef::hdmatx

UART Tx DMA Handle parameters

Definition at line 177 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DMAStop(), HAL_UART_Transmit_DMA(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

UART_InitTypeDef UART_HandleTypeDef::Init

UART communication parameters

Definition at line 163 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), UART_SetConfig(), and UART_Transmit_IT().

USART_TypeDef* UART_HandleTypeDef::Instance

UART registers base address

Definition at line 161 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_EnableReceiver(), HAL_HalfDuplex_EnableTransmitter(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_EnterMuteMode(), HAL_MultiProcessor_ExitMuteMode(), HAL_MultiProcessor_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMATransmitCplt(), UART_EndRxTransfer(), UART_EndTxTransfer(), UART_Receive_IT(), UART_SetConfig(), UART_Transmit_IT(), and UART_WaitOnFlagUntilTimeout().

HAL_LockTypeDef UART_HandleTypeDef::Lock

Locking object

Definition at line 181 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

uint8_t* UART_HandleTypeDef::pRxBuffPtr

Pointer to UART Rx transfer Buffer

Definition at line 171 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), and UART_Receive_IT().

uint8_t* UART_HandleTypeDef::pTxBuffPtr

Pointer to UART Tx transfer Buffer

Definition at line 165 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), and UART_Transmit_IT().

__IO HAL_UART_StateTypeDef UART_HandleTypeDef::RxState

UART state information related to Rx operations. This parameter can be a value of HAL_UART_StateTypeDef

Definition at line 187 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_DeInit(), HAL_UART_DMAPause(), HAL_UART_DMAResume(), HAL_UART_DMAStop(), HAL_UART_GetState(), HAL_UART_Init(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), UART_EndRxTransfer(), UART_Receive_IT(), and UART_WaitOnFlagUntilTimeout().

__IO uint16_t UART_HandleTypeDef::RxXferCount

UART Rx Transfer Counter

Definition at line 175 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortReceive(), HAL_UART_AbortReceive_IT(), HAL_UART_Receive(), HAL_UART_Receive_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMAReceiveCplt(), UART_DMARxAbortCallback(), UART_DMARxOnlyAbortCallback(), UART_DMATxAbortCallback(), and UART_Receive_IT().

uint16_t UART_HandleTypeDef::RxXferSize

UART Rx Transfer size

Definition at line 173 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Receive_DMA(), and HAL_UART_Receive_IT().

__IO uint16_t UART_HandleTypeDef::TxXferCount

UART Tx Transfer Counter

Definition at line 169 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_AbortTransmit(), HAL_UART_AbortTransmit_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMAAbortOnError(), UART_DMAError(), UART_DMARxAbortCallback(), UART_DMATransmitCplt(), UART_DMATxAbortCallback(), UART_DMATxOnlyAbortCallback(), and UART_Transmit_IT().

uint16_t UART_HandleTypeDef::TxXferSize

UART Tx Transfer size

Definition at line 167 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), and HAL_UART_Transmit_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_uart.h
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Error Code

Defines
UART Error Code
UART Exported constants

Defines

#define | HAL_UART_ERROR_NONE 0x00000000U
#define | HAL_UART_ERROR_PE 0x00000001U
#define | HAL_UART_ERROR_NE 0x00000002U
#define | HAL_UART_ERROR_FE 0x00000004U
#define | HAL_UART_ERROR_ORE 0x00000008U
#define | HAL_UART_ERROR_DMA 0x00000010U

Define Documentation

#define HAL_UART_ERROR_DMA 0x00000010U

DMA transfer error

Definition at line 210 of file stm32f1xx_hal_uart.h.

Referenced by UART_DMAError().

#define HAL_UART_ERROR_FE 0x00000004U

Frame error

Definition at line 208 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_NE 0x00000002U

Noise error

Definition at line 207 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_NONE 0x00000000U

No error

Definition at line 205 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), HAL_UART_Abort(), HAL_UART_Abort_IT(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_UART_IRQHandler(), HAL_UART_Receive(), HAL_UART_Receive_DMA(), HAL_UART_Receive_IT(), HAL_UART_Transmit(), HAL_UART_Transmit_DMA(), HAL_UART_Transmit_IT(), UART_DMARxAbortCallback(), and UART_DMATxAbortCallback().

#define HAL_UART_ERROR_ORE 0x00000008U

Overrun error

Definition at line 209 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

#define HAL_UART_ERROR_PE 0x00000001U

Parity error

Definition at line 206 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_IRQHandler().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Word Length

Defines
UART Word Length
UART Exported constants

Defines

#define | UART_WORDLENGTH_8B 0x00000000U
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define UART_WORDLENGTH_8B 0x00000000U

Definition at line 218 of file stm32f1xx_hal_uart.h.

#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Definition at line 219 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Number of Stop Bits

Defines
UART Number of Stop Bits
UART Exported constants

Defines

#define | UART_STOPBITS_1 0x00000000U
#define | UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Define Documentation

#define UART_STOPBITS_1 0x00000000U

Definition at line 227 of file stm32f1xx_hal_uart.h.

#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Definition at line 228 of file stm32f1xx_hal_uart.h.

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STM32F103xB HAL User Manual: UART Parity

Defines
UART Parity
UART Exported constants

Defines

#define | UART_PARITY_NONE 0x00000000U
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 237 of file stm32f1xx_hal_uart.h.

#define UART_PARITY_NONE 0x00000000U

Definition at line 236 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Receive(), HAL_UART_Transmit(), UART_Receive_IT(), and UART_Transmit_IT().

#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 238 of file stm32f1xx_hal_uart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Hardware Flow Control

Defines
UART Hardware Flow Control
UART Exported constants

Defines

#define | UART_HWCONTROL_NONE 0x00000000U
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Define Documentation

#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)

Definition at line 248 of file stm32f1xx_hal_uart.h.

#define UART_HWCONTROL_NONE 0x00000000U

Definition at line 246 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)

Definition at line 247 of file stm32f1xx_hal_uart.h.

#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))

Definition at line 249 of file stm32f1xx_hal_uart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Transfer Mode

Defines
UART Transfer Mode
UART Exported constants

Defines

#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define UART_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 257 of file stm32f1xx_hal_uart.h.

#define UART_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 258 of file stm32f1xx_hal_uart.h.

#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 259 of file stm32f1xx_hal_uart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART State

Defines
UART State
UART Exported constants

Defines

#define | UART_STATE_DISABLE 0x00000000U
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Define Documentation

#define UART_STATE_DISABLE 0x00000000U

Definition at line 267 of file stm32f1xx_hal_uart.h.

#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)

Definition at line 268 of file stm32f1xx_hal_uart.h.

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STM32F103xB HAL User Manual: UART Over Sampling

Defines
UART Over Sampling
UART Exported constants

Defines

#define UART_OVERSAMPLING_16 0x00000000U

Define Documentation

#define UART_OVERSAMPLING_16 0x00000000U

Definition at line 277 of file stm32f1xx_hal_uart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART LIN Break Detection Length

Defines
UART LIN Break Detection Length
UART Exported constants

Defines

#define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)

Define Documentation

#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U

Definition at line 289 of file stm32f1xx_hal_uart.h.

#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)

Definition at line 290 of file stm32f1xx_hal_uart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Wakeup Functions

Defines
UART Wakeup Functions
UART Exported constants

Defines

#define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)

Define Documentation

#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)

Definition at line 298 of file stm32f1xx_hal_uart.h.

#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U

Definition at line 297 of file stm32f1xx_hal_uart.h.

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STM32F103xB HAL User Manual: UART FLags

Defines
UART FLags
UART Exported constants

Elements values convention: 0xXXXX. More...

Defines

#define | UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
#define | UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
#define | UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define | UART_FLAG_TC ((uint32_t)USART_SR_TC)
#define | UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define | UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define | UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define | UART_FLAG_NE ((uint32_t)USART_SR_NE)
#define | UART_FLAG_FE ((uint32_t)USART_SR_FE)
#define | UART_FLAG_PE ((uint32_t)USART_SR_PE)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the SR register

Define Documentation

#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)

Definition at line 308 of file stm32f1xx_hal_uart.h.

#define UART_FLAG_FE ((uint32_t)USART_SR_FE)

Definition at line 316 of file stm32f1xx_hal_uart.h.

#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)

Definition at line 313 of file stm32f1xx_hal_uart.h.

#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)

Definition at line 309 of file stm32f1xx_hal_uart.h.

#define UART_FLAG_NE ((uint32_t)USART_SR_NE)

Definition at line 315 of file stm32f1xx_hal_uart.h.

#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)

Definition at line 314 of file stm32f1xx_hal_uart.h.

#define UART_FLAG_PE ((uint32_t)USART_SR_PE)

Definition at line 317 of file stm32f1xx_hal_uart.h.

#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)

Definition at line 312 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Receive().

#define UART_FLAG_TC ((uint32_t)USART_SR_TC)

Definition at line 311 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Transmit(), and HAL_UART_Transmit_DMA().

#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)

Definition at line 310 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Transmit().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Interrupt Definitions

Defines
UART Interrupt Definitions
UART Exported constants

Elements values convention: 0xY000XXXX. More...

Defines

#define | UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Detailed Description

Elements values convention: 0xY000XXXX.

  • XXXX : Interrupt mask (16 bits) in the Y register
  • Y : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register

Define Documentation

#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))

Definition at line 340 of file stm32f1xx_hal_uart.h.

#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Definition at line 341 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Receive_IT(), and UART_Receive_IT().

#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))

Definition at line 336 of file stm32f1xx_hal_uart.h.

#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))

Definition at line 338 of file stm32f1xx_hal_uart.h.

#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))

Definition at line 332 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Receive_IT(), and UART_Receive_IT().

#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))

Definition at line 335 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Receive_IT(), and UART_Receive_IT().

#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))

Definition at line 334 of file stm32f1xx_hal_uart.h.

Referenced by UART_EndTransmit_IT(), and UART_Transmit_IT().

#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))

Definition at line 333 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Transmit_IT(), and UART_Transmit_IT().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Exported Macros

Defines
UART Exported Macros
UART

Defines

#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle gstate & RxState.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flushs the UART DR register.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified UART flag is set or not.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clears the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clears the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clears the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clears the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clears the UART IDLE pending flag.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.

Define Documentation

#define __HAL_UART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)

Clears the UART FE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 433 of file stm32f1xx_hal_uart.h.

#define __HAL_UART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clears the specified UART pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
  • UART_FLAG_LBD: LIN Break detection flag.
  • UART_FLAG_TC: Transmission Complete flag.
  • UART_FLAG_RXNE: Receive data register not empty flag.
Note:
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register followed by a read operation to USART_DR register.
RXNE flag can be also cleared by a read to the USART_DR register.
TC flag can be also cleared by software sequence: a read operation to USART_SR register followed by a write operation to USART_DR register.
TXE flag is cleared only by a write to the USART_DR register.

Definition at line 413 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Transmit_DMA().

#define __HAL_UART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)

Clears the UART IDLE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 454 of file stm32f1xx_hal_uart.h.

#define __HAL_UART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)

Clears the UART NE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 440 of file stm32f1xx_hal_uart.h.

#define __HAL_UART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)

Clears the UART ORE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 447 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_DMAResume(), and HAL_UART_Receive_DMA().

#define __HAL_UART_CLEAR_PEFLAG ( __HANDLE__ )
Value:
do{                                           \
    __IO uint32_t tmpreg = 0x00U;               \
    tmpreg = (__HANDLE__)->Instance->SR;        \
    tmpreg = (__HANDLE__)->Instance->DR;        \
    UNUSED(tmpreg);                             \
  } while(0U)

Clears the UART PE pending flag.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 420 of file stm32f1xx_hal_uart.h.

#define __HAL_UART_DISABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

Disable UART.

Parameters:
__HANDLE__,: specifies the UART Handle.

Definition at line 609 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

#define __HAL_UART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))

Disable the specified UART interrupt.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
__INTERRUPT__,: specifies the UART interrupt source to disable. This parameter can be one of the following values:
  • UART_IT_CTS: CTS change interrupt
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_PE: Parity Error interrupt
  • UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)

Definition at line 490 of file stm32f1xx_hal_uart.h.

Referenced by UART_EndTransmit_IT(), UART_Receive_IT(), and UART_Transmit_IT().

#define __HAL_UART_ENABLE ( __HANDLE__ ) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

Enable UART.

Parameters:
__HANDLE__,: specifies the UART Handle.

Definition at line 604 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

#define __HAL_UART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))

Enable the specified UART interrupt.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
__INTERRUPT__,: specifies the UART interrupt source to enable. This parameter can be one of the following values:
  • UART_IT_CTS: CTS change interrupt
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_PE: Parity Error interrupt
  • UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)

Definition at line 471 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Receive_IT(), HAL_UART_Transmit_IT(), and UART_Transmit_IT().

#define __HAL_UART_FLUSH_DRREGISTER ( __HANDLE__ ) ((__HANDLE__)->Instance->DR)

Flushs the UART DR register.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 370 of file stm32f1xx_hal_uart.h.

#define __HAL_UART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Checks whether the specified UART flag is set or not.

Parameters:
__HANDLE__,: specifies the UART Handle. This parameter can be UARTx where x: 1, 2, 3, 4 or 5 to select the USART or UART peripheral.
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
  • UART_FLAG_LBD: LIN Break detection flag
  • UART_FLAG_TXE: Transmit data register empty flag
  • UART_FLAG_TC: Transmission Complete flag
  • UART_FLAG_RXNE: Receive data register not empty flag
  • UART_FLAG_IDLE: Idle Line detection flag
  • UART_FLAG_ORE: OverRun Error flag
  • UART_FLAG_NE: Noise Error flag
  • UART_FLAG_FE: Framing Error flag
  • UART_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 390 of file stm32f1xx_hal_uart.h.

Referenced by UART_WaitOnFlagUntilTimeout().

#define __HAL_UART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
(((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))

Checks whether the specified UART interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).
__IT__,: specifies the UART interrupt source to check. This parameter can be one of the following values:
  • UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
  • UART_IT_LBD: LIN Break detection interrupt
  • UART_IT_TXE: Transmit Data Register empty interrupt
  • UART_IT_TC: Transmission complete interrupt
  • UART_IT_RXNE: Receive Data register not empty interrupt
  • UART_IT_IDLE: Idle line detection interrupt
  • UART_IT_ERR: Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 509 of file stm32f1xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_DISABLE ( __HANDLE__ )
Value:
do{                                                       \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
  } while(0U)

Disable CTS flow control This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be any USARTx (supporting the HW Flow control feature). It is used to select the USART peripheral (USART availability and x value depending on device).

Definition at line 544 of file stm32f1xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_CTS_ENABLE ( __HANDLE__ )
Value:
do{                                                      \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
  } while(0U)

Enable CTS flow control This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying CTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be any USARTx (supporting the HW Flow control feature). It is used to select the USART peripheral (USART availability and x value depending on device).

Definition at line 525 of file stm32f1xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_DISABLE ( __HANDLE__ )
Value:
do{                                                      \
    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
  } while(0U)

Disable RTS flow control This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be any USARTx (supporting the HW Flow control feature). It is used to select the USART peripheral (USART availability and x value depending on device).

Definition at line 582 of file stm32f1xx_hal_uart.h.

#define __HAL_UART_HWCONTROL_RTS_ENABLE ( __HANDLE__ )
Value:
do{                                                     \
    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
  } while(0U)

Enable RTS flow control This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.

As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

Note:
As macro is expected to be used for modifying RTS Hw flow control feature activation, without need for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
  • UART instance should have already been initialised (through call of HAL_UART_Init() )
  • macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
Parameters:
__HANDLE__,: specifies the UART Handle. The Handle Instance can be any USARTx (supporting the HW Flow control feature). It is used to select the USART peripheral (USART availability and x value depending on device).

Definition at line 563 of file stm32f1xx_hal_uart.h.

#define __HAL_UART_RESET_HANDLE_STATE ( __HANDLE__ )
Value:
do{                                                   \
                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
                                                     } while(0U)

Reset UART handle gstate & RxState.

Parameters:
__HANDLE__,: specifies the UART Handle. UART Handle selects the USARTx or UARTy peripheral (USART,UART availability and x,y values depending on device).

Definition at line 360 of file stm32f1xx_hal_uart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Private Constants

Defines
UART Private Constants
UART

Defines

#define | UART_IT_MASK 0x0000FFFFU
UART interruptions flag mask.
#define | UART_CR1_REG_INDEX 1U
#define | UART_CR2_REG_INDEX 2U
#define | UART_CR3_REG_INDEX 3U

Define Documentation

#define UART_CR1_REG_INDEX 1U

Definition at line 704 of file stm32f1xx_hal_uart.h.

#define UART_CR2_REG_INDEX 2U

Definition at line 705 of file stm32f1xx_hal_uart.h.

#define UART_CR3_REG_INDEX 3U

Definition at line 706 of file stm32f1xx_hal_uart.h.

#define UART_IT_MASK 0x0000FFFFU

UART interruptions flag mask.

Definition at line 702 of file stm32f1xx_hal_uart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Private Macros

Defines
UART Private Macros
UART

Defines

#define | IS_UART_WORD_LENGTH(LENGTH)
#define | IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
#define | IS_UART_STOPBITS(STOPBITS)
#define | IS_UART_PARITY(PARITY)
#define | IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)
#define | IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
#define | IS_UART_STATE(STATE)
#define | IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH)
#define | IS_UART_WAKEUPMETHOD(WAKEUP)
#define | IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
#define | IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
#define | UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
#define | UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | UART_BRR_SAMPLING16(_PCLK_, _BAUD_)
#define | UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define | UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
#define | UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
#define | UART_BRR_SAMPLING8(_PCLK_, _BAUD_)

Define Documentation

#define IS_UART_ADDRESS ( ADDRESS ) ((ADDRESS) <= 0x0FU)

Definition at line 741 of file stm32f1xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define IS_UART_BAUDRATE ( BAUDRATE ) ((BAUDRATE) < 4500001U)

Definition at line 740 of file stm32f1xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_HARDWARE_FLOW_CONTROL ( CONTROL )
Value:
(((CONTROL) == UART_HWCONTROL_NONE) || \
                               ((CONTROL) == UART_HWCONTROL_RTS) || \
                               ((CONTROL) == UART_HWCONTROL_CTS) || \
                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))

Definition at line 723 of file stm32f1xx_hal_uart.h.

Referenced by HAL_UART_Init().

#define IS_UART_LIN_BREAK_DETECT_LENGTH ( LENGTH )
Value:
(((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))

Definition at line 736 of file stm32f1xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_LIN_OVERSAMPLING ( SAMPLING ) (((SAMPLING) == UART_OVERSAMPLING_16))

Definition at line 735 of file stm32f1xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_LIN_WORD_LENGTH ( LENGTH ) (((LENGTH) == UART_WORDLENGTH_8B))

Definition at line 717 of file stm32f1xx_hal_uart.h.

Referenced by HAL_LIN_Init().

#define IS_UART_MODE ( MODE ) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))

Definition at line 728 of file stm32f1xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_PARITY ( PARITY )
Value:
(((PARITY) == UART_PARITY_NONE) || \
                                ((PARITY) == UART_PARITY_EVEN) || \
                                ((PARITY) == UART_PARITY_ODD))

Definition at line 720 of file stm32f1xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_STATE ( STATE )
Value:
(((STATE) == UART_STATE_DISABLE) || \
                              ((STATE) == UART_STATE_ENABLE))

Definition at line 729 of file stm32f1xx_hal_uart.h.

#define IS_UART_STOPBITS ( STOPBITS )
Value:
(((STOPBITS) == UART_STOPBITS_1) || \
                                    ((STOPBITS) == UART_STOPBITS_2))

Definition at line 718 of file stm32f1xx_hal_uart.h.

Referenced by UART_SetConfig().

#define IS_UART_WAKEUPMETHOD ( WAKEUP )
Value:
(((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))

Definition at line 738 of file stm32f1xx_hal_uart.h.

Referenced by HAL_MultiProcessor_Init().

#define IS_UART_WORD_LENGTH ( LENGTH )
Value:
(((LENGTH) == UART_WORDLENGTH_8B) || \
                                     ((LENGTH) == UART_WORDLENGTH_9B))

Definition at line 715 of file stm32f1xx_hal_uart.h.

Referenced by HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(), and HAL_UART_Init().

#define UART_BRR_SAMPLING16 | ( | _PCLK_,
 |  | _BAUD_
 | ) |
Value:
(((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))

Definition at line 748 of file stm32f1xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_BRR_SAMPLING8 | ( | _PCLK_,
 |  | _BAUD_
 | ) |
Value:
(((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
                                                        ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
                                                        (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))

Definition at line 757 of file stm32f1xx_hal_uart.h.

Referenced by UART_SetConfig().

#define UART_DIV_SAMPLING16 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*25U)/(4U*(_BAUD_)))

Definition at line 743 of file stm32f1xx_hal_uart.h.

#define UART_DIV_SAMPLING8 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*25U)/(2U*(_BAUD_)))

Definition at line 752 of file stm32f1xx_hal_uart.h.

#define UART_DIVFRAQ_SAMPLING16 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)

Definition at line 745 of file stm32f1xx_hal_uart.h.

#define UART_DIVFRAQ_SAMPLING8 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)

Definition at line 754 of file stm32f1xx_hal_uart.h.

#define UART_DIVMANT_SAMPLING16 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)

Definition at line 744 of file stm32f1xx_hal_uart.h.

#define UART_DIVMANT_SAMPLING8 | ( | _PCLK_,
 |  | _BAUD_
 | ) | (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)

Definition at line 753 of file stm32f1xx_hal_uart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Private Functions

UART Private Functions
UART
Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Initialization and de-initialization functions

Functions
USART Initialization and de-initialization functions
USART Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitializes the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
USART MSP Init.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
USART MSP DeInit.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
            ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
  This subsection provides a set of functions allowing to initialize the USART
  in asynchronous and in synchronous modes.
  (+) For the asynchronous mode only these parameters can be configured:
      (++) Baud Rate
      (++) Word Length
      (++) Stop Bit
      (++) Parity: If the parity is enabled, then the MSB bit of the data written
           in the data register is transmitted but is changed by the parity bit.
           Depending on the frame length defined by the M bit (8-bits or 9-bits),
           please refer to Reference manual for possible USART frame formats.
      (++) USART polarity
      (++) USART phase
      (++) USART LastBit
      (++) Receiver/transmitter modes

  [..]
    The HAL_USART_Init() function follows the USART  synchronous configuration
    procedure (details for the procedure are available in reference manuals
    (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).

Function Documentation

HAL_StatusTypeDef HAL_USART_DeInit ( USART_HandleTypeDef * husart )

DeInitializes the USART peripheral.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 297 of file stm32f1xx_hal_usart.c.

References assert_param, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspDeInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

HAL_StatusTypeDef HAL_USART_Init ( USART_HandleTypeDef * husart )

Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 250 of file stm32f1xx_hal_usart.c.

References __HAL_USART_ENABLE, assert_param, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_MspInit(), HAL_USART_STATE_BUSY, HAL_USART_STATE_READY, HAL_USART_STATE_RESET, USART_HandleTypeDef::Instance, USART_HandleTypeDef::Lock, USART_HandleTypeDef::State, and USART_SetConfig().

void HAL_USART_MspDeInit ( USART_HandleTypeDef * husart )

USART MSP DeInit.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 343 of file stm32f1xx_hal_usart.c.

Referenced by HAL_USART_DeInit().

void HAL_USART_MspInit ( USART_HandleTypeDef * husart )

USART MSP Init.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 328 of file stm32f1xx_hal_usart.c.

Referenced by HAL_USART_Init().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
USART Exported Functions

USART Transmit and Receive functions. More...

Functions

HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Simplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Full-Duplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stops the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfer (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
This function handles USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callbacks.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callbacks.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callbacks.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callbacks.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callbacks.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.

Detailed Description

USART Transmit and Receive functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to manage the USART synchronous
    data transfers.

  [..]
    The USART supports master mode only: it cannot receive or send data related to an input
    clock (SCLK is always an output).

    (#) There are two modes of transfer:
        (++) Blocking mode: The communication is performed in polling mode.
             The HAL status of all data processing is returned by the same function
             after finishing transfer.
        (++) No-Blocking mode: The communication is performed using Interrupts
             or DMA, These API's return the HAL status.
             The end of the data processing will be indicated through the
             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
             using DMA mode.
             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
             user callbacks
             will be executed respectively at the end of the transmit or Receive process
             The HAL_USART_ErrorCallback() user callback will be executed when a communication
             error is detected

    (#) Blocking mode APIs are :
        (++) HAL_USART_Transmit() in simplex mode
        (++) HAL_USART_Receive() in full duplex receive only
        (++) HAL_USART_TransmitReceive() in full duplex mode

    (#) Non Blocking mode APIs with Interrupt are :
        (++) HAL_USART_Transmit_IT()in simplex mode
        (++) HAL_USART_Receive_IT() in full duplex receive only
        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
        (++) HAL_USART_IRQHandler()

    (#) Non Blocking mode functions with DMA are :
        (++) HAL_USART_Transmit_DMA()in simplex mode
        (++) HAL_USART_Receive_DMA() in full duplex receive only
        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
        (++) HAL_USART_DMAPause()
        (++) HAL_USART_DMAResume()
        (++) HAL_USART_DMAStop()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) HAL_USART_TxHalfCpltCallback()
        (++) HAL_USART_TxCpltCallback()
        (++) HAL_USART_RxHalfCpltCallback()
        (++) HAL_USART_RxCpltCallback()
        (++) HAL_USART_ErrorCallback()
        (++) HAL_USART_TxRxCpltCallback()

Function Documentation

HAL_StatusTypeDef HAL_USART_Abort ( USART_HandleTypeDef * husart )

Abort ongoing transfer (blocking mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer (either Tx or Rx, as described by TransferType parameter) started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
  • Set handle State to READY
This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
Return values:
HAL status

Definition at line 1218 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Abort_IT ( USART_HandleTypeDef * husart )

Abort ongoing transfer (Interrupt mode).

Parameters:
husart USART handle.
Note:
This procedure could be used for aborting any ongoing transfer (either Tx or Rx, as described by TransferType parameter) started in Interrupt or DMA mode. This procedure performs following operations :
  • Disable PPP Interrupts (depending of transfer direction)
  • Disable the DMA transfer in the peripheral register (if enabled)
  • Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
  • Set handle State to READY
  • At abort completion, call user abort complete callback
This procedure is executed in Interrupt mode, meaning that abort procedure could be considered as completed only when user abort complete callback is executed (not when exiting function).
Return values:
HAL status

Definition at line 1284 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), and __DMA_HandleTypeDef::XferAbortCallback.

void HAL_USART_AbortCpltCallback ( USART_HandleTypeDef * husart )

USART Abort Complete callback.

Parameters:
husart USART handle.
Return values:
None

Definition at line 1630 of file stm32f1xx_hal_usart.c.

Referenced by HAL_USART_Abort_IT(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

HAL_StatusTypeDef HAL_USART_DMAPause ( USART_HandleTypeDef * husart )

Pauses the DMA Transfer.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1121 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_USART_DMAResume ( USART_HandleTypeDef * husart )

Resumes the DMA Transfer.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1141 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::Instance.

HAL_StatusTypeDef HAL_USART_DMAStop ( USART_HandleTypeDef * husart )

Stops the DMA Transfer.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 1161 of file stm32f1xx_hal_usart.c.

References HAL_DMA_Abort(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_EndRxTransfer(), and USART_EndTxTransfer().

void HAL_USART_ErrorCallback ( USART_HandleTypeDef * husart )

USART error callbacks.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1616 of file stm32f1xx_hal_usart.c.

Referenced by HAL_USART_IRQHandler(), USART_DMAAbortOnError(), and USART_DMAError().

void HAL_USART_IRQHandler ( USART_HandleTypeDef * husart )

This function handles USART interrupt request.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1397 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_DMA_Abort_IT(), HAL_USART_ERROR_FE, HAL_USART_ERROR_NE, HAL_USART_ERROR_NONE, HAL_USART_ERROR_ORE, HAL_USART_ERROR_PE, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_DMAAbortOnError(), USART_EndRxTransfer(), USART_EndTransmit_IT(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and __DMA_HandleTypeDef::XferAbortCallback.

HAL_StatusTypeDef HAL_USART_Receive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Receive an amount of data in blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pRxData,: Pointer to data buffer
Size,: Amount of data to be received
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 507 of file stm32f1xx_hal_usart.c.

References DUMMY_DATA, USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_FLAG_RXNE, USART_FLAG_TXE, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Receive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Receive an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pRxData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status
Note:
The USART DMA transmit channel must be configured in order to generate the clock for the slave.
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.

Definition at line 942 of file stm32f1xx_hal_usart.c.

References __HAL_USART_CLEAR_OREFLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Receive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Simplex Receive an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pRxData,: Pointer to data buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 776 of file stm32f1xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, DUMMY_DATA, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_IT_ERR, USART_IT_PE, and USART_IT_RXNE.

void HAL_USART_RxCpltCallback ( USART_HandleTypeDef * husart )

Rx Transfer completed callbacks.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1571 of file stm32f1xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_Receive_IT().

void HAL_USART_RxHalfCpltCallback ( USART_HandleTypeDef * husart )

Rx Half Transfer completed callbacks.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1586 of file stm32f1xx_hal_usart.c.

Referenced by USART_DMARxHalfCplt().

HAL_StatusTypeDef HAL_USART_Transmit | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Simplex Send an amount of data in blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 426 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_TC, USART_FLAG_TXE, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_Transmit_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Simplex Send an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status

Definition at line 878 of file stm32f1xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), USART_FLAG_TC, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_Transmit_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint16_t | Size
 | ) |  |

Simplex Send an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data buffer
Size,: Amount of data to be sent
Return values:
HAL status
Note:
The USART errors are not managed to avoid the overrun error.

Definition at line 727 of file stm32f1xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, and USART_IT_TXE.

HAL_StatusTypeDef HAL_USART_TransmitReceive | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size,
 |  | uint32_t | Timeout
 | ) |  |

Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data transmitted buffer
pRxData,: Pointer to data received buffer
Size,: Amount of data to be sent
Timeout,: Timeout duration
Return values:
HAL status

Definition at line 613 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_GetTick(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_FLAG_RXNE, USART_FLAG_TXE, USART_PARITY_NONE, USART_WaitOnFlagUntilTimeout(), USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Transmit Receive an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data transmitted buffer
pRxData,: Pointer to data received buffer
Size,: Amount of data to be received
Note:
When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
Return values:
HAL status

Definition at line 1034 of file stm32f1xx_hal_usart.c.

References __HAL_USART_CLEAR_FLAG, __HAL_USART_CLEAR_OREFLAG, USART_HandleTypeDef::ErrorCode, HAL_DMA_Start_IT(), HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::Instance, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferSize, USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxHalfCplt(), USART_DMATransmitCplt(), USART_DMATxHalfCplt(), USART_FLAG_TC, __DMA_HandleTypeDef::XferAbortCallback, __DMA_HandleTypeDef::XferCpltCallback, __DMA_HandleTypeDef::XferErrorCallback, and __DMA_HandleTypeDef::XferHalfCpltCallback.

HAL_StatusTypeDef HAL_USART_TransmitReceive_IT | ( | USART_HandleTypeDef * | husart,
 |  | uint8_t * | pTxData,
 |  | uint8_t * | pRxData,
 |  | uint16_t | Size
 | ) |  |

Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
pTxData,: Pointer to data transmitted buffer
pRxData,: Pointer to data received buffer
Size,: Amount of data to be received
Return values:
HAL status

Definition at line 826 of file stm32f1xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_NONE, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::RxXferSize, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_HandleTypeDef::TxXferSize, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, and USART_IT_TXE.

void HAL_USART_TxCpltCallback ( USART_HandleTypeDef * husart )

Tx Transfer completed callbacks.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1541 of file stm32f1xx_hal_usart.c.

Referenced by USART_DMATransmitCplt(), and USART_EndTransmit_IT().

void HAL_USART_TxHalfCpltCallback ( USART_HandleTypeDef * husart )

Tx Half Transfer completed callbacks.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1556 of file stm32f1xx_hal_usart.c.

Referenced by USART_DMATxHalfCplt().

void HAL_USART_TxRxCpltCallback ( USART_HandleTypeDef * husart )

Tx/Rx Transfers completed callback for the non-blocking process.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 1601 of file stm32f1xx_hal_usart.c.

Referenced by USART_DMAReceiveCplt(), and USART_TransmitReceive_IT().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
USART Exported Functions

USART State and Errors functions. More...

Functions

HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Returns the USART state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART State and Errors functions.

  ==============================================================================
                  ##### Peripheral State and Errors functions #####
  ==============================================================================
  [..]
    This subsection provides a set of functions allowing to return the State of
    USART communication
    process, return Peripheral Errors occurred during communication process
     (+) HAL_USART_GetState() API can be helpful to check in run-time the state
         of the USART peripheral.
     (+) HAL_USART_GetError() check in run-time errors that could be occurred during
         communication.

Function Documentation

uint32_t HAL_USART_GetError ( USART_HandleTypeDef * husart )

Return the USART error code.

Parameters:
husart : pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART.
Return values:
USART Error Code

Definition at line 1680 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode.

HAL_USART_StateTypeDef HAL_USART_GetState ( USART_HandleTypeDef * husart )

Returns the USART state.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL state

Definition at line 1669 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::State.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Private Functions

Functions
USART Private Functions
USART

USART Private functions. More...

Functions

static void | USART_EndTxTransfer (USART_HandleTypeDef *husart)
End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
static void | USART_EndRxTransfer (USART_HandleTypeDef *husart)
End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex Receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
static void | USART_SetConfig (USART_HandleTypeDef *husart)
Configures the USART pferipheral.
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles USART Communication Timeout.

Detailed Description

USART Private functions.

Function Documentation

static void USART_DMAAbortOnError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).

Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1914 of file stm32f1xx_hal_usart.c.

References HAL_USART_ErrorCallback(), USART_HandleTypeDef::RxXferCount, and USART_HandleTypeDef::TxXferCount.

Referenced by HAL_USART_IRQHandler().

static void USART_DMAError ( DMA_HandleTypeDef * hdma ) [static]

DMA USART communication error callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1814 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_ERROR_DMA, HAL_USART_ErrorCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_BUSY_TX, HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_EndRxTransfer(), and USART_EndTxTransfer().

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMAReceiveCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process complete callback.

Parameters:
hdma,: DMA handle
Return values:
None

Definition at line 1749 of file stm32f1xx_hal_usart.c.

References HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, USART_HandleTypeDef::RxXferCount, and USART_HandleTypeDef::State.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMARxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Tx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1968 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMARxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART receive process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1802 of file stm32f1xx_hal_usart.c.

References HAL_USART_RxHalfCpltCallback().

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATransmitCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process complete callback.

Parameters:
hdma,: DMA handle
hdma,: Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1704 of file stm32f1xx_hal_usart.c.

References __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, HAL_USART_TxCpltCallback(), USART_HandleTypeDef::Instance, __DMA_HandleTypeDef::Instance, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and USART_IT_TC.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_DMATxAbortCallback ( DMA_HandleTypeDef * hdma ) [static]

DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).

Note:
When this callback is executed, User Abort complete call back is called only if no Abort still ongoing for Rx DMA Handle.
Parameters:
hdma DMA handle.
Return values:
None

Definition at line 1931 of file stm32f1xx_hal_usart.c.

References USART_HandleTypeDef::ErrorCode, HAL_USART_AbortCpltCallback(), HAL_USART_ERROR_NONE, HAL_USART_STATE_READY, USART_HandleTypeDef::hdmarx, USART_HandleTypeDef::hdmatx, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, and __DMA_HandleTypeDef::XferAbortCallback.

Referenced by HAL_USART_Abort_IT().

static void USART_DMATxHalfCplt ( DMA_HandleTypeDef * hdma ) [static]

DMA USART transmit process half complete callback.

Parameters:
hdma,: pointer to a DMA_HandleTypeDef structure that contains the configuration information for the specified DMA module.
Return values:
None

Definition at line 1737 of file stm32f1xx_hal_usart.c.

References HAL_USART_TxHalfCpltCallback().

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

static void USART_EndRxTransfer ( USART_HandleTypeDef * husart ) [static]

End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1898 of file stm32f1xx_hal_usart.c.

References HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

Referenced by HAL_USART_DMAStop(), HAL_USART_IRQHandler(), and USART_DMAError().

static HAL_StatusTypeDef USART_EndTransmit_IT ( USART_HandleTypeDef * husart ) [static]

Wraps up transmission in non blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 2050 of file stm32f1xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, HAL_USART_STATE_READY, HAL_USART_TxCpltCallback(), USART_HandleTypeDef::State, USART_IT_ERR, and USART_IT_TC.

Referenced by HAL_USART_IRQHandler().

static void USART_EndTxTransfer ( USART_HandleTypeDef * husart ) [static]

End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).

Parameters:
husart,: USART handle.
Return values:
None

Definition at line 1884 of file stm32f1xx_hal_usart.c.

References HAL_USART_STATE_READY, USART_HandleTypeDef::Instance, and USART_HandleTypeDef::State.

Referenced by HAL_USART_DMAStop(), and USART_DMAError().

static HAL_StatusTypeDef USART_Receive_IT ( USART_HandleTypeDef * husart ) [static]

Simplex Receive an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 2071 of file stm32f1xx_hal_usart.c.

References DUMMY_DATA, HAL_USART_RxCpltCallback(), HAL_USART_STATE_BUSY_RX, HAL_USART_STATE_READY, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static void USART_SetConfig ( USART_HandleTypeDef * husart ) [static]

Configures the USART pferipheral.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
None

Definition at line 2246 of file stm32f1xx_hal_usart.c.

References assert_param, USART_InitTypeDef::BaudRate, USART_InitTypeDef::CLKLastBit, USART_InitTypeDef::CLKPhase, USART_InitTypeDef::CLKPolarity, HAL_RCC_GetPCLK1Freq(), HAL_RCC_GetPCLK2Freq(), USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, IS_USART_BAUDRATE, IS_USART_LASTBIT, IS_USART_MODE, IS_USART_PARITY, IS_USART_PHASE, IS_USART_POLARITY, IS_USART_STOPBITS, IS_USART_WORD_LENGTH, USART_InitTypeDef::Mode, USART_InitTypeDef::Parity, USART_InitTypeDef::StopBits, USART_BRR, USART_CLOCK_ENABLE, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_Init().

static HAL_StatusTypeDef USART_Transmit_IT ( USART_HandleTypeDef * husart ) [static]

Simplex Send an amount of data in non-blocking mode.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status
Note:
The USART errors are not managed to avoid the overrun error.

Definition at line 2004 of file stm32f1xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_ENABLE_IT, HAL_USART_STATE_BUSY_TX, USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_IT_TC, USART_IT_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_TransmitReceive_IT ( USART_HandleTypeDef * husart ) [static]

Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Return values:
HAL status

Definition at line 2143 of file stm32f1xx_hal_usart.c.

References __HAL_USART_GET_FLAG, HAL_USART_STATE_BUSY_TX_RX, HAL_USART_STATE_READY, HAL_USART_TxRxCpltCallback(), USART_HandleTypeDef::Init, USART_HandleTypeDef::Instance, USART_InitTypeDef::Parity, USART_HandleTypeDef::pRxBuffPtr, USART_HandleTypeDef::pTxBuffPtr, USART_HandleTypeDef::RxXferCount, USART_HandleTypeDef::State, USART_HandleTypeDef::TxXferCount, USART_FLAG_RXNE, USART_FLAG_TXE, USART_PARITY_NONE, USART_WORDLENGTH_9B, and USART_InitTypeDef::WordLength.

Referenced by HAL_USART_IRQHandler().

static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout | ( | USART_HandleTypeDef * | husart,
 |  | uint32_t | Flag,
 |  | FlagStatus | Status,
 |  | uint32_t | Tickstart,
 |  | uint32_t | Timeout
 | ) |  | [static]

This function handles USART Communication Timeout.

Parameters:
husart,: pointer to a USART_HandleTypeDef structure that contains the configuration information for the specified USART module.
Flag,: specifies the USART flag to check.
Status,: The new Flag status (SET or RESET).
Tickstart,: Tick start value.
Timeout,: Timeout duration.
Return values:
HAL status

Definition at line 1851 of file stm32f1xx_hal_usart.c.

References __HAL_USART_DISABLE_IT, __HAL_USART_GET_FLAG, HAL_GetTick(), HAL_USART_STATE_READY, USART_HandleTypeDef::State, USART_IT_ERR, USART_IT_PE, USART_IT_RXNE, and USART_IT_TXE.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), and HAL_USART_TransmitReceive().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Exported Types

Data Structures | Enumerations
USART Exported Types
USART

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Enumeration Type Documentation

enum HAL_USART_StateTypeDef

HAL State structures definition.

Enumerator:
HAL_USART_STATE_RESET

Peripheral is not yet initialized

HAL_USART_STATE_READY

Peripheral Initialized and ready for use

HAL_USART_STATE_BUSY

an internal process is ongoing

HAL_USART_STATE_BUSY_TX

Data Transmission process is ongoing

HAL_USART_STATE_BUSY_RX

Data Reception process is ongoing

HAL_USART_STATE_BUSY_TX_RX

Data Transmission Reception process is ongoing

HAL_USART_STATE_TIMEOUT

Timeout state

HAL_USART_STATE_ERROR

Error

Definition at line 102 of file stm32f1xx_hal_usart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_InitTypeDef Struct Reference
USART Exported Types

USART Init Structure definition. More...

#include <stm32f1xx_hal_usart.h>

Data Fields

uint32_t | BaudRate
uint32_t | WordLength
uint32_t | StopBits
uint32_t | Parity
uint32_t | Mode
uint32_t | CLKPolarity
uint32_t | CLKPhase
uint32_t | CLKLastBit

Detailed Description

USART Init Structure definition.

Definition at line 65 of file stm32f1xx_hal_usart.h.

Field Documentation

uint32_t USART_InitTypeDef::BaudRate

This member configures the Usart communication baud rate. The baud rate is computed using the following formula:

  • IntegerDivider = ((PCLKx) / (16 * (husart->Init.BaudRate)))
  • FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5

Definition at line 67 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKLastBit

Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of USART Last Bit

Definition at line 94 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPhase

Specifies the clock transition on which the bit capture is made. This parameter can be a value of USART Clock Phase

Definition at line 91 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::CLKPolarity

Specifies the steady state of the serial clock. This parameter can be a value of USART Clock Polarity

Definition at line 88 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Mode

Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of USART Mode

Definition at line 85 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::Parity

Specifies the parity mode. This parameter can be a value of USART Parity

Note:
When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits).

Definition at line 78 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint32_t USART_InitTypeDef::StopBits

Specifies the number of stop bits transmitted. This parameter can be a value of USART Number of Stop Bits

Definition at line 75 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

uint32_t USART_InitTypeDef::WordLength

Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of USART Word Length

Definition at line 72 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_usart.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
USART_HandleTypeDef Struct Reference
USART Exported Types

USART handle Structure definition. More...

#include <stm32f1xx_hal_usart.h>

Data Fields

USART_TypeDef * | Instance
USART_InitTypeDef Init
uint8_t * | pTxBuffPtr
uint16_t | TxXferSize
__IO uint16_t | TxXferCount
uint8_t * | pRxBuffPtr
uint16_t | RxXferSize
__IO uint16_t | RxXferCount
DMA_HandleTypeDef * hdmatx
DMA_HandleTypeDef * hdmarx
HAL_LockTypeDef | Lock
__IO HAL_USART_StateTypeDef | State
__IO uint32_t | ErrorCode

Detailed Description

USART handle Structure definition.

Definition at line 117 of file stm32f1xx_hal_usart.h.

Field Documentation

__IO uint32_t USART_HandleTypeDef::ErrorCode

USART Error code

Definition at line 143 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_GetError(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_DMAError(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmarx

Usart Rx DMA Handle parameters

Definition at line 137 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_IRQHandler(), HAL_USART_Receive_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

DMA_HandleTypeDef* USART_HandleTypeDef::hdmatx

Usart Tx DMA Handle parameters

Definition at line 135 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DMAStop(), HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive_DMA(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

USART_InitTypeDef USART_HandleTypeDef::Init

Usart communication parameters

Definition at line 121 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

USART_TypeDef* USART_HandleTypeDef::Instance

USART registers base address

Definition at line 119 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAPause(), HAL_USART_DMAResume(), HAL_USART_DMAStop(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMATransmitCplt(), USART_EndRxTransfer(), USART_EndTxTransfer(), USART_Receive_IT(), USART_SetConfig(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

HAL_LockTypeDef USART_HandleTypeDef::Lock

Locking object

Definition at line 139 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Init().

uint8_t* USART_HandleTypeDef::pRxBuffPtr

Pointer to Usart Rx transfer Buffer

Definition at line 129 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint8_t* USART_HandleTypeDef::pTxBuffPtr

Pointer to Usart Tx transfer Buffer

Definition at line 123 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

__IO uint16_t USART_HandleTypeDef::RxXferCount

Usart Rx Transfer Counter

Definition at line 133 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Receive(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATxAbortCallback(), USART_Receive_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::RxXferSize

Usart Rx Transfer size

Definition at line 131 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

__IO HAL_USART_StateTypeDef USART_HandleTypeDef::State

Usart communication state

Definition at line 141 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_DMAStop(), HAL_USART_GetState(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_DMAError(), USART_DMAReceiveCplt(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_EndRxTransfer(), USART_EndTransmit_IT(), USART_EndTxTransfer(), USART_Receive_IT(), USART_Transmit_IT(), USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

__IO uint16_t USART_HandleTypeDef::TxXferCount

Usart Tx Transfer Counter

Definition at line 127 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_IT(), USART_DMAAbortOnError(), USART_DMAError(), USART_DMARxAbortCallback(), USART_DMATransmitCplt(), USART_DMATxAbortCallback(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

uint16_t USART_HandleTypeDef::TxXferSize

Usart Tx Transfer size

Definition at line 125 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), and HAL_USART_TransmitReceive_IT().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_usart.h
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STM32F103xB HAL User Manual: USART Error Code

Defines
USART Error Code
USART Exported Constants

USART Error Code. More...

Defines

#define | HAL_USART_ERROR_NONE 0x00000000U
#define | HAL_USART_ERROR_PE 0x00000001U
#define | HAL_USART_ERROR_NE 0x00000002U
#define | HAL_USART_ERROR_FE 0x00000004U
#define | HAL_USART_ERROR_ORE 0x00000008U
#define | HAL_USART_ERROR_DMA 0x00000010U

Detailed Description

USART Error Code.

Define Documentation

#define HAL_USART_ERROR_DMA 0x00000010U

DMA transfer error

Definition at line 163 of file stm32f1xx_hal_usart.h.

Referenced by USART_DMAError().

#define HAL_USART_ERROR_FE 0x00000004U

Frame error

Definition at line 161 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NE 0x00000002U

Noise error

Definition at line 160 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_NONE 0x00000000U

No error

Definition at line 158 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Abort(), HAL_USART_Abort_IT(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_USART_IRQHandler(), HAL_USART_Receive(), HAL_USART_Receive_DMA(), HAL_USART_Receive_IT(), HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive(), HAL_USART_TransmitReceive_DMA(), HAL_USART_TransmitReceive_IT(), USART_DMARxAbortCallback(), and USART_DMATxAbortCallback().

#define HAL_USART_ERROR_ORE 0x00000008U

Overrun error

Definition at line 162 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

#define HAL_USART_ERROR_PE 0x00000001U

Parity error

Definition at line 159 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_IRQHandler().

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STM32F103xB HAL User Manual: USART Word Length

Defines
USART Word Length
USART Exported Constants

Defines

#define | USART_WORDLENGTH_8B 0x00000000U
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Define Documentation

#define USART_WORDLENGTH_8B 0x00000000U

Definition at line 171 of file stm32f1xx_hal_usart.h.

#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)

Definition at line 172 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Number of Stop Bits

Defines
USART Number of Stop Bits
USART Exported Constants

Defines

#define | USART_STOPBITS_1 0x00000000U
#define | USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Define Documentation

#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)

Definition at line 181 of file stm32f1xx_hal_usart.h.

#define USART_STOPBITS_1 0x00000000U

Definition at line 180 of file stm32f1xx_hal_usart.h.

#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))

Definition at line 183 of file stm32f1xx_hal_usart.h.

#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)

Definition at line 182 of file stm32f1xx_hal_usart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Parity

Defines
USART Parity
USART Exported Constants

Defines

#define | USART_PARITY_NONE 0x00000000U
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Define Documentation

#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)

Definition at line 192 of file stm32f1xx_hal_usart.h.

#define USART_PARITY_NONE 0x00000000U

Definition at line 191 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), USART_Receive_IT(), USART_Transmit_IT(), and USART_TransmitReceive_IT().

#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))

Definition at line 193 of file stm32f1xx_hal_usart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Mode

Defines
USART Mode
USART Exported Constants

Defines

#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Define Documentation

#define USART_MODE_RX ((uint32_t)USART_CR1_RE)

Definition at line 201 of file stm32f1xx_hal_usart.h.

#define USART_MODE_TX ((uint32_t)USART_CR1_TE)

Definition at line 202 of file stm32f1xx_hal_usart.h.

#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))

Definition at line 203 of file stm32f1xx_hal_usart.h.

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STM32F103xB HAL User Manual: USART Clock

Defines
USART Clock
USART Exported Constants

Defines

#define | USART_CLOCK_DISABLE 0x00000000U
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

Define Documentation

#define USART_CLOCK_DISABLE 0x00000000U

Definition at line 211 of file stm32f1xx_hal_usart.h.

#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)

Definition at line 212 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Clock Polarity

Defines
USART Clock Polarity
USART Exported Constants

Defines

#define | USART_POLARITY_LOW 0x00000000U
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Define Documentation

#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)

Definition at line 221 of file stm32f1xx_hal_usart.h.

#define USART_POLARITY_LOW 0x00000000U

Definition at line 220 of file stm32f1xx_hal_usart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Clock Phase

Defines
USART Clock Phase
USART Exported Constants

Defines

#define | USART_PHASE_1EDGE 0x00000000U
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Define Documentation

#define USART_PHASE_1EDGE 0x00000000U

Definition at line 229 of file stm32f1xx_hal_usart.h.

#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)

Definition at line 230 of file stm32f1xx_hal_usart.h.

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STM32F103xB HAL User Manual: USART Last Bit

Defines
USART Last Bit
USART Exported Constants

Defines

#define | USART_LASTBIT_DISABLE 0x00000000U
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Define Documentation

#define USART_LASTBIT_DISABLE 0x00000000U

Definition at line 238 of file stm32f1xx_hal_usart.h.

#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)

Definition at line 239 of file stm32f1xx_hal_usart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART NACK State

Defines
USART NACK State
USART Exported Constants

Defines

#define | USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | USART_NACK_DISABLE 0x00000000U

Define Documentation

#define USART_NACK_DISABLE 0x00000000U

Definition at line 248 of file stm32f1xx_hal_usart.h.

#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)

Definition at line 247 of file stm32f1xx_hal_usart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Flags

Defines
USART Flags
USART Exported Constants

Elements values convention: 0xXXXX. More...

Defines

#define | USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define | USART_FLAG_TC ((uint32_t)USART_SR_TC)
#define | USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define | USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define | USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define | USART_FLAG_NE ((uint32_t)USART_SR_NE)
#define | USART_FLAG_FE ((uint32_t)USART_SR_FE)
#define | USART_FLAG_PE ((uint32_t)USART_SR_PE)

Detailed Description

Elements values convention: 0xXXXX.

  • 0xXXXX : Flag mask in the SR register

Define Documentation

#define USART_FLAG_FE ((uint32_t)USART_SR_FE)

Definition at line 264 of file stm32f1xx_hal_usart.h.

#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)

Definition at line 261 of file stm32f1xx_hal_usart.h.

#define USART_FLAG_NE ((uint32_t)USART_SR_NE)

Definition at line 263 of file stm32f1xx_hal_usart.h.

#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE)

Definition at line 262 of file stm32f1xx_hal_usart.h.

#define USART_FLAG_PE ((uint32_t)USART_SR_PE)

Definition at line 265 of file stm32f1xx_hal_usart.h.

#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)

Definition at line 260 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_TransmitReceive(), and USART_TransmitReceive_IT().

#define USART_FLAG_TC ((uint32_t)USART_SR_TC)

Definition at line 259 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Transmit(), HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)

Definition at line 258 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive(), HAL_USART_Transmit(), HAL_USART_TransmitReceive(), and USART_TransmitReceive_IT().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Interrupts Definition

Defines
USART Interrupts Definition
USART Exported Constants

Elements values convention: 0xY000XXXX. More...

Defines

#define | USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Detailed Description

Elements values convention: 0xY000XXXX.

  • XXXX : Interrupt mask in the XX register
  • Y : Interrupt source register (2bits)
    • 01: CR1 register
    • 10: CR2 register
    • 11: CR3 register

Define Documentation

#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))

Definition at line 289 of file stm32f1xx_hal_usart.h.

#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))

Definition at line 290 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), USART_EndTransmit_IT(), and USART_WaitOnFlagUntilTimeout().

#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))

Definition at line 285 of file stm32f1xx_hal_usart.h.

#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))

Definition at line 287 of file stm32f1xx_hal_usart.h.

#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))

Definition at line 281 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))

Definition at line 284 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive_IT(), HAL_USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))

Definition at line 283 of file stm32f1xx_hal_usart.h.

Referenced by USART_DMATransmitCplt(), USART_EndTransmit_IT(), and USART_Transmit_IT().

#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))

Definition at line 282 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), USART_Transmit_IT(), and USART_WaitOnFlagUntilTimeout().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Exported Macros

Defines
USART Exported Macros
USART

Defines

#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified USART pending flags.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART IDLE pending flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupts.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupts.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
Disable USART.

Define Documentation

#define __HAL_USART_CLEAR_FEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)

Clear the USART FE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 363 of file stm32f1xx_hal_usart.h.

#define __HAL_USART_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | ((__HANDLE__)->Instance->SR = ~(__FLAG__))

Clears the specified USART pending flags.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
__FLAG__,: specifies the flag to check. This parameter can be any combination of the following values:
  • USART_FLAG_TC: Transmission Complete flag.
  • USART_FLAG_RXNE: Receive data register not empty flag.
Note:
PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun error) and IDLE (Idle line detected) flags are cleared by software sequence: a read operation to USART_SR register followed by a read operation to USART_DR register.
RXNE flag can be also cleared by a read to the USART_DR register.
TC flag can be also cleared by software sequence: a read operation to USART_SR register followed by a write operation to USART_DR register
TXE flag is cleared only by a write to the USART_DR register

Definition at line 345 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Transmit_DMA(), and HAL_USART_TransmitReceive_DMA().

#define __HAL_USART_CLEAR_IDLEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)

Clear the USART IDLE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 382 of file stm32f1xx_hal_usart.h.

#define __HAL_USART_CLEAR_NEFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)

Clear the USART NE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 369 of file stm32f1xx_hal_usart.h.

#define __HAL_USART_CLEAR_OREFLAG ( __HANDLE__ ) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)

Clear the USART ORE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 376 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive_DMA(), and HAL_USART_TransmitReceive_DMA().

#define __HAL_USART_CLEAR_PEFLAG ( __HANDLE__ )
Value:
do{                                           \
    __IO uint32_t tmpreg = 0x00U;               \
    tmpreg = (__HANDLE__)->Instance->SR;        \
    tmpreg = (__HANDLE__)->Instance->DR;        \
    UNUSED(tmpreg);                             \
  } while(0U)

Clear the USART PE pending flag.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 351 of file stm32f1xx_hal_usart.h.

#define __HAL_USART_DISABLE ( __HANDLE__ ) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))

Disable USART.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 444 of file stm32f1xx_hal_usart.h.

#define __HAL_USART_DISABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
                                                            (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
                                                             ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))

Disable the specified USART interrupts.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
__INTERRUPT__,: specifies the USART interrupt source to disable. This parameter can be one of the following values:
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_PE: Parity Error interrupt
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) This parameter can be: ENABLE or DISABLE.

Definition at line 414 of file stm32f1xx_hal_usart.h.

Referenced by USART_EndTransmit_IT(), USART_Transmit_IT(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))

Enable USART.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 438 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Init().

#define __HAL_USART_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) |
Value:
((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
                                                            (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & USART_IT_MASK)): \
                                                            ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))

Enable the specified USART interrupts.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
__INTERRUPT__,: specifies the USART interrupt source to enable. This parameter can be one of the following values:
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_PE: Parity Error interrupt
  • USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) This parameter can be: ENABLE or DISABLE.

Definition at line 397 of file stm32f1xx_hal_usart.h.

Referenced by HAL_USART_Receive_IT(), HAL_USART_Transmit_IT(), HAL_USART_TransmitReceive_IT(), USART_DMATransmitCplt(), and USART_Transmit_IT().

#define __HAL_USART_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Checks whether the specified USART flag is set or not.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
__FLAG__,: specifies the flag to check. This parameter can be one of the following values:
  • USART_FLAG_TXE: Transmit data register empty flag
  • USART_FLAG_TC: Transmission Complete flag
  • USART_FLAG_RXNE: Receive data register not empty flag
  • USART_FLAG_IDLE: Idle Line detection flag
  • USART_FLAG_ORE: OverRun Error flag
  • USART_FLAG_NE: Noise Error flag
  • USART_FLAG_FE: Framing Error flag
  • USART_FLAG_PE: Parity Error flag
Return values:
The new state of __FLAG__ (TRUE or FALSE).

Definition at line 325 of file stm32f1xx_hal_usart.h.

Referenced by USART_TransmitReceive_IT(), and USART_WaitOnFlagUntilTimeout().

#define __HAL_USART_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __IT__
 | ) |
Value:
(((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))

Checks whether the specified USART interrupt has occurred or not.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
__IT__,: specifies the USART interrupt source to check. This parameter can be one of the following values:
  • USART_IT_TXE: Transmit Data Register empty interrupt
  • USART_IT_TC: Transmission complete interrupt
  • USART_IT_RXNE: Receive Data register not empty interrupt
  • USART_IT_IDLE: Idle line detection interrupt
  • USART_IT_ERR: Error interrupt
  • USART_IT_PE: Parity Error interrupt
Return values:
The new state of __IT__ (TRUE or FALSE).

Definition at line 431 of file stm32f1xx_hal_usart.h.

#define __HAL_USART_RESET_HANDLE_STATE ( __HANDLE__ ) ((__HANDLE__)->State = HAL_USART_STATE_RESET)

Reset USART handle state.

Parameters:
__HANDLE__,: specifies the USART Handle. USART Handle selects the USARTx peripheral (USART availability and x value depending on device).

Definition at line 308 of file stm32f1xx_hal_usart.h.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Private Constants

Defines
USART Private Constants
USART

Defines

#define | DUMMY_DATA 0xFFFFU
#define | USART_TIMEOUT_VALUE 22000U
#define | USART_IT_MASK 0x0000FFFFU
USART interruptions flag mask.
#define | USART_CR1_REG_INDEX 1U
#define | USART_CR2_REG_INDEX 2U
#define | USART_CR3_REG_INDEX 3U

Define Documentation

#define DUMMY_DATA 0xFFFFU

Definition at line 173 of file stm32f1xx_hal_usart.c.

Referenced by HAL_USART_Receive(), HAL_USART_Receive_IT(), and USART_Receive_IT().

#define USART_CR1_REG_INDEX 1U

Definition at line 521 of file stm32f1xx_hal_usart.h.

#define USART_CR2_REG_INDEX 2U

Definition at line 522 of file stm32f1xx_hal_usart.h.

#define USART_CR3_REG_INDEX 3U

Definition at line 523 of file stm32f1xx_hal_usart.h.

#define USART_IT_MASK 0x0000FFFFU

USART interruptions flag mask.

Definition at line 519 of file stm32f1xx_hal_usart.h.

#define USART_TIMEOUT_VALUE 22000U

Definition at line 174 of file stm32f1xx_hal_usart.c.

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STM32F103xB HAL User Manual: USART Private Macros

Defines
USART Private Macros
USART

Defines

#define | IS_USART_NACK_STATE(NACK)
#define | IS_USART_LASTBIT(LASTBIT)
#define | IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
#define | IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
#define | IS_USART_CLOCK(CLOCK)
#define | IS_USART_WORD_LENGTH(LENGTH)
#define | IS_USART_STOPBITS(STOPBITS)
#define | IS_USART_PARITY(PARITY)
#define | IS_USART_MODE(MODE) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U))
#define | IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
#define | USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define | USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
#define | USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))

Define Documentation

#define IS_USART_BAUDRATE ( BAUDRATE ) ((BAUDRATE) < 4500001U)

Definition at line 559 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_CLOCK ( CLOCK )
Value:
(((CLOCK) == USART_CLOCK_DISABLE) || \
                               ((CLOCK) == USART_CLOCK_ENABLE))

Definition at line 542 of file stm32f1xx_hal_usart.h.

#define IS_USART_LASTBIT ( LASTBIT )
Value:
(((LASTBIT) == USART_LASTBIT_DISABLE) || \
                                   ((LASTBIT) == USART_LASTBIT_ENABLE))

Definition at line 535 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_MODE ( MODE ) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U))

Definition at line 557 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_NACK_STATE ( NACK )
Value:
(((NACK) == USART_NACK_ENABLE) || \
                                   ((NACK) == USART_NACK_DISABLE))

Definition at line 532 of file stm32f1xx_hal_usart.h.

#define IS_USART_PARITY ( PARITY )
Value:
(((PARITY) == USART_PARITY_NONE) || \
                                 ((PARITY) == USART_PARITY_EVEN) || \
                                 ((PARITY) == USART_PARITY_ODD))

Definition at line 553 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_PHASE ( CPHA ) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))

Definition at line 538 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_POLARITY ( CPOL ) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))

Definition at line 540 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_STOPBITS ( STOPBITS )
Value:
(((STOPBITS) == USART_STOPBITS_1)   || \
                                     ((STOPBITS) == USART_STOPBITS_0_5) || \
                                     ((STOPBITS) == USART_STOPBITS_1_5) || \
                                     ((STOPBITS) == USART_STOPBITS_2))

Definition at line 548 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

#define IS_USART_WORD_LENGTH ( LENGTH )
Value:
(((LENGTH) == USART_WORDLENGTH_8B) || \
                                      ((LENGTH) == USART_WORDLENGTH_9B))

Definition at line 545 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_BRR | ( | _PCLK_,
 |  | _BAUD_
 | ) | ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))

Definition at line 567 of file stm32f1xx_hal_usart.h.

Referenced by USART_SetConfig().

#define USART_DIV | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((_PCLK_)*25U)/(2U*(_BAUD_)))

Definition at line 561 of file stm32f1xx_hal_usart.h.

#define USART_DIVFRAQ | ( | _PCLK_,
 |  | _BAUD_
 | ) | (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)

Definition at line 565 of file stm32f1xx_hal_usart.h.

#define USART_DIVMANT | ( | _PCLK_,
 |  | _BAUD_
 | ) | (USART_DIV((_PCLK_), (_BAUD_))/100U)

Definition at line 563 of file stm32f1xx_hal_usart.h.

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STM32F103xB HAL User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
WWDG Exported Functions

Initialization and Configuration functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.

Detailed Description

Initialization and Configuration functions.

  ==============================================================================
          ##### Initialization and Configuration functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
      (+) Initialize and start the WWDG according to the specified parameters
          in the WWDG_InitTypeDef of associated handle.
      (+) Initialize the WWDG MSP.

Function Documentation

HAL_StatusTypeDef HAL_WWDG_Init ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG according to the specified.

parameters in the WWDG_InitTypeDef of associated handle.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 168 of file stm32f1xx_hal_wwdg.c.

References assert_param, WWDG_InitTypeDef::Counter, WWDG_InitTypeDef::EWIMode, HAL_WWDG_MspInit(), WWDG_HandleTypeDef::Init, WWDG_HandleTypeDef::Instance, IS_WWDG_COUNTER, IS_WWDG_EWI_MODE, IS_WWDG_PRESCALER, IS_WWDG_WINDOW, WWDG_InitTypeDef::Prescaler, and WWDG_InitTypeDef::Window.

void HAL_WWDG_MspInit ( WWDG_HandleTypeDef * hwwdg )

Initialize the WWDG MSP.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Note:
When rewriting this function in user file, mechanism may be added to avoid multiple initialize when HAL_WWDG_Init function is called again to change parameters.
Return values:
None

Definition at line 205 of file stm32f1xx_hal_wwdg.c.

Referenced by HAL_WWDG_Init().

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STM32F103xB HAL User Manual: IO operation functions

Functions
IO operation functions
WWDG Exported Functions

IO operation functions. More...

Functions

HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

IO operation functions.

  ==============================================================================
                      ##### IO operation functions #####
  ==============================================================================
  [..]
    This section provides functions allowing to:
    (+) Refresh the WWDG.
    (+) Handle WWDG interrupt request and associated function callback.

Function Documentation

void HAL_WWDG_EarlyWakeupCallback ( WWDG_HandleTypeDef * hwwdg )

WWDG Early Wakeup callback.

Parameters:
hwwdg : pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 287 of file stm32f1xx_hal_wwdg.c.

Referenced by HAL_WWDG_IRQHandler().

void HAL_WWDG_IRQHandler ( WWDG_HandleTypeDef * hwwdg )

Handle WWDG interrupt request.

Note:
The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by calling HAL_WWDG_Init function with EWIMode set to WWDG_EWI_ENABLE. When the downcounter reaches the value 0x40, and EWI interrupt is generated and the corresponding Interrupt Service Routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device.
Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
None

Definition at line 264 of file stm32f1xx_hal_wwdg.c.

References __HAL_WWDG_CLEAR_FLAG, __HAL_WWDG_GET_FLAG, __HAL_WWDG_GET_IT_SOURCE, HAL_WWDG_EarlyWakeupCallback(), WWDG_FLAG_EWIF, and WWDG_IT_EWI.

HAL_StatusTypeDef HAL_WWDG_Refresh ( WWDG_HandleTypeDef * hwwdg )

Refresh the WWDG.

Parameters:
hwwdg pointer to a WWDG_HandleTypeDef structure that contains the configuration information for the specified WWDG module.
Return values:
HAL status

Definition at line 241 of file stm32f1xx_hal_wwdg.c.

References WWDG_InitTypeDef::Counter, WWDG_HandleTypeDef::Init, and WWDG_HandleTypeDef::Instance.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: WWDG_InitTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_InitTypeDef Struct Reference
WWDG Exported Types

WWDG Init structure definition. More...

#include <stm32f1xx_hal_wwdg.h>

Data Fields

uint32_t | Prescaler
uint32_t | Window
uint32_t | Counter
uint32_t | EWIMode

Detailed Description

WWDG Init structure definition.

Definition at line 65 of file stm32f1xx_hal_wwdg.h.

Field Documentation

uint32_t WWDG_InitTypeDef::Counter

Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 73 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

uint32_t WWDG_InitTypeDef::EWIMode

Specifies if WWDG Early Wakeup Interupt is enable or not. This parameter can be a value of WWDG Early Wakeup Interrupt Mode

Definition at line 76 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Prescaler

Specifies the prescaler value of the WWDG. This parameter can be a value of WWDG Prescaler

Definition at line 67 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

uint32_t WWDG_InitTypeDef::Window

Specifies the WWDG window value to be compared to the downcounter. This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F

Definition at line 70 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_wwdg.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: WWDG_HandleTypeDef Struct Reference

  • Data Structure Index
  • Data Fields
Data Fields
WWDG_HandleTypeDef Struct Reference
WWDG Exported Types

WWDG handle Structure definition. More...

#include <stm32f1xx_hal_wwdg.h>

Data Fields

WWDG_TypeDef * Instance
WWDG_InitTypeDef Init

Detailed Description

WWDG handle Structure definition.

Definition at line 84 of file stm32f1xx_hal_wwdg.h.

Field Documentation

WWDG_InitTypeDef WWDG_HandleTypeDef::Init

WWDG required parameters

Definition at line 88 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

WWDG_TypeDef* WWDG_HandleTypeDef::Instance

Register base address

Definition at line 86 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init(), and HAL_WWDG_Refresh().

The documentation for this struct was generated from the following file:
  • stm32f1xx_hal_wwdg.h
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STM32F103xB HAL User Manual: WWDG Interrupt definition

Defines
WWDG Interrupt definition
WWDG Exported Constants

Defines

#define WWDG_IT_EWI WWDG_CFR_EWI

Define Documentation

#define WWDG_IT_EWI WWDG_CFR_EWI

Early wakeup interrupt

Definition at line 104 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: WWDG Flag definition

Defines
WWDG Flag definition
WWDG Exported Constants

WWDG Flag definition. More...

Defines

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Detailed Description

WWDG Flag definition.

Define Documentation

#define WWDG_FLAG_EWIF WWDG_SR_EWIF

Early wakeup interrupt flag

Definition at line 113 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: WWDG Prescaler

Defines
WWDG Prescaler
WWDG Exported Constants

Defines

#define | WWDG_PRESCALER_1 0x00000000U
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB1
#define | WWDG_PRESCALER_8 WWDG_CFR_WDGTB

Define Documentation

#define WWDG_PRESCALER_1 0x00000000U

WWDG counter clock = (PCLK1/4096)/1

Definition at line 121 of file stm32f1xx_hal_wwdg.h.

#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0

WWDG counter clock = (PCLK1/4096)/2

Definition at line 122 of file stm32f1xx_hal_wwdg.h.

#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1

WWDG counter clock = (PCLK1/4096)/4

Definition at line 123 of file stm32f1xx_hal_wwdg.h.

#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB

WWDG counter clock = (PCLK1/4096)/8

Definition at line 124 of file stm32f1xx_hal_wwdg.h.

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STM32F103xB HAL User Manual: WWDG Early Wakeup Interrupt Mode

Defines
WWDG Early Wakeup Interrupt Mode
WWDG Exported Constants

Defines

#define | WWDG_EWI_DISABLE 0x00000000U
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI

Define Documentation

#define WWDG_EWI_DISABLE 0x00000000U

EWI Disable

Definition at line 132 of file stm32f1xx_hal_wwdg.h.

#define WWDG_EWI_ENABLE WWDG_CFR_EWI

EWI Enable

Definition at line 133 of file stm32f1xx_hal_wwdg.h.

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STM32F103xB HAL User Manual: WWDG Private Macros

Defines
WWDG Private Macros
WWDG

Defines

#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)

Define Documentation

#define IS_WWDG_COUNTER ( __COUNTER__ ) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))

Definition at line 154 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_EWI_MODE ( __MODE__ )
Value:
(((__MODE__) == WWDG_EWI_ENABLE) || \
                                             ((__MODE__) == WWDG_EWI_DISABLE))

Definition at line 156 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_PRESCALER ( __PRESCALER__ )
Value:
(((__PRESCALER__) == WWDG_PRESCALER_1) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_2) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_4) || \
                                             ((__PRESCALER__) == WWDG_PRESCALER_8))

Definition at line 147 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

#define IS_WWDG_WINDOW ( __WINDOW__ ) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))

Definition at line 152 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_Init().

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: WWDG Exported Macros

Defines
WWDG Exported Macros
WWDG

Defines

#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enables the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enables the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Checks whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG's interrupt pending bits bits to clear the selected interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
Clears the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified WWDG interrupt source is enabled or disabled.

Define Documentation

#define __HAL_WWDG_CLEAR_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR) = ~(__FLAG__))

Clears the WWDG's pending flags.

Parameters:
__HANDLE__,: WWDG handle
__FLAG__,: specifies the flag to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
None

Definition at line 224 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_CLEAR_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

Clear the WWDG's interrupt pending bits bits to clear the selected interrupt pending bits.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__,: specifies the interrupt pending bit to clear. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag

Definition at line 204 of file stm32f1xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE ( __HANDLE__ ) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

Enables the WWDG peripheral.

Parameters:
__HANDLE__,: WWDG handle
Return values:
None

Definition at line 174 of file stm32f1xx_hal_wwdg.h.

#define __HAL_WWDG_ENABLE_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

Enables the WWDG early wakeup interrupt.

Parameters:
__HANDLE__,: WWDG handle
__INTERRUPT__ specifies the interrupt to enable. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early wakeup interrupt
Note:
Once enabled this interrupt cannot be disabled except by a system reset.
Return values:
None

Definition at line 185 of file stm32f1xx_hal_wwdg.h.

#define __HAL_WWDG_GET_FLAG | ( | __HANDLE__,
 |  | __FLAG__
 | ) | (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

Check whether the specified WWDG flag is set or not.

Parameters:
__HANDLE__ WWDG handle
__FLAG__ specifies the flag to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt flag
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 214 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

#define __HAL_WWDG_GET_IT | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

Checks whether the selected WWDG interrupt has occurred or not.

Parameters:
__HANDLE__ WWDG handle
__INTERRUPT__ specifies the it to check. This parameter can be one of the following values:
  • WWDG_FLAG_EWIF: Early wakeup interrupt IT
Return values:
The new state of WWDG_FLAG (SET or RESET).

Definition at line 195 of file stm32f1xx_hal_wwdg.h.

#define __HAL_WWDG_GET_IT_SOURCE | ( | __HANDLE__,
 |  | __INTERRUPT__
 | ) | (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))

Checks if the specified WWDG interrupt source is enabled or disabled.

Parameters:
__HANDLE__,: WWDG Handle.
__INTERRUPT__,: specifies the WWDG interrupt source to check. This parameter can be one of the following values:
  • WWDG_IT_EWI: Early Wakeup Interrupt
Return values:
state of __INTERRUPT__ (TRUE or FALSE).

Definition at line 233 of file stm32f1xx_hal_wwdg.h.

Referenced by HAL_WWDG_IRQHandler().

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  • ABOM : CAN_InitTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • Address : FLASH_ProcessTypeDef
  • AddressingMode : I2C_InitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AudioFreq : LL_I2S_InitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AWUM : CAN_InitTypeDef
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  • BankNumber : CAN_FilterConfTypeDef
  • Banks : FLASH_EraseInitTypeDef , FLASH_OBProgramInitTypeDef
  • BaudRate : IRDA_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BreakPolarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakState : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BS1 : CAN_InitTypeDef
  • BS2 : CAN_InitTypeDef
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  • Channel : ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef , TIM_HandleTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SPI_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : LL_USART_ClockInitTypeDef , TIM_ClockConfigTypeDef , LL_I2S_InitTypeDef , LL_SPI_InitTypeDef
  • ClockPrescaler : TIM_ClockConfigTypeDef
  • ClockSource : TIM_ClockConfigTypeDef
  • ClockSpeed : LL_I2C_InitTypeDef , I2C_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
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  • Data : CanTxMsgTypeDef , CanRxMsgTypeDef , FLASH_ProcessTypeDef
  • DATAAddress : FLASH_OBProgramInitTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DATAData : FLASH_OBProgramInitTypeDef
  • DataFormat : LL_I2S_InitTypeDef
  • DataRemaining : FLASH_ProcessTypeDef
  • DataSize : SPI_InitTypeDef
  • DataWidth : LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • Date : RTC_DateTypeDef
  • DateToUpdate : RTC_HandleTypeDef
  • DeadTime : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Devaddress : I2C_HandleTypeDef
  • Direction : DMA_InitTypeDef , LL_DMA_InitTypeDef , SPI_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DLC : CanRxMsgTypeDef , CanTxMsgTypeDef
  • DMA_Handle : ADC_HandleTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • DualAddressMode : I2C_InitTypeDef
  • DutyCycle : LL_I2C_InitTypeDef , I2C_InitTypeDef
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • ErrorCode : CAN_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , __DMA_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , ADC_HandleTypeDef , FLASH_ProcessTypeDef , I2C_HandleTypeDef
  • EventCount : I2C_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExtId : CanTxMsgTypeDef , CanRxMsgTypeDef
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  • FIFONumber : CanRxMsgTypeDef
  • FilterActivation : CAN_FilterConfTypeDef
  • FilterFIFOAssignment : CAN_FilterConfTypeDef
  • FilterIdHigh : CAN_FilterConfTypeDef
  • FilterIdLow : CAN_FilterConfTypeDef
  • FilterMaskIdHigh : CAN_FilterConfTypeDef
  • FilterMaskIdLow : CAN_FilterConfTypeDef
  • FilterMode : CAN_FilterConfTypeDef
  • FilterNumber : CAN_FilterConfTypeDef
  • FilterScale : CAN_FilterConfTypeDef
  • FirstBit : SPI_InitTypeDef
  • FMI : CanRxMsgTypeDef
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  • GeneralCallMode : I2C_InitTypeDef
  • gState : IRDA_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • HardwareFlowControl : LL_USART_InitTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : TIM_HandleTypeDef
  • hdmarx : I2C_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • hdmatx : I2C_HandleTypeDef , __SPI_HandleTypeDef , IRDA_HandleTypeDef , USART_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • Hours : RTC_TimeTypeDef
  • HSEPredivValue : RCC_OscInitTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IDE : CanTxMsgTypeDef , CanRxMsgTypeDef
  • IN_ep : PCD_HandleTypeDef
  • Init : PCD_HandleTypeDef , ADC_HandleTypeDef , CAN_HandleTypeDef , __DMA_HandleTypeDef , I2C_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , RTC_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , TIM_HandleTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : WWDG_HandleTypeDef , CAN_HandleTypeDef , ADC_HandleTypeDef , __SPI_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , UART_HandleTypeDef , IWDG_HandleTypeDef , TIM_HandleTypeDef , IRDA_HandleTypeDef , RTC_HandleTypeDef , SMARTCARD_HandleTypeDef , I2C_HandleTypeDef , PCD_HandleTypeDef , USART_HandleTypeDef
  • IrDAMode : IRDA_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

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  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • Lock : ADC_HandleTypeDef , FLASH_ProcessTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , I2C_HandleTypeDef , TIM_HandleTypeDef , __SPI_HandleTypeDef , SMARTCARD_HandleTypeDef , CAN_HandleTypeDef , IRDA_HandleTypeDef , PCD_HandleTypeDef , CRC_HandleTypeDef , RTC_HandleTypeDef , __DMA_HandleTypeDef
  • LockLevel : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MCLKOutput : LL_I2S_InitTypeDef
  • Memaddress : I2C_HandleTypeDef
  • MemaddSize : I2C_HandleTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • Minutes : RTC_TimeTypeDef
  • Mode : SMARTCARD_InitTypeDef , PWR_PVDTypeDef , IRDA_InitTypeDef , SPI_InitTypeDef , GPIO_InitTypeDef , DMA_InitTypeDef , CAN_InitTypeDef , LL_DMA_InitTypeDef , USART_InitTypeDef , LL_SPI_InitTypeDef , I2C_HandleTypeDef , LL_I2S_InitTypeDef , LL_GPIO_InitTypeDef , LL_EXTI_InitTypeDef , UART_InitTypeDef , ADC_MultiModeTypeDef
  • Month : RTC_DateTypeDef
  • Multimode : LL_ADC_CommonInitTypeDef
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • NACKState : SMARTCARD_InitTypeDef
  • NART : CAN_InitTypeDef
  • NbData : LL_DMA_InitTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NoStretchMode : I2C_InitTypeDef
  • NSS : SPI_InitTypeDef , LL_SPI_InitTypeDef
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OUT_ep : PCD_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • OverSampling : UART_InitTypeDef
  • OwnAddress1 : LL_I2C_InitTypeDef , I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • PageAddress : FLASH_EraseInitTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : SMARTCARD_InitTypeDef , UART_InitTypeDef , IRDA_InitTypeDef , USART_InitTypeDef , LL_USART_InitTypeDef
  • pBuffPtr : I2C_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • pData : PCD_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLMul : LL_UTILS_PLLInitTypeDef
  • PLLMUL : RCC_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • Prediv : LL_UTILS_PLLInitTypeDef
  • Prescaler : TIM_Base_InitTypeDef , WWDG_InitTypeDef , LL_TIM_InitTypeDef , SMARTCARD_InitTypeDef , CAN_InitTypeDef , IRDA_InitTypeDef , IWDG_InitTypeDef
  • PreviousState : I2C_HandleTypeDef
  • Priority : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • pRxBuffPtr : USART_HandleTypeDef , IRDA_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , SMARTCARD_HandleTypeDef
  • pRxMsg : CAN_HandleTypeDef
  • pTxBuffPtr : SMARTCARD_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef
  • pTxMsg : CAN_HandleTypeDef
  • Pull : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Pulse : TIM_OnePulse_InitTypeDef , TIM_OC_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • Rank : ADC_ChannelConfTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • Reload : IWDG_InitTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • RFLM : CAN_InitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RTR : CanTxMsgTypeDef , CanRxMsgTypeDef
  • RxISR : __SPI_HandleTypeDef
  • RxState : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • RxXferCount : UART_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , SMARTCARD_HandleTypeDef , IRDA_HandleTypeDef
  • RxXferSize : SMARTCARD_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
  • b
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • Seconds : RTC_TimeTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencersScanMode : LL_ADC_InitTypeDef
  • Setup : PCD_HandleTypeDef
  • SJW : CAN_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Standard : LL_I2S_InitTypeDef
  • State : I2C_HandleTypeDef , TIM_HandleTypeDef , CAN_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , PCD_HandleTypeDef , RTC_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , ADC_HandleTypeDef
  • StdId : CanRxMsgTypeDef , CanTxMsgTypeDef
  • StopBits : SMARTCARD_InitTypeDef , USART_InitTypeDef , LL_USART_InitTypeDef , UART_InitTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • Tamper : RTC_TamperTypeDef
  • TIMode : SPI_InitTypeDef
  • TransferDirection : LL_USART_InitTypeDef , LL_SPI_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • TTCM : CAN_InitTypeDef
  • TXFP : CAN_InitTypeDef
  • TxISR : __SPI_HandleTypeDef
  • TxXferCount : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef
  • TxXferSize : SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • USB_Address : PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WeekDay : RTC_DateTypeDef
  • Window : WWDG_InitTypeDef
  • WordLength : UART_InitTypeDef , USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef
  • WRPPage : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : I2C_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferOptions : I2C_HandleTypeDef
  • XferSize : I2C_HandleTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • Year : RTC_DateTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- a -

  • ABOM : CAN_InitTypeDef
  • AdcClockSelection : RCC_PeriphCLKInitTypeDef
  • Address : FLASH_ProcessTypeDef
  • AddressingMode : I2C_InitTypeDef
  • AHBCLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • Alarm : RTC_AlarmTypeDef
  • AlarmTime : RTC_AlarmTypeDef
  • APB1CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • APB2CLKDivider : RCC_ClkInitTypeDef , LL_UTILS_ClkInitTypeDef
  • AsynchPrediv : RTC_InitTypeDef
  • AudioFreq : LL_I2S_InitTypeDef
  • AutoInjectedConv : ADC_InjectionConfTypeDef
  • AutomaticOutput : TIM_BreakDeadTimeConfigTypeDef , LL_TIM_BDTR_InitTypeDef
  • Autoreload : LL_TIM_InitTypeDef
  • AutoReloadPreload : TIM_Base_InitTypeDef
  • AWUM : CAN_InitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- b -

  • BankNumber : CAN_FilterConfTypeDef
  • Banks : FLASH_EraseInitTypeDef , FLASH_OBProgramInitTypeDef
  • BaudRate : IRDA_InitTypeDef , LL_SPI_InitTypeDef , LL_USART_InitTypeDef , SMARTCARD_InitTypeDef , UART_InitTypeDef , USART_InitTypeDef
  • BaudRatePrescaler : SPI_InitTypeDef
  • BitOrder : LL_SPI_InitTypeDef
  • BreakPolarity : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BreakState : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • BS1 : CAN_InitTypeDef
  • BS2 : CAN_InitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- c -

  • Channel : ADC_ChannelConfTypeDef , ADC_AnalogWDGConfTypeDef , TIM_HandleTypeDef
  • ChannelIndex : __DMA_HandleTypeDef
  • ClearInputFilter : TIM_ClearInputConfigTypeDef
  • ClearInputPolarity : TIM_ClearInputConfigTypeDef
  • ClearInputPrescaler : TIM_ClearInputConfigTypeDef
  • ClearInputSource : TIM_ClearInputConfigTypeDef
  • ClearInputState : TIM_ClearInputConfigTypeDef
  • CLKLastBit : SMARTCARD_InitTypeDef , USART_InitTypeDef
  • CLKPhase : SMARTCARD_InitTypeDef , SPI_InitTypeDef , USART_InitTypeDef
  • CLKPolarity : SPI_InitTypeDef , USART_InitTypeDef , SMARTCARD_InitTypeDef
  • ClockDivision : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • ClockFilter : TIM_ClockConfigTypeDef
  • ClockOutput : LL_USART_ClockInitTypeDef
  • ClockPhase : LL_SPI_InitTypeDef , LL_USART_ClockInitTypeDef
  • ClockPolarity : LL_USART_ClockInitTypeDef , TIM_ClockConfigTypeDef , LL_I2S_InitTypeDef , LL_SPI_InitTypeDef
  • ClockPrescaler : TIM_ClockConfigTypeDef
  • ClockSource : TIM_ClockConfigTypeDef
  • ClockSpeed : LL_I2C_InitTypeDef , I2C_InitTypeDef
  • ClockType : RCC_ClkInitTypeDef
  • Commutation_Delay : TIM_HallSensor_InitTypeDef
  • CommutationDelay : LL_TIM_HALLSENSOR_InitTypeDef
  • CompareValue : LL_TIM_OC_InitTypeDef
  • ContinuousConvMode : ADC_InitTypeDef
  • ContinuousMode : LL_ADC_REG_InitTypeDef
  • Counter : WWDG_InitTypeDef
  • CounterMode : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • CRCCalculation : LL_SPI_InitTypeDef , SPI_InitTypeDef
  • CRCPoly : LL_SPI_InitTypeDef
  • CRCPolynomial : SPI_InitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- d -

  • Data : CanTxMsgTypeDef , CanRxMsgTypeDef , FLASH_ProcessTypeDef
  • DATAAddress : FLASH_OBProgramInitTypeDef
  • DataAlign : ADC_InitTypeDef
  • DataAlignment : LL_ADC_InitTypeDef
  • DATAData : FLASH_OBProgramInitTypeDef
  • DataFormat : LL_I2S_InitTypeDef
  • DataRemaining : FLASH_ProcessTypeDef
  • DataSize : SPI_InitTypeDef
  • DataWidth : LL_SPI_InitTypeDef , LL_USART_InitTypeDef
  • Date : RTC_DateTypeDef
  • DateToUpdate : RTC_HandleTypeDef
  • DeadTime : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • Devaddress : I2C_HandleTypeDef
  • Direction : DMA_InitTypeDef , LL_DMA_InitTypeDef , SPI_InitTypeDef
  • DiscontinuousConvMode : ADC_InitTypeDef
  • DLC : CanRxMsgTypeDef , CanTxMsgTypeDef
  • DMA_Handle : ADC_HandleTypeDef
  • DmaBaseAddress : __DMA_HandleTypeDef
  • DMATransfer : LL_ADC_REG_InitTypeDef
  • DualAddressMode : I2C_InitTypeDef
  • DutyCycle : LL_I2C_InitTypeDef , I2C_InitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
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- e -

  • EncoderMode : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • ErrorCode : CAN_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , __DMA_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , ADC_HandleTypeDef , FLASH_ProcessTypeDef , I2C_HandleTypeDef
  • EventCount : I2C_HandleTypeDef
  • EWIMode : WWDG_InitTypeDef
  • ExternalTrigConv : ADC_InitTypeDef
  • ExternalTrigInjecConv : ADC_InjectionConfTypeDef
  • ExtId : CanTxMsgTypeDef , CanRxMsgTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- f -

  • FIFONumber : CanRxMsgTypeDef
  • FilterActivation : CAN_FilterConfTypeDef
  • FilterFIFOAssignment : CAN_FilterConfTypeDef
  • FilterIdHigh : CAN_FilterConfTypeDef
  • FilterIdLow : CAN_FilterConfTypeDef
  • FilterMaskIdHigh : CAN_FilterConfTypeDef
  • FilterMaskIdLow : CAN_FilterConfTypeDef
  • FilterMode : CAN_FilterConfTypeDef
  • FilterNumber : CAN_FilterConfTypeDef
  • FilterScale : CAN_FilterConfTypeDef
  • FirstBit : SPI_InitTypeDef
  • FMI : CanRxMsgTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- g -

  • GeneralCallMode : I2C_InitTypeDef
  • gState : IRDA_HandleTypeDef , UART_HandleTypeDef , SMARTCARD_HandleTypeDef
  • GuardTime : SMARTCARD_InitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- h -

  • HardwareFlowControl : LL_USART_InitTypeDef
  • HCLK_Frequency : LL_RCC_ClocksTypeDef
  • hdma : TIM_HandleTypeDef
  • hdmarx : I2C_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef
  • hdmatx : I2C_HandleTypeDef , __SPI_HandleTypeDef , IRDA_HandleTypeDef , USART_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • HighThreshold : ADC_AnalogWDGConfTypeDef
  • Hours : RTC_TimeTypeDef
  • HSEPredivValue : RCC_OscInitTypeDef
  • HSEState : RCC_OscInitTypeDef
  • HSICalibrationValue : RCC_OscInitTypeDef
  • HSIState : RCC_OscInitTypeDef
  • HwFlowCtl : UART_InitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- i -

  • IC1ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC1Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Polarity : LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef , TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef
  • IC1Prescaler : TIM_Encoder_InitTypeDef , TIM_HallSensor_InitTypeDef , LL_TIM_ENCODER_InitTypeDef , LL_TIM_HALLSENSOR_InitTypeDef
  • IC1Selection : TIM_Encoder_InitTypeDef
  • IC2ActiveInput : LL_TIM_ENCODER_InitTypeDef
  • IC2Filter : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Polarity : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Prescaler : TIM_Encoder_InitTypeDef , LL_TIM_ENCODER_InitTypeDef
  • IC2Selection : TIM_Encoder_InitTypeDef
  • ICActiveInput : LL_TIM_IC_InitTypeDef
  • ICFilter : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPolarity : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICPrescaler : TIM_IC_InitTypeDef , LL_TIM_IC_InitTypeDef
  • ICSelection : TIM_OnePulse_InitTypeDef , TIM_IC_InitTypeDef
  • IDE : CanTxMsgTypeDef , CanRxMsgTypeDef
  • IN_ep : PCD_HandleTypeDef
  • Init : PCD_HandleTypeDef , ADC_HandleTypeDef , CAN_HandleTypeDef , __DMA_HandleTypeDef , I2C_HandleTypeDef , IRDA_HandleTypeDef , IWDG_HandleTypeDef , RTC_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , WWDG_HandleTypeDef , TIM_HandleTypeDef
  • InjectedChannel : ADC_InjectionConfTypeDef
  • InjectedDiscontinuousConvMode : ADC_InjectionConfTypeDef
  • InjectedNbrOfConversion : ADC_InjectionConfTypeDef
  • InjectedOffset : ADC_InjectionConfTypeDef
  • InjectedRank : ADC_InjectionConfTypeDef
  • InjectedSamplingTime : ADC_InjectionConfTypeDef
  • InputTrigger : TIM_SlaveConfigTypeDef
  • Instance : WWDG_HandleTypeDef , CAN_HandleTypeDef , ADC_HandleTypeDef , __SPI_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , UART_HandleTypeDef , IWDG_HandleTypeDef , TIM_HandleTypeDef , IRDA_HandleTypeDef , RTC_HandleTypeDef , SMARTCARD_HandleTypeDef , I2C_HandleTypeDef , PCD_HandleTypeDef , USART_HandleTypeDef
  • IrDAMode : IRDA_InitTypeDef
  • ITMode : ADC_AnalogWDGConfTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- l -

  • LastBitClockPulse : LL_USART_ClockInitTypeDef
  • Line_0_31 : LL_EXTI_InitTypeDef
  • LineCommand : LL_EXTI_InitTypeDef
  • Lock : ADC_HandleTypeDef , FLASH_ProcessTypeDef , UART_HandleTypeDef , USART_HandleTypeDef , I2C_HandleTypeDef , TIM_HandleTypeDef , __SPI_HandleTypeDef , SMARTCARD_HandleTypeDef , CAN_HandleTypeDef , IRDA_HandleTypeDef , PCD_HandleTypeDef , CRC_HandleTypeDef , RTC_HandleTypeDef , __DMA_HandleTypeDef
  • LockLevel : LL_TIM_BDTR_InitTypeDef , TIM_BreakDeadTimeConfigTypeDef
  • LowThreshold : ADC_AnalogWDGConfTypeDef
  • LSEState : RCC_OscInitTypeDef
  • LSIState : RCC_OscInitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

  • Data Structure Index
  • Data Fields
  • All
  • Variables
  • a
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- m -

  • MasterOutputTrigger : TIM_MasterConfigTypeDef
  • MasterSlaveMode : TIM_MasterConfigTypeDef
  • MCLKOutput : LL_I2S_InitTypeDef
  • Memaddress : I2C_HandleTypeDef
  • MemaddSize : I2C_HandleTypeDef
  • MemDataAlignment : DMA_InitTypeDef
  • MemInc : DMA_InitTypeDef
  • MemoryOrM2MDstAddress : LL_DMA_InitTypeDef
  • MemoryOrM2MDstDataSize : LL_DMA_InitTypeDef
  • MemoryOrM2MDstIncMode : LL_DMA_InitTypeDef
  • Minutes : RTC_TimeTypeDef
  • Mode : SMARTCARD_InitTypeDef , PWR_PVDTypeDef , IRDA_InitTypeDef , SPI_InitTypeDef , GPIO_InitTypeDef , DMA_InitTypeDef , CAN_InitTypeDef , LL_DMA_InitTypeDef , USART_InitTypeDef , LL_SPI_InitTypeDef , I2C_HandleTypeDef , LL_I2S_InitTypeDef , LL_GPIO_InitTypeDef , LL_EXTI_InitTypeDef , UART_InitTypeDef , ADC_MultiModeTypeDef
  • Month : RTC_DateTypeDef
  • Multimode : LL_ADC_CommonInitTypeDef
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Fields - Variables

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- n -

  • NACKState : SMARTCARD_InitTypeDef
  • NART : CAN_InitTypeDef
  • NbData : LL_DMA_InitTypeDef
  • NbPages : FLASH_EraseInitTypeDef
  • NbrOfConversion : ADC_InitTypeDef
  • NbrOfDiscConversion : ADC_InitTypeDef
  • NoStretchMode : I2C_InitTypeDef
  • NSS : SPI_InitTypeDef , LL_SPI_InitTypeDef
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STM32F103xB HAL User Manual: Data Fields - Variables

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  • OCFastMode : TIM_OC_InitTypeDef
  • OCIdleState : TIM_OC_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef
  • OCMode : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNIdleState : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNPolarity : TIM_OC_InitTypeDef , TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef
  • OCNState : LL_TIM_OC_InitTypeDef
  • OCPolarity : TIM_OnePulse_InitTypeDef , LL_TIM_OC_InitTypeDef , TIM_OC_InitTypeDef
  • OCState : LL_TIM_OC_InitTypeDef
  • OffStateIDLEMode : TIM_BreakDeadTimeConfigTypeDef
  • OffStateRunMode : TIM_BreakDeadTimeConfigTypeDef
  • OptionType : FLASH_OBProgramInitTypeDef
  • OscillatorType : RCC_OscInitTypeDef
  • OSSIState : LL_TIM_BDTR_InitTypeDef
  • OSSRState : LL_TIM_BDTR_InitTypeDef
  • OUT_ep : PCD_HandleTypeDef
  • OutPut : RTC_InitTypeDef
  • OutputType : LL_GPIO_InitTypeDef
  • OverSampling : UART_InitTypeDef
  • OwnAddress1 : LL_I2C_InitTypeDef , I2C_InitTypeDef
  • OwnAddress2 : I2C_InitTypeDef
  • OwnAddrSize : LL_I2C_InitTypeDef
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STM32F103xB HAL User Manual: Data Fields - Variables

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  • PageAddress : FLASH_EraseInitTypeDef
  • Parent : __DMA_HandleTypeDef
  • Parity : SMARTCARD_InitTypeDef , UART_InitTypeDef , IRDA_InitTypeDef , USART_InitTypeDef , LL_USART_InitTypeDef
  • pBuffPtr : I2C_HandleTypeDef
  • PCLK1_Frequency : LL_RCC_ClocksTypeDef
  • PCLK2_Frequency : LL_RCC_ClocksTypeDef
  • pData : PCD_HandleTypeDef
  • Period : TIM_Base_InitTypeDef
  • PeriphClockSelection : RCC_PeriphCLKInitTypeDef
  • PeriphDataAlignment : DMA_InitTypeDef
  • PeripheralMode : LL_I2C_InitTypeDef
  • PeriphInc : DMA_InitTypeDef
  • PeriphOrM2MSrcAddress : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcDataSize : LL_DMA_InitTypeDef
  • PeriphOrM2MSrcIncMode : LL_DMA_InitTypeDef
  • Pin : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • PLL : RCC_OscInitTypeDef
  • PLLMul : LL_UTILS_PLLInitTypeDef
  • PLLMUL : RCC_PLLInitTypeDef
  • PLLSource : RCC_PLLInitTypeDef
  • PLLState : RCC_PLLInitTypeDef
  • Prediv : LL_UTILS_PLLInitTypeDef
  • Prescaler : TIM_Base_InitTypeDef , WWDG_InitTypeDef , LL_TIM_InitTypeDef , SMARTCARD_InitTypeDef , CAN_InitTypeDef , IRDA_InitTypeDef , IWDG_InitTypeDef
  • PreviousState : I2C_HandleTypeDef
  • Priority : DMA_InitTypeDef , LL_DMA_InitTypeDef
  • ProcedureOnGoing : FLASH_ProcessTypeDef
  • pRxBuffPtr : USART_HandleTypeDef , IRDA_HandleTypeDef , UART_HandleTypeDef , __SPI_HandleTypeDef , SMARTCARD_HandleTypeDef
  • pRxMsg : CAN_HandleTypeDef
  • pTxBuffPtr : SMARTCARD_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef
  • pTxMsg : CAN_HandleTypeDef
  • Pull : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Pulse : TIM_OnePulse_InitTypeDef , TIM_OC_InitTypeDef
  • PVDLevel : PWR_PVDTypeDef
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STM32F103xB HAL User Manual: Data Fields - Variables

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  • Rank : ADC_ChannelConfTypeDef
  • RDPLevel : FLASH_OBProgramInitTypeDef
  • Reload : IWDG_InitTypeDef
  • RepetitionCounter : TIM_Base_InitTypeDef , LL_TIM_InitTypeDef
  • RFLM : CAN_InitTypeDef
  • RTCClockSelection : RCC_PeriphCLKInitTypeDef
  • RTR : CanTxMsgTypeDef , CanRxMsgTypeDef
  • RxISR : __SPI_HandleTypeDef
  • RxState : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , UART_HandleTypeDef
  • RxXferCount : UART_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , SMARTCARD_HandleTypeDef , IRDA_HandleTypeDef
  • RxXferSize : SMARTCARD_HandleTypeDef , USART_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef
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STM32F103xB HAL User Manual: Data Fields - Variables

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  • SamplingTime : ADC_ChannelConfTypeDef
  • ScanConvMode : ADC_InitTypeDef
  • Seconds : RTC_TimeTypeDef
  • SequencerDiscont : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencerLength : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • SequencersScanMode : LL_ADC_InitTypeDef
  • Setup : PCD_HandleTypeDef
  • SJW : CAN_InitTypeDef
  • SlaveMode : TIM_SlaveConfigTypeDef
  • Speed : GPIO_InitTypeDef , LL_GPIO_InitTypeDef
  • Standard : LL_I2S_InitTypeDef
  • State : I2C_HandleTypeDef , TIM_HandleTypeDef , CAN_HandleTypeDef , CRC_HandleTypeDef , __DMA_HandleTypeDef , PCD_HandleTypeDef , RTC_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , ADC_HandleTypeDef
  • StdId : CanRxMsgTypeDef , CanTxMsgTypeDef
  • StopBits : SMARTCARD_InitTypeDef , USART_InitTypeDef , LL_USART_InitTypeDef , UART_InitTypeDef
  • SYSCLK_Frequency : LL_RCC_ClocksTypeDef
  • SYSCLKSource : RCC_ClkInitTypeDef
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STM32F103xB HAL User Manual: Data Fields - Variables

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  • Tamper : RTC_TamperTypeDef
  • TIMode : SPI_InitTypeDef
  • TransferDirection : LL_USART_InitTypeDef , LL_SPI_InitTypeDef
  • TrigAuto : LL_ADC_INJ_InitTypeDef
  • Trigger : RTC_TamperTypeDef , LL_EXTI_InitTypeDef
  • TriggerFilter : TIM_SlaveConfigTypeDef
  • TriggerPolarity : TIM_SlaveConfigTypeDef
  • TriggerPrescaler : TIM_SlaveConfigTypeDef
  • TriggerSource : LL_ADC_REG_InitTypeDef , LL_ADC_INJ_InitTypeDef
  • TTCM : CAN_InitTypeDef
  • TXFP : CAN_InitTypeDef
  • TxISR : __SPI_HandleTypeDef
  • TxXferCount : IRDA_HandleTypeDef , SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , UART_HandleTypeDef , USART_HandleTypeDef
  • TxXferSize : SMARTCARD_HandleTypeDef , __SPI_HandleTypeDef , USART_HandleTypeDef , UART_HandleTypeDef , IRDA_HandleTypeDef
  • TypeAcknowledge : LL_I2C_InitTypeDef
  • TypeErase : FLASH_EraseInitTypeDef
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STM32F103xB HAL User Manual: Data Fields - Variables

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  • USB_Address : PCD_HandleTypeDef
  • UsbClockSelection : RCC_PeriphCLKInitTypeDef
  • USERConfig : FLASH_OBProgramInitTypeDef
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STM32F103xB HAL User Manual: Data Fields - Variables

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  • WatchdogMode : ADC_AnalogWDGConfTypeDef
  • WatchdogNumber : ADC_AnalogWDGConfTypeDef
  • WeekDay : RTC_DateTypeDef
  • Window : WWDG_InitTypeDef
  • WordLength : UART_InitTypeDef , USART_InitTypeDef , IRDA_InitTypeDef , SMARTCARD_InitTypeDef
  • WRPPage : FLASH_OBProgramInitTypeDef
  • WRPState : FLASH_OBProgramInitTypeDef
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STM32F103xB HAL User Manual: Data Fields - Variables

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  • XferAbortCallback : __DMA_HandleTypeDef
  • XferCount : I2C_HandleTypeDef
  • XferCpltCallback : __DMA_HandleTypeDef
  • XferErrorCallback : __DMA_HandleTypeDef
  • XferHalfCpltCallback : __DMA_HandleTypeDef
  • XferOptions : I2C_HandleTypeDef
  • XferSize : I2C_HandleTypeDef
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- y -

  • Year : RTC_DateTypeDef
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STM32F103xB HAL User Manual: stm32f1xx_hal_cec.c File Reference

  • File List
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  • Drivers
  • STM32F1xx_HAL_Driver
  • Src
stm32f1xx_hal_cec.c File Reference

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
    [..]
    The CEC HAL driver can be used as follow:

    (#) Declare a CEC_HandleTypeDef handle structure.
    (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
        (##) Enable the CEC interface clock.
        (##) CEC pins configuration:
            (+++) Enable the clock for the CEC GPIOs.
            (+++) Configure these CEC pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
             and HAL_CEC_Receive_IT() APIs):
            (+++) Configure the CEC interrupt priority.
            (+++) Enable the NVIC CEC IRQ handle.
            (+++) The specific CEC interrupts (Transmission complete interrupt,
                  RXNE interrupt and Error Interrupts) will be managed using the macros
                  __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
                  and receive process.

    (#) Program the Bit Timing Error Mode and the Bit Period Error Mode in the hcec Init structure.

    (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.

  [..]
    (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
        by calling the customed HAL_CEC_MspInit() API.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_cec.c.

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STM32F103xB HAL User Manual: stm32f1xx_hal_cec.h File Reference

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stm32f1xx_hal_cec.h File Reference

Header file of CEC HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of CEC HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_cec.h.

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STM32F103xB HAL User Manual: stm32f1xx_hal_conf.h File Reference

  • File List
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Defines
stm32f1xx_hal_conf.h File Reference

HAL configuration template file. This file should be copied to the application folder and renamed to stm32f1xx_hal_conf.h. More...

#include "stm32f1xx_hal_rcc.h"
#include "stm32f1xx_hal_gpio.h"
#include "stm32f1xx_hal_dma.h"
#include "stm32f1xx_hal_eth.h"
#include "stm32f1xx_hal_can.h"
#include "stm32f1xx_hal_cec.h"
#include "stm32f1xx_hal_cortex.h"
#include "stm32f1xx_hal_adc.h"
#include "stm32f1xx_hal_crc.h"
#include "stm32f1xx_hal_dac.h"
#include "stm32f1xx_hal_flash.h"
#include "stm32f1xx_hal_sram.h"
#include "stm32f1xx_hal_nor.h"
#include "stm32f1xx_hal_i2c.h"
#include "stm32f1xx_hal_i2s.h"
#include "stm32f1xx_hal_iwdg.h"
#include "stm32f1xx_hal_pwr.h"
#include "stm32f1xx_hal_rtc.h"
#include "stm32f1xx_hal_pccard.h"
#include "stm32f1xx_hal_sd.h"
#include "stm32f1xx_hal_nand.h"
#include "stm32f1xx_hal_spi.h"
#include "stm32f1xx_hal_tim.h"
#include "stm32f1xx_hal_uart.h"
#include "stm32f1xx_hal_usart.h"
#include "stm32f1xx_hal_irda.h"
#include "stm32f1xx_hal_smartcard.h"
#include "stm32f1xx_hal_wwdg.h"
#include "stm32f1xx_hal_pcd.h"
#include "stm32f1xx_hal_hcd.h"

Go to the source code of this file.

Defines

#define | HAL_MODULE_ENABLED
This is the list of modules to be used in the HAL driver.
#define | HAL_ADC_MODULE_ENABLED
#define | HAL_CAN_MODULE_ENABLED
#define | HAL_CEC_MODULE_ENABLED
#define | HAL_CORTEX_MODULE_ENABLED
#define | HAL_CRC_MODULE_ENABLED
#define | HAL_DAC_MODULE_ENABLED
#define | HAL_DMA_MODULE_ENABLED
#define | HAL_ETH_MODULE_ENABLED
#define | HAL_FLASH_MODULE_ENABLED
#define | HAL_GPIO_MODULE_ENABLED
#define | HAL_HCD_MODULE_ENABLED
#define | HAL_I2C_MODULE_ENABLED
#define | HAL_I2S_MODULE_ENABLED
#define | HAL_IRDA_MODULE_ENABLED
#define | HAL_IWDG_MODULE_ENABLED
#define | HAL_NAND_MODULE_ENABLED
#define | HAL_NOR_MODULE_ENABLED
#define | HAL_PCCARD_MODULE_ENABLED
#define | HAL_PCD_MODULE_ENABLED
#define | HAL_PWR_MODULE_ENABLED
#define | HAL_RCC_MODULE_ENABLED
#define | HAL_RTC_MODULE_ENABLED
#define | HAL_SD_MODULE_ENABLED
#define | HAL_SMARTCARD_MODULE_ENABLED
#define | HAL_SPI_MODULE_ENABLED
#define | HAL_SRAM_MODULE_ENABLED
#define | HAL_TIM_MODULE_ENABLED
#define | HAL_UART_MODULE_ENABLED
#define | HAL_USART_MODULE_ENABLED
#define | HAL_WWDG_MODULE_ENABLED
#define | HSE_VALUE 8000000U
Adjust the value of External High Speed oscillator (HSE) used in your application.
#define | HSE_STARTUP_TIMEOUT 100U
#define | HSI_VALUE 8000000U
Internal High Speed oscillator (HSI) value.
#define | LSI_VALUE 40000U
Internal Low Speed oscillator (LSI) value.
#define | LSE_VALUE 32768U
External Low Speed oscillator (LSE) value.
#define | LSE_STARTUP_TIMEOUT 5000U
#define | VDD_VALUE 3300U
This is the HAL system configuration section.
#define | TICK_INT_PRIORITY 0x0FU
#define | USE_RTOS 0U
#define | PREFETCH_ENABLE 1U
#define | MAC_ADDR0 2U
Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.
#define | MAC_ADDR1 0U
#define | MAC_ADDR2 0U
#define | MAC_ADDR3 0U
#define | MAC_ADDR4 0U
#define | MAC_ADDR5 0U
#define | ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define | ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define | ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */
#define | ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
#define | DP83848_PHY_ADDRESS 0x01U
#define | PHY_RESET_DELAY 0x000000FFU
#define | PHY_CONFIG_DELAY 0x00000FFFU
#define | PHY_READ_TO 0x0000FFFFU
#define | PHY_WRITE_TO 0x0000FFFFU
#define | PHY_BCR ((uint16_t)0x0000)
#define | PHY_BSR ((uint16_t)0x0001)
#define | PHY_RESET ((uint16_t)0x8000)
#define | PHY_LOOPBACK ((uint16_t)0x4000)
#define | PHY_FULLDUPLEX_100M ((uint16_t)0x2100)
#define | PHY_HALFDUPLEX_100M ((uint16_t)0x2000)
#define | PHY_FULLDUPLEX_10M ((uint16_t)0x0100)
#define | PHY_HALFDUPLEX_10M ((uint16_t)0x0000)
#define | PHY_AUTONEGOTIATION ((uint16_t)0x1000)
#define | PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200)
#define | PHY_POWERDOWN ((uint16_t)0x0800)
#define | PHY_ISOLATE ((uint16_t)0x0400)
#define | PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020)
#define | PHY_LINKED_STATUS ((uint16_t)0x0004)
#define | PHY_JABBER_DETECTION ((uint16_t)0x0002)
#define | PHY_SR ((uint16_t)0x0010)
#define | PHY_MICR ((uint16_t)0x0011)
#define | PHY_MISR ((uint16_t)0x0012)
#define | PHY_LINK_STATUS ((uint16_t)0x0001)
#define | PHY_SPEED_STATUS ((uint16_t)0x0002)
#define | PHY_DUPLEX_STATUS ((uint16_t)0x0004)
#define | PHY_MICR_INT_EN ((uint16_t)0x0002)
#define | PHY_MICR_INT_OE ((uint16_t)0x0001)
#define | PHY_MISR_LINK_INT_EN ((uint16_t)0x0020)
#define | PHY_LINK_INTERRUPT ((uint16_t)0x2000)
#define | USE_SPI_CRC 1U
#define | assert_param(expr) ((void)0U)
Include module's header file.

Detailed Description

HAL configuration template file. This file should be copied to the application folder and renamed to stm32f1xx_hal_conf.h.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_conf.h.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Include module's header file.

Definition at line 369 of file stm32f1xx_hal_conf.h.

Referenced by FLASH_MassErase(), FLASH_OB_DisableWRP(), FLASH_OB_EnableWRP(), FLASH_OB_ProgramData(), FLASH_OB_RDP_LevelConfig(), FLASH_OB_UserConfig(), HAL_ADC_AnalogWDGConfig(), HAL_ADC_ConfigChannel(), HAL_ADC_DeInit(), HAL_ADC_GetValue(), HAL_ADC_Init(), HAL_ADC_IRQHandler(), HAL_ADC_PollForConversion(), HAL_ADC_PollForEvent(), HAL_ADC_Start(), HAL_ADC_Start_DMA(), HAL_ADC_Start_IT(), HAL_ADC_Stop(), HAL_ADC_Stop_DMA(), HAL_ADC_Stop_IT(), HAL_ADCEx_Calibration_Start(), HAL_ADCEx_InjectedConfigChannel(), HAL_ADCEx_InjectedGetValue(), HAL_ADCEx_InjectedPollForConversion(), HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT(), HAL_ADCEx_InjectedStop(), HAL_ADCEx_InjectedStop_IT(), HAL_ADCEx_MultiModeConfigChannel(), HAL_ADCEx_MultiModeGetValue(), HAL_ADCEx_MultiModeStart_DMA(), HAL_ADCEx_MultiModeStop_DMA(), HAL_CAN_ConfigFilter(), HAL_CAN_DeInit(), HAL_CAN_Init(), HAL_CAN_Receive(), HAL_CAN_Receive_IT(), HAL_CAN_Transmit(), HAL_CAN_Transmit_IT(), HAL_CRC_DeInit(), HAL_CRC_Init(), HAL_DMA_DeInit(), HAL_DMA_Init(), HAL_DMA_Start(), HAL_DMA_Start_IT(), HAL_FLASH_Program(), HAL_FLASH_Program_IT(), HAL_FLASHEx_Erase(), HAL_FLASHEx_Erase_IT(), HAL_FLASHEx_OBProgram(), HAL_GPIO_DeInit(), HAL_GPIO_Init(), HAL_GPIO_LockPin(), HAL_GPIO_ReadPin(), HAL_GPIO_TogglePin(), HAL_GPIO_WritePin(), HAL_GPIOEx_ConfigEventout(), HAL_HalfDuplex_Init(), HAL_I2C_DeInit(), HAL_I2C_Init(), HAL_I2C_Master_Sequential_Receive_IT(), HAL_I2C_Master_Sequential_Transmit_IT(), HAL_I2C_Mem_Read(), HAL_I2C_Mem_Read_DMA(), HAL_I2C_Mem_Read_IT(), HAL_I2C_Mem_Write(), HAL_I2C_Mem_Write_DMA(), HAL_I2C_Mem_Write_IT(), HAL_I2C_Slave_Sequential_Receive_IT(), HAL_I2C_Slave_Sequential_Transmit_IT(), HAL_IRDA_DeInit(), HAL_IRDA_Init(), HAL_IWDG_Init(), HAL_LIN_Init(), HAL_LIN_SendBreak(), HAL_MultiProcessor_EnterMuteMode(), HAL_MultiProcessor_ExitMuteMode(), HAL_MultiProcessor_Init(), HAL_NVIC_ClearPendingIRQ(), HAL_NVIC_DisableIRQ(), HAL_NVIC_EnableIRQ(), HAL_NVIC_GetActive(), HAL_NVIC_GetPendingIRQ(), HAL_NVIC_GetPriority(), HAL_NVIC_SetPendingIRQ(), HAL_NVIC_SetPriority(), HAL_NVIC_SetPriorityGrouping(), HAL_PCD_Init(), HAL_PWR_ConfigPVD(), HAL_PWR_DisableWakeUpPin(), HAL_PWR_EnableWakeUpPin(), HAL_PWR_EnterSLEEPMode(), HAL_PWR_EnterSTOPMode(), HAL_RCC_ClockConfig(), HAL_RCC_GetClockConfig(), HAL_RCC_GetOscConfig(), HAL_RCC_MCOConfig(), HAL_RCC_OscConfig(), HAL_RCCEx_GetPeriphCLKFreq(), HAL_RCCEx_PeriphCLKConfig(), HAL_RTC_DeactivateAlarm(), HAL_RTC_DeInit(), HAL_RTC_GetAlarm(), HAL_RTC_GetDate(), HAL_RTC_GetTime(), HAL_RTC_Init(), HAL_RTC_SetAlarm(), HAL_RTC_SetAlarm_IT(), HAL_RTC_SetDate(), HAL_RTC_SetTime(), HAL_RTCEx_BKUPRead(), HAL_RTCEx_BKUPWrite(), HAL_RTCEx_DeactivateTamper(), HAL_RTCEx_SetSmoothCalib(), HAL_RTCEx_SetTamper(), HAL_RTCEx_SetTamper_IT(), HAL_SMARTCARD_DeInit(), HAL_SMARTCARD_Init(), HAL_SPI_DeInit(), HAL_SPI_Init(), HAL_SPI_Transmit(), HAL_SPI_Transmit_DMA(), HAL_SPI_Transmit_IT(), HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_DMA(), HAL_SPI_TransmitReceive_IT(), HAL_SYSTICK_CLKSourceConfig(), HAL_TIM_Base_DeInit(), HAL_TIM_Base_Init(), HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(), HAL_TIM_Base_Stop(), HAL_TIM_Base_Stop_DMA(), HAL_TIM_Base_Stop_IT(), HAL_TIM_ConfigClockSource(), HAL_TIM_ConfigOCrefClear(), HAL_TIM_ConfigTI1Input(), HAL_TIM_DMABurst_ReadStart(), HAL_TIM_DMABurst_ReadStop(), HAL_TIM_DMABurst_WriteStart(), HAL_TIM_DMABurst_WriteStop(), HAL_TIM_Encoder_DeInit(), HAL_TIM_Encoder_Init(), HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(), HAL_TIM_Encoder_Stop(), HAL_TIM_Encoder_Stop_DMA(), HAL_TIM_Encoder_Stop_IT(), HAL_TIM_GenerateEvent(), HAL_TIM_IC_ConfigChannel(), HAL_TIM_IC_DeInit(), HAL_TIM_IC_Init(), HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(), HAL_TIM_IC_Stop(), HAL_TIM_IC_Stop_DMA(), HAL_TIM_IC_Stop_IT(), HAL_TIM_OC_ConfigChannel(), HAL_TIM_OC_DeInit(), HAL_TIM_OC_Init(), HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(), HAL_TIM_OC_Stop(), HAL_TIM_OC_Stop_DMA(), HAL_TIM_OC_Stop_IT(), HAL_TIM_OnePulse_ConfigChannel(), HAL_TIM_OnePulse_DeInit(), HAL_TIM_OnePulse_Init(), HAL_TIM_PWM_ConfigChannel(), HAL_TIM_PWM_DeInit(), HAL_TIM_PWM_Init(), HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(), HAL_TIM_PWM_Stop(), HAL_TIM_PWM_Stop_DMA(), HAL_TIM_PWM_Stop_IT(), HAL_TIM_ReadCapturedValue(), HAL_TIM_SlaveConfigSynchronization(), HAL_TIM_SlaveConfigSynchronization_IT(), HAL_TIMEx_ConfigBreakDeadTime(), HAL_TIMEx_ConfigCommutationEvent(), HAL_TIMEx_ConfigCommutationEvent_DMA(), HAL_TIMEx_ConfigCommutationEvent_IT(), HAL_TIMEx_HallSensor_DeInit(), HAL_TIMEx_HallSensor_Init(), HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(), HAL_TIMEx_HallSensor_Stop(), HAL_TIMEx_HallSensor_Stop_DMA(), HAL_TIMEx_HallSensor_Stop_IT(), HAL_TIMEx_MasterConfigSynchronization(), HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT(), HAL_TIMEx_OCN_Stop(), HAL_TIMEx_OCN_Stop_DMA(), HAL_TIMEx_OCN_Stop_IT(), HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT(), HAL_TIMEx_OnePulseN_Stop(), HAL_TIMEx_OnePulseN_Stop_IT(), HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT(), HAL_TIMEx_PWMN_Stop(), HAL_TIMEx_PWMN_Stop_DMA(), HAL_TIMEx_PWMN_Stop_IT(), HAL_UART_DeInit(), HAL_UART_Init(), HAL_USART_DeInit(), HAL_USART_Init(), HAL_WWDG_Init(), IRDA_SetConfig(), SMARTCARD_SetConfig(), TIM_CCxChannelCmd(), TIM_OC1_SetConfig(), TIM_OC2_SetConfig(), TIM_OC3_SetConfig(), TIM_OC4_SetConfig(), TIM_SlaveTimer_SetConfig(), UART_SetConfig(), and USART_SetConfig().

#define DP83848_PHY_ADDRESS 0x01U

Definition at line 174 of file stm32f1xx_hal_conf.h.

#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */

Definition at line 166 of file stm32f1xx_hal_conf.h.

#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */

Definition at line 168 of file stm32f1xx_hal_conf.h.

#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */

Definition at line 167 of file stm32f1xx_hal_conf.h.

#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */

Definition at line 169 of file stm32f1xx_hal_conf.h.

#define HAL_ADC_MODULE_ENABLED

Definition at line 56 of file stm32f1xx_hal_conf.h.

#define HAL_CAN_MODULE_ENABLED

Definition at line 57 of file stm32f1xx_hal_conf.h.

#define HAL_CEC_MODULE_ENABLED

Definition at line 58 of file stm32f1xx_hal_conf.h.

#define HAL_CORTEX_MODULE_ENABLED

Definition at line 59 of file stm32f1xx_hal_conf.h.

#define HAL_CRC_MODULE_ENABLED

Definition at line 60 of file stm32f1xx_hal_conf.h.

#define HAL_DAC_MODULE_ENABLED

Definition at line 61 of file stm32f1xx_hal_conf.h.

#define HAL_DMA_MODULE_ENABLED

Definition at line 62 of file stm32f1xx_hal_conf.h.

#define HAL_ETH_MODULE_ENABLED

Definition at line 63 of file stm32f1xx_hal_conf.h.

#define HAL_FLASH_MODULE_ENABLED

Definition at line 64 of file stm32f1xx_hal_conf.h.

#define HAL_GPIO_MODULE_ENABLED

Definition at line 65 of file stm32f1xx_hal_conf.h.

#define HAL_HCD_MODULE_ENABLED

Definition at line 66 of file stm32f1xx_hal_conf.h.

#define HAL_I2C_MODULE_ENABLED

Definition at line 67 of file stm32f1xx_hal_conf.h.

#define HAL_I2S_MODULE_ENABLED

Definition at line 68 of file stm32f1xx_hal_conf.h.

#define HAL_IRDA_MODULE_ENABLED

Definition at line 69 of file stm32f1xx_hal_conf.h.

#define HAL_IWDG_MODULE_ENABLED

Definition at line 70 of file stm32f1xx_hal_conf.h.

#define HAL_MODULE_ENABLED

This is the list of modules to be used in the HAL driver.

Definition at line 55 of file stm32f1xx_hal_conf.h.

#define HAL_NAND_MODULE_ENABLED

Definition at line 71 of file stm32f1xx_hal_conf.h.

#define HAL_NOR_MODULE_ENABLED

Definition at line 72 of file stm32f1xx_hal_conf.h.

#define HAL_PCCARD_MODULE_ENABLED

Definition at line 73 of file stm32f1xx_hal_conf.h.

#define HAL_PCD_MODULE_ENABLED

Definition at line 74 of file stm32f1xx_hal_conf.h.

#define HAL_PWR_MODULE_ENABLED

Definition at line 75 of file stm32f1xx_hal_conf.h.

#define HAL_RCC_MODULE_ENABLED

Definition at line 76 of file stm32f1xx_hal_conf.h.

#define HAL_RTC_MODULE_ENABLED

Definition at line 77 of file stm32f1xx_hal_conf.h.

#define HAL_SD_MODULE_ENABLED

Definition at line 78 of file stm32f1xx_hal_conf.h.

#define HAL_SMARTCARD_MODULE_ENABLED

Definition at line 79 of file stm32f1xx_hal_conf.h.

#define HAL_SPI_MODULE_ENABLED

Definition at line 80 of file stm32f1xx_hal_conf.h.

#define HAL_SRAM_MODULE_ENABLED

Definition at line 81 of file stm32f1xx_hal_conf.h.

#define HAL_TIM_MODULE_ENABLED

Definition at line 82 of file stm32f1xx_hal_conf.h.

#define HAL_UART_MODULE_ENABLED

Definition at line 83 of file stm32f1xx_hal_conf.h.

#define HAL_USART_MODULE_ENABLED

Definition at line 84 of file stm32f1xx_hal_conf.h.

#define HAL_WWDG_MODULE_ENABLED

Definition at line 85 of file stm32f1xx_hal_conf.h.

#define HSE_STARTUP_TIMEOUT 100U

Time out for HSE start up, in ms

Definition at line 102 of file stm32f1xx_hal_conf.h.

#define HSE_VALUE 8000000U

Adjust the value of External High Speed oscillator (HSE) used in your application.

This value is used by the RCC HAL module to compute the system frequency (when HSE is used as system clock source, directly or through the PLL). Value of the External oscillator in Hz

Definition at line 97 of file stm32f1xx_hal_conf.h.

Referenced by HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), RCC_GetSystemClockFreq(), and RCC_PLL_GetFreqDomain_SYS().

#define HSI_VALUE 8000000U

Internal High Speed oscillator (HSI) value.

This value is used by the RCC HAL module to compute the system frequency (when HSI is used as system clock source, directly or through the PLL). Value of the Internal oscillator in Hz

Definition at line 111 of file stm32f1xx_hal_conf.h.

Referenced by HAL_RCC_DeInit(), HAL_RCC_GetSysClockFreq(), HAL_RCCEx_GetPeriphCLKFreq(), LL_PLL_ConfigSystemClock_HSI(), RCC_GetSystemClockFreq(), and RCC_PLL_GetFreqDomain_SYS().

#define LSE_STARTUP_TIMEOUT 5000U

Time out for LSE start up, in ms

Definition at line 131 of file stm32f1xx_hal_conf.h.

#define LSE_VALUE 32768U

External Low Speed oscillator (LSE) value.

< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. This value is used by the UART, RTC HAL module to compute the system frequency Value of the External Low Speed oscillator in Hz

Definition at line 127 of file stm32f1xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define LSI_VALUE 40000U

Internal Low Speed oscillator (LSI) value.

LSI Typical Value in Hz

Definition at line 118 of file stm32f1xx_hal_conf.h.

Referenced by HAL_RCCEx_GetPeriphCLKFreq().

#define MAC_ADDR0 2U

Uncomment the line below to expanse the "assert_param" macro in the HAL drivers code.

Definition at line 158 of file stm32f1xx_hal_conf.h.

#define MAC_ADDR1 0U

Definition at line 159 of file stm32f1xx_hal_conf.h.

#define MAC_ADDR2 0U

Definition at line 160 of file stm32f1xx_hal_conf.h.

#define MAC_ADDR3 0U

Definition at line 161 of file stm32f1xx_hal_conf.h.

#define MAC_ADDR4 0U

Definition at line 162 of file stm32f1xx_hal_conf.h.

#define MAC_ADDR5 0U

Definition at line 163 of file stm32f1xx_hal_conf.h.

#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020)

Auto-Negotiation process completed

Definition at line 199 of file stm32f1xx_hal_conf.h.

#define PHY_AUTONEGOTIATION ((uint16_t)0x1000)

Enable auto-negotiation function

Definition at line 194 of file stm32f1xx_hal_conf.h.

#define PHY_BCR ((uint16_t)0x0000)

Transceiver Basic Control Register

Definition at line 185 of file stm32f1xx_hal_conf.h.

#define PHY_BSR ((uint16_t)0x0001)

Transceiver Basic Status Register

Definition at line 186 of file stm32f1xx_hal_conf.h.

#define PHY_CONFIG_DELAY 0x00000FFFU

Definition at line 178 of file stm32f1xx_hal_conf.h.

#define PHY_DUPLEX_STATUS ((uint16_t)0x0004)

PHY Duplex mask

Definition at line 211 of file stm32f1xx_hal_conf.h.

#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100)

Set the full-duplex mode at 100 Mb/s

Definition at line 190 of file stm32f1xx_hal_conf.h.

#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100)

Set the full-duplex mode at 10 Mb/s

Definition at line 192 of file stm32f1xx_hal_conf.h.

#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000)

Set the half-duplex mode at 100 Mb/s

Definition at line 191 of file stm32f1xx_hal_conf.h.

#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000)

Set the half-duplex mode at 10 Mb/s

Definition at line 193 of file stm32f1xx_hal_conf.h.

#define PHY_ISOLATE ((uint16_t)0x0400)

Isolate PHY from MII

Definition at line 197 of file stm32f1xx_hal_conf.h.

#define PHY_JABBER_DETECTION ((uint16_t)0x0002)

Jabber condition detected

Definition at line 201 of file stm32f1xx_hal_conf.h.

#define PHY_LINK_INTERRUPT ((uint16_t)0x2000)

PHY link status interrupt mask

Definition at line 217 of file stm32f1xx_hal_conf.h.

#define PHY_LINK_STATUS ((uint16_t)0x0001)

PHY Link mask

Definition at line 209 of file stm32f1xx_hal_conf.h.

#define PHY_LINKED_STATUS ((uint16_t)0x0004)

Valid link established

Definition at line 200 of file stm32f1xx_hal_conf.h.

#define PHY_LOOPBACK ((uint16_t)0x4000)

Select loop-back mode

Definition at line 189 of file stm32f1xx_hal_conf.h.

#define PHY_MICR ((uint16_t)0x0011)

MII Interrupt Control Register

Definition at line 206 of file stm32f1xx_hal_conf.h.

#define PHY_MICR_INT_EN ((uint16_t)0x0002)

PHY Enable interrupts

Definition at line 213 of file stm32f1xx_hal_conf.h.

#define PHY_MICR_INT_OE ((uint16_t)0x0001)

PHY Enable output interrupt events

Definition at line 214 of file stm32f1xx_hal_conf.h.

#define PHY_MISR ((uint16_t)0x0012)

MII Interrupt Status and Misc. Control Register

Definition at line 207 of file stm32f1xx_hal_conf.h.

#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020)

Enable Interrupt on change of link status

Definition at line 216 of file stm32f1xx_hal_conf.h.

#define PHY_POWERDOWN ((uint16_t)0x0800)

Select the power down mode

Definition at line 196 of file stm32f1xx_hal_conf.h.

#define PHY_READ_TO 0x0000FFFFU

Definition at line 180 of file stm32f1xx_hal_conf.h.

#define PHY_RESET ((uint16_t)0x8000)

PHY Reset

Definition at line 188 of file stm32f1xx_hal_conf.h.

#define PHY_RESET_DELAY 0x000000FFU

Definition at line 176 of file stm32f1xx_hal_conf.h.

#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200)

Restart auto-negotiation function

Definition at line 195 of file stm32f1xx_hal_conf.h.

#define PHY_SPEED_STATUS ((uint16_t)0x0002)

PHY Speed mask

Definition at line 210 of file stm32f1xx_hal_conf.h.

#define PHY_SR ((uint16_t)0x0010)

PHY status register Offset

Definition at line 205 of file stm32f1xx_hal_conf.h.

#define PHY_WRITE_TO 0x0000FFFFU

Definition at line 181 of file stm32f1xx_hal_conf.h.

#define PREFETCH_ENABLE 1U

Definition at line 144 of file stm32f1xx_hal_conf.h.

#define TICK_INT_PRIORITY 0x0FU

tick interrupt priority

Definition at line 142 of file stm32f1xx_hal_conf.h.

Referenced by HAL_Init(), and HAL_RCC_ClockConfig().

#define USE_RTOS 0U

Definition at line 143 of file stm32f1xx_hal_conf.h.

#define USE_SPI_CRC 1U

Definition at line 226 of file stm32f1xx_hal_conf.h.

#define VDD_VALUE 3300U

This is the HAL system configuration section.

Value of VDD in mv

Definition at line 141 of file stm32f1xx_hal_conf.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dac.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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stm32f1xx_hal_dac.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                      ##### DAC Peripheral features #####
  ==============================================================================
    [..]
      *** DAC Channels ***
      ====================
    [..]
    The device integrates two 12-bit Digital Analog Converters that can
    be used independently or simultaneously (dual mode):
      (#) DAC channel1 with DAC_OUT1 (PA4) as output
      (#) DAC channel2 with DAC_OUT2 (PA5) as output

      *** DAC Triggers ***
      ====================
    [..]
    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
    [..]
    Digital to Analog conversion can be triggered by:
      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
          The used pin (GPIOx_PIN_9) must be configured in input mode.

      (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7
          For STM32F10x connectivity line devices and STM32F100x devices: TIM3
          For STM32F10x high-density and XL-density devices: TIM8
          For STM32F100x high-density value line devices: TIM15 as
          replacement of TIM5.
          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)

      (#) Software using DAC_TRIGGER_SOFTWARE

      *** DAC Buffer mode feature ***
      ===============================
      [..]
      Each DAC channel integrates an output buffer that can be used to
      reduce the output impedance, and to drive external loads directly
      without having to add an external operational amplifier.
      To enable, the output buffer use
      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
      [..]
      (@) Refer to the device datasheet for more details about output
          impedance value with and without output buffer.

      *** DAC connect feature ***
      ===============================
      [..]
      Each DAC channel can be connected internally.
      To connect, use
      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;

      *** GPIO configurations guidelines ***
      =====================
      [..]
      When a DAC channel is used (ex channel1 on PA4) and the other is not
      (ex channel1 on PA5 is configured in Analog and disabled).
      Channel1 may disturb channel2 as coupling effect.
      Note that there is no coupling on channel2 as soon as channel2 is turned on.
      Coupling on adjacent channel could be avoided as follows:
      when unused PA5 is configured as INPUT PULL-UP or DOWN.
      PA5 is configured in ANALOG just before it is turned on.

       *** DAC wave generation feature ***
       ===================================
       [..]
       Both DAC channels can be used to generate
         (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
         (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()

       *** DAC data format ***
       =======================
       [..]
       The DAC data format can be:
         (#) 8-bit right alignment using DAC_ALIGN_8B_R
         (#) 12-bit left alignment using DAC_ALIGN_12B_L
         (#) 12-bit right alignment using DAC_ALIGN_12B_R

       *** DAC data value to voltage correspondance ***
       ================================================
       [..]
       The analog output voltage on each DAC channel pin is determined
       by the following equation:
       [..]
       DAC_OUTx = VREF+ * DOR / 4095
       (+) with  DOR is the Data Output Register
       [..]
          VEF+ is the input voltage reference (refer to the device datasheet)
       [..]
        e.g. To set DAC_OUT1 to 0.7V, use
       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V

       *** DMA requests  ***
       =====================
       [..]
       A DMA1 request can be generated when an external trigger (but not
       a software trigger) occurs if DMA1 requests are enabled using
       HAL_DAC_Start_DMA()
       [..]
       DMA requests are mapped as following:
         (#) DAC channel1 :
             For STM32F100x low-density, medium-density, high-density with DAC
             DMA remap:
                            mapped on DMA1 channel3 which must be
             already configured
             For STM32F100x high-density without DAC DMA remap and other
             STM32F1 devices:
                            mapped on DMA2 channel3 which must be
             already configured
         (#) DAC channel2 :
             For STM32F100x low-density, medium-density, high-density with DAC
             DMA remap:
                            mapped on DMA1 channel4 which must be
             already configured
             For STM32F100x high-density without DAC DMA remap and other
             STM32F1 devices:
                            mapped on DMA2 channel4 which must be
             already configured

                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) DAC APB clock must be enabled to get write access to DAC
          registers using HAL_DAC_Init()
      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start()
       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
       (+) Stop the DAC peripheral using HAL_DAC_Stop()

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
           of data to be transferred at each end of conversion
       (+) At the middle of data transfer HAL_DACEx_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2
       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() or HAL_DACEx_ErrorCallbackCh2() function is executed and user can
           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 or HAL_DACEx_ErrorCallbackCh2
       (+) For STM32F100x devices with specific feature: DMA underrun.
           In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
           HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2()
           function is executed and user can add his own code by customization of function pointer
           HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DACEx_DMAUnderrunCallbackCh2
           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()

     *** DAC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DAC HAL driver.

      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (For STM32F100x devices with specific feature: DMA underrun)
      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status (For STM32F100x devices with specific feature: DMA underrun)

     [..]
      (@) You can refer to the DAC HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_dac.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dac.h File Reference

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stm32f1xx_hal_dac.h File Reference

Header file of DAC HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of DAC HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_dac.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dac_ex.c File Reference

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stm32f1xx_hal_dac_ex.c File Reference

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                      ##### How to use this driver #####
  ==============================================================================
    [..]
      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_dac_ex.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dac_ex.h File Reference

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stm32f1xx_hal_dac_ex.h File Reference

Header file of DAC HAL Extension module. More...

Go to the source code of this file.

Detailed Description

Header file of DAC HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_dac_ex.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_eth.c File Reference

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stm32f1xx_hal_eth.c File Reference

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      (#)Declare a ETH_HandleTypeDef handle structure, for example:
         ETH_HandleTypeDef  heth;

      (#)Fill parameters of Init structure in heth handle

      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)

      (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
          (##) Enable the Ethernet interface clock using
               (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
               (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
               (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();

          (##) Initialize the related GPIO clocks
          (##) Configure Ethernet pin-out
          (##) Configure Ethernet NVIC interrupt (IT mode)

      (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
          (##) HAL_ETH_DMATxDescListInit(); for Transmission process
          (##) HAL_ETH_DMARxDescListInit(); for Reception process

      (#)Enable MAC and DMA transmission and reception:
          (##) HAL_ETH_Start();

      (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
         the frame to MAC TX FIFO:
         (##) HAL_ETH_TransmitFrame();

      (#)Poll for a received frame in ETH RX DMA Descriptors and get received
         frame parameters
         (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)

      (#) Get a received frame when an ETH RX interrupt occurs:
         (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)

      (#) Communicate with external PHY device:
         (##) Read a specific register from the PHY
              HAL_ETH_ReadPHYRegister();
         (##) Write data to a specific RHY register:
              HAL_ETH_WritePHYRegister();

      (#) Configure the Ethernet MAC after ETH peripheral initialization
          HAL_ETH_ConfigMAC(); all MAC parameters should be filled.

      (#) Configure the Ethernet DMA after ETH peripheral initialization
          HAL_ETH_ConfigDMA(); all DMA parameters should be filled.

      -@- The PTP protocol and the DMA descriptors ring mode are not supported
          in this driver
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_eth.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_eth.h File Reference

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stm32f1xx_hal_eth.h File Reference

Header file of ETH HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Detailed Description

Header file of ETH HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_eth.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_hcd.c File Reference

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stm32f1xx_hal_hcd.c File Reference

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
  [..]
    (#)Declare a HCD_HandleTypeDef handle structure, for example:
       HCD_HandleTypeDef  hhcd;

    (#)Fill parameters of Init structure in HCD handle

    (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)

    (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
        (##) Enable the HCD/USB Low Level interface clock using the following macro
             (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE()

        (##) Initialize the related GPIO clocks
        (##) Configure HCD pin-out
        (##) Configure HCD NVIC interrupt

    (#)Associate the Upper USB Host stack to the HAL HCD Driver:
        (##) hhcd.pData = phost;

    (#)Enable HCD transmission and reception:
        (##) HAL_HCD_Start();
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_hcd.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_hcd.h File Reference

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stm32f1xx_hal_hcd.h File Reference

Header file of HCD HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of HCD HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_hcd.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_i2s.c File Reference

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stm32f1xx_hal_i2s.c File Reference

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
 ===============================================================================
                  ##### How to use this driver #####
 ===============================================================================
 [..]
    The I2S HAL driver can be used as follow:

    (#) Declare a I2S_HandleTypeDef handle structure.
    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
        (##) Enable the SPIx interface clock.
        (##) I2S pins configuration:
            (+++) Enable the clock for the I2S GPIOs.
            (+++) Configure these I2S pins as alternate function.
        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
             and HAL_I2S_Receive_IT() APIs).
            (+++) Configure the I2Sx interrupt priority.
            (+++) Enable the NVIC I2S IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
             and HAL_I2S_Receive_DMA() APIs:
            (+++) Declare a DMA handle structure for the Tx/Rx Channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx Channel.
            (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                  DMA Tx/Rx Channel.

   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
       using HAL_I2S_Init() function.

   -@- The specific I2S interrupts (Transmission complete interrupt,
       RXNE interrupt and Error Interrupts) will be managed using the macros
       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
   -@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock).
       For connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO (2 x PLL3CLK) clock
       in order to achieve the maximum accuracy.
   -@- Make sure that either:
       (+@) External clock source is configured after setting correctly
            the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file.

   (#) Three operation modes are available within this driver :

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
         add his own code by customization of function pointer HAL_I2S_ErrorCallback
     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()

   *** I2S HAL driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in I2S HAL driver.

      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not

    [..]
      (@) You can refer to the I2S HAL driver header file for more useful macros

     *** I2C Workarounds linked to Silicon Limitation ***
     ====================================================
     [..]
       (@) Only the 16-bit mode with no data extension can be used when the I2S
           is in Master and used the PCM long synchronization mode.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_i2s.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_i2s.h File Reference

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stm32f1xx_hal_i2s.h File Reference

Header file of I2S HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of I2S HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_i2s.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_nand.c File Reference

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stm32f1xx_hal_nand.c File Reference

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                         ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NAND flash memories. It uses the FSMC layer functions to interface
      with NAND devices. This driver is used as follows:

      (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
          with control and timing parameters for both common and attribute spaces.

      (+) Read NAND flash memory maker and device IDs using the function
          HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
          structure declared by the function caller.

      (+) Access NAND flash memory by read/write operations using the functions
          HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
          HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
          HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
          HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
          to read/write page(s)/spare area(s). These functions use specific device
          information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
          structure. The read/write address information is contained by the Nand_Address_Typedef
          structure passed as parameter.

      (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().

      (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
          The erase block address information is contained in the Nand_Address_Typedef
          structure passed as parameter.

      (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().

      (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
          HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
          feature or the function HAL_NAND_GetECC() to get the ECC correction code.

      (+) You can monitor the NAND device HAL state by calling the function
          HAL_NAND_GetState()

    [..]
      (@) This driver is a set of generic APIs which handle standard NAND flash operations.
          If a NAND flash device contains different operations and/or implementations,
          it should be implemented separately.
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_nand.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_nand.h File Reference

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stm32f1xx_hal_nand.h File Reference

Header file of NAND HAL module. More...

#include "stm32f1xx_ll_fsmc.h"

Go to the source code of this file.

Detailed Description

Header file of NAND HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_nand.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_nor.c File Reference

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stm32f1xx_hal_nor.c File Reference

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      This driver is a generic layered driver which contains a set of APIs used to
      control NOR flash memories. It uses the FSMC layer functions to interface
      with NOR devices. This driver is used as follows:

      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
          with control and timing parameters for both normal and extended mode.

      (+) Read NOR flash memory manufacturer code and device IDs using the function
          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
          structure declared by the function caller.

      (+) Access NOR flash memory by read/write data unit operations using the functions
          HAL_NOR_Read(), HAL_NOR_Program().

      (+) Perform NOR flash erase block/chip operations using the functions
          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().

      (+) Read the NOR flash CFI (common flash interface) IDs using the function
          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
          structure declared by the function caller.

      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation

      (+) You can monitor the NOR device HAL state by calling the function
          HAL_NOR_GetState()
    [..]
     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
         If a NOR flash device contains different operations and/or implementations,
         it should be implemented separately.

     *** NOR HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in NOR HAL driver.

      (+) NOR_WRITE : NOR memory write data to specified address
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_nor.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_nor.h File Reference

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stm32f1xx_hal_nor.h File Reference

Header file of NOR HAL module. More...

#include "stm32f1xx_ll_fsmc.h"

Go to the source code of this file.

Detailed Description

Header file of NOR HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_nor.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pccard.c File Reference

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stm32f1xx_hal_pccard.c File Reference

PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
 ===============================================================================
                        ##### How to use this driver #####
 ===============================================================================
   [..]
     This driver is a generic layered driver which contains a set of APIs used to
     control PCCARD/compact flash memories. It uses the FSMC/FSMC layer functions
     to interface with PCCARD devices. This driver is used for:

    (+) PCCARD/compact flash memory configuration sequence using the function
        HAL_PCCARD_Init() with control and timing parameters for both common and
        attribute spaces.

    (+) Read PCCARD/compact flash memory maker and device IDs using the function
        HAL_PCCARD_Read_ID(). The read information is stored in the CompactFlash_ID
        structure declared by the function caller.

    (+) Access PCCARD/compact flash memory by read/write operations using the functions
        HAL_PCCARD_Read_Sector()/HAL_PCCARD_Write_Sector(), to read/write sector.

    (+) Perform PCCARD/compact flash Reset chip operation using the function HAL_PCCARD_Reset().

    (+) Perform PCCARD/compact flash erase sector operation using the function
        HAL_PCCARD_Erase_Sector().

    (+) Read the PCCARD/compact flash status operation using the function HAL_PCCARD_ReadStatus().

    (+) You can monitor the PCCARD/compact flash  device HAL state by calling the function
        HAL_PCCARD_GetState()

   [..]
     (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
         operations. If a PCCARD/compact flash device contains different operations
         and/or implementations, it should be implemented separately.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_pccard.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pccard.h File Reference

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stm32f1xx_hal_pccard.h File Reference

Header file of PCCARD HAL module. More...

#include "stm32f1xx_ll_fsmc.h"

Go to the source code of this file.

Detailed Description

Header file of PCCARD HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_pccard.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_sd.c File Reference

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stm32f1xx_hal_sd.c File Reference

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + SD card Control functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + SD card Control functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver implements a high level communication layer for read and write from/to
    this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
    the user in HAL_SD_MspInit() function (MSP layer).
    Basically, the MSP layer configuration should be the same as we provide in the
    examples.
    You can easily tailor this configuration according to hardware resources.

  [..]
    This driver is a generic layered driver for SDIO memories which uses the HAL
    SDIO driver functions to interface with SD and uSD cards devices.
    It is used as follows:

    (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
        (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
        (##) SDIO pins configuration for SD card
            (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
                  and according to your pin assignment;
        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
             and HAL_SD_WriteBlocks_DMA() APIs).
            (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
            (+++) Configure the SDIO and DMA interrupt priorities using functions
                  HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
            (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
            (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
                  and __HAL_SD_DISABLE_IT() inside the communication process.
            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
                  and __HAL_SD_CLEAR_IT()
        (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
             and HAL_SD_WriteBlocks_IT() APIs).
            (+++) Configure the SDIO interrupt priorities using function
                  HAL_NVIC_SetPriority();
            (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()
            (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
                  and __HAL_SD_DISABLE_IT() inside the communication process.
            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
                  and __HAL_SD_CLEAR_IT()
    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization

  *** SD Card Initialization and configuration ***
  ================================================
  [..]
    To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
    SDIO IP(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
    This function provide the following operations:

    (#) Initialize the SDIO peripheral interface with defaullt configuration.
        The initialization process is done at 400KHz. You can change or adapt
        this frequency by adjusting the "ClockDiv" field.
        The SD Card frequency (SDIO_CK) is computed as follows:

           SDIO_CK = SDIOCLK / (ClockDiv + 2)

        In initialization mode and according to the SD Card standard,
        make sure that the SDIO_CK frequency doesn't exceed 400KHz.

        This phase of initialization is done through SDIO_Init() and
        SDIO_PowerState_ON() SDIO low level APIs.

    (#) Initialize the SD card. The API used is HAL_SD_InitCard().
        This phase allows the card initialization and identification
        and check the SD Card type (Standard Capacity or High Capacity)
        The initialization flow is compatible with SD standard.

        This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
        of plug-off plug-in.

    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
        frequency is set to 24MHz. You can change or adapt this frequency by adjusting
        the "ClockDiv" field.
        In transfer mode and according to the SD Card standard, make sure that the
        SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
        To be able to use a frequency higher than 24MHz, you should use the SDIO
        peripheral in bypass mode. Refer to the corresponding reference manual
        for more details.

    (#) Select the corresponding SD Card according to the address read with the step 2.

    (#) Configure the SD Card in wide bus mode: 4-bits data.

  *** SD Card Read operation ***
  ==============================
  [..]
    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
        This function allows the read of 512 bytes blocks.
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.

    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
        This function allows the read of 512 bytes blocks.
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.
        You could also check the DMA transfer process through the SD Rx interrupt event.

    (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
        This function allows the read of 512 bytes blocks.
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.
        You could also check the IT transfer process through the SD Rx interrupt event.

  *** SD Card Write operation ***
  ===============================
  [..]
    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
        This function allows the read of 512 bytes blocks.
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.

    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
        This function allows the read of 512 bytes blocks.
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.
        You could also check the DMA transfer process through the SD Tx interrupt event.

    (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
        This function allows the read of 512 bytes blocks.
        You can choose either one block read operation or multiple block read operation
        by adjusting the "NumberOfBlocks" parameter.
        After this, you have to ensure that the transfer is done correctly. The check is done
        through HAL_SD_GetCardState() function for SD card state.
        You could also check the IT transfer process through the SD Tx interrupt event.

  *** SD card status ***
  ======================
  [..]
    (+) The SD Status contains status bits that are related to the SD Memory
        Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().

  *** SD card information ***
  ===========================
  [..]
    (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
        It returns useful information about the SD card such as block size, card type,
        block number ...

  *** SD card CSD register ***
  ============================
  [..]
    (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
        Some of the CSD parameters are useful for card initialization and identification.

  *** SD card CID register ***
  ============================
  [..]
    (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
        Some of the CSD parameters are useful for card initialization and identification.

  *** SD HAL driver macros list ***
  ==================================
  [..]
    Below the list of most used macros in SD HAL driver.

    (+) __HAL_SD_ENABLE : Enable the SD device
    (+) __HAL_SD_DISABLE : Disable the SD device
    (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer
    (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer
    (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
    (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
    (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
    (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags

   [..]
    (@) You can refer to the SD HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_sd.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_sd.h File Reference

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stm32f1xx_hal_sd.h File Reference

Header file of SD HAL module. More...

Go to the source code of this file.

Detailed Description

Header file of SD HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_sd.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_sram.c File Reference

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stm32f1xx_hal_sram.c File Reference

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Detailed Description

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                          ##### How to use this driver #####
  ==============================================================================
  [..]
    This driver is a generic layered driver which contains a set of APIs used to
    control SRAM memories. It uses the FSMC layer functions to interface
    with SRAM devices.
    The following sequence should be followed to configure the FSMC to interface
    with SRAM/PSRAM memories:

   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
          SRAM_HandleTypeDef  hsram; and:

       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
            values of the structure member.

       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
            base register instance for NOR or SRAM device

       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
            base register instance for NOR or SRAM extended mode

   (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
       mode timings; for example:
          FSMC_NORSRAM_TimingTypeDef  Timing and FSMC_NORSRAM_TimingTypeDef  ExTiming;
      and fill its fields with the allowed values of the structure member.

   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
       performs the following sequence:

       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
       (##) Control register configuration using the FSMC NORSRAM interface function
            FSMC_NORSRAM_Init()
       (##) Timing register configuration using the FSMC NORSRAM interface function
            FSMC_NORSRAM_Timing_Init()
       (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
            FSMC_NORSRAM_Extended_Timing_Init()
       (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()

   (#) At this stage you can perform read/write accesses from/to the memory connected
       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
       following APIs:
       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer

   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation

   (#) You can continuously monitor the SRAM device HAL state by calling the function
       HAL_SRAM_GetState()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_sram.c.

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STM32F103xB HAL User Manual: stm32f1xx_hal_sram.h File Reference

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stm32f1xx_hal_sram.h File Reference

Header file of SRAM HAL module. More...

#include "stm32f1xx_ll_fsmc.h"

Go to the source code of this file.

Detailed Description

Header file of SRAM HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_sram.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_adc.c File Reference

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Defines | Functions
stm32f1xx_ll_adc.c File Reference

ADC LL module driver. More...

#include "stm32f1xx_ll_adc.h"
#include "stm32f1xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)
#define | IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__)
#define | IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__)
#define | IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)
#define | IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)
#define | IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)
#define | IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)
#define | IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)
#define | IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)
#define | IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)
#define | IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)

Functions

ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

ADC LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_adc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32f1xx_ll_adc.c.

Referenced by LL_ADC_CommonDeInit(), LL_ADC_CommonInit(), LL_ADC_DeInit(), LL_ADC_Init(), LL_ADC_INJ_Init(), and LL_ADC_REG_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_crc.c File Reference

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Defines | Functions
stm32f1xx_ll_crc.c File Reference

CRC LL module driver. More...

#include "stm32f1xx_ll_crc.h"
#include "stm32f1xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)

Functions

ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

CRC LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_crc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32f1xx_ll_crc.c.

Referenced by LL_CRC_DeInit().

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STM32F103xB HAL User Manual: stm32f1xx_ll_dac.c File Reference

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Defines
stm32f1xx_ll_dac.c File Reference

DAC LL module driver. More...

#include "stm32f1xx_ll_dac.h"
#include "stm32f1xx_ll_bus.h"

Go to the source code of this file.

Defines

#define assert_param(expr) ((void)0U)

Detailed Description

DAC LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_dac.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32f1xx_ll_dac.c.

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STM32F103xB HAL User Manual: stm32f1xx_ll_dac.h File Reference

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  • Inc
stm32f1xx_ll_dac.h File Reference

Header file of DAC LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Detailed Description

Header file of DAC LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_dac.h.

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STM32F103xB HAL User Manual: stm32f1xx_ll_dma.c File Reference

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  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_ll_dma.c File Reference

DMA LL module driver. More...

#include "stm32f1xx_ll_dma.h"
#include "stm32f1xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_DMA_DIRECTION(__VALUE__)
#define | IS_LL_DMA_MODE(__VALUE__)
#define | IS_LL_DMA_PERIPHINCMODE(__VALUE__)
#define | IS_LL_DMA_MEMORYINCMODE(__VALUE__)
#define | IS_LL_DMA_PERIPHDATASIZE(__VALUE__)
#define | IS_LL_DMA_MEMORYDATASIZE(__VALUE__)
#define | IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define | IS_LL_DMA_PRIORITY(__VALUE__)
#define | IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)

Functions

uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Detailed Description

DMA LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_dma.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32f1xx_ll_dma.c.

Referenced by LL_DMA_DeInit(), and LL_DMA_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_exti.c File Reference

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Defines | Functions
stm32f1xx_ll_exti.c File Reference

EXTI LL module driver. More...

#include "stm32f1xx_ll_exti.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define | IS_LL_EXTI_MODE(__VALUE__)
#define | IS_LL_EXTI_TRIGGER(__VALUE__)

Functions

uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

EXTI LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_exti.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 44 of file stm32f1xx_ll_exti.c.

Referenced by LL_EXTI_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_gpio.c File Reference

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Defines | Functions
stm32f1xx_ll_gpio.c File Reference

GPIO LL module driver. More...

#include "stm32f1xx_ll_gpio.h"
#include "stm32f1xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define | IS_LL_GPIO_MODE(__VALUE__)
#define | IS_LL_GPIO_SPEED(__VALUE__)
#define | IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)
#define | IS_LL_GPIO_PULL(__VALUE__)

Functions

ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

GPIO LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_gpio.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 45 of file stm32f1xx_ll_gpio.c.

Referenced by LL_GPIO_DeInit(), and LL_GPIO_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_i2c.c File Reference

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Defines | Functions
stm32f1xx_ll_i2c.c File Reference

I2C LL module driver. More...

#include "stm32f1xx_ll_i2c.h"
#include "stm32f1xx_ll_bus.h"
#include "stm32f1xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)
#define | IS_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
#define | IS_I2C_DUTY_CYCLE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define | IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)
#define | IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)

Functions

uint32_t | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
uint32_t | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

I2C LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_i2c.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32f1xx_ll_i2c.c.

Referenced by LL_I2C_DeInit(), and LL_I2C_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_i2s.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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stm32f1xx_ll_i2s.c File Reference
#include "stm32f1xx_ll_spi.h"
#include "stm32f1xx_ll_bus.h"
#include "stm32f1xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | I2S_I2SCFGR_CLEAR_MASK
#define | I2S_I2SPR_CLEAR_MASK 0x0002U
#define | IS_LL_I2S_DATAFORMAT(__VALUE__)
#define | IS_LL_I2S_CPOL(__VALUE__)
#define | IS_LL_I2S_STANDARD(__VALUE__)
#define | IS_LL_I2S_MODE(__VALUE__)
#define | IS_LL_I2S_MCLK_OUTPUT(__VALUE__)
#define | IS_LL_I2S_AUDIO_FREQ(__VALUE__)
#define | IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define | IS_LL_I2S_PRESCALER_PARITY(__VALUE__)

Functions

ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 47 of file stm32f1xx_ll_i2s.c.

Referenced by LL_I2S_ConfigPrescaler(), and LL_I2S_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_rcc.c File Reference

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  • STM32F1xx_HAL_Driver
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stm32f1xx_ll_rcc.c File Reference

RCC LL module driver. More...

#include "stm32f1xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#define | IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))

Functions

uint32_t | RCC_GetSystemClockFreq (void)
Return SYSTEM clock frequency.
uint32_t | RCC_GetHCLKClockFreq (uint32_t SYSCLK_Frequency)
Return HCLK clock frequency.
uint32_t | RCC_GetPCLK1ClockFreq (uint32_t HCLK_Frequency)
Return PCLK1 clock frequency.
uint32_t | RCC_GetPCLK2ClockFreq (uint32_t HCLK_Frequency)
Return PCLK2 clock frequency.
uint32_t | RCC_PLL_GetFreqDomain_SYS (void)
Return PLL clock frequency used for system domain.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.

Detailed Description

RCC LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_rcc.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 44 of file stm32f1xx_ll_rcc.c.

Referenced by LL_RCC_GetADCClockFreq(), and LL_RCC_GetUSBClockFreq().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_spi.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_ll_spi.c File Reference

SPI LL module driver. More...

#include "stm32f1xx_ll_spi.h"
#include "stm32f1xx_ll_bus.h"
#include "stm32f1xx_ll_rcc.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | SPI_CR1_CLEAR_MASK
#define | IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)
#define | IS_LL_SPI_MODE(__VALUE__)
#define | IS_LL_SPI_DATAWIDTH(__VALUE__)
#define | IS_LL_SPI_POLARITY(__VALUE__)
#define | IS_LL_SPI_PHASE(__VALUE__)
#define | IS_LL_SPI_NSS(__VALUE__)
#define | IS_LL_SPI_BAUDRATE(__VALUE__)
#define | IS_LL_SPI_BITORDER(__VALUE__)
#define | IS_LL_SPI_CRCCALCULATION(__VALUE__)
#define | IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)

Functions

ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Detailed Description

SPI LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_spi.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 47 of file stm32f1xx_ll_spi.c.

Referenced by LL_SPI_DeInit(), and LL_SPI_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_tim.c File Reference

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  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_ll_tim.c File Reference

TIM LL module driver. More...

#include "stm32f1xx_ll_tim.h"
#include "stm32f1xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_TIM_COUNTERMODE(__VALUE__)
#define | IS_LL_TIM_CLOCKDIVISION(__VALUE__)
#define | IS_LL_TIM_OCMODE(__VALUE__)
#define | IS_LL_TIM_OCSTATE(__VALUE__)
#define | IS_LL_TIM_OCPOLARITY(__VALUE__)
#define | IS_LL_TIM_OCIDLESTATE(__VALUE__)
#define | IS_LL_TIM_ACTIVEINPUT(__VALUE__)
#define | IS_LL_TIM_ICPSC(__VALUE__)
#define | IS_LL_TIM_IC_FILTER(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY(__VALUE__)
#define | IS_LL_TIM_ENCODERMODE(__VALUE__)
#define | IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__)
#define | IS_LL_TIM_OSSR_STATE(__VALUE__)
#define | IS_LL_TIM_OSSI_STATE(__VALUE__)
#define | IS_LL_TIM_LOCK_LEVEL(__VALUE__)
#define | IS_LL_TIM_BREAK_STATE(__VALUE__)
#define | IS_LL_TIM_BREAK_POLARITY(__VALUE__)
#define | IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__)

Functions

static ErrorStatus | OC1Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 1.
static ErrorStatus | OC2Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 2.
static ErrorStatus | OC3Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 3.
static ErrorStatus | OC4Config (TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
Configure the TIMx output channel 4.
static ErrorStatus | IC1Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 1.
static ErrorStatus | IC2Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 2.
static ErrorStatus | IC3Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 3.
static ErrorStatus | IC4Config (TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Configure the TIMx input channel 4.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Detailed Description

TIM LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_tim.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32f1xx_ll_tim.c.

Referenced by IC1Config(), IC2Config(), IC3Config(), IC4Config(), LL_TIM_BDTR_Init(), LL_TIM_DeInit(), LL_TIM_ENCODER_Init(), LL_TIM_HALLSENSOR_Init(), LL_TIM_Init(), OC1Config(), OC2Config(), OC3Config(), and OC4Config().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_usart.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_ll_usart.c File Reference

USART LL module driver. More...

#include "stm32f1xx_ll_usart.h"
#include "stm32f1xx_ll_rcc.h"
#include "stm32f1xx_ll_bus.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
#define | IS_LL_USART_DIRECTION(__VALUE__)
#define | IS_LL_USART_PARITY(__VALUE__)
#define | IS_LL_USART_DATAWIDTH(__VALUE__)
#define | IS_LL_USART_OVERSAMPLING(__VALUE__)
#define | IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__)
#define | IS_LL_USART_CLOCKPHASE(__VALUE__)
#define | IS_LL_USART_CLOCKPOLARITY(__VALUE__)
#define | IS_LL_USART_CLOCKOUTPUT(__VALUE__)
#define | IS_LL_USART_STOPBITS(__VALUE__)
#define | IS_LL_USART_HWCONTROL(__VALUE__)

Functions

ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Detailed Description

USART LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_usart.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 46 of file stm32f1xx_ll_usart.c.

Referenced by LL_USART_ClockInit(), LL_USART_DeInit(), and LL_USART_Init().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_utils.c File Reference

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Defines | Functions
stm32f1xx_ll_utils.c File Reference

UTILS LL module driver. More...

#include "stm32f1xx_ll_rcc.h"
#include "stm32f1xx_ll_utils.h"
#include "stm32f1xx_ll_system.h"

Go to the source code of this file.

Defines

#define | assert_param(expr) ((void)0U)
#define | UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY
#define | UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN
#define | UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX
#define | UTILS_LATENCY1_FREQ 24000000U
#define | UTILS_LATENCY2_FREQ 48000000U
#define | IS_LL_UTILS_SYSCLK_DIV(__VALUE__)
#define | IS_LL_UTILS_APB1_DIV(__VALUE__)
#define | IS_LL_UTILS_APB2_DIV(__VALUE__)
#define | IS_LL_UTILS_PLLMUL_VALUE(__VALUE__)
#define | IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
#define | IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
#define | IS_LL_UTILS_HSE_BYPASS(__STATE__)
#define | IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))

Functions

static uint32_t | UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
Function to check that PLL can be modified.
static ErrorStatus | UTILS_SetFlashLatency (uint32_t Frequency)
Update number of Flash wait states in line with new frequency and current voltage range.
static ErrorStatus | UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
Function to enable PLL and switch system clock to PLL.
static ErrorStatus | UTILS_PLL_IsBusy (void)
Function to check that PLL can be modified.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

UTILS LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_utils.c.

Define Documentation

#define assert_param ( expr ) ((void)0U)

Definition at line 44 of file stm32f1xx_ll_utils.c.

Referenced by LL_PLL_ConfigSystemClock_HSE(), LL_PLL_ConfigSystemClock_HSI(), UTILS_EnablePLLAndSwitchSystem(), and UTILS_GetPLLOutputFrequency().

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __ADC_MASK_SHIFT : stm32f1xx_ll_adc.h
  • __ADC_PTR_REG_OFFSET : stm32f1xx_ll_adc.h
  • __HAL_ADC_CLEAR_FLAG : stm32f1xx_hal_adc.h
  • __HAL_ADC_DISABLE : stm32f1xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32f1xx_hal_adc.h
  • __HAL_ADC_ENABLE : stm32f1xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32f1xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32f1xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32f1xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32f1xx_hal_adc.h
  • __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_CAN1_1 : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_CAN1_2 : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_CAN1_3 : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_I2C1_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_I2C1_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_PD01_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_PD01_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SPI1_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SPI1_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SWJ_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SWJ_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SWJ_NOJTAG : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SWJ_NONJTRST : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM1_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM1_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM1_PARTIAL : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM2_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM2_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM2_PARTIAL_1 : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM2_PARTIAL_2 : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM3_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM3_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM3_PARTIAL : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM4_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM4_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART1_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART1_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART2_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART2_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART3_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART3_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART3_PARTIAL : stm32f1xx_hal_gpio_ex.h
  • __HAL_CAN_CANCEL_TRANSMIT : stm32f1xx_hal_can.h
  • __HAL_CAN_CLEAR_FLAG : stm32f1xx_hal_can.h
  • __HAL_CAN_DBG_FREEZE : stm32f1xx_hal_can.h
  • __HAL_CAN_DISABLE_IT : stm32f1xx_hal_can.h
  • __HAL_CAN_ENABLE_IT : stm32f1xx_hal_can.h
  • __HAL_CAN_FIFO_RELEASE : stm32f1xx_hal_can.h
  • __HAL_CAN_GET_FLAG : stm32f1xx_hal_can.h
  • __HAL_CAN_GET_IT_SOURCE : stm32f1xx_hal_can.h
  • __HAL_CAN_MSG_PENDING : stm32f1xx_hal_can.h
  • __HAL_CAN_RESET_HANDLE_STATE : stm32f1xx_hal_can.h
  • __HAL_CAN_TRANSMIT_STATUS : stm32f1xx_hal_can.h
  • __HAL_CRC_DR_RESET : stm32f1xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32f1xx_hal_crc.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32f1xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32f1xx_hal_crc.h
  • __HAL_DBGMCU_FREEZE_CAN1 : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN1 : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32f1xx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_DISABLE : stm32f1xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32f1xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32f1xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32f1xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32f1xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_GET_IT_SOURCE : stm32f1xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32f1xx_hal_dma.h
  • __HAL_FLASH_CLEAR_FLAG : stm32f1xx_hal_flash_ex.h
  • __HAL_FLASH_DISABLE_IT : stm32f1xx_hal_flash_ex.h
  • __HAL_FLASH_ENABLE_IT : stm32f1xx_hal_flash_ex.h
  • __HAL_FLASH_GET_FLAG : stm32f1xx_hal_flash_ex.h
  • __HAL_FLASH_GET_LATENCY : stm32f1xx_hal_flash.h
  • __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE : stm32f1xx_hal_flash.h
  • __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE : stm32f1xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32f1xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32f1xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32f1xx_hal_flash.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32f1xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32f1xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32f1xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32f1xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32f1xx_hal_gpio.h
  • __HAL_I2C_CLEAR_ADDRFLAG : stm32f1xx_hal_i2c.h
  • __HAL_I2C_CLEAR_FLAG : stm32f1xx_hal_i2c.h
  • __HAL_I2C_CLEAR_STOPFLAG : stm32f1xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32f1xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32f1xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32f1xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32f1xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32f1xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32f1xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32f1xx_hal_i2c.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32f1xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32f1xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32f1xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32f1xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32f1xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32f1xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32f1xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32f1xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32f1xx_hal_iwdg.h
  • __HAL_PCD_CLEAR_FLAG : stm32f1xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32f1xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32f1xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32f1xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32f1xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32f1xx_hal_pwr.h
  • __HAL_RCC_ADC1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC2_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC_CONFIG : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_AFIO_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_AFIO_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_AFIO_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_AFIO_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_AFIO_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_AFIO_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CLEAR_IT : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32f1xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32f1xx_hal_rcc.h
  • __HAL_RCC_FLITF_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_FLITF_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_FLITF_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_FLITF_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_IT : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_USB_SOURCE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_HSE_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_HSE_GET_PREDIV : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_HSE_PREDIV_CONFIG : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32f1xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_LSE_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SRAM_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_CONFIG : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_WWDG_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_WWDG_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_WWDG_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_OVERFLOW_CLEAR_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_OVERFLOW_DISABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_OVERFLOW_ENABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_OVERFLOW_GET_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_OVERFLOW_GET_IT_SOURCE : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_SECOND_CLEAR_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_SECOND_DISABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_SECOND_ENABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_SECOND_GET_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_SECOND_GET_IT_SOURCE : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32f1xx_hal_rtc.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_DISABLE : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_ENABLE : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32f1xx_hal_smartcard.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32f1xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32f1xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32f1xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32f1xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32f1xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32f1xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32f1xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32f1xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32f1xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32f1xx_hal_spi.h
  • __HAL_TIM_CLEAR_FLAG : stm32f1xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32f1xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32f1xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32f1xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32f1xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32f1xx_hal_tim_ex.h
  • __HAL_TIM_ENABLE : stm32f1xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32f1xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32f1xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32f1xx_hal_tim_ex.h
  • __HAL_TIM_GET_AUTORELOAD : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32f1xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32f1xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32f1xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32f1xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32f1xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32f1xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32f1xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32f1xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32f1xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32f1xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32f1xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32f1xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32f1xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32f1xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32f1xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32f1xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32f1xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32f1xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32f1xx_hal_usart.h
  • __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_DISABLE_IT : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_IT : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_GET_FLAG : stm32f1xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32f1xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32f1xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32f1xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32f1xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32f1xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32f1xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32f1xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32f1xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32f1xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32f1xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32f1xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32f1xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32f1xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32f1xx_ll_adc.h
  • __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32f1xx_ll_adc.h
  • __LL_DMA_GET_CHANNEL : stm32f1xx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32f1xx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32f1xx_ll_dma.h
  • __LL_I2C_10BIT_ADDRESS : stm32f1xx_ll_i2c.h
  • __LL_I2C_10BIT_HEADER_READ : stm32f1xx_ll_i2c.h
  • __LL_I2C_10BIT_HEADER_WRITE : stm32f1xx_ll_i2c.h
  • __LL_I2C_FREQ_HZ_TO_MHZ : stm32f1xx_ll_i2c.h
  • __LL_I2C_FREQ_MHZ_TO_HZ : stm32f1xx_ll_i2c.h
  • __LL_I2C_RISE_TIME : stm32f1xx_ll_i2c.h
  • __LL_I2C_SPEED_FAST_TO_CCR : stm32f1xx_ll_i2c.h
  • __LL_I2C_SPEED_STANDARD_TO_CCR : stm32f1xx_ll_i2c.h
  • __LL_I2C_SPEED_TO_CCR : stm32f1xx_ll_i2c.h
  • __LL_RCC_CALC_HCLK_FREQ : stm32f1xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32f1xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK2_FREQ : stm32f1xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32f1xx_ll_rcc.h
  • __LL_TIM_CALC_ARR : stm32f1xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32f1xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32f1xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32f1xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32f1xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32f1xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32f1xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING16_100 : stm32f1xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32f1xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8_100 : stm32f1xx_ll_usart.h
  • __LL_USART_DIVFRAQ_SAMPLING16 : stm32f1xx_ll_usart.h
  • __LL_USART_DIVFRAQ_SAMPLING8 : stm32f1xx_ll_usart.h
  • __LL_USART_DIVMANT_SAMPLING16 : stm32f1xx_ll_usart.h
  • __LL_USART_DIVMANT_SAMPLING8 : stm32f1xx_ll_usart.h
  • __STM32F1xx_HAL_VERSION : stm32f1xx_hal.c
  • __STM32F1xx_HAL_VERSION_MAIN : stm32f1xx_hal.c
  • __STM32F1xx_HAL_VERSION_RC : stm32f1xx_hal.c
  • __STM32F1xx_HAL_VERSION_SUB1 : stm32f1xx_hal.c
  • __STM32F1xx_HAL_VERSION_SUB2 : stm32f1xx_hal.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ADC1_2_3_EXTERNALTRIG_T1_CC3 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC1_2_3_JSWSTART : stm32f1xx_hal_adc_ex.h
  • ADC1_2_3_SWSTART : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_EXT_IT11 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_T1_CC1 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_T1_CC2 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_T2_CC2 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_T3_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_T4_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIGINJEC_T2_CC1 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIGINJEC_T2_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIGINJEC_T3_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIGINJEC_T4_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32f1xx_hal_adc.h
  • ADC_AWD1_EVENT : stm32f1xx_hal_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32f1xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32f1xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_AWD_EVENT : stm32f1xx_hal_adc.h
  • ADC_AWD_TR1_HIGH_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_AWD_TR1_LOW_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_CALIBRATION_TIMEOUT : stm32f1xx_hal_adc_ex.c
  • ADC_CFGR_EXTSEL : stm32f1xx_hal_adc_ex.h
  • ADC_CFGR_JEXTSEL : stm32f1xx_hal_adc_ex.h
  • ADC_CHANNEL_0 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_2 : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32f1xx_hal_adc.h
  • ADC_CLEAR_ERRORCODE : stm32f1xx_hal_adc.h
  • ADC_COMMON_ADC_OTHER : stm32f1xx_hal_adc_ex.h
  • ADC_CONVCYCLES_MAX_RANGE : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_ConversionStop_Disable() : stm32f1xx_hal_adc.c
  • ADC_CR1_DISCONTINUOUS_NUM : stm32f1xx_hal_adc.h
  • ADC_CR1_DUALMOD_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_CR1_SCAN_SET : stm32f1xx_hal_adc.h
  • ADC_CR2_CONTINUOUS : stm32f1xx_hal_adc.h
  • ADC_DATAALIGN_LEFT : stm32f1xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32f1xx_hal_adc.h
  • ADC_DISABLE_TIMEOUT : stm32f1xx_hal_adc.c
  • ADC_DMAConvCplt() : stm32f1xx_hal_adc.c
  • ADC_DMAError() : stm32f1xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32f1xx_hal_adc.c
  • ADC_DUALMODE_ALTERTRIG : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT_INTERLFAST : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT_INTERLSLOW : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERLFAST : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERLSLOW : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32f1xx_hal_adc_ex.h
  • ADC_Enable() : stm32f1xx_hal_adc.c
  • ADC_ENABLE_TIMEOUT : stm32f1xx_hal_adc.c
  • ADC_EXTERNALTRIGCONV_EXT_IT11 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T1_CC1 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T1_CC2 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T1_CC3 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T2_CC2 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T3_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T4_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32f1xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32f1xx_hal_adc.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EXT_IT15 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_CC1 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32f1xx_hal_adc.h
  • ADC_FLAG_EOC : stm32f1xx_hal_adc.h
  • ADC_FLAG_JEOC : stm32f1xx_hal_adc.h
  • ADC_FLAG_JSTRT : stm32f1xx_hal_adc.h
  • ADC_FLAG_POSTCONV_ALL : stm32f1xx_hal_adc.h
  • ADC_FLAG_STRT : stm32f1xx_hal_adc.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_INJ_JOFRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32f1xx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32f1xx_hal_adc.h
  • ADC_INJECTED_RANK_1 : stm32f1xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32f1xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32f1xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32f1xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32f1xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32f1xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32f1xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32f1xx_hal_adc.h
  • ADC_IT_AWD : stm32f1xx_hal_adc.h
  • ADC_IT_EOC : stm32f1xx_hal_adc.h
  • ADC_IT_JEOC : stm32f1xx_hal_adc.h
  • ADC_JDR1_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JOFR1_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JOFR2_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JOFR3_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JOFR4_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JSQR_JL_SHIFT : stm32f1xx_hal_adc.h
  • ADC_JSQR_RK_JL : stm32f1xx_hal_adc.h
  • ADC_MODE_INDEPENDENT : stm32f1xx_hal_adc_ex.h
  • ADC_MULTI_SLAVE : stm32f1xx_hal_adc_ex.h
  • ADC_MULTIMODE_AUTO_INJECTED : stm32f1xx_hal_adc_ex.h
  • ADC_MULTIMODE_IS_ENABLE : stm32f1xx_hal_adc_ex.h
  • ADC_NONMULTIMODE_OR_MULTIMODEMASTER : stm32f1xx_hal_adc_ex.h
  • ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES : stm32f1xx_hal_adc_ex.c
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32f1xx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_REGULAR_GROUP : stm32f1xx_hal_adc.h
  • ADC_REGULAR_INJECTED_GROUP : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_1 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_10 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_11 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_12 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_13 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_14 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_15 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_16 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_9 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_13CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_1CYCLE_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_239CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_28CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_41CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_55CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_71CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_7CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 : stm32f1xx_hal_adc.h
  • ADC_SCAN_DISABLE : stm32f1xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32f1xx_hal_adc.h
  • ADC_SMPR1 : stm32f1xx_hal_adc.h
  • ADC_SMPR1_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_SMPR2 : stm32f1xx_hal_adc.h
  • ADC_SMPR2_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_SOFTWARE_START : stm32f1xx_hal_adc_ex.h
  • ADC_SQR1_L_SHIFT : stm32f1xx_hal_adc.h
  • ADC_SQR1_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_SQR1_RK : stm32f1xx_hal_adc.h
  • ADC_SQR2_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_SQR2_RK : stm32f1xx_hal_adc.h
  • ADC_SQR3_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_SQR3_RK : stm32f1xx_hal_adc.h
  • ADC_SQR4_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_STAB_DELAY_US : stm32f1xx_hal_adc.c
  • ADC_StabilizationTime() : stm32f1xx_hal_adc.h
  • ADC_STATE_CLR_SET : stm32f1xx_hal_adc.h
  • ADC_TEMPSENSOR_DELAY_US : stm32f1xx_hal_adc_ex.c , stm32f1xx_hal_adc.c
  • AFIO_EVENTOUT_PIN_0 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_1 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_10 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_11 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_12 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_13 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_14 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_15 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_2 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_3 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_4 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_5 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_6 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_7 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_8 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_9 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PORT_A : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PORT_B : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PORT_C : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PORT_D : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PORT_E : stm32f1xx_hal_gpio_ex.h
  • assert_param : stm32f1xx_ll_rcc.c , stm32f1xx_ll_usart.c , stm32f1xx_hal_conf.h , stm32f1xx_ll_adc.c , stm32f1xx_ll_dac.c , stm32f1xx_ll_i2c.c , stm32f1xx_ll_i2s.c , stm32f1xx_ll_gpio.c , stm32f1xx_ll_utils.c , stm32f1xx_ll_spi.c , stm32f1xx_ll_tim.c , stm32f1xx_ll_crc.c , stm32f1xx_ll_exti.c , stm32f1xx_ll_dma.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • a
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • BDCR_REG_INDEX : stm32f1xx_hal_rcc.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • CAN_BS1_10TQ : stm32f1xx_hal_can.h
  • CAN_BS1_11TQ : stm32f1xx_hal_can.h
  • CAN_BS1_12TQ : stm32f1xx_hal_can.h
  • CAN_BS1_13TQ : stm32f1xx_hal_can.h
  • CAN_BS1_14TQ : stm32f1xx_hal_can.h
  • CAN_BS1_15TQ : stm32f1xx_hal_can.h
  • CAN_BS1_16TQ : stm32f1xx_hal_can.h
  • CAN_BS1_1TQ : stm32f1xx_hal_can.h
  • CAN_BS1_2TQ : stm32f1xx_hal_can.h
  • CAN_BS1_3TQ : stm32f1xx_hal_can.h
  • CAN_BS1_4TQ : stm32f1xx_hal_can.h
  • CAN_BS1_5TQ : stm32f1xx_hal_can.h
  • CAN_BS1_6TQ : stm32f1xx_hal_can.h
  • CAN_BS1_7TQ : stm32f1xx_hal_can.h
  • CAN_BS1_8TQ : stm32f1xx_hal_can.h
  • CAN_BS1_9TQ : stm32f1xx_hal_can.h
  • CAN_BS2_1TQ : stm32f1xx_hal_can.h
  • CAN_BS2_2TQ : stm32f1xx_hal_can.h
  • CAN_BS2_3TQ : stm32f1xx_hal_can.h
  • CAN_BS2_4TQ : stm32f1xx_hal_can.h
  • CAN_BS2_5TQ : stm32f1xx_hal_can.h
  • CAN_BS2_6TQ : stm32f1xx_hal_can.h
  • CAN_BS2_7TQ : stm32f1xx_hal_can.h
  • CAN_BS2_8TQ : stm32f1xx_hal_can.h
  • CAN_ESR_BOF_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_ESR_EPV_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_ESR_EWG_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_FIFO0 : stm32f1xx_hal_can.h
  • CAN_FIFO1 : stm32f1xx_hal_can.h
  • CAN_FILTER_FIFO0 : stm32f1xx_hal_can.h
  • CAN_FILTER_FIFO1 : stm32f1xx_hal_can.h
  • CAN_FILTERMODE_IDLIST : stm32f1xx_hal_can.h
  • CAN_FILTERMODE_IDMASK : stm32f1xx_hal_can.h
  • CAN_FILTERSCALE_16BIT : stm32f1xx_hal_can.h
  • CAN_FILTERSCALE_32BIT : stm32f1xx_hal_can.h
  • CAN_FLAG_BOF : stm32f1xx_hal_can.h
  • CAN_FLAG_EPV : stm32f1xx_hal_can.h
  • CAN_FLAG_EWG : stm32f1xx_hal_can.h
  • CAN_FLAG_FF0 : stm32f1xx_hal_can.h
  • CAN_FLAG_FF1 : stm32f1xx_hal_can.h
  • CAN_FLAG_FOV0 : stm32f1xx_hal_can.h
  • CAN_FLAG_FOV1 : stm32f1xx_hal_can.h
  • CAN_FLAG_MASK : stm32f1xx_hal_can.h
  • CAN_FLAG_RQCP0 : stm32f1xx_hal_can.h
  • CAN_FLAG_RQCP1 : stm32f1xx_hal_can.h
  • CAN_FLAG_RQCP2 : stm32f1xx_hal_can.h
  • CAN_FLAG_SLAK : stm32f1xx_hal_can.h
  • CAN_FLAG_SLAKI : stm32f1xx_hal_can.h
  • CAN_FLAG_TME0 : stm32f1xx_hal_can.h
  • CAN_FLAG_TME1 : stm32f1xx_hal_can.h
  • CAN_FLAG_TME2 : stm32f1xx_hal_can.h
  • CAN_FLAG_TXOK0 : stm32f1xx_hal_can.h
  • CAN_FLAG_TXOK1 : stm32f1xx_hal_can.h
  • CAN_FLAG_TXOK2 : stm32f1xx_hal_can.h
  • CAN_FLAG_WKU : stm32f1xx_hal_can.h
  • CAN_ID_EXT : stm32f1xx_hal_can.h
  • CAN_ID_STD : stm32f1xx_hal_can.h
  • CAN_INITSTATUS_FAILED : stm32f1xx_hal_can.h
  • CAN_INITSTATUS_SUCCESS : stm32f1xx_hal_can.h
  • CAN_IT_BOF : stm32f1xx_hal_can.h
  • CAN_IT_EPV : stm32f1xx_hal_can.h
  • CAN_IT_ERR : stm32f1xx_hal_can.h
  • CAN_IT_EWG : stm32f1xx_hal_can.h
  • CAN_IT_FF0 : stm32f1xx_hal_can.h
  • CAN_IT_FF1 : stm32f1xx_hal_can.h
  • CAN_IT_FMP0 : stm32f1xx_hal_can.h
  • CAN_IT_FMP1 : stm32f1xx_hal_can.h
  • CAN_IT_FOV0 : stm32f1xx_hal_can.h
  • CAN_IT_FOV1 : stm32f1xx_hal_can.h
  • CAN_IT_LEC : stm32f1xx_hal_can.h
  • CAN_IT_SLK : stm32f1xx_hal_can.h
  • CAN_IT_TME : stm32f1xx_hal_can.h
  • CAN_IT_WKU : stm32f1xx_hal_can.h
  • CAN_MODE_LOOPBACK : stm32f1xx_hal_can.h
  • CAN_MODE_NORMAL : stm32f1xx_hal_can.h
  • CAN_MODE_SILENT : stm32f1xx_hal_can.h
  • CAN_MODE_SILENT_LOOPBACK : stm32f1xx_hal_can.h
  • CAN_MSR_SLAK_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_MSR_SLAKI_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_MSR_WKU_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_Receive_IT() : stm32f1xx_hal_can.c
  • CAN_RF0R_FF0_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_RF0R_FOV0_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_RF1R_FF1_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_RF1R_FOV1_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_RTR_DATA : stm32f1xx_hal_can.h
  • CAN_RTR_REMOTE : stm32f1xx_hal_can.h
  • CAN_SJW_1TQ : stm32f1xx_hal_can.h
  • CAN_SJW_2TQ : stm32f1xx_hal_can.h
  • CAN_SJW_3TQ : stm32f1xx_hal_can.h
  • CAN_SJW_4TQ : stm32f1xx_hal_can.h
  • CAN_TIMEOUT_VALUE : stm32f1xx_hal_can.c
  • CAN_Transmit_IT() : stm32f1xx_hal_can.c
  • CAN_TSR_RQCP0_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_RQCP1_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_RQCP2_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TME0_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TME1_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TME2_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TXOK0_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TXOK1_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TXOK2_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TXMAILBOX_0 : stm32f1xx_hal_can.h
  • CAN_TXMAILBOX_1 : stm32f1xx_hal_can.h
  • CAN_TXMAILBOX_2 : stm32f1xx_hal_can.h
  • CAN_TXSTATUS_NOMAILBOX : stm32f1xx_hal_can.h
  • CHANNEL_OFFSET_TAB : stm32f1xx_ll_dma.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • CR_DBP_BB : stm32f1xx_hal_pwr.c
  • CR_LPSDSR_BB : stm32f1xx_hal_pwr.c
  • CR_PVDE_BB : stm32f1xx_hal_pwr.c
  • CR_REG_INDEX : stm32f1xx_hal_rcc.h , stm32f1xx_hal_rcc_ex.h
  • CSR_EWUP_BB : stm32f1xx_hal_pwr.c
  • CSR_REG_INDEX : stm32f1xx_hal_rcc.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DBP_BIT_NUMBER : stm32f1xx_hal_pwr.c
  • DMA_CIRCULAR : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL1 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL2 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL3 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL4 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL5 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL6 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL7 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT1 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT2 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT3 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT4 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT5 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT6 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT7 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC1 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC2 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC3 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC4 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC5 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC6 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC7 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE1 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE2 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE3 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE4 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE5 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE6 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE7 : stm32f1xx_hal_dma.h
  • DMA_HandleTypeDef : stm32f1xx_hal_dma.h
  • DMA_IT_HT : stm32f1xx_hal_dma.h
  • DMA_IT_TC : stm32f1xx_hal_dma.h
  • DMA_IT_TE : stm32f1xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32f1xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32f1xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32f1xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32f1xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32f1xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32f1xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32f1xx_hal_dma.h
  • DMA_NORMAL : stm32f1xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32f1xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32f1xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32f1xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32f1xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32f1xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32f1xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32f1xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32f1xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32f1xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32f1xx_hal_dma.h
  • DMA_SetConfig() : stm32f1xx_hal_dma.c
  • DP83848_PHY_ADDRESS : stm32f1xx_hal_conf.h
  • DT_DELAY_1 : stm32f1xx_ll_tim.h
  • DT_DELAY_2 : stm32f1xx_ll_tim.h
  • DT_DELAY_3 : stm32f1xx_ll_tim.h
  • DT_DELAY_4 : stm32f1xx_ll_tim.h
  • DT_RANGE_1 : stm32f1xx_ll_tim.h
  • DT_RANGE_2 : stm32f1xx_ll_tim.h
  • DT_RANGE_3 : stm32f1xx_ll_tim.h
  • DT_RANGE_4 : stm32f1xx_ll_tim.h
  • DUMMY_DATA : stm32f1xx_hal_usart.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • Defines
  • _
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • ESR_REGISTER_INDEX : stm32f1xx_hal_can.h
  • ETH_RX_BUF_SIZE : stm32f1xx_hal_conf.h
  • ETH_RXBUFNB : stm32f1xx_hal_conf.h
  • ETH_TX_BUF_SIZE : stm32f1xx_hal_conf.h
  • ETH_TXBUFNB : stm32f1xx_hal_conf.h
  • EXTI_MODE : stm32f1xx_hal_gpio.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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  • _
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALLING_EDGE : stm32f1xx_hal_gpio.c
  • FLASH_BANK_1 : stm32f1xx_hal_flash_ex.h
  • FLASH_FLAG_BSY : stm32f1xx_hal_flash_ex.h
  • FLASH_FLAG_EOP : stm32f1xx_hal_flash_ex.h
  • FLASH_FLAG_OPTVERR : stm32f1xx_hal_flash_ex.h
  • FLASH_FLAG_PGERR : stm32f1xx_hal_flash_ex.h
  • FLASH_FLAG_WRPERR : stm32f1xx_hal_flash_ex.h
  • FLASH_IT_EOP : stm32f1xx_hal_flash_ex.h
  • FLASH_IT_ERR : stm32f1xx_hal_flash_ex.h
  • FLASH_LATENCY_0 : stm32f1xx_hal_flash.h
  • FLASH_LATENCY_1 : stm32f1xx_hal_flash.h
  • FLASH_LATENCY_2 : stm32f1xx_hal_flash.h
  • FLASH_MassErase() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_ProgramData() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_RDP_LevelConfig() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32f1xx_hal_flash_ex.c
  • FLASH_PAGE_SIZE : stm32f1xx_hal_flash_ex.h
  • FLASH_PageErase() : stm32f1xx_hal_flash.c , stm32f1xx_hal_flash_ex.c
  • FLASH_POSITION_IWDGSW_BIT : stm32f1xx_hal_flash_ex.c
  • FLASH_POSITION_OB_USERDATA0_BIT : stm32f1xx_hal_flash_ex.c
  • FLASH_POSITION_OB_USERDATA1_BIT : stm32f1xx_hal_flash_ex.c
  • FLASH_PROC_MASSERASE : stm32f1xx_hal_flash.h
  • FLASH_PROC_NONE : stm32f1xx_hal_flash.h
  • FLASH_PROC_PAGEERASE : stm32f1xx_hal_flash.h
  • FLASH_PROC_PROGRAMDOUBLEWORD : stm32f1xx_hal_flash.h
  • FLASH_PROC_PROGRAMHALFWORD : stm32f1xx_hal_flash.h
  • FLASH_PROC_PROGRAMWORD : stm32f1xx_hal_flash.h
  • FLASH_ProcedureTypeDef : stm32f1xx_hal_flash.h
  • FLASH_Program_HalfWord() : stm32f1xx_hal_flash.c
  • FLASH_SetErrorCode() : stm32f1xx_hal_flash.c
  • FLASH_SIZE_DATA_REGISTER : stm32f1xx_hal_flash_ex.h
  • FLASH_TIMEOUT_VALUE : stm32f1xx_hal_flash.h
  • FLASH_TYPEERASE_MASSERASE : stm32f1xx_hal_flash_ex.h
  • FLASH_TYPEERASE_PAGES : stm32f1xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32f1xx_hal_flash.h
  • FLASH_TYPEPROGRAM_HALFWORD : stm32f1xx_hal_flash.h
  • FLASH_TYPEPROGRAM_WORD : stm32f1xx_hal_flash.h
  • FLASH_WaitForLastOperation() : stm32f1xx_hal_flash.c
  • FLASHSIZE_BASE_ADDRESS : stm32f1xx_ll_utils.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • i
  • l
  • m
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • GPIO_CR_CNF_AF_OUTPUT_OD : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_AF_OUTPUT_PP : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_ANALOG : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_GP_OUTPUT_OD : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_GP_OUTPUT_PP : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_INPUT_FLOATING : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_INPUT_PU_PD : stm32f1xx_hal_gpio.c
  • GPIO_CR_MODE_INPUT : stm32f1xx_hal_gpio.c
  • GPIO_GET_INDEX : stm32f1xx_hal_gpio_ex.h
  • GPIO_MODE : stm32f1xx_hal_gpio.c
  • GPIO_MODE_AF_INPUT : stm32f1xx_hal_gpio.h
  • GPIO_MODE_AF_OD : stm32f1xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32f1xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32f1xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32f1xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32f1xx_hal_gpio.h
  • GPIO_MODE_IT : stm32f1xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32f1xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32f1xx_hal_gpio.h
  • GPIO_NOPULL : stm32f1xx_hal_gpio.h
  • GPIO_NUMBER : stm32f1xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32f1xx_hal_gpio.c
  • GPIO_PIN_0 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_1 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_10 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_11 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_12 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_13 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_14 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_15 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_2 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_3 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_4 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_5 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_6 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_7 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_8 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_9 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_All : stm32f1xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32f1xx_hal_gpio.h
  • GPIO_PIN_RESET : stm32f1xx_hal_gpio.h
  • GPIO_PIN_SET : stm32f1xx_hal_gpio.h
  • GPIO_PinState : stm32f1xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32f1xx_hal_gpio.h
  • GPIO_PULLUP : stm32f1xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32f1xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32f1xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32f1xx_hal_gpio.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
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  • Variables
  • Typedefs
  • Enumerations
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  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- h -

  • HAL_ADC_AnalogWDGConfig() : stm32f1xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32f1xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32f1xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32f1xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32f1xx_hal_adc.c
  • HAL_ADC_ERROR_DMA : stm32f1xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32f1xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32f1xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32f1xx_hal_adc.h
  • HAL_ADC_ErrorCallback() : stm32f1xx_hal_adc.c
  • HAL_ADC_GetError() : stm32f1xx_hal_adc.c
  • HAL_ADC_GetState() : stm32f1xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32f1xx_hal_adc.c
  • HAL_ADC_Init() : stm32f1xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32f1xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32f1xx_hal_adc.c
  • HAL_ADC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_ADC_MspDeInit() : stm32f1xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32f1xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32f1xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32f1xx_hal_adc.c
  • HAL_ADC_Start() : stm32f1xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32f1xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32f1xx_hal_adc.c
  • HAL_ADC_STATE_AWD1 : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32f1xx_hal_adc.h
  • HAL_ADC_Stop() : stm32f1xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32f1xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32f1xx_hal_adc.c
  • HAL_ADCEx_Calibration_Start() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32f1xx_hal_adc_ex.c
  • HAL_CAN_ConfigFilter() : stm32f1xx_hal_can.c
  • HAL_CAN_DeInit() : stm32f1xx_hal_can.c
  • HAL_CAN_ERROR_ACK : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_BD : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_BOF : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_BR : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_CRC : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_EPV : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_EWG : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_FOR : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_FOV0 : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_FOV1 : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_NONE : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_STF : stm32f1xx_hal_can.h
  • HAL_CAN_ErrorCallback() : stm32f1xx_hal_can.c
  • HAL_CAN_GetError() : stm32f1xx_hal_can.c
  • HAL_CAN_GetState() : stm32f1xx_hal_can.c
  • HAL_CAN_Init() : stm32f1xx_hal_can.c
  • HAL_CAN_IRQHandler() : stm32f1xx_hal_can.c
  • HAL_CAN_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_CAN_MspDeInit() : stm32f1xx_hal_can.c
  • HAL_CAN_MspInit() : stm32f1xx_hal_can.c
  • HAL_CAN_Receive() : stm32f1xx_hal_can.c
  • HAL_CAN_Receive_IT() : stm32f1xx_hal_can.c
  • HAL_CAN_RxCpltCallback() : stm32f1xx_hal_can.c
  • HAL_CAN_Sleep() : stm32f1xx_hal_can.c
  • HAL_CAN_STATE_BUSY : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_ERROR : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_READY : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_RESET : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_TIMEOUT : stm32f1xx_hal_can.h
  • HAL_CAN_StateTypeDef : stm32f1xx_hal_can.h
  • HAL_CAN_Transmit() : stm32f1xx_hal_can.c
  • HAL_CAN_Transmit_IT() : stm32f1xx_hal_can.c
  • HAL_CAN_TxCpltCallback() : stm32f1xx_hal_can.c
  • HAL_CAN_WakeUp() : stm32f1xx_hal_can.c
  • HAL_CEC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_CRC_Accumulate() : stm32f1xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32f1xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32f1xx_hal_crc.c
  • HAL_CRC_GetState() : stm32f1xx_hal_crc.c
  • HAL_CRC_Init() : stm32f1xx_hal_crc.c
  • HAL_CRC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_CRC_MspDeInit() : stm32f1xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32f1xx_hal_crc.c
  • HAL_CRC_STATE_BUSY : stm32f1xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32f1xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32f1xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32f1xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32f1xx_hal_crc.h
  • HAL_CRC_StateTypeDef : stm32f1xx_hal_crc.h
  • HAL_DAC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32f1xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32f1xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32f1xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32f1xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32f1xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32f1xx_hal.c
  • HAL_DeInit() : stm32f1xx_hal.c
  • HAL_Delay() : stm32f1xx_hal.c
  • HAL_DMA_Abort() : stm32f1xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32f1xx_hal_dma.c
  • HAL_DMA_CallbackIDTypeDef : stm32f1xx_hal_dma.h
  • HAL_DMA_DeInit() : stm32f1xx_hal_dma.c
  • HAL_DMA_ERROR_NO_XFER : stm32f1xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32f1xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32f1xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32f1xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32f1xx_hal_dma.h
  • HAL_DMA_FULL_TRANSFER : stm32f1xx_hal_dma.h
  • HAL_DMA_GetError() : stm32f1xx_hal_dma.c
  • HAL_DMA_GetState() : stm32f1xx_hal_dma.c
  • HAL_DMA_HALF_TRANSFER : stm32f1xx_hal_dma.h
  • HAL_DMA_Init() : stm32f1xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32f1xx_hal_dma.c
  • HAL_DMA_LevelCompleteTypeDef : stm32f1xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_DMA_PollForTransfer() : stm32f1xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32f1xx_hal_dma.c
  • HAL_DMA_Start() : stm32f1xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32f1xx_hal_dma.c
  • HAL_DMA_STATE_BUSY : stm32f1xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32f1xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32f1xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32f1xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32f1xx_hal_dma.h
  • HAL_DMA_UnRegisterCallback() : stm32f1xx_hal_dma.c
  • HAL_DMA_XFER_ABORT_CB_ID : stm32f1xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32f1xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32f1xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32f1xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32f1xx_hal_dma.h
  • HAL_ETH_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_FLASH_EndOfOperationCallback() : stm32f1xx_hal_flash.c
  • HAL_FLASH_ERROR_NONE : stm32f1xx_hal_flash.h
  • HAL_FLASH_ERROR_OPTV : stm32f1xx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32f1xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32f1xx_hal_flash.h
  • HAL_FLASH_GetError() : stm32f1xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32f1xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32f1xx_hal_flash.c
  • HAL_FLASH_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_FLASH_OB_Launch() : stm32f1xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32f1xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32f1xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32f1xx_hal_flash.c
  • HAL_FLASH_Program() : stm32f1xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32f1xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32f1xx_hal_flash.c
  • HAL_FLASHEx_Erase() : stm32f1xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32f1xx_hal_flash_ex.c
  • HAL_FLASHEx_OBErase() : stm32f1xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32f1xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetUserData() : stm32f1xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32f1xx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32f1xx_hal.c
  • HAL_GetHalVersion() : stm32f1xx_hal.c
  • HAL_GetREVID() : stm32f1xx_hal.c
  • HAL_GetTick() : stm32f1xx_hal.c
  • HAL_GetUID() : stm32f1xx_hal.c
  • HAL_GPIO_DeInit() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_GPIO_ReadPin() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32f1xx_hal_gpio.c
  • HAL_GPIOEx_ConfigEventout() : stm32f1xx_hal_gpio_ex.c
  • HAL_GPIOEx_DisableEventout() : stm32f1xx_hal_gpio_ex.c
  • HAL_GPIOEx_EnableEventout() : stm32f1xx_hal_gpio_ex.c
  • HAL_HalfDuplex_EnableReceiver() : stm32f1xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32f1xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32f1xx_hal_uart.c
  • HAL_HCD_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_I2C_AbortCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32f1xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32f1xx_hal_i2c.c
  • HAL_I2C_ERROR_AF : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32f1xx_hal_i2c.h
  • HAL_I2C_ErrorCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32f1xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32f1xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32f1xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Init() : stm32f1xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32f1xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Receive_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Transmit_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MODE_MASTER : stm32f1xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32f1xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32f1xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32f1xx_hal_i2c.h
  • HAL_I2C_ModeTypeDef : stm32f1xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_I2C_MspDeInit() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Receive_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Transmit_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_STATE_ABORT : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32f1xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32f1xx_hal_i2c.h
  • HAL_I2S_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_IncTick() : stm32f1xx_hal.c
  • HAL_Init() : stm32f1xx_hal.c
  • HAL_InitTick() : stm32f1xx_hal.c
  • HAL_IRDA_Abort() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Abort_IT() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_DeInit() : stm32f1xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32f1xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32f1xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32f1xx_hal_irda.c
  • HAL_IRDA_ERROR_DMA : stm32f1xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32f1xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32f1xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32f1xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32f1xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32f1xx_hal_irda.h
  • HAL_IRDA_ErrorCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32f1xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Init() : stm32f1xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32f1xx_hal_irda.c
  • HAL_IRDA_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_IRDA_MspDeInit() : stm32f1xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32f1xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_STATE_BUSY : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32f1xx_hal_irda.h
  • HAL_IRDA_StateTypeDef : stm32f1xx_hal_irda.h
  • HAL_IRDA_Transmit() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32f1xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32f1xx_hal_iwdg.c
  • HAL_IWDG_Init() : stm32f1xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_IWDG_Refresh() : stm32f1xx_hal_iwdg.c
  • HAL_LIN_Init() : stm32f1xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32f1xx_hal_uart.c
  • HAL_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_MspDeInit() : stm32f1xx_hal.c
  • HAL_MspInit() : stm32f1xx_hal.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32f1xx_hal_uart.c
  • HAL_MultiProcessor_ExitMuteMode() : stm32f1xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32f1xx_hal_uart.c
  • HAL_NAND_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_NVIC_ClearPendingIRQ() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32f1xx_hal_cortex.c
  • HAL_PCCARD_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_PCD_ActivateRemoteWakeup() : stm32f1xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32f1xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32f1xx_hal_pcd.c
  • HAL_PCD_Init() : stm32f1xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32f1xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_PCD_MspDeInit() : stm32f1xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32f1xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32f1xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_Start() : stm32f1xx_hal_pcd.c
  • HAL_PCD_STATE_BUSY : stm32f1xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32f1xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32f1xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32f1xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32f1xx_hal_pcd.h
  • HAL_PCD_Stop() : stm32f1xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCDEx_PMAConfig() : stm32f1xx_hal_pcd_ex.c
  • HAL_PCDEx_SetConnectionState() : stm32f1xx_hal_pcd_ex.c
  • HAL_PWR_ConfigPVD() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32f1xx_hal_pwr.c
  • HAL_PWR_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_PWR_PVD_IRQHandler() : stm32f1xx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32f1xx_hal_pwr.c
  • HAL_RCC_ClockConfig() : stm32f1xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32f1xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32f1xx_hal_rcc.c
  • HAL_RCC_DisableCSS() : stm32f1xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32f1xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32f1xx_hal_rcc.c
  • HAL_RCC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_RCC_NMI_IRQHandler() : stm32f1xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32f1xx_hal_rcc.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32f1xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32f1xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32f1xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32f1xx_hal.c
  • HAL_RTC_AlarmAEventCallback() : stm32f1xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32f1xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32f1xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32f1xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32f1xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32f1xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32f1xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32f1xx_hal_rtc.c
  • HAL_RTC_Init() : stm32f1xx_hal_rtc.c
  • HAL_RTC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_RTC_MspDeInit() : stm32f1xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32f1xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32f1xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32f1xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32f1xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32f1xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32f1xx_hal_rtc.c
  • HAL_RTC_STATE_BUSY : stm32f1xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32f1xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32f1xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32f1xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32f1xx_hal_rtc.h
  • HAL_RTC_WaitForSynchro() : stm32f1xx_hal_rtc.c
  • HAL_RTCEx_BKUPRead() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateSecond() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_RTCEventCallback() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_RTCEventErrorCallback() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_RTCIRQHandler() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSecond_IT() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperIRQHandler() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperTimeStampIRQHandler : stm32f1xx_hal_rtc_ex.h
  • HAL_RTCStateTypeDef : stm32f1xx_hal_rtc.h
  • HAL_SD_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_SMARTCARD_Abort() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Abort_IT() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortCpltCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_DeInit() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_ERROR_DMA : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ErrorCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_SMARTCARD_MspDeInit() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_ReInit() : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_RxCpltCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_STATE_BUSY : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_StateTypeDef : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_Transmit() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SPI_Abort() : stm32f1xx_hal_spi.c
  • HAL_SPI_Abort_IT() : stm32f1xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_DeInit() : stm32f1xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32f1xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32f1xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32f1xx_hal_spi.c
  • HAL_SPI_ERROR_CRC : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32f1xx_hal_spi.h
  • HAL_SPI_ErrorCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_GetError() : stm32f1xx_hal_spi.c
  • HAL_SPI_GetState() : stm32f1xx_hal_spi.c
  • HAL_SPI_Init() : stm32f1xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32f1xx_hal_spi.c
  • HAL_SPI_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_SPI_MspDeInit() : stm32f1xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32f1xx_hal_spi.c
  • HAL_SPI_Receive() : stm32f1xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32f1xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32f1xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_STATE_BUSY : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32f1xx_hal_spi.h
  • HAL_SPI_StateTypeDef : stm32f1xx_hal_spi.h
  • HAL_SPI_Transmit() : stm32f1xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32f1xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32f1xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32f1xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32f1xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32f1xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SRAM_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_SuspendTick() : stm32f1xx_hal.c
  • HAL_SYSTICK_Callback() : stm32f1xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32f1xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32f1xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32f1xx_hal_cortex.c
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32f1xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32f1xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32f1xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32f1xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32f1xx_hal_tim.h
  • HAL_TIM_ActiveChannel : stm32f1xx_hal_tim.h
  • HAL_TIM_Base_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32f1xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32f1xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32f1xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32f1xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32f1xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32f1xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32f1xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32f1xx_hal_tim.c
  • HAL_TIM_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_TIM_OC_ConfigChannel() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32f1xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32f1xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_STATE_BUSY : stm32f1xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32f1xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32f1xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32f1xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32f1xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32f1xx_hal_tim.h
  • HAL_TIM_TriggerCallback() : stm32f1xx_hal_tim.c
  • HAL_TIMEx_BreakCallback() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_UART_Abort() : stm32f1xx_hal_uart.c
  • HAL_UART_Abort_IT() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_DeInit() : stm32f1xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32f1xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32f1xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32f1xx_hal_uart.c
  • HAL_UART_ERROR_DMA : stm32f1xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32f1xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32f1xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32f1xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32f1xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32f1xx_hal_uart.h
  • HAL_UART_ErrorCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_GetError() : stm32f1xx_hal_uart.c
  • HAL_UART_GetState() : stm32f1xx_hal_uart.c
  • HAL_UART_Init() : stm32f1xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32f1xx_hal_uart.c
  • HAL_UART_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_UART_MspDeInit() : stm32f1xx_hal_uart.c
  • HAL_UART_MspInit() : stm32f1xx_hal_uart.c
  • HAL_UART_Receive() : stm32f1xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32f1xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32f1xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_STATE_BUSY : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32f1xx_hal_uart.h
  • HAL_UART_StateTypeDef : stm32f1xx_hal_uart.h
  • HAL_UART_Transmit() : stm32f1xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32f1xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32f1xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_USART_Abort() : stm32f1xx_hal_usart.c
  • HAL_USART_Abort_IT() : stm32f1xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_DeInit() : stm32f1xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32f1xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32f1xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32f1xx_hal_usart.c
  • HAL_USART_ERROR_DMA : stm32f1xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32f1xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32f1xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32f1xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32f1xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32f1xx_hal_usart.h
  • HAL_USART_ErrorCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_GetError() : stm32f1xx_hal_usart.c
  • HAL_USART_GetState() : stm32f1xx_hal_usart.c
  • HAL_USART_Init() : stm32f1xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32f1xx_hal_usart.c
  • HAL_USART_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_USART_MspDeInit() : stm32f1xx_hal_usart.c
  • HAL_USART_MspInit() : stm32f1xx_hal_usart.c
  • HAL_USART_Receive() : stm32f1xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32f1xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32f1xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_STATE_BUSY : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32f1xx_hal_usart.h
  • HAL_USART_StateTypeDef : stm32f1xx_hal_usart.h
  • HAL_USART_Transmit() : stm32f1xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32f1xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32f1xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32f1xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32f1xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32f1xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32f1xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32f1xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32f1xx_hal_wwdg.c
  • HAL_WWDG_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_WWDG_MspInit() : stm32f1xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32f1xx_hal_wwdg.c
  • HSE_STARTUP_TIMEOUT : stm32f1xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • HSE_VALUE : stm32f1xx_hal_conf.h , stm32f1xx_ll_rcc.h
  • HSI_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • HSI_VALUE : stm32f1xx_hal_conf.h , stm32f1xx_ll_rcc.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • I2C_10BIT_ADDRESS : stm32f1xx_hal_i2c.h
  • I2C_10BIT_HEADER_READ : stm32f1xx_hal_i2c.h
  • I2C_10BIT_HEADER_WRITE : stm32f1xx_hal_i2c.h
  • I2C_7BIT_ADD_READ : stm32f1xx_hal_i2c.h
  • I2C_7BIT_ADD_WRITE : stm32f1xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_10BIT : stm32f1xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32f1xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32f1xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32f1xx_hal_i2c.h
  • I2C_DMAAbort() : stm32f1xx_hal_i2c.c
  • I2C_DMAError() : stm32f1xx_hal_i2c.c
  • I2C_DMAXferCplt() : stm32f1xx_hal_i2c.c
  • I2C_DUALADDRESS_DISABLE : stm32f1xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32f1xx_hal_i2c.h
  • I2C_DUTYCYCLE_16_9 : stm32f1xx_hal_i2c.h
  • I2C_DUTYCYCLE_2 : stm32f1xx_hal_i2c.h
  • I2C_FIRST_AND_LAST_FRAME : stm32f1xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32f1xx_hal_i2c.h
  • I2C_FLAG_ADD10 : stm32f1xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32f1xx_hal_i2c.h
  • I2C_FLAG_AF : stm32f1xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32f1xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32f1xx_hal_i2c.h
  • I2C_FLAG_BTF : stm32f1xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32f1xx_hal_i2c.h
  • I2C_FLAG_DUALF : stm32f1xx_hal_i2c.h
  • I2C_FLAG_GENCALL : stm32f1xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32f1xx_hal_i2c.h
  • I2C_FLAG_MSL : stm32f1xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32f1xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32f1xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32f1xx_hal_i2c.h
  • I2C_FLAG_SB : stm32f1xx_hal_i2c.h
  • I2C_FLAG_SMBALERT : stm32f1xx_hal_i2c.h
  • I2C_FLAG_SMBDEFAULT : stm32f1xx_hal_i2c.h
  • I2C_FLAG_SMBHOST : stm32f1xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32f1xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32f1xx_hal_i2c.h
  • I2C_FLAG_TRA : stm32f1xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32f1xx_hal_i2c.h
  • I2C_FREQRANGE : stm32f1xx_hal_i2c.h
  • I2C_GENERALCALL_DISABLE : stm32f1xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32f1xx_hal_i2c.h
  • I2C_IsAcknowledgeFailed() : stm32f1xx_hal_i2c.c
  • I2C_IT_BUF : stm32f1xx_hal_i2c.h
  • I2C_IT_ERR : stm32f1xx_hal_i2c.h
  • I2C_IT_EVT : stm32f1xx_hal_i2c.h
  • I2C_ITError() : stm32f1xx_hal_i2c.c
  • I2C_LAST_FRAME : stm32f1xx_hal_i2c.h
  • I2C_Master_ADD10() : stm32f1xx_hal_i2c.c
  • I2C_Master_ADDR() : stm32f1xx_hal_i2c.c
  • I2C_Master_SB() : stm32f1xx_hal_i2c.c
  • I2C_MasterReceive_BTF() : stm32f1xx_hal_i2c.c
  • I2C_MasterReceive_RXNE() : stm32f1xx_hal_i2c.c
  • I2C_MasterRequestRead() : stm32f1xx_hal_i2c.c
  • I2C_MasterRequestWrite() : stm32f1xx_hal_i2c.c
  • I2C_MasterTransmit_BTF() : stm32f1xx_hal_i2c.c
  • I2C_MasterTransmit_TXE() : stm32f1xx_hal_i2c.c
  • I2C_MEM_ADD_LSB : stm32f1xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32f1xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32f1xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32f1xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32f1xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32f1xx_hal_i2c.c
  • I2C_NOSTRETCH_DISABLE : stm32f1xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32f1xx_hal_i2c.h
  • I2C_RequestMemoryRead() : stm32f1xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32f1xx_hal_i2c.c
  • I2C_RISE_TIME : stm32f1xx_hal_i2c.h
  • I2C_Slave_ADDR() : stm32f1xx_hal_i2c.c
  • I2C_Slave_AF() : stm32f1xx_hal_i2c.c
  • I2C_Slave_STOPF() : stm32f1xx_hal_i2c.c
  • I2C_SlaveReceive_BTF() : stm32f1xx_hal_i2c.c
  • I2C_SlaveReceive_RXNE() : stm32f1xx_hal_i2c.c
  • I2C_SlaveTransmit_BTF() : stm32f1xx_hal_i2c.c
  • I2C_SlaveTransmit_TXE() : stm32f1xx_hal_i2c.c
  • I2C_SPEED : stm32f1xx_hal_i2c.h
  • I2C_SPEED_FAST : stm32f1xx_hal_i2c.h
  • I2C_SPEED_STANDARD : stm32f1xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32f1xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32f1xx_hal_i2c.c
  • I2C_STATE_MSK : stm32f1xx_hal_i2c.c
  • I2C_STATE_NONE : stm32f1xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32f1xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32f1xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY_FLAG : stm32f1xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32f1xx_hal_i2c.c
  • I2C_WaitOnBTFFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnMasterAddressFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnTXEFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2S_I2SCFGR_CLEAR_MASK : stm32f1xx_ll_i2s.c
  • I2S_I2SPR_CLEAR_MASK : stm32f1xx_ll_i2s.c
  • IC1Config() : stm32f1xx_ll_tim.c
  • IC2Config() : stm32f1xx_ll_tim.c
  • IC3Config() : stm32f1xx_ll_tim.c
  • IC4Config() : stm32f1xx_ll_tim.c
  • IDCODE_DEVID_MASK : stm32f1xx_hal.c
  • IRDA_BRR : stm32f1xx_hal_irda.h
  • IRDA_CR1_REG_INDEX : stm32f1xx_hal_irda.h
  • IRDA_CR2_REG_INDEX : stm32f1xx_hal_irda.h
  • IRDA_CR3_REG_INDEX : stm32f1xx_hal_irda.h
  • IRDA_DIV : stm32f1xx_hal_irda.h
  • IRDA_DIVFRAQ : stm32f1xx_hal_irda.h
  • IRDA_DIVMANT : stm32f1xx_hal_irda.h
  • IRDA_DMAAbortOnError() : stm32f1xx_hal_irda.c
  • IRDA_DMAError() : stm32f1xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32f1xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32f1xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32f1xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32f1xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32f1xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32f1xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32f1xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32f1xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32f1xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32f1xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32f1xx_hal_irda.c
  • IRDA_FLAG_FE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_IDLE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_NE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_PE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_TC : stm32f1xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32f1xx_hal_irda.h
  • IRDA_IT_CTS : stm32f1xx_hal_irda.h
  • IRDA_IT_ERR : stm32f1xx_hal_irda.h
  • IRDA_IT_IDLE : stm32f1xx_hal_irda.h
  • IRDA_IT_LBD : stm32f1xx_hal_irda.h
  • IRDA_IT_MASK : stm32f1xx_hal_irda.h
  • IRDA_IT_PE : stm32f1xx_hal_irda.h
  • IRDA_IT_RXNE : stm32f1xx_hal_irda.h
  • IRDA_IT_TC : stm32f1xx_hal_irda.h
  • IRDA_IT_TXE : stm32f1xx_hal_irda.h
  • IRDA_MODE_RX : stm32f1xx_hal_irda.h
  • IRDA_MODE_TX : stm32f1xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32f1xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32f1xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32f1xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32f1xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32f1xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32f1xx_hal_irda.h
  • IRDA_Receive_IT() : stm32f1xx_hal_irda.c
  • IRDA_SetConfig() : stm32f1xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32f1xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32f1xx_hal_irda.c
  • IRDA_WORDLENGTH_8B : stm32f1xx_hal_irda.h
  • IRDA_WORDLENGTH_9B : stm32f1xx_hal_irda.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32f1xx_hal_adc.h
  • IS_ADC_CHANNEL : stm32f1xx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32f1xx_hal_adc.h
  • IS_ADC_DATA_ALIGN : stm32f1xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32f1xx_hal_adc.h
  • IS_ADC_EXTTRIG : stm32f1xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG_EDGE : stm32f1xx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32f1xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32f1xx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32f1xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32f1xx_hal_adc_ex.h
  • IS_ADC_MODE : stm32f1xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32f1xx_hal_adc.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32f1xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32f1xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32f1xx_hal_adc.h
  • IS_ADC_SAMPLE_TIME : stm32f1xx_hal_adc.h
  • IS_ADC_SCAN_MODE : stm32f1xx_hal_adc.h
  • IS_AFIO_EVENTOUT_PIN : stm32f1xx_hal_gpio_ex.h
  • IS_AFIO_EVENTOUT_PORT : stm32f1xx_hal_gpio_ex.h
  • IS_CAN_BANKNUMBER : stm32f1xx_hal_can.h
  • IS_CAN_BS1 : stm32f1xx_hal_can.h
  • IS_CAN_BS2 : stm32f1xx_hal_can.h
  • IS_CAN_DLC : stm32f1xx_hal_can.h
  • IS_CAN_EXTID : stm32f1xx_hal_can.h
  • IS_CAN_FIFO : stm32f1xx_hal_can.h
  • IS_CAN_FILTER_FIFO : stm32f1xx_hal_can.h
  • IS_CAN_FILTER_MODE : stm32f1xx_hal_can.h
  • IS_CAN_FILTER_NUMBER : stm32f1xx_hal_can_ex.h
  • IS_CAN_FILTER_SCALE : stm32f1xx_hal_can.h
  • IS_CAN_IDTYPE : stm32f1xx_hal_can.h
  • IS_CAN_MODE : stm32f1xx_hal_can.h
  • IS_CAN_PRESCALER : stm32f1xx_hal_can.h
  • IS_CAN_RTR : stm32f1xx_hal_can.h
  • IS_CAN_SJW : stm32f1xx_hal_can.h
  • IS_CAN_STDID : stm32f1xx_hal_can.h
  • IS_CAN_TRANSMITMAILBOX : stm32f1xx_hal_can.h
  • IS_DMA_BUFFER_SIZE : stm32f1xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32f1xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32f1xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32f1xx_hal_dma.h
  • IS_DMA_MODE : stm32f1xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32f1xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32f1xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32f1xx_hal_dma.h
  • IS_FLASH_BANK : stm32f1xx_hal_flash_ex.h
  • IS_FLASH_LATENCY : stm32f1xx_hal_flash.h
  • IS_FLASH_NB_PAGES : stm32f1xx_hal_flash_ex.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32f1xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32f1xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32f1xx_hal_flash.h
  • IS_GPIO_MODE : stm32f1xx_hal_gpio.h
  • IS_GPIO_PIN : stm32f1xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32f1xx_hal_gpio.h
  • IS_GPIO_PULL : stm32f1xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32f1xx_hal_gpio.h
  • IS_I2C_ADDRESSING_MODE : stm32f1xx_hal_i2c.h
  • IS_I2C_CLOCK_SPEED : stm32f1xx_hal_i2c.h , stm32f1xx_ll_i2c.c
  • IS_I2C_DUAL_ADDRESS : stm32f1xx_hal_i2c.h
  • IS_I2C_DUTY_CYCLE : stm32f1xx_hal_i2c.h , stm32f1xx_ll_i2c.c
  • IS_I2C_GENERAL_CALL : stm32f1xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32f1xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32f1xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32f1xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32f1xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32f1xx_hal_i2c.h
  • IS_IRDA_BAUDRATE : stm32f1xx_hal_irda.h
  • IS_IRDA_MODE : stm32f1xx_hal_irda.h
  • IS_IRDA_PARITY : stm32f1xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32f1xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32f1xx_hal_irda.h
  • IS_IWDG_PRESCALER : stm32f1xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32f1xx_hal_iwdg.h
  • IS_LL_ADC_DATA_ALIGN : stm32f1xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32f1xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32f1xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_MULTI_MASTER_SLAVE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_MULTI_MODE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32f1xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32f1xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_SCAN_SELECTION : stm32f1xx_ll_adc.c
  • IS_LL_ADC_SEQ_SCAN_MODE : stm32f1xx_ll_adc.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32f1xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32f1xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32f1xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32f1xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32f1xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32f1xx_ll_exti.c
  • IS_LL_GPIO_MODE : stm32f1xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32f1xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32f1xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32f1xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32f1xx_ll_gpio.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32f1xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32f1xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32f1xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32f1xx_ll_i2c.c
  • IS_LL_I2S_AUDIO_FREQ : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_CPOL : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_DATAFORMAT : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_MCLK_OUTPUT : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_MODE : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_PRESCALER_LINEAR : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_PRESCALER_PARITY : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_STANDARD : stm32f1xx_ll_i2s.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32f1xx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32f1xx_ll_rcc.c
  • IS_LL_SPI_BAUDRATE : stm32f1xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32f1xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32f1xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32f1xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32f1xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32f1xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32f1xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32f1xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32f1xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32f1xx_ll_spi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32f1xx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32f1xx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32f1xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32f1xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32f1xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32f1xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32f1xx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32f1xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32f1xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32f1xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32f1xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32f1xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32f1xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32f1xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32f1xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32f1xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32f1xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32f1xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32f1xx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_PLLMUL_VALUE : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_PREDIV_VALUE : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32f1xx_ll_utils.c
  • IS_NVIC_DEVICE_IRQ : stm32f1xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32f1xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32f1xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32f1xx_hal_cortex.h
  • IS_OB_DATA_ADDRESS : stm32f1xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32f1xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32f1xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32f1xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32f1xx_hal_flash_ex.h
  • IS_OB_WRP : stm32f1xx_hal_flash_ex.h
  • IS_OPTIONBYTE : stm32f1xx_hal_flash_ex.h
  • IS_PCD_ALL_INSTANCE : stm32f1xx_hal_pcd.h
  • IS_PWR_PVD_LEVEL : stm32f1xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32f1xx_hal_pwr.h
  • IS_PWR_REGULATOR : stm32f1xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32f1xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32f1xx_hal_pwr.h
  • IS_PWR_WAKEUP_PIN : stm32f1xx_hal_pwr.h
  • IS_RCC_ADCPLLCLK_DIV : stm32f1xx_hal_rcc_ex.h
  • IS_RCC_CALIBRATION_VALUE : stm32f1xx_hal_rcc.h
  • IS_RCC_CLOCKTYPE : stm32f1xx_hal_rcc.h
  • IS_RCC_HCLK : stm32f1xx_hal_rcc.h
  • IS_RCC_HSE : stm32f1xx_hal_rcc.h
  • IS_RCC_HSE_PREDIV : stm32f1xx_hal_rcc_ex.h
  • IS_RCC_HSI : stm32f1xx_hal_rcc.h
  • IS_RCC_LSE : stm32f1xx_hal_rcc.h
  • IS_RCC_LSI : stm32f1xx_hal_rcc.h
  • IS_RCC_MCO : stm32f1xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32f1xx_hal_rcc_ex.h
  • IS_RCC_MCODIV : stm32f1xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32f1xx_hal_rcc.h
  • IS_RCC_PCLK : stm32f1xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32f1xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32f1xx_hal_rcc.h
  • IS_RCC_PLL_MUL : stm32f1xx_hal_rcc_ex.h
  • IS_RCC_PLLSOURCE : stm32f1xx_hal_rcc.h
  • IS_RCC_RTCCLKSOURCE : stm32f1xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32f1xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE_STATUS : stm32f1xx_hal_rcc.h
  • IS_RCC_USBPLLCLK_DIV : stm32f1xx_hal_rcc_ex.h
  • IS_RTC_ALARM : stm32f1xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32f1xx_hal_rtc.h
  • IS_RTC_BKP : stm32f1xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32f1xx_hal_rtc.h
  • IS_RTC_DATE : stm32f1xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32f1xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32f1xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32f1xx_hal_rtc.h
  • IS_RTC_MONTH : stm32f1xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32f1xx_hal_rtc.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32f1xx_hal_rtc_ex.h
  • IS_RTC_TAMPER : stm32f1xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32f1xx_hal_rtc_ex.h
  • IS_RTC_YEAR : stm32f1xx_hal_rtc.h
  • IS_SMARTCARD_BAUDRATE : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_NACK_STATE : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_WORD_LENGTH : stm32f1xx_hal_smartcard.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32f1xx_hal_spi.h
  • IS_SPI_CPHA : stm32f1xx_hal_spi.h
  • IS_SPI_CPOL : stm32f1xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32f1xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32f1xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32f1xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32f1xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32f1xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32f1xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32f1xx_hal_spi.h
  • IS_SPI_MODE : stm32f1xx_hal_spi.h
  • IS_SPI_NSS : stm32f1xx_hal_spi.h
  • IS_SYSTICK_CLK_SOURCE : stm32f1xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32f1xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_CHANNELS : stm32f1xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32f1xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32f1xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32f1xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32f1xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32f1xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32f1xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32f1xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32f1xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32f1xx_hal_tim_ex.h
  • IS_TIM_DMA_BASE : stm32f1xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32f1xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32f1xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32f1xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32f1xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32f1xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32f1xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32f1xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32f1xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32f1xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_SLAVE_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32f1xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32f1xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32f1xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32f1xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32f1xx_hal_tim.h
  • IS_UART_ADDRESS : stm32f1xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32f1xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32f1xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32f1xx_hal_uart.h
  • IS_UART_LIN_OVERSAMPLING : stm32f1xx_hal_uart.h
  • IS_UART_LIN_WORD_LENGTH : stm32f1xx_hal_uart.h
  • IS_UART_MODE : stm32f1xx_hal_uart.h
  • IS_UART_PARITY : stm32f1xx_hal_uart.h
  • IS_UART_STATE : stm32f1xx_hal_uart.h
  • IS_UART_STOPBITS : stm32f1xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32f1xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32f1xx_hal_uart.h
  • IS_USART_BAUDRATE : stm32f1xx_hal_usart.h
  • IS_USART_CLOCK : stm32f1xx_hal_usart.h
  • IS_USART_LASTBIT : stm32f1xx_hal_usart.h
  • IS_USART_MODE : stm32f1xx_hal_usart.h
  • IS_USART_NACK_STATE : stm32f1xx_hal_usart.h
  • IS_USART_PARITY : stm32f1xx_hal_usart.h
  • IS_USART_PHASE : stm32f1xx_hal_usart.h
  • IS_USART_POLARITY : stm32f1xx_hal_usart.h
  • IS_USART_STOPBITS : stm32f1xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32f1xx_hal_usart.h
  • IS_WRPSTATE : stm32f1xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32f1xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32f1xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32f1xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32f1xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32f1xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32f1xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32f1xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32f1xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32f1xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32f1xx_hal_iwdg.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LL_ADC_AWD1 : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32f1xx_ll_adc.h
  • LL_ADC_ClearFlag_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32f1xx_ll_adc.c
  • LL_ADC_CommonInit() : stm32f1xx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32f1xx_ll_adc.c
  • LL_ADC_DATA_ALIGN_LEFT : stm32f1xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32f1xx_ll_adc.h
  • LL_ADC_DeInit() : stm32f1xx_ll_adc.c
  • LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES : stm32f1xx_ll_adc.h
  • LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES : stm32f1xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32f1xx_ll_adc.h
  • LL_ADC_Disable() : stm32f1xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32f1xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32f1xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI : stm32f1xx_ll_adc.h
  • LL_ADC_Enable() : stm32f1xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_MST : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_SLV : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_EOS_MST : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_EOS_SLV : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_MST : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_SLV : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_JSTRT : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_STRT : stm32f1xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32f1xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32f1xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32f1xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32f1xx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32f1xx_ll_adc.h
  • LL_ADC_GetMultimode() : stm32f1xx_ll_adc.h
  • LL_ADC_GetSequencersScanMode() : stm32f1xx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32f1xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32f1xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32f1xx_ll_adc.h
  • LL_ADC_Init() : stm32f1xx_ll_adc.c
  • LL_ADC_INJ_GetOffset() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32f1xx_ll_adc.c
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetOffset() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_StartConversionExtTrig() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_StartConversionSWStart() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_StopConversionExtTrig() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32f1xx_ll_adc.c
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32f1xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32f1xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32f1xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32f1xx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_ALTERN : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_SIMULT : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTERL_FAST : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTERL_SLOW : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIMULT : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_INDEPENDENT : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_MASTER : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_MASTER_SLAVE : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_SLAVE : stm32f1xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32f1xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32f1xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32f1xx_ll_adc.h
  • LL_ADC_ReadReg : stm32f1xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32f1xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32f1xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32f1xx_ll_adc.c
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_ReadMultiConversionData32() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_StartConversionExtTrig() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_StartConversionSWStart() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_StopConversionExtTrig() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32f1xx_ll_adc.c
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32f1xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_13CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_1CYCLE_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_239CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_28CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_41CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_55CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_71CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_7CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SEQ_SCAN_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_SEQ_SCAN_ENABLE : stm32f1xx_ll_adc.h
  • LL_ADC_SetAnalogWDMonitChannels() : stm32f1xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32f1xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32f1xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32f1xx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32f1xx_ll_adc.h
  • LL_ADC_SetMultimode() : stm32f1xx_ll_adc.h
  • LL_ADC_SetSequencersScanMode() : stm32f1xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32f1xx_ll_adc.h
  • LL_ADC_StructInit() : stm32f1xx_ll_adc.c
  • LL_ADC_WriteReg : stm32f1xx_ll_adc.h
  • LL_AHB1_GRP1_DisableClock() : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FLASH : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SDIO : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_BKP : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CAN1 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_PWR : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USB : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ADC1 : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ADC2 : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_AFIO : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_GPIOA : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_GPIOB : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_GPIOC : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_GPIOD : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_GPIOE : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32f1xx_ll_bus.h
  • LL_CPUID_GetConstant() : stm32f1xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32f1xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32f1xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32f1xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32f1xx_ll_cortex.h
  • LL_CRC_DeInit() : stm32f1xx_ll_crc.c
  • LL_CRC_FeedData32() : stm32f1xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32f1xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32f1xx_ll_crc.h
  • LL_CRC_ReadReg : stm32f1xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32f1xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32f1xx_ll_crc.h
  • LL_CRC_WriteReg : stm32f1xx_ll_crc.h
  • LL_DBGMCU_APB1_GRP1_CAN1_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32f1xx_ll_system.h
  • LL_DBGMCU_DisableDBGSleepMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_EnableDBGSleepMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32f1xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32f1xx_ll_system.h
  • LL_DBGMCU_GetTracePinAssignment() : stm32f1xx_ll_system.h
  • LL_DBGMCU_SetTracePinAssignment() : stm32f1xx_ll_system.h
  • LL_DBGMCU_TRACE_ASYNCH : stm32f1xx_ll_system.h
  • LL_DBGMCU_TRACE_NONE : stm32f1xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE1 : stm32f1xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE2 : stm32f1xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE4 : stm32f1xx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32f1xx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32f1xx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_7 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI1() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI7() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32f1xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32f1xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32f1xx_ll_dma.h
  • LL_DMA_DeInit() : stm32f1xx_ll_dma.c
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32f1xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32f1xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32f1xx_ll_dma.h
  • LL_DMA_DisableChannel() : stm32f1xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32f1xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32f1xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32f1xx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32f1xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32f1xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32f1xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32f1xx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32f1xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32f1xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32f1xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32f1xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32f1xx_ll_dma.h
  • LL_DMA_GetMode() : stm32f1xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32f1xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_Init() : stm32f1xx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI7() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32f1xx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32f1xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32f1xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32f1xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32f1xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32f1xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32f1xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32f1xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32f1xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32f1xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32f1xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32f1xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32f1xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32f1xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32f1xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32f1xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32f1xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32f1xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32f1xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32f1xx_ll_dma.h
  • LL_DMA_ReadReg : stm32f1xx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32f1xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32f1xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32f1xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32f1xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32f1xx_ll_dma.h
  • LL_DMA_SetMode() : stm32f1xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32f1xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32f1xx_ll_dma.h
  • LL_DMA_StructInit() : stm32f1xx_ll_dma.c
  • LL_DMA_WriteReg : stm32f1xx_ll_dma.h
  • LL_EXTI_ClearFlag_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32f1xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_Init() : stm32f1xx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_0 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32f1xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32f1xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32f1xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32f1xx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32f1xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32f1xx_ll_exti.c
  • LL_EXTI_TRIGGER_FALLING : stm32f1xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32f1xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32f1xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32f1xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32f1xx_ll_exti.h
  • LL_FLASH_DisableHalfCycleAccess() : stm32f1xx_ll_system.h
  • LL_FLASH_DisablePrefetch() : stm32f1xx_ll_system.h
  • LL_FLASH_EnableHalfCycleAccess() : stm32f1xx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32f1xx_ll_system.h
  • LL_FLASH_GetLatency() : stm32f1xx_ll_system.h
  • LL_FLASH_IsHalfCycleAccessEnabled() : stm32f1xx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32f1xx_ll_system.h
  • LL_FLASH_LATENCY_0 : stm32f1xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32f1xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32f1xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32f1xx_ll_system.h
  • LL_GetFlashSize() : stm32f1xx_ll_utils.h
  • LL_GetUID_Word0() : stm32f1xx_ll_utils.h
  • LL_GetUID_Word1() : stm32f1xx_ll_utils.h
  • LL_GetUID_Word2() : stm32f1xx_ll_utils.h
  • LL_GPIO_AF_ConfigEventout() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableEventout() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_I2C1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_PD01() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_SPI1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_SWJ() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_TIM1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_TIM2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_TIM3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_TIM4() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_USART1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_USART2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_USART3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableEventout() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_I2C1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_PD01() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_SPI1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_SWJ() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_TIM1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_TIM2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_TIM3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_TIM4() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_USART1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_USART2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_USART3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_0 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_1 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_10 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_11 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_12 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_13 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_14 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_15 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_2 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_3 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_4 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_5 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_6 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_7 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_8 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_9 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PORT_A : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PORT_B : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PORT_C : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PORT_D : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PORT_E : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE0 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE1 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE10 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE11 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE12 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE13 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE14 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE15 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE2 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE3 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE4 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE5 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE6 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE7 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE8 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE9 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTA : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTB : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTC : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTD : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTE : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTF : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTG : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_GetEXTISource() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_I2C1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_PD01() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_SPI1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_TIM4() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_USART1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_USART2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_Remap_SWJ_NOJTAG() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_Remap_SWJ_NONJTRST() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial1_CAN1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial1_TIM2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial2_CAN1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial2_TIM2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial3_CAN1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial_TIM1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial_TIM3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial_USART3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_SetEXTISource() : stm32f1xx_ll_gpio.h
  • LL_GPIO_DeInit() : stm32f1xx_ll_gpio.c
  • LL_GPIO_GetPinMode() : stm32f1xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32f1xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32f1xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32f1xx_ll_gpio.h
  • LL_GPIO_Init() : stm32f1xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32f1xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32f1xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32f1xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32f1xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_FLOATING : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT_10MHz : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT_2MHz : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT_50MHz : stm32f1xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32f1xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32f1xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32f1xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32f1xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32f1xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32f1xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32f1xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32f1xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32f1xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32f1xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32f1xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32f1xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32f1xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32f1xx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32f1xx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32f1xx_ll_cortex.h
  • LL_HANDLER_FAULT_BUS : stm32f1xx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32f1xx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32f1xx_ll_cortex.h
  • LL_I2C_ACK : stm32f1xx_ll_i2c.h
  • LL_I2C_AcknowledgeNextData() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_AF() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32f1xx_ll_i2c.h
  • LL_I2C_CLOCK_SPEED_FAST_MODE : stm32f1xx_ll_i2c.h
  • LL_I2C_CLOCK_SPEED_STANDARD_MODE : stm32f1xx_ll_i2c.h
  • LL_I2C_ConfigSpeed() : stm32f1xx_ll_i2c.h
  • LL_I2C_CR2_ITBUFEN : stm32f1xx_ll_i2c.h
  • LL_I2C_CR2_ITERREN : stm32f1xx_ll_i2c.h
  • LL_I2C_CR2_ITEVTEN : stm32f1xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32f1xx_ll_i2c.c
  • LL_I2C_DIRECTION_READ : stm32f1xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32f1xx_ll_i2c.h
  • LL_I2C_Disable() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableBitPOS() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableIT_BUF() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableIT_EVT() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableLastDMA() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableReset() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableSMBusPECCompare() : stm32f1xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32f1xx_ll_i2c.h
  • LL_I2C_DUTYCYCLE_16_9 : stm32f1xx_ll_i2c.h
  • LL_I2C_DUTYCYCLE_2 : stm32f1xx_ll_i2c.h
  • LL_I2C_Enable() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableBitPOS() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableIT_BUF() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableIT_EVT() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableLastDMA() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableReset() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32f1xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32f1xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetClockPeriod() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetClockSpeedMode() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetDutyCycle() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetPeriphClock() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetRiseTime() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32f1xx_ll_i2c.h
  • LL_I2C_Init() : stm32f1xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADD10() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ADDR() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_AF() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BTF() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_DUAL() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_GENCALL() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_MSL() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_SB() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_SMBDEFAULT() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_SMBHOST() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledBitPOS() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_BUF() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_EVT() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledLastDMA() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsResetEnabled() : stm32f1xx_ll_i2c.h
  • LL_I2C_MAX_SPEED_FAST : stm32f1xx_ll_i2c.h
  • LL_I2C_MAX_SPEED_STANDARD : stm32f1xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32f1xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32f1xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32f1xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32f1xx_ll_i2c.h
  • LL_I2C_NACK : stm32f1xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32f1xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32f1xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32f1xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetClockPeriod() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetClockSpeedMode() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetDutyCycle() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetPeriphClock() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetRiseTime() : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_ADD10 : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_ADDR : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_AF : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_ARLO : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_BERR : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_BTF : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_OVR : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_PECERR : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_RXNE : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_SB : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_SMALERT : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_STOPF : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_TIMEOUT : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_TXE : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_BUSY : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_DUALF : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_GENCALL : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_MSL : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_SMBDEFAULT : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_SMBHOST : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_TRA : stm32f1xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32f1xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32f1xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32f1xx_ll_i2c.h
  • LL_I2S_AUDIOFREQ_11K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_16K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_192K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_22K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_32K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_44K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_48K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_8K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_96K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_DEFAULT : stm32f1xx_ll_i2s.h
  • LL_I2S_ClearFlag_FRE() : stm32f1xx_ll_i2s.h
  • LL_I2S_ClearFlag_OVR() : stm32f1xx_ll_i2s.h
  • LL_I2S_ClearFlag_UDR() : stm32f1xx_ll_i2s.h
  • LL_I2S_ConfigPrescaler() : stm32f1xx_ll_i2s.c
  • LL_I2S_CR2_ERRIE : stm32f1xx_ll_i2s.h
  • LL_I2S_CR2_RXNEIE : stm32f1xx_ll_i2s.h
  • LL_I2S_CR2_TXEIE : stm32f1xx_ll_i2s.h
  • LL_I2S_DATAFORMAT_16B : stm32f1xx_ll_i2s.h
  • LL_I2S_DATAFORMAT_16B_EXTENDED : stm32f1xx_ll_i2s.h
  • LL_I2S_DATAFORMAT_24B : stm32f1xx_ll_i2s.h
  • LL_I2S_DATAFORMAT_32B : stm32f1xx_ll_i2s.h
  • LL_I2S_DeInit() : stm32f1xx_ll_i2s.c
  • LL_I2S_Disable() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableDMAReq_RX() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableDMAReq_TX() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableIT_ERR() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableIT_RXNE() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableIT_TXE() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableMasterClock() : stm32f1xx_ll_i2s.h
  • LL_I2S_Enable() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableDMAReq_RX() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableDMAReq_TX() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableIT_ERR() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableIT_RXNE() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableIT_TXE() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableMasterClock() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetClockPolarity() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetDataFormat() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetPrescalerLinear() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetPrescalerParity() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetStandard() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetTransferMode() : stm32f1xx_ll_i2s.h
  • LL_I2S_Init() : stm32f1xx_ll_i2s.c
  • LL_I2S_IsActiveFlag_BSY() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_CHSIDE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_FRE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_OVR() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_RXNE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_TXE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_UDR() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabled() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledDMAReq_RX() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledDMAReq_TX() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledIT_ERR() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledIT_RXNE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledIT_TXE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledMasterClock() : stm32f1xx_ll_i2s.h
  • LL_I2S_MCLK_OUTPUT_DISABLE : stm32f1xx_ll_i2s.h
  • LL_I2S_MCLK_OUTPUT_ENABLE : stm32f1xx_ll_i2s.h
  • LL_I2S_MODE_MASTER_RX : stm32f1xx_ll_i2s.h
  • LL_I2S_MODE_MASTER_TX : stm32f1xx_ll_i2s.h
  • LL_I2S_MODE_SLAVE_RX : stm32f1xx_ll_i2s.h
  • LL_I2S_MODE_SLAVE_TX : stm32f1xx_ll_i2s.h
  • LL_I2S_POLARITY_HIGH : stm32f1xx_ll_i2s.h
  • LL_I2S_POLARITY_LOW : stm32f1xx_ll_i2s.h
  • LL_I2S_PRESCALER_PARITY_EVEN : stm32f1xx_ll_i2s.h
  • LL_I2S_PRESCALER_PARITY_ODD : stm32f1xx_ll_i2s.h
  • LL_I2S_ReadReg : stm32f1xx_ll_i2s.h
  • LL_I2S_ReceiveData16() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetClockPolarity() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetDataFormat() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetPrescalerLinear() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetPrescalerParity() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetStandard() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetTransferMode() : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_BSY : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_FRE : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_OVR : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_RXNE : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_TXE : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_UDR : stm32f1xx_ll_i2s.h
  • LL_I2S_STANDARD_LSB : stm32f1xx_ll_i2s.h
  • LL_I2S_STANDARD_MSB : stm32f1xx_ll_i2s.h
  • LL_I2S_STANDARD_PCM_LONG : stm32f1xx_ll_i2s.h
  • LL_I2S_STANDARD_PCM_SHORT : stm32f1xx_ll_i2s.h
  • LL_I2S_STANDARD_PHILIPS : stm32f1xx_ll_i2s.h
  • LL_I2S_StructInit() : stm32f1xx_ll_i2s.c
  • LL_I2S_TransmitData16() : stm32f1xx_ll_i2s.h
  • LL_I2S_WriteReg : stm32f1xx_ll_i2s.h
  • LL_Init1msTick() : stm32f1xx_ll_utils.c
  • LL_InitTick() : stm32f1xx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_KEY_ENABLE : stm32f1xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32f1xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32f1xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32f1xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32f1xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32f1xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32f1xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32f1xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32f1xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32f1xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32f1xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32f1xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32f1xx_ll_cortex.h
  • LL_MAX_DELAY : stm32f1xx_ll_utils.h
  • LL_mDelay() : stm32f1xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSE() : stm32f1xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32f1xx_ll_utils.c
  • LL_PWR_ClearFlag_SB() : stm32f1xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32f1xx_ll_pwr.h
  • LL_PWR_CR_CSBF : stm32f1xx_ll_pwr.h
  • LL_PWR_CR_CWUF : stm32f1xx_ll_pwr.h
  • LL_PWR_CSR_EWUP1 : stm32f1xx_ll_pwr.h
  • LL_PWR_CSR_PVDO : stm32f1xx_ll_pwr.h
  • LL_PWR_CSR_SBF : stm32f1xx_ll_pwr.h
  • LL_PWR_CSR_WUF : stm32f1xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32f1xx_ll_pwr.c
  • LL_PWR_DisableBkUpAccess() : stm32f1xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32f1xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32f1xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32f1xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32f1xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32f1xx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32f1xx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32f1xx_ll_pwr.h
  • LL_PWR_GetRegulModeDS() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SB() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32f1xx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32f1xx_ll_pwr.h
  • LL_PWR_MODE_STOP_LPREGU : stm32f1xx_ll_pwr.h
  • LL_PWR_MODE_STOP_MAINREGU : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32f1xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32f1xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_LOW_POWER : stm32f1xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_MAIN : stm32f1xx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32f1xx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32f1xx_ll_pwr.h
  • LL_PWR_SetRegulModeDS() : stm32f1xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32f1xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32f1xx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32f1xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 : stm32f1xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 : stm32f1xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_CSSC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_CSSF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL2RDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL2RDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL2RDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL3RDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL3RDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL3RDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSECSS() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32f1xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_PORRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32f1xx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32f1xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32f1xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetRTCClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32f1xx_ll_rcc.c
  • LL_RCC_GetUSBClockFreq() : stm32f1xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PORRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32f1xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32f1xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32f1xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32f1xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32f1xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32f1xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_GetMultiplicator() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_GetPrediv() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_10 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_11 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_12 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_13 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_14 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_15 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_16 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_3 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_4 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_5 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_6 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_7 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_8 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_9 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32f1xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_1 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_1 : stm32f1xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32f1xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32f1xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV128 : stm32f1xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32f1xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32f1xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32f1xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32f1xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32f1xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32f1xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 : stm32f1xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32f1xx_ll_rcc.h
  • LL_SetSystemCoreClock() : stm32f1xx_ll_utils.c
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32f1xx_ll_spi.h
  • LL_SPI_ClearFlag_CRCERR() : stm32f1xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32f1xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32f1xx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32f1xx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32f1xx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32f1xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32f1xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32f1xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32f1xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32f1xx_ll_spi.h
  • LL_SPI_DeInit() : stm32f1xx_ll_spi.c
  • LL_SPI_Disable() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32f1xx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32f1xx_ll_spi.h
  • LL_SPI_Enable() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32f1xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32f1xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32f1xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32f1xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32f1xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32f1xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32f1xx_ll_spi.h
  • LL_SPI_GetMode() : stm32f1xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32f1xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32f1xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32f1xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32f1xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32f1xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32f1xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32f1xx_ll_spi.h
  • LL_SPI_Init() : stm32f1xx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32f1xx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32f1xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32f1xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32f1xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32f1xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32f1xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32f1xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32f1xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32f1xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32f1xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32f1xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32f1xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32f1xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32f1xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32f1xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32f1xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32f1xx_ll_spi.h
  • LL_SPI_ReadReg : stm32f1xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32f1xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32f1xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32f1xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32f1xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32f1xx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32f1xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32f1xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32f1xx_ll_spi.h
  • LL_SPI_SetMode() : stm32f1xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32f1xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32f1xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32f1xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32f1xx_ll_spi.h
  • LL_SPI_SR_BSY : stm32f1xx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32f1xx_ll_spi.h
  • LL_SPI_SR_FRE : stm32f1xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32f1xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32f1xx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32f1xx_ll_spi.h
  • LL_SPI_SR_TXE : stm32f1xx_ll_spi.h
  • LL_SPI_StructInit() : stm32f1xx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32f1xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32f1xx_ll_spi.h
  • LL_SPI_WriteReg : stm32f1xx_ll_spi.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_DisableIT() : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32f1xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32f1xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32f1xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32f1xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32f1xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_BDTR_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_BREAK_DISABLE : stm32f1xx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32f1xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32f1xx_ll_tim.h
  • LL_TIM_CC_DisableChannel() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32f1xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32f1xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32f1xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32f1xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32f1xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32f1xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32f1xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32f1xx_ll_tim.h
  • LL_TIM_DeInit() : stm32f1xx_ll_tim.c
  • LL_TIM_DIER_BIE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32f1xx_ll_tim.h
  • LL_TIM_DisableAllOutputs() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32f1xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32f1xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32f1xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32f1xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32f1xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32f1xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32f1xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32f1xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32f1xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32f1xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_IC_Config() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32f1xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32f1xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_ICPSC_DIV1 : stm32f1xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32f1xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32f1xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32f1xx_ll_tim.h
  • LL_TIM_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32f1xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32f1xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32f1xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32f1xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32f1xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_OCIDLESTATE_HIGH : stm32f1xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32f1xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32f1xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32f1xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32f1xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32f1xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32f1xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32f1xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32f1xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_ReadReg : stm32f1xx_ll_tim.h
  • LL_TIM_SetAutoReload() : stm32f1xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32f1xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32f1xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32f1xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32f1xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32f1xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32f1xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32f1xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32f1xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32f1xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32f1xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32f1xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32f1xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32f1xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32f1xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32f1xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32f1xx_ll_tim.h
  • LL_TIM_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_TRGO_CC1IF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32f1xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32f1xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32f1xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32f1xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32f1xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32f1xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32f1xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32f1xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32f1xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32f1xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32f1xx_ll_tim.h
  • LL_TIM_WriteReg : stm32f1xx_ll_tim.h
  • LL_USART_ClearFlag_FE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_RXNE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32f1xx_ll_usart.h
  • LL_USART_CLOCK_DISABLE : stm32f1xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32f1xx_ll_usart.h
  • LL_USART_ClockInit() : stm32f1xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32f1xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32f1xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32f1xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32f1xx_ll_usart.h
  • LL_USART_CR1_RXNEIE : stm32f1xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32f1xx_ll_usart.h
  • LL_USART_CR1_TXEIE : stm32f1xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32f1xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32f1xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32f1xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32f1xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32f1xx_ll_usart.h
  • LL_USART_DeInit() : stm32f1xx_ll_usart.c
  • LL_USART_DIRECTION_NONE : stm32f1xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32f1xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32f1xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32f1xx_ll_usart.h
  • LL_USART_Disable() : stm32f1xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32f1xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32f1xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32f1xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32f1xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_RXNE() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_TXE() : stm32f1xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32f1xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32f1xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32f1xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32f1xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32f1xx_ll_usart.h
  • LL_USART_Enable() : stm32f1xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32f1xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32f1xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32f1xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32f1xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_RXNE() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_TXE() : stm32f1xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32f1xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32f1xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32f1xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32f1xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32f1xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32f1xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32f1xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32f1xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32f1xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32f1xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32f1xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32f1xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32f1xx_ll_usart.h
  • LL_USART_GetParity() : stm32f1xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32f1xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32f1xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32f1xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32f1xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32f1xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32f1xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32f1xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32f1xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32f1xx_ll_usart.h
  • LL_USART_Init() : stm32f1xx_ll_usart.c
  • LL_USART_IRDA_POWER_LOW : stm32f1xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_FE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32f1xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32f1xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32f1xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32f1xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32f1xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32f1xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32f1xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32f1xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32f1xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32f1xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32f1xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32f1xx_ll_usart.h
  • LL_USART_ReadReg : stm32f1xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32f1xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32f1xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32f1xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32f1xx_ll_usart.h
  • LL_USART_RequestExitMuteMode() : stm32f1xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32f1xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32f1xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32f1xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32f1xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32f1xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32f1xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32f1xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32f1xx_ll_usart.h
  • LL_USART_SetNodeAddress() : stm32f1xx_ll_usart.h
  • LL_USART_SetParity() : stm32f1xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32f1xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32f1xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32f1xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32f1xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32f1xx_ll_usart.h
  • LL_USART_SR_CTS : stm32f1xx_ll_usart.h
  • LL_USART_SR_FE : stm32f1xx_ll_usart.h
  • LL_USART_SR_IDLE : stm32f1xx_ll_usart.h
  • LL_USART_SR_LBD : stm32f1xx_ll_usart.h
  • LL_USART_SR_NE : stm32f1xx_ll_usart.h
  • LL_USART_SR_ORE : stm32f1xx_ll_usart.h
  • LL_USART_SR_PE : stm32f1xx_ll_usart.h
  • LL_USART_SR_RXNE : stm32f1xx_ll_usart.h
  • LL_USART_SR_TC : stm32f1xx_ll_usart.h
  • LL_USART_SR_TXE : stm32f1xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32f1xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32f1xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32f1xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32f1xx_ll_usart.h
  • LL_USART_StructInit() : stm32f1xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32f1xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32f1xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32f1xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32f1xx_ll_usart.h
  • LL_USART_WriteReg : stm32f1xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32f1xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32f1xx_ll_utils.h
  • LL_WWDG_CFR_EWI : stm32f1xx_ll_wwdg.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32f1xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32f1xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32f1xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32f1xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32f1xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32f1xx_ll_wwdg.h
  • LPSDSR_BIT_NUMBER : stm32f1xx_hal_pwr.c
  • LSE_STARTUP_TIMEOUT : stm32f1xx_hal_conf.h
  • LSE_VALUE : stm32f1xx_ll_rcc.h , stm32f1xx_hal_conf.h
  • LSI_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • LSI_VALUE : stm32f1xx_hal_conf.h , stm32f1xx_ll_rcc.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
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  • Enumerations
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAC_ADDR0 : stm32f1xx_hal_conf.h
  • MAC_ADDR1 : stm32f1xx_hal_conf.h
  • MAC_ADDR2 : stm32f1xx_hal_conf.h
  • MAC_ADDR3 : stm32f1xx_hal_conf.h
  • MAC_ADDR4 : stm32f1xx_hal_conf.h
  • MAC_ADDR5 : stm32f1xx_hal_conf.h
  • MCO1_CLK_ENABLE : stm32f1xx_hal_rcc.c
  • MCO1_GPIO_PORT : stm32f1xx_hal_rcc.c
  • MCO1_PIN : stm32f1xx_hal_rcc.c
  • MSR_REGISTER_INDEX : stm32f1xx_hal_can.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
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  • b
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  • d
  • e
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NVIC_PRIORITYGROUP_0 : stm32f1xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32f1xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32f1xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32f1xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32f1xx_hal_cortex.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OB_DATA_ADDRESS_DATA0 : stm32f1xx_hal_flash_ex.h
  • OB_DATA_ADDRESS_DATA1 : stm32f1xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32f1xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32f1xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32f1xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32f1xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32f1xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32f1xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32f1xx_hal_flash_ex.h
  • OB_STOP_RST : stm32f1xx_hal_flash_ex.h
  • OB_WRP_ALLPAGES : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES0TO3 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES0TO31MASK : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES100TO103 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES104TO107 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES108TO111 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES112TO115 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES116TO119 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES120TO123 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES124TO127 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES12TO15 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES16TO19 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES20TO23 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES24TO27 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES28TO31 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES32TO35 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES32TO63MASK : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES36TO39 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES40TO43 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES44TO47 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES48TO51 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES4TO7 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES52TO55 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES56TO59 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES60TO63 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES64TO67 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES64TO95MASK : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES68TO71 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES72TO75 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES76TO79 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES80TO83 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES84TO87 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES88TO91 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES8TO11 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES92TO95 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES96TO127MASK : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES96TO99 : stm32f1xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32f1xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32f1xx_hal_flash_ex.h
  • OBR_REG_INDEX : stm32f1xx_hal_flash_ex.h
  • OC1Config() : stm32f1xx_ll_tim.c
  • OC2Config() : stm32f1xx_ll_tim.c
  • OC3Config() : stm32f1xx_ll_tim.c
  • OC4Config() : stm32f1xx_ll_tim.c
  • OFFSET_TAB_CCMRx : stm32f1xx_ll_tim.h
  • OPTIONBYTE_DATA : stm32f1xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32f1xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32f1xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32f1xx_hal_flash_ex.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
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  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • PCD_CALC_BLK2 : stm32f1xx_hal_pcd.h
  • PCD_CALC_BLK32 : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_EP_DBUF : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_EP_KIND : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_OUT_STATUS : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_RX_DTOG : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_RX_EP_CTR : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_TX_DTOG : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_TX_EP_CTR : stm32f1xx_hal_pcd.h
  • PCD_DBL_BUF : stm32f1xx_hal_pcd.h
  • PCD_ENDP0 : stm32f1xx_hal_pcd.h
  • PCD_ENDP1 : stm32f1xx_hal_pcd.h
  • PCD_ENDP2 : stm32f1xx_hal_pcd.h
  • PCD_ENDP3 : stm32f1xx_hal_pcd.h
  • PCD_ENDP4 : stm32f1xx_hal_pcd.h
  • PCD_ENDP5 : stm32f1xx_hal_pcd.h
  • PCD_ENDP6 : stm32f1xx_hal_pcd.h
  • PCD_ENDP7 : stm32f1xx_hal_pcd.h
  • PCD_EP0MPS_08 : stm32f1xx_hal_pcd.h
  • PCD_EP0MPS_16 : stm32f1xx_hal_pcd.h
  • PCD_EP0MPS_32 : stm32f1xx_hal_pcd.h
  • PCD_EP0MPS_64 : stm32f1xx_hal_pcd.h
  • PCD_EP_BUF0 : stm32f1xx_hal_pcd.h
  • PCD_EP_BUF1 : stm32f1xx_hal_pcd.h
  • PCD_EP_BUF_NUM : stm32f1xx_hal_pcd.h
  • PCD_EP_DBUF_DIR : stm32f1xx_hal_pcd.h
  • PCD_EP_DBUF_ERR : stm32f1xx_hal_pcd.h
  • PCD_EP_DBUF_IN : stm32f1xx_hal_pcd.h
  • PCD_EP_DBUF_OUT : stm32f1xx_hal_pcd.h
  • PCD_EP_ISR_Handler() : stm32f1xx_hal_pcd.c
  • PCD_EP_NOBUF : stm32f1xx_hal_pcd.h
  • PCD_EP_RX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_EP_RX_CNT : stm32f1xx_hal_pcd.h
  • PCD_EP_TX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_EP_TX_CNT : stm32f1xx_hal_pcd.h
  • PCD_EPTypeDef : stm32f1xx_hal_pcd.h
  • PCD_FreeUserBuffer : stm32f1xx_hal_pcd.h
  • PCD_GET_DB_DIR : stm32f1xx_hal_pcd.h
  • PCD_GET_ENDPOINT : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_ADDR : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_CNT : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_ADDR : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_CNT : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_RX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_RX_CNT : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_RX_STALL_STATUS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_RX_STATUS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_TX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_TX_CNT : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_TX_STALL_STATUS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_TX_STATUS : stm32f1xx_hal_pcd.h
  • PCD_GET_EPTYPE : stm32f1xx_hal_pcd.h
  • PCD_InitTypeDef : stm32f1xx_hal_pcd.h
  • PCD_MAX : stm32f1xx_hal_pcd.c
  • PCD_MIN : stm32f1xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32f1xx_hal_pcd.h
  • PCD_RX_DTOG : stm32f1xx_hal_pcd.h
  • PCD_SET_ENDPOINT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_CNT_RX_REG : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_ADDR : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_ADDR : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF_ADDR : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_KIND : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_RX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_RX_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_RX_DBUF0_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_RX_STATUS : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_RX_VALID : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_TX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_TX_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_TX_STATUS : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_TX_VALID : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_TXRX_STATUS : stm32f1xx_hal_pcd.h
  • PCD_SET_EPTYPE : stm32f1xx_hal_pcd.h
  • PCD_SET_OUT_STATUS : stm32f1xx_hal_pcd.h
  • PCD_SNG_BUF : stm32f1xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32f1xx_hal_pcd.h
  • PCD_SPEED_HIGH : stm32f1xx_hal_pcd.h
  • PCD_SPEED_HIGH_IN_FULL : stm32f1xx_hal_pcd.h
  • PCD_StateTypeDef : stm32f1xx_hal_pcd.h
  • PCD_TX_DTOG : stm32f1xx_hal_pcd.h
  • PCD_TypeDef : stm32f1xx_hal_pcd.h
  • pFlash : stm32f1xx_hal_flash.c , stm32f1xx_hal_flash_ex.c
  • PHY_AUTONEGO_COMPLETE : stm32f1xx_hal_conf.h
  • PHY_AUTONEGOTIATION : stm32f1xx_hal_conf.h
  • PHY_BCR : stm32f1xx_hal_conf.h
  • PHY_BSR : stm32f1xx_hal_conf.h
  • PHY_CONFIG_DELAY : stm32f1xx_hal_conf.h
  • PHY_DUPLEX_STATUS : stm32f1xx_hal_conf.h
  • PHY_FULLDUPLEX_100M : stm32f1xx_hal_conf.h
  • PHY_FULLDUPLEX_10M : stm32f1xx_hal_conf.h
  • PHY_HALFDUPLEX_100M : stm32f1xx_hal_conf.h
  • PHY_HALFDUPLEX_10M : stm32f1xx_hal_conf.h
  • PHY_ISOLATE : stm32f1xx_hal_conf.h
  • PHY_JABBER_DETECTION : stm32f1xx_hal_conf.h
  • PHY_LINK_INTERRUPT : stm32f1xx_hal_conf.h
  • PHY_LINK_STATUS : stm32f1xx_hal_conf.h
  • PHY_LINKED_STATUS : stm32f1xx_hal_conf.h
  • PHY_LOOPBACK : stm32f1xx_hal_conf.h
  • PHY_MICR : stm32f1xx_hal_conf.h
  • PHY_MICR_INT_EN : stm32f1xx_hal_conf.h
  • PHY_MICR_INT_OE : stm32f1xx_hal_conf.h
  • PHY_MISR : stm32f1xx_hal_conf.h
  • PHY_MISR_LINK_INT_EN : stm32f1xx_hal_conf.h
  • PHY_POWERDOWN : stm32f1xx_hal_conf.h
  • PHY_READ_TO : stm32f1xx_hal_conf.h
  • PHY_RESET : stm32f1xx_hal_conf.h
  • PHY_RESET_DELAY : stm32f1xx_hal_conf.h
  • PHY_RESTART_AUTONEGOTIATION : stm32f1xx_hal_conf.h
  • PHY_SPEED_STATUS : stm32f1xx_hal_conf.h
  • PHY_SR : stm32f1xx_hal_conf.h
  • PHY_WRITE_TO : stm32f1xx_hal_conf.h
  • PLL_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • PREFETCH_ENABLE : stm32f1xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32f1xx_hal_pwr.c
  • PVD_MODE_EVT : stm32f1xx_hal_pwr.c
  • PVD_MODE_IT : stm32f1xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32f1xx_hal_pwr.c
  • PVDE_BIT_NUMBER : stm32f1xx_hal_pwr.c
  • PWR_CR_OFFSET : stm32f1xx_hal_pwr.c
  • PWR_CR_OFFSET_BB : stm32f1xx_hal_pwr.c
  • PWR_CSR_OFFSET : stm32f1xx_hal_pwr.c
  • PWR_CSR_OFFSET_BB : stm32f1xx_hal_pwr.c
  • PWR_EXTI_LINE_PVD : stm32f1xx_hal_pwr.h
  • PWR_FLAG_PVDO : stm32f1xx_hal_pwr.h
  • PWR_FLAG_SB : stm32f1xx_hal_pwr.h
  • PWR_FLAG_WU : stm32f1xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32f1xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32f1xx_hal_pwr.h
  • PWR_OFFSET : stm32f1xx_hal_pwr.c
  • PWR_OverloadWfe() : stm32f1xx_hal_pwr.c
  • PWR_PVD_MODE_EVENT_FALLING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32f1xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFE : stm32f1xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32f1xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32f1xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32f1xx_hal_pwr.h
  • PWR_WAKEUP_PIN1 : stm32f1xx_hal_pwr.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RCC_ADCPCLK2_DIV2 : stm32f1xx_hal_rcc_ex.h
  • RCC_ADCPCLK2_DIV4 : stm32f1xx_hal_rcc_ex.h
  • RCC_ADCPCLK2_DIV6 : stm32f1xx_hal_rcc_ex.h
  • RCC_ADCPCLK2_DIV8 : stm32f1xx_hal_rcc_ex.h
  • RCC_BDCR_BDRST_BB : stm32f1xx_hal_rcc.h
  • RCC_BDCR_LSEBYP_BB : stm32f1xx_hal_rcc.h
  • RCC_BDCR_LSEON_BB : stm32f1xx_hal_rcc.h
  • RCC_BDCR_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_BDCR_OFFSET_BB : stm32f1xx_hal_rcc.h
  • RCC_BDCR_RTCEN_BB : stm32f1xx_hal_rcc.h
  • RCC_BDRST_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_CFGR_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_CFGR_OFFSET_BB : stm32f1xx_hal_rcc.h
  • RCC_CIR_BYTE1_ADDRESS : stm32f1xx_hal_rcc.h
  • RCC_CIR_BYTE2_ADDRESS : stm32f1xx_hal_rcc.h
  • RCC_CIR_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_CIR_OFFSET_BB : stm32f1xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32f1xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32f1xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32f1xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32f1xx_hal_rcc.h
  • RCC_CR_BYTE2_ADDRESS : stm32f1xx_hal_rcc.h
  • RCC_CR_CSSON_BB : stm32f1xx_hal_rcc.h
  • RCC_CR_HSEON_BB : stm32f1xx_hal_rcc.h
  • RCC_CR_HSION_BB : stm32f1xx_hal_rcc.h
  • RCC_CR_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_CR_OFFSET_BB : stm32f1xx_hal_rcc.h
  • RCC_CR_PLLON_BB : stm32f1xx_hal_rcc.h
  • RCC_CSR_LSION_BB : stm32f1xx_hal_rcc.h
  • RCC_CSR_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_CSR_OFFSET_BB : stm32f1xx_hal_rcc.h
  • RCC_CSR_RMVF_BB : stm32f1xx_hal_rcc.h
  • RCC_CSSON_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32f1xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32f1xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32f1xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32f1xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32f1xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32f1xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32f1xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32f1xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32f1xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32f1xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32f1xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32f1xx_hal_rcc.h
  • RCC_GetHCLKClockFreq() : stm32f1xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32f1xx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32f1xx_ll_rcc.c
  • RCC_GetSystemClockFreq() : stm32f1xx_ll_rcc.c
  • RCC_HCLK_DIV1 : stm32f1xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32f1xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32f1xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32f1xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32f1xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32f1xx_hal_rcc.h
  • RCC_HSE_OFF : stm32f1xx_hal_rcc.h
  • RCC_HSE_ON : stm32f1xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV1 : stm32f1xx_hal_rcc_ex.h
  • RCC_HSE_PREDIV_DIV2 : stm32f1xx_hal_rcc_ex.h
  • RCC_HSEON_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_HSI_OFF : stm32f1xx_hal_rcc.h
  • RCC_HSI_ON : stm32f1xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32f1xx_hal_rcc.h
  • RCC_HSION_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_IT_CSS : stm32f1xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32f1xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32f1xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32f1xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32f1xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32f1xx_hal_rcc.h
  • RCC_LSE_BYPASS : stm32f1xx_hal_rcc.h
  • RCC_LSE_OFF : stm32f1xx_hal_rcc.h
  • RCC_LSE_ON : stm32f1xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • RCC_LSEBYP_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_LSEON_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_LSI_OFF : stm32f1xx_hal_rcc.h
  • RCC_LSI_ON : stm32f1xx_hal_rcc.h
  • RCC_LSION_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_MCO : stm32f1xx_hal_rcc.h
  • RCC_MCO1 : stm32f1xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32f1xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_HSI : stm32f1xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32f1xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_PLLCLK : stm32f1xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_SYSCLK : stm32f1xx_hal_rcc_ex.h
  • RCC_MCODIV_1 : stm32f1xx_hal_rcc.h
  • RCC_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32f1xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32f1xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32f1xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32f1xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32f1xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC : stm32f1xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32f1xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_GetFreqDomain_SYS() : stm32f1xx_ll_rcc.c
  • RCC_PLL_MUL10 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL11 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL12 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL13 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL14 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL15 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL16 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL2 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL3 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL4 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL5 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL6 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL7 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL8 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL9 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32f1xx_hal_rcc.h
  • RCC_PLL_OFF : stm32f1xx_hal_rcc.h
  • RCC_PLL_ON : stm32f1xx_hal_rcc.h
  • RCC_PLLON_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32f1xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI_DIV2 : stm32f1xx_hal_rcc.h
  • RCC_RMVF_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV128 : stm32f1xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32f1xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32f1xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NO_CLK : stm32f1xx_hal_rcc.h
  • RCC_RTCEN_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV1 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32f1xx_hal_rcc.h
  • RCC_USBCLKSOURCE_PLL : stm32f1xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL_DIV1_5 : stm32f1xx_hal_rcc_ex.h
  • RF0R_REGISTER_INDEX : stm32f1xx_hal_can.h
  • RF1R_REGISTER_INDEX : stm32f1xx_hal_can.h
  • RISING_EDGE : stm32f1xx_hal_gpio.c
  • RTC_ALARM_A : stm32f1xx_hal_rtc.h
  • RTC_ALARM_RESETVALUE : stm32f1xx_hal_rtc.c
  • RTC_ALARM_RESETVALUE_REGISTER : stm32f1xx_hal_rtc.c
  • RTC_AUTO_1_SECOND : stm32f1xx_hal_rtc.h
  • RTC_Bcd2ToByte() : stm32f1xx_hal_rtc.c
  • RTC_BKP_DR1 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32f1xx_hal_rtc_ex.h
  • RTC_ByteToBcd2() : stm32f1xx_hal_rtc.c
  • RTC_DateUpdate() : stm32f1xx_hal_rtc.c
  • RTC_EnterInitMode() : stm32f1xx_hal_rtc.c
  • RTC_ExitInitMode() : stm32f1xx_hal_rtc.c
  • RTC_EXTI_LINE_ALARM_EVENT : stm32f1xx_hal_rtc.h
  • RTC_FLAG_ALRAF : stm32f1xx_hal_rtc.h
  • RTC_FLAG_OW : stm32f1xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32f1xx_hal_rtc.h
  • RTC_FLAG_RTOFF : stm32f1xx_hal_rtc.h
  • RTC_FLAG_SEC : stm32f1xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32f1xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32f1xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32f1xx_hal_rtc.h
  • RTC_IsLeapYear() : stm32f1xx_hal_rtc.c
  • RTC_IT_ALRA : stm32f1xx_hal_rtc.h
  • RTC_IT_OW : stm32f1xx_hal_rtc.h
  • RTC_IT_SEC : stm32f1xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32f1xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32f1xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32f1xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32f1xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32f1xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32f1xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32f1xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32f1xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32f1xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32f1xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32f1xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32f1xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32f1xx_hal_rtc.h
  • RTC_OUTPUTSOURCE_ALARM : stm32f1xx_hal_rtc.h
  • RTC_OUTPUTSOURCE_CALIBCLOCK : stm32f1xx_hal_rtc.h
  • RTC_OUTPUTSOURCE_NONE : stm32f1xx_hal_rtc.h
  • RTC_OUTPUTSOURCE_SECOND : stm32f1xx_hal_rtc.h
  • RTC_ReadAlarmCounter() : stm32f1xx_hal_rtc.c
  • RTC_ReadTimeCounter() : stm32f1xx_hal_rtc.c
  • RTC_TAMPER_1 : stm32f1xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32f1xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32f1xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_FRIDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32f1xx_hal_rtc.h
  • RTC_WeekDayNum() : stm32f1xx_hal_rtc.c
  • RTC_WriteAlarmCounter() : stm32f1xx_hal_rtc.c
  • RTC_WriteTimeCounter() : stm32f1xx_hal_rtc.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • SHIFT_TAB_CCxP : stm32f1xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32f1xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32f1xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32f1xx_ll_tim.h
  • SMARTCARD_BRR : stm32f1xx_hal_smartcard.h
  • SMARTCARD_CR1_REG_INDEX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_CR3_REG_INDEX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DIV : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DIVFRAQ : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DIVMANT : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DMAAbortOnError() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMAREQ_RX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DMAREQ_TX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DMARxAbortCallback() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_FLAG_FE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_IDLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_NE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_ORE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_PE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_RXNE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_TC : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_TXE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_ERR : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_IDLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_MASK : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_PE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_RXNE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_TC : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_TXE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_DISABLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32f1xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV10 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV12 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV14 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV16 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV18 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV2 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV20 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV22 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV24 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV26 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV28 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV30 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV32 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV34 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV36 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV38 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV4 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV40 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV42 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV44 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV46 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV48 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV50 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV52 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV54 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV56 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV58 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV6 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV60 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV62 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV8 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_Receive_IT() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_STOPBITS_0_5 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_Transmit_IT() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_WORDLENGTH_9B : stm32f1xx_hal_smartcard.h
  • SPI_1LINE_RX : stm32f1xx_hal_spi.h
  • SPI_1LINE_TX : stm32f1xx_hal_spi.h
  • SPI_2linesRxISR_16BIT() : stm32f1xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32f1xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32f1xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32f1xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32f1xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32f1xx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32f1xx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32f1xx_hal_spi.c
  • SPI_BAUDRATEPRESCALER_128 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32f1xx_hal_spi.h
  • SPI_CheckFlag_BSY() : stm32f1xx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32f1xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32f1xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32f1xx_hal_spi.c
  • SPI_CR1_CLEAR_MASK : stm32f1xx_ll_spi.c
  • SPI_CRCCALCULATION_DISABLE : stm32f1xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32f1xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32f1xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32f1xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32f1xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32f1xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32f1xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32f1xx_hal_spi.h
  • SPI_DMAAbortOnError() : stm32f1xx_hal_spi.c
  • SPI_DMAError() : stm32f1xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32f1xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32f1xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32f1xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32f1xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32f1xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32f1xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32f1xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32f1xx_hal_spi.c
  • SPI_FIRSTBIT_LSB : stm32f1xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32f1xx_hal_spi.h
  • SPI_FLAG_BSY : stm32f1xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32f1xx_hal_spi.h
  • SPI_FLAG_MODF : stm32f1xx_hal_spi.h
  • SPI_FLAG_OVR : stm32f1xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32f1xx_hal_spi.h
  • SPI_FLAG_TXE : stm32f1xx_hal_spi.h
  • SPI_HandleTypeDef : stm32f1xx_hal_spi.h
  • SPI_INVALID_CRC_ERROR : stm32f1xx_hal_spi.h
  • SPI_ISCRCErrorValid() : stm32f1xx_hal_spi.c , stm32f1xx_hal_spi.h
  • SPI_IT_ERR : stm32f1xx_hal_spi.h
  • SPI_IT_RXNE : stm32f1xx_hal_spi.h
  • SPI_IT_TXE : stm32f1xx_hal_spi.h
  • SPI_MODE_MASTER : stm32f1xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32f1xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32f1xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32f1xx_hal_spi.h
  • SPI_NSS_SOFT : stm32f1xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32f1xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32f1xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32f1xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32f1xx_hal_spi.h
  • SPI_RESET_CRC : stm32f1xx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32f1xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32f1xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32f1xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32f1xx_hal_spi.c
  • SPI_TIMODE_DISABLE : stm32f1xx_hal_spi.h
  • SPI_TxISR_16BIT() : stm32f1xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32f1xx_hal_spi.c
  • SPI_VALID_CRC_ERROR : stm32f1xx_hal_spi.h
  • SPI_WaitFlagStateUntilTimeout() : stm32f1xx_hal_spi.c
  • SR_FLAG_MASK : stm32f1xx_hal_flash_ex.h
  • SYSTICK_CLKSOURCE_HCLK : stm32f1xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f1xx_hal_cortex.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TICK_INT_PRIORITY : stm32f1xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32f1xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32f1xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32f1xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32f1xx_hal_tim.h
  • TIM_Base_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_BREAK_DISABLE : stm32f1xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32f1xx_hal_tim.h
  • TIM_BREAKPOLARITY_HIGH : stm32f1xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32f1xx_hal_tim.h
  • TIM_CALC_DTS : stm32f1xx_ll_tim.h
  • TIM_CCER_CCxE_MASK : stm32f1xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32f1xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32f1xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32f1xx_hal_tim.h
  • TIM_CCxChannelCmd() : stm32f1xx_hal_tim.c
  • TIM_CCxN_DISABLE : stm32f1xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32f1xx_hal_tim.h
  • TIM_CCxNChannelCmd() : stm32f1xx_hal_tim_ex.c
  • TIM_CHANNEL_1 : stm32f1xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32f1xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32f1xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32f1xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32f1xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32f1xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32f1xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32f1xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32f1xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32f1xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32f1xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32f1xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32f1xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32f1xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32f1xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32f1xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32f1xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32f1xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32f1xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32f1xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32f1xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32f1xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32f1xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32f1xx_hal_tim.h
  • TIM_DMA_CC1 : stm32f1xx_hal_tim.h
  • TIM_DMA_CC2 : stm32f1xx_hal_tim.h
  • TIM_DMA_CC3 : stm32f1xx_hal_tim.h
  • TIM_DMA_CC4 : stm32f1xx_hal_tim.h
  • TIM_DMA_COM : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32f1xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32f1xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32f1xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32f1xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_SR : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMACaptureCplt() : stm32f1xx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32f1xx_hal_tim.c
  • TIM_DMAError() : stm32f1xx_hal_tim.c
  • TIM_DMAPeriodElapsedCplt() : stm32f1xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32f1xx_hal_tim.c
  • TIM_ENCODERMODE_TI1 : stm32f1xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32f1xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32f1xx_hal_tim.h
  • TIM_ETR_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_ETRPOLARITY_INVERTED : stm32f1xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32f1xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32f1xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32f1xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32f1xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32f1xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32f1xx_hal_tim.h
  • TIM_FLAG_COM : stm32f1xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32f1xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32f1xx_ll_tim.h
  • TIM_ICPOLARITY_FALLING : stm32f1xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32f1xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32f1xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32f1xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32f1xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32f1xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32f1xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32f1xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32f1xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32f1xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32f1xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32f1xx_hal_tim.h
  • TIM_IT_BREAK : stm32f1xx_hal_tim.h
  • TIM_IT_CC1 : stm32f1xx_hal_tim.h
  • TIM_IT_CC2 : stm32f1xx_hal_tim.h
  • TIM_IT_CC3 : stm32f1xx_hal_tim.h
  • TIM_IT_CC4 : stm32f1xx_hal_tim.h
  • TIM_IT_COM : stm32f1xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_IT_UPDATE : stm32f1xx_hal_tim.h
  • TIM_ITRx_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_LOCKLEVEL_1 : stm32f1xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32f1xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32f1xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32f1xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32f1xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32f1xx_hal_tim.h
  • TIM_OC1_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_OCFAST_DISABLE : stm32f1xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32f1xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32f1xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32f1xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32f1xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32f1xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32f1xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32f1xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32f1xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32f1xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32f1xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32f1xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32f1xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32f1xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32f1xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32f1xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32f1xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32f1xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32f1xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32f1xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32f1xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32f1xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32f1xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32f1xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32f1xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32f1xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32f1xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32f1xx_hal_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32f1xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32f1xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32f1xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32f1xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32f1xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32f1xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32f1xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32f1xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_SlaveTimer_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32f1xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_TI1SELECTION_CH1 : stm32f1xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32f1xx_hal_tim.h
  • TIM_TI2_ConfigInputStage() : stm32f1xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_TRGO_ENABLE : stm32f1xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32f1xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32f1xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32f1xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32f1xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32f1xx_hal_tim.h
  • TIM_TRGO_RESET : stm32f1xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32f1xx_hal_tim.h
  • TIM_TS_ETRF : stm32f1xx_hal_tim.h
  • TIM_TS_ITR0 : stm32f1xx_hal_tim.h
  • TIM_TS_ITR1 : stm32f1xx_hal_tim.h
  • TIM_TS_ITR2 : stm32f1xx_hal_tim.h
  • TIM_TS_ITR3 : stm32f1xx_hal_tim.h
  • TIM_TS_NONE : stm32f1xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32f1xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32f1xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32f1xx_hal_tim.h
  • TIMEx_DMACommutationCplt() : stm32f1xx_hal_tim_ex.h , stm32f1xx_hal_tim_ex.c
  • TSR_REGISTER_INDEX : stm32f1xx_hal_can.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_BRR_SAMPLING16 : stm32f1xx_hal_uart.h
  • UART_BRR_SAMPLING8 : stm32f1xx_hal_uart.h
  • UART_CR1_REG_INDEX : stm32f1xx_hal_uart.h
  • UART_CR2_REG_INDEX : stm32f1xx_hal_uart.h
  • UART_CR3_REG_INDEX : stm32f1xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32f1xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32f1xx_hal_uart.h
  • UART_DIVFRAQ_SAMPLING16 : stm32f1xx_hal_uart.h
  • UART_DIVFRAQ_SAMPLING8 : stm32f1xx_hal_uart.h
  • UART_DIVMANT_SAMPLING16 : stm32f1xx_hal_uart.h
  • UART_DIVMANT_SAMPLING8 : stm32f1xx_hal_uart.h
  • UART_DMAAbortOnError() : stm32f1xx_hal_uart.c
  • UART_DMAError() : stm32f1xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32f1xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32f1xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32f1xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32f1xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32f1xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32f1xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32f1xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32f1xx_hal_uart.c
  • UART_EndRxTransfer() : stm32f1xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32f1xx_hal_uart.c
  • UART_EndTxTransfer() : stm32f1xx_hal_uart.c
  • UART_FLAG_CTS : stm32f1xx_hal_uart.h
  • UART_FLAG_FE : stm32f1xx_hal_uart.h
  • UART_FLAG_IDLE : stm32f1xx_hal_uart.h
  • UART_FLAG_LBD : stm32f1xx_hal_uart.h
  • UART_FLAG_NE : stm32f1xx_hal_uart.h
  • UART_FLAG_ORE : stm32f1xx_hal_uart.h
  • UART_FLAG_PE : stm32f1xx_hal_uart.h
  • UART_FLAG_RXNE : stm32f1xx_hal_uart.h
  • UART_FLAG_TC : stm32f1xx_hal_uart.h
  • UART_FLAG_TXE : stm32f1xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32f1xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32f1xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32f1xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32f1xx_hal_uart.h
  • UART_IT_CTS : stm32f1xx_hal_uart.h
  • UART_IT_ERR : stm32f1xx_hal_uart.h
  • UART_IT_IDLE : stm32f1xx_hal_uart.h
  • UART_IT_LBD : stm32f1xx_hal_uart.h
  • UART_IT_MASK : stm32f1xx_hal_uart.h
  • UART_IT_PE : stm32f1xx_hal_uart.h
  • UART_IT_RXNE : stm32f1xx_hal_uart.h
  • UART_IT_TC : stm32f1xx_hal_uart.h
  • UART_IT_TXE : stm32f1xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32f1xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32f1xx_hal_uart.h
  • UART_MODE_RX : stm32f1xx_hal_uart.h
  • UART_MODE_TX : stm32f1xx_hal_uart.h
  • UART_MODE_TX_RX : stm32f1xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32f1xx_hal_uart.h
  • UART_PARITY_EVEN : stm32f1xx_hal_uart.h
  • UART_PARITY_NONE : stm32f1xx_hal_uart.h
  • UART_PARITY_ODD : stm32f1xx_hal_uart.h
  • UART_Receive_IT() : stm32f1xx_hal_uart.c
  • UART_SetConfig() : stm32f1xx_hal_uart.c
  • UART_STATE_DISABLE : stm32f1xx_hal_uart.h
  • UART_STATE_ENABLE : stm32f1xx_hal_uart.h
  • UART_STOPBITS_1 : stm32f1xx_hal_uart.h
  • UART_STOPBITS_2 : stm32f1xx_hal_uart.h
  • UART_Transmit_IT() : stm32f1xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32f1xx_hal_uart.c
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32f1xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32f1xx_hal_uart.h
  • UART_WORDLENGTH_8B : stm32f1xx_hal_uart.h
  • UART_WORDLENGTH_9B : stm32f1xx_hal_uart.h
  • uCRCErrorWorkaroundCheck : stm32f1xx_hal_spi_ex.c
  • UID_BASE_ADDRESS : stm32f1xx_ll_utils.h
  • USART_BRR : stm32f1xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32f1xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32f1xx_hal_usart.h
  • USART_CR1_REG_INDEX : stm32f1xx_hal_usart.h
  • USART_CR2_REG_INDEX : stm32f1xx_hal_usart.h
  • USART_CR3_REG_INDEX : stm32f1xx_hal_usart.h
  • USART_DIV : stm32f1xx_hal_usart.h
  • USART_DIVFRAQ : stm32f1xx_hal_usart.h
  • USART_DIVMANT : stm32f1xx_hal_usart.h
  • USART_DMAAbortOnError() : stm32f1xx_hal_usart.c
  • USART_DMAError() : stm32f1xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32f1xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32f1xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32f1xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32f1xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32f1xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32f1xx_hal_usart.c
  • USART_EndRxTransfer() : stm32f1xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32f1xx_hal_usart.c
  • USART_EndTxTransfer() : stm32f1xx_hal_usart.c
  • USART_FLAG_FE : stm32f1xx_hal_usart.h
  • USART_FLAG_IDLE : stm32f1xx_hal_usart.h
  • USART_FLAG_NE : stm32f1xx_hal_usart.h
  • USART_FLAG_ORE : stm32f1xx_hal_usart.h
  • USART_FLAG_PE : stm32f1xx_hal_usart.h
  • USART_FLAG_RXNE : stm32f1xx_hal_usart.h
  • USART_FLAG_TC : stm32f1xx_hal_usart.h
  • USART_FLAG_TXE : stm32f1xx_hal_usart.h
  • USART_IT_CTS : stm32f1xx_hal_usart.h
  • USART_IT_ERR : stm32f1xx_hal_usart.h
  • USART_IT_IDLE : stm32f1xx_hal_usart.h
  • USART_IT_LBD : stm32f1xx_hal_usart.h
  • USART_IT_MASK : stm32f1xx_hal_usart.h
  • USART_IT_PE : stm32f1xx_hal_usart.h
  • USART_IT_RXNE : stm32f1xx_hal_usart.h
  • USART_IT_TC : stm32f1xx_hal_usart.h
  • USART_IT_TXE : stm32f1xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32f1xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32f1xx_hal_usart.h
  • USART_MODE_RX : stm32f1xx_hal_usart.h
  • USART_MODE_TX : stm32f1xx_hal_usart.h
  • USART_MODE_TX_RX : stm32f1xx_hal_usart.h
  • USART_NACK_DISABLE : stm32f1xx_hal_usart.h
  • USART_NACK_ENABLE : stm32f1xx_hal_usart.h
  • USART_PARITY_EVEN : stm32f1xx_hal_usart.h
  • USART_PARITY_NONE : stm32f1xx_hal_usart.h
  • USART_PARITY_ODD : stm32f1xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32f1xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32f1xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32f1xx_hal_usart.h
  • USART_POLARITY_LOW : stm32f1xx_hal_usart.h
  • USART_POSITION_GTPR_GT : stm32f1xx_ll_usart.h
  • USART_Receive_IT() : stm32f1xx_hal_usart.c
  • USART_SetConfig() : stm32f1xx_hal_usart.c
  • USART_STOPBITS_0_5 : stm32f1xx_hal_usart.h
  • USART_STOPBITS_1 : stm32f1xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32f1xx_hal_usart.h
  • USART_STOPBITS_2 : stm32f1xx_hal_usart.h
  • USART_TIMEOUT_VALUE : stm32f1xx_hal_usart.c
  • USART_Transmit_IT() : stm32f1xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32f1xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32f1xx_hal_usart.c
  • USART_WORDLENGTH_8B : stm32f1xx_hal_usart.h
  • USART_WORDLENGTH_9B : stm32f1xx_hal_usart.h
  • USB_EP0StartXfer : stm32f1xx_hal_pcd.h
  • USB_WAKEUP_EXTI_LINE : stm32f1xx_hal_pcd.h
  • USBD_FS_TRDT_VALUE : stm32f1xx_hal_pcd.h
  • USE_RTOS : stm32f1xx_hal_conf.h
  • USE_SPI_CRC : stm32f1xx_hal_conf.h
  • UTILS_EnablePLLAndSwitchSystem() : stm32f1xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32f1xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MAX : stm32f1xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32f1xx_ll_utils.c
  • UTILS_LATENCY1_FREQ : stm32f1xx_ll_utils.c
  • UTILS_LATENCY2_FREQ : stm32f1xx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32f1xx_ll_utils.c
  • UTILS_PLL_OUTPUT_MAX : stm32f1xx_ll_utils.c
  • UTILS_SetFlashLatency() : stm32f1xx_ll_utils.c
  • uwTick : stm32f1xx_hal.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- v -

  • VDD_VALUE : stm32f1xx_hal_conf.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • WWDG_EWI_DISABLE : stm32f1xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32f1xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32f1xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32f1xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32f1xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32f1xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32f1xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32f1xx_hal_wwdg.h
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STM32F103xB HAL User Manual: Globals

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- a -

  • ADC_ConversionStop_Disable() : stm32f1xx_hal_adc.c
  • ADC_DMAConvCplt() : stm32f1xx_hal_adc.c
  • ADC_DMAError() : stm32f1xx_hal_adc.c
  • ADC_DMAHalfConvCplt() : stm32f1xx_hal_adc.c
  • ADC_Enable() : stm32f1xx_hal_adc.c
  • ADC_StabilizationTime() : stm32f1xx_hal_adc.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- c -

  • CAN_Receive_IT() : stm32f1xx_hal_can.c
  • CAN_Transmit_IT() : stm32f1xx_hal_can.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- d -

  • DMA_SetConfig() : stm32f1xx_hal_dma.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- f -

  • FLASH_MassErase() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_DisableWRP() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_EnableWRP() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_GetRDP() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_GetUser() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_GetWRP() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_ProgramData() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_RDP_LevelConfig() : stm32f1xx_hal_flash_ex.c
  • FLASH_OB_UserConfig() : stm32f1xx_hal_flash_ex.c
  • FLASH_PageErase() : stm32f1xx_hal_flash.c , stm32f1xx_hal_flash_ex.c
  • FLASH_Program_HalfWord() : stm32f1xx_hal_flash.c
  • FLASH_SetErrorCode() : stm32f1xx_hal_flash.c
  • FLASH_WaitForLastOperation() : stm32f1xx_hal_flash.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- h -

  • HAL_ADC_AnalogWDGConfig() : stm32f1xx_hal_adc.c
  • HAL_ADC_ConfigChannel() : stm32f1xx_hal_adc.c
  • HAL_ADC_ConvCpltCallback() : stm32f1xx_hal_adc.c
  • HAL_ADC_ConvHalfCpltCallback() : stm32f1xx_hal_adc.c
  • HAL_ADC_DeInit() : stm32f1xx_hal_adc.c
  • HAL_ADC_ErrorCallback() : stm32f1xx_hal_adc.c
  • HAL_ADC_GetError() : stm32f1xx_hal_adc.c
  • HAL_ADC_GetState() : stm32f1xx_hal_adc.c
  • HAL_ADC_GetValue() : stm32f1xx_hal_adc.c
  • HAL_ADC_Init() : stm32f1xx_hal_adc.c
  • HAL_ADC_IRQHandler() : stm32f1xx_hal_adc.c
  • HAL_ADC_LevelOutOfWindowCallback() : stm32f1xx_hal_adc.c
  • HAL_ADC_MspDeInit() : stm32f1xx_hal_adc.c
  • HAL_ADC_MspInit() : stm32f1xx_hal_adc.c
  • HAL_ADC_PollForConversion() : stm32f1xx_hal_adc.c
  • HAL_ADC_PollForEvent() : stm32f1xx_hal_adc.c
  • HAL_ADC_Start() : stm32f1xx_hal_adc.c
  • HAL_ADC_Start_DMA() : stm32f1xx_hal_adc.c
  • HAL_ADC_Start_IT() : stm32f1xx_hal_adc.c
  • HAL_ADC_Stop() : stm32f1xx_hal_adc.c
  • HAL_ADC_Stop_DMA() : stm32f1xx_hal_adc.c
  • HAL_ADC_Stop_IT() : stm32f1xx_hal_adc.c
  • HAL_ADCEx_Calibration_Start() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConfigChannel() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedConvCpltCallback() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedGetValue() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedPollForConversion() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStart_IT() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_InjectedStop_IT() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeConfigChannel() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeGetValue() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStart_DMA() : stm32f1xx_hal_adc_ex.c
  • HAL_ADCEx_MultiModeStop_DMA() : stm32f1xx_hal_adc_ex.c
  • HAL_CAN_ConfigFilter() : stm32f1xx_hal_can.c
  • HAL_CAN_DeInit() : stm32f1xx_hal_can.c
  • HAL_CAN_ErrorCallback() : stm32f1xx_hal_can.c
  • HAL_CAN_GetError() : stm32f1xx_hal_can.c
  • HAL_CAN_GetState() : stm32f1xx_hal_can.c
  • HAL_CAN_Init() : stm32f1xx_hal_can.c
  • HAL_CAN_IRQHandler() : stm32f1xx_hal_can.c
  • HAL_CAN_MspDeInit() : stm32f1xx_hal_can.c
  • HAL_CAN_MspInit() : stm32f1xx_hal_can.c
  • HAL_CAN_Receive() : stm32f1xx_hal_can.c
  • HAL_CAN_Receive_IT() : stm32f1xx_hal_can.c
  • HAL_CAN_RxCpltCallback() : stm32f1xx_hal_can.c
  • HAL_CAN_Sleep() : stm32f1xx_hal_can.c
  • HAL_CAN_Transmit() : stm32f1xx_hal_can.c
  • HAL_CAN_Transmit_IT() : stm32f1xx_hal_can.c
  • HAL_CAN_TxCpltCallback() : stm32f1xx_hal_can.c
  • HAL_CAN_WakeUp() : stm32f1xx_hal_can.c
  • HAL_CRC_Accumulate() : stm32f1xx_hal_crc.c
  • HAL_CRC_Calculate() : stm32f1xx_hal_crc.c
  • HAL_CRC_DeInit() : stm32f1xx_hal_crc.c
  • HAL_CRC_GetState() : stm32f1xx_hal_crc.c
  • HAL_CRC_Init() : stm32f1xx_hal_crc.c
  • HAL_CRC_MspDeInit() : stm32f1xx_hal_crc.c
  • HAL_CRC_MspInit() : stm32f1xx_hal_crc.c
  • HAL_DBGMCU_DisableDBGSleepMode() : stm32f1xx_hal.c
  • HAL_DBGMCU_DisableDBGStandbyMode() : stm32f1xx_hal.c
  • HAL_DBGMCU_DisableDBGStopMode() : stm32f1xx_hal.c
  • HAL_DBGMCU_EnableDBGSleepMode() : stm32f1xx_hal.c
  • HAL_DBGMCU_EnableDBGStandbyMode() : stm32f1xx_hal.c
  • HAL_DBGMCU_EnableDBGStopMode() : stm32f1xx_hal.c
  • HAL_DeInit() : stm32f1xx_hal.c
  • HAL_Delay() : stm32f1xx_hal.c
  • HAL_DMA_Abort() : stm32f1xx_hal_dma.c
  • HAL_DMA_Abort_IT() : stm32f1xx_hal_dma.c
  • HAL_DMA_DeInit() : stm32f1xx_hal_dma.c
  • HAL_DMA_GetError() : stm32f1xx_hal_dma.c
  • HAL_DMA_GetState() : stm32f1xx_hal_dma.c
  • HAL_DMA_Init() : stm32f1xx_hal_dma.c
  • HAL_DMA_IRQHandler() : stm32f1xx_hal_dma.c
  • HAL_DMA_PollForTransfer() : stm32f1xx_hal_dma.c
  • HAL_DMA_RegisterCallback() : stm32f1xx_hal_dma.c
  • HAL_DMA_Start() : stm32f1xx_hal_dma.c
  • HAL_DMA_Start_IT() : stm32f1xx_hal_dma.c
  • HAL_DMA_UnRegisterCallback() : stm32f1xx_hal_dma.c
  • HAL_FLASH_EndOfOperationCallback() : stm32f1xx_hal_flash.c
  • HAL_FLASH_GetError() : stm32f1xx_hal_flash.c
  • HAL_FLASH_IRQHandler() : stm32f1xx_hal_flash.c
  • HAL_FLASH_Lock() : stm32f1xx_hal_flash.c
  • HAL_FLASH_OB_Launch() : stm32f1xx_hal_flash.c
  • HAL_FLASH_OB_Lock() : stm32f1xx_hal_flash.c
  • HAL_FLASH_OB_Unlock() : stm32f1xx_hal_flash.c
  • HAL_FLASH_OperationErrorCallback() : stm32f1xx_hal_flash.c
  • HAL_FLASH_Program() : stm32f1xx_hal_flash.c
  • HAL_FLASH_Program_IT() : stm32f1xx_hal_flash.c
  • HAL_FLASH_Unlock() : stm32f1xx_hal_flash.c
  • HAL_FLASHEx_Erase() : stm32f1xx_hal_flash_ex.c
  • HAL_FLASHEx_Erase_IT() : stm32f1xx_hal_flash_ex.c
  • HAL_FLASHEx_OBErase() : stm32f1xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetConfig() : stm32f1xx_hal_flash_ex.c
  • HAL_FLASHEx_OBGetUserData() : stm32f1xx_hal_flash_ex.c
  • HAL_FLASHEx_OBProgram() : stm32f1xx_hal_flash_ex.c
  • HAL_GetDEVID() : stm32f1xx_hal.c
  • HAL_GetHalVersion() : stm32f1xx_hal.c
  • HAL_GetREVID() : stm32f1xx_hal.c
  • HAL_GetTick() : stm32f1xx_hal.c
  • HAL_GetUID() : stm32f1xx_hal.c
  • HAL_GPIO_DeInit() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_EXTI_Callback() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_EXTI_IRQHandler() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_Init() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_LockPin() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_ReadPin() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_TogglePin() : stm32f1xx_hal_gpio.c
  • HAL_GPIO_WritePin() : stm32f1xx_hal_gpio.c
  • HAL_GPIOEx_ConfigEventout() : stm32f1xx_hal_gpio_ex.c
  • HAL_GPIOEx_DisableEventout() : stm32f1xx_hal_gpio_ex.c
  • HAL_GPIOEx_EnableEventout() : stm32f1xx_hal_gpio_ex.c
  • HAL_HalfDuplex_EnableReceiver() : stm32f1xx_hal_uart.c
  • HAL_HalfDuplex_EnableTransmitter() : stm32f1xx_hal_uart.c
  • HAL_HalfDuplex_Init() : stm32f1xx_hal_uart.c
  • HAL_I2C_AbortCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_AddrCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_DeInit() : stm32f1xx_hal_i2c.c
  • HAL_I2C_DisableListen_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_EnableListen_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_ER_IRQHandler() : stm32f1xx_hal_i2c.c
  • HAL_I2C_ErrorCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_EV_IRQHandler() : stm32f1xx_hal_i2c.c
  • HAL_I2C_GetError() : stm32f1xx_hal_i2c.c
  • HAL_I2C_GetMode() : stm32f1xx_hal_i2c.c
  • HAL_I2C_GetState() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Init() : stm32f1xx_hal_i2c.c
  • HAL_I2C_IsDeviceReady() : stm32f1xx_hal_i2c.c
  • HAL_I2C_ListenCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Abort_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Receive() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Receive_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Receive_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Receive_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Sequential_Transmit_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Transmit() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Master_Transmit_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MasterRxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MasterTxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Read() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Read_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Read_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Write() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Write_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Mem_Write_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MemRxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MemTxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MspDeInit() : stm32f1xx_hal_i2c.c
  • HAL_I2C_MspInit() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Receive() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Receive_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Receive_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Sequential_Transmit_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_DMA() : stm32f1xx_hal_i2c.c
  • HAL_I2C_Slave_Transmit_IT() : stm32f1xx_hal_i2c.c
  • HAL_I2C_SlaveRxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_I2C_SlaveTxCpltCallback() : stm32f1xx_hal_i2c.c
  • HAL_IncTick() : stm32f1xx_hal.c
  • HAL_Init() : stm32f1xx_hal.c
  • HAL_InitTick() : stm32f1xx_hal.c
  • HAL_IRDA_Abort() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Abort_IT() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortReceive() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortReceive_IT() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortReceiveCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortTransmit() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortTransmit_IT() : stm32f1xx_hal_irda.c
  • HAL_IRDA_AbortTransmitCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_DeInit() : stm32f1xx_hal_irda.c
  • HAL_IRDA_DMAPause() : stm32f1xx_hal_irda.c
  • HAL_IRDA_DMAResume() : stm32f1xx_hal_irda.c
  • HAL_IRDA_DMAStop() : stm32f1xx_hal_irda.c
  • HAL_IRDA_ErrorCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_GetError() : stm32f1xx_hal_irda.c
  • HAL_IRDA_GetState() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Init() : stm32f1xx_hal_irda.c
  • HAL_IRDA_IRQHandler() : stm32f1xx_hal_irda.c
  • HAL_IRDA_MspDeInit() : stm32f1xx_hal_irda.c
  • HAL_IRDA_MspInit() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Receive() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Receive_DMA() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Receive_IT() : stm32f1xx_hal_irda.c
  • HAL_IRDA_RxCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_RxHalfCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Transmit() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Transmit_DMA() : stm32f1xx_hal_irda.c
  • HAL_IRDA_Transmit_IT() : stm32f1xx_hal_irda.c
  • HAL_IRDA_TxCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IRDA_TxHalfCpltCallback() : stm32f1xx_hal_irda.c
  • HAL_IWDG_Init() : stm32f1xx_hal_iwdg.c
  • HAL_IWDG_Refresh() : stm32f1xx_hal_iwdg.c
  • HAL_LIN_Init() : stm32f1xx_hal_uart.c
  • HAL_LIN_SendBreak() : stm32f1xx_hal_uart.c
  • HAL_MspDeInit() : stm32f1xx_hal.c
  • HAL_MspInit() : stm32f1xx_hal.c
  • HAL_MultiProcessor_EnterMuteMode() : stm32f1xx_hal_uart.c
  • HAL_MultiProcessor_ExitMuteMode() : stm32f1xx_hal_uart.c
  • HAL_MultiProcessor_Init() : stm32f1xx_hal_uart.c
  • HAL_NVIC_ClearPendingIRQ() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_DisableIRQ() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_EnableIRQ() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_GetActive() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_GetPendingIRQ() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_GetPriority() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_GetPriorityGrouping() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_SetPendingIRQ() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_SetPriority() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_SetPriorityGrouping() : stm32f1xx_hal_cortex.c
  • HAL_NVIC_SystemReset() : stm32f1xx_hal_cortex.c
  • HAL_PCD_ActivateRemoteWakeup() : stm32f1xx_hal_pcd.c
  • HAL_PCD_ConnectCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DataInStageCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DataOutStageCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DeActivateRemoteWakeup() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DeInit() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DevConnect() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DevDisconnect() : stm32f1xx_hal_pcd.c
  • HAL_PCD_DisconnectCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_Close() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_ClrStall() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_Flush() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_GetRxCount() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_Open() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_Receive() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_SetStall() : stm32f1xx_hal_pcd.c
  • HAL_PCD_EP_Transmit() : stm32f1xx_hal_pcd.c
  • HAL_PCD_GetState() : stm32f1xx_hal_pcd.c
  • HAL_PCD_Init() : stm32f1xx_hal_pcd.c
  • HAL_PCD_IRQHandler() : stm32f1xx_hal_pcd.c
  • HAL_PCD_ISOINIncompleteCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_ISOOUTIncompleteCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_MspDeInit() : stm32f1xx_hal_pcd.c
  • HAL_PCD_MspInit() : stm32f1xx_hal_pcd.c
  • HAL_PCD_ResetCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_ResumeCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_SetAddress() : stm32f1xx_hal_pcd.c
  • HAL_PCD_SetupStageCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_SOFCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCD_Start() : stm32f1xx_hal_pcd.c
  • HAL_PCD_Stop() : stm32f1xx_hal_pcd.c
  • HAL_PCD_SuspendCallback() : stm32f1xx_hal_pcd.c
  • HAL_PCDEx_PMAConfig() : stm32f1xx_hal_pcd_ex.c
  • HAL_PCDEx_SetConnectionState() : stm32f1xx_hal_pcd_ex.c
  • HAL_PWR_ConfigPVD() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DeInit() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DisableBkUpAccess() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DisablePVD() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DisableSEVOnPend() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DisableSleepOnExit() : stm32f1xx_hal_pwr.c
  • HAL_PWR_DisableWakeUpPin() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnableBkUpAccess() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnablePVD() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnableSEVOnPend() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnableSleepOnExit() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnableWakeUpPin() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnterSLEEPMode() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnterSTANDBYMode() : stm32f1xx_hal_pwr.c
  • HAL_PWR_EnterSTOPMode() : stm32f1xx_hal_pwr.c
  • HAL_PWR_PVD_IRQHandler() : stm32f1xx_hal_pwr.c
  • HAL_PWR_PVDCallback() : stm32f1xx_hal_pwr.c
  • HAL_RCC_ClockConfig() : stm32f1xx_hal_rcc.c
  • HAL_RCC_CSSCallback() : stm32f1xx_hal_rcc.c
  • HAL_RCC_DeInit() : stm32f1xx_hal_rcc.c
  • HAL_RCC_DisableCSS() : stm32f1xx_hal_rcc.c
  • HAL_RCC_EnableCSS() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetClockConfig() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetHCLKFreq() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetOscConfig() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetPCLK1Freq() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetPCLK2Freq() : stm32f1xx_hal_rcc.c
  • HAL_RCC_GetSysClockFreq() : stm32f1xx_hal_rcc.c
  • HAL_RCC_MCOConfig() : stm32f1xx_hal_rcc.c
  • HAL_RCC_NMI_IRQHandler() : stm32f1xx_hal_rcc.c
  • HAL_RCC_OscConfig() : stm32f1xx_hal_rcc.c
  • HAL_RCCEx_GetPeriphCLKConfig() : stm32f1xx_hal_rcc_ex.c
  • HAL_RCCEx_GetPeriphCLKFreq() : stm32f1xx_hal_rcc_ex.c
  • HAL_RCCEx_PeriphCLKConfig() : stm32f1xx_hal_rcc_ex.c
  • HAL_ResumeTick() : stm32f1xx_hal.c
  • HAL_RTC_AlarmAEventCallback() : stm32f1xx_hal_rtc.c
  • HAL_RTC_AlarmIRQHandler() : stm32f1xx_hal_rtc.c
  • HAL_RTC_DeactivateAlarm() : stm32f1xx_hal_rtc.c
  • HAL_RTC_DeInit() : stm32f1xx_hal_rtc.c
  • HAL_RTC_GetAlarm() : stm32f1xx_hal_rtc.c
  • HAL_RTC_GetDate() : stm32f1xx_hal_rtc.c
  • HAL_RTC_GetState() : stm32f1xx_hal_rtc.c
  • HAL_RTC_GetTime() : stm32f1xx_hal_rtc.c
  • HAL_RTC_Init() : stm32f1xx_hal_rtc.c
  • HAL_RTC_MspDeInit() : stm32f1xx_hal_rtc.c
  • HAL_RTC_MspInit() : stm32f1xx_hal_rtc.c
  • HAL_RTC_PollForAlarmAEvent() : stm32f1xx_hal_rtc.c
  • HAL_RTC_SetAlarm() : stm32f1xx_hal_rtc.c
  • HAL_RTC_SetAlarm_IT() : stm32f1xx_hal_rtc.c
  • HAL_RTC_SetDate() : stm32f1xx_hal_rtc.c
  • HAL_RTC_SetTime() : stm32f1xx_hal_rtc.c
  • HAL_RTC_WaitForSynchro() : stm32f1xx_hal_rtc.c
  • HAL_RTCEx_BKUPRead() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_BKUPWrite() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateSecond() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_DeactivateTamper() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_PollForTamper1Event() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_RTCEventCallback() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_RTCEventErrorCallback() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_RTCIRQHandler() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSecond_IT() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_SetSmoothCalib() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_SetTamper_IT() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_Tamper1EventCallback() : stm32f1xx_hal_rtc_ex.c
  • HAL_RTCEx_TamperIRQHandler() : stm32f1xx_hal_rtc_ex.c
  • HAL_SMARTCARD_Abort() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Abort_IT() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortCpltCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceive_IT() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortReceiveCpltCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmit_IT() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_AbortTransmitCpltCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_DeInit() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_ErrorCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_GetError() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_GetState() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Init() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_IRQHandler() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_MspDeInit() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_MspInit() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_DMA() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Receive_IT() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_ReInit() : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_RxCpltCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_DMA() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_Transmit_IT() : stm32f1xx_hal_smartcard.c
  • HAL_SMARTCARD_TxCpltCallback() : stm32f1xx_hal_smartcard.c
  • HAL_SPI_Abort() : stm32f1xx_hal_spi.c
  • HAL_SPI_Abort_IT() : stm32f1xx_hal_spi.c
  • HAL_SPI_AbortCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_DeInit() : stm32f1xx_hal_spi.c
  • HAL_SPI_DMAPause() : stm32f1xx_hal_spi.c
  • HAL_SPI_DMAResume() : stm32f1xx_hal_spi.c
  • HAL_SPI_DMAStop() : stm32f1xx_hal_spi.c
  • HAL_SPI_ErrorCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_GetError() : stm32f1xx_hal_spi.c
  • HAL_SPI_GetState() : stm32f1xx_hal_spi.c
  • HAL_SPI_Init() : stm32f1xx_hal_spi.c
  • HAL_SPI_IRQHandler() : stm32f1xx_hal_spi.c
  • HAL_SPI_MspDeInit() : stm32f1xx_hal_spi.c
  • HAL_SPI_MspInit() : stm32f1xx_hal_spi.c
  • HAL_SPI_Receive() : stm32f1xx_hal_spi.c
  • HAL_SPI_Receive_DMA() : stm32f1xx_hal_spi.c
  • HAL_SPI_Receive_IT() : stm32f1xx_hal_spi.c
  • HAL_SPI_RxCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_RxHalfCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_Transmit() : stm32f1xx_hal_spi.c
  • HAL_SPI_Transmit_DMA() : stm32f1xx_hal_spi.c
  • HAL_SPI_Transmit_IT() : stm32f1xx_hal_spi.c
  • HAL_SPI_TransmitReceive() : stm32f1xx_hal_spi.c
  • HAL_SPI_TransmitReceive_DMA() : stm32f1xx_hal_spi.c
  • HAL_SPI_TransmitReceive_IT() : stm32f1xx_hal_spi.c
  • HAL_SPI_TxCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_TxHalfCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_TxRxCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SPI_TxRxHalfCpltCallback() : stm32f1xx_hal_spi.c
  • HAL_SuspendTick() : stm32f1xx_hal.c
  • HAL_SYSTICK_Callback() : stm32f1xx_hal_cortex.c
  • HAL_SYSTICK_CLKSourceConfig() : stm32f1xx_hal_cortex.c
  • HAL_SYSTICK_Config() : stm32f1xx_hal_cortex.c
  • HAL_SYSTICK_IRQHandler() : stm32f1xx_hal_cortex.c
  • HAL_TIM_Base_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Start_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Stop_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_Base_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_ConfigClockSource() : stm32f1xx_hal_tim.c
  • HAL_TIM_ConfigOCrefClear() : stm32f1xx_hal_tim.c
  • HAL_TIM_ConfigTI1Input() : stm32f1xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStart() : stm32f1xx_hal_tim.c
  • HAL_TIM_DMABurst_ReadStop() : stm32f1xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStart() : stm32f1xx_hal_tim.c
  • HAL_TIM_DMABurst_WriteStop() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Start_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_Encoder_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_ErrorCallback() : stm32f1xx_hal_tim.c
  • HAL_TIM_GenerateEvent() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_CaptureCallback() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_ConfigChannel() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Start_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Stop_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_IC_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_IRQHandler() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_ConfigChannel() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_DelayElapsedCallback() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Start_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Stop_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_OC_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_ConfigChannel() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_OnePulse_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_PeriodElapsedCallback() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_ConfigChannel() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_DeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_GetState() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Init() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_MspDeInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_MspInit() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_PulseFinishedCallback() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Start() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Start_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Start_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Stop() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Stop_DMA() : stm32f1xx_hal_tim.c
  • HAL_TIM_PWM_Stop_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_ReadCapturedValue() : stm32f1xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization() : stm32f1xx_hal_tim.c
  • HAL_TIM_SlaveConfigSynchronization_IT() : stm32f1xx_hal_tim.c
  • HAL_TIM_TriggerCallback() : stm32f1xx_hal_tim.c
  • HAL_TIMEx_BreakCallback() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_CommutationCallback() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigBreakDeadTime() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_ConfigCommutationEvent_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_DeInit() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_GetState() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Init() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspDeInit() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_MspInit() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Start_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_HallSensor_Stop_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_MasterConfigSynchronization() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Start_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OCN_Stop_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Start_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_OnePulseN_Stop_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Start_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_DMA() : stm32f1xx_hal_tim_ex.c
  • HAL_TIMEx_PWMN_Stop_IT() : stm32f1xx_hal_tim_ex.c
  • HAL_UART_Abort() : stm32f1xx_hal_uart.c
  • HAL_UART_Abort_IT() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortReceive() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortReceive_IT() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortReceiveCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortTransmit() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortTransmit_IT() : stm32f1xx_hal_uart.c
  • HAL_UART_AbortTransmitCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_DeInit() : stm32f1xx_hal_uart.c
  • HAL_UART_DMAPause() : stm32f1xx_hal_uart.c
  • HAL_UART_DMAResume() : stm32f1xx_hal_uart.c
  • HAL_UART_DMAStop() : stm32f1xx_hal_uart.c
  • HAL_UART_ErrorCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_GetError() : stm32f1xx_hal_uart.c
  • HAL_UART_GetState() : stm32f1xx_hal_uart.c
  • HAL_UART_Init() : stm32f1xx_hal_uart.c
  • HAL_UART_IRQHandler() : stm32f1xx_hal_uart.c
  • HAL_UART_MspDeInit() : stm32f1xx_hal_uart.c
  • HAL_UART_MspInit() : stm32f1xx_hal_uart.c
  • HAL_UART_Receive() : stm32f1xx_hal_uart.c
  • HAL_UART_Receive_DMA() : stm32f1xx_hal_uart.c
  • HAL_UART_Receive_IT() : stm32f1xx_hal_uart.c
  • HAL_UART_RxCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_RxHalfCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_Transmit() : stm32f1xx_hal_uart.c
  • HAL_UART_Transmit_DMA() : stm32f1xx_hal_uart.c
  • HAL_UART_Transmit_IT() : stm32f1xx_hal_uart.c
  • HAL_UART_TxCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_UART_TxHalfCpltCallback() : stm32f1xx_hal_uart.c
  • HAL_USART_Abort() : stm32f1xx_hal_usart.c
  • HAL_USART_Abort_IT() : stm32f1xx_hal_usart.c
  • HAL_USART_AbortCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_DeInit() : stm32f1xx_hal_usart.c
  • HAL_USART_DMAPause() : stm32f1xx_hal_usart.c
  • HAL_USART_DMAResume() : stm32f1xx_hal_usart.c
  • HAL_USART_DMAStop() : stm32f1xx_hal_usart.c
  • HAL_USART_ErrorCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_GetError() : stm32f1xx_hal_usart.c
  • HAL_USART_GetState() : stm32f1xx_hal_usart.c
  • HAL_USART_Init() : stm32f1xx_hal_usart.c
  • HAL_USART_IRQHandler() : stm32f1xx_hal_usart.c
  • HAL_USART_MspDeInit() : stm32f1xx_hal_usart.c
  • HAL_USART_MspInit() : stm32f1xx_hal_usart.c
  • HAL_USART_Receive() : stm32f1xx_hal_usart.c
  • HAL_USART_Receive_DMA() : stm32f1xx_hal_usart.c
  • HAL_USART_Receive_IT() : stm32f1xx_hal_usart.c
  • HAL_USART_RxCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_RxHalfCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_Transmit() : stm32f1xx_hal_usart.c
  • HAL_USART_Transmit_DMA() : stm32f1xx_hal_usart.c
  • HAL_USART_Transmit_IT() : stm32f1xx_hal_usart.c
  • HAL_USART_TransmitReceive() : stm32f1xx_hal_usart.c
  • HAL_USART_TransmitReceive_DMA() : stm32f1xx_hal_usart.c
  • HAL_USART_TransmitReceive_IT() : stm32f1xx_hal_usart.c
  • HAL_USART_TxCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_TxHalfCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_USART_TxRxCpltCallback() : stm32f1xx_hal_usart.c
  • HAL_WWDG_EarlyWakeupCallback() : stm32f1xx_hal_wwdg.c
  • HAL_WWDG_Init() : stm32f1xx_hal_wwdg.c
  • HAL_WWDG_IRQHandler() : stm32f1xx_hal_wwdg.c
  • HAL_WWDG_MspInit() : stm32f1xx_hal_wwdg.c
  • HAL_WWDG_Refresh() : stm32f1xx_hal_wwdg.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • Defines
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  • r
  • s
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  • u

- i -

  • I2C_DMAAbort() : stm32f1xx_hal_i2c.c
  • I2C_DMAError() : stm32f1xx_hal_i2c.c
  • I2C_DMAXferCplt() : stm32f1xx_hal_i2c.c
  • I2C_IsAcknowledgeFailed() : stm32f1xx_hal_i2c.c
  • I2C_ITError() : stm32f1xx_hal_i2c.c
  • I2C_Master_ADD10() : stm32f1xx_hal_i2c.c
  • I2C_Master_ADDR() : stm32f1xx_hal_i2c.c
  • I2C_Master_SB() : stm32f1xx_hal_i2c.c
  • I2C_MasterReceive_BTF() : stm32f1xx_hal_i2c.c
  • I2C_MasterReceive_RXNE() : stm32f1xx_hal_i2c.c
  • I2C_MasterRequestRead() : stm32f1xx_hal_i2c.c
  • I2C_MasterRequestWrite() : stm32f1xx_hal_i2c.c
  • I2C_MasterTransmit_BTF() : stm32f1xx_hal_i2c.c
  • I2C_MasterTransmit_TXE() : stm32f1xx_hal_i2c.c
  • I2C_RequestMemoryRead() : stm32f1xx_hal_i2c.c
  • I2C_RequestMemoryWrite() : stm32f1xx_hal_i2c.c
  • I2C_Slave_ADDR() : stm32f1xx_hal_i2c.c
  • I2C_Slave_AF() : stm32f1xx_hal_i2c.c
  • I2C_Slave_STOPF() : stm32f1xx_hal_i2c.c
  • I2C_SlaveReceive_BTF() : stm32f1xx_hal_i2c.c
  • I2C_SlaveReceive_RXNE() : stm32f1xx_hal_i2c.c
  • I2C_SlaveTransmit_BTF() : stm32f1xx_hal_i2c.c
  • I2C_SlaveTransmit_TXE() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnBTFFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnMasterAddressFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnRXNEFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnSTOPFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • I2C_WaitOnTXEFlagUntilTimeout() : stm32f1xx_hal_i2c.c
  • IC1Config() : stm32f1xx_ll_tim.c
  • IC2Config() : stm32f1xx_ll_tim.c
  • IC3Config() : stm32f1xx_ll_tim.c
  • IC4Config() : stm32f1xx_ll_tim.c
  • IRDA_DMAAbortOnError() : stm32f1xx_hal_irda.c
  • IRDA_DMAError() : stm32f1xx_hal_irda.c
  • IRDA_DMAReceiveCplt() : stm32f1xx_hal_irda.c
  • IRDA_DMAReceiveHalfCplt() : stm32f1xx_hal_irda.c
  • IRDA_DMARxAbortCallback() : stm32f1xx_hal_irda.c
  • IRDA_DMARxOnlyAbortCallback() : stm32f1xx_hal_irda.c
  • IRDA_DMATransmitCplt() : stm32f1xx_hal_irda.c
  • IRDA_DMATransmitHalfCplt() : stm32f1xx_hal_irda.c
  • IRDA_DMATxAbortCallback() : stm32f1xx_hal_irda.c
  • IRDA_DMATxOnlyAbortCallback() : stm32f1xx_hal_irda.c
  • IRDA_EndRxTransfer() : stm32f1xx_hal_irda.c
  • IRDA_EndTransmit_IT() : stm32f1xx_hal_irda.c
  • IRDA_EndTxTransfer() : stm32f1xx_hal_irda.c
  • IRDA_Receive_IT() : stm32f1xx_hal_irda.c
  • IRDA_SetConfig() : stm32f1xx_hal_irda.c
  • IRDA_Transmit_IT() : stm32f1xx_hal_irda.c
  • IRDA_WaitOnFlagUntilTimeout() : stm32f1xx_hal_irda.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • a
  • c
  • d
  • f
  • h
  • i
  • l
  • o
  • p
  • r
  • s
  • t
  • u

- l -

  • LL_ADC_ClearFlag_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_ClearFlag_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_ClearFlag_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_CommonDeInit() : stm32f1xx_ll_adc.c
  • LL_ADC_CommonInit() : stm32f1xx_ll_adc.c
  • LL_ADC_CommonStructInit() : stm32f1xx_ll_adc.c
  • LL_ADC_DeInit() : stm32f1xx_ll_adc.c
  • LL_ADC_Disable() : stm32f1xx_ll_adc.h
  • LL_ADC_DisableIT_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_DisableIT_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_DisableIT_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_DMA_GetRegAddr() : stm32f1xx_ll_adc.h
  • LL_ADC_Enable() : stm32f1xx_ll_adc.h
  • LL_ADC_EnableIT_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_EnableIT_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_EnableIT_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_GetAnalogWDMonitChannels() : stm32f1xx_ll_adc.h
  • LL_ADC_GetAnalogWDThresholds() : stm32f1xx_ll_adc.h
  • LL_ADC_GetChannelSamplingTime() : stm32f1xx_ll_adc.h
  • LL_ADC_GetCommonPathInternalCh() : stm32f1xx_ll_adc.h
  • LL_ADC_GetDataAlignment() : stm32f1xx_ll_adc.h
  • LL_ADC_GetMultimode() : stm32f1xx_ll_adc.h
  • LL_ADC_GetSequencersScanMode() : stm32f1xx_ll_adc.h
  • LL_ADC_Init() : stm32f1xx_ll_adc.c
  • LL_ADC_INJ_GetOffset() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerDiscont() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerLength() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_GetSequencerRanks() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_GetTrigAuto() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_GetTriggerSource() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_Init() : stm32f1xx_ll_adc.c
  • LL_ADC_INJ_IsTriggerSourceSWStart() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData12() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_ReadConversionData32() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetOffset() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerDiscont() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerLength() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetSequencerRanks() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetTrigAuto() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SetTriggerSource() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_StartConversionExtTrig() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_StartConversionSWStart() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_StopConversionExtTrig() : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_StructInit() : stm32f1xx_ll_adc.c
  • LL_ADC_IsActiveFlag_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_MST_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsActiveFlag_SLV_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsCalibrationOnGoing() : stm32f1xx_ll_adc.h
  • LL_ADC_IsEnabled() : stm32f1xx_ll_adc.h
  • LL_ADC_IsEnabledIT_AWD1() : stm32f1xx_ll_adc.h
  • LL_ADC_IsEnabledIT_EOS() : stm32f1xx_ll_adc.h
  • LL_ADC_IsEnabledIT_JEOS() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetContinuousMode() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetDMATransfer() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetSequencerDiscont() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetSequencerLength() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetSequencerRanks() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_GetTriggerSource() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_Init() : stm32f1xx_ll_adc.c
  • LL_ADC_REG_IsTriggerSourceSWStart() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData12() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_ReadConversionData32() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_ReadMultiConversionData32() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetContinuousMode() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetDMATransfer() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetSequencerDiscont() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetSequencerLength() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetSequencerRanks() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SetTriggerSource() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_StartConversionExtTrig() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_StartConversionSWStart() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_StopConversionExtTrig() : stm32f1xx_ll_adc.h
  • LL_ADC_REG_StructInit() : stm32f1xx_ll_adc.c
  • LL_ADC_SetAnalogWDMonitChannels() : stm32f1xx_ll_adc.h
  • LL_ADC_SetAnalogWDThresholds() : stm32f1xx_ll_adc.h
  • LL_ADC_SetChannelSamplingTime() : stm32f1xx_ll_adc.h
  • LL_ADC_SetCommonPathInternalCh() : stm32f1xx_ll_adc.h
  • LL_ADC_SetDataAlignment() : stm32f1xx_ll_adc.h
  • LL_ADC_SetMultimode() : stm32f1xx_ll_adc.h
  • LL_ADC_SetSequencersScanMode() : stm32f1xx_ll_adc.h
  • LL_ADC_StartCalibration() : stm32f1xx_ll_adc.h
  • LL_ADC_StructInit() : stm32f1xx_ll_adc.c
  • LL_AHB1_GRP1_DisableClock() : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_EnableClock() : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_IsEnabledClock() : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_DisableClock() : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_EnableClock() : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_ForceReset() : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_IsEnabledClock() : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_ReleaseReset() : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_DisableClock() : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_EnableClock() : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_ForceReset() : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_IsEnabledClock() : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_ReleaseReset() : stm32f1xx_ll_bus.h
  • LL_CPUID_GetConstant() : stm32f1xx_ll_cortex.h
  • LL_CPUID_GetImplementer() : stm32f1xx_ll_cortex.h
  • LL_CPUID_GetParNo() : stm32f1xx_ll_cortex.h
  • LL_CPUID_GetRevision() : stm32f1xx_ll_cortex.h
  • LL_CPUID_GetVariant() : stm32f1xx_ll_cortex.h
  • LL_CRC_DeInit() : stm32f1xx_ll_crc.c
  • LL_CRC_FeedData32() : stm32f1xx_ll_crc.h
  • LL_CRC_Read_IDR() : stm32f1xx_ll_crc.h
  • LL_CRC_ReadData32() : stm32f1xx_ll_crc.h
  • LL_CRC_ResetCRCCalculationUnit() : stm32f1xx_ll_crc.h
  • LL_CRC_Write_IDR() : stm32f1xx_ll_crc.h
  • LL_DBGMCU_APB1_GRP1_FreezePeriph() : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_UnFreezePeriph() : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_FreezePeriph() : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_UnFreezePeriph() : stm32f1xx_ll_system.h
  • LL_DBGMCU_DisableDBGSleepMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_DisableDBGStandbyMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_DisableDBGStopMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_EnableDBGSleepMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_EnableDBGStandbyMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_EnableDBGStopMode() : stm32f1xx_ll_system.h
  • LL_DBGMCU_GetDeviceID() : stm32f1xx_ll_system.h
  • LL_DBGMCU_GetRevisionID() : stm32f1xx_ll_system.h
  • LL_DBGMCU_GetTracePinAssignment() : stm32f1xx_ll_system.h
  • LL_DBGMCU_SetTracePinAssignment() : stm32f1xx_ll_system.h
  • LL_DMA_ClearFlag_GI1() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI2() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI3() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI4() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI5() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI6() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_GI7() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT1() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT2() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT3() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT4() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT5() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT6() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_HT7() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC1() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC2() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC3() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC4() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC5() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC6() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TC7() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE1() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE2() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE3() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE4() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE5() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE6() : stm32f1xx_ll_dma.h
  • LL_DMA_ClearFlag_TE7() : stm32f1xx_ll_dma.h
  • LL_DMA_ConfigAddresses() : stm32f1xx_ll_dma.h
  • LL_DMA_ConfigTransfer() : stm32f1xx_ll_dma.h
  • LL_DMA_DeInit() : stm32f1xx_ll_dma.c
  • LL_DMA_DisableChannel() : stm32f1xx_ll_dma.h
  • LL_DMA_DisableIT_HT() : stm32f1xx_ll_dma.h
  • LL_DMA_DisableIT_TC() : stm32f1xx_ll_dma.h
  • LL_DMA_DisableIT_TE() : stm32f1xx_ll_dma.h
  • LL_DMA_EnableChannel() : stm32f1xx_ll_dma.h
  • LL_DMA_EnableIT_HT() : stm32f1xx_ll_dma.h
  • LL_DMA_EnableIT_TC() : stm32f1xx_ll_dma.h
  • LL_DMA_EnableIT_TE() : stm32f1xx_ll_dma.h
  • LL_DMA_GetChannelPriorityLevel() : stm32f1xx_ll_dma.h
  • LL_DMA_GetDataLength() : stm32f1xx_ll_dma.h
  • LL_DMA_GetDataTransferDirection() : stm32f1xx_ll_dma.h
  • LL_DMA_GetM2MDstAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_GetM2MSrcAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_GetMemoryAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_GetMemoryIncMode() : stm32f1xx_ll_dma.h
  • LL_DMA_GetMemorySize() : stm32f1xx_ll_dma.h
  • LL_DMA_GetMode() : stm32f1xx_ll_dma.h
  • LL_DMA_GetPeriphAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_GetPeriphIncMode() : stm32f1xx_ll_dma.h
  • LL_DMA_GetPeriphSize() : stm32f1xx_ll_dma.h
  • LL_DMA_Init() : stm32f1xx_ll_dma.c
  • LL_DMA_IsActiveFlag_GI1() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI2() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI3() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI4() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI5() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI6() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_GI7() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT1() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT2() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT3() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT4() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT5() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT6() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_HT7() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC1() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC2() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC3() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC4() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC5() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC6() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TC7() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE1() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE2() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE3() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE4() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE5() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE6() : stm32f1xx_ll_dma.h
  • LL_DMA_IsActiveFlag_TE7() : stm32f1xx_ll_dma.h
  • LL_DMA_IsEnabledChannel() : stm32f1xx_ll_dma.h
  • LL_DMA_IsEnabledIT_HT() : stm32f1xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TC() : stm32f1xx_ll_dma.h
  • LL_DMA_IsEnabledIT_TE() : stm32f1xx_ll_dma.h
  • LL_DMA_SetChannelPriorityLevel() : stm32f1xx_ll_dma.h
  • LL_DMA_SetDataLength() : stm32f1xx_ll_dma.h
  • LL_DMA_SetDataTransferDirection() : stm32f1xx_ll_dma.h
  • LL_DMA_SetM2MDstAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_SetM2MSrcAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_SetMemoryAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_SetMemoryIncMode() : stm32f1xx_ll_dma.h
  • LL_DMA_SetMemorySize() : stm32f1xx_ll_dma.h
  • LL_DMA_SetMode() : stm32f1xx_ll_dma.h
  • LL_DMA_SetPeriphAddress() : stm32f1xx_ll_dma.h
  • LL_DMA_SetPeriphIncMode() : stm32f1xx_ll_dma.h
  • LL_DMA_SetPeriphSize() : stm32f1xx_ll_dma.h
  • LL_DMA_StructInit() : stm32f1xx_ll_dma.c
  • LL_EXTI_ClearFlag_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_DeInit() : stm32f1xx_ll_exti.c
  • LL_EXTI_DisableEvent_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_DisableFallingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_DisableIT_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_DisableRisingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_EnableEvent_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_EnableFallingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_EnableIT_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_EnableRisingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_GenerateSWI_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_Init() : stm32f1xx_ll_exti.c
  • LL_EXTI_IsActiveFlag_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_IsEnabledEvent_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_IsEnabledFallingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_IsEnabledIT_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_IsEnabledRisingTrig_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_ReadFlag_0_31() : stm32f1xx_ll_exti.h
  • LL_EXTI_StructInit() : stm32f1xx_ll_exti.c
  • LL_FLASH_DisableHalfCycleAccess() : stm32f1xx_ll_system.h
  • LL_FLASH_DisablePrefetch() : stm32f1xx_ll_system.h
  • LL_FLASH_EnableHalfCycleAccess() : stm32f1xx_ll_system.h
  • LL_FLASH_EnablePrefetch() : stm32f1xx_ll_system.h
  • LL_FLASH_GetLatency() : stm32f1xx_ll_system.h
  • LL_FLASH_IsHalfCycleAccessEnabled() : stm32f1xx_ll_system.h
  • LL_FLASH_IsPrefetchEnabled() : stm32f1xx_ll_system.h
  • LL_FLASH_SetLatency() : stm32f1xx_ll_system.h
  • LL_GetFlashSize() : stm32f1xx_ll_utils.h
  • LL_GetUID_Word0() : stm32f1xx_ll_utils.h
  • LL_GetUID_Word1() : stm32f1xx_ll_utils.h
  • LL_GetUID_Word2() : stm32f1xx_ll_utils.h
  • LL_GPIO_AF_ConfigEventout() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableEventout() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_I2C1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_PD01() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_SPI1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_SWJ() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_TIM1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_TIM2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_TIM3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_TIM4() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_USART1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_USART2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_DisableRemap_USART3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableEventout() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_I2C1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_PD01() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_SPI1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_SWJ() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_TIM1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_TIM2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_TIM3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_TIM4() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_USART1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_USART2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EnableRemap_USART3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_GetEXTISource() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_I2C1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_PD01() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_SPI1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_TIM4() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_USART1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_IsEnabledRemap_USART2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_Remap_SWJ_NOJTAG() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_Remap_SWJ_NONJTRST() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial1_CAN1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial1_TIM2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial2_CAN1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial2_TIM2() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial3_CAN1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial_TIM1() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial_TIM3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_RemapPartial_USART3() : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_SetEXTISource() : stm32f1xx_ll_gpio.h
  • LL_GPIO_DeInit() : stm32f1xx_ll_gpio.c
  • LL_GPIO_GetPinMode() : stm32f1xx_ll_gpio.h
  • LL_GPIO_GetPinOutputType() : stm32f1xx_ll_gpio.h
  • LL_GPIO_GetPinPull() : stm32f1xx_ll_gpio.h
  • LL_GPIO_GetPinSpeed() : stm32f1xx_ll_gpio.h
  • LL_GPIO_Init() : stm32f1xx_ll_gpio.c
  • LL_GPIO_IsAnyPinLocked() : stm32f1xx_ll_gpio.h
  • LL_GPIO_IsInputPinSet() : stm32f1xx_ll_gpio.h
  • LL_GPIO_IsOutputPinSet() : stm32f1xx_ll_gpio.h
  • LL_GPIO_IsPinLocked() : stm32f1xx_ll_gpio.h
  • LL_GPIO_LockPin() : stm32f1xx_ll_gpio.h
  • LL_GPIO_ReadInputPort() : stm32f1xx_ll_gpio.h
  • LL_GPIO_ReadOutputPort() : stm32f1xx_ll_gpio.h
  • LL_GPIO_ResetOutputPin() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SetOutputPin() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SetPinMode() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SetPinOutputType() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SetPinPull() : stm32f1xx_ll_gpio.h
  • LL_GPIO_SetPinSpeed() : stm32f1xx_ll_gpio.h
  • LL_GPIO_StructInit() : stm32f1xx_ll_gpio.c
  • LL_GPIO_TogglePin() : stm32f1xx_ll_gpio.h
  • LL_GPIO_WriteOutputPort() : stm32f1xx_ll_gpio.h
  • LL_HANDLER_DisableFault() : stm32f1xx_ll_cortex.h
  • LL_HANDLER_EnableFault() : stm32f1xx_ll_cortex.h
  • LL_I2C_AcknowledgeNextData() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_ADDR() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_AF() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_ARLO() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_BERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_OVR() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearFlag_STOP() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_ALERT() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_PECERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_ClearSMBusFlag_TIMEOUT() : stm32f1xx_ll_i2c.h
  • LL_I2C_ConfigSpeed() : stm32f1xx_ll_i2c.h
  • LL_I2C_DeInit() : stm32f1xx_ll_i2c.c
  • LL_I2C_Disable() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableBitPOS() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableClockStretching() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableDMAReq_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableGeneralCall() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableIT_BUF() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableIT_ERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableIT_EVT() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableIT_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableIT_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableLastDMA() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableOwnAddress2() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableReset() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableSMBusAlert() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableSMBusPEC() : stm32f1xx_ll_i2c.h
  • LL_I2C_DisableSMBusPECCompare() : stm32f1xx_ll_i2c.h
  • LL_I2C_DMA_GetRegAddr() : stm32f1xx_ll_i2c.h
  • LL_I2C_Enable() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableBitPOS() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableClockStretching() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableDMAReq_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableGeneralCall() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableIT_BUF() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableIT_ERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableIT_EVT() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableIT_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableIT_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableLastDMA() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableOwnAddress2() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableReset() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableSMBusAlert() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableSMBusPEC() : stm32f1xx_ll_i2c.h
  • LL_I2C_EnableSMBusPECCompare() : stm32f1xx_ll_i2c.h
  • LL_I2C_GenerateStartCondition() : stm32f1xx_ll_i2c.h
  • LL_I2C_GenerateStopCondition() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetClockPeriod() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetClockSpeedMode() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetDutyCycle() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetMode() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetPeriphClock() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetRiseTime() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetSMBusPEC() : stm32f1xx_ll_i2c.h
  • LL_I2C_GetTransferDirection() : stm32f1xx_ll_i2c.h
  • LL_I2C_Init() : stm32f1xx_ll_i2c.c
  • LL_I2C_IsActiveFlag_ADD10() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ADDR() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_AF() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_ARLO() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BTF() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_BUSY() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_DUAL() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_GENCALL() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_MSL() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_OVR() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_RXNE() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_SB() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_STOP() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveFlag_TXE() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_ALERT() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_PECERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_SMBDEFAULT() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_SMBHOST() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsActiveSMBusFlag_TIMEOUT() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabled() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledBitPOS() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledClockStretching() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledDMAReq_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledGeneralCall() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_BUF() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_ERR() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_EVT() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_RX() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledIT_TX() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledLastDMA() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledOwnAddress2() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusAlert() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPEC() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsEnabledSMBusPECCompare() : stm32f1xx_ll_i2c.h
  • LL_I2C_IsResetEnabled() : stm32f1xx_ll_i2c.h
  • LL_I2C_ReceiveData8() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetClockPeriod() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetClockSpeedMode() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetDutyCycle() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetMode() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetOwnAddress1() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetOwnAddress2() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetPeriphClock() : stm32f1xx_ll_i2c.h
  • LL_I2C_SetRiseTime() : stm32f1xx_ll_i2c.h
  • LL_I2C_StructInit() : stm32f1xx_ll_i2c.c
  • LL_I2C_TransmitData8() : stm32f1xx_ll_i2c.h
  • LL_I2S_ClearFlag_FRE() : stm32f1xx_ll_i2s.h
  • LL_I2S_ClearFlag_OVR() : stm32f1xx_ll_i2s.h
  • LL_I2S_ClearFlag_UDR() : stm32f1xx_ll_i2s.h
  • LL_I2S_ConfigPrescaler() : stm32f1xx_ll_i2s.c
  • LL_I2S_DeInit() : stm32f1xx_ll_i2s.c
  • LL_I2S_Disable() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableDMAReq_RX() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableDMAReq_TX() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableIT_ERR() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableIT_RXNE() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableIT_TXE() : stm32f1xx_ll_i2s.h
  • LL_I2S_DisableMasterClock() : stm32f1xx_ll_i2s.h
  • LL_I2S_Enable() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableDMAReq_RX() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableDMAReq_TX() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableIT_ERR() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableIT_RXNE() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableIT_TXE() : stm32f1xx_ll_i2s.h
  • LL_I2S_EnableMasterClock() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetClockPolarity() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetDataFormat() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetPrescalerLinear() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetPrescalerParity() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetStandard() : stm32f1xx_ll_i2s.h
  • LL_I2S_GetTransferMode() : stm32f1xx_ll_i2s.h
  • LL_I2S_Init() : stm32f1xx_ll_i2s.c
  • LL_I2S_IsActiveFlag_BSY() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_CHSIDE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_FRE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_OVR() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_RXNE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_TXE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsActiveFlag_UDR() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabled() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledDMAReq_RX() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledDMAReq_TX() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledIT_ERR() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledIT_RXNE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledIT_TXE() : stm32f1xx_ll_i2s.h
  • LL_I2S_IsEnabledMasterClock() : stm32f1xx_ll_i2s.h
  • LL_I2S_ReceiveData16() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetClockPolarity() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetDataFormat() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetPrescalerLinear() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetPrescalerParity() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetStandard() : stm32f1xx_ll_i2s.h
  • LL_I2S_SetTransferMode() : stm32f1xx_ll_i2s.h
  • LL_I2S_StructInit() : stm32f1xx_ll_i2s.c
  • LL_I2S_TransmitData16() : stm32f1xx_ll_i2s.h
  • LL_Init1msTick() : stm32f1xx_ll_utils.c
  • LL_InitTick() : stm32f1xx_ll_utils.h
  • LL_IWDG_DisableWriteAccess() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_Enable() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_EnableWriteAccess() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_GetPrescaler() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_GetReloadCounter() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_PVU() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_IsActiveFlag_RVU() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_IsReady() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_ReloadCounter() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_SetPrescaler() : stm32f1xx_ll_iwdg.h
  • LL_IWDG_SetReloadCounter() : stm32f1xx_ll_iwdg.h
  • LL_LPM_DisableEventOnPend() : stm32f1xx_ll_cortex.h
  • LL_LPM_DisableSleepOnExit() : stm32f1xx_ll_cortex.h
  • LL_LPM_EnableDeepSleep() : stm32f1xx_ll_cortex.h
  • LL_LPM_EnableEventOnPend() : stm32f1xx_ll_cortex.h
  • LL_LPM_EnableSleep() : stm32f1xx_ll_cortex.h
  • LL_LPM_EnableSleepOnExit() : stm32f1xx_ll_cortex.h
  • LL_mDelay() : stm32f1xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSE() : stm32f1xx_ll_utils.c
  • LL_PLL_ConfigSystemClock_HSI() : stm32f1xx_ll_utils.c
  • LL_PWR_ClearFlag_SB() : stm32f1xx_ll_pwr.h
  • LL_PWR_ClearFlag_WU() : stm32f1xx_ll_pwr.h
  • LL_PWR_DeInit() : stm32f1xx_ll_pwr.c
  • LL_PWR_DisableBkUpAccess() : stm32f1xx_ll_pwr.h
  • LL_PWR_DisablePVD() : stm32f1xx_ll_pwr.h
  • LL_PWR_DisableWakeUpPin() : stm32f1xx_ll_pwr.h
  • LL_PWR_EnableBkUpAccess() : stm32f1xx_ll_pwr.h
  • LL_PWR_EnablePVD() : stm32f1xx_ll_pwr.h
  • LL_PWR_EnableWakeUpPin() : stm32f1xx_ll_pwr.h
  • LL_PWR_GetPowerMode() : stm32f1xx_ll_pwr.h
  • LL_PWR_GetPVDLevel() : stm32f1xx_ll_pwr.h
  • LL_PWR_GetRegulModeDS() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_PVDO() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_SB() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsActiveFlag_WU() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsEnabledBkUpAccess() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsEnabledPVD() : stm32f1xx_ll_pwr.h
  • LL_PWR_IsEnabledWakeUpPin() : stm32f1xx_ll_pwr.h
  • LL_PWR_SetPowerMode() : stm32f1xx_ll_pwr.h
  • LL_PWR_SetPVDLevel() : stm32f1xx_ll_pwr.h
  • LL_PWR_SetRegulModeDS() : stm32f1xx_ll_pwr.h
  • LL_RCC_ClearFlag_HSECSS() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_HSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_LSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearFlag_PLLRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_ClearResetFlags() : stm32f1xx_ll_rcc.h
  • LL_RCC_ConfigMCO() : stm32f1xx_ll_rcc.h
  • LL_RCC_DeInit() : stm32f1xx_ll_rcc.c
  • LL_RCC_DisableIT_HSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_DisableIT_HSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_DisableIT_LSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_DisableIT_LSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_DisableIT_PLLRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_DisableRTC() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableIT_HSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableIT_HSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableIT_LSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableIT_LSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableIT_PLLRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_EnableRTC() : stm32f1xx_ll_rcc.h
  • LL_RCC_ForceBackupDomainReset() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetADCClockFreq() : stm32f1xx_ll_rcc.c
  • LL_RCC_GetADCClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetAHBPrescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetAPB1Prescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetAPB2Prescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetRTCClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetSysClkSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_GetSystemClocksFreq() : stm32f1xx_ll_rcc.c
  • LL_RCC_GetUSBClockFreq() : stm32f1xx_ll_rcc.c
  • LL_RCC_GetUSBClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_Disable() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_DisableBypass() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_Enable() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_EnableBypass() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_EnableCSS() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSE_IsReady() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_Disable() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_Enable() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibration() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_GetCalibTrimming() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_IsReady() : stm32f1xx_ll_rcc.h
  • LL_RCC_HSI_SetCalibTrimming() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSECSS() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_HSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_IWDGRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LPWRRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_LSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PINRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PLLRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_PORRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_SFTRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsActiveFlag_WWDGRST() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_HSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSERDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_LSIRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledIT_PLLRDY() : stm32f1xx_ll_rcc.h
  • LL_RCC_IsEnabledRTC() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSE_Disable() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSE_DisableBypass() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSE_Enable() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSE_EnableBypass() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSE_IsReady() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSI_Disable() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSI_Enable() : stm32f1xx_ll_rcc.h
  • LL_RCC_LSI_IsReady() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_ConfigDomain_SYS() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_Disable() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_Enable() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_GetMainSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_GetMultiplicator() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_GetPrediv() : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_IsReady() : stm32f1xx_ll_rcc.h
  • LL_RCC_ReleaseBackupDomainReset() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetADCClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetAHBPrescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetAPB1Prescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetAPB2Prescaler() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetRTCClockSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetSysClkSource() : stm32f1xx_ll_rcc.h
  • LL_RCC_SetUSBClockSource() : stm32f1xx_ll_rcc.h
  • LL_SetSystemCoreClock() : stm32f1xx_ll_utils.c
  • LL_SPI_ClearFlag_CRCERR() : stm32f1xx_ll_spi.h
  • LL_SPI_ClearFlag_MODF() : stm32f1xx_ll_spi.h
  • LL_SPI_ClearFlag_OVR() : stm32f1xx_ll_spi.h
  • LL_SPI_DeInit() : stm32f1xx_ll_spi.c
  • LL_SPI_Disable() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableCRC() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableDMAReq_RX() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableDMAReq_TX() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableIT_ERR() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableIT_RXNE() : stm32f1xx_ll_spi.h
  • LL_SPI_DisableIT_TXE() : stm32f1xx_ll_spi.h
  • LL_SPI_DMA_GetRegAddr() : stm32f1xx_ll_spi.h
  • LL_SPI_Enable() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableCRC() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableDMAReq_RX() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableDMAReq_TX() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableIT_ERR() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableIT_RXNE() : stm32f1xx_ll_spi.h
  • LL_SPI_EnableIT_TXE() : stm32f1xx_ll_spi.h
  • LL_SPI_GetBaudRatePrescaler() : stm32f1xx_ll_spi.h
  • LL_SPI_GetClockPhase() : stm32f1xx_ll_spi.h
  • LL_SPI_GetClockPolarity() : stm32f1xx_ll_spi.h
  • LL_SPI_GetCRCPolynomial() : stm32f1xx_ll_spi.h
  • LL_SPI_GetDataWidth() : stm32f1xx_ll_spi.h
  • LL_SPI_GetMode() : stm32f1xx_ll_spi.h
  • LL_SPI_GetNSSMode() : stm32f1xx_ll_spi.h
  • LL_SPI_GetRxCRC() : stm32f1xx_ll_spi.h
  • LL_SPI_GetTransferBitOrder() : stm32f1xx_ll_spi.h
  • LL_SPI_GetTransferDirection() : stm32f1xx_ll_spi.h
  • LL_SPI_GetTxCRC() : stm32f1xx_ll_spi.h
  • LL_SPI_Init() : stm32f1xx_ll_spi.c
  • LL_SPI_IsActiveFlag_BSY() : stm32f1xx_ll_spi.h
  • LL_SPI_IsActiveFlag_CRCERR() : stm32f1xx_ll_spi.h
  • LL_SPI_IsActiveFlag_MODF() : stm32f1xx_ll_spi.h
  • LL_SPI_IsActiveFlag_OVR() : stm32f1xx_ll_spi.h
  • LL_SPI_IsActiveFlag_RXNE() : stm32f1xx_ll_spi.h
  • LL_SPI_IsActiveFlag_TXE() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabled() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledCRC() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_RX() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledDMAReq_TX() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledIT_ERR() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledIT_RXNE() : stm32f1xx_ll_spi.h
  • LL_SPI_IsEnabledIT_TXE() : stm32f1xx_ll_spi.h
  • LL_SPI_ReceiveData16() : stm32f1xx_ll_spi.h
  • LL_SPI_ReceiveData8() : stm32f1xx_ll_spi.h
  • LL_SPI_SetBaudRatePrescaler() : stm32f1xx_ll_spi.h
  • LL_SPI_SetClockPhase() : stm32f1xx_ll_spi.h
  • LL_SPI_SetClockPolarity() : stm32f1xx_ll_spi.h
  • LL_SPI_SetCRCNext() : stm32f1xx_ll_spi.h
  • LL_SPI_SetCRCPolynomial() : stm32f1xx_ll_spi.h
  • LL_SPI_SetDataWidth() : stm32f1xx_ll_spi.h
  • LL_SPI_SetMode() : stm32f1xx_ll_spi.h
  • LL_SPI_SetNSSMode() : stm32f1xx_ll_spi.h
  • LL_SPI_SetTransferBitOrder() : stm32f1xx_ll_spi.h
  • LL_SPI_SetTransferDirection() : stm32f1xx_ll_spi.h
  • LL_SPI_StructInit() : stm32f1xx_ll_spi.c
  • LL_SPI_TransmitData16() : stm32f1xx_ll_spi.h
  • LL_SPI_TransmitData8() : stm32f1xx_ll_spi.h
  • LL_SYSTICK_DisableIT() : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_EnableIT() : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_GetClkSource() : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_IsActiveCounterFlag() : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_IsEnabledIT() : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_SetClkSource() : stm32f1xx_ll_cortex.h
  • LL_TIM_BDTR_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_BDTR_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_CC_DisableChannel() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_DisablePreload() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_EnableChannel() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_EnablePreload() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_GetDMAReqTrigger() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_IsEnabledChannel() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_SetDMAReqTrigger() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_SetLockLevel() : stm32f1xx_ll_tim.h
  • LL_TIM_CC_SetUpdate() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC1OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC2OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC3OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_CC4OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_ClearFlag_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_ConfigBRK() : stm32f1xx_ll_tim.h
  • LL_TIM_ConfigDMABurst() : stm32f1xx_ll_tim.h
  • LL_TIM_ConfigETR() : stm32f1xx_ll_tim.h
  • LL_TIM_DeInit() : stm32f1xx_ll_tim.c
  • LL_TIM_DisableAllOutputs() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableARRPreload() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableAutomaticOutput() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableBRK() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableDMAReq_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableExternalClock() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableIT_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableMasterSlaveMode() : stm32f1xx_ll_tim.h
  • LL_TIM_DisableUpdateEvent() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableAllOutputs() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableARRPreload() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableAutomaticOutput() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableBRK() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableDMAReq_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableExternalClock() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableIT_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableMasterSlaveMode() : stm32f1xx_ll_tim.h
  • LL_TIM_EnableUpdateEvent() : stm32f1xx_ll_tim.h
  • LL_TIM_ENCODER_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_ENCODER_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_GenerateEvent_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_GenerateEvent_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_GetAutoReload() : stm32f1xx_ll_tim.h
  • LL_TIM_GetClockDivision() : stm32f1xx_ll_tim.h
  • LL_TIM_GetCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_GetCounterMode() : stm32f1xx_ll_tim.h
  • LL_TIM_GetDirection() : stm32f1xx_ll_tim.h
  • LL_TIM_GetOnePulseMode() : stm32f1xx_ll_tim.h
  • LL_TIM_GetPrescaler() : stm32f1xx_ll_tim.h
  • LL_TIM_GetRepetitionCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_GetUpdateSource() : stm32f1xx_ll_tim.h
  • LL_TIM_HALLSENSOR_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_HALLSENSOR_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_IC_Config() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_DisableXORCombination() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_EnableXORCombination() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetActiveInput() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH1() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH2() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH3() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetCaptureCH4() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetFilter() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetPolarity() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_GetPrescaler() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_IC_IsEnabledXORCombination() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_SetActiveInput() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_SetFilter() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_SetPolarity() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_SetPrescaler() : stm32f1xx_ll_tim.h
  • LL_TIM_IC_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_IsActiveFlag_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC1OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC2OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC3OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_CC4OVR() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_IsActiveFlag_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledAllOutputs() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledARRPreload() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledAutomaticOutput() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledDMAReq_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledExternalClock() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_BRK() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC1() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC2() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC3() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_CC4() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_COM() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_TRIG() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledIT_UPDATE() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledMasterSlaveMode() : stm32f1xx_ll_tim.h
  • LL_TIM_IsEnabledUpdateEvent() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_ConfigOutput() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_DisableClear() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_DisableFast() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_DisablePreload() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_EnableClear() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_EnableFast() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_EnablePreload() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH1() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH2() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH3() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetCompareCH4() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetIdleState() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetMode() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_GetPolarity() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_Init() : stm32f1xx_ll_tim.c
  • LL_TIM_OC_IsEnabledClear() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_IsEnabledFast() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_IsEnabledPreload() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH1() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH2() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH3() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetCompareCH4() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetDeadTime() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetIdleState() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetMode() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_SetPolarity() : stm32f1xx_ll_tim.h
  • LL_TIM_OC_StructInit() : stm32f1xx_ll_tim.c
  • LL_TIM_SetAutoReload() : stm32f1xx_ll_tim.h
  • LL_TIM_SetClockDivision() : stm32f1xx_ll_tim.h
  • LL_TIM_SetClockSource() : stm32f1xx_ll_tim.h
  • LL_TIM_SetCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_SetCounterMode() : stm32f1xx_ll_tim.h
  • LL_TIM_SetEncoderMode() : stm32f1xx_ll_tim.h
  • LL_TIM_SetOffStates() : stm32f1xx_ll_tim.h
  • LL_TIM_SetOnePulseMode() : stm32f1xx_ll_tim.h
  • LL_TIM_SetPrescaler() : stm32f1xx_ll_tim.h
  • LL_TIM_SetRepetitionCounter() : stm32f1xx_ll_tim.h
  • LL_TIM_SetSlaveMode() : stm32f1xx_ll_tim.h
  • LL_TIM_SetTriggerInput() : stm32f1xx_ll_tim.h
  • LL_TIM_SetTriggerOutput() : stm32f1xx_ll_tim.h
  • LL_TIM_SetUpdateSource() : stm32f1xx_ll_tim.h
  • LL_TIM_StructInit() : stm32f1xx_ll_tim.c
  • LL_USART_ClearFlag_FE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_IDLE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_LBD() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_nCTS() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_NE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_ORE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_PE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_RXNE() : stm32f1xx_ll_usart.h
  • LL_USART_ClearFlag_TC() : stm32f1xx_ll_usart.h
  • LL_USART_ClockInit() : stm32f1xx_ll_usart.c
  • LL_USART_ClockStructInit() : stm32f1xx_ll_usart.c
  • LL_USART_ConfigAsyncMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigCharacter() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigClock() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigHalfDuplexMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigIrdaMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigLINMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigMultiProcessMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigSmartcardMode() : stm32f1xx_ll_usart.h
  • LL_USART_ConfigSyncMode() : stm32f1xx_ll_usart.h
  • LL_USART_DeInit() : stm32f1xx_ll_usart.c
  • LL_USART_Disable() : stm32f1xx_ll_usart.h
  • LL_USART_DisableCTSHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_DisableDirectionRx() : stm32f1xx_ll_usart.h
  • LL_USART_DisableDirectionTx() : stm32f1xx_ll_usart.h
  • LL_USART_DisableDMAReq_RX() : stm32f1xx_ll_usart.h
  • LL_USART_DisableDMAReq_TX() : stm32f1xx_ll_usart.h
  • LL_USART_DisableHalfDuplex() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIrda() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_CTS() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_ERROR() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_IDLE() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_LBD() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_PE() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_RXNE() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_TC() : stm32f1xx_ll_usart.h
  • LL_USART_DisableIT_TXE() : stm32f1xx_ll_usart.h
  • LL_USART_DisableLIN() : stm32f1xx_ll_usart.h
  • LL_USART_DisableRTSHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_DisableSCLKOutput() : stm32f1xx_ll_usart.h
  • LL_USART_DisableSmartcard() : stm32f1xx_ll_usart.h
  • LL_USART_DisableSmartcardNACK() : stm32f1xx_ll_usart.h
  • LL_USART_DMA_GetRegAddr() : stm32f1xx_ll_usart.h
  • LL_USART_Enable() : stm32f1xx_ll_usart.h
  • LL_USART_EnableCTSHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_EnableDirectionRx() : stm32f1xx_ll_usart.h
  • LL_USART_EnableDirectionTx() : stm32f1xx_ll_usart.h
  • LL_USART_EnableDMAReq_RX() : stm32f1xx_ll_usart.h
  • LL_USART_EnableDMAReq_TX() : stm32f1xx_ll_usart.h
  • LL_USART_EnableHalfDuplex() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIrda() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_CTS() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_ERROR() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_IDLE() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_LBD() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_PE() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_RXNE() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_TC() : stm32f1xx_ll_usart.h
  • LL_USART_EnableIT_TXE() : stm32f1xx_ll_usart.h
  • LL_USART_EnableLIN() : stm32f1xx_ll_usart.h
  • LL_USART_EnableRTSHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_EnableSCLKOutput() : stm32f1xx_ll_usart.h
  • LL_USART_EnableSmartcard() : stm32f1xx_ll_usart.h
  • LL_USART_EnableSmartcardNACK() : stm32f1xx_ll_usart.h
  • LL_USART_GetBaudRate() : stm32f1xx_ll_usart.h
  • LL_USART_GetClockPhase() : stm32f1xx_ll_usart.h
  • LL_USART_GetClockPolarity() : stm32f1xx_ll_usart.h
  • LL_USART_GetDataWidth() : stm32f1xx_ll_usart.h
  • LL_USART_GetHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_GetIrdaPowerMode() : stm32f1xx_ll_usart.h
  • LL_USART_GetIrdaPrescaler() : stm32f1xx_ll_usart.h
  • LL_USART_GetLastClkPulseOutput() : stm32f1xx_ll_usart.h
  • LL_USART_GetLINBrkDetectionLen() : stm32f1xx_ll_usart.h
  • LL_USART_GetNodeAddress() : stm32f1xx_ll_usart.h
  • LL_USART_GetParity() : stm32f1xx_ll_usart.h
  • LL_USART_GetSmartcardGuardTime() : stm32f1xx_ll_usart.h
  • LL_USART_GetSmartcardPrescaler() : stm32f1xx_ll_usart.h
  • LL_USART_GetStopBitsLength() : stm32f1xx_ll_usart.h
  • LL_USART_GetTransferDirection() : stm32f1xx_ll_usart.h
  • LL_USART_GetWakeUpMethod() : stm32f1xx_ll_usart.h
  • LL_USART_Init() : stm32f1xx_ll_usart.c
  • LL_USART_IsActiveFlag_FE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_IDLE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_LBD() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_nCTS() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_NE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_ORE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_PE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_RWU() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_RXNE() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_SBK() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_TC() : stm32f1xx_ll_usart.h
  • LL_USART_IsActiveFlag_TXE() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabled() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_RX() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledDMAReq_TX() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledHalfDuplex() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIrda() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_CTS() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_ERROR() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_IDLE() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_LBD() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_PE() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_RXNE() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_TC() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledIT_TXE() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledLIN() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledSCLKOutput() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledSmartcard() : stm32f1xx_ll_usart.h
  • LL_USART_IsEnabledSmartcardNACK() : stm32f1xx_ll_usart.h
  • LL_USART_ReceiveData8() : stm32f1xx_ll_usart.h
  • LL_USART_ReceiveData9() : stm32f1xx_ll_usart.h
  • LL_USART_RequestBreakSending() : stm32f1xx_ll_usart.h
  • LL_USART_RequestEnterMuteMode() : stm32f1xx_ll_usart.h
  • LL_USART_RequestExitMuteMode() : stm32f1xx_ll_usart.h
  • LL_USART_SetBaudRate() : stm32f1xx_ll_usart.h
  • LL_USART_SetClockPhase() : stm32f1xx_ll_usart.h
  • LL_USART_SetClockPolarity() : stm32f1xx_ll_usart.h
  • LL_USART_SetDataWidth() : stm32f1xx_ll_usart.h
  • LL_USART_SetHWFlowCtrl() : stm32f1xx_ll_usart.h
  • LL_USART_SetIrdaPowerMode() : stm32f1xx_ll_usart.h
  • LL_USART_SetIrdaPrescaler() : stm32f1xx_ll_usart.h
  • LL_USART_SetLastClkPulseOutput() : stm32f1xx_ll_usart.h
  • LL_USART_SetLINBrkDetectionLen() : stm32f1xx_ll_usart.h
  • LL_USART_SetNodeAddress() : stm32f1xx_ll_usart.h
  • LL_USART_SetParity() : stm32f1xx_ll_usart.h
  • LL_USART_SetSmartcardGuardTime() : stm32f1xx_ll_usart.h
  • LL_USART_SetSmartcardPrescaler() : stm32f1xx_ll_usart.h
  • LL_USART_SetStopBitsLength() : stm32f1xx_ll_usart.h
  • LL_USART_SetTransferDirection() : stm32f1xx_ll_usart.h
  • LL_USART_SetWakeUpMethod() : stm32f1xx_ll_usart.h
  • LL_USART_StructInit() : stm32f1xx_ll_usart.c
  • LL_USART_TransmitData8() : stm32f1xx_ll_usart.h
  • LL_USART_TransmitData9() : stm32f1xx_ll_usart.h
  • LL_WWDG_ClearFlag_EWKUP() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_Enable() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_EnableIT_EWKUP() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_GetCounter() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_GetPrescaler() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_GetWindow() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_IsActiveFlag_EWKUP() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_IsEnabled() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_IsEnabledIT_EWKUP() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_SetCounter() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_SetPrescaler() : stm32f1xx_ll_wwdg.h
  • LL_WWDG_SetWindow() : stm32f1xx_ll_wwdg.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- o -

  • OC1Config() : stm32f1xx_ll_tim.c
  • OC2Config() : stm32f1xx_ll_tim.c
  • OC3Config() : stm32f1xx_ll_tim.c
  • OC4Config() : stm32f1xx_ll_tim.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- p -

  • PCD_EP_ISR_Handler() : stm32f1xx_hal_pcd.c
  • PWR_OverloadWfe() : stm32f1xx_hal_pwr.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- r -

  • RCC_GetHCLKClockFreq() : stm32f1xx_ll_rcc.c
  • RCC_GetPCLK1ClockFreq() : stm32f1xx_ll_rcc.c
  • RCC_GetPCLK2ClockFreq() : stm32f1xx_ll_rcc.c
  • RCC_GetSystemClockFreq() : stm32f1xx_ll_rcc.c
  • RCC_PLL_GetFreqDomain_SYS() : stm32f1xx_ll_rcc.c
  • RTC_Bcd2ToByte() : stm32f1xx_hal_rtc.c
  • RTC_ByteToBcd2() : stm32f1xx_hal_rtc.c
  • RTC_DateUpdate() : stm32f1xx_hal_rtc.c
  • RTC_EnterInitMode() : stm32f1xx_hal_rtc.c
  • RTC_ExitInitMode() : stm32f1xx_hal_rtc.c
  • RTC_IsLeapYear() : stm32f1xx_hal_rtc.c
  • RTC_ReadAlarmCounter() : stm32f1xx_hal_rtc.c
  • RTC_ReadTimeCounter() : stm32f1xx_hal_rtc.c
  • RTC_WeekDayNum() : stm32f1xx_hal_rtc.c
  • RTC_WriteAlarmCounter() : stm32f1xx_hal_rtc.c
  • RTC_WriteTimeCounter() : stm32f1xx_hal_rtc.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- s -

  • SMARTCARD_DMAAbortOnError() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMAError() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMAReceiveCplt() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMARxAbortCallback() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMARxOnlyAbortCallback() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMATransmitCplt() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMATxAbortCallback() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_DMATxOnlyAbortCallback() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_EndRxTransfer() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_EndTransmit_IT() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_EndTxTransfer() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_Receive_IT() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_SetConfig() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_Transmit_IT() : stm32f1xx_hal_smartcard.c
  • SMARTCARD_WaitOnFlagUntilTimeout() : stm32f1xx_hal_smartcard.c
  • SPI_2linesRxISR_16BIT() : stm32f1xx_hal_spi.c
  • SPI_2linesRxISR_16BITCRC() : stm32f1xx_hal_spi.c
  • SPI_2linesRxISR_8BIT() : stm32f1xx_hal_spi.c
  • SPI_2linesRxISR_8BITCRC() : stm32f1xx_hal_spi.c
  • SPI_2linesTxISR_16BIT() : stm32f1xx_hal_spi.c
  • SPI_2linesTxISR_8BIT() : stm32f1xx_hal_spi.c
  • SPI_AbortRx_ISR() : stm32f1xx_hal_spi.c
  • SPI_AbortTx_ISR() : stm32f1xx_hal_spi.c
  • SPI_CheckFlag_BSY() : stm32f1xx_hal_spi.c
  • SPI_CloseRx_ISR() : stm32f1xx_hal_spi.c
  • SPI_CloseRxTx_ISR() : stm32f1xx_hal_spi.c
  • SPI_CloseTx_ISR() : stm32f1xx_hal_spi.c
  • SPI_DMAAbortOnError() : stm32f1xx_hal_spi.c
  • SPI_DMAError() : stm32f1xx_hal_spi.c
  • SPI_DMAHalfReceiveCplt() : stm32f1xx_hal_spi.c
  • SPI_DMAHalfTransmitCplt() : stm32f1xx_hal_spi.c
  • SPI_DMAHalfTransmitReceiveCplt() : stm32f1xx_hal_spi.c
  • SPI_DMAReceiveCplt() : stm32f1xx_hal_spi.c
  • SPI_DMARxAbortCallback() : stm32f1xx_hal_spi.c
  • SPI_DMATransmitCplt() : stm32f1xx_hal_spi.c
  • SPI_DMATransmitReceiveCplt() : stm32f1xx_hal_spi.c
  • SPI_DMATxAbortCallback() : stm32f1xx_hal_spi.c
  • SPI_ISCRCErrorValid() : stm32f1xx_hal_spi.c , stm32f1xx_hal_spi.h
  • SPI_RxISR_16BIT() : stm32f1xx_hal_spi.c
  • SPI_RxISR_16BITCRC() : stm32f1xx_hal_spi.c
  • SPI_RxISR_8BIT() : stm32f1xx_hal_spi.c
  • SPI_RxISR_8BITCRC() : stm32f1xx_hal_spi.c
  • SPI_TxISR_16BIT() : stm32f1xx_hal_spi.c
  • SPI_TxISR_8BIT() : stm32f1xx_hal_spi.c
  • SPI_WaitFlagStateUntilTimeout() : stm32f1xx_hal_spi.c
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STM32F103xB HAL User Manual: Globals

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- t -

  • TIM_Base_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_CCxChannelCmd() : stm32f1xx_hal_tim.c
  • TIM_CCxNChannelCmd() : stm32f1xx_hal_tim_ex.c
  • TIM_DMACaptureCplt() : stm32f1xx_hal_tim.c
  • TIM_DMADelayPulseCplt() : stm32f1xx_hal_tim.c
  • TIM_DMAError() : stm32f1xx_hal_tim.c
  • TIM_DMAPeriodElapsedCplt() : stm32f1xx_hal_tim.c
  • TIM_DMATriggerCplt() : stm32f1xx_hal_tim.c
  • TIM_ETR_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_ITRx_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_OC1_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_OC2_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_OC3_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_OC4_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_SlaveTimer_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_TI1_ConfigInputStage() : stm32f1xx_hal_tim.c
  • TIM_TI1_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_TI2_ConfigInputStage() : stm32f1xx_hal_tim.c
  • TIM_TI2_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_TI3_SetConfig() : stm32f1xx_hal_tim.c
  • TIM_TI4_SetConfig() : stm32f1xx_hal_tim.c
  • TIMEx_DMACommutationCplt() : stm32f1xx_hal_tim_ex.h , stm32f1xx_hal_tim_ex.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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  • u

- u -

  • UART_DMAAbortOnError() : stm32f1xx_hal_uart.c
  • UART_DMAError() : stm32f1xx_hal_uart.c
  • UART_DMAReceiveCplt() : stm32f1xx_hal_uart.c
  • UART_DMARxAbortCallback() : stm32f1xx_hal_uart.c
  • UART_DMARxHalfCplt() : stm32f1xx_hal_uart.c
  • UART_DMARxOnlyAbortCallback() : stm32f1xx_hal_uart.c
  • UART_DMATransmitCplt() : stm32f1xx_hal_uart.c
  • UART_DMATxAbortCallback() : stm32f1xx_hal_uart.c
  • UART_DMATxHalfCplt() : stm32f1xx_hal_uart.c
  • UART_DMATxOnlyAbortCallback() : stm32f1xx_hal_uart.c
  • UART_EndRxTransfer() : stm32f1xx_hal_uart.c
  • UART_EndTransmit_IT() : stm32f1xx_hal_uart.c
  • UART_EndTxTransfer() : stm32f1xx_hal_uart.c
  • UART_Receive_IT() : stm32f1xx_hal_uart.c
  • UART_SetConfig() : stm32f1xx_hal_uart.c
  • UART_Transmit_IT() : stm32f1xx_hal_uart.c
  • UART_WaitOnFlagUntilTimeout() : stm32f1xx_hal_uart.c
  • USART_DMAAbortOnError() : stm32f1xx_hal_usart.c
  • USART_DMAError() : stm32f1xx_hal_usart.c
  • USART_DMAReceiveCplt() : stm32f1xx_hal_usart.c
  • USART_DMARxAbortCallback() : stm32f1xx_hal_usart.c
  • USART_DMARxHalfCplt() : stm32f1xx_hal_usart.c
  • USART_DMATransmitCplt() : stm32f1xx_hal_usart.c
  • USART_DMATxAbortCallback() : stm32f1xx_hal_usart.c
  • USART_DMATxHalfCplt() : stm32f1xx_hal_usart.c
  • USART_EndRxTransfer() : stm32f1xx_hal_usart.c
  • USART_EndTransmit_IT() : stm32f1xx_hal_usart.c
  • USART_EndTxTransfer() : stm32f1xx_hal_usart.c
  • USART_Receive_IT() : stm32f1xx_hal_usart.c
  • USART_SetConfig() : stm32f1xx_hal_usart.c
  • USART_Transmit_IT() : stm32f1xx_hal_usart.c
  • USART_TransmitReceive_IT() : stm32f1xx_hal_usart.c
  • USART_WaitOnFlagUntilTimeout() : stm32f1xx_hal_usart.c
  • UTILS_EnablePLLAndSwitchSystem() : stm32f1xx_ll_utils.c
  • UTILS_GetPLLOutputFrequency() : stm32f1xx_ll_utils.c
  • UTILS_PLL_IsBusy() : stm32f1xx_ll_utils.c
  • UTILS_SetFlashLatency() : stm32f1xx_ll_utils.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
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  • CHANNEL_OFFSET_TAB : stm32f1xx_ll_dma.h
  • OFFSET_TAB_CCMRx : stm32f1xx_ll_tim.h
  • pFlash : stm32f1xx_hal_flash.c , stm32f1xx_hal_flash_ex.c
  • SHIFT_TAB_CCxP : stm32f1xx_ll_tim.h
  • SHIFT_TAB_ICxx : stm32f1xx_ll_tim.h
  • SHIFT_TAB_OCxx : stm32f1xx_ll_tim.h
  • SHIFT_TAB_OISx : stm32f1xx_ll_tim.h
  • uCRCErrorWorkaroundCheck : stm32f1xx_hal_spi_ex.c
  • uwTick : stm32f1xx_hal.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • DMA_HandleTypeDef : stm32f1xx_hal_dma.h
  • PCD_EPTypeDef : stm32f1xx_hal_pcd.h
  • PCD_InitTypeDef : stm32f1xx_hal_pcd.h
  • PCD_TypeDef : stm32f1xx_hal_pcd.h
  • SPI_HandleTypeDef : stm32f1xx_hal_spi.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
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  • FLASH_ProcedureTypeDef : stm32f1xx_hal_flash.h
  • GPIO_PinState : stm32f1xx_hal_gpio.h
  • HAL_CAN_StateTypeDef : stm32f1xx_hal_can.h
  • HAL_CRC_StateTypeDef : stm32f1xx_hal_crc.h
  • HAL_DMA_CallbackIDTypeDef : stm32f1xx_hal_dma.h
  • HAL_DMA_LevelCompleteTypeDef : stm32f1xx_hal_dma.h
  • HAL_DMA_StateTypeDef : stm32f1xx_hal_dma.h
  • HAL_I2C_ModeTypeDef : stm32f1xx_hal_i2c.h
  • HAL_I2C_StateTypeDef : stm32f1xx_hal_i2c.h
  • HAL_IRDA_StateTypeDef : stm32f1xx_hal_irda.h
  • HAL_RTCStateTypeDef : stm32f1xx_hal_rtc.h
  • HAL_SMARTCARD_StateTypeDef : stm32f1xx_hal_smartcard.h
  • HAL_SPI_StateTypeDef : stm32f1xx_hal_spi.h
  • HAL_TIM_ActiveChannel : stm32f1xx_hal_tim.h
  • HAL_TIM_StateTypeDef : stm32f1xx_hal_tim.h
  • HAL_UART_StateTypeDef : stm32f1xx_hal_uart.h
  • HAL_USART_StateTypeDef : stm32f1xx_hal_usart.h
  • PCD_EP_BUF_NUM : stm32f1xx_hal_pcd.h
  • PCD_EP_DBUF_DIR : stm32f1xx_hal_pcd.h
  • PCD_StateTypeDef : stm32f1xx_hal_pcd.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
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  • f
  • g
  • h
  • p

- f -

  • FLASH_PROC_MASSERASE : stm32f1xx_hal_flash.h
  • FLASH_PROC_NONE : stm32f1xx_hal_flash.h
  • FLASH_PROC_PAGEERASE : stm32f1xx_hal_flash.h
  • FLASH_PROC_PROGRAMDOUBLEWORD : stm32f1xx_hal_flash.h
  • FLASH_PROC_PROGRAMHALFWORD : stm32f1xx_hal_flash.h
  • FLASH_PROC_PROGRAMWORD : stm32f1xx_hal_flash.h

- g -

  • GPIO_PIN_RESET : stm32f1xx_hal_gpio.h
  • GPIO_PIN_SET : stm32f1xx_hal_gpio.h

- h -

  • HAL_CAN_STATE_BUSY : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_BUSY_RX : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_BUSY_TX_RX : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_ERROR : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_READY : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_RESET : stm32f1xx_hal_can.h
  • HAL_CAN_STATE_TIMEOUT : stm32f1xx_hal_can.h
  • HAL_CRC_STATE_BUSY : stm32f1xx_hal_crc.h
  • HAL_CRC_STATE_ERROR : stm32f1xx_hal_crc.h
  • HAL_CRC_STATE_READY : stm32f1xx_hal_crc.h
  • HAL_CRC_STATE_RESET : stm32f1xx_hal_crc.h
  • HAL_CRC_STATE_TIMEOUT : stm32f1xx_hal_crc.h
  • HAL_DMA_FULL_TRANSFER : stm32f1xx_hal_dma.h
  • HAL_DMA_HALF_TRANSFER : stm32f1xx_hal_dma.h
  • HAL_DMA_STATE_BUSY : stm32f1xx_hal_dma.h
  • HAL_DMA_STATE_READY : stm32f1xx_hal_dma.h
  • HAL_DMA_STATE_RESET : stm32f1xx_hal_dma.h
  • HAL_DMA_STATE_TIMEOUT : stm32f1xx_hal_dma.h
  • HAL_DMA_XFER_ABORT_CB_ID : stm32f1xx_hal_dma.h
  • HAL_DMA_XFER_ALL_CB_ID : stm32f1xx_hal_dma.h
  • HAL_DMA_XFER_CPLT_CB_ID : stm32f1xx_hal_dma.h
  • HAL_DMA_XFER_ERROR_CB_ID : stm32f1xx_hal_dma.h
  • HAL_DMA_XFER_HALFCPLT_CB_ID : stm32f1xx_hal_dma.h
  • HAL_I2C_MODE_MASTER : stm32f1xx_hal_i2c.h
  • HAL_I2C_MODE_MEM : stm32f1xx_hal_i2c.h
  • HAL_I2C_MODE_NONE : stm32f1xx_hal_i2c.h
  • HAL_I2C_MODE_SLAVE : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_ABORT : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_RX_LISTEN : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_BUSY_TX_LISTEN : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_ERROR : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_LISTEN : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_READY : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_RESET : stm32f1xx_hal_i2c.h
  • HAL_I2C_STATE_TIMEOUT : stm32f1xx_hal_i2c.h
  • HAL_IRDA_STATE_BUSY : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_RX : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_BUSY_TX_RX : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_ERROR : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_READY : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_RESET : stm32f1xx_hal_irda.h
  • HAL_IRDA_STATE_TIMEOUT : stm32f1xx_hal_irda.h
  • HAL_PCD_STATE_BUSY : stm32f1xx_hal_pcd.h
  • HAL_PCD_STATE_ERROR : stm32f1xx_hal_pcd.h
  • HAL_PCD_STATE_READY : stm32f1xx_hal_pcd.h
  • HAL_PCD_STATE_RESET : stm32f1xx_hal_pcd.h
  • HAL_PCD_STATE_TIMEOUT : stm32f1xx_hal_pcd.h
  • HAL_RTC_STATE_BUSY : stm32f1xx_hal_rtc.h
  • HAL_RTC_STATE_ERROR : stm32f1xx_hal_rtc.h
  • HAL_RTC_STATE_READY : stm32f1xx_hal_rtc.h
  • HAL_RTC_STATE_RESET : stm32f1xx_hal_rtc.h
  • HAL_RTC_STATE_TIMEOUT : stm32f1xx_hal_rtc.h
  • HAL_SMARTCARD_STATE_BUSY : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_RX : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_BUSY_TX_RX : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_ERROR : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_READY : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_RESET : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_STATE_TIMEOUT : stm32f1xx_hal_smartcard.h
  • HAL_SPI_STATE_BUSY : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_RX : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_BUSY_TX_RX : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_ERROR : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_READY : stm32f1xx_hal_spi.h
  • HAL_SPI_STATE_RESET : stm32f1xx_hal_spi.h
  • HAL_TIM_ACTIVE_CHANNEL_1 : stm32f1xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_2 : stm32f1xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_3 : stm32f1xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_4 : stm32f1xx_hal_tim.h
  • HAL_TIM_ACTIVE_CHANNEL_CLEARED : stm32f1xx_hal_tim.h
  • HAL_TIM_STATE_BUSY : stm32f1xx_hal_tim.h
  • HAL_TIM_STATE_ERROR : stm32f1xx_hal_tim.h
  • HAL_TIM_STATE_READY : stm32f1xx_hal_tim.h
  • HAL_TIM_STATE_RESET : stm32f1xx_hal_tim.h
  • HAL_TIM_STATE_TIMEOUT : stm32f1xx_hal_tim.h
  • HAL_UART_STATE_BUSY : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_BUSY_RX : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_BUSY_TX_RX : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_ERROR : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_READY : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_RESET : stm32f1xx_hal_uart.h
  • HAL_UART_STATE_TIMEOUT : stm32f1xx_hal_uart.h
  • HAL_USART_STATE_BUSY : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_BUSY_RX : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_BUSY_TX_RX : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_ERROR : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_READY : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_RESET : stm32f1xx_hal_usart.h
  • HAL_USART_STATE_TIMEOUT : stm32f1xx_hal_usart.h

- p -

  • PCD_EP_BUF0 : stm32f1xx_hal_pcd.h
  • PCD_EP_BUF1 : stm32f1xx_hal_pcd.h
  • PCD_EP_DBUF_ERR : stm32f1xx_hal_pcd.h
  • PCD_EP_DBUF_IN : stm32f1xx_hal_pcd.h
  • PCD_EP_DBUF_OUT : stm32f1xx_hal_pcd.h
  • PCD_EP_NOBUF : stm32f1xx_hal_pcd.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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  • _
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  • h
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  • m
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  • o
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  • v
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- _ -

  • __ADC_MASK_SHIFT : stm32f1xx_ll_adc.h
  • __ADC_PTR_REG_OFFSET : stm32f1xx_ll_adc.h
  • __HAL_ADC_CLEAR_FLAG : stm32f1xx_hal_adc.h
  • __HAL_ADC_DISABLE : stm32f1xx_hal_adc.h
  • __HAL_ADC_DISABLE_IT : stm32f1xx_hal_adc.h
  • __HAL_ADC_ENABLE : stm32f1xx_hal_adc.h
  • __HAL_ADC_ENABLE_IT : stm32f1xx_hal_adc.h
  • __HAL_ADC_GET_FLAG : stm32f1xx_hal_adc.h
  • __HAL_ADC_GET_IT_SOURCE : stm32f1xx_hal_adc.h
  • __HAL_ADC_RESET_HANDLE_STATE : stm32f1xx_hal_adc.h
  • __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_CAN1_1 : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_CAN1_2 : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_CAN1_3 : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_I2C1_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_I2C1_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_PD01_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_PD01_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SPI1_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SPI1_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SWJ_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SWJ_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SWJ_NOJTAG : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_SWJ_NONJTRST : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM1_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM1_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM1_PARTIAL : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM2_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM2_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM2_PARTIAL_1 : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM2_PARTIAL_2 : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM3_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM3_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM3_PARTIAL : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM4_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_TIM4_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART1_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART1_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART2_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART2_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART3_DISABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART3_ENABLE : stm32f1xx_hal_gpio_ex.h
  • __HAL_AFIO_REMAP_USART3_PARTIAL : stm32f1xx_hal_gpio_ex.h
  • __HAL_CAN_CANCEL_TRANSMIT : stm32f1xx_hal_can.h
  • __HAL_CAN_CLEAR_FLAG : stm32f1xx_hal_can.h
  • __HAL_CAN_DBG_FREEZE : stm32f1xx_hal_can.h
  • __HAL_CAN_DISABLE_IT : stm32f1xx_hal_can.h
  • __HAL_CAN_ENABLE_IT : stm32f1xx_hal_can.h
  • __HAL_CAN_FIFO_RELEASE : stm32f1xx_hal_can.h
  • __HAL_CAN_GET_FLAG : stm32f1xx_hal_can.h
  • __HAL_CAN_GET_IT_SOURCE : stm32f1xx_hal_can.h
  • __HAL_CAN_MSG_PENDING : stm32f1xx_hal_can.h
  • __HAL_CAN_RESET_HANDLE_STATE : stm32f1xx_hal_can.h
  • __HAL_CAN_TRANSMIT_STATUS : stm32f1xx_hal_can.h
  • __HAL_CRC_DR_RESET : stm32f1xx_hal_crc.h
  • __HAL_CRC_GET_IDR : stm32f1xx_hal_crc.h
  • __HAL_CRC_RESET_HANDLE_STATE : stm32f1xx_hal_crc.h
  • __HAL_CRC_SET_IDR : stm32f1xx_hal_crc.h
  • __HAL_DBGMCU_FREEZE_CAN1 : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_IWDG : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM1 : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM2 : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM3 : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_TIM4 : stm32f1xx_hal.h
  • __HAL_DBGMCU_FREEZE_WWDG : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_CAN1 : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_IWDG : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM1 : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM2 : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM3 : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_TIM4 : stm32f1xx_hal.h
  • __HAL_DBGMCU_UNFREEZE_WWDG : stm32f1xx_hal.h
  • __HAL_DMA_CLEAR_FLAG : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_DISABLE : stm32f1xx_hal_dma.h
  • __HAL_DMA_DISABLE_IT : stm32f1xx_hal_dma.h
  • __HAL_DMA_ENABLE : stm32f1xx_hal_dma.h
  • __HAL_DMA_ENABLE_IT : stm32f1xx_hal_dma.h
  • __HAL_DMA_GET_COUNTER : stm32f1xx_hal_dma.h
  • __HAL_DMA_GET_FLAG : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_GET_GI_FLAG_INDEX : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_GET_HT_FLAG_INDEX : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_GET_IT_SOURCE : stm32f1xx_hal_dma.h
  • __HAL_DMA_GET_TC_FLAG_INDEX : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_GET_TE_FLAG_INDEX : stm32f1xx_hal_dma_ex.h
  • __HAL_DMA_RESET_HANDLE_STATE : stm32f1xx_hal_dma.h
  • __HAL_FLASH_CLEAR_FLAG : stm32f1xx_hal_flash_ex.h
  • __HAL_FLASH_DISABLE_IT : stm32f1xx_hal_flash_ex.h
  • __HAL_FLASH_ENABLE_IT : stm32f1xx_hal_flash_ex.h
  • __HAL_FLASH_GET_FLAG : stm32f1xx_hal_flash_ex.h
  • __HAL_FLASH_GET_LATENCY : stm32f1xx_hal_flash.h
  • __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE : stm32f1xx_hal_flash.h
  • __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE : stm32f1xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_DISABLE : stm32f1xx_hal_flash.h
  • __HAL_FLASH_PREFETCH_BUFFER_ENABLE : stm32f1xx_hal_flash.h
  • __HAL_FLASH_SET_LATENCY : stm32f1xx_hal_flash.h
  • __HAL_GPIO_EXTI_CLEAR_FLAG : stm32f1xx_hal_gpio.h
  • __HAL_GPIO_EXTI_CLEAR_IT : stm32f1xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GENERATE_SWIT : stm32f1xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_FLAG : stm32f1xx_hal_gpio.h
  • __HAL_GPIO_EXTI_GET_IT : stm32f1xx_hal_gpio.h
  • __HAL_I2C_CLEAR_ADDRFLAG : stm32f1xx_hal_i2c.h
  • __HAL_I2C_CLEAR_FLAG : stm32f1xx_hal_i2c.h
  • __HAL_I2C_CLEAR_STOPFLAG : stm32f1xx_hal_i2c.h
  • __HAL_I2C_DISABLE : stm32f1xx_hal_i2c.h
  • __HAL_I2C_DISABLE_IT : stm32f1xx_hal_i2c.h
  • __HAL_I2C_ENABLE : stm32f1xx_hal_i2c.h
  • __HAL_I2C_ENABLE_IT : stm32f1xx_hal_i2c.h
  • __HAL_I2C_GET_FLAG : stm32f1xx_hal_i2c.h
  • __HAL_I2C_GET_IT_SOURCE : stm32f1xx_hal_i2c.h
  • __HAL_I2C_RESET_HANDLE_STATE : stm32f1xx_hal_i2c.h
  • __HAL_IRDA_CLEAR_FEFLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_CLEAR_FLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_CLEAR_IDLEFLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_CLEAR_NEFLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_CLEAR_OREFLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_CLEAR_PEFLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_DISABLE : stm32f1xx_hal_irda.h
  • __HAL_IRDA_DISABLE_IT : stm32f1xx_hal_irda.h
  • __HAL_IRDA_ENABLE : stm32f1xx_hal_irda.h
  • __HAL_IRDA_ENABLE_IT : stm32f1xx_hal_irda.h
  • __HAL_IRDA_FLUSH_DRREGISTER : stm32f1xx_hal_irda.h
  • __HAL_IRDA_GET_FLAG : stm32f1xx_hal_irda.h
  • __HAL_IRDA_GET_IT_SOURCE : stm32f1xx_hal_irda.h
  • __HAL_IRDA_RESET_HANDLE_STATE : stm32f1xx_hal_irda.h
  • __HAL_IWDG_RELOAD_COUNTER : stm32f1xx_hal_iwdg.h
  • __HAL_IWDG_START : stm32f1xx_hal_iwdg.h
  • __HAL_PCD_CLEAR_FLAG : stm32f1xx_hal_pcd.h
  • __HAL_PCD_DISABLE : stm32f1xx_hal_pcd.h
  • __HAL_PCD_ENABLE : stm32f1xx_hal_pcd.h
  • __HAL_PCD_GET_FLAG : stm32f1xx_hal_pcd.h
  • __HAL_PWR_CLEAR_FLAG : stm32f1xx_hal_pwr.h
  • __HAL_PWR_GET_FLAG : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_CLEAR_FLAG : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_EVENT : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_IT : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_EVENT : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_IT : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GENERATE_SWIT : stm32f1xx_hal_pwr.h
  • __HAL_PWR_PVD_EXTI_GET_FLAG : stm32f1xx_hal_pwr.h
  • __HAL_RCC_ADC1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ADC2_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC2_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_ADC_CONFIG : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_AFIO_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_AFIO_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_AFIO_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_AFIO_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_AFIO_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_AFIO_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_APB1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_APB1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_APB2_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_APB2_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_FORCE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BACKUPRESET_RELEASE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_BKP_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CAN1_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CAN1_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_CLEAR_IT : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CLEAR_RESET_FLAGS : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CRC_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_CRC_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_DISABLE_IT : stm32f1xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_DMA1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_DMA1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_ENABLE_IT : stm32f1xx_hal_rcc.h
  • __HAL_RCC_FLITF_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_FLITF_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_FLITF_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_FLITF_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_ADC_SOURCE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GET_FLAG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_IT : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_PLL_OSCSOURCE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_RTC_SOURCE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_SYSCLK_SOURCE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GET_USB_SOURCE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOA_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOA_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOA_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOA_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOA_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOB_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOC_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOD_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_GPIOE_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_GPIOE_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_HSE_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_HSE_GET_PREDIV : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_HSE_PREDIV_CONFIG : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST : stm32f1xx_hal_rcc.h
  • __HAL_RCC_HSI_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_HSI_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_I2C2_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_I2C2_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_LSE_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_LSI_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_LSI_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_MCO1_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PLL_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PLL_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PLL_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_PWR_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_RTC_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_RTC_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_RTC_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SPI2_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SPI2_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_SRAM_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SRAM_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SRAM_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SYSCFG_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_SYSCLK_CONFIG : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM2_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM3_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_TIM4_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_TIM4_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART1_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART1_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART1_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART1_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART1_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART2_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_USART3_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USART3_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_CLK_DISABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_CLK_ENABLE : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_CONFIG : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_FORCE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_IS_CLK_DISABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_IS_CLK_ENABLED : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_USB_RELEASE_RESET : stm32f1xx_hal_rcc_ex.h
  • __HAL_RCC_WWDG_CLK_DISABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_WWDG_CLK_ENABLE : stm32f1xx_hal_rcc.h
  • __HAL_RCC_WWDG_FORCE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_DISABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_WWDG_IS_CLK_ENABLED : stm32f1xx_hal_rcc.h
  • __HAL_RCC_WWDG_RELEASE_RESET : stm32f1xx_hal_rcc.h
  • __HAL_RTC_ALARM_CLEAR_FLAG : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_DISABLE_IT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_ENABLE_IT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_CLEAR_FLAG : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_EVENT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_IT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_EVENT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_IT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GENERATE_SWIT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_EXTI_GET_FLAG : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_FLAG : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT : stm32f1xx_hal_rtc.h
  • __HAL_RTC_ALARM_GET_IT_SOURCE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_OVERFLOW_CLEAR_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_OVERFLOW_DISABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_OVERFLOW_ENABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_OVERFLOW_GET_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_OVERFLOW_GET_IT_SOURCE : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_RESET_HANDLE_STATE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_SECOND_CLEAR_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_SECOND_DISABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_SECOND_ENABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_SECOND_GET_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_SECOND_GET_IT_SOURCE : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_CLEAR_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_DISABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_ENABLE_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_FLAG : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_TAMPER_GET_IT_SOURCE : stm32f1xx_hal_rtc_ex.h
  • __HAL_RTC_WRITEPROTECTION_DISABLE : stm32f1xx_hal_rtc.h
  • __HAL_RTC_WRITEPROTECTION_ENABLE : stm32f1xx_hal_rtc.h
  • __HAL_SMARTCARD_CLEAR_FEFLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_FLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_IDLEFLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_NEFLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_OREFLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_CLEAR_PEFLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_DISABLE_IT : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_DISABLE : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_DMA_REQUEST_ENABLE : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_ENABLE_IT : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_FLUSH_DRREGISTER : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_FLAG : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_GET_IT_SOURCE : stm32f1xx_hal_smartcard.h
  • __HAL_SMARTCARD_RESET_HANDLE_STATE : stm32f1xx_hal_smartcard.h
  • __HAL_SPI_CLEAR_CRCERRFLAG : stm32f1xx_hal_spi.h
  • __HAL_SPI_CLEAR_MODFFLAG : stm32f1xx_hal_spi.h
  • __HAL_SPI_CLEAR_OVRFLAG : stm32f1xx_hal_spi.h
  • __HAL_SPI_DISABLE : stm32f1xx_hal_spi.h
  • __HAL_SPI_DISABLE_IT : stm32f1xx_hal_spi.h
  • __HAL_SPI_ENABLE : stm32f1xx_hal_spi.h
  • __HAL_SPI_ENABLE_IT : stm32f1xx_hal_spi.h
  • __HAL_SPI_GET_FLAG : stm32f1xx_hal_spi.h
  • __HAL_SPI_GET_IT_SOURCE : stm32f1xx_hal_spi.h
  • __HAL_SPI_RESET_HANDLE_STATE : stm32f1xx_hal_spi.h
  • __HAL_TIM_CLEAR_FLAG : stm32f1xx_hal_tim.h
  • __HAL_TIM_CLEAR_IT : stm32f1xx_hal_tim.h
  • __HAL_TIM_DISABLE : stm32f1xx_hal_tim.h
  • __HAL_TIM_DISABLE_DMA : stm32f1xx_hal_tim.h
  • __HAL_TIM_DISABLE_IT : stm32f1xx_hal_tim.h
  • __HAL_TIM_DISABLE_OCxPRELOAD : stm32f1xx_hal_tim_ex.h
  • __HAL_TIM_ENABLE : stm32f1xx_hal_tim.h
  • __HAL_TIM_ENABLE_DMA : stm32f1xx_hal_tim.h
  • __HAL_TIM_ENABLE_IT : stm32f1xx_hal_tim.h
  • __HAL_TIM_ENABLE_OCxPRELOAD : stm32f1xx_hal_tim_ex.h
  • __HAL_TIM_GET_AUTORELOAD : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_CLOCKDIVISION : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_COMPARE : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_COUNTER : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_FLAG : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_ICPRESCALER : stm32f1xx_hal_tim.h
  • __HAL_TIM_GET_IT_SOURCE : stm32f1xx_hal_tim.h
  • __HAL_TIM_IS_TIM_COUNTING_DOWN : stm32f1xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE : stm32f1xx_hal_tim.h
  • __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY : stm32f1xx_hal_tim.h
  • __HAL_TIM_MOE_ENABLE : stm32f1xx_hal_tim.h
  • __HAL_TIM_RESET_HANDLE_STATE : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_AUTORELOAD : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_CAPTUREPOLARITY : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_CLOCKDIVISION : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_COMPARE : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_COUNTER : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_ICPRESCALER : stm32f1xx_hal_tim.h
  • __HAL_TIM_SET_PRESCALER : stm32f1xx_hal_tim.h
  • __HAL_TIM_URS_DISABLE : stm32f1xx_hal_tim.h
  • __HAL_TIM_URS_ENABLE : stm32f1xx_hal_tim.h
  • __HAL_UART_CLEAR_FEFLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_CLEAR_FLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_CLEAR_IDLEFLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_CLEAR_NEFLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_CLEAR_OREFLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_CLEAR_PEFLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_DISABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_DISABLE_IT : stm32f1xx_hal_uart.h
  • __HAL_UART_ENABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_ENABLE_IT : stm32f1xx_hal_uart.h
  • __HAL_UART_FLUSH_DRREGISTER : stm32f1xx_hal_uart.h
  • __HAL_UART_GET_FLAG : stm32f1xx_hal_uart.h
  • __HAL_UART_GET_IT_SOURCE : stm32f1xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_DISABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_HWCONTROL_CTS_ENABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_DISABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_HWCONTROL_RTS_ENABLE : stm32f1xx_hal_uart.h
  • __HAL_UART_RESET_HANDLE_STATE : stm32f1xx_hal_uart.h
  • __HAL_USART_CLEAR_FEFLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_CLEAR_FLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_CLEAR_IDLEFLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_CLEAR_NEFLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_CLEAR_OREFLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_CLEAR_PEFLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_DISABLE : stm32f1xx_hal_usart.h
  • __HAL_USART_DISABLE_IT : stm32f1xx_hal_usart.h
  • __HAL_USART_ENABLE : stm32f1xx_hal_usart.h
  • __HAL_USART_ENABLE_IT : stm32f1xx_hal_usart.h
  • __HAL_USART_GET_FLAG : stm32f1xx_hal_usart.h
  • __HAL_USART_GET_IT_SOURCE : stm32f1xx_hal_usart.h
  • __HAL_USART_RESET_HANDLE_STATE : stm32f1xx_hal_usart.h
  • __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_DISABLE_IT : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_IT : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE : stm32f1xx_hal_pcd.h
  • __HAL_USB_WAKEUP_EXTI_GET_FLAG : stm32f1xx_hal_pcd.h
  • __HAL_WWDG_CLEAR_FLAG : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_CLEAR_IT : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_ENABLE_IT : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_GET_FLAG : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT : stm32f1xx_hal_wwdg.h
  • __HAL_WWDG_GET_IT_SOURCE : stm32f1xx_hal_wwdg.h
  • __LL_ADC_ANALOGWD_CHANNEL_GROUP : stm32f1xx_ll_adc.h
  • __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION : stm32f1xx_ll_adc.h
  • __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION : stm32f1xx_ll_adc.h
  • __LL_ADC_CALC_DATA_TO_VOLTAGE : stm32f1xx_ll_adc.h
  • __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS : stm32f1xx_ll_adc.h
  • __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL : stm32f1xx_ll_adc.h
  • __LL_ADC_CHANNEL_TO_DECIMAL_NB : stm32f1xx_ll_adc.h
  • __LL_ADC_COMMON_INSTANCE : stm32f1xx_ll_adc.h
  • __LL_ADC_DECIMAL_NB_TO_CHANNEL : stm32f1xx_ll_adc.h
  • __LL_ADC_DIGITAL_SCALE : stm32f1xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL : stm32f1xx_ll_adc.h
  • __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE : stm32f1xx_ll_adc.h
  • __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE : stm32f1xx_ll_adc.h
  • __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE : stm32f1xx_ll_adc.h
  • __LL_DMA_GET_CHANNEL : stm32f1xx_ll_dma.h
  • __LL_DMA_GET_CHANNEL_INSTANCE : stm32f1xx_ll_dma.h
  • __LL_DMA_GET_INSTANCE : stm32f1xx_ll_dma.h
  • __LL_I2C_10BIT_ADDRESS : stm32f1xx_ll_i2c.h
  • __LL_I2C_10BIT_HEADER_READ : stm32f1xx_ll_i2c.h
  • __LL_I2C_10BIT_HEADER_WRITE : stm32f1xx_ll_i2c.h
  • __LL_I2C_FREQ_HZ_TO_MHZ : stm32f1xx_ll_i2c.h
  • __LL_I2C_FREQ_MHZ_TO_HZ : stm32f1xx_ll_i2c.h
  • __LL_I2C_RISE_TIME : stm32f1xx_ll_i2c.h
  • __LL_I2C_SPEED_FAST_TO_CCR : stm32f1xx_ll_i2c.h
  • __LL_I2C_SPEED_STANDARD_TO_CCR : stm32f1xx_ll_i2c.h
  • __LL_I2C_SPEED_TO_CCR : stm32f1xx_ll_i2c.h
  • __LL_RCC_CALC_HCLK_FREQ : stm32f1xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK1_FREQ : stm32f1xx_ll_rcc.h
  • __LL_RCC_CALC_PCLK2_FREQ : stm32f1xx_ll_rcc.h
  • __LL_RCC_CALC_PLLCLK_FREQ : stm32f1xx_ll_rcc.h
  • __LL_TIM_CALC_ARR : stm32f1xx_ll_tim.h
  • __LL_TIM_CALC_DEADTIME : stm32f1xx_ll_tim.h
  • __LL_TIM_CALC_DELAY : stm32f1xx_ll_tim.h
  • __LL_TIM_CALC_PSC : stm32f1xx_ll_tim.h
  • __LL_TIM_CALC_PULSE : stm32f1xx_ll_tim.h
  • __LL_TIM_GET_ICPSC_RATIO : stm32f1xx_ll_tim.h
  • __LL_USART_DIV_SAMPLING16 : stm32f1xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING16_100 : stm32f1xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8 : stm32f1xx_ll_usart.h
  • __LL_USART_DIV_SAMPLING8_100 : stm32f1xx_ll_usart.h
  • __LL_USART_DIVFRAQ_SAMPLING16 : stm32f1xx_ll_usart.h
  • __LL_USART_DIVFRAQ_SAMPLING8 : stm32f1xx_ll_usart.h
  • __LL_USART_DIVMANT_SAMPLING16 : stm32f1xx_ll_usart.h
  • __LL_USART_DIVMANT_SAMPLING8 : stm32f1xx_ll_usart.h
  • __STM32F1xx_HAL_VERSION : stm32f1xx_hal.c
  • __STM32F1xx_HAL_VERSION_MAIN : stm32f1xx_hal.c
  • __STM32F1xx_HAL_VERSION_RC : stm32f1xx_hal.c
  • __STM32F1xx_HAL_VERSION_SUB1 : stm32f1xx_hal.c
  • __STM32F1xx_HAL_VERSION_SUB2 : stm32f1xx_hal.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- a -

  • ADC1_2_3_EXTERNALTRIG_T1_CC3 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC1_2_3_JSWSTART : stm32f1xx_hal_adc_ex.h
  • ADC1_2_3_SWSTART : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_EXT_IT11 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_T1_CC1 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_T1_CC2 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_T2_CC2 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_T3_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIG_T4_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIGINJEC_T2_CC1 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIGINJEC_T2_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIGINJEC_T3_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC1_2_EXTERNALTRIGINJEC_T4_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC_ANALOGWATCHDOG_ALL_INJEC : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REG : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_ALL_REGINJEC : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_NONE : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_INJEC : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REG : stm32f1xx_hal_adc.h
  • ADC_ANALOGWATCHDOG_SINGLE_REGINJEC : stm32f1xx_hal_adc.h
  • ADC_AWD1_EVENT : stm32f1xx_hal_adc.h
  • ADC_AWD_CR1_CHANNEL_MASK : stm32f1xx_ll_adc.h
  • ADC_AWD_CR1_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_AWD_CR_ALL_CHANNEL_MASK : stm32f1xx_ll_adc.h
  • ADC_AWD_CRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_AWD_EVENT : stm32f1xx_hal_adc.h
  • ADC_AWD_TR1_HIGH_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_AWD_TR1_LOW_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_AWD_TRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_CALIBRATION_TIMEOUT : stm32f1xx_hal_adc_ex.c
  • ADC_CFGR_EXTSEL : stm32f1xx_hal_adc_ex.h
  • ADC_CFGR_JEXTSEL : stm32f1xx_hal_adc_ex.h
  • ADC_CHANNEL_0 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_0_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_0_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_1 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_10 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_10_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_10_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_11 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_11_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_11_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_12 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_12_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_12_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_13 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_13_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_13_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_14 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_14_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_14_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_15 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_15_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_15_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_16 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_16_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_16_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_17 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_17_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_17_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_1_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_1_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_2 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_2_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_2_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_3 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_3_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_3_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_4 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_4_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_4_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_5 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_5_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_5_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_6 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_6_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_6_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_7 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_7_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_7_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_8 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_8_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_8_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_9 : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_9_NUMBER : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_9_SMP : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_2 : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_INTERNAL_CH_MASK : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_MASK : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_SMPRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_SMPx_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_CHANNEL_TEMPSENSOR : stm32f1xx_hal_adc.h
  • ADC_CHANNEL_VREFINT : stm32f1xx_hal_adc.h
  • ADC_CLEAR_ERRORCODE : stm32f1xx_hal_adc.h
  • ADC_COMMON_ADC_OTHER : stm32f1xx_hal_adc_ex.h
  • ADC_CONVCYCLES_MAX_RANGE : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : stm32f1xx_hal_adc.h
  • ADC_CR1_DISCONTINUOUS_NUM : stm32f1xx_hal_adc.h
  • ADC_CR1_DUALMOD_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_CR1_SCAN_SET : stm32f1xx_hal_adc.h
  • ADC_CR2_CONTINUOUS : stm32f1xx_hal_adc.h
  • ADC_DATAALIGN_LEFT : stm32f1xx_hal_adc.h
  • ADC_DATAALIGN_RIGHT : stm32f1xx_hal_adc.h
  • ADC_DISABLE_TIMEOUT : stm32f1xx_hal_adc.c
  • ADC_DUALMODE_ALTERTRIG : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT_INTERLFAST : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_INJECSIMULT_INTERLSLOW : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERLFAST : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_INTERLSLOW : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_ALTERTRIG : stm32f1xx_hal_adc_ex.h
  • ADC_DUALMODE_REGSIMULT_INJECSIMULT : stm32f1xx_hal_adc_ex.h
  • ADC_ENABLE_TIMEOUT : stm32f1xx_hal_adc.c
  • ADC_EXTERNALTRIGCONV_EXT_IT11 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T1_CC1 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T1_CC2 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T1_CC3 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T2_CC2 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T3_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONV_T4_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGCONVEDGE_NONE : stm32f1xx_hal_adc.h
  • ADC_EXTERNALTRIGCONVEDGE_RISING : stm32f1xx_hal_adc.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_NONE : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EDGE_RISING : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_EXT_IT15 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T1_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_CC1 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T2_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T3_CC4 : stm32f1xx_hal_adc_ex.h
  • ADC_EXTERNALTRIGINJECCONV_T4_TRGO : stm32f1xx_hal_adc_ex.h
  • ADC_FLAG_AWD : stm32f1xx_hal_adc.h
  • ADC_FLAG_EOC : stm32f1xx_hal_adc.h
  • ADC_FLAG_JEOC : stm32f1xx_hal_adc.h
  • ADC_FLAG_JSTRT : stm32f1xx_hal_adc.h
  • ADC_FLAG_POSTCONV_ALL : stm32f1xx_hal_adc.h
  • ADC_FLAG_STRT : stm32f1xx_hal_adc.h
  • ADC_INJ_JDRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_INJ_JOFRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_INJ_RANK_ID_JSQR_MASK : stm32f1xx_ll_adc.h
  • ADC_INJECTED_GROUP : stm32f1xx_hal_adc.h
  • ADC_INJECTED_RANK_1 : stm32f1xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_2 : stm32f1xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_3 : stm32f1xx_hal_adc_ex.h
  • ADC_INJECTED_RANK_4 : stm32f1xx_hal_adc_ex.h
  • ADC_INJECTED_SOFTWARE_START : stm32f1xx_hal_adc_ex.h
  • ADC_IS_ENABLE : stm32f1xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_INJECTED : stm32f1xx_hal_adc.h
  • ADC_IS_SOFTWARE_START_REGULAR : stm32f1xx_hal_adc.h
  • ADC_IT_AWD : stm32f1xx_hal_adc.h
  • ADC_IT_EOC : stm32f1xx_hal_adc.h
  • ADC_IT_JEOC : stm32f1xx_hal_adc.h
  • ADC_JDR1_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JDR2_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JDR3_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JDR4_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JOFR1_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JOFR2_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JOFR3_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JOFR4_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_JSQR_JL_SHIFT : stm32f1xx_hal_adc.h
  • ADC_JSQR_RK_JL : stm32f1xx_hal_adc.h
  • ADC_MODE_INDEPENDENT : stm32f1xx_hal_adc_ex.h
  • ADC_MULTI_SLAVE : stm32f1xx_hal_adc_ex.h
  • ADC_MULTIMODE_AUTO_INJECTED : stm32f1xx_hal_adc_ex.h
  • ADC_MULTIMODE_IS_ENABLE : stm32f1xx_hal_adc_ex.h
  • ADC_NONMULTIMODE_OR_MULTIMODEMASTER : stm32f1xx_hal_adc_ex.h
  • ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES : stm32f1xx_hal_adc_ex.c
  • ADC_REG_RANK_10_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_11_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_12_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_13_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_14_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_15_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_16_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_1_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_2_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_3_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_4_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_5_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_6_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_7_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_8_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_9_SQRX_BITOFFSET_POS : stm32f1xx_ll_adc.h
  • ADC_REG_RANK_ID_SQRX_MASK : stm32f1xx_ll_adc.h
  • ADC_REG_SQRX_REGOFFSET_MASK : stm32f1xx_ll_adc.h
  • ADC_REGULAR_GROUP : stm32f1xx_hal_adc.h
  • ADC_REGULAR_INJECTED_GROUP : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_1 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_10 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_11 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_12 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_13 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_14 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_15 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_16 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_2 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_3 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_4 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_5 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_6 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_7 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_8 : stm32f1xx_hal_adc.h
  • ADC_REGULAR_RANK_9 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_13CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_1CYCLE_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_239CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_28CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_41CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_55CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_71CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_7CYCLES_5 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 : stm32f1xx_hal_adc.h
  • ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 : stm32f1xx_hal_adc.h
  • ADC_SCAN_DISABLE : stm32f1xx_hal_adc.h
  • ADC_SCAN_ENABLE : stm32f1xx_hal_adc.h
  • ADC_SMPR1 : stm32f1xx_hal_adc.h
  • ADC_SMPR1_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_SMPR2 : stm32f1xx_hal_adc.h
  • ADC_SMPR2_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_SOFTWARE_START : stm32f1xx_hal_adc_ex.h
  • ADC_SQR1_L_SHIFT : stm32f1xx_hal_adc.h
  • ADC_SQR1_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_SQR1_RK : stm32f1xx_hal_adc.h
  • ADC_SQR2_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_SQR2_RK : stm32f1xx_hal_adc.h
  • ADC_SQR3_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_SQR3_RK : stm32f1xx_hal_adc.h
  • ADC_SQR4_REGOFFSET : stm32f1xx_ll_adc.h
  • ADC_STAB_DELAY_US : stm32f1xx_hal_adc.c
  • ADC_STATE_CLR_SET : stm32f1xx_hal_adc.h
  • ADC_TEMPSENSOR_DELAY_US : stm32f1xx_hal_adc_ex.c , stm32f1xx_hal_adc.c
  • AFIO_EVENTOUT_PIN_0 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_1 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_10 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_11 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_12 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_13 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_14 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_15 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_2 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_3 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_4 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_5 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_6 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_7 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_8 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PIN_9 : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PORT_A : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PORT_B : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PORT_C : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PORT_D : stm32f1xx_hal_gpio_ex.h
  • AFIO_EVENTOUT_PORT_E : stm32f1xx_hal_gpio_ex.h
  • assert_param : stm32f1xx_ll_usart.c , stm32f1xx_hal_conf.h , stm32f1xx_ll_adc.c , stm32f1xx_ll_gpio.c , stm32f1xx_ll_rcc.c , stm32f1xx_ll_exti.c , stm32f1xx_ll_spi.c , stm32f1xx_ll_i2c.c , stm32f1xx_ll_dac.c , stm32f1xx_ll_dma.c , stm32f1xx_ll_tim.c , stm32f1xx_ll_crc.c , stm32f1xx_ll_i2s.c , stm32f1xx_ll_utils.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- b -

  • BDCR_REG_INDEX : stm32f1xx_hal_rcc.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- c -

  • CAN_BS1_10TQ : stm32f1xx_hal_can.h
  • CAN_BS1_11TQ : stm32f1xx_hal_can.h
  • CAN_BS1_12TQ : stm32f1xx_hal_can.h
  • CAN_BS1_13TQ : stm32f1xx_hal_can.h
  • CAN_BS1_14TQ : stm32f1xx_hal_can.h
  • CAN_BS1_15TQ : stm32f1xx_hal_can.h
  • CAN_BS1_16TQ : stm32f1xx_hal_can.h
  • CAN_BS1_1TQ : stm32f1xx_hal_can.h
  • CAN_BS1_2TQ : stm32f1xx_hal_can.h
  • CAN_BS1_3TQ : stm32f1xx_hal_can.h
  • CAN_BS1_4TQ : stm32f1xx_hal_can.h
  • CAN_BS1_5TQ : stm32f1xx_hal_can.h
  • CAN_BS1_6TQ : stm32f1xx_hal_can.h
  • CAN_BS1_7TQ : stm32f1xx_hal_can.h
  • CAN_BS1_8TQ : stm32f1xx_hal_can.h
  • CAN_BS1_9TQ : stm32f1xx_hal_can.h
  • CAN_BS2_1TQ : stm32f1xx_hal_can.h
  • CAN_BS2_2TQ : stm32f1xx_hal_can.h
  • CAN_BS2_3TQ : stm32f1xx_hal_can.h
  • CAN_BS2_4TQ : stm32f1xx_hal_can.h
  • CAN_BS2_5TQ : stm32f1xx_hal_can.h
  • CAN_BS2_6TQ : stm32f1xx_hal_can.h
  • CAN_BS2_7TQ : stm32f1xx_hal_can.h
  • CAN_BS2_8TQ : stm32f1xx_hal_can.h
  • CAN_ESR_BOF_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_ESR_EPV_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_ESR_EWG_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_FIFO0 : stm32f1xx_hal_can.h
  • CAN_FIFO1 : stm32f1xx_hal_can.h
  • CAN_FILTER_FIFO0 : stm32f1xx_hal_can.h
  • CAN_FILTER_FIFO1 : stm32f1xx_hal_can.h
  • CAN_FILTERMODE_IDLIST : stm32f1xx_hal_can.h
  • CAN_FILTERMODE_IDMASK : stm32f1xx_hal_can.h
  • CAN_FILTERSCALE_16BIT : stm32f1xx_hal_can.h
  • CAN_FILTERSCALE_32BIT : stm32f1xx_hal_can.h
  • CAN_FLAG_BOF : stm32f1xx_hal_can.h
  • CAN_FLAG_EPV : stm32f1xx_hal_can.h
  • CAN_FLAG_EWG : stm32f1xx_hal_can.h
  • CAN_FLAG_FF0 : stm32f1xx_hal_can.h
  • CAN_FLAG_FF1 : stm32f1xx_hal_can.h
  • CAN_FLAG_FOV0 : stm32f1xx_hal_can.h
  • CAN_FLAG_FOV1 : stm32f1xx_hal_can.h
  • CAN_FLAG_MASK : stm32f1xx_hal_can.h
  • CAN_FLAG_RQCP0 : stm32f1xx_hal_can.h
  • CAN_FLAG_RQCP1 : stm32f1xx_hal_can.h
  • CAN_FLAG_RQCP2 : stm32f1xx_hal_can.h
  • CAN_FLAG_SLAK : stm32f1xx_hal_can.h
  • CAN_FLAG_SLAKI : stm32f1xx_hal_can.h
  • CAN_FLAG_TME0 : stm32f1xx_hal_can.h
  • CAN_FLAG_TME1 : stm32f1xx_hal_can.h
  • CAN_FLAG_TME2 : stm32f1xx_hal_can.h
  • CAN_FLAG_TXOK0 : stm32f1xx_hal_can.h
  • CAN_FLAG_TXOK1 : stm32f1xx_hal_can.h
  • CAN_FLAG_TXOK2 : stm32f1xx_hal_can.h
  • CAN_FLAG_WKU : stm32f1xx_hal_can.h
  • CAN_ID_EXT : stm32f1xx_hal_can.h
  • CAN_ID_STD : stm32f1xx_hal_can.h
  • CAN_INITSTATUS_FAILED : stm32f1xx_hal_can.h
  • CAN_INITSTATUS_SUCCESS : stm32f1xx_hal_can.h
  • CAN_IT_BOF : stm32f1xx_hal_can.h
  • CAN_IT_EPV : stm32f1xx_hal_can.h
  • CAN_IT_ERR : stm32f1xx_hal_can.h
  • CAN_IT_EWG : stm32f1xx_hal_can.h
  • CAN_IT_FF0 : stm32f1xx_hal_can.h
  • CAN_IT_FF1 : stm32f1xx_hal_can.h
  • CAN_IT_FMP0 : stm32f1xx_hal_can.h
  • CAN_IT_FMP1 : stm32f1xx_hal_can.h
  • CAN_IT_FOV0 : stm32f1xx_hal_can.h
  • CAN_IT_FOV1 : stm32f1xx_hal_can.h
  • CAN_IT_LEC : stm32f1xx_hal_can.h
  • CAN_IT_SLK : stm32f1xx_hal_can.h
  • CAN_IT_TME : stm32f1xx_hal_can.h
  • CAN_IT_WKU : stm32f1xx_hal_can.h
  • CAN_MODE_LOOPBACK : stm32f1xx_hal_can.h
  • CAN_MODE_NORMAL : stm32f1xx_hal_can.h
  • CAN_MODE_SILENT : stm32f1xx_hal_can.h
  • CAN_MODE_SILENT_LOOPBACK : stm32f1xx_hal_can.h
  • CAN_MSR_SLAK_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_MSR_SLAKI_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_MSR_WKU_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_RF0R_FF0_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_RF0R_FOV0_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_RF1R_FF1_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_RF1R_FOV1_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_RTR_DATA : stm32f1xx_hal_can.h
  • CAN_RTR_REMOTE : stm32f1xx_hal_can.h
  • CAN_SJW_1TQ : stm32f1xx_hal_can.h
  • CAN_SJW_2TQ : stm32f1xx_hal_can.h
  • CAN_SJW_3TQ : stm32f1xx_hal_can.h
  • CAN_SJW_4TQ : stm32f1xx_hal_can.h
  • CAN_TIMEOUT_VALUE : stm32f1xx_hal_can.c
  • CAN_TSR_RQCP0_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_RQCP1_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_RQCP2_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TME0_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TME1_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TME2_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TXOK0_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TXOK1_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TSR_TXOK2_BIT_POSITION : stm32f1xx_hal_can.h
  • CAN_TXMAILBOX_0 : stm32f1xx_hal_can.h
  • CAN_TXMAILBOX_1 : stm32f1xx_hal_can.h
  • CAN_TXMAILBOX_2 : stm32f1xx_hal_can.h
  • CAN_TXSTATUS_NOMAILBOX : stm32f1xx_hal_can.h
  • CLOCKSWITCH_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • CR_DBP_BB : stm32f1xx_hal_pwr.c
  • CR_LPSDSR_BB : stm32f1xx_hal_pwr.c
  • CR_PVDE_BB : stm32f1xx_hal_pwr.c
  • CR_REG_INDEX : stm32f1xx_hal_rcc.h , stm32f1xx_hal_rcc_ex.h
  • CSR_EWUP_BB : stm32f1xx_hal_pwr.c
  • CSR_REG_INDEX : stm32f1xx_hal_rcc.h
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STM32F103xB HAL User Manual: Globals

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- d -

  • DBP_BIT_NUMBER : stm32f1xx_hal_pwr.c
  • DMA_CIRCULAR : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL1 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL2 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL3 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL4 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL5 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL6 : stm32f1xx_hal_dma.h
  • DMA_FLAG_GL7 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT1 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT2 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT3 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT4 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT5 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT6 : stm32f1xx_hal_dma.h
  • DMA_FLAG_HT7 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC1 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC2 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC3 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC4 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC5 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC6 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TC7 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE1 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE2 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE3 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE4 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE5 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE6 : stm32f1xx_hal_dma.h
  • DMA_FLAG_TE7 : stm32f1xx_hal_dma.h
  • DMA_IT_HT : stm32f1xx_hal_dma.h
  • DMA_IT_TC : stm32f1xx_hal_dma.h
  • DMA_IT_TE : stm32f1xx_hal_dma.h
  • DMA_MDATAALIGN_BYTE : stm32f1xx_hal_dma.h
  • DMA_MDATAALIGN_HALFWORD : stm32f1xx_hal_dma.h
  • DMA_MDATAALIGN_WORD : stm32f1xx_hal_dma.h
  • DMA_MEMORY_TO_MEMORY : stm32f1xx_hal_dma.h
  • DMA_MEMORY_TO_PERIPH : stm32f1xx_hal_dma.h
  • DMA_MINC_DISABLE : stm32f1xx_hal_dma.h
  • DMA_MINC_ENABLE : stm32f1xx_hal_dma.h
  • DMA_NORMAL : stm32f1xx_hal_dma.h
  • DMA_PDATAALIGN_BYTE : stm32f1xx_hal_dma.h
  • DMA_PDATAALIGN_HALFWORD : stm32f1xx_hal_dma.h
  • DMA_PDATAALIGN_WORD : stm32f1xx_hal_dma.h
  • DMA_PERIPH_TO_MEMORY : stm32f1xx_hal_dma.h
  • DMA_PINC_DISABLE : stm32f1xx_hal_dma.h
  • DMA_PINC_ENABLE : stm32f1xx_hal_dma.h
  • DMA_PRIORITY_HIGH : stm32f1xx_hal_dma.h
  • DMA_PRIORITY_LOW : stm32f1xx_hal_dma.h
  • DMA_PRIORITY_MEDIUM : stm32f1xx_hal_dma.h
  • DMA_PRIORITY_VERY_HIGH : stm32f1xx_hal_dma.h
  • DP83848_PHY_ADDRESS : stm32f1xx_hal_conf.h
  • DT_DELAY_1 : stm32f1xx_ll_tim.h
  • DT_DELAY_2 : stm32f1xx_ll_tim.h
  • DT_DELAY_3 : stm32f1xx_ll_tim.h
  • DT_DELAY_4 : stm32f1xx_ll_tim.h
  • DT_RANGE_1 : stm32f1xx_ll_tim.h
  • DT_RANGE_2 : stm32f1xx_ll_tim.h
  • DT_RANGE_3 : stm32f1xx_ll_tim.h
  • DT_RANGE_4 : stm32f1xx_ll_tim.h
  • DUMMY_DATA : stm32f1xx_hal_usart.c
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- e -

  • ESR_REGISTER_INDEX : stm32f1xx_hal_can.h
  • ETH_RX_BUF_SIZE : stm32f1xx_hal_conf.h
  • ETH_RXBUFNB : stm32f1xx_hal_conf.h
  • ETH_TX_BUF_SIZE : stm32f1xx_hal_conf.h
  • ETH_TXBUFNB : stm32f1xx_hal_conf.h
  • EXTI_MODE : stm32f1xx_hal_gpio.c
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STM32F103xB HAL User Manual: Globals

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- f -

  • FALLING_EDGE : stm32f1xx_hal_gpio.c
  • FLASH_BANK_1 : stm32f1xx_hal_flash_ex.h
  • FLASH_FLAG_BSY : stm32f1xx_hal_flash_ex.h
  • FLASH_FLAG_EOP : stm32f1xx_hal_flash_ex.h
  • FLASH_FLAG_OPTVERR : stm32f1xx_hal_flash_ex.h
  • FLASH_FLAG_PGERR : stm32f1xx_hal_flash_ex.h
  • FLASH_FLAG_WRPERR : stm32f1xx_hal_flash_ex.h
  • FLASH_IT_EOP : stm32f1xx_hal_flash_ex.h
  • FLASH_IT_ERR : stm32f1xx_hal_flash_ex.h
  • FLASH_LATENCY_0 : stm32f1xx_hal_flash.h
  • FLASH_LATENCY_1 : stm32f1xx_hal_flash.h
  • FLASH_LATENCY_2 : stm32f1xx_hal_flash.h
  • FLASH_PAGE_SIZE : stm32f1xx_hal_flash_ex.h
  • FLASH_POSITION_IWDGSW_BIT : stm32f1xx_hal_flash_ex.c
  • FLASH_POSITION_OB_USERDATA0_BIT : stm32f1xx_hal_flash_ex.c
  • FLASH_POSITION_OB_USERDATA1_BIT : stm32f1xx_hal_flash_ex.c
  • FLASH_SIZE_DATA_REGISTER : stm32f1xx_hal_flash_ex.h
  • FLASH_TIMEOUT_VALUE : stm32f1xx_hal_flash.h
  • FLASH_TYPEERASE_MASSERASE : stm32f1xx_hal_flash_ex.h
  • FLASH_TYPEERASE_PAGES : stm32f1xx_hal_flash_ex.h
  • FLASH_TYPEPROGRAM_DOUBLEWORD : stm32f1xx_hal_flash.h
  • FLASH_TYPEPROGRAM_HALFWORD : stm32f1xx_hal_flash.h
  • FLASH_TYPEPROGRAM_WORD : stm32f1xx_hal_flash.h
  • FLASHSIZE_BASE_ADDRESS : stm32f1xx_ll_utils.h
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- g -

  • GPIO_CR_CNF_AF_OUTPUT_OD : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_AF_OUTPUT_PP : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_ANALOG : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_GP_OUTPUT_OD : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_GP_OUTPUT_PP : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_INPUT_FLOATING : stm32f1xx_hal_gpio.c
  • GPIO_CR_CNF_INPUT_PU_PD : stm32f1xx_hal_gpio.c
  • GPIO_CR_MODE_INPUT : stm32f1xx_hal_gpio.c
  • GPIO_GET_INDEX : stm32f1xx_hal_gpio_ex.h
  • GPIO_MODE : stm32f1xx_hal_gpio.c
  • GPIO_MODE_AF_INPUT : stm32f1xx_hal_gpio.h
  • GPIO_MODE_AF_OD : stm32f1xx_hal_gpio.h
  • GPIO_MODE_AF_PP : stm32f1xx_hal_gpio.h
  • GPIO_MODE_ANALOG : stm32f1xx_hal_gpio.h
  • GPIO_MODE_EVT : stm32f1xx_hal_gpio.c
  • GPIO_MODE_EVT_FALLING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_EVT_RISING_FALLING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_INPUT : stm32f1xx_hal_gpio.h
  • GPIO_MODE_IT : stm32f1xx_hal_gpio.c
  • GPIO_MODE_IT_FALLING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_IT_RISING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_IT_RISING_FALLING : stm32f1xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_OD : stm32f1xx_hal_gpio.h
  • GPIO_MODE_OUTPUT_PP : stm32f1xx_hal_gpio.h
  • GPIO_NOPULL : stm32f1xx_hal_gpio.h
  • GPIO_NUMBER : stm32f1xx_hal_gpio.c
  • GPIO_OUTPUT_TYPE : stm32f1xx_hal_gpio.c
  • GPIO_PIN_0 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_1 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_10 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_11 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_12 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_13 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_14 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_15 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_2 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_3 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_4 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_5 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_6 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_7 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_8 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_9 : stm32f1xx_hal_gpio.h
  • GPIO_PIN_All : stm32f1xx_hal_gpio.h
  • GPIO_PIN_MASK : stm32f1xx_hal_gpio.h
  • GPIO_PULLDOWN : stm32f1xx_hal_gpio.h
  • GPIO_PULLUP : stm32f1xx_hal_gpio.h
  • GPIO_SPEED_FREQ_HIGH : stm32f1xx_hal_gpio.h
  • GPIO_SPEED_FREQ_LOW : stm32f1xx_hal_gpio.h
  • GPIO_SPEED_FREQ_MEDIUM : stm32f1xx_hal_gpio.h
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- h -

  • HAL_ADC_ERROR_DMA : stm32f1xx_hal_adc.h
  • HAL_ADC_ERROR_INTERNAL : stm32f1xx_hal_adc.h
  • HAL_ADC_ERROR_NONE : stm32f1xx_hal_adc.h
  • HAL_ADC_ERROR_OVR : stm32f1xx_hal_adc.h
  • HAL_ADC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_ADC_STATE_AWD1 : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_AWD2 : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_AWD3 : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_BUSY_INTERNAL : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_CONFIG : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_DMA : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_ERROR_INTERNAL : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_INJ_BUSY : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_INJ_EOC : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_INJ_JQOVF : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_MULTIMODE_SLAVE : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_READY : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_REG_BUSY : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOC : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_REG_EOSMP : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_REG_OVR : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_RESET : stm32f1xx_hal_adc.h
  • HAL_ADC_STATE_TIMEOUT : stm32f1xx_hal_adc.h
  • HAL_CAN_ERROR_ACK : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_BD : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_BOF : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_BR : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_CRC : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_EPV : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_EWG : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_FOR : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_FOV0 : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_FOV1 : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_NONE : stm32f1xx_hal_can.h
  • HAL_CAN_ERROR_STF : stm32f1xx_hal_can.h
  • HAL_CAN_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_CEC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_CORTEX_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_CRC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_DAC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_DMA_ERROR_NO_XFER : stm32f1xx_hal_dma.h
  • HAL_DMA_ERROR_NONE : stm32f1xx_hal_dma.h
  • HAL_DMA_ERROR_NOT_SUPPORTED : stm32f1xx_hal_dma.h
  • HAL_DMA_ERROR_TE : stm32f1xx_hal_dma.h
  • HAL_DMA_ERROR_TIMEOUT : stm32f1xx_hal_dma.h
  • HAL_DMA_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_ETH_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_FLASH_ERROR_NONE : stm32f1xx_hal_flash.h
  • HAL_FLASH_ERROR_OPTV : stm32f1xx_hal_flash.h
  • HAL_FLASH_ERROR_PROG : stm32f1xx_hal_flash.h
  • HAL_FLASH_ERROR_WRP : stm32f1xx_hal_flash.h
  • HAL_FLASH_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_GPIO_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_HCD_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_I2C_ERROR_AF : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_ARLO : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_BERR : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_DMA : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_NONE : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_OVR : stm32f1xx_hal_i2c.h
  • HAL_I2C_ERROR_TIMEOUT : stm32f1xx_hal_i2c.h
  • HAL_I2C_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_I2S_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_IRDA_ERROR_DMA : stm32f1xx_hal_irda.h
  • HAL_IRDA_ERROR_FE : stm32f1xx_hal_irda.h
  • HAL_IRDA_ERROR_NE : stm32f1xx_hal_irda.h
  • HAL_IRDA_ERROR_NONE : stm32f1xx_hal_irda.h
  • HAL_IRDA_ERROR_ORE : stm32f1xx_hal_irda.h
  • HAL_IRDA_ERROR_PE : stm32f1xx_hal_irda.h
  • HAL_IRDA_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_IWDG_DEFAULT_TIMEOUT : stm32f1xx_hal_iwdg.c
  • HAL_IWDG_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_NAND_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_NOR_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_PCCARD_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_PCD_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_PWR_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_RCC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_RTC_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_RTCEx_TamperTimeStampIRQHandler : stm32f1xx_hal_rtc_ex.h
  • HAL_SD_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_SMARTCARD_ERROR_DMA : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_FE : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NE : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_NONE : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_ORE : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_ERROR_PE : stm32f1xx_hal_smartcard.h
  • HAL_SMARTCARD_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_SPI_ERROR_CRC : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_DMA : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_FLAG : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_FRE : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_MODF : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_NONE : stm32f1xx_hal_spi.h
  • HAL_SPI_ERROR_OVR : stm32f1xx_hal_spi.h
  • HAL_SPI_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_SRAM_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_TIM_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_UART_ERROR_DMA : stm32f1xx_hal_uart.h
  • HAL_UART_ERROR_FE : stm32f1xx_hal_uart.h
  • HAL_UART_ERROR_NE : stm32f1xx_hal_uart.h
  • HAL_UART_ERROR_NONE : stm32f1xx_hal_uart.h
  • HAL_UART_ERROR_ORE : stm32f1xx_hal_uart.h
  • HAL_UART_ERROR_PE : stm32f1xx_hal_uart.h
  • HAL_UART_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_USART_ERROR_DMA : stm32f1xx_hal_usart.h
  • HAL_USART_ERROR_FE : stm32f1xx_hal_usart.h
  • HAL_USART_ERROR_NE : stm32f1xx_hal_usart.h
  • HAL_USART_ERROR_NONE : stm32f1xx_hal_usart.h
  • HAL_USART_ERROR_ORE : stm32f1xx_hal_usart.h
  • HAL_USART_ERROR_PE : stm32f1xx_hal_usart.h
  • HAL_USART_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HAL_WWDG_MODULE_ENABLED : stm32f1xx_hal_conf.h
  • HSE_STARTUP_TIMEOUT : stm32f1xx_hal_conf.h
  • HSE_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • HSE_VALUE : stm32f1xx_hal_conf.h , stm32f1xx_ll_rcc.h
  • HSI_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • HSI_VALUE : stm32f1xx_ll_rcc.h , stm32f1xx_hal_conf.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- i -

  • I2C_10BIT_ADDRESS : stm32f1xx_hal_i2c.h
  • I2C_10BIT_HEADER_READ : stm32f1xx_hal_i2c.h
  • I2C_10BIT_HEADER_WRITE : stm32f1xx_hal_i2c.h
  • I2C_7BIT_ADD_READ : stm32f1xx_hal_i2c.h
  • I2C_7BIT_ADD_WRITE : stm32f1xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_10BIT : stm32f1xx_hal_i2c.h
  • I2C_ADDRESSINGMODE_7BIT : stm32f1xx_hal_i2c.h
  • I2C_DIRECTION_RECEIVE : stm32f1xx_hal_i2c.h
  • I2C_DIRECTION_TRANSMIT : stm32f1xx_hal_i2c.h
  • I2C_DUALADDRESS_DISABLE : stm32f1xx_hal_i2c.h
  • I2C_DUALADDRESS_ENABLE : stm32f1xx_hal_i2c.h
  • I2C_DUTYCYCLE_16_9 : stm32f1xx_hal_i2c.h
  • I2C_DUTYCYCLE_2 : stm32f1xx_hal_i2c.h
  • I2C_FIRST_AND_LAST_FRAME : stm32f1xx_hal_i2c.h
  • I2C_FIRST_FRAME : stm32f1xx_hal_i2c.h
  • I2C_FLAG_ADD10 : stm32f1xx_hal_i2c.h
  • I2C_FLAG_ADDR : stm32f1xx_hal_i2c.h
  • I2C_FLAG_AF : stm32f1xx_hal_i2c.h
  • I2C_FLAG_ARLO : stm32f1xx_hal_i2c.h
  • I2C_FLAG_BERR : stm32f1xx_hal_i2c.h
  • I2C_FLAG_BTF : stm32f1xx_hal_i2c.h
  • I2C_FLAG_BUSY : stm32f1xx_hal_i2c.h
  • I2C_FLAG_DUALF : stm32f1xx_hal_i2c.h
  • I2C_FLAG_GENCALL : stm32f1xx_hal_i2c.h
  • I2C_FLAG_MASK : stm32f1xx_hal_i2c.h
  • I2C_FLAG_MSL : stm32f1xx_hal_i2c.h
  • I2C_FLAG_OVR : stm32f1xx_hal_i2c.h
  • I2C_FLAG_PECERR : stm32f1xx_hal_i2c.h
  • I2C_FLAG_RXNE : stm32f1xx_hal_i2c.h
  • I2C_FLAG_SB : stm32f1xx_hal_i2c.h
  • I2C_FLAG_SMBALERT : stm32f1xx_hal_i2c.h
  • I2C_FLAG_SMBDEFAULT : stm32f1xx_hal_i2c.h
  • I2C_FLAG_SMBHOST : stm32f1xx_hal_i2c.h
  • I2C_FLAG_STOPF : stm32f1xx_hal_i2c.h
  • I2C_FLAG_TIMEOUT : stm32f1xx_hal_i2c.h
  • I2C_FLAG_TRA : stm32f1xx_hal_i2c.h
  • I2C_FLAG_TXE : stm32f1xx_hal_i2c.h
  • I2C_FREQRANGE : stm32f1xx_hal_i2c.h
  • I2C_GENERALCALL_DISABLE : stm32f1xx_hal_i2c.h
  • I2C_GENERALCALL_ENABLE : stm32f1xx_hal_i2c.h
  • I2C_IT_BUF : stm32f1xx_hal_i2c.h
  • I2C_IT_ERR : stm32f1xx_hal_i2c.h
  • I2C_IT_EVT : stm32f1xx_hal_i2c.h
  • I2C_LAST_FRAME : stm32f1xx_hal_i2c.h
  • I2C_MEM_ADD_LSB : stm32f1xx_hal_i2c.h
  • I2C_MEM_ADD_MSB : stm32f1xx_hal_i2c.h
  • I2C_MEMADD_SIZE_16BIT : stm32f1xx_hal_i2c.h
  • I2C_MEMADD_SIZE_8BIT : stm32f1xx_hal_i2c.h
  • I2C_NEXT_FRAME : stm32f1xx_hal_i2c.h
  • I2C_NO_OPTION_FRAME : stm32f1xx_hal_i2c.c
  • I2C_NOSTRETCH_DISABLE : stm32f1xx_hal_i2c.h
  • I2C_NOSTRETCH_ENABLE : stm32f1xx_hal_i2c.h
  • I2C_RISE_TIME : stm32f1xx_hal_i2c.h
  • I2C_SPEED : stm32f1xx_hal_i2c.h
  • I2C_SPEED_FAST : stm32f1xx_hal_i2c.h
  • I2C_SPEED_STANDARD : stm32f1xx_hal_i2c.h
  • I2C_STATE_MASTER_BUSY_RX : stm32f1xx_hal_i2c.c
  • I2C_STATE_MASTER_BUSY_TX : stm32f1xx_hal_i2c.c
  • I2C_STATE_MSK : stm32f1xx_hal_i2c.c
  • I2C_STATE_NONE : stm32f1xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_RX : stm32f1xx_hal_i2c.c
  • I2C_STATE_SLAVE_BUSY_TX : stm32f1xx_hal_i2c.c
  • I2C_TIMEOUT_BUSY_FLAG : stm32f1xx_hal_i2c.c
  • I2C_TIMEOUT_FLAG : stm32f1xx_hal_i2c.c
  • I2S_I2SCFGR_CLEAR_MASK : stm32f1xx_ll_i2s.c
  • I2S_I2SPR_CLEAR_MASK : stm32f1xx_ll_i2s.c
  • IDCODE_DEVID_MASK : stm32f1xx_hal.c
  • IRDA_BRR : stm32f1xx_hal_irda.h
  • IRDA_CR1_REG_INDEX : stm32f1xx_hal_irda.h
  • IRDA_CR2_REG_INDEX : stm32f1xx_hal_irda.h
  • IRDA_CR3_REG_INDEX : stm32f1xx_hal_irda.h
  • IRDA_DIV : stm32f1xx_hal_irda.h
  • IRDA_DIVFRAQ : stm32f1xx_hal_irda.h
  • IRDA_DIVMANT : stm32f1xx_hal_irda.h
  • IRDA_FLAG_FE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_IDLE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_NE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_ORE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_PE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_RXNE : stm32f1xx_hal_irda.h
  • IRDA_FLAG_TC : stm32f1xx_hal_irda.h
  • IRDA_FLAG_TXE : stm32f1xx_hal_irda.h
  • IRDA_IT_CTS : stm32f1xx_hal_irda.h
  • IRDA_IT_ERR : stm32f1xx_hal_irda.h
  • IRDA_IT_IDLE : stm32f1xx_hal_irda.h
  • IRDA_IT_LBD : stm32f1xx_hal_irda.h
  • IRDA_IT_MASK : stm32f1xx_hal_irda.h
  • IRDA_IT_PE : stm32f1xx_hal_irda.h
  • IRDA_IT_RXNE : stm32f1xx_hal_irda.h
  • IRDA_IT_TC : stm32f1xx_hal_irda.h
  • IRDA_IT_TXE : stm32f1xx_hal_irda.h
  • IRDA_MODE_RX : stm32f1xx_hal_irda.h
  • IRDA_MODE_TX : stm32f1xx_hal_irda.h
  • IRDA_MODE_TX_RX : stm32f1xx_hal_irda.h
  • IRDA_PARITY_EVEN : stm32f1xx_hal_irda.h
  • IRDA_PARITY_NONE : stm32f1xx_hal_irda.h
  • IRDA_PARITY_ODD : stm32f1xx_hal_irda.h
  • IRDA_POWERMODE_LOWPOWER : stm32f1xx_hal_irda.h
  • IRDA_POWERMODE_NORMAL : stm32f1xx_hal_irda.h
  • IRDA_WORDLENGTH_8B : stm32f1xx_hal_irda.h
  • IRDA_WORDLENGTH_9B : stm32f1xx_hal_irda.h
  • IS_ADC_ANALOG_WATCHDOG_MODE : stm32f1xx_hal_adc.h
  • IS_ADC_CHANNEL : stm32f1xx_hal_adc.h
  • IS_ADC_CONVERSION_GROUP : stm32f1xx_hal_adc.h
  • IS_ADC_DATA_ALIGN : stm32f1xx_hal_adc.h
  • IS_ADC_EVENT_TYPE : stm32f1xx_hal_adc.h
  • IS_ADC_EXTTRIG : stm32f1xx_hal_adc_ex.h
  • IS_ADC_EXTTRIG_EDGE : stm32f1xx_hal_adc.h
  • IS_ADC_EXTTRIGINJEC : stm32f1xx_hal_adc_ex.h
  • IS_ADC_EXTTRIGINJEC_EDGE : stm32f1xx_hal_adc_ex.h
  • IS_ADC_INJECTED_NB_CONV : stm32f1xx_hal_adc_ex.h
  • IS_ADC_INJECTED_RANK : stm32f1xx_hal_adc_ex.h
  • IS_ADC_MODE : stm32f1xx_hal_adc_ex.h
  • IS_ADC_RANGE : stm32f1xx_hal_adc.h
  • IS_ADC_REGULAR_DISCONT_NUMBER : stm32f1xx_hal_adc.h
  • IS_ADC_REGULAR_NB_CONV : stm32f1xx_hal_adc.h
  • IS_ADC_REGULAR_RANK : stm32f1xx_hal_adc.h
  • IS_ADC_SAMPLE_TIME : stm32f1xx_hal_adc.h
  • IS_ADC_SCAN_MODE : stm32f1xx_hal_adc.h
  • IS_AFIO_EVENTOUT_PIN : stm32f1xx_hal_gpio_ex.h
  • IS_AFIO_EVENTOUT_PORT : stm32f1xx_hal_gpio_ex.h
  • IS_CAN_BANKNUMBER : stm32f1xx_hal_can.h
  • IS_CAN_BS1 : stm32f1xx_hal_can.h
  • IS_CAN_BS2 : stm32f1xx_hal_can.h
  • IS_CAN_DLC : stm32f1xx_hal_can.h
  • IS_CAN_EXTID : stm32f1xx_hal_can.h
  • IS_CAN_FIFO : stm32f1xx_hal_can.h
  • IS_CAN_FILTER_FIFO : stm32f1xx_hal_can.h
  • IS_CAN_FILTER_MODE : stm32f1xx_hal_can.h
  • IS_CAN_FILTER_NUMBER : stm32f1xx_hal_can_ex.h
  • IS_CAN_FILTER_SCALE : stm32f1xx_hal_can.h
  • IS_CAN_IDTYPE : stm32f1xx_hal_can.h
  • IS_CAN_MODE : stm32f1xx_hal_can.h
  • IS_CAN_PRESCALER : stm32f1xx_hal_can.h
  • IS_CAN_RTR : stm32f1xx_hal_can.h
  • IS_CAN_SJW : stm32f1xx_hal_can.h
  • IS_CAN_STDID : stm32f1xx_hal_can.h
  • IS_CAN_TRANSMITMAILBOX : stm32f1xx_hal_can.h
  • IS_DMA_BUFFER_SIZE : stm32f1xx_hal_dma.h
  • IS_DMA_DIRECTION : stm32f1xx_hal_dma.h
  • IS_DMA_MEMORY_DATA_SIZE : stm32f1xx_hal_dma.h
  • IS_DMA_MEMORY_INC_STATE : stm32f1xx_hal_dma.h
  • IS_DMA_MODE : stm32f1xx_hal_dma.h
  • IS_DMA_PERIPHERAL_DATA_SIZE : stm32f1xx_hal_dma.h
  • IS_DMA_PERIPHERAL_INC_STATE : stm32f1xx_hal_dma.h
  • IS_DMA_PRIORITY : stm32f1xx_hal_dma.h
  • IS_FLASH_BANK : stm32f1xx_hal_flash_ex.h
  • IS_FLASH_LATENCY : stm32f1xx_hal_flash.h
  • IS_FLASH_NB_PAGES : stm32f1xx_hal_flash_ex.h
  • IS_FLASH_PROGRAM_ADDRESS : stm32f1xx_hal_flash_ex.h
  • IS_FLASH_TYPEERASE : stm32f1xx_hal_flash_ex.h
  • IS_FLASH_TYPEPROGRAM : stm32f1xx_hal_flash.h
  • IS_GPIO_MODE : stm32f1xx_hal_gpio.h
  • IS_GPIO_PIN : stm32f1xx_hal_gpio.h
  • IS_GPIO_PIN_ACTION : stm32f1xx_hal_gpio.h
  • IS_GPIO_PULL : stm32f1xx_hal_gpio.h
  • IS_GPIO_SPEED : stm32f1xx_hal_gpio.h
  • IS_I2C_ADDRESSING_MODE : stm32f1xx_hal_i2c.h
  • IS_I2C_CLOCK_SPEED : stm32f1xx_hal_i2c.h , stm32f1xx_ll_i2c.c
  • IS_I2C_DUAL_ADDRESS : stm32f1xx_hal_i2c.h
  • IS_I2C_DUTY_CYCLE : stm32f1xx_hal_i2c.h , stm32f1xx_ll_i2c.c
  • IS_I2C_GENERAL_CALL : stm32f1xx_hal_i2c.h
  • IS_I2C_MEMADD_SIZE : stm32f1xx_hal_i2c.h
  • IS_I2C_NO_STRETCH : stm32f1xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS1 : stm32f1xx_hal_i2c.h
  • IS_I2C_OWN_ADDRESS2 : stm32f1xx_hal_i2c.h
  • IS_I2C_TRANSFER_OPTIONS_REQUEST : stm32f1xx_hal_i2c.h
  • IS_IRDA_BAUDRATE : stm32f1xx_hal_irda.h
  • IS_IRDA_MODE : stm32f1xx_hal_irda.h
  • IS_IRDA_PARITY : stm32f1xx_hal_irda.h
  • IS_IRDA_POWERMODE : stm32f1xx_hal_irda.h
  • IS_IRDA_WORD_LENGTH : stm32f1xx_hal_irda.h
  • IS_IWDG_PRESCALER : stm32f1xx_hal_iwdg.h
  • IS_IWDG_RELOAD : stm32f1xx_hal_iwdg.h
  • IS_LL_ADC_DATA_ALIGN : stm32f1xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_INJ_SEQ_SCAN_LENGTH : stm32f1xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_AUTO : stm32f1xx_ll_adc.c
  • IS_LL_ADC_INJ_TRIG_SOURCE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_MULTI_MASTER_SLAVE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_MULTI_MODE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_REG_CONTINUOUS_MODE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_REG_DMA_TRANSFER : stm32f1xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_REG_SEQ_SCAN_LENGTH : stm32f1xx_ll_adc.c
  • IS_LL_ADC_REG_TRIG_SOURCE : stm32f1xx_ll_adc.c
  • IS_LL_ADC_SCAN_SELECTION : stm32f1xx_ll_adc.c
  • IS_LL_ADC_SEQ_SCAN_MODE : stm32f1xx_ll_adc.c
  • IS_LL_DMA_ALL_CHANNEL_INSTANCE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_DIRECTION : stm32f1xx_ll_dma.c
  • IS_LL_DMA_MEMORYDATASIZE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_MEMORYINCMODE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_MODE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_NBDATA : stm32f1xx_ll_dma.c
  • IS_LL_DMA_PERIPHDATASIZE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_PERIPHINCMODE : stm32f1xx_ll_dma.c
  • IS_LL_DMA_PRIORITY : stm32f1xx_ll_dma.c
  • IS_LL_EXTI_LINE_0_31 : stm32f1xx_ll_exti.c
  • IS_LL_EXTI_MODE : stm32f1xx_ll_exti.c
  • IS_LL_EXTI_TRIGGER : stm32f1xx_ll_exti.c
  • IS_LL_GPIO_MODE : stm32f1xx_ll_gpio.c
  • IS_LL_GPIO_OUTPUT_TYPE : stm32f1xx_ll_gpio.c
  • IS_LL_GPIO_PIN : stm32f1xx_ll_gpio.c
  • IS_LL_GPIO_PULL : stm32f1xx_ll_gpio.c
  • IS_LL_GPIO_SPEED : stm32f1xx_ll_gpio.c
  • IS_LL_I2C_OWN_ADDRESS1 : stm32f1xx_ll_i2c.c
  • IS_LL_I2C_OWN_ADDRSIZE : stm32f1xx_ll_i2c.c
  • IS_LL_I2C_PERIPHERAL_MODE : stm32f1xx_ll_i2c.c
  • IS_LL_I2C_TYPE_ACKNOWLEDGE : stm32f1xx_ll_i2c.c
  • IS_LL_I2S_AUDIO_FREQ : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_CPOL : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_DATAFORMAT : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_MCLK_OUTPUT : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_MODE : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_PRESCALER_LINEAR : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_PRESCALER_PARITY : stm32f1xx_ll_i2s.c
  • IS_LL_I2S_STANDARD : stm32f1xx_ll_i2s.c
  • IS_LL_RCC_ADC_CLKSOURCE : stm32f1xx_ll_rcc.c
  • IS_LL_RCC_USB_CLKSOURCE : stm32f1xx_ll_rcc.c
  • IS_LL_SPI_BAUDRATE : stm32f1xx_ll_spi.c
  • IS_LL_SPI_BITORDER : stm32f1xx_ll_spi.c
  • IS_LL_SPI_CRC_POLYNOMIAL : stm32f1xx_ll_spi.c
  • IS_LL_SPI_CRCCALCULATION : stm32f1xx_ll_spi.c
  • IS_LL_SPI_DATAWIDTH : stm32f1xx_ll_spi.c
  • IS_LL_SPI_MODE : stm32f1xx_ll_spi.c
  • IS_LL_SPI_NSS : stm32f1xx_ll_spi.c
  • IS_LL_SPI_PHASE : stm32f1xx_ll_spi.c
  • IS_LL_SPI_POLARITY : stm32f1xx_ll_spi.c
  • IS_LL_SPI_TRANSFER_DIRECTION : stm32f1xx_ll_spi.c
  • IS_LL_TIM_ACTIVEINPUT : stm32f1xx_ll_tim.c
  • IS_LL_TIM_AUTOMATIC_OUTPUT_STATE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_BREAK_POLARITY : stm32f1xx_ll_tim.c
  • IS_LL_TIM_BREAK_STATE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_CLOCKDIVISION : stm32f1xx_ll_tim.c
  • IS_LL_TIM_COUNTERMODE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_ENCODERMODE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_IC_FILTER : stm32f1xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY : stm32f1xx_ll_tim.c
  • IS_LL_TIM_IC_POLARITY_ENCODER : stm32f1xx_ll_tim.c
  • IS_LL_TIM_ICPSC : stm32f1xx_ll_tim.c
  • IS_LL_TIM_LOCK_LEVEL : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OCIDLESTATE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OCMODE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OCPOLARITY : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OCSTATE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OSSI_STATE : stm32f1xx_ll_tim.c
  • IS_LL_TIM_OSSR_STATE : stm32f1xx_ll_tim.c
  • IS_LL_USART_BAUDRATE : stm32f1xx_ll_usart.c
  • IS_LL_USART_CLOCKOUTPUT : stm32f1xx_ll_usart.c
  • IS_LL_USART_CLOCKPHASE : stm32f1xx_ll_usart.c
  • IS_LL_USART_CLOCKPOLARITY : stm32f1xx_ll_usart.c
  • IS_LL_USART_DATAWIDTH : stm32f1xx_ll_usart.c
  • IS_LL_USART_DIRECTION : stm32f1xx_ll_usart.c
  • IS_LL_USART_HWCONTROL : stm32f1xx_ll_usart.c
  • IS_LL_USART_LASTBITCLKOUTPUT : stm32f1xx_ll_usart.c
  • IS_LL_USART_OVERSAMPLING : stm32f1xx_ll_usart.c
  • IS_LL_USART_PARITY : stm32f1xx_ll_usart.c
  • IS_LL_USART_STOPBITS : stm32f1xx_ll_usart.c
  • IS_LL_UTILS_APB1_DIV : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_APB2_DIV : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_HSE_BYPASS : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_HSE_FREQUENCY : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_PLL_FREQUENCY : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_PLLMUL_VALUE : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_PREDIV_VALUE : stm32f1xx_ll_utils.c
  • IS_LL_UTILS_SYSCLK_DIV : stm32f1xx_ll_utils.c
  • IS_NVIC_DEVICE_IRQ : stm32f1xx_hal_cortex.h
  • IS_NVIC_PREEMPTION_PRIORITY : stm32f1xx_hal_cortex.h
  • IS_NVIC_PRIORITY_GROUP : stm32f1xx_hal_cortex.h
  • IS_NVIC_SUB_PRIORITY : stm32f1xx_hal_cortex.h
  • IS_OB_DATA_ADDRESS : stm32f1xx_hal_flash_ex.h
  • IS_OB_IWDG_SOURCE : stm32f1xx_hal_flash_ex.h
  • IS_OB_RDP_LEVEL : stm32f1xx_hal_flash_ex.h
  • IS_OB_STDBY_SOURCE : stm32f1xx_hal_flash_ex.h
  • IS_OB_STOP_SOURCE : stm32f1xx_hal_flash_ex.h
  • IS_OB_WRP : stm32f1xx_hal_flash_ex.h
  • IS_OPTIONBYTE : stm32f1xx_hal_flash_ex.h
  • IS_PCD_ALL_INSTANCE : stm32f1xx_hal_pcd.h
  • IS_PWR_PVD_LEVEL : stm32f1xx_hal_pwr.h
  • IS_PWR_PVD_MODE : stm32f1xx_hal_pwr.h
  • IS_PWR_REGULATOR : stm32f1xx_hal_pwr.h
  • IS_PWR_SLEEP_ENTRY : stm32f1xx_hal_pwr.h
  • IS_PWR_STOP_ENTRY : stm32f1xx_hal_pwr.h
  • IS_PWR_WAKEUP_PIN : stm32f1xx_hal_pwr.h
  • IS_RCC_ADCPLLCLK_DIV : stm32f1xx_hal_rcc_ex.h
  • IS_RCC_CALIBRATION_VALUE : stm32f1xx_hal_rcc.h
  • IS_RCC_CLOCKTYPE : stm32f1xx_hal_rcc.h
  • IS_RCC_HCLK : stm32f1xx_hal_rcc.h
  • IS_RCC_HSE : stm32f1xx_hal_rcc.h
  • IS_RCC_HSE_PREDIV : stm32f1xx_hal_rcc_ex.h
  • IS_RCC_HSI : stm32f1xx_hal_rcc.h
  • IS_RCC_LSE : stm32f1xx_hal_rcc.h
  • IS_RCC_LSI : stm32f1xx_hal_rcc.h
  • IS_RCC_MCO : stm32f1xx_hal_rcc.h
  • IS_RCC_MCO1SOURCE : stm32f1xx_hal_rcc_ex.h
  • IS_RCC_MCODIV : stm32f1xx_hal_rcc.h
  • IS_RCC_OSCILLATORTYPE : stm32f1xx_hal_rcc.h
  • IS_RCC_PCLK : stm32f1xx_hal_rcc.h
  • IS_RCC_PERIPHCLOCK : stm32f1xx_hal_rcc_ex.h
  • IS_RCC_PLL : stm32f1xx_hal_rcc.h
  • IS_RCC_PLL_MUL : stm32f1xx_hal_rcc_ex.h
  • IS_RCC_PLLSOURCE : stm32f1xx_hal_rcc.h
  • IS_RCC_RTCCLKSOURCE : stm32f1xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE : stm32f1xx_hal_rcc.h
  • IS_RCC_SYSCLKSOURCE_STATUS : stm32f1xx_hal_rcc.h
  • IS_RCC_USBPLLCLK_DIV : stm32f1xx_hal_rcc_ex.h
  • IS_RTC_ALARM : stm32f1xx_hal_rtc.h
  • IS_RTC_ASYNCH_PREDIV : stm32f1xx_hal_rtc.h
  • IS_RTC_BKP : stm32f1xx_hal_rtc_ex.h
  • IS_RTC_CALIB_OUTPUT : stm32f1xx_hal_rtc.h
  • IS_RTC_DATE : stm32f1xx_hal_rtc.h
  • IS_RTC_FORMAT : stm32f1xx_hal_rtc.h
  • IS_RTC_HOUR24 : stm32f1xx_hal_rtc.h
  • IS_RTC_MINUTES : stm32f1xx_hal_rtc.h
  • IS_RTC_MONTH : stm32f1xx_hal_rtc.h
  • IS_RTC_SECONDS : stm32f1xx_hal_rtc.h
  • IS_RTC_SMOOTH_CALIB_MINUS : stm32f1xx_hal_rtc_ex.h
  • IS_RTC_TAMPER : stm32f1xx_hal_rtc_ex.h
  • IS_RTC_TAMPER_TRIGGER : stm32f1xx_hal_rtc_ex.h
  • IS_RTC_YEAR : stm32f1xx_hal_rtc.h
  • IS_SMARTCARD_BAUDRATE : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_LASTBIT : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_MODE : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_NACK_STATE : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_PARITY : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_PHASE : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_POLARITY : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_STOPBITS : stm32f1xx_hal_smartcard.h
  • IS_SMARTCARD_WORD_LENGTH : stm32f1xx_hal_smartcard.h
  • IS_SPI_BAUDRATE_PRESCALER : stm32f1xx_hal_spi.h
  • IS_SPI_CPHA : stm32f1xx_hal_spi.h
  • IS_SPI_CPOL : stm32f1xx_hal_spi.h
  • IS_SPI_CRC_CALCULATION : stm32f1xx_hal_spi.h
  • IS_SPI_CRC_POLYNOMIAL : stm32f1xx_hal_spi.h
  • IS_SPI_DATASIZE : stm32f1xx_hal_spi.h
  • IS_SPI_DIRECTION : stm32f1xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES : stm32f1xx_hal_spi.h
  • IS_SPI_DIRECTION_2LINES_OR_1LINE : stm32f1xx_hal_spi.h
  • IS_SPI_FIRST_BIT : stm32f1xx_hal_spi.h
  • IS_SPI_MODE : stm32f1xx_hal_spi.h
  • IS_SPI_NSS : stm32f1xx_hal_spi.h
  • IS_SYSTICK_CLK_SOURCE : stm32f1xx_hal_cortex.h
  • IS_TIM_AUTOMATIC_OUTPUT_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_AUTORELOAD_PRELOAD : stm32f1xx_hal_tim.h
  • IS_TIM_BREAK_POLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_BREAK_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_CHANNELS : stm32f1xx_hal_tim.h
  • IS_TIM_CLEARINPUT_FILTER : stm32f1xx_hal_tim.h
  • IS_TIM_CLEARINPUT_POLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_CLEARINPUT_PRESCALER : stm32f1xx_hal_tim.h
  • IS_TIM_CLEARINPUT_SOURCE : stm32f1xx_hal_tim.h
  • IS_TIM_CLOCKDIVISION_DIV : stm32f1xx_hal_tim.h
  • IS_TIM_CLOCKFILTER : stm32f1xx_hal_tim.h
  • IS_TIM_CLOCKPOLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_CLOCKPRESCALER : stm32f1xx_hal_tim.h
  • IS_TIM_CLOCKSOURCE : stm32f1xx_hal_tim.h
  • IS_TIM_COMPLEMENTARY_CHANNELS : stm32f1xx_hal_tim.h
  • IS_TIM_COUNTER_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_DEADTIME : stm32f1xx_hal_tim_ex.h
  • IS_TIM_DMA_BASE : stm32f1xx_hal_tim.h
  • IS_TIM_DMA_LENGTH : stm32f1xx_hal_tim.h
  • IS_TIM_DMA_SOURCE : stm32f1xx_hal_tim.h
  • IS_TIM_ENCODER_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_EVENT_SOURCE : stm32f1xx_hal_tim.h
  • IS_TIM_FAST_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_IC_FILTER : stm32f1xx_hal_tim.h
  • IS_TIM_IC_POLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_IC_PRESCALER : stm32f1xx_hal_tim.h
  • IS_TIM_IC_SELECTION : stm32f1xx_hal_tim.h
  • IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION : stm32f1xx_hal_tim.h
  • IS_TIM_LOCK_LEVEL : stm32f1xx_hal_tim.h
  • IS_TIM_MSM_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_OC_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_OC_POLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_OCIDLE_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_OCN_POLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_OCNIDLE_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_OPM_CHANNELS : stm32f1xx_hal_tim.h
  • IS_TIM_OPM_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_OSSI_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_OSSR_STATE : stm32f1xx_hal_tim.h
  • IS_TIM_PWM_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_SLAVE_MODE : stm32f1xx_hal_tim.h
  • IS_TIM_TI1SELECTION : stm32f1xx_hal_tim.h
  • IS_TIM_TRGO_SOURCE : stm32f1xx_hal_tim.h
  • IS_TIM_TRIGGER_SELECTION : stm32f1xx_hal_tim.h
  • IS_TIM_TRIGGERFILTER : stm32f1xx_hal_tim.h
  • IS_TIM_TRIGGERPOLARITY : stm32f1xx_hal_tim.h
  • IS_TIM_TRIGGERPRESCALER : stm32f1xx_hal_tim.h
  • IS_UART_ADDRESS : stm32f1xx_hal_uart.h
  • IS_UART_BAUDRATE : stm32f1xx_hal_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : stm32f1xx_hal_uart.h
  • IS_UART_LIN_BREAK_DETECT_LENGTH : stm32f1xx_hal_uart.h
  • IS_UART_LIN_OVERSAMPLING : stm32f1xx_hal_uart.h
  • IS_UART_LIN_WORD_LENGTH : stm32f1xx_hal_uart.h
  • IS_UART_MODE : stm32f1xx_hal_uart.h
  • IS_UART_PARITY : stm32f1xx_hal_uart.h
  • IS_UART_STATE : stm32f1xx_hal_uart.h
  • IS_UART_STOPBITS : stm32f1xx_hal_uart.h
  • IS_UART_WAKEUPMETHOD : stm32f1xx_hal_uart.h
  • IS_UART_WORD_LENGTH : stm32f1xx_hal_uart.h
  • IS_USART_BAUDRATE : stm32f1xx_hal_usart.h
  • IS_USART_CLOCK : stm32f1xx_hal_usart.h
  • IS_USART_LASTBIT : stm32f1xx_hal_usart.h
  • IS_USART_MODE : stm32f1xx_hal_usart.h
  • IS_USART_NACK_STATE : stm32f1xx_hal_usart.h
  • IS_USART_PARITY : stm32f1xx_hal_usart.h
  • IS_USART_PHASE : stm32f1xx_hal_usart.h
  • IS_USART_POLARITY : stm32f1xx_hal_usart.h
  • IS_USART_STOPBITS : stm32f1xx_hal_usart.h
  • IS_USART_WORD_LENGTH : stm32f1xx_hal_usart.h
  • IS_WRPSTATE : stm32f1xx_hal_flash_ex.h
  • IS_WWDG_COUNTER : stm32f1xx_hal_wwdg.h
  • IS_WWDG_EWI_MODE : stm32f1xx_hal_wwdg.h
  • IS_WWDG_PRESCALER : stm32f1xx_hal_wwdg.h
  • IS_WWDG_WINDOW : stm32f1xx_hal_wwdg.h
  • IWDG_DISABLE_WRITE_ACCESS : stm32f1xx_hal_iwdg.h
  • IWDG_ENABLE_WRITE_ACCESS : stm32f1xx_hal_iwdg.h
  • IWDG_KEY_ENABLE : stm32f1xx_hal_iwdg.h
  • IWDG_KEY_RELOAD : stm32f1xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_DISABLE : stm32f1xx_hal_iwdg.h
  • IWDG_KEY_WRITE_ACCESS_ENABLE : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_128 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_16 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_256 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_32 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_4 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_64 : stm32f1xx_hal_iwdg.h
  • IWDG_PRESCALER_8 : stm32f1xx_hal_iwdg.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- l -

  • LL_ADC_AWD1 : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_ALL_CHANNELS_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CH_VREFINT_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_0_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_10_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_11_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_12_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_13_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_14_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_15_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_16_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_17_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_1_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_2_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_3_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_4_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_5_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_6_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_7_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_8_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_CHANNEL_9_REG_INJ : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_HIGH : stm32f1xx_ll_adc.h
  • LL_ADC_AWD_THRESHOLD_LOW : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_0 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_1 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_10 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_11 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_12 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_13 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_14 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_15 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_16 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_17 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_2 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_3 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_4 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_5 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_6 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_7 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_8 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_9 : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_TEMPSENSOR : stm32f1xx_ll_adc.h
  • LL_ADC_CHANNEL_VREFINT : stm32f1xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_LEFT : stm32f1xx_ll_adc.h
  • LL_ADC_DATA_ALIGN_RIGHT : stm32f1xx_ll_adc.h
  • LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES : stm32f1xx_ll_adc.h
  • LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES : stm32f1xx_ll_adc.h
  • LL_ADC_DELAY_TEMPSENSOR_STAB_US : stm32f1xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA : stm32f1xx_ll_adc.h
  • LL_ADC_DMA_REG_REGULAR_DATA_MULTI : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_AWD1 : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_MST : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_AWD1_SLV : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_EOS : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_EOS_MST : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_EOS_SLV : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_JEOS : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_MST : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_JEOS_SLV : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_JSTRT : stm32f1xx_ll_adc.h
  • LL_ADC_FLAG_STRT : stm32f1xx_ll_adc.h
  • LL_ADC_GROUP_INJECTED : stm32f1xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR : stm32f1xx_ll_adc.h
  • LL_ADC_GROUP_REGULAR_INJECTED : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_RANK_1 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_RANK_2 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_RANK_3 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_RANK_4 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_1RANK : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_DISCONT_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_RISING : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_CH4 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM1_TRGO : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_CH1 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM2_TRGO : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM3_CH4 : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_EXT_TIM4_TRGO : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_FROM_GRP_REGULAR : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_INDEPENDENT : stm32f1xx_ll_adc.h
  • LL_ADC_INJ_TRIG_SOFTWARE : stm32f1xx_ll_adc.h
  • LL_ADC_IT_AWD1 : stm32f1xx_ll_adc.h
  • LL_ADC_IT_EOS : stm32f1xx_ll_adc.h
  • LL_ADC_IT_JEOS : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_ALTERN : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_INJ_SIMULT : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTERL_FAST : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTERL_SLOW : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_DUAL_REG_SIMULT : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_INDEPENDENT : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_MASTER : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_MASTER_SLAVE : stm32f1xx_ll_adc.h
  • LL_ADC_MULTI_SLAVE : stm32f1xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_NONE : stm32f1xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_TEMPSENSOR : stm32f1xx_ll_adc.h
  • LL_ADC_PATH_INTERNAL_VREFINT : stm32f1xx_ll_adc.h
  • LL_ADC_ReadReg : stm32f1xx_ll_adc.h
  • LL_ADC_REG_CONV_CONTINUOUS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_CONV_SINGLE : stm32f1xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_NONE : stm32f1xx_ll_adc.h
  • LL_ADC_REG_DMA_TRANSFER_UNLIMITED : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_1 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_10 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_11 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_12 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_13 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_14 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_15 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_16 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_2 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_3 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_4 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_5 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_6 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_7 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_8 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_RANK_9 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_1RANK : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_2RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_3RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_4RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_5RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_6RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_7RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_8RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_DISCONT_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_EXTI_LINE11 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_RISING : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH1 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH2 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM1_CH3 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM2_CH2 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM3_TRGO : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_EXT_TIM4_CH4 : stm32f1xx_ll_adc.h
  • LL_ADC_REG_TRIG_SOFTWARE : stm32f1xx_ll_adc.h
  • LL_ADC_RESOLUTION_12B : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_13CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_1CYCLE_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_239CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_28CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_41CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_55CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_71CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SAMPLINGTIME_7CYCLES_5 : stm32f1xx_ll_adc.h
  • LL_ADC_SEQ_SCAN_DISABLE : stm32f1xx_ll_adc.h
  • LL_ADC_SEQ_SCAN_ENABLE : stm32f1xx_ll_adc.h
  • LL_ADC_WriteReg : stm32f1xx_ll_adc.h
  • LL_AHB1_GRP1_PERIPH_ALL : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_CRC : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_DMA1 : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_FLASH : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SDIO : stm32f1xx_ll_bus.h
  • LL_AHB1_GRP1_PERIPH_SRAM : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_ALL : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_BKP : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_CAN1 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C1 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_I2C2 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_PWR : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_SPI2 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM2 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM3 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_TIM4 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART2 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USART3 : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_USB : stm32f1xx_ll_bus.h
  • LL_APB1_GRP1_PERIPH_WWDG : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ADC1 : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ADC2 : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_AFIO : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_ALL : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_GPIOA : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_GPIOB : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_GPIOC : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_GPIOD : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_GPIOE : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_SPI1 : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_TIM1 : stm32f1xx_ll_bus.h
  • LL_APB2_GRP1_PERIPH_USART1 : stm32f1xx_ll_bus.h
  • LL_CRC_ReadReg : stm32f1xx_ll_crc.h
  • LL_CRC_WriteReg : stm32f1xx_ll_crc.h
  • LL_DBGMCU_APB1_GRP1_CAN1_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C1_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_I2C2_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_IWDG_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_RTC_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM2_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM3_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_TIM4_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB1_GRP1_WWDG_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_APB2_GRP1_TIM1_STOP : stm32f1xx_ll_system.h
  • LL_DBGMCU_TRACE_ASYNCH : stm32f1xx_ll_system.h
  • LL_DBGMCU_TRACE_NONE : stm32f1xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE1 : stm32f1xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE2 : stm32f1xx_ll_system.h
  • LL_DBGMCU_TRACE_SYNCH_SIZE4 : stm32f1xx_ll_system.h
  • LL_DMA_CCR_HTIE : stm32f1xx_ll_dma.h
  • LL_DMA_CCR_TCIE : stm32f1xx_ll_dma.h
  • LL_DMA_CCR_TEIE : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_1 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_2 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_3 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_4 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_5 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_6 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_7 : stm32f1xx_ll_dma.h
  • LL_DMA_CHANNEL_ALL : stm32f1xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_MEMORY : stm32f1xx_ll_dma.h
  • LL_DMA_DIRECTION_MEMORY_TO_PERIPH : stm32f1xx_ll_dma.h
  • LL_DMA_DIRECTION_PERIPH_TO_MEMORY : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CGIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CHTIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTCIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_IFCR_CTEIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_GIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_HTIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TCIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF1 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF2 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF3 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF4 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF5 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF6 : stm32f1xx_ll_dma.h
  • LL_DMA_ISR_TEIF7 : stm32f1xx_ll_dma.h
  • LL_DMA_MDATAALIGN_BYTE : stm32f1xx_ll_dma.h
  • LL_DMA_MDATAALIGN_HALFWORD : stm32f1xx_ll_dma.h
  • LL_DMA_MDATAALIGN_WORD : stm32f1xx_ll_dma.h
  • LL_DMA_MEMORY_INCREMENT : stm32f1xx_ll_dma.h
  • LL_DMA_MEMORY_NOINCREMENT : stm32f1xx_ll_dma.h
  • LL_DMA_MODE_CIRCULAR : stm32f1xx_ll_dma.h
  • LL_DMA_MODE_NORMAL : stm32f1xx_ll_dma.h
  • LL_DMA_PDATAALIGN_BYTE : stm32f1xx_ll_dma.h
  • LL_DMA_PDATAALIGN_HALFWORD : stm32f1xx_ll_dma.h
  • LL_DMA_PDATAALIGN_WORD : stm32f1xx_ll_dma.h
  • LL_DMA_PERIPH_INCREMENT : stm32f1xx_ll_dma.h
  • LL_DMA_PERIPH_NOINCREMENT : stm32f1xx_ll_dma.h
  • LL_DMA_PRIORITY_HIGH : stm32f1xx_ll_dma.h
  • LL_DMA_PRIORITY_LOW : stm32f1xx_ll_dma.h
  • LL_DMA_PRIORITY_MEDIUM : stm32f1xx_ll_dma.h
  • LL_DMA_PRIORITY_VERYHIGH : stm32f1xx_ll_dma.h
  • LL_DMA_ReadReg : stm32f1xx_ll_dma.h
  • LL_DMA_WriteReg : stm32f1xx_ll_dma.h
  • LL_EXTI_LINE_0 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_1 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_10 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_11 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_12 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_13 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_14 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_15 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_16 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_17 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_18 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_2 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_3 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_4 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_5 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_6 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_7 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_8 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_9 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_ALL : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_ALL_0_31 : stm32f1xx_ll_exti.h
  • LL_EXTI_LINE_NONE : stm32f1xx_ll_exti.h
  • LL_EXTI_MODE_EVENT : stm32f1xx_ll_exti.h
  • LL_EXTI_MODE_IT : stm32f1xx_ll_exti.h
  • LL_EXTI_MODE_IT_EVENT : stm32f1xx_ll_exti.h
  • LL_EXTI_ReadReg : stm32f1xx_ll_exti.h
  • LL_EXTI_TRIGGER_FALLING : stm32f1xx_ll_exti.h
  • LL_EXTI_TRIGGER_NONE : stm32f1xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING : stm32f1xx_ll_exti.h
  • LL_EXTI_TRIGGER_RISING_FALLING : stm32f1xx_ll_exti.h
  • LL_EXTI_WriteReg : stm32f1xx_ll_exti.h
  • LL_FLASH_LATENCY_0 : stm32f1xx_ll_system.h
  • LL_FLASH_LATENCY_1 : stm32f1xx_ll_system.h
  • LL_FLASH_LATENCY_2 : stm32f1xx_ll_system.h
  • LL_GPIO_AF_EVENTOUT_PIN_0 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_1 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_10 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_11 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_12 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_13 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_14 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_15 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_2 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_3 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_4 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_5 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_6 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_7 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_8 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PIN_9 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PORT_A : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PORT_B : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PORT_C : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PORT_D : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EVENTOUT_PORT_E : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE0 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE1 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE10 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE11 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE12 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE13 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE14 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE15 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE2 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE3 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE4 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE5 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE6 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE7 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE8 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_LINE9 : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTA : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTB : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTC : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTD : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTE : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTF : stm32f1xx_ll_gpio.h
  • LL_GPIO_AF_EXTI_PORTG : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_ALTERNATE : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_ANALOG : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_FLOATING : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_INPUT : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT_10MHz : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT_2MHz : stm32f1xx_ll_gpio.h
  • LL_GPIO_MODE_OUTPUT_50MHz : stm32f1xx_ll_gpio.h
  • LL_GPIO_OUTPUT_OPENDRAIN : stm32f1xx_ll_gpio.h
  • LL_GPIO_OUTPUT_PUSHPULL : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_0 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_1 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_10 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_11 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_12 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_13 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_14 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_15 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_2 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_3 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_4 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_5 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_6 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_7 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_8 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_9 : stm32f1xx_ll_gpio.h
  • LL_GPIO_PIN_ALL : stm32f1xx_ll_gpio.h
  • LL_GPIO_PULL_DOWN : stm32f1xx_ll_gpio.h
  • LL_GPIO_PULL_UP : stm32f1xx_ll_gpio.h
  • LL_GPIO_ReadReg : stm32f1xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_HIGH : stm32f1xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_LOW : stm32f1xx_ll_gpio.h
  • LL_GPIO_SPEED_FREQ_MEDIUM : stm32f1xx_ll_gpio.h
  • LL_GPIO_WriteReg : stm32f1xx_ll_gpio.h
  • LL_HANDLER_FAULT_BUS : stm32f1xx_ll_cortex.h
  • LL_HANDLER_FAULT_MEM : stm32f1xx_ll_cortex.h
  • LL_HANDLER_FAULT_USG : stm32f1xx_ll_cortex.h
  • LL_I2C_ACK : stm32f1xx_ll_i2c.h
  • LL_I2C_CLOCK_SPEED_FAST_MODE : stm32f1xx_ll_i2c.h
  • LL_I2C_CLOCK_SPEED_STANDARD_MODE : stm32f1xx_ll_i2c.h
  • LL_I2C_CR2_ITBUFEN : stm32f1xx_ll_i2c.h
  • LL_I2C_CR2_ITERREN : stm32f1xx_ll_i2c.h
  • LL_I2C_CR2_ITEVTEN : stm32f1xx_ll_i2c.h
  • LL_I2C_DIRECTION_READ : stm32f1xx_ll_i2c.h
  • LL_I2C_DIRECTION_WRITE : stm32f1xx_ll_i2c.h
  • LL_I2C_DUTYCYCLE_16_9 : stm32f1xx_ll_i2c.h
  • LL_I2C_DUTYCYCLE_2 : stm32f1xx_ll_i2c.h
  • LL_I2C_MAX_SPEED_FAST : stm32f1xx_ll_i2c.h
  • LL_I2C_MAX_SPEED_STANDARD : stm32f1xx_ll_i2c.h
  • LL_I2C_MODE_I2C : stm32f1xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE : stm32f1xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_DEVICE_ARP : stm32f1xx_ll_i2c.h
  • LL_I2C_MODE_SMBUS_HOST : stm32f1xx_ll_i2c.h
  • LL_I2C_NACK : stm32f1xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_10BIT : stm32f1xx_ll_i2c.h
  • LL_I2C_OWNADDRESS1_7BIT : stm32f1xx_ll_i2c.h
  • LL_I2C_ReadReg : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_ADD10 : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_ADDR : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_AF : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_ARLO : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_BERR : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_BTF : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_OVR : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_PECERR : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_RXNE : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_SB : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_SMALERT : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_STOPF : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_TIMEOUT : stm32f1xx_ll_i2c.h
  • LL_I2C_SR1_TXE : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_BUSY : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_DUALF : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_GENCALL : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_MSL : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_SMBDEFAULT : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_SMBHOST : stm32f1xx_ll_i2c.h
  • LL_I2C_SR2_TRA : stm32f1xx_ll_i2c.h
  • LL_I2C_WriteReg : stm32f1xx_ll_i2c.h
  • LL_I2S_AUDIOFREQ_11K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_16K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_192K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_22K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_32K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_44K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_48K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_8K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_96K : stm32f1xx_ll_i2s.h
  • LL_I2S_AUDIOFREQ_DEFAULT : stm32f1xx_ll_i2s.h
  • LL_I2S_CR2_ERRIE : stm32f1xx_ll_i2s.h
  • LL_I2S_CR2_RXNEIE : stm32f1xx_ll_i2s.h
  • LL_I2S_CR2_TXEIE : stm32f1xx_ll_i2s.h
  • LL_I2S_DATAFORMAT_16B : stm32f1xx_ll_i2s.h
  • LL_I2S_DATAFORMAT_16B_EXTENDED : stm32f1xx_ll_i2s.h
  • LL_I2S_DATAFORMAT_24B : stm32f1xx_ll_i2s.h
  • LL_I2S_DATAFORMAT_32B : stm32f1xx_ll_i2s.h
  • LL_I2S_MCLK_OUTPUT_DISABLE : stm32f1xx_ll_i2s.h
  • LL_I2S_MCLK_OUTPUT_ENABLE : stm32f1xx_ll_i2s.h
  • LL_I2S_MODE_MASTER_RX : stm32f1xx_ll_i2s.h
  • LL_I2S_MODE_MASTER_TX : stm32f1xx_ll_i2s.h
  • LL_I2S_MODE_SLAVE_RX : stm32f1xx_ll_i2s.h
  • LL_I2S_MODE_SLAVE_TX : stm32f1xx_ll_i2s.h
  • LL_I2S_POLARITY_HIGH : stm32f1xx_ll_i2s.h
  • LL_I2S_POLARITY_LOW : stm32f1xx_ll_i2s.h
  • LL_I2S_PRESCALER_PARITY_EVEN : stm32f1xx_ll_i2s.h
  • LL_I2S_PRESCALER_PARITY_ODD : stm32f1xx_ll_i2s.h
  • LL_I2S_ReadReg : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_BSY : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_FRE : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_OVR : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_RXNE : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_TXE : stm32f1xx_ll_i2s.h
  • LL_I2S_SR_UDR : stm32f1xx_ll_i2s.h
  • LL_I2S_STANDARD_LSB : stm32f1xx_ll_i2s.h
  • LL_I2S_STANDARD_MSB : stm32f1xx_ll_i2s.h
  • LL_I2S_STANDARD_PCM_LONG : stm32f1xx_ll_i2s.h
  • LL_I2S_STANDARD_PCM_SHORT : stm32f1xx_ll_i2s.h
  • LL_I2S_STANDARD_PHILIPS : stm32f1xx_ll_i2s.h
  • LL_I2S_WriteReg : stm32f1xx_ll_i2s.h
  • LL_IWDG_KEY_ENABLE : stm32f1xx_ll_iwdg.h
  • LL_IWDG_KEY_RELOAD : stm32f1xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_DISABLE : stm32f1xx_ll_iwdg.h
  • LL_IWDG_KEY_WR_ACCESS_ENABLE : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_128 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_16 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_256 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_32 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_4 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_64 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_PRESCALER_8 : stm32f1xx_ll_iwdg.h
  • LL_IWDG_ReadReg : stm32f1xx_ll_iwdg.h
  • LL_IWDG_SR_PVU : stm32f1xx_ll_iwdg.h
  • LL_IWDG_SR_RVU : stm32f1xx_ll_iwdg.h
  • LL_IWDG_WriteReg : stm32f1xx_ll_iwdg.h
  • LL_MAX_DELAY : stm32f1xx_ll_utils.h
  • LL_PWR_CR_CSBF : stm32f1xx_ll_pwr.h
  • LL_PWR_CR_CWUF : stm32f1xx_ll_pwr.h
  • LL_PWR_CSR_EWUP1 : stm32f1xx_ll_pwr.h
  • LL_PWR_CSR_PVDO : stm32f1xx_ll_pwr.h
  • LL_PWR_CSR_SBF : stm32f1xx_ll_pwr.h
  • LL_PWR_CSR_WUF : stm32f1xx_ll_pwr.h
  • LL_PWR_MODE_STANDBY : stm32f1xx_ll_pwr.h
  • LL_PWR_MODE_STOP_LPREGU : stm32f1xx_ll_pwr.h
  • LL_PWR_MODE_STOP_MAINREGU : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_0 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_1 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_2 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_3 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_4 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_5 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_6 : stm32f1xx_ll_pwr.h
  • LL_PWR_PVDLEVEL_7 : stm32f1xx_ll_pwr.h
  • LL_PWR_ReadReg : stm32f1xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_LOW_POWER : stm32f1xx_ll_pwr.h
  • LL_PWR_REGU_DSMODE_MAIN : stm32f1xx_ll_pwr.h
  • LL_PWR_WAKEUP_PIN1 : stm32f1xx_ll_pwr.h
  • LL_PWR_WriteReg : stm32f1xx_ll_pwr.h
  • LL_RCC_ADC_CLKSOURCE : stm32f1xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 : stm32f1xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 : stm32f1xx_ll_rcc.h
  • LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB1_DIV_1 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB1_DIV_16 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB1_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB1_DIV_4 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB1_DIV_8 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB2_DIV_1 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB2_DIV_16 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB2_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB2_DIV_4 : stm32f1xx_ll_rcc.h
  • LL_RCC_APB2_DIV_8 : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_CSSC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_CSSF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSERDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_HSIRDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSERDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_LSIRDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL2RDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL2RDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL2RDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL3RDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL3RDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLL3RDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYC : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYF : stm32f1xx_ll_rcc.h
  • LL_RCC_CIR_PLLRDYIE : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_IWDGRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_LPWRRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_PINRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_PORRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_SFTRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_CSR_WWDGRSTF : stm32f1xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSE : stm32f1xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_HSI : stm32f1xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_NOCLOCK : stm32f1xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_MCO1SOURCE_SYSCLK : stm32f1xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NA : stm32f1xx_ll_rcc.h
  • LL_RCC_PERIPH_FREQUENCY_NO : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_10 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_11 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_12 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_13 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_14 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_15 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_16 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_3 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_4 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_5 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_6 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_7 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_8 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLL_MUL_9 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE : stm32f1xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_1 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSE_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_PLLSOURCE_HSI_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_1 : stm32f1xx_ll_rcc.h
  • LL_RCC_PREDIV_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_ReadReg : stm32f1xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_HSE_DIV128 : stm32f1xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSE : stm32f1xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_LSI : stm32f1xx_ll_rcc.h
  • LL_RCC_RTC_CLKSOURCE_NONE : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSE : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_HSI : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_PLL : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSE : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_HSI : stm32f1xx_ll_rcc.h
  • LL_RCC_SYS_CLKSOURCE_STATUS_PLL : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_1 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_128 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_16 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_2 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_256 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_4 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_512 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_64 : stm32f1xx_ll_rcc.h
  • LL_RCC_SYSCLK_DIV_8 : stm32f1xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE : stm32f1xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL : stm32f1xx_ll_rcc.h
  • LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 : stm32f1xx_ll_rcc.h
  • LL_RCC_WriteReg : stm32f1xx_ll_rcc.h
  • LL_SPI_BAUDRATEPRESCALER_DIV128 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV16 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV2 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV256 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV32 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV4 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV64 : stm32f1xx_ll_spi.h
  • LL_SPI_BAUDRATEPRESCALER_DIV8 : stm32f1xx_ll_spi.h
  • LL_SPI_CR2_ERRIE : stm32f1xx_ll_spi.h
  • LL_SPI_CR2_RXNEIE : stm32f1xx_ll_spi.h
  • LL_SPI_CR2_TXEIE : stm32f1xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_DISABLE : stm32f1xx_ll_spi.h
  • LL_SPI_CRCCALCULATION_ENABLE : stm32f1xx_ll_spi.h
  • LL_SPI_DATAWIDTH_16BIT : stm32f1xx_ll_spi.h
  • LL_SPI_DATAWIDTH_8BIT : stm32f1xx_ll_spi.h
  • LL_SPI_FULL_DUPLEX : stm32f1xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_RX : stm32f1xx_ll_spi.h
  • LL_SPI_HALF_DUPLEX_TX : stm32f1xx_ll_spi.h
  • LL_SPI_LSB_FIRST : stm32f1xx_ll_spi.h
  • LL_SPI_MODE_MASTER : stm32f1xx_ll_spi.h
  • LL_SPI_MODE_SLAVE : stm32f1xx_ll_spi.h
  • LL_SPI_MSB_FIRST : stm32f1xx_ll_spi.h
  • LL_SPI_NSS_HARD_INPUT : stm32f1xx_ll_spi.h
  • LL_SPI_NSS_HARD_OUTPUT : stm32f1xx_ll_spi.h
  • LL_SPI_NSS_SOFT : stm32f1xx_ll_spi.h
  • LL_SPI_PHASE_1EDGE : stm32f1xx_ll_spi.h
  • LL_SPI_PHASE_2EDGE : stm32f1xx_ll_spi.h
  • LL_SPI_POLARITY_HIGH : stm32f1xx_ll_spi.h
  • LL_SPI_POLARITY_LOW : stm32f1xx_ll_spi.h
  • LL_SPI_ReadReg : stm32f1xx_ll_spi.h
  • LL_SPI_SIMPLEX_RX : stm32f1xx_ll_spi.h
  • LL_SPI_SR_BSY : stm32f1xx_ll_spi.h
  • LL_SPI_SR_CRCERR : stm32f1xx_ll_spi.h
  • LL_SPI_SR_FRE : stm32f1xx_ll_spi.h
  • LL_SPI_SR_MODF : stm32f1xx_ll_spi.h
  • LL_SPI_SR_OVR : stm32f1xx_ll_spi.h
  • LL_SPI_SR_RXNE : stm32f1xx_ll_spi.h
  • LL_SPI_SR_TXE : stm32f1xx_ll_spi.h
  • LL_SPI_WriteReg : stm32f1xx_ll_spi.h
  • LL_SYSTICK_CLKSOURCE_HCLK : stm32f1xx_ll_cortex.h
  • LL_SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f1xx_ll_cortex.h
  • LL_TIM_ACTIVEINPUT_DIRECTTI : stm32f1xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_INDIRECTTI : stm32f1xx_ll_tim.h
  • LL_TIM_ACTIVEINPUT_TRC : stm32f1xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_DISABLE : stm32f1xx_ll_tim.h
  • LL_TIM_AUTOMATICOUTPUT_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_BREAK_DISABLE : stm32f1xx_ll_tim.h
  • LL_TIM_BREAK_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_HIGH : stm32f1xx_ll_tim.h
  • LL_TIM_BREAK_POLARITY_LOW : stm32f1xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_CC : stm32f1xx_ll_tim.h
  • LL_TIM_CCDMAREQUEST_UPDATE : stm32f1xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI : stm32f1xx_ll_tim.h
  • LL_TIM_CCUPDATESOURCE_COMG_ONLY : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1 : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH1N : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2 : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH2N : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3 : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH3N : stm32f1xx_ll_tim.h
  • LL_TIM_CHANNEL_CH4 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV1 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV2 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKDIVISION_DIV4 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE1 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_EXT_MODE2 : stm32f1xx_ll_tim.h
  • LL_TIM_CLOCKSOURCE_INTERNAL : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_DOWN : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERDIRECTION_UP : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_DOWN : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERMODE_CENTER_UP_DOWN : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERMODE_DOWN : stm32f1xx_ll_tim.h
  • LL_TIM_COUNTERMODE_UP : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_BIE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_CC1IE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_CC2IE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_CC3IE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_CC4IE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_COMIE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_TIE : stm32f1xx_ll_tim.h
  • LL_TIM_DIER_UIE : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_ARR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_BDTR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCER : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR1 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCMR2 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR1 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR2 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR3 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CCR4 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CNT : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR1 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_CR2 : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_DIER : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_EGR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_PSC : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_RCR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SMCR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_BASEADDR_SR : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_10TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_11TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_12TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_13TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_14TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_15TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_16TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_17TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_18TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_1TRANSFER : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_2TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_3TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_4TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_5TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_6TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_7TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_8TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_DMABURST_LENGTH_9TRANSFERS : stm32f1xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI1 : stm32f1xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X2_TI2 : stm32f1xx_ll_tim.h
  • LL_TIM_ENCODERMODE_X4_TI12 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N5 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV16_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N2 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N4 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV1_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV2_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N5 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV32_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV4_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_FILTER_FDIV8_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_INVERTED : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_POLARITY_NONINVERTED : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV1 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV2 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV4 : stm32f1xx_ll_tim.h
  • LL_TIM_ETR_PRESCALER_DIV8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N5 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV16_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N2 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N4 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV1_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV2_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N5 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV32_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV4_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N6 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_FILTER_FDIV8_N8 : stm32f1xx_ll_tim.h
  • LL_TIM_IC_POLARITY_FALLING : stm32f1xx_ll_tim.h
  • LL_TIM_IC_POLARITY_RISING : stm32f1xx_ll_tim.h
  • LL_TIM_ICPSC_DIV1 : stm32f1xx_ll_tim.h
  • LL_TIM_ICPSC_DIV2 : stm32f1xx_ll_tim.h
  • LL_TIM_ICPSC_DIV4 : stm32f1xx_ll_tim.h
  • LL_TIM_ICPSC_DIV8 : stm32f1xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_1 : stm32f1xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_2 : stm32f1xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_3 : stm32f1xx_ll_tim.h
  • LL_TIM_LOCKLEVEL_OFF : stm32f1xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_HIGH : stm32f1xx_ll_tim.h
  • LL_TIM_OCIDLESTATE_LOW : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_ACTIVE : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_ACTIVE : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_FORCED_INACTIVE : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_FROZEN : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_INACTIVE : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_PWM1 : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_PWM2 : stm32f1xx_ll_tim.h
  • LL_TIM_OCMODE_TOGGLE : stm32f1xx_ll_tim.h
  • LL_TIM_OCPOLARITY_HIGH : stm32f1xx_ll_tim.h
  • LL_TIM_OCPOLARITY_LOW : stm32f1xx_ll_tim.h
  • LL_TIM_OCSTATE_DISABLE : stm32f1xx_ll_tim.h
  • LL_TIM_OCSTATE_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_REPETITIVE : stm32f1xx_ll_tim.h
  • LL_TIM_ONEPULSEMODE_SINGLE : stm32f1xx_ll_tim.h
  • LL_TIM_OSSI_DISABLE : stm32f1xx_ll_tim.h
  • LL_TIM_OSSI_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_OSSR_DISABLE : stm32f1xx_ll_tim.h
  • LL_TIM_OSSR_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_ReadReg : stm32f1xx_ll_tim.h
  • LL_TIM_SLAVEMODE_DISABLED : stm32f1xx_ll_tim.h
  • LL_TIM_SLAVEMODE_GATED : stm32f1xx_ll_tim.h
  • LL_TIM_SLAVEMODE_RESET : stm32f1xx_ll_tim.h
  • LL_TIM_SLAVEMODE_TRIGGER : stm32f1xx_ll_tim.h
  • LL_TIM_SR_BIF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC1IF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC1OF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC2IF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC2OF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC3IF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC3OF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC4IF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_CC4OF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_COMIF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_TIF : stm32f1xx_ll_tim.h
  • LL_TIM_SR_UIF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_CC1IF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_ENABLE : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_OC1REF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_OC2REF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_OC3REF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_OC4REF : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_RESET : stm32f1xx_ll_tim.h
  • LL_TIM_TRGO_UPDATE : stm32f1xx_ll_tim.h
  • LL_TIM_TS_ETRF : stm32f1xx_ll_tim.h
  • LL_TIM_TS_ITR0 : stm32f1xx_ll_tim.h
  • LL_TIM_TS_ITR1 : stm32f1xx_ll_tim.h
  • LL_TIM_TS_ITR2 : stm32f1xx_ll_tim.h
  • LL_TIM_TS_ITR3 : stm32f1xx_ll_tim.h
  • LL_TIM_TS_TI1F_ED : stm32f1xx_ll_tim.h
  • LL_TIM_TS_TI1FP1 : stm32f1xx_ll_tim.h
  • LL_TIM_TS_TI2FP2 : stm32f1xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_COUNTER : stm32f1xx_ll_tim.h
  • LL_TIM_UPDATESOURCE_REGULAR : stm32f1xx_ll_tim.h
  • LL_TIM_WriteReg : stm32f1xx_ll_tim.h
  • LL_USART_CLOCK_DISABLE : stm32f1xx_ll_usart.h
  • LL_USART_CLOCK_ENABLE : stm32f1xx_ll_usart.h
  • LL_USART_CR1_IDLEIE : stm32f1xx_ll_usart.h
  • LL_USART_CR1_PEIE : stm32f1xx_ll_usart.h
  • LL_USART_CR1_RXNEIE : stm32f1xx_ll_usart.h
  • LL_USART_CR1_TCIE : stm32f1xx_ll_usart.h
  • LL_USART_CR1_TXEIE : stm32f1xx_ll_usart.h
  • LL_USART_CR2_LBDIE : stm32f1xx_ll_usart.h
  • LL_USART_CR3_CTSIE : stm32f1xx_ll_usart.h
  • LL_USART_CR3_EIE : stm32f1xx_ll_usart.h
  • LL_USART_DATAWIDTH_8B : stm32f1xx_ll_usart.h
  • LL_USART_DATAWIDTH_9B : stm32f1xx_ll_usart.h
  • LL_USART_DIRECTION_NONE : stm32f1xx_ll_usart.h
  • LL_USART_DIRECTION_RX : stm32f1xx_ll_usart.h
  • LL_USART_DIRECTION_TX : stm32f1xx_ll_usart.h
  • LL_USART_DIRECTION_TX_RX : stm32f1xx_ll_usart.h
  • LL_USART_HWCONTROL_CTS : stm32f1xx_ll_usart.h
  • LL_USART_HWCONTROL_NONE : stm32f1xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS : stm32f1xx_ll_usart.h
  • LL_USART_HWCONTROL_RTS_CTS : stm32f1xx_ll_usart.h
  • LL_USART_IRDA_POWER_LOW : stm32f1xx_ll_usart.h
  • LL_USART_IRDA_POWER_NORMAL : stm32f1xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_NO_OUTPUT : stm32f1xx_ll_usart.h
  • LL_USART_LASTCLKPULSE_OUTPUT : stm32f1xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_10B : stm32f1xx_ll_usart.h
  • LL_USART_LINBREAK_DETECT_11B : stm32f1xx_ll_usart.h
  • LL_USART_PARITY_EVEN : stm32f1xx_ll_usart.h
  • LL_USART_PARITY_NONE : stm32f1xx_ll_usart.h
  • LL_USART_PARITY_ODD : stm32f1xx_ll_usart.h
  • LL_USART_PHASE_1EDGE : stm32f1xx_ll_usart.h
  • LL_USART_PHASE_2EDGE : stm32f1xx_ll_usart.h
  • LL_USART_POLARITY_HIGH : stm32f1xx_ll_usart.h
  • LL_USART_POLARITY_LOW : stm32f1xx_ll_usart.h
  • LL_USART_ReadReg : stm32f1xx_ll_usart.h
  • LL_USART_SR_CTS : stm32f1xx_ll_usart.h
  • LL_USART_SR_FE : stm32f1xx_ll_usart.h
  • LL_USART_SR_IDLE : stm32f1xx_ll_usart.h
  • LL_USART_SR_LBD : stm32f1xx_ll_usart.h
  • LL_USART_SR_NE : stm32f1xx_ll_usart.h
  • LL_USART_SR_ORE : stm32f1xx_ll_usart.h
  • LL_USART_SR_PE : stm32f1xx_ll_usart.h
  • LL_USART_SR_RXNE : stm32f1xx_ll_usart.h
  • LL_USART_SR_TC : stm32f1xx_ll_usart.h
  • LL_USART_SR_TXE : stm32f1xx_ll_usart.h
  • LL_USART_STOPBITS_0_5 : stm32f1xx_ll_usart.h
  • LL_USART_STOPBITS_1 : stm32f1xx_ll_usart.h
  • LL_USART_STOPBITS_1_5 : stm32f1xx_ll_usart.h
  • LL_USART_STOPBITS_2 : stm32f1xx_ll_usart.h
  • LL_USART_WAKEUP_ADDRESSMARK : stm32f1xx_ll_usart.h
  • LL_USART_WAKEUP_IDLELINE : stm32f1xx_ll_usart.h
  • LL_USART_WriteReg : stm32f1xx_ll_usart.h
  • LL_UTILS_HSEBYPASS_OFF : stm32f1xx_ll_utils.h
  • LL_UTILS_HSEBYPASS_ON : stm32f1xx_ll_utils.h
  • LL_WWDG_CFR_EWI : stm32f1xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_1 : stm32f1xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_2 : stm32f1xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_4 : stm32f1xx_ll_wwdg.h
  • LL_WWDG_PRESCALER_8 : stm32f1xx_ll_wwdg.h
  • LL_WWDG_ReadReg : stm32f1xx_ll_wwdg.h
  • LL_WWDG_WriteReg : stm32f1xx_ll_wwdg.h
  • LPSDSR_BIT_NUMBER : stm32f1xx_hal_pwr.c
  • LSE_STARTUP_TIMEOUT : stm32f1xx_hal_conf.h
  • LSE_VALUE : stm32f1xx_hal_conf.h , stm32f1xx_ll_rcc.h
  • LSI_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • LSI_VALUE : stm32f1xx_hal_conf.h , stm32f1xx_ll_rcc.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- m -

  • MAC_ADDR0 : stm32f1xx_hal_conf.h
  • MAC_ADDR1 : stm32f1xx_hal_conf.h
  • MAC_ADDR2 : stm32f1xx_hal_conf.h
  • MAC_ADDR3 : stm32f1xx_hal_conf.h
  • MAC_ADDR4 : stm32f1xx_hal_conf.h
  • MAC_ADDR5 : stm32f1xx_hal_conf.h
  • MCO1_CLK_ENABLE : stm32f1xx_hal_rcc.c
  • MCO1_GPIO_PORT : stm32f1xx_hal_rcc.c
  • MCO1_PIN : stm32f1xx_hal_rcc.c
  • MSR_REGISTER_INDEX : stm32f1xx_hal_can.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- n -

  • NVIC_PRIORITYGROUP_0 : stm32f1xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_1 : stm32f1xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_2 : stm32f1xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_3 : stm32f1xx_hal_cortex.h
  • NVIC_PRIORITYGROUP_4 : stm32f1xx_hal_cortex.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
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  • Functions
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  • Typedefs
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- o -

  • OB_DATA_ADDRESS_DATA0 : stm32f1xx_hal_flash_ex.h
  • OB_DATA_ADDRESS_DATA1 : stm32f1xx_hal_flash_ex.h
  • OB_IWDG_HW : stm32f1xx_hal_flash_ex.h
  • OB_IWDG_SW : stm32f1xx_hal_flash_ex.h
  • OB_RDP_LEVEL_0 : stm32f1xx_hal_flash_ex.h
  • OB_RDP_LEVEL_1 : stm32f1xx_hal_flash_ex.h
  • OB_STDBY_NO_RST : stm32f1xx_hal_flash_ex.h
  • OB_STDBY_RST : stm32f1xx_hal_flash_ex.h
  • OB_STOP_NO_RST : stm32f1xx_hal_flash_ex.h
  • OB_STOP_RST : stm32f1xx_hal_flash_ex.h
  • OB_WRP_ALLPAGES : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES0TO3 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES0TO31MASK : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES100TO103 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES104TO107 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES108TO111 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES112TO115 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES116TO119 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES120TO123 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES124TO127 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES12TO15 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES16TO19 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES20TO23 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES24TO27 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES28TO31 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES32TO35 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES32TO63MASK : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES36TO39 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES40TO43 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES44TO47 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES48TO51 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES4TO7 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES52TO55 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES56TO59 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES60TO63 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES64TO67 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES64TO95MASK : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES68TO71 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES72TO75 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES76TO79 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES80TO83 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES84TO87 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES88TO91 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES8TO11 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES92TO95 : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES96TO127MASK : stm32f1xx_hal_flash_ex.h
  • OB_WRP_PAGES96TO99 : stm32f1xx_hal_flash_ex.h
  • OB_WRPSTATE_DISABLE : stm32f1xx_hal_flash_ex.h
  • OB_WRPSTATE_ENABLE : stm32f1xx_hal_flash_ex.h
  • OBR_REG_INDEX : stm32f1xx_hal_flash_ex.h
  • OPTIONBYTE_DATA : stm32f1xx_hal_flash_ex.h
  • OPTIONBYTE_RDP : stm32f1xx_hal_flash_ex.h
  • OPTIONBYTE_USER : stm32f1xx_hal_flash_ex.h
  • OPTIONBYTE_WRP : stm32f1xx_hal_flash_ex.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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  • Globals
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- p -

  • PCD_CALC_BLK2 : stm32f1xx_hal_pcd.h
  • PCD_CALC_BLK32 : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_EP_DBUF : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_EP_KIND : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_OUT_STATUS : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_RX_DTOG : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_RX_EP_CTR : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_TX_DTOG : stm32f1xx_hal_pcd.h
  • PCD_CLEAR_TX_EP_CTR : stm32f1xx_hal_pcd.h
  • PCD_DBL_BUF : stm32f1xx_hal_pcd.h
  • PCD_ENDP0 : stm32f1xx_hal_pcd.h
  • PCD_ENDP1 : stm32f1xx_hal_pcd.h
  • PCD_ENDP2 : stm32f1xx_hal_pcd.h
  • PCD_ENDP3 : stm32f1xx_hal_pcd.h
  • PCD_ENDP4 : stm32f1xx_hal_pcd.h
  • PCD_ENDP5 : stm32f1xx_hal_pcd.h
  • PCD_ENDP6 : stm32f1xx_hal_pcd.h
  • PCD_ENDP7 : stm32f1xx_hal_pcd.h
  • PCD_EP0MPS_08 : stm32f1xx_hal_pcd.h
  • PCD_EP0MPS_16 : stm32f1xx_hal_pcd.h
  • PCD_EP0MPS_32 : stm32f1xx_hal_pcd.h
  • PCD_EP0MPS_64 : stm32f1xx_hal_pcd.h
  • PCD_EP_RX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_EP_RX_CNT : stm32f1xx_hal_pcd.h
  • PCD_EP_TX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_EP_TX_CNT : stm32f1xx_hal_pcd.h
  • PCD_FreeUserBuffer : stm32f1xx_hal_pcd.h
  • PCD_GET_DB_DIR : stm32f1xx_hal_pcd.h
  • PCD_GET_ENDPOINT : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_ADDR : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_DBUF0_CNT : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_ADDR : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_DBUF1_CNT : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_RX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_RX_CNT : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_RX_STALL_STATUS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_RX_STATUS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_TX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_TX_CNT : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_TX_STALL_STATUS : stm32f1xx_hal_pcd.h
  • PCD_GET_EP_TX_STATUS : stm32f1xx_hal_pcd.h
  • PCD_GET_EPTYPE : stm32f1xx_hal_pcd.h
  • PCD_MAX : stm32f1xx_hal_pcd.c
  • PCD_MIN : stm32f1xx_hal_pcd.c
  • PCD_PHY_EMBEDDED : stm32f1xx_hal_pcd.h
  • PCD_RX_DTOG : stm32f1xx_hal_pcd.h
  • PCD_SET_ENDPOINT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_CNT_RX_REG : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_ADDR : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF0_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_ADDR : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF1_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF_ADDR : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_DBUF_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_KIND : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_RX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_RX_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_RX_DBUF0_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_RX_STATUS : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_RX_VALID : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_TX_ADDRESS : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_TX_CNT : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_TX_STATUS : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_TX_VALID : stm32f1xx_hal_pcd.h
  • PCD_SET_EP_TXRX_STATUS : stm32f1xx_hal_pcd.h
  • PCD_SET_EPTYPE : stm32f1xx_hal_pcd.h
  • PCD_SET_OUT_STATUS : stm32f1xx_hal_pcd.h
  • PCD_SNG_BUF : stm32f1xx_hal_pcd.h
  • PCD_SPEED_FULL : stm32f1xx_hal_pcd.h
  • PCD_SPEED_HIGH : stm32f1xx_hal_pcd.h
  • PCD_SPEED_HIGH_IN_FULL : stm32f1xx_hal_pcd.h
  • PCD_TX_DTOG : stm32f1xx_hal_pcd.h
  • PHY_AUTONEGO_COMPLETE : stm32f1xx_hal_conf.h
  • PHY_AUTONEGOTIATION : stm32f1xx_hal_conf.h
  • PHY_BCR : stm32f1xx_hal_conf.h
  • PHY_BSR : stm32f1xx_hal_conf.h
  • PHY_CONFIG_DELAY : stm32f1xx_hal_conf.h
  • PHY_DUPLEX_STATUS : stm32f1xx_hal_conf.h
  • PHY_FULLDUPLEX_100M : stm32f1xx_hal_conf.h
  • PHY_FULLDUPLEX_10M : stm32f1xx_hal_conf.h
  • PHY_HALFDUPLEX_100M : stm32f1xx_hal_conf.h
  • PHY_HALFDUPLEX_10M : stm32f1xx_hal_conf.h
  • PHY_ISOLATE : stm32f1xx_hal_conf.h
  • PHY_JABBER_DETECTION : stm32f1xx_hal_conf.h
  • PHY_LINK_INTERRUPT : stm32f1xx_hal_conf.h
  • PHY_LINK_STATUS : stm32f1xx_hal_conf.h
  • PHY_LINKED_STATUS : stm32f1xx_hal_conf.h
  • PHY_LOOPBACK : stm32f1xx_hal_conf.h
  • PHY_MICR : stm32f1xx_hal_conf.h
  • PHY_MICR_INT_EN : stm32f1xx_hal_conf.h
  • PHY_MICR_INT_OE : stm32f1xx_hal_conf.h
  • PHY_MISR : stm32f1xx_hal_conf.h
  • PHY_MISR_LINK_INT_EN : stm32f1xx_hal_conf.h
  • PHY_POWERDOWN : stm32f1xx_hal_conf.h
  • PHY_READ_TO : stm32f1xx_hal_conf.h
  • PHY_RESET : stm32f1xx_hal_conf.h
  • PHY_RESET_DELAY : stm32f1xx_hal_conf.h
  • PHY_RESTART_AUTONEGOTIATION : stm32f1xx_hal_conf.h
  • PHY_SPEED_STATUS : stm32f1xx_hal_conf.h
  • PHY_SR : stm32f1xx_hal_conf.h
  • PHY_WRITE_TO : stm32f1xx_hal_conf.h
  • PLL_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • PREFETCH_ENABLE : stm32f1xx_hal_conf.h
  • PVD_FALLING_EDGE : stm32f1xx_hal_pwr.c
  • PVD_MODE_EVT : stm32f1xx_hal_pwr.c
  • PVD_MODE_IT : stm32f1xx_hal_pwr.c
  • PVD_RISING_EDGE : stm32f1xx_hal_pwr.c
  • PVDE_BIT_NUMBER : stm32f1xx_hal_pwr.c
  • PWR_CR_OFFSET : stm32f1xx_hal_pwr.c
  • PWR_CR_OFFSET_BB : stm32f1xx_hal_pwr.c
  • PWR_CSR_OFFSET : stm32f1xx_hal_pwr.c
  • PWR_CSR_OFFSET_BB : stm32f1xx_hal_pwr.c
  • PWR_EXTI_LINE_PVD : stm32f1xx_hal_pwr.h
  • PWR_FLAG_PVDO : stm32f1xx_hal_pwr.h
  • PWR_FLAG_SB : stm32f1xx_hal_pwr.h
  • PWR_FLAG_WU : stm32f1xx_hal_pwr.h
  • PWR_LOWPOWERREGULATOR_ON : stm32f1xx_hal_pwr.h
  • PWR_MAINREGULATOR_ON : stm32f1xx_hal_pwr.h
  • PWR_OFFSET : stm32f1xx_hal_pwr.c
  • PWR_PVD_MODE_EVENT_FALLING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_EVENT_RISING_FALLING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_IT_FALLING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_IT_RISING_FALLING : stm32f1xx_hal_pwr.h
  • PWR_PVD_MODE_NORMAL : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_0 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_1 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_2 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_3 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_4 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_5 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_6 : stm32f1xx_hal_pwr.h
  • PWR_PVDLEVEL_7 : stm32f1xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFE : stm32f1xx_hal_pwr.h
  • PWR_SLEEPENTRY_WFI : stm32f1xx_hal_pwr.h
  • PWR_STOPENTRY_WFE : stm32f1xx_hal_pwr.h
  • PWR_STOPENTRY_WFI : stm32f1xx_hal_pwr.h
  • PWR_WAKEUP_PIN1 : stm32f1xx_hal_pwr.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
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- r -

  • RCC_ADCPCLK2_DIV2 : stm32f1xx_hal_rcc_ex.h
  • RCC_ADCPCLK2_DIV4 : stm32f1xx_hal_rcc_ex.h
  • RCC_ADCPCLK2_DIV6 : stm32f1xx_hal_rcc_ex.h
  • RCC_ADCPCLK2_DIV8 : stm32f1xx_hal_rcc_ex.h
  • RCC_BDCR_BDRST_BB : stm32f1xx_hal_rcc.h
  • RCC_BDCR_LSEBYP_BB : stm32f1xx_hal_rcc.h
  • RCC_BDCR_LSEON_BB : stm32f1xx_hal_rcc.h
  • RCC_BDCR_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_BDCR_OFFSET_BB : stm32f1xx_hal_rcc.h
  • RCC_BDCR_RTCEN_BB : stm32f1xx_hal_rcc.h
  • RCC_BDRST_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_CFGR_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_CFGR_OFFSET_BB : stm32f1xx_hal_rcc.h
  • RCC_CIR_BYTE1_ADDRESS : stm32f1xx_hal_rcc.h
  • RCC_CIR_BYTE2_ADDRESS : stm32f1xx_hal_rcc.h
  • RCC_CIR_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_CIR_OFFSET_BB : stm32f1xx_hal_rcc.h
  • RCC_CLOCKTYPE_HCLK : stm32f1xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK1 : stm32f1xx_hal_rcc.h
  • RCC_CLOCKTYPE_PCLK2 : stm32f1xx_hal_rcc.h
  • RCC_CLOCKTYPE_SYSCLK : stm32f1xx_hal_rcc.h
  • RCC_CR_BYTE2_ADDRESS : stm32f1xx_hal_rcc.h
  • RCC_CR_CSSON_BB : stm32f1xx_hal_rcc.h
  • RCC_CR_HSEON_BB : stm32f1xx_hal_rcc.h
  • RCC_CR_HSION_BB : stm32f1xx_hal_rcc.h
  • RCC_CR_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_CR_OFFSET_BB : stm32f1xx_hal_rcc.h
  • RCC_CR_PLLON_BB : stm32f1xx_hal_rcc.h
  • RCC_CSR_LSION_BB : stm32f1xx_hal_rcc.h
  • RCC_CSR_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_CSR_OFFSET_BB : stm32f1xx_hal_rcc.h
  • RCC_CSR_RMVF_BB : stm32f1xx_hal_rcc.h
  • RCC_CSSON_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_DBP_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • RCC_FLAG_HSERDY : stm32f1xx_hal_rcc.h
  • RCC_FLAG_HSIRDY : stm32f1xx_hal_rcc.h
  • RCC_FLAG_IWDGRST : stm32f1xx_hal_rcc.h
  • RCC_FLAG_LPWRRST : stm32f1xx_hal_rcc.h
  • RCC_FLAG_LSERDY : stm32f1xx_hal_rcc.h
  • RCC_FLAG_LSIRDY : stm32f1xx_hal_rcc.h
  • RCC_FLAG_MASK : stm32f1xx_hal_rcc.h
  • RCC_FLAG_PINRST : stm32f1xx_hal_rcc.h
  • RCC_FLAG_PLLRDY : stm32f1xx_hal_rcc.h
  • RCC_FLAG_PORRST : stm32f1xx_hal_rcc.h
  • RCC_FLAG_SFTRST : stm32f1xx_hal_rcc.h
  • RCC_FLAG_WWDGRST : stm32f1xx_hal_rcc.h
  • RCC_HCLK_DIV1 : stm32f1xx_hal_rcc.h
  • RCC_HCLK_DIV16 : stm32f1xx_hal_rcc.h
  • RCC_HCLK_DIV2 : stm32f1xx_hal_rcc.h
  • RCC_HCLK_DIV4 : stm32f1xx_hal_rcc.h
  • RCC_HCLK_DIV8 : stm32f1xx_hal_rcc.h
  • RCC_HSE_BYPASS : stm32f1xx_hal_rcc.h
  • RCC_HSE_OFF : stm32f1xx_hal_rcc.h
  • RCC_HSE_ON : stm32f1xx_hal_rcc.h
  • RCC_HSE_PREDIV_DIV1 : stm32f1xx_hal_rcc_ex.h
  • RCC_HSE_PREDIV_DIV2 : stm32f1xx_hal_rcc_ex.h
  • RCC_HSEON_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_HSI_OFF : stm32f1xx_hal_rcc.h
  • RCC_HSI_ON : stm32f1xx_hal_rcc.h
  • RCC_HSICALIBRATION_DEFAULT : stm32f1xx_hal_rcc.h
  • RCC_HSION_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_IT_CSS : stm32f1xx_hal_rcc.h
  • RCC_IT_HSERDY : stm32f1xx_hal_rcc.h
  • RCC_IT_HSIRDY : stm32f1xx_hal_rcc.h
  • RCC_IT_LSERDY : stm32f1xx_hal_rcc.h
  • RCC_IT_LSIRDY : stm32f1xx_hal_rcc.h
  • RCC_IT_PLLRDY : stm32f1xx_hal_rcc.h
  • RCC_LSE_BYPASS : stm32f1xx_hal_rcc.h
  • RCC_LSE_OFF : stm32f1xx_hal_rcc.h
  • RCC_LSE_ON : stm32f1xx_hal_rcc.h
  • RCC_LSE_TIMEOUT_VALUE : stm32f1xx_hal_rcc.h
  • RCC_LSEBYP_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_LSEON_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_LSI_OFF : stm32f1xx_hal_rcc.h
  • RCC_LSI_ON : stm32f1xx_hal_rcc.h
  • RCC_LSION_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_MCO : stm32f1xx_hal_rcc.h
  • RCC_MCO1 : stm32f1xx_hal_rcc.h
  • RCC_MCO1SOURCE_HSE : stm32f1xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_HSI : stm32f1xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_NOCLOCK : stm32f1xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_PLLCLK : stm32f1xx_hal_rcc_ex.h
  • RCC_MCO1SOURCE_SYSCLK : stm32f1xx_hal_rcc_ex.h
  • RCC_MCODIV_1 : stm32f1xx_hal_rcc.h
  • RCC_OFFSET : stm32f1xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSE : stm32f1xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_HSI : stm32f1xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSE : stm32f1xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_LSI : stm32f1xx_hal_rcc.h
  • RCC_OSCILLATORTYPE_NONE : stm32f1xx_hal_rcc.h
  • RCC_PERIPHCLK_ADC : stm32f1xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_RTC : stm32f1xx_hal_rcc_ex.h
  • RCC_PERIPHCLK_USB : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL10 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL11 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL12 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL13 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL14 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL15 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL16 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL2 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL3 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL4 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL5 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL6 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL7 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL8 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_MUL9 : stm32f1xx_hal_rcc_ex.h
  • RCC_PLL_NONE : stm32f1xx_hal_rcc.h
  • RCC_PLL_OFF : stm32f1xx_hal_rcc.h
  • RCC_PLL_ON : stm32f1xx_hal_rcc.h
  • RCC_PLLON_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_PLLSOURCE_HSE : stm32f1xx_hal_rcc.h
  • RCC_PLLSOURCE_HSI_DIV2 : stm32f1xx_hal_rcc.h
  • RCC_RMVF_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_HSE_DIV128 : stm32f1xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSE : stm32f1xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_LSI : stm32f1xx_hal_rcc.h
  • RCC_RTCCLKSOURCE_NO_CLK : stm32f1xx_hal_rcc.h
  • RCC_RTCEN_BIT_NUMBER : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV1 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV128 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV16 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV2 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV256 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV4 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV512 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV64 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLK_DIV8 : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSE : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_HSI : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_PLLCLK : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSE : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_HSI : stm32f1xx_hal_rcc.h
  • RCC_SYSCLKSOURCE_STATUS_PLLCLK : stm32f1xx_hal_rcc.h
  • RCC_USBCLKSOURCE_PLL : stm32f1xx_hal_rcc_ex.h
  • RCC_USBCLKSOURCE_PLL_DIV1_5 : stm32f1xx_hal_rcc_ex.h
  • RF0R_REGISTER_INDEX : stm32f1xx_hal_can.h
  • RF1R_REGISTER_INDEX : stm32f1xx_hal_can.h
  • RISING_EDGE : stm32f1xx_hal_gpio.c
  • RTC_ALARM_A : stm32f1xx_hal_rtc.h
  • RTC_ALARM_RESETVALUE : stm32f1xx_hal_rtc.c
  • RTC_ALARM_RESETVALUE_REGISTER : stm32f1xx_hal_rtc.c
  • RTC_AUTO_1_SECOND : stm32f1xx_hal_rtc.h
  • RTC_BKP_DR1 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR10 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR2 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR3 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR4 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR5 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR6 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR7 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR8 : stm32f1xx_hal_rtc_ex.h
  • RTC_BKP_DR9 : stm32f1xx_hal_rtc_ex.h
  • RTC_EXTI_LINE_ALARM_EVENT : stm32f1xx_hal_rtc.h
  • RTC_FLAG_ALRAF : stm32f1xx_hal_rtc.h
  • RTC_FLAG_OW : stm32f1xx_hal_rtc.h
  • RTC_FLAG_RSF : stm32f1xx_hal_rtc.h
  • RTC_FLAG_RTOFF : stm32f1xx_hal_rtc.h
  • RTC_FLAG_SEC : stm32f1xx_hal_rtc.h
  • RTC_FLAG_TAMP1F : stm32f1xx_hal_rtc.h
  • RTC_FORMAT_BCD : stm32f1xx_hal_rtc.h
  • RTC_FORMAT_BIN : stm32f1xx_hal_rtc.h
  • RTC_IT_ALRA : stm32f1xx_hal_rtc.h
  • RTC_IT_OW : stm32f1xx_hal_rtc.h
  • RTC_IT_SEC : stm32f1xx_hal_rtc.h
  • RTC_IT_TAMP1 : stm32f1xx_hal_rtc.h
  • RTC_MONTH_APRIL : stm32f1xx_hal_rtc.h
  • RTC_MONTH_AUGUST : stm32f1xx_hal_rtc.h
  • RTC_MONTH_DECEMBER : stm32f1xx_hal_rtc.h
  • RTC_MONTH_FEBRUARY : stm32f1xx_hal_rtc.h
  • RTC_MONTH_JANUARY : stm32f1xx_hal_rtc.h
  • RTC_MONTH_JULY : stm32f1xx_hal_rtc.h
  • RTC_MONTH_JUNE : stm32f1xx_hal_rtc.h
  • RTC_MONTH_MARCH : stm32f1xx_hal_rtc.h
  • RTC_MONTH_MAY : stm32f1xx_hal_rtc.h
  • RTC_MONTH_NOVEMBER : stm32f1xx_hal_rtc.h
  • RTC_MONTH_OCTOBER : stm32f1xx_hal_rtc.h
  • RTC_MONTH_SEPTEMBER : stm32f1xx_hal_rtc.h
  • RTC_OUTPUTSOURCE_ALARM : stm32f1xx_hal_rtc.h
  • RTC_OUTPUTSOURCE_CALIBCLOCK : stm32f1xx_hal_rtc.h
  • RTC_OUTPUTSOURCE_NONE : stm32f1xx_hal_rtc.h
  • RTC_OUTPUTSOURCE_SECOND : stm32f1xx_hal_rtc.h
  • RTC_TAMPER_1 : stm32f1xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_HIGHLEVEL : stm32f1xx_hal_rtc_ex.h
  • RTC_TAMPERTRIGGER_LOWLEVEL : stm32f1xx_hal_rtc_ex.h
  • RTC_TIMEOUT_VALUE : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_FRIDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_MONDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_SATURDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_SUNDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_THURSDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_TUESDAY : stm32f1xx_hal_rtc.h
  • RTC_WEEKDAY_WEDNESDAY : stm32f1xx_hal_rtc.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
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- s -

  • SMARTCARD_BRR : stm32f1xx_hal_smartcard.h
  • SMARTCARD_CR1_REG_INDEX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_CR3_REG_INDEX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DIV : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DIVFRAQ : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DIVMANT : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DMAREQ_RX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_DMAREQ_TX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_FE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_IDLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_NE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_ORE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_PE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_RXNE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_TC : stm32f1xx_hal_smartcard.h
  • SMARTCARD_FLAG_TXE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_ERR : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_IDLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_MASK : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_PE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_RXNE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_TC : stm32f1xx_hal_smartcard.h
  • SMARTCARD_IT_TXE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_DISABLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_LASTBIT_ENABLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_MODE_RX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_MODE_TX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_MODE_TX_RX : stm32f1xx_hal_smartcard.h
  • SMARTCARD_NACK_DISABLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_NACK_ENABLE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PARITY_EVEN : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PARITY_ODD : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PHASE_1EDGE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PHASE_2EDGE : stm32f1xx_hal_smartcard.h
  • SMARTCARD_POLARITY_HIGH : stm32f1xx_hal_smartcard.h
  • SMARTCARD_POLARITY_LOW : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV10 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV12 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV14 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV16 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV18 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV2 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV20 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV22 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV24 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV26 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV28 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV30 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV32 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV34 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV36 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV38 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV4 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV40 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV42 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV44 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV46 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV48 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV50 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV52 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV54 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV56 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV58 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV6 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV60 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV62 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_PRESCALER_SYSCLK_DIV8 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_0_5 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_STOPBITS_1_5 : stm32f1xx_hal_smartcard.h
  • SMARTCARD_WORDLENGTH_9B : stm32f1xx_hal_smartcard.h
  • SPI_1LINE_RX : stm32f1xx_hal_spi.h
  • SPI_1LINE_TX : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_128 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_16 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_2 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_256 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_32 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_4 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_64 : stm32f1xx_hal_spi.h
  • SPI_BAUDRATEPRESCALER_8 : stm32f1xx_hal_spi.h
  • SPI_CR1_CLEAR_MASK : stm32f1xx_ll_spi.c
  • SPI_CRCCALCULATION_DISABLE : stm32f1xx_hal_spi.h
  • SPI_CRCCALCULATION_ENABLE : stm32f1xx_hal_spi.h
  • SPI_DATASIZE_16BIT : stm32f1xx_hal_spi.h
  • SPI_DATASIZE_8BIT : stm32f1xx_hal_spi.h
  • SPI_DEFAULT_TIMEOUT : stm32f1xx_hal_spi.c
  • SPI_DIRECTION_1LINE : stm32f1xx_hal_spi.h
  • SPI_DIRECTION_2LINES : stm32f1xx_hal_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : stm32f1xx_hal_spi.h
  • SPI_FIRSTBIT_LSB : stm32f1xx_hal_spi.h
  • SPI_FIRSTBIT_MSB : stm32f1xx_hal_spi.h
  • SPI_FLAG_BSY : stm32f1xx_hal_spi.h
  • SPI_FLAG_CRCERR : stm32f1xx_hal_spi.h
  • SPI_FLAG_MODF : stm32f1xx_hal_spi.h
  • SPI_FLAG_OVR : stm32f1xx_hal_spi.h
  • SPI_FLAG_RXNE : stm32f1xx_hal_spi.h
  • SPI_FLAG_TXE : stm32f1xx_hal_spi.h
  • SPI_INVALID_CRC_ERROR : stm32f1xx_hal_spi.h
  • SPI_IT_ERR : stm32f1xx_hal_spi.h
  • SPI_IT_RXNE : stm32f1xx_hal_spi.h
  • SPI_IT_TXE : stm32f1xx_hal_spi.h
  • SPI_MODE_MASTER : stm32f1xx_hal_spi.h
  • SPI_MODE_SLAVE : stm32f1xx_hal_spi.h
  • SPI_NSS_HARD_INPUT : stm32f1xx_hal_spi.h
  • SPI_NSS_HARD_OUTPUT : stm32f1xx_hal_spi.h
  • SPI_NSS_SOFT : stm32f1xx_hal_spi.h
  • SPI_PHASE_1EDGE : stm32f1xx_hal_spi.h
  • SPI_PHASE_2EDGE : stm32f1xx_hal_spi.h
  • SPI_POLARITY_HIGH : stm32f1xx_hal_spi.h
  • SPI_POLARITY_LOW : stm32f1xx_hal_spi.h
  • SPI_RESET_CRC : stm32f1xx_hal_spi.h
  • SPI_TIMODE_DISABLE : stm32f1xx_hal_spi.h
  • SPI_VALID_CRC_ERROR : stm32f1xx_hal_spi.h
  • SR_FLAG_MASK : stm32f1xx_hal_flash_ex.h
  • SYSTICK_CLKSOURCE_HCLK : stm32f1xx_hal_cortex.h
  • SYSTICK_CLKSOURCE_HCLK_DIV8 : stm32f1xx_hal_cortex.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- t -

  • TICK_INT_PRIORITY : stm32f1xx_hal_conf.h
  • TIM_AUTOMATICOUTPUT_DISABLE : stm32f1xx_hal_tim.h
  • TIM_AUTOMATICOUTPUT_ENABLE : stm32f1xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_DISABLE : stm32f1xx_hal_tim.h
  • TIM_AUTORELOAD_PRELOAD_ENABLE : stm32f1xx_hal_tim.h
  • TIM_BREAK_DISABLE : stm32f1xx_hal_tim.h
  • TIM_BREAK_ENABLE : stm32f1xx_hal_tim.h
  • TIM_BREAKPOLARITY_HIGH : stm32f1xx_hal_tim.h
  • TIM_BREAKPOLARITY_LOW : stm32f1xx_hal_tim.h
  • TIM_CALC_DTS : stm32f1xx_ll_tim.h
  • TIM_CCER_CCxE_MASK : stm32f1xx_hal_tim.h
  • TIM_CCER_CCxNE_MASK : stm32f1xx_hal_tim.h
  • TIM_CCx_DISABLE : stm32f1xx_hal_tim.h
  • TIM_CCx_ENABLE : stm32f1xx_hal_tim.h
  • TIM_CCxN_DISABLE : stm32f1xx_hal_tim.h
  • TIM_CCxN_ENABLE : stm32f1xx_hal_tim.h
  • TIM_CHANNEL_1 : stm32f1xx_hal_tim.h
  • TIM_CHANNEL_2 : stm32f1xx_hal_tim.h
  • TIM_CHANNEL_3 : stm32f1xx_hal_tim.h
  • TIM_CHANNEL_4 : stm32f1xx_hal_tim.h
  • TIM_CHANNEL_ALL : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_INVERTED : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPOLARITY_NONINVERTED : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV1 : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV2 : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV4 : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTPRESCALER_DIV8 : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_ETR : stm32f1xx_hal_tim.h
  • TIM_CLEARINPUTSOURCE_NONE : stm32f1xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV1 : stm32f1xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV2 : stm32f1xx_hal_tim.h
  • TIM_CLOCKDIVISION_DIV4 : stm32f1xx_hal_tim.h
  • TIM_CLOCKPOLARITY_BOTHEDGE : stm32f1xx_hal_tim.h
  • TIM_CLOCKPOLARITY_FALLING : stm32f1xx_hal_tim.h
  • TIM_CLOCKPOLARITY_INVERTED : stm32f1xx_hal_tim.h
  • TIM_CLOCKPOLARITY_NONINVERTED : stm32f1xx_hal_tim.h
  • TIM_CLOCKPOLARITY_RISING : stm32f1xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV1 : stm32f1xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV2 : stm32f1xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV4 : stm32f1xx_hal_tim.h
  • TIM_CLOCKPRESCALER_DIV8 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE1 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ETRMODE2 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_INTERNAL : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR0 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR1 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR2 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_ITR3 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1 : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI1ED : stm32f1xx_hal_tim.h
  • TIM_CLOCKSOURCE_TI2 : stm32f1xx_hal_tim.h
  • TIM_COMMUTATION_SOFTWARE : stm32f1xx_hal_tim.h
  • TIM_COMMUTATION_TRGI : stm32f1xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED1 : stm32f1xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED2 : stm32f1xx_hal_tim.h
  • TIM_COUNTERMODE_CENTERALIGNED3 : stm32f1xx_hal_tim.h
  • TIM_COUNTERMODE_DOWN : stm32f1xx_hal_tim.h
  • TIM_COUNTERMODE_UP : stm32f1xx_hal_tim.h
  • TIM_DMA_CC1 : stm32f1xx_hal_tim.h
  • TIM_DMA_CC2 : stm32f1xx_hal_tim.h
  • TIM_DMA_CC3 : stm32f1xx_hal_tim.h
  • TIM_DMA_CC4 : stm32f1xx_hal_tim.h
  • TIM_DMA_COM : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_CC1 : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_CC2 : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_CC3 : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_CC4 : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_COMMUTATION : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_DMA_ID_UPDATE : stm32f1xx_hal_tim.h
  • TIM_DMA_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_DMA_UPDATE : stm32f1xx_hal_tim.h
  • TIM_DMABASE_ARR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_BDTR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCER : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCMR1 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCMR2 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCR1 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCR2 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCR3 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CCR4 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CNT : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CR1 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_CR2 : stm32f1xx_hal_tim.h
  • TIM_DMABASE_DCR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_DIER : stm32f1xx_hal_tim.h
  • TIM_DMABASE_EGR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_PSC : stm32f1xx_hal_tim.h
  • TIM_DMABASE_RCR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_SMCR : stm32f1xx_hal_tim.h
  • TIM_DMABASE_SR : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_10TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_11TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_12TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_13TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_14TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_15TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_16TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_17TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_18TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_1TRANSFER : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_2TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_3TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_4TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_5TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_6TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_7TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_8TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_DMABURSTLENGTH_9TRANSFERS : stm32f1xx_hal_tim.h
  • TIM_ENCODERMODE_TI1 : stm32f1xx_hal_tim.h
  • TIM_ENCODERMODE_TI12 : stm32f1xx_hal_tim.h
  • TIM_ENCODERMODE_TI2 : stm32f1xx_hal_tim.h
  • TIM_ETRPOLARITY_INVERTED : stm32f1xx_hal_tim.h
  • TIM_ETRPOLARITY_NONINVERTED : stm32f1xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV1 : stm32f1xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV2 : stm32f1xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV4 : stm32f1xx_hal_tim.h
  • TIM_ETRPRESCALER_DIV8 : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_BREAK : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_CC1 : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_CC2 : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_CC3 : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_CC4 : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_COM : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_EVENTSOURCE_UPDATE : stm32f1xx_hal_tim.h
  • TIM_FLAG_BREAK : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC1 : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC1OF : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC2 : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC2OF : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC3 : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC3OF : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC4 : stm32f1xx_hal_tim.h
  • TIM_FLAG_CC4OF : stm32f1xx_hal_tim.h
  • TIM_FLAG_COM : stm32f1xx_hal_tim.h
  • TIM_FLAG_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_FLAG_UPDATE : stm32f1xx_hal_tim.h
  • TIM_GET_CHANNEL_INDEX : stm32f1xx_ll_tim.h
  • TIM_ICPOLARITY_FALLING : stm32f1xx_hal_tim.h
  • TIM_ICPOLARITY_RISING : stm32f1xx_hal_tim.h
  • TIM_ICPSC_DIV1 : stm32f1xx_hal_tim.h
  • TIM_ICPSC_DIV2 : stm32f1xx_hal_tim.h
  • TIM_ICPSC_DIV4 : stm32f1xx_hal_tim.h
  • TIM_ICPSC_DIV8 : stm32f1xx_hal_tim.h
  • TIM_ICSELECTION_DIRECTTI : stm32f1xx_hal_tim.h
  • TIM_ICSELECTION_INDIRECTTI : stm32f1xx_hal_tim.h
  • TIM_ICSELECTION_TRC : stm32f1xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_BOTHEDGE : stm32f1xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_FALLING : stm32f1xx_hal_tim.h
  • TIM_INPUTCHANNELPOLARITY_RISING : stm32f1xx_hal_tim.h
  • TIM_IT_BREAK : stm32f1xx_hal_tim.h
  • TIM_IT_CC1 : stm32f1xx_hal_tim.h
  • TIM_IT_CC2 : stm32f1xx_hal_tim.h
  • TIM_IT_CC3 : stm32f1xx_hal_tim.h
  • TIM_IT_CC4 : stm32f1xx_hal_tim.h
  • TIM_IT_COM : stm32f1xx_hal_tim.h
  • TIM_IT_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_IT_UPDATE : stm32f1xx_hal_tim.h
  • TIM_LOCKLEVEL_1 : stm32f1xx_hal_tim.h
  • TIM_LOCKLEVEL_2 : stm32f1xx_hal_tim.h
  • TIM_LOCKLEVEL_3 : stm32f1xx_hal_tim.h
  • TIM_LOCKLEVEL_OFF : stm32f1xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_DISABLE : stm32f1xx_hal_tim.h
  • TIM_MASTERSLAVEMODE_ENABLE : stm32f1xx_hal_tim.h
  • TIM_OCFAST_DISABLE : stm32f1xx_hal_tim.h
  • TIM_OCFAST_ENABLE : stm32f1xx_hal_tim.h
  • TIM_OCIDLESTATE_RESET : stm32f1xx_hal_tim.h
  • TIM_OCIDLESTATE_SET : stm32f1xx_hal_tim.h
  • TIM_OCMODE_ACTIVE : stm32f1xx_hal_tim.h
  • TIM_OCMODE_FORCED_ACTIVE : stm32f1xx_hal_tim.h
  • TIM_OCMODE_FORCED_INACTIVE : stm32f1xx_hal_tim.h
  • TIM_OCMODE_INACTIVE : stm32f1xx_hal_tim.h
  • TIM_OCMODE_PWM1 : stm32f1xx_hal_tim.h
  • TIM_OCMODE_PWM2 : stm32f1xx_hal_tim.h
  • TIM_OCMODE_TIMING : stm32f1xx_hal_tim.h
  • TIM_OCMODE_TOGGLE : stm32f1xx_hal_tim.h
  • TIM_OCNIDLESTATE_RESET : stm32f1xx_hal_tim.h
  • TIM_OCNIDLESTATE_SET : stm32f1xx_hal_tim.h
  • TIM_OCNPOLARITY_HIGH : stm32f1xx_hal_tim.h
  • TIM_OCNPOLARITY_LOW : stm32f1xx_hal_tim.h
  • TIM_OCPOLARITY_HIGH : stm32f1xx_hal_tim.h
  • TIM_OCPOLARITY_LOW : stm32f1xx_hal_tim.h
  • TIM_OPMODE_REPETITIVE : stm32f1xx_hal_tim.h
  • TIM_OPMODE_SINGLE : stm32f1xx_hal_tim.h
  • TIM_OSSI_DISABLE : stm32f1xx_hal_tim.h
  • TIM_OSSI_ENABLE : stm32f1xx_hal_tim.h
  • TIM_OSSR_DISABLE : stm32f1xx_hal_tim.h
  • TIM_OSSR_ENABLE : stm32f1xx_hal_tim.h
  • TIM_OUTPUTNSTATE_DISABLE : stm32f1xx_hal_tim.h
  • TIM_OUTPUTNSTATE_ENABLE : stm32f1xx_hal_tim.h
  • TIM_OUTPUTSTATE_DISABLE : stm32f1xx_hal_tim.h
  • TIM_OUTPUTSTATE_ENABLE : stm32f1xx_hal_tim.h
  • TIM_RESET_CAPTUREPOLARITY : stm32f1xx_hal_tim.h
  • TIM_RESET_ICPRESCALERVALUE : stm32f1xx_hal_tim.h
  • TIM_SET_CAPTUREPOLARITY : stm32f1xx_hal_tim.h
  • TIM_SET_ICPRESCALERVALUE : stm32f1xx_hal_tim.h
  • TIM_SLAVEMODE_DISABLE : stm32f1xx_hal_tim.h
  • TIM_SLAVEMODE_EXTERNAL1 : stm32f1xx_hal_tim.h
  • TIM_SLAVEMODE_GATED : stm32f1xx_hal_tim.h
  • TIM_SLAVEMODE_RESET : stm32f1xx_hal_tim.h
  • TIM_SLAVEMODE_TRIGGER : stm32f1xx_hal_tim.h
  • TIM_TI1SELECTION_CH1 : stm32f1xx_hal_tim.h
  • TIM_TI1SELECTION_XORCOMBINATION : stm32f1xx_hal_tim.h
  • TIM_TRGO_ENABLE : stm32f1xx_hal_tim.h
  • TIM_TRGO_OC1 : stm32f1xx_hal_tim.h
  • TIM_TRGO_OC1REF : stm32f1xx_hal_tim.h
  • TIM_TRGO_OC2REF : stm32f1xx_hal_tim.h
  • TIM_TRGO_OC3REF : stm32f1xx_hal_tim.h
  • TIM_TRGO_OC4REF : stm32f1xx_hal_tim.h
  • TIM_TRGO_RESET : stm32f1xx_hal_tim.h
  • TIM_TRGO_UPDATE : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_BOTHEDGE : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_FALLING : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_INVERTED : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_NONINVERTED : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPOLARITY_RISING : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV1 : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV2 : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV4 : stm32f1xx_hal_tim.h
  • TIM_TRIGGERPRESCALER_DIV8 : stm32f1xx_hal_tim.h
  • TIM_TS_ETRF : stm32f1xx_hal_tim.h
  • TIM_TS_ITR0 : stm32f1xx_hal_tim.h
  • TIM_TS_ITR1 : stm32f1xx_hal_tim.h
  • TIM_TS_ITR2 : stm32f1xx_hal_tim.h
  • TIM_TS_ITR3 : stm32f1xx_hal_tim.h
  • TIM_TS_NONE : stm32f1xx_hal_tim.h
  • TIM_TS_TI1F_ED : stm32f1xx_hal_tim.h
  • TIM_TS_TI1FP1 : stm32f1xx_hal_tim.h
  • TIM_TS_TI2FP2 : stm32f1xx_hal_tim.h
  • TSR_REGISTER_INDEX : stm32f1xx_hal_can.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Defines
  • _
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- u -

  • UART_BRR_SAMPLING16 : stm32f1xx_hal_uart.h
  • UART_BRR_SAMPLING8 : stm32f1xx_hal_uart.h
  • UART_CR1_REG_INDEX : stm32f1xx_hal_uart.h
  • UART_CR2_REG_INDEX : stm32f1xx_hal_uart.h
  • UART_CR3_REG_INDEX : stm32f1xx_hal_uart.h
  • UART_DIV_SAMPLING16 : stm32f1xx_hal_uart.h
  • UART_DIV_SAMPLING8 : stm32f1xx_hal_uart.h
  • UART_DIVFRAQ_SAMPLING16 : stm32f1xx_hal_uart.h
  • UART_DIVFRAQ_SAMPLING8 : stm32f1xx_hal_uart.h
  • UART_DIVMANT_SAMPLING16 : stm32f1xx_hal_uart.h
  • UART_DIVMANT_SAMPLING8 : stm32f1xx_hal_uart.h
  • UART_FLAG_CTS : stm32f1xx_hal_uart.h
  • UART_FLAG_FE : stm32f1xx_hal_uart.h
  • UART_FLAG_IDLE : stm32f1xx_hal_uart.h
  • UART_FLAG_LBD : stm32f1xx_hal_uart.h
  • UART_FLAG_NE : stm32f1xx_hal_uart.h
  • UART_FLAG_ORE : stm32f1xx_hal_uart.h
  • UART_FLAG_PE : stm32f1xx_hal_uart.h
  • UART_FLAG_RXNE : stm32f1xx_hal_uart.h
  • UART_FLAG_TC : stm32f1xx_hal_uart.h
  • UART_FLAG_TXE : stm32f1xx_hal_uart.h
  • UART_HWCONTROL_CTS : stm32f1xx_hal_uart.h
  • UART_HWCONTROL_NONE : stm32f1xx_hal_uart.h
  • UART_HWCONTROL_RTS : stm32f1xx_hal_uart.h
  • UART_HWCONTROL_RTS_CTS : stm32f1xx_hal_uart.h
  • UART_IT_CTS : stm32f1xx_hal_uart.h
  • UART_IT_ERR : stm32f1xx_hal_uart.h
  • UART_IT_IDLE : stm32f1xx_hal_uart.h
  • UART_IT_LBD : stm32f1xx_hal_uart.h
  • UART_IT_MASK : stm32f1xx_hal_uart.h
  • UART_IT_PE : stm32f1xx_hal_uart.h
  • UART_IT_RXNE : stm32f1xx_hal_uart.h
  • UART_IT_TC : stm32f1xx_hal_uart.h
  • UART_IT_TXE : stm32f1xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_10B : stm32f1xx_hal_uart.h
  • UART_LINBREAKDETECTLENGTH_11B : stm32f1xx_hal_uart.h
  • UART_MODE_RX : stm32f1xx_hal_uart.h
  • UART_MODE_TX : stm32f1xx_hal_uart.h
  • UART_MODE_TX_RX : stm32f1xx_hal_uart.h
  • UART_OVERSAMPLING_16 : stm32f1xx_hal_uart.h
  • UART_PARITY_EVEN : stm32f1xx_hal_uart.h
  • UART_PARITY_NONE : stm32f1xx_hal_uart.h
  • UART_PARITY_ODD : stm32f1xx_hal_uart.h
  • UART_STATE_DISABLE : stm32f1xx_hal_uart.h
  • UART_STATE_ENABLE : stm32f1xx_hal_uart.h
  • UART_STOPBITS_1 : stm32f1xx_hal_uart.h
  • UART_STOPBITS_2 : stm32f1xx_hal_uart.h
  • UART_WAKEUPMETHOD_ADDRESSMARK : stm32f1xx_hal_uart.h
  • UART_WAKEUPMETHOD_IDLELINE : stm32f1xx_hal_uart.h
  • UART_WORDLENGTH_8B : stm32f1xx_hal_uart.h
  • UART_WORDLENGTH_9B : stm32f1xx_hal_uart.h
  • UID_BASE_ADDRESS : stm32f1xx_ll_utils.h
  • USART_BRR : stm32f1xx_hal_usart.h
  • USART_CLOCK_DISABLE : stm32f1xx_hal_usart.h
  • USART_CLOCK_ENABLE : stm32f1xx_hal_usart.h
  • USART_CR1_REG_INDEX : stm32f1xx_hal_usart.h
  • USART_CR2_REG_INDEX : stm32f1xx_hal_usart.h
  • USART_CR3_REG_INDEX : stm32f1xx_hal_usart.h
  • USART_DIV : stm32f1xx_hal_usart.h
  • USART_DIVFRAQ : stm32f1xx_hal_usart.h
  • USART_DIVMANT : stm32f1xx_hal_usart.h
  • USART_FLAG_FE : stm32f1xx_hal_usart.h
  • USART_FLAG_IDLE : stm32f1xx_hal_usart.h
  • USART_FLAG_NE : stm32f1xx_hal_usart.h
  • USART_FLAG_ORE : stm32f1xx_hal_usart.h
  • USART_FLAG_PE : stm32f1xx_hal_usart.h
  • USART_FLAG_RXNE : stm32f1xx_hal_usart.h
  • USART_FLAG_TC : stm32f1xx_hal_usart.h
  • USART_FLAG_TXE : stm32f1xx_hal_usart.h
  • USART_IT_CTS : stm32f1xx_hal_usart.h
  • USART_IT_ERR : stm32f1xx_hal_usart.h
  • USART_IT_IDLE : stm32f1xx_hal_usart.h
  • USART_IT_LBD : stm32f1xx_hal_usart.h
  • USART_IT_MASK : stm32f1xx_hal_usart.h
  • USART_IT_PE : stm32f1xx_hal_usart.h
  • USART_IT_RXNE : stm32f1xx_hal_usart.h
  • USART_IT_TC : stm32f1xx_hal_usart.h
  • USART_IT_TXE : stm32f1xx_hal_usart.h
  • USART_LASTBIT_DISABLE : stm32f1xx_hal_usart.h
  • USART_LASTBIT_ENABLE : stm32f1xx_hal_usart.h
  • USART_MODE_RX : stm32f1xx_hal_usart.h
  • USART_MODE_TX : stm32f1xx_hal_usart.h
  • USART_MODE_TX_RX : stm32f1xx_hal_usart.h
  • USART_NACK_DISABLE : stm32f1xx_hal_usart.h
  • USART_NACK_ENABLE : stm32f1xx_hal_usart.h
  • USART_PARITY_EVEN : stm32f1xx_hal_usart.h
  • USART_PARITY_NONE : stm32f1xx_hal_usart.h
  • USART_PARITY_ODD : stm32f1xx_hal_usart.h
  • USART_PHASE_1EDGE : stm32f1xx_hal_usart.h
  • USART_PHASE_2EDGE : stm32f1xx_hal_usart.h
  • USART_POLARITY_HIGH : stm32f1xx_hal_usart.h
  • USART_POLARITY_LOW : stm32f1xx_hal_usart.h
  • USART_POSITION_GTPR_GT : stm32f1xx_ll_usart.h
  • USART_STOPBITS_0_5 : stm32f1xx_hal_usart.h
  • USART_STOPBITS_1 : stm32f1xx_hal_usart.h
  • USART_STOPBITS_1_5 : stm32f1xx_hal_usart.h
  • USART_STOPBITS_2 : stm32f1xx_hal_usart.h
  • USART_TIMEOUT_VALUE : stm32f1xx_hal_usart.c
  • USART_WORDLENGTH_8B : stm32f1xx_hal_usart.h
  • USART_WORDLENGTH_9B : stm32f1xx_hal_usart.h
  • USB_EP0StartXfer : stm32f1xx_hal_pcd.h
  • USB_WAKEUP_EXTI_LINE : stm32f1xx_hal_pcd.h
  • USBD_FS_TRDT_VALUE : stm32f1xx_hal_pcd.h
  • USE_RTOS : stm32f1xx_hal_conf.h
  • USE_SPI_CRC : stm32f1xx_hal_conf.h
  • UTILS_HSE_FREQUENCY_MAX : stm32f1xx_ll_utils.c
  • UTILS_HSE_FREQUENCY_MIN : stm32f1xx_ll_utils.c
  • UTILS_LATENCY1_FREQ : stm32f1xx_ll_utils.c
  • UTILS_LATENCY2_FREQ : stm32f1xx_ll_utils.c
  • UTILS_PLL_OUTPUT_MAX : stm32f1xx_ll_utils.c
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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  • VDD_VALUE : stm32f1xx_hal_conf.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Globals

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- w -

  • WWDG_EWI_DISABLE : stm32f1xx_hal_wwdg.h
  • WWDG_EWI_ENABLE : stm32f1xx_hal_wwdg.h
  • WWDG_FLAG_EWIF : stm32f1xx_hal_wwdg.h
  • WWDG_IT_EWI : stm32f1xx_hal_wwdg.h
  • WWDG_PRESCALER_1 : stm32f1xx_hal_wwdg.h
  • WWDG_PRESCALER_2 : stm32f1xx_hal_wwdg.h
  • WWDG_PRESCALER_4 : stm32f1xx_hal_wwdg.h
  • WWDG_PRESCALER_8 : stm32f1xx_hal_wwdg.h
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal.h File Reference

  • File List
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  • Drivers
  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_hal.h File Reference

This file contains all the functions prototypes for the HAL module driver. More...

#include "stm32f1xx_hal_conf.h"

Go to the source code of this file.

Defines

#define | __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
TIM2 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
TIM3 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
TIM4 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
#define | __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
WWDG Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
IWDG Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
#define | __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
I2C1 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
#define | __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
I2C2 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#define | __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
CAN1 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
#define | __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
TIM1 Peripherals Debug mode.
#define | __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_GetUID (uint32_t *UID)
Return the unique device identifier (UID based on 96 bits)

Detailed Description

This file contains all the functions prototypes for the HAL module driver.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal.h.

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STM32F103xB HAL User Manual: stm32f1xx_hal_adc.h File Reference

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  • STM32F1xx_HAL_Driver
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Data Structures | Defines | Functions
stm32f1xx_hal_adc.h File Reference

Header file containing functions prototypes of ADC HAL library. More...

#include "stm32f1xx_hal_def.h"
#include "stm32f1xx_hal_adc_ex.h"

Go to the source code of this file.

Data Structures

struct | ADC_InitTypeDef
Structure definition of ADC and regular group initialization. More...
struct | ADC_ChannelConfTypeDef
Structure definition of ADC channel for regular group. More...
struct | ADC_AnalogWDGConfTypeDef
ADC Configuration analog watchdog definition. More...
struct | ADC_HandleTypeDef
ADC handle Structure definition. More...

Defines

#define | HAL_ADC_STATE_RESET 0x00000000U
HAL ADC state machine: ADC states definition (bitfields)
#define | HAL_ADC_STATE_READY 0x00000001U
#define | HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U
#define | HAL_ADC_STATE_TIMEOUT 0x00000004U
#define | HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U
#define | HAL_ADC_STATE_ERROR_CONFIG 0x00000020U
#define | HAL_ADC_STATE_ERROR_DMA 0x00000040U
#define | HAL_ADC_STATE_REG_BUSY 0x00000100U
#define | HAL_ADC_STATE_REG_EOC 0x00000200U
#define | HAL_ADC_STATE_REG_OVR 0x00000400U
#define | HAL_ADC_STATE_REG_EOSMP 0x00000800U
#define | HAL_ADC_STATE_INJ_BUSY 0x00001000U
#define | HAL_ADC_STATE_INJ_EOC 0x00002000U
#define | HAL_ADC_STATE_INJ_JQOVF 0x00004000U
#define | HAL_ADC_STATE_AWD1 0x00010000U
#define | HAL_ADC_STATE_AWD2 0x00020000U
#define | HAL_ADC_STATE_AWD3 0x00040000U
#define | HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U
#define | HAL_ADC_ERROR_NONE 0x00U
#define | HAL_ADC_ERROR_INTERNAL 0x01U
#define | HAL_ADC_ERROR_OVR 0x02U
#define | HAL_ADC_ERROR_DMA 0x04U
#define | ADC_DATAALIGN_RIGHT 0x00000000U
#define | ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
#define | ADC_SCAN_DISABLE 0x00000000U
#define | ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
#define | ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
#define | ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
#define | ADC_CHANNEL_0 0x00000000U
#define | ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
#define | ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
#define | ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
#define | ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
#define | ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 ))
#define | ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 ))
#define | ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
#define | ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
#define | ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
#define | ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
#define | ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
#define | ADC_SAMPLETIME_1CYCLE_5 0x00000000U
#define | ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0))
#define | ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 ))
#define | ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))
#define | ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 ))
#define | ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0))
#define | ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 ))
#define | ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0))
#define | ADC_REGULAR_RANK_1 0x00000001U
#define | ADC_REGULAR_RANK_2 0x00000002U
#define | ADC_REGULAR_RANK_3 0x00000003U
#define | ADC_REGULAR_RANK_4 0x00000004U
#define | ADC_REGULAR_RANK_5 0x00000005U
#define | ADC_REGULAR_RANK_6 0x00000006U
#define | ADC_REGULAR_RANK_7 0x00000007U
#define | ADC_REGULAR_RANK_8 0x00000008U
#define | ADC_REGULAR_RANK_9 0x00000009U
#define | ADC_REGULAR_RANK_10 0x0000000AU
#define | ADC_REGULAR_RANK_11 0x0000000BU
#define | ADC_REGULAR_RANK_12 0x0000000CU
#define | ADC_REGULAR_RANK_13 0x0000000DU
#define | ADC_REGULAR_RANK_14 0x0000000EU
#define | ADC_REGULAR_RANK_15 0x0000000FU
#define | ADC_REGULAR_RANK_16 0x00000010U
#define | ADC_ANALOGWATCHDOG_NONE 0x00000000U
#define | ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define | ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define | ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
#define | ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
#define | ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
#define | ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
#define | ADC_AWD1_EVENT ADC_AWD_EVENT
#define | ADC_IT_EOC ADC_CR1_EOCIE
#define | ADC_IT_JEOC ADC_CR1_JEOCIE
#define | ADC_IT_AWD ADC_CR1_AWDIE
#define | ADC_FLAG_STRT ADC_SR_STRT
#define | ADC_FLAG_JSTRT ADC_SR_JSTRT
#define | ADC_FLAG_EOC ADC_SR_EOC
#define | ADC_FLAG_JEOC ADC_SR_JEOC
#define | ADC_FLAG_AWD ADC_SR_AWD
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
#define | ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0
#define | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0
#define | ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
#define | ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define | ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
#define | ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define | ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define | ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
#define | ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define | ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
#define | ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define | ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define | ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
#define | __HAL_ADC_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
Enable the ADC peripheral.
#define | __HAL_ADC_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
Disable the ADC peripheral.
#define | __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Enable the ADC end of conversion interrupt.
#define | __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
Disable the ADC end of conversion interrupt.
#define | __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified ADC interrupt source is enabled or disabled.
#define | __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Get the selected ADC's flag status.
#define | __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
Clear the ADC's pending flags.
#define | __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
Reset ADC handle state.
#define | ADC_IS_ENABLE(__HANDLE__)
Verification of ADC state: enabled or disabled.
#define | ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
Test if conversion trigger of regular group is software start or external trigger.
#define | ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
Test if conversion trigger of injected group is software start or external trigger.
#define | ADC_STATE_CLR_SET MODIFY_REG
Simultaneously clears and sets specific bits of the handle State.
#define | ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
Clear ADC error code (set it to error code: "no error")
#define | ADC_SQR1_L_SHIFT(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
Set ADC number of conversions into regular channel sequence length.
#define | ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
Set the ADC's sample time for channel numbers between 10 and 18.
#define | ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
Set the ADC's sample time for channel numbers between 0 and 9.
#define | ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
Set the selected regular channel rank for rank between 1 and 6.
#define | ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
Set the selected regular channel rank for rank between 7 and 12.
#define | ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
Set the selected regular channel rank for rank between 13 and 16.
#define | ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
Set the injected sequence length.
#define | ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
Set the selected injected channel rank Note: on STM32F1 devices, channel rank position in JSQR register is depending on total number of ranks selected into injected sequencer (ranks sequence starting from 4-JL)
#define | ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
Enable ADC continuous conversion mode.
#define | ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
Configures the number of discontinuous conversions for the regular group channels.
#define | ADC_CR1_SCAN_SET(_SCAN_MODE_)
Enable ADC scan mode to convert multiple ranks with sequencer.
#define | ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)
Get the maximum ADC conversion cycles on all channels.
#define | IS_ADC_DATA_ALIGN(ALIGN)
#define | IS_ADC_SCAN_MODE(SCAN_MODE)
#define | IS_ADC_EXTTRIG_EDGE(EDGE)
#define | IS_ADC_CHANNEL(CHANNEL)
#define | IS_ADC_SAMPLE_TIME(TIME)
#define | IS_ADC_REGULAR_RANK(CHANNEL)
#define | IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG)
#define | IS_ADC_CONVERSION_GROUP(CONVERSION)
#define | IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
#define | IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
#define | IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
#define | IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non blocking mode (ADC conversion with interruption or transfer by DMA)
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures the the selected channel to be linked to the regular group.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_ConversionStop_Disable (ADC_HandleTypeDef *hadc)
Stop ADC conversion and disable the selected ADC.
void | ADC_StabilizationTime (uint32_t DelayUs)
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

Header file containing functions prototypes of ADC HAL library.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_adc.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_adc_ex.h File Reference

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Data Structures | Defines | Functions
stm32f1xx_hal_adc_ex.h File Reference

Header file of ADC HAL extension module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | ADC_InjectionConfTypeDef
ADC Configuration injected Channel structure definition. More...
struct | ADC_MultiModeTypeDef
Structure definition of ADC multimode. More...

Defines

#define | ADC_INJECTED_RANK_1 0x00000001U
#define | ADC_INJECTED_RANK_2 0x00000002U
#define | ADC_INJECTED_RANK_3 0x00000003U
#define | ADC_INJECTED_RANK_4 0x00000004U
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U
#define | ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
#define | ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
#define | ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
#define | ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
#define | ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
#define | ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
#define | ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
#define | ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
#define | ADC_SOFTWARE_START ADC1_2_3_SWSTART
#define | ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
#define | ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
#define | ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
#define | ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
#define | ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
#define | ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
#define | ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
#define | ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
#define | ADC_MODE_INDEPENDENT 0x00000000U
#define | ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0))
#define | ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 ))
#define | ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0))
#define | ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 ))
#define | ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0))
#define | ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ))
#define | ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0))
#define | ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 ))
#define | ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0))
#define | ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U
#define | ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0))
#define | ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 ))
#define | ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define | ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
#define | ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
#define | ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define | ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
#define | ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 ))
#define | ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define | ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
#define | ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
#define | ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0))
#define | ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define | ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) (__EXT_TRIG_CONV__)
For devices with 3 ADCs: Defines the external trigger source for regular group according to ADC into common group ADC1&ADC2 or ADC3 (some triggers with same source have different value to be programmed into ADC EXTSEL bits of CR2 register).
#define | ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) (__EXT_TRIG_INJECTCONV__)
For devices with 3 ADCs: Defines the external trigger source for injected group according to ADC into common group ADC1&ADC2 or ADC3 (some triggers with same source have different value to be programmed into ADC JEXTSEL bits of CR2 register).
#define | ADC_MULTIMODE_IS_ENABLE(__HANDLE__)
Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
#define | ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)
Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
#define | ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)
Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
#define | ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
Set handle of the other ADC sharing the common multimode settings.
#define | ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) ((__HANDLE_SLAVE__)->Instance = ADC2)
Set handle of the ADC slave associated to the ADC master On STM32F1 devices, ADC slave is always ADC2 (this can be different on other STM32 devices)
#define | IS_ADC_INJECTED_RANK(CHANNEL)
#define | IS_ADC_EXTTRIGINJEC_EDGE(EDGE)
#define | IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
#define | IS_ADC_EXTTRIG(REGTRIG)
#define | IS_ADC_EXTTRIGINJEC(REGTRIG)
#define | IS_ADC_MODE(MODE)

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Returns the last ADC Master&Slave regular conversions results data in the selected multi mode.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures the ADC injected group and the selected channel to be linked to the injected group.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.

Detailed Description

Header file of ADC HAL extension module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_adc_ex.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_can.h File Reference

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stm32f1xx_hal_can.h File Reference

Header file of CAN HAL module. More...

#include "stm32f1xx_hal_def.h"
#include "stm32f1xx_hal_can_ex.h"

Go to the source code of this file.

Data Structures

struct | CAN_InitTypeDef
CAN init structure definition. More...
struct | CanTxMsgTypeDef
CAN Tx message structure definition. More...
struct | CanRxMsgTypeDef
CAN Rx message structure definition. More...
struct | CAN_HandleTypeDef
CAN handle Structure definition. More...

Defines

#define | HAL_CAN_ERROR_NONE 0x00U
#define | HAL_CAN_ERROR_EWG 0x01U
#define | HAL_CAN_ERROR_EPV 0x02U
#define | HAL_CAN_ERROR_BOF 0x04U
#define | HAL_CAN_ERROR_STF 0x08U
#define | HAL_CAN_ERROR_FOR 0x10U
#define | HAL_CAN_ERROR_ACK 0x20U
#define | HAL_CAN_ERROR_BR 0x40U
#define | HAL_CAN_ERROR_BD 0x80U
#define | HAL_CAN_ERROR_CRC 0x100U
#define | HAL_CAN_ERROR_FOV0 0x200U
#define | HAL_CAN_ERROR_FOV1 0x400U
#define | CAN_INITSTATUS_FAILED 0x00000000U
#define | CAN_INITSTATUS_SUCCESS 0x00000001U
#define | CAN_MODE_NORMAL 0x00000000U
#define | CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM)
#define | CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM)
#define | CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))
#define | CAN_SJW_1TQ 0x00000000U
#define | CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0)
#define | CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1)
#define | CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW)
#define | CAN_BS1_1TQ 0x00000000U
#define | CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0)
#define | CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1)
#define | CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2)
#define | CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3)
#define | CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))
#define | CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))
#define | CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))
#define | CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))
#define | CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))
#define | CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))
#define | CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1)
#define | CAN_BS2_1TQ 0x00000000U
#define | CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0)
#define | CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1)
#define | CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))
#define | CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2)
#define | CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))
#define | CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))
#define | CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2)
#define | CAN_FILTERMODE_IDMASK ((uint8_t)0x00)
#define | CAN_FILTERMODE_IDLIST ((uint8_t)0x01)
#define | CAN_FILTERSCALE_16BIT ((uint8_t)0x00)
#define | CAN_FILTERSCALE_32BIT ((uint8_t)0x01)
#define | CAN_FILTER_FIFO0 ((uint8_t)0x00)
#define | CAN_FILTER_FIFO1 ((uint8_t)0x01)
#define | CAN_ID_STD 0x00000000U
#define | CAN_ID_EXT 0x00000004U
#define | CAN_RTR_DATA 0x00000000U
#define | CAN_RTR_REMOTE 0x00000002U
#define | CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04)
#define | CAN_FIFO0 ((uint8_t)0x00)
#define | CAN_FIFO1 ((uint8_t)0x01)
#define | CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))
#define | CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION))
#define | CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION))
#define | CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION))
#define | CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION))
#define | CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))
#define | CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION))
#define | CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION))
#define | CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION))
#define | CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION))
#define | CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION))
#define | CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION))
#define | CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION))
#define | CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION))
#define | CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION))
#define | CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION))
#define | CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION))
#define | CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION))
#define | CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION))
#define | CAN_IT_TME ((uint32_t)CAN_IER_TMEIE)
#define | CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0)
#define | CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0)
#define | CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0)
#define | CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1)
#define | CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1)
#define | CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1)
#define | CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE)
#define | CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE)
#define | CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE)
#define | CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE)
#define | CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE)
#define | CAN_IT_LEC ((uint32_t)CAN_IER_LECIE)
#define | CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE)
#define | TSR_REGISTER_INDEX 0x5U
#define | RF0R_REGISTER_INDEX 0x2U
#define | RF1R_REGISTER_INDEX 0x4U
#define | MSR_REGISTER_INDEX 0x1U
#define | ESR_REGISTER_INDEX 0x3U
#define | CAN_TSR_RQCP0_BIT_POSITION 0x00000000U
#define | CAN_TSR_RQCP1_BIT_POSITION 0x00000008U
#define | CAN_TSR_RQCP2_BIT_POSITION 0x00000010U
#define | CAN_TSR_TXOK0_BIT_POSITION 0x00000001U
#define | CAN_TSR_TXOK1_BIT_POSITION 0x00000009U
#define | CAN_TSR_TXOK2_BIT_POSITION 0x00000011U
#define | CAN_TSR_TME0_BIT_POSITION 0x0000001AU
#define | CAN_TSR_TME1_BIT_POSITION 0x0000001BU
#define | CAN_TSR_TME2_BIT_POSITION 0x0000001CU
#define | CAN_RF0R_FF0_BIT_POSITION 0x00000003U
#define | CAN_RF0R_FOV0_BIT_POSITION 0x00000004U
#define | CAN_RF1R_FF1_BIT_POSITION 0x00000003U
#define | CAN_RF1R_FOV1_BIT_POSITION 0x00000004U
#define | CAN_MSR_WKU_BIT_POSITION 0x00000003U
#define | CAN_MSR_SLAK_BIT_POSITION 0x00000001U
#define | CAN_MSR_SLAKI_BIT_POSITION 0x00000004U
#define | CAN_ESR_EWG_BIT_POSITION 0x00000000U
#define | CAN_ESR_EPV_BIT_POSITION 0x00000001U
#define | CAN_ESR_BOF_BIT_POSITION 0x00000002U
#define | CAN_FLAG_MASK 0x000000FFU
#define | CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define | CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define | CAN_TXMAILBOX_2 ((uint8_t)0x02)
#define | __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
Reset CAN handle state.
#define | __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
Enable the specified CAN interrupts.
#define | __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
Disable the specified CAN interrupts.
#define | __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__)
Return the number of pending received messages.
#define | __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__)
Check whether the specified CAN flag is set or not.
#define | __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__)
Clear the specified CAN pending flag.
#define | __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check if the specified CAN interrupt source is enabled or disabled.
#define | __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)
Check the transmission status of a CAN Frame.
#define | __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__)
Release the specified receive FIFO.
#define | __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)
Cancel a transmit request.
#define | __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__)
Enable or disables the DBG Freeze for CAN.
#define | IS_CAN_MODE(MODE)
#define | IS_CAN_SJW(SJW)
#define | IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define | IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define | IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define | IS_CAN_FILTER_MODE(MODE)
#define | IS_CAN_FILTER_SCALE(SCALE)
#define | IS_CAN_FILTER_FIFO(FIFO)
#define | IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define | IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
#define | IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU)
#define | IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
#define | IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
#define | IS_CAN_IDTYPE(IDTYPE)
#define | IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define | IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))

Enumerations

enum HAL_CAN_StateTypeDef {
HAL_CAN_STATE_RESET = 0x00U, HAL_CAN_STATE_READY = 0x01U, HAL_CAN_STATE_BUSY = 0x02U, HAL_CAN_STATE_BUSY_TX = 0x12U,
HAL_CAN_STATE_BUSY_RX = 0x22U, HAL_CAN_STATE_BUSY_TX_RX = 0x32U, HAL_CAN_STATE_TIMEOUT = 0x03U, HAL_CAN_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
Deinitializes the CANx peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initializes the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitializes the CAN MSP.
HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enters the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handles CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.
HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
return the CAN state

Detailed Description

Header file of CAN HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_can.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_can_ex.h File Reference

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stm32f1xx_hal_can_ex.h File Reference

Header file of CAN HAL Extension module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CAN_FilterConfTypeDef
CAN filter configuration structure definition. More...

Defines

#define | IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13U)

Detailed Description

Header file of CAN HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_can_ex.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_cortex.h File Reference

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stm32f1xx_hal_cortex.h File Reference

Header file of CORTEX HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Defines

#define | NVIC_PRIORITYGROUP_0 0x00000007U
#define | NVIC_PRIORITYGROUP_1 0x00000006U
#define | NVIC_PRIORITYGROUP_2 0x00000005U
#define | NVIC_PRIORITYGROUP_3 0x00000004U
#define | NVIC_PRIORITYGROUP_4 0x00000003U
#define | SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | SYSTICK_CLKSOURCE_HCLK 0x00000004U
#define | IS_NVIC_PRIORITY_GROUP(GROUP)
#define | IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define | IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
#define | IS_SYSTICK_CLK_SOURCE(SOURCE)

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.

Detailed Description

Header file of CORTEX HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_cortex.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_crc.h File Reference

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stm32f1xx_hal_crc.h File Reference

Header file of CRC HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | CRC_HandleTypeDef
CRC handle Structure definition. More...

Defines

#define | __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
Reset CRC handle state.
#define | __HAL_CRC_DR_RESET(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET))
Resets CRC Data Register.
#define | __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
Stores a 8-bit data in the Independent Data(ID) register.
#define | __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
Returns the 8-bit data stored in the Independent Data(ID) register.

Enumerations

enum HAL_CRC_StateTypeDef {
HAL_CRC_STATE_RESET = 0x00U, HAL_CRC_STATE_READY = 0x01U, HAL_CRC_STATE_BUSY = 0x02U, HAL_CRC_STATE_TIMEOUT = 0x03U,
HAL_CRC_STATE_ERROR = 0x04U
}
CRC HAL State Structure definition. More...

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initializes the CRC according to the specified parameters in the CRC_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer using combination of the previous CRC value and the new one.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer independently of the previous CRC value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Returns the CRC state.

Detailed Description

Header file of CRC HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_crc.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dma.h File Reference

  • File List
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  • Drivers
  • STM32F1xx_HAL_Driver
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32f1xx_hal_dma.h File Reference

Header file of DMA HAL module. More...

#include "stm32f1xx_hal_def.h"
#include "stm32f1xx_hal_dma_ex.h"

Go to the source code of this file.

Data Structures

struct | DMA_InitTypeDef
DMA Configuration Structure definition. More...
struct | __DMA_HandleTypeDef
DMA handle Structure definition. More...

Defines

#define | HAL_DMA_ERROR_NONE 0x00000000U
#define | HAL_DMA_ERROR_TE 0x00000001U
#define | HAL_DMA_ERROR_NO_XFER 0x00000004U
#define | HAL_DMA_ERROR_TIMEOUT 0x00000020U
#define | HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U
#define | DMA_PERIPH_TO_MEMORY 0x00000000U
#define | DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR)
#define | DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM)
#define | DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC)
#define | DMA_PINC_DISABLE 0x00000000U
#define | DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC)
#define | DMA_MINC_DISABLE 0x00000000U
#define | DMA_PDATAALIGN_BYTE 0x00000000U
#define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0)
#define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1)
#define | DMA_MDATAALIGN_BYTE 0x00000000U
#define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0)
#define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1)
#define | DMA_NORMAL 0x00000000U
#define | DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC)
#define | DMA_PRIORITY_LOW 0x00000000U
#define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0)
#define | DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1)
#define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL)
#define | DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define | DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define | DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
#define | DMA_FLAG_GL1 0x00000001U
#define | DMA_FLAG_TC1 0x00000002U
#define | DMA_FLAG_HT1 0x00000004U
#define | DMA_FLAG_TE1 0x00000008U
#define | DMA_FLAG_GL2 0x00000010U
#define | DMA_FLAG_TC2 0x00000020U
#define | DMA_FLAG_HT2 0x00000040U
#define | DMA_FLAG_TE2 0x00000080U
#define | DMA_FLAG_GL3 0x00000100U
#define | DMA_FLAG_TC3 0x00000200U
#define | DMA_FLAG_HT3 0x00000400U
#define | DMA_FLAG_TE3 0x00000800U
#define | DMA_FLAG_GL4 0x00001000U
#define | DMA_FLAG_TC4 0x00002000U
#define | DMA_FLAG_HT4 0x00004000U
#define | DMA_FLAG_TE4 0x00008000U
#define | DMA_FLAG_GL5 0x00010000U
#define | DMA_FLAG_TC5 0x00020000U
#define | DMA_FLAG_HT5 0x00040000U
#define | DMA_FLAG_TE5 0x00080000U
#define | DMA_FLAG_GL6 0x00100000U
#define | DMA_FLAG_TC6 0x00200000U
#define | DMA_FLAG_HT6 0x00400000U
#define | DMA_FLAG_TE6 0x00800000U
#define | DMA_FLAG_GL7 0x01000000U
#define | DMA_FLAG_TC7 0x02000000U
#define | DMA_FLAG_HT7 0x04000000U
#define | DMA_FLAG_TE7 0x08000000U
#define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Reset DMA handle state.
#define | __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
Enable the specified DMA Channel.
#define | __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
Disable the specified DMA Channel.
#define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
Enables the specified DMA Channel interrupts.
#define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
Disable the specified DMA Channel interrupts.
#define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified DMA Channel interrupt is enabled or not.
#define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
Return the number of remaining data units in the current DMA Channel transfer.
#define | IS_DMA_DIRECTION(DIRECTION)
#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define | IS_DMA_PERIPHERAL_INC_STATE(STATE)
#define | IS_DMA_MEMORY_INC_STATE(STATE)
#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)
#define | IS_DMA_MEMORY_DATA_SIZE(SIZE)
#define | IS_DMA_MODE(MODE)
#define | IS_DMA_PRIORITY(PRIORITY)

Typedefs

typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef
DMA handle Structure definition.

Enumerations

enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U }
HAL DMA State structures definition. More...
enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U }
HAL DMA Error Code structure definition. More...
enum HAL_DMA_CallbackIDTypeDef {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U,
HAL_DMA_XFER_ALL_CB_ID = 0x04U
}
HAL DMA Callback ID structure definition. More...

Functions

HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA hande state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

Header file of DMA HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_dma.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dma_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32F1xx_HAL_Driver
  • Inc
Defines
stm32f1xx_hal_dma_ex.h File Reference

Header file of DMA HAL extension module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Defines

#define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__)
Returns the current DMA Channel transfer complete flag.
#define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel half transfer complete flag.
#define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel transfer error flag.
#define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)
Return the current DMA Channel Global interrupt flag.
#define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
Get the DMA Channel pending flags.
#define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
Clear the DMA Channel pending flags.

Detailed Description

Header file of DMA HAL extension module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_dma_ex.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_flash.h File Reference

  • File List
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  • Drivers
  • STM32F1xx_HAL_Driver
  • Inc
Data Structures | Defines | Enumerations | Functions
stm32f1xx_hal_flash.h File Reference

Header file of Flash HAL module. More...

#include "stm32f1xx_hal_def.h"
#include "stm32f1xx_hal_flash_ex.h"

Go to the source code of this file.

Data Structures

struct | FLASH_ProcessTypeDef
FLASH handle Structure definition. More...

Defines

#define | FLASH_TIMEOUT_VALUE 50000U /* 50 s */
#define | IS_FLASH_TYPEPROGRAM(VALUE)
#define | IS_FLASH_LATENCY(__LATENCY__)
#define | HAL_FLASH_ERROR_NONE 0x00U
#define | HAL_FLASH_ERROR_PROG 0x01U
#define | HAL_FLASH_ERROR_WRP 0x02U
#define | HAL_FLASH_ERROR_OPTV 0x04U
#define | FLASH_TYPEPROGRAM_HALFWORD 0x01U
#define | FLASH_TYPEPROGRAM_WORD 0x02U
#define | FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U
#define | FLASH_LATENCY_0 0x00000000U
#define | FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | FLASH_LATENCY_2 FLASH_ACR_LATENCY_1
#define | __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
Enable the FLASH half cycle access.
#define | __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
Disable the FLASH half cycle access.
#define | __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
Set the FLASH Latency.
#define | __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
Get the FLASH Latency.
#define | __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
Enable the FLASH prefetch buffer.
#define | __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
Disable the FLASH prefetch buffer.

Enumerations

enum FLASH_ProcedureTypeDef {
FLASH_PROC_NONE = 0U, FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_MASSERASE = 2U, FLASH_PROC_PROGRAMHALFWORD = 3U,
FLASH_PROC_PROGRAMWORD = 4U, FLASH_PROC_PROGRAMDOUBLEWORD = 5U
}
FLASH Procedure structure definition. More...

Functions

HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Detailed Description

Header file of Flash HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_flash.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_flash_ex.h File Reference

  • File List
  • Globals
  • Drivers
  • STM32F1xx_HAL_Driver
  • Inc
Data Structures | Defines | Functions
stm32f1xx_hal_flash_ex.h File Reference

Header file of Flash HAL Extended module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Options bytes program structure definition. More...

Defines

#define | FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
#define | OBR_REG_INDEX 1U
#define | SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
#define | IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define | IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
#define | IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
#define | IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
#define | IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
#define | IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define | IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define | IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define | IS_FLASH_NB_PAGES(ADDRESS, NBPAGES)
#define | IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#define | IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
#define | IS_FLASH_PROGRAM_ADDRESS(ADDRESS)
#define | FLASH_PAGE_SIZE 0x400U
#define | FLASH_TYPEERASE_PAGES 0x00U
#define | FLASH_TYPEERASE_MASSERASE 0x02U
#define | FLASH_BANK_1 1U
#define | OPTIONBYTE_WRP 0x01U
#define | OPTIONBYTE_RDP 0x02U
#define | OPTIONBYTE_USER 0x04U
#define | OPTIONBYTE_DATA 0x08U
#define | OB_WRPSTATE_DISABLE 0x00U
#define | OB_WRPSTATE_ENABLE 0x01U
#define | OB_WRP_PAGES0TO3 0x00000001U
#define | OB_WRP_PAGES4TO7 0x00000002U
#define | OB_WRP_PAGES8TO11 0x00000004U
#define | OB_WRP_PAGES12TO15 0x00000008U
#define | OB_WRP_PAGES16TO19 0x00000010U
#define | OB_WRP_PAGES20TO23 0x00000020U
#define | OB_WRP_PAGES24TO27 0x00000040U
#define | OB_WRP_PAGES28TO31 0x00000080U
#define | OB_WRP_PAGES32TO35 0x00000100U
#define | OB_WRP_PAGES36TO39 0x00000200U
#define | OB_WRP_PAGES40TO43 0x00000400U
#define | OB_WRP_PAGES44TO47 0x00000800U
#define | OB_WRP_PAGES48TO51 0x00001000U
#define | OB_WRP_PAGES52TO55 0x00002000U
#define | OB_WRP_PAGES56TO59 0x00004000U
#define | OB_WRP_PAGES60TO63 0x00008000U
#define | OB_WRP_PAGES64TO67 0x00010000U
#define | OB_WRP_PAGES68TO71 0x00020000U
#define | OB_WRP_PAGES72TO75 0x00040000U
#define | OB_WRP_PAGES76TO79 0x00080000U
#define | OB_WRP_PAGES80TO83 0x00100000U
#define | OB_WRP_PAGES84TO87 0x00200000U
#define | OB_WRP_PAGES88TO91 0x00400000U
#define | OB_WRP_PAGES92TO95 0x00800000U
#define | OB_WRP_PAGES96TO99 0x01000000U
#define | OB_WRP_PAGES100TO103 0x02000000U
#define | OB_WRP_PAGES104TO107 0x04000000U
#define | OB_WRP_PAGES108TO111 0x08000000U
#define | OB_WRP_PAGES112TO115 0x10000000U
#define | OB_WRP_PAGES116TO119 0x20000000U
#define | OB_WRP_PAGES120TO123 0x40000000U
#define | OB_WRP_PAGES124TO127 0x80000000U
#define | OB_WRP_ALLPAGES 0xFFFFFFFFU
#define | OB_WRP_PAGES0TO31MASK 0x000000FFU
#define | OB_WRP_PAGES32TO63MASK 0x0000FF00U
#define | OB_WRP_PAGES64TO95MASK 0x00FF0000U
#define | OB_WRP_PAGES96TO127MASK 0xFF000000U
#define | OB_RDP_LEVEL_0 ((uint8_t)0xA5)
#define | OB_RDP_LEVEL_1 ((uint8_t)0x00)
#define | OB_IWDG_SW ((uint16_t)0x0001)
#define | OB_IWDG_HW ((uint16_t)0x0000)
#define | OB_STOP_NO_RST ((uint16_t)0x0002)
#define | OB_STOP_RST ((uint16_t)0x0000)
#define | OB_STDBY_NO_RST ((uint16_t)0x0004)
#define | OB_STDBY_RST ((uint16_t)0x0000)
#define | OB_DATA_ADDRESS_DATA0 0x1FFFF804U
#define | OB_DATA_ADDRESS_DATA1 0x1FFFF806U
#define | FLASH_FLAG_BSY FLASH_SR_BSY
#define | FLASH_FLAG_PGERR FLASH_SR_PGERR
#define | FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR
#define | FLASH_FLAG_EOP FLASH_SR_EOP
#define | FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR))
#define | FLASH_IT_EOP FLASH_CR_EOPIE
#define | FLASH_IT_ERR FLASH_CR_ERRIE
#define | __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
Enable the specified FLASH interrupt.
#define | __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
Disable the specified FLASH interrupt.
#define | __HAL_FLASH_GET_FLAG(__FLAG__)
Get the specified FLASH flag status.
#define | __HAL_FLASH_CLEAR_FLAG(__FLAG__)
Clear the specified FLASH flag.

Functions

HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBErase (void)
Erases the FLASH option bytes.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
uint32_t | HAL_FLASHEx_OBGetUserData (uint32_t DATAAdress)
Get the Option byte user data.

Detailed Description

Header file of Flash HAL Extended module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_flash_ex.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_gpio.h File Reference

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stm32f1xx_hal_gpio.h File Reference

Header file of GPIO HAL module. More...

#include "stm32f1xx_hal_def.h"
#include "stm32f1xx_hal_gpio_ex.h"

Go to the source code of this file.

Data Structures

struct | GPIO_InitTypeDef
GPIO Init structure definition. More...

Defines

#define | GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define | GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define | GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define | GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define | GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define | GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define | GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define | GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define | GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define | GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define | GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define | GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define | GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define | GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define | GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define | GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define | GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define | GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
#define | GPIO_MODE_INPUT 0x00000000U
#define | GPIO_MODE_OUTPUT_PP 0x00000001U
#define | GPIO_MODE_OUTPUT_OD 0x00000011U
#define | GPIO_MODE_AF_PP 0x00000002U
#define | GPIO_MODE_AF_OD 0x00000012U
#define | GPIO_MODE_AF_INPUT GPIO_MODE_INPUT
#define | GPIO_MODE_ANALOG 0x00000003U
#define | GPIO_MODE_IT_RISING 0x10110000U
#define | GPIO_MODE_IT_FALLING 0x10210000U
#define | GPIO_MODE_IT_RISING_FALLING 0x10310000U
#define | GPIO_MODE_EVT_RISING 0x10120000U
#define | GPIO_MODE_EVT_FALLING 0x10220000U
#define | GPIO_MODE_EVT_RISING_FALLING 0x10320000U
#define | GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1)
#define | GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0)
#define | GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0)
#define | GPIO_NOPULL 0x00000000U
#define | GPIO_PULLUP 0x00000001U
#define | GPIO_PULLDOWN 0x00000002U
#define | __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line flag is set or not.
#define | __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending flags.
#define | __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
Checks whether the specified EXTI line is asserted or not.
#define | __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
Clears the EXTI's line pending bits.
#define | __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
Generates a Software interrupt on selected EXTI line.
#define | IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define | IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
#define | IS_GPIO_MODE(MODE)
#define | IS_GPIO_SPEED(SPEED)
#define | IS_GPIO_PULL(PULL)

Enumerations

enum | GPIO_PinState { GPIO_PIN_RESET = 0U, GPIO_PIN_SET }
GPIO Bit SET and Bit RESET enumeration. More...

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
This function handles EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callbacks.

Detailed Description

Header file of GPIO HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_gpio.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_gpio_ex.h File Reference

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stm32f1xx_hal_gpio_ex.h File Reference

Header file of GPIO HAL Extension module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Defines

#define | AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0
#define | AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1
#define | AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2
#define | AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3
#define | AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4
#define | AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5
#define | AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6
#define | AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7
#define | AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8
#define | AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9
#define | AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10
#define | AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11
#define | AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12
#define | AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13
#define | AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14
#define | AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15
#define | IS_AFIO_EVENTOUT_PIN(__PIN__)
#define | AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA
#define | AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB
#define | AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC
#define | AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD
#define | AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE
#define | IS_AFIO_EVENTOUT_PORT(__PORT__)
#define | __HAL_AFIO_REMAP_SPI1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
#define | __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
#define | __HAL_AFIO_REMAP_I2C1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
Enable the remapping of I2C1 alternate function SCL and SDA.
#define | __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
Disable the remapping of I2C1 alternate function SCL and SDA.
#define | __HAL_AFIO_REMAP_USART1_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
Enable the remapping of USART1 alternate function TX and RX.
#define | __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
Disable the remapping of USART1 alternate function TX and RX.
#define | __HAL_AFIO_REMAP_USART2_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
#define | __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
#define | __HAL_AFIO_REMAP_USART3_ENABLE()
Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
#define | __HAL_AFIO_REMAP_USART3_PARTIAL()
Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
#define | __HAL_AFIO_REMAP_USART3_DISABLE()
Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
#define | __HAL_AFIO_REMAP_TIM1_ENABLE()
Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
#define | __HAL_AFIO_REMAP_TIM1_PARTIAL()
Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
#define | __HAL_AFIO_REMAP_TIM1_DISABLE()
Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
#define | __HAL_AFIO_REMAP_TIM2_ENABLE()
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
#define | __HAL_AFIO_REMAP_TIM2_PARTIAL_2()
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
#define | __HAL_AFIO_REMAP_TIM2_PARTIAL_1()
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
#define | __HAL_AFIO_REMAP_TIM2_DISABLE()
Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
#define | __HAL_AFIO_REMAP_TIM3_ENABLE()
Enable the remapping of TIM3 alternate function channels 1 to 4.
#define | __HAL_AFIO_REMAP_TIM3_PARTIAL()
Enable the remapping of TIM3 alternate function channels 1 to 4.
#define | __HAL_AFIO_REMAP_TIM3_DISABLE()
Disable the remapping of TIM3 alternate function channels 1 to 4.
#define | __HAL_AFIO_REMAP_TIM4_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
Enable the remapping of TIM4 alternate function channels 1 to 4.
#define | __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
Disable the remapping of TIM4 alternate function channels 1 to 4.
#define | __HAL_AFIO_REMAP_CAN1_1()
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
#define | __HAL_AFIO_REMAP_CAN1_2()
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
#define | __HAL_AFIO_REMAP_CAN1_3()
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
#define | __HAL_AFIO_REMAP_PD01_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
Enable the remapping of PD0 and PD1.
#define | __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
Disable the remapping of PD0 and PD1.
#define | __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
#define | __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
#define | __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
#define | __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
#define | __HAL_AFIO_REMAP_SWJ_ENABLE()
Enable the Serial wire JTAG configuration.
#define | __HAL_AFIO_REMAP_SWJ_NONJTRST()
Enable the Serial wire JTAG configuration.
#define | __HAL_AFIO_REMAP_SWJ_NOJTAG()
Enable the Serial wire JTAG configuration.
#define | __HAL_AFIO_REMAP_SWJ_DISABLE()
Disable the Serial wire JTAG configuration.
#define | GPIO_GET_INDEX(__GPIOx__)

Functions

void | HAL_GPIOEx_ConfigEventout (uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
void | HAL_GPIOEx_EnableEventout (void)
Enables the Event Output.
void | HAL_GPIOEx_DisableEventout (void)
Disables the Event Output.

Detailed Description

Header file of GPIO HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_gpio_ex.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_i2c.h File Reference

  • File List
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stm32f1xx_hal_i2c.h File Reference

Header file of I2C HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | I2C_InitTypeDef
I2C Configuration Structure definition. More...
struct | I2C_HandleTypeDef
I2C handle Structure definition. More...

Defines

#define | HAL_I2C_ERROR_NONE 0x00000000U
#define | HAL_I2C_ERROR_BERR 0x00000001U
#define | HAL_I2C_ERROR_ARLO 0x00000002U
#define | HAL_I2C_ERROR_AF 0x00000004U
#define | HAL_I2C_ERROR_OVR 0x00000008U
#define | HAL_I2C_ERROR_DMA 0x00000010U
#define | HAL_I2C_ERROR_TIMEOUT 0x00000020U
#define | I2C_DUTYCYCLE_2 0x00000000U
#define | I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
#define | I2C_ADDRESSINGMODE_7BIT 0x00004000U
#define | I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
#define | I2C_DUALADDRESS_DISABLE 0x00000000U
#define | I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
#define | I2C_GENERALCALL_DISABLE 0x00000000U
#define | I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
#define | I2C_NOSTRETCH_DISABLE 0x00000000U
#define | I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
#define | I2C_MEMADD_SIZE_8BIT 0x00000001U
#define | I2C_MEMADD_SIZE_16BIT 0x00000010U
#define | I2C_DIRECTION_RECEIVE 0x00000000U
#define | I2C_DIRECTION_TRANSMIT 0x00000001U
#define | I2C_FIRST_FRAME 0x00000001U
#define | I2C_NEXT_FRAME 0x00000002U
#define | I2C_FIRST_AND_LAST_FRAME 0x00000004U
#define | I2C_LAST_FRAME 0x00000008U
#define | I2C_IT_BUF I2C_CR2_ITBUFEN
#define | I2C_IT_EVT I2C_CR2_ITEVTEN
#define | I2C_IT_ERR I2C_CR2_ITERREN
#define | I2C_FLAG_SMBALERT 0x00018000U
#define | I2C_FLAG_TIMEOUT 0x00014000U
#define | I2C_FLAG_PECERR 0x00011000U
#define | I2C_FLAG_OVR 0x00010800U
#define | I2C_FLAG_AF 0x00010400U
#define | I2C_FLAG_ARLO 0x00010200U
#define | I2C_FLAG_BERR 0x00010100U
#define | I2C_FLAG_TXE 0x00010080U
#define | I2C_FLAG_RXNE 0x00010040U
#define | I2C_FLAG_STOPF 0x00010010U
#define | I2C_FLAG_ADD10 0x00010008U
#define | I2C_FLAG_BTF 0x00010004U
#define | I2C_FLAG_ADDR 0x00010002U
#define | I2C_FLAG_SB 0x00010001U
#define | I2C_FLAG_DUALF 0x00100080U
#define | I2C_FLAG_SMBHOST 0x00100040U
#define | I2C_FLAG_SMBDEFAULT 0x00100020U
#define | I2C_FLAG_GENCALL 0x00100010U
#define | I2C_FLAG_TRA 0x00100004U
#define | I2C_FLAG_BUSY 0x00100002U
#define | I2C_FLAG_MSL 0x00100001U
#define | __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
Reset I2C handle state.
#define | __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable or disable the specified I2C interrupts.
#define | __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
#define | __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks if the specified I2C interrupt source is enabled or disabled.
#define | __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)
Checks whether the specified I2C flag is set or not.
#define | __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
#define | __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)
Clears the I2C ADDR pending flag.
#define | __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)
Clears the I2C STOPF pending flag.
#define | __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
Enable the I2C peripheral.
#define | __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
Disable the I2C peripheral.
#define | I2C_FLAG_MASK 0x0000FFFFU
#define | I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
#define | I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
#define | I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
#define | I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
#define | I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)
#define | I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
#define | I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
#define | I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
#define | I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
#define | I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define | IS_I2C_DUTY_CYCLE(CYCLE)
#define | IS_I2C_ADDRESSING_MODE(ADDRESS)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_MEMADD_SIZE(SIZE)
#define | IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
#define | IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
#define | IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
#define | IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)

Enumerations

enum HAL_I2C_StateTypeDef {
HAL_I2C_STATE_RESET = 0x00U, HAL_I2C_STATE_READY = 0x20U, HAL_I2C_STATE_BUSY = 0x24U, HAL_I2C_STATE_BUSY_TX = 0x21U,
HAL_I2C_STATE_BUSY_RX = 0x22U, HAL_I2C_STATE_LISTEN = 0x28U, HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU,
HAL_I2C_STATE_ABORT = 0x60U, HAL_I2C_STATE_TIMEOUT = 0xA0U, HAL_I2C_STATE_ERROR = 0xE0U
}
HAL State structure definition. More...
enum | HAL_I2C_ModeTypeDef { HAL_I2C_MODE_NONE = 0x00U, HAL_I2C_MODE_MASTER = 0x10U, HAL_I2C_MODE_SLAVE = 0x20U, HAL_I2C_MODE_MEM = 0x40U }
HAL Mode structure definition. More...

Functions

HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitializes the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
I2C MSP Init.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
I2C MSP DeInit.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Return the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

Header file of I2C HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_i2c.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_irda.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f1xx_hal_irda.h File Reference

Header file of IRDA HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IRDA_InitTypeDef
IRDA Init Structure definition. More...
struct | IRDA_HandleTypeDef
IRDA handle Structure definition. More...

Defines

#define | HAL_IRDA_ERROR_NONE 0x00000000U
#define | HAL_IRDA_ERROR_PE 0x00000001U
#define | HAL_IRDA_ERROR_NE 0x00000002U
#define | HAL_IRDA_ERROR_FE 0x00000004U
#define | HAL_IRDA_ERROR_ORE 0x00000008U
#define | HAL_IRDA_ERROR_DMA 0x00000010U
#define | IRDA_WORDLENGTH_8B 0x00000000U
#define | IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | IRDA_PARITY_NONE 0x00000000U
#define | IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
#define | IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
#define | IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
#define | IRDA_POWERMODE_NORMAL 0x00000000U
#define | IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define | IRDA_FLAG_TC ((uint32_t)USART_SR_TC)
#define | IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define | IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define | IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define | IRDA_FLAG_NE ((uint32_t)USART_SR_NE)
#define | IRDA_FLAG_FE ((uint32_t)USART_SR_FE)
#define | IRDA_FLAG_PE ((uint32_t)USART_SR_PE)
#define | IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
#define | __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)
Reset IRDA handle gstate & RxState.
#define | __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flush the IRDA DR register.
#define | __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified IRDA flag is set or not.
#define | __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified IRDA pending flag.
#define | __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA PE pending flag.
#define | __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA FE pending flag.
#define | __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA NE pending flag.
#define | __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA ORE pending flag.
#define | __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
Clear the IRDA IDLE pending flag.
#define | __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified IRDA interrupt.
#define | __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified IRDA interrupt.
#define | __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__)
Check whether the specified IRDA interrupt has occurred or not.
#define | __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
Enable UART/USART associated to IRDA Handle.
#define | __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
Disable UART/USART associated to IRDA Handle.
#define | IRDA_IT_MASK 0x0000FFFFU
IRDA interruptions flag mask.
#define | IRDA_CR1_REG_INDEX 1U
#define | IRDA_CR2_REG_INDEX 2U
#define | IRDA_CR3_REG_INDEX 3U
#define | IS_IRDA_WORD_LENGTH(LENGTH)
#define | IS_IRDA_PARITY(PARITY)
#define | IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
#define | IS_IRDA_POWERMODE(MODE)
#define | IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
#define | IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
#define | IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | IRDA_BRR(_PCLK_, _BAUD_)

Enumerations

enum HAL_IRDA_StateTypeDef {
HAL_IRDA_STATE_RESET = 0x00U, HAL_IRDA_STATE_READY = 0x20U, HAL_IRDA_STATE_BUSY = 0x24U, HAL_IRDA_STATE_BUSY_TX = 0x21U,
HAL_IRDA_STATE_BUSY_RX = 0x22U, HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, HAL_IRDA_STATE_TIMEOUT = 0xA0U, HAL_IRDA_STATE_ERROR = 0xE0U
}
HAL IRDA State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitializes the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
IRDA MSP Init.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
IRDA MSP DeInit.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stops the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
This function handles IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer complete callbacks.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer complete callbacks.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callbacks.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callbacks.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callbacks.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Transmit Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort ReceiveComplete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Returns the IRDA state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA error code.

Detailed Description

Header file of IRDA HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_irda.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_iwdg.h File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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stm32f1xx_hal_iwdg.h File Reference

Header file of IWDG HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...

Defines

#define | IWDG_PRESCALER_4 0x00000000U
#define | IWDG_PRESCALER_8 IWDG_PR_PR_0
#define | IWDG_PRESCALER_16 IWDG_PR_PR_1
#define | IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_64 IWDG_PR_PR_2
#define | IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
Enable the IWDG peripheral.
#define | __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
Reload IWDG counter with value defined in the reload register (write access to IWDG_PR & IWDG_RLR registers disabled).
#define | IWDG_KEY_RELOAD 0x0000AAAAU
IWDG Key Register BitMask.
#define | IWDG_KEY_ENABLE 0x0000CCCCU
#define | IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U
#define | IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U
#define | IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
Enable write access to IWDG_PR and IWDG_RLR registers.
#define | IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
Disable write access to IWDG_PR and IWDG_RLR registers.
#define | IS_IWDG_PRESCALER(__PRESCALER__)
Check IWDG prescaler value.
#define | IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
Check IWDG reload value.

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

Header file of IWDG HAL module.

Author:
MCD Application Team
Version:
V1.5.0
Date:
06-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_iwdg.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pcd.h File Reference

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stm32f1xx_hal_pcd.h File Reference

Header file of PCD HAL module. More...

#include "stm32f1xx_ll_usb.h"
#include "stm32f1xx_hal_pcd_ex.h"

Go to the source code of this file.

Data Structures

struct | PCD_HandleTypeDef
PCD Handle Structure definition. More...

Defines

#define | PCD_SPEED_HIGH 0U /* Not Supported */
#define | PCD_SPEED_HIGH_IN_FULL 1U /* Not Supported */
#define | PCD_SPEED_FULL 2U
#define | PCD_PHY_EMBEDDED 2U
#define | USBD_FS_TRDT_VALUE 5U
#define | __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define | __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define | __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
#define | __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
#define | __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE()
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE()
#define | __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()
#define | USB_WAKEUP_EXTI_LINE 0x00040000U
#define | PCD_EP0MPS_64 DEP0CTL_MPS_64
#define | PCD_EP0MPS_32 DEP0CTL_MPS_32
#define | PCD_EP0MPS_16 DEP0CTL_MPS_16
#define | PCD_EP0MPS_08 DEP0CTL_MPS_8
#define | PCD_ENDP0 ((uint8_t)0)
#define | PCD_ENDP1 ((uint8_t)1)
#define | PCD_ENDP2 ((uint8_t)2)
#define | PCD_ENDP3 ((uint8_t)3)
#define | PCD_ENDP4 ((uint8_t)4)
#define | PCD_ENDP5 ((uint8_t)5)
#define | PCD_ENDP6 ((uint8_t)6)
#define | PCD_ENDP7 ((uint8_t)7)
#define | PCD_SNG_BUF 0U
#define | PCD_DBL_BUF 1U
#define | PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2U)= (uint16_t)(wRegValue))
#define | PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2U))
#define | USB_EP0StartXfer USB_EPStartXfer
#define | PCD_SET_EPTYPE(USBx, bEpNum, wType)
sets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
gets the type in the endpoint register(bits EP_TYPE[1:0])
#define | PCD_FreeUserBuffer(USBx, bEpNum, bDir)
free buffer used from the application realizing it to the line toggles bit SW_BUF in the double buffered endpoint register
#define | PCD_GET_DB_DIR(USBx, bEpNum)
gets direction of the double buffered endpoint
#define | PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState)
sets the status for tx transfer (bits STAT_TX[1:0]).
#define | PCD_SET_EP_RX_STATUS(USBx, bEpNum, wState)
sets the status for rx transfer (bits STAT_TX[1:0])
#define | PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx)
sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
#define | PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
gets the status for tx/rx transfer (bits STAT_TX[1:0] /STAT_RX[1:0])
#define | PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
#define | PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
sets directly the VALID tx/rx-status into the endpoint register
#define | PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
#define | PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum)
checks stall condition in an endpoint.
#define | PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum)
#define | PCD_SET_EP_KIND(USBx, bEpNum)
set & clear EP_KIND bit.
#define | PCD_CLEAR_EP_KIND(USBx, bEpNum)
#define | PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly STATUS_OUT bit in the endpoint register.
#define | PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
Sets/clears directly EP_KIND bit in the endpoint register.
#define | PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
#define | PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)
Clears bit CTR_RX / CTR_TX in the endpoint register.
#define | PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)
#define | PCD_RX_DTOG(USBx, bEpNum)
Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_TX_DTOG(USBx, bEpNum)
#define | PCD_CLEAR_RX_DTOG(USBx, bEpNum)
Clears DTOG_RX / DTOG_TX bit in the endpoint register.
#define | PCD_CLEAR_TX_DTOG(USBx, bEpNum)
#define | PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr)
Sets address in an endpoint register.
#define | PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
#define | PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U)*2U+ ((uint32_t)(USBx) + 0x400U)))
#define | PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+2U)*2U+ ((uint32_t)(USBx) + 0x400U)))
#define | PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+4U)*2U+ ((uint32_t)(USBx) + 0x400U)))
#define | PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+6U)*2U+ ((uint32_t)(USBx) + 0x400U)))
#define | PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount)
#define | PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
sets address of the tx/rx buffer.
#define | PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
#define | PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets address of the tx/rx buffer.
#define | PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_CALC_BLK32(dwReg, wCount, wNBlocks)
Sets counter of rx buffer with no.
#define | PCD_CALC_BLK2(dwReg, wCount, wNBlocks)
#define | PCD_SET_EP_CNT_RX_REG(dwReg, wCount)
#define | PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount)
#define | PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
sets counter for the tx/rx buffer.
#define | PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3FFU)
gets counter of the tx buffer.
#define | PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3FFU)
#define | PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
Sets buffer 0/1 address in a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
#define | PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr)
Sets addresses in a double buffer endpoint.
#define | PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
#define | PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)
Gets buffer 0/1 address of a double buffer endpoint.
#define | PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount)
#define | PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
Gets buffer 0/1 rx/tx counter for double buffering.
#define | PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
#define | IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE

Typedefs

typedef USB_TypeDef | PCD_TypeDef
typedef USB_CfgTypeDef | PCD_InitTypeDef
typedef USB_EPTypeDef | PCD_EPTypeDef

Enumerations

enum PCD_StateTypeDef {
HAL_PCD_STATE_RESET = 0x00U, HAL_PCD_STATE_READY = 0x01U, HAL_PCD_STATE_ERROR = 0x02U, HAL_PCD_STATE_BUSY = 0x03U,
HAL_PCD_STATE_TIMEOUT = 0x04U
}
PCD State structure definition. More...
enum | PCD_EP_DBUF_DIR { PCD_EP_DBUF_OUT, PCD_EP_DBUF_IN, PCD_EP_DBUF_ERR }
PCD double buffered endpoint direction. More...
enum | PCD_EP_BUF_NUM { PCD_EP_NOBUF, PCD_EP_BUF0, PCD_EP_BUF1 }
PCD endpoint buffer number. More...

Functions

HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data out stage callbacks.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callbacks.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callbacks.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callbacks.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callbacks.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callbacks.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callbacks.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callbacks.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callbacks.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callbacks.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD state.

Detailed Description

Header file of PCD HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_pcd.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pcd_ex.h File Reference

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Functions
stm32f1xx_hal_pcd_ex.h File Reference

Header file of Extended PCD HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
__weak void | HAL_PCDEx_SetConnectionState (PCD_HandleTypeDef *hpcd, uint8_t state)
Software Device Connection, this function is not required by USB OTG FS peripheral, it is used only by USB Device FS peripheral.

Detailed Description

Header file of Extended PCD HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_pcd_ex.h.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pwr.h File Reference

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stm32f1xx_hal_pwr.h File Reference

Header file of PWR HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | PWR_PVDTypeDef
PWR PVD configuration structure definition. More...

Defines

#define | PWR_EXTI_LINE_PVD ((uint32_t)0x00010000)
#define | PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
#define | PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
#define | PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
#define | PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
#define | PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
#define | PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
#define | PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
#define | PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
#define | PWR_PVD_MODE_NORMAL 0x00000000U
#define | PWR_PVD_MODE_IT_RISING 0x00010001U
#define | PWR_PVD_MODE_IT_FALLING 0x00010002U
#define | PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U
#define | PWR_PVD_MODE_EVENT_RISING 0x00020001U
#define | PWR_PVD_MODE_EVENT_FALLING 0x00020002U
#define | PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U
#define | PWR_WAKEUP_PIN1 PWR_CSR_EWUP
#define | PWR_MAINREGULATOR_ON 0x00000000U
#define | PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
#define | PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define | PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
#define | PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define | PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define | PWR_FLAG_WU PWR_CSR_WUF
#define | PWR_FLAG_SB PWR_CSR_SBF
#define | PWR_FLAG_PVDO PWR_CSR_PVDO
#define | __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
Check PWR flag is set or not.
#define | __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
Clear the PWR's pending flags.
#define | __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
Enable interrupt on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
Disable interrupt on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
Enable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
Disable event on PVD Exti Line 16.
#define | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
PVD EXTI line configuration: set falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
PVD EXTI line configuration: set rising edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Disable the PVD Extended Interrupt Rising Trigger.
#define | __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
PVD EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
Disable the PVD Extended Interrupt Rising & Falling Trigger.
#define | __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
Check whether the specified PVD EXTI interrupt flag is set or not.
#define | __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Clear the PVD EXTI flag.
#define | __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
Generate a Software interrupt on selected EXTI line.
#define | IS_PWR_PVD_LEVEL(LEVEL)
#define | IS_PWR_PVD_MODE(MODE)
#define | IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
#define | IS_PWR_REGULATOR(REGULATOR)
#define | IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define | IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))

Functions

void | HAL_PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers ).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinx)
Enables the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the WakeUp PINx functionality.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters Stop mode.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M3 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M3 SEVONPEND bit.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

Header file of PWR HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_pwr.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rcc.h File Reference

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Data Structures | Defines | Functions
stm32f1xx_hal_rcc.h File Reference

Header file of RCC HAL module. More...

#include "stm32f1xx_hal_def.h"
#include "stm32f1xx_hal_rcc_ex.h"

Go to the source code of this file.

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...

Defines

#define | RCC_PLLSOURCE_HSI_DIV2 0x00000000U
#define | RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC
#define | RCC_OSCILLATORTYPE_NONE 0x00000000U
#define | RCC_OSCILLATORTYPE_HSE 0x00000001U
#define | RCC_OSCILLATORTYPE_HSI 0x00000002U
#define | RCC_OSCILLATORTYPE_LSE 0x00000004U
#define | RCC_OSCILLATORTYPE_LSI 0x00000008U
#define | RCC_HSE_OFF 0x00000000U
#define | RCC_HSE_ON RCC_CR_HSEON
#define | RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
#define | RCC_LSE_OFF 0x00000000U
#define | RCC_LSE_ON RCC_BDCR_LSEON
#define | RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
#define | RCC_HSI_OFF 0x00000000U
#define | RCC_HSI_ON RCC_CR_HSION
#define | RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
#define | RCC_LSI_OFF 0x00000000U
#define | RCC_LSI_ON RCC_CSR_LSION
#define | RCC_PLL_NONE 0x00000000U
#define | RCC_PLL_OFF 0x00000001U
#define | RCC_PLL_ON 0x00000002U
#define | RCC_CLOCKTYPE_SYSCLK 0x00000001U
#define | RCC_CLOCKTYPE_HCLK 0x00000002U
#define | RCC_CLOCKTYPE_PCLK1 0x00000004U
#define | RCC_CLOCKTYPE_PCLK2 0x00000008U
#define | RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
#define | RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
#define | RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
#define | RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
#define | RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
#define | RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
#define | RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
#define | RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
#define | RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
#define | RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
#define | RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
#define | RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
#define | RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
#define | RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
#define | RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
#define | RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
#define | RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
#define | RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
#define | RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
#define | RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE
#define | RCC_MCO1 0x00000000U
#define | RCC_MCO RCC_MCO1
#define | RCC_MCODIV_1 0x00000000U
#define | RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)
#define | RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)
#define | RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)
#define | RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)
#define | RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)
#define | RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)
#define | RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos))
#define | RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos))
#define | RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos))
#define | RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos))
#define | RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))
#define | RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos))
#define | RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))
#define | RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos))
#define | RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos))
#define | RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos))
#define | RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos))
#define | __HAL_RCC_DMA1_CLK_ENABLE()
#define | __HAL_RCC_SRAM_CLK_ENABLE()
#define | __HAL_RCC_FLITF_CLK_ENABLE()
#define | __HAL_RCC_CRC_CLK_ENABLE()
#define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
#define | __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
#define | __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
#define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
#define | __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
#define | __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
#define | __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
#define | __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
#define | __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
#define | __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
#define | __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
#define | __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
#define | __HAL_RCC_TIM2_CLK_ENABLE()
#define | __HAL_RCC_TIM3_CLK_ENABLE()
#define | __HAL_RCC_WWDG_CLK_ENABLE()
#define | __HAL_RCC_USART2_CLK_ENABLE()
#define | __HAL_RCC_I2C1_CLK_ENABLE()
#define | __HAL_RCC_BKP_CLK_ENABLE()
#define | __HAL_RCC_PWR_CLK_ENABLE()
#define | __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define | __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
#define | __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
#define | __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define | __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define | __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
#define | __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
#define | __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
#define | __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
#define | __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
#define | __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
#define | __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define | __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define | __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
#define | __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define | __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define | __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define | __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
#define | __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
#define | __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define | __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
#define | __HAL_RCC_AFIO_CLK_ENABLE()
#define | __HAL_RCC_GPIOA_CLK_ENABLE()
#define | __HAL_RCC_GPIOB_CLK_ENABLE()
#define | __HAL_RCC_GPIOC_CLK_ENABLE()
#define | __HAL_RCC_GPIOD_CLK_ENABLE()
#define | __HAL_RCC_ADC1_CLK_ENABLE()
#define | __HAL_RCC_TIM1_CLK_ENABLE()
#define | __HAL_RCC_SPI1_CLK_ENABLE()
#define | __HAL_RCC_USART1_CLK_ENABLE()
#define | __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
#define | __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
#define | __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
#define | __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
#define | __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
#define | __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
#define | __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
#define | __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
#define | __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
#define | __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
#define | __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
#define | __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
#define | __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
#define | __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
#define | __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
#define | __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define | __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define | __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
#define | __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define | __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define | __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define | __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define | __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
#define | __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
#define | __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
#define | __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
#define | __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
#define | __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
#define | __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define | __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define | __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
#define | __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
#define | __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
#define | __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define | __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
#define | __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
#define | __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
#define | __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
#define | __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
#define | __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
#define | __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
#define | __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
#define | __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
#define | __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
#define | __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
#define | __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
#define | __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
#define | __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
#define | __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
#define | __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
#define | __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
#define | __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Macros to enable or disable the Internal High Speed oscillator (HSI).
#define | __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
#define | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
#define | __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Macro to enable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Macro to disable the Internal Low Speed oscillator (LSI).
#define | __HAL_RCC_HSE_CONFIG(__STATE__)
Macro to configure the External High Speed oscillator (HSE).
#define | __HAL_RCC_LSE_CONFIG(__STATE__)
Macro to configure the External Low Speed oscillator (LSE).
#define | __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Macro to enable the main PLL.
#define | __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
Macro to disable the main PLL.
#define | __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
Macro to configure the main PLL clock source and multiplication factors.
#define | __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Get oscillator clock selected as PLL input clock.
#define | __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Macro to configure the system clock source.
#define | __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Macro to get the clock source used as system clock.
#define | __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
Macro to configure the MCO clock.
#define | __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
Macro to configure the RTC clock (RTCCLK).
#define | __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
Macro to get the RTC clock source.
#define | __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Macro to enable the the RTC clock.
#define | __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
Macro to disable the the RTC clock.
#define | __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Macro to force the Backup domain reset.
#define | __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Macros to release the Backup domain reset.
#define | __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Enable RCC interrupt.
#define | __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
Disable RCC interrupt.
#define | __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Clear the RCC's interrupt pending bits.
#define | __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Check the RCC's interrupt has occurred or not.
#define | __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
Set RMVF bit to clear the reset flags.
#define | __HAL_RCC_GET_FLAG(__FLAG__)
Check RCC flag is set or not.
#define | RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define | CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define | HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define | RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define | RCC_CR_OFFSET 0x00U
#define | RCC_CFGR_OFFSET 0x04U
#define | RCC_CIR_OFFSET 0x08U
#define | RCC_BDCR_OFFSET 0x20U
#define | RCC_CSR_OFFSET 0x24U
#define | RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
#define | RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
#define | RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
#define | RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
#define | RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
#define | RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
#define | RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
#define | RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
#define | RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
#define | RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
#define | RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
#define | RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
#define | RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
#define | RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
#define | RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
#define | RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
#define | RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
#define | RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
#define | RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
#define | RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
#define | RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
#define | RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
#define | RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
#define | RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
#define | RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
#define | RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
#define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
#define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
#define | CR_REG_INDEX ((uint8_t)1)
#define | BDCR_REG_INDEX ((uint8_t)2)
#define | CSR_REG_INDEX ((uint8_t)3)
#define | RCC_FLAG_MASK ((uint8_t)0x1F)
#define | __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
#define | __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
#define | __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
#define | __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
#define | IS_RCC_PLLSOURCE(__SOURCE__)
#define | IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)
#define | IS_RCC_HSE(__HSE__)
#define | IS_RCC_LSE(__LSE__)
#define | IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define | IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
#define | IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define | IS_RCC_PLL(__PLL__)
#define | IS_RCC_CLOCKTYPE(CLK)
#define | IS_RCC_SYSCLKSOURCE(__SOURCE__)
#define | IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__)
#define | IS_RCC_HCLK(__HCLK__)
#define | IS_RCC_PCLK(__PCLK__)
#define | IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
#define | IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
#define | IS_RCC_RTCCLKSOURCE(__SOURCE__)

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO pin.
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

Header file of RCC HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_rcc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rcc_ex.h File Reference

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Data Structures | Defines | Functions
stm32f1xx_hal_rcc_ex.h File Reference

Header file of RCC HAL Extension module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...

Defines

#define | CR_REG_INDEX ((uint8_t)1)
#define | IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
#define | IS_RCC_PLL_MUL(__MUL__)
#define | IS_RCC_MCO1SOURCE(__SOURCE__)
#define | IS_RCC_ADCPLLCLK_DIV(__ADCCLK__)
#define | IS_RCC_PERIPHCLOCK(__SELECTION__)
#define | IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
#define | RCC_PERIPHCLK_RTC 0x00000001U
#define | RCC_PERIPHCLK_ADC 0x00000002U
#define | RCC_PERIPHCLK_USB 0x00000010U
#define | RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
#define | RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
#define | RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
#define | RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
#define | RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
#define | RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U
#define | RCC_HSE_PREDIV_DIV1 0x00000000U
#define | RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
#define | RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
#define | RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
#define | RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
#define | RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
#define | RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
#define | RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
#define | RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
#define | RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
#define | RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
#define | RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
#define | RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
#define | RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
#define | RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
#define | RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
#define | RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
#define | RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
#define | RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
#define | RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
#define | RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
#define | RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
#define | __HAL_RCC_CAN1_CLK_ENABLE()
#define | __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
#define | __HAL_RCC_TIM4_CLK_ENABLE()
#define | __HAL_RCC_SPI2_CLK_ENABLE()
#define | __HAL_RCC_USART3_CLK_ENABLE()
#define | __HAL_RCC_I2C2_CLK_ENABLE()
#define | __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
#define | __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
#define | __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define | __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
#define | __HAL_RCC_USB_CLK_ENABLE()
#define | __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
#define | __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
#define | __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
#define | __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
#define | __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
#define | __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
#define | __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
#define | __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#define | __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#define | __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
#define | __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
#define | __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
#define | __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
#define | __HAL_RCC_ADC2_CLK_ENABLE()
#define | __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
#define | __HAL_RCC_GPIOE_CLK_ENABLE()
#define | __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
#define | __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
#define | __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
#define | __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
#define | __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
#define | __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
#define | __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
#define | __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
#define | __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#define | __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
#define | __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
#define | __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
#define | __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
#define | __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
#define | __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
#define | __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
#define | __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
#define | __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
Macro to get prediv1 factor for PLL.
#define | __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
Macro to configure the USB clock.
#define | __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
Macro to get the USB clock (USBCLK).
#define | __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
Macro to configure the ADCx clock (x=1 to 3 depending on devices).
#define | __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the PeriphClkInit according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Returns the peripheral clock frequency.

Detailed Description

Header file of RCC HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_rcc_ex.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rtc.h File Reference

  • File List
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Data Structures | Defines | Enumerations | Functions
stm32f1xx_hal_rtc.h File Reference

Header file of RTC HAL module. More...

#include "stm32f1xx_hal_def.h"
#include "stm32f1xx_hal_rtc_ex.h"

Go to the source code of this file.

Data Structures

struct | RTC_TimeTypeDef
RTC Time structure definition. More...
struct | RTC_AlarmTypeDef
RTC Alarm structure definition. More...
struct | RTC_InitTypeDef
RTC Configuration Structure definition. More...
struct | RTC_DateTypeDef
RTC Date structure definition. More...
struct | RTC_HandleTypeDef
Time Handle Structure definition. More...

Defines

#define | IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND))
#define | IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define | IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define | IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
#define | IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define | IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
#define | IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
#define | IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define | IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
#define | IS_RTC_CALIB_OUTPUT(__OUTPUT__)
#define | RTC_TIMEOUT_VALUE 1000U
#define | RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17)
#define | RTC_AUTO_1_SECOND 0xFFFFFFFFU
#define | RTC_FORMAT_BIN 0x000000000U
#define | RTC_FORMAT_BCD 0x000000001U
#define | RTC_MONTH_JANUARY ((uint8_t)0x01)
#define | RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define | RTC_MONTH_MARCH ((uint8_t)0x03)
#define | RTC_MONTH_APRIL ((uint8_t)0x04)
#define | RTC_MONTH_MAY ((uint8_t)0x05)
#define | RTC_MONTH_JUNE ((uint8_t)0x06)
#define | RTC_MONTH_JULY ((uint8_t)0x07)
#define | RTC_MONTH_AUGUST ((uint8_t)0x08)
#define | RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define | RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define | RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define | RTC_MONTH_DECEMBER ((uint8_t)0x12)
#define | RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define | RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define | RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define | RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define | RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define | RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define | RTC_WEEKDAY_SUNDAY ((uint8_t)0x00)
#define | RTC_ALARM_A 0U
#define | RTC_OUTPUTSOURCE_NONE 0x00000000U
#define | RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO
#define | RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE
#define | RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE)
#define | RTC_IT_OW RTC_CRH_OWIE
#define | RTC_IT_ALRA RTC_CRH_ALRIE
#define | RTC_IT_SEC RTC_CRH_SECIE
#define | RTC_IT_TAMP1 BKP_CSR_TPIE
#define | RTC_FLAG_RTOFF RTC_CRL_RTOFF
#define | RTC_FLAG_RSF RTC_CRL_RSF
#define | RTC_FLAG_OW RTC_CRL_OWF
#define | RTC_FLAG_ALRAF RTC_CRL_ALRF
#define | RTC_FLAG_SEC RTC_CRL_SECF
#define | RTC_FLAG_TAMP1F BKP_CSR_TEF
#define | __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
Reset RTC handle state.
#define | __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
Disable the write protection for RTC registers.
#define | __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
Enable the write protection for RTC registers.
#define | __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Enable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Disable the RTC Alarm interrupt.
#define | __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
Check whether the specified RTC Alarm interrupt has been enabled or not.
#define | __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Alarm's flag status.
#define | __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET)
Check whether the specified RTC Alarm interrupt has occurred or not.
#define | __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
Clear the RTC Alarm's pending flags.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
Enable interrupt on ALARM Exti Line 17.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
Disable interrupt on ALARM Exti Line 17.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
Enable event on ALARM Exti Line 17.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
Disable event on ALARM Exti Line 17.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
ALARM EXTI line configuration: set falling edge trigger.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
Disable the ALARM Extended Interrupt Falling Trigger.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
ALARM EXTI line configuration: set rising edge trigger.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
Disable the ALARM Extended Interrupt Rising Trigger.
#define | __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()
ALARM EXTI line configuration: set rising & falling edge trigger.
#define | __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()
Disable the ALARM Extended Interrupt Rising & Falling Trigger.
#define | __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT))
Check whether the specified ALARM EXTI interrupt flag is set or not.
#define | __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT))
Clear the ALARM EXTI flag.
#define | __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT)
Generate a Software interrupt on selected EXTI line.

Enumerations

enum HAL_RTCStateTypeDef {
HAL_RTC_STATE_RESET = 0x00U, HAL_RTC_STATE_READY = 0x01U, HAL_RTC_STATE_BUSY = 0x02U, HAL_RTC_STATE_TIMEOUT = 0x03U,
HAL_RTC_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initializes the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initializes the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Sets RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Gets RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Sets RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Gets RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactive the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Gets the RTC Alarm value and masks.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Alarm interrupt request.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmA Polling request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Returns the RTC state.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) are synchronized with RTC APB clock.

Detailed Description

Header file of RTC HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_rtc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rtc_ex.h File Reference

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Data Structures | Defines | Functions
stm32f1xx_hal_rtc_ex.h File Reference

Header file of RTC HAL Extension module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | RTC_TamperTypeDef
RTC Tamper structure definition. More...

Defines

#define | HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler
#define | IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1)
#define | IS_RTC_TAMPER_TRIGGER(__TRIGGER__)
#define | IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER)
#define | IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU)
#define | RTC_TAMPER_1 BKP_CR_TPE
#define | RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL
#define | RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U
#define | RTC_BKP_DR1 0x00000001U
#define | RTC_BKP_DR2 0x00000002U
#define | RTC_BKP_DR3 0x00000003U
#define | RTC_BKP_DR4 0x00000004U
#define | RTC_BKP_DR5 0x00000005U
#define | RTC_BKP_DR6 0x00000006U
#define | RTC_BKP_DR7 0x00000007U
#define | RTC_BKP_DR8 0x00000008U
#define | RTC_BKP_DR9 0x00000009U
#define | RTC_BKP_DR10 0x0000000AU
#define | __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__))
Enable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(BKP->CSR, (__INTERRUPT__))
Disable the RTC Tamper interrupt.
#define | __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET)
Check whether the specified RTC Tamper interrupt has been enabled or not.
#define | __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET)
Get the selected RTC Tamper's flag status.
#define | __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI)
Clear the RTC Tamper's pending flags.
#define | __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Enable the RTC Second interrupt.
#define | __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Disable the RTC Second interrupt.
#define | __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
Check whether the specified RTC Second interrupt has occurred or not.
#define | __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Second's flag status.
#define | __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
Clear the RTC Second's pending flags.
#define | __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Enable the RTC Overflow interrupt.
#define | __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
Disable the RTC Overflow interrupt.
#define | __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET)
Check whether the specified RTC Overflow interrupt has occurred or not.
#define | __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
Get the selected RTC Overflow's flag status.
#define | __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
Clear the RTC Overflow's pending flags.

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivates Tamper.
void | HAL_RTCEx_TamperIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Tamper interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetSecond_IT (RTC_HandleTypeDef *hrtc)
Sets Interrupt for second.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateSecond (RTC_HandleTypeDef *hrtc)
Deactivates Second.
void | HAL_RTCEx_RTCIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles second interrupt request.
__weak void | HAL_RTCEx_RTCEventCallback (RTC_HandleTypeDef *hrtc)
Second event callback.
__weak void | HAL_RTCEx_RTCEventErrorCallback (RTC_HandleTypeDef *hrtc)
Second event error callback.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
Sets the Smooth calibration parameters.

Detailed Description

Header file of RTC HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_rtc_ex.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_smartcard.h File Reference

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stm32f1xx_hal_smartcard.h File Reference

Header file of SMARTCARD HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SMARTCARD_InitTypeDef
SMARTCARD Init Structure definition. More...
struct | SMARTCARD_HandleTypeDef
SMARTCARD handle Structure definition. More...

Defines

#define | HAL_SMARTCARD_ERROR_NONE 0x00000000U
#define | HAL_SMARTCARD_ERROR_PE 0x00000001U
#define | HAL_SMARTCARD_ERROR_NE 0x00000002U
#define | HAL_SMARTCARD_ERROR_FE 0x00000004U
#define | HAL_SMARTCARD_ERROR_ORE 0x00000008U
#define | HAL_SMARTCARD_ERROR_DMA 0x00000010U
#define | SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
#define | SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
#define | SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | SMARTCARD_POLARITY_LOW 0x00000000U
#define | SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | SMARTCARD_PHASE_1EDGE 0x00000000U
#define | SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define | SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | SMARTCARD_NACK_DISABLE 0x00000000U
#define | SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
#define | SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
#define | SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U
#define | SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU
#define | SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU
#define | SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define | SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)
#define | SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define | SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define | SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define | SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE)
#define | SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE)
#define | SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE)
#define | SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
#define | __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)
Reset SMARTCARD handle gstate & RxState.
#define | __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flush the Smartcard DR register.
#define | __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified Smartcard flag is set or not.
#define | __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clear the specified Smartcard pending flags.
#define | __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD PE pending flag.
#define | __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD FE pending flag.
#define | __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD NE pending flag.
#define | __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD ORE pending flag.
#define | __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
Clear the SMARTCARD IDLE pending flag.
#define | __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified SmartCard interrupt.
#define | __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
Checks whether the specified SmartCard interrupt has occurred or not.
#define | __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable the USART associated to the SMARTCARD Handle.
#define | __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
Macros to enable the SmartCard DMA request.
#define | __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
Macros to disable the SmartCard DMA request.
#define | SMARTCARD_IT_MASK 0x0000FFFFU
SMARTCARD interruptions flag mask.
#define | SMARTCARD_CR1_REG_INDEX 1U
#define | SMARTCARD_CR3_REG_INDEX 3U
#define | IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
#define | IS_SMARTCARD_STOPBITS(STOPBITS)
#define | IS_SMARTCARD_PARITY(PARITY)
#define | IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
#define | IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
#define | IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
#define | IS_SMARTCARD_LASTBIT(LASTBIT)
#define | IS_SMARTCARD_NACK_STATE(NACK)
#define | IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
#define | SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
#define | SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | SMARTCARD_BRR(_PCLK_, _BAUD_)

Enumerations

enum HAL_SMARTCARD_StateTypeDef {
HAL_SMARTCARD_STATE_RESET = 0x00U, HAL_SMARTCARD_STATE_READY = 0x20U, HAL_SMARTCARD_STATE_BUSY = 0x24U, HAL_SMARTCARD_STATE_BUSY_TX = 0x21U,
HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, HAL_SMARTCARD_STATE_ERROR = 0xE0U
}
HAL SMARTCARD State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsc)
Initializes the SmartCard mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_ReInit (SMARTCARD_HandleTypeDef *hsc)
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsc)
DeInitializes the USART SmartCard peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP Init.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP DeInit.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsc)
This function handles SMARTCARD interrupt request.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Tx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Rx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD error callbacks.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD Abort Transmit Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD Abort ReceiveComplete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsc)
return the SMARTCARD state
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsc)
Return the SMARTCARD error code.

Detailed Description

Header file of SMARTCARD HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_smartcard.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_spi.h File Reference

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  • STM32F1xx_HAL_Driver
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Data Structures | Defines | Typedefs | Enumerations | Functions
stm32f1xx_hal_spi.h File Reference

Header file of SPI HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | SPI_InitTypeDef
SPI Configuration Structure definition. More...
struct | __SPI_HandleTypeDef
SPI handle Structure definition. More...

Defines

#define | HAL_SPI_ERROR_NONE 0x00000000U
#define | HAL_SPI_ERROR_MODF 0x00000001U
#define | HAL_SPI_ERROR_CRC 0x00000002U
#define | HAL_SPI_ERROR_OVR 0x00000004U
#define | HAL_SPI_ERROR_FRE 0x00000008U
#define | HAL_SPI_ERROR_DMA 0x00000010U
#define | HAL_SPI_ERROR_FLAG 0x00000020U
#define | SPI_MODE_SLAVE 0x00000000U
#define | SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | SPI_DIRECTION_2LINES 0x00000000U
#define | SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define | SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
#define | SPI_DATASIZE_8BIT 0x00000000U
#define | SPI_DATASIZE_16BIT SPI_CR1_DFF
#define | SPI_POLARITY_LOW 0x00000000U
#define | SPI_POLARITY_HIGH SPI_CR1_CPOL
#define | SPI_PHASE_1EDGE 0x00000000U
#define | SPI_PHASE_2EDGE SPI_CR1_CPHA
#define | SPI_NSS_SOFT SPI_CR1_SSM
#define | SPI_NSS_HARD_INPUT 0x00000000U
#define | SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))
#define | SPI_BAUDRATEPRESCALER_2 0x00000000U
#define | SPI_BAUDRATEPRESCALER_4 SPI_CR1_BR_0
#define | SPI_BAUDRATEPRESCALER_8 SPI_CR1_BR_1
#define | SPI_BAUDRATEPRESCALER_16 (uint32_t)(SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_32 SPI_CR1_BR_2
#define | SPI_BAUDRATEPRESCALER_64 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | SPI_BAUDRATEPRESCALER_128 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | SPI_BAUDRATEPRESCALER_256 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | SPI_FIRSTBIT_MSB 0x00000000U
#define | SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
#define | SPI_TIMODE_DISABLE 0x00000000U
#define | SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
#define | SPI_IT_TXE SPI_CR2_TXEIE
#define | SPI_IT_RXNE SPI_CR2_RXNEIE
#define | SPI_IT_ERR SPI_CR2_ERRIE
#define | SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define | SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define | SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define | SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define | SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define | SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define | __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
Reset SPI handle state.
#define | __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
Enable the specified SPI interrupts.
#define | __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
Disable the specified SPI interrupts.
#define | __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Check whether the specified SPI interrupt source is enabled or not.
#define | __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
Check whether the specified SPI flag is set or not.
#define | __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
Clear the SPI CRCERR pending flag.
#define | __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)
Clear the SPI MODF pending flag.
#define | __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)
Clear the SPI OVR pending flag.
#define | __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
Enable the SPI peripheral.
#define | __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
Disable the SPI peripheral.
#define | SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */
#define | SPI_VALID_CRC_ERROR 1U /* CRC error is true */
#define | SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
Set the SPI transmit-only mode.
#define | SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
Set the SPI receive-only mode.
#define | SPI_RESET_CRC(__HANDLE__)
Reset the CRC calculation of the SPI.
#define | IS_SPI_MODE(MODE)
#define | IS_SPI_DIRECTION(MODE)
#define | IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define | IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE)
#define | IS_SPI_DATASIZE(DATASIZE)
#define | IS_SPI_CPOL(CPOL)
#define | IS_SPI_CPHA(CPHA)
#define | IS_SPI_NSS(NSS)
#define | IS_SPI_BAUDRATE_PRESCALER(PRESCALER)
#define | IS_SPI_FIRST_BIT(BIT)
#define | IS_SPI_CRC_CALCULATION(CALCULATION)
#define | IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))

Typedefs

typedef struct __SPI_HandleTypeDef | SPI_HandleTypeDef
SPI handle Structure definition.

Enumerations

enum HAL_SPI_StateTypeDef {
HAL_SPI_STATE_RESET = 0x00U, HAL_SPI_STATE_READY = 0x01U, HAL_SPI_STATE_BUSY = 0x02U, HAL_SPI_STATE_BUSY_TX = 0x03U,
HAL_SPI_STATE_BUSY_RX = 0x04U, HAL_SPI_STATE_BUSY_TX_RX = 0x05U, HAL_SPI_STATE_ERROR = 0x06U
}
HAL SPI State structure definition. More...

Functions

__weak HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.
uint8_t | SPI_ISCRCErrorValid (SPI_HandleTypeDef *hspi)
Checks if encountered CRC error could be corresponding to wrongly detected errors according to SPI instance, Device type, and revision ID.

Detailed Description

Header file of SPI HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_spi.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_tim.h File Reference

  • File List
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  • Drivers
  • STM32F1xx_HAL_Driver
  • Inc
Data Structures | Defines | Enumerations | Functions
stm32f1xx_hal_tim.h File Reference

Header file of TIM HAL module. More...

#include "stm32f1xx_hal_def.h"
#include "stm32f1xx_hal_tim_ex.h"

Go to the source code of this file.

Data Structures

struct | TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition. More...
struct | TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition. More...
struct | TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition. More...
struct | TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition. More...
struct | TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition. More...
struct | TIM_ClockConfigTypeDef
TIM Clock Configuration Handle Structure definition. More...
struct | TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition. More...
struct | TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition. More...
struct | TIM_HandleTypeDef
TIM Time Base Handle Structure definition. More...

Defines

#define | TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
#define | TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P)
#define | TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
#define | TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP)
#define | TIM_ETRPOLARITY_NONINVERTED 0x00000000U
#define | TIM_ETRPRESCALER_DIV1 0x00000000U
#define | TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0)
#define | TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1)
#define | TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS)
#define | TIM_COUNTERMODE_UP 0x00000000U
#define | TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define | TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
#define | TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
#define | TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define | TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
#define | TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U
#define | TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE)
#define | TIM_OCMODE_TIMING 0x00000000U
#define | TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
#define | TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
#define | TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
#define | TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
#define | TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
#define | TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
#define | TIM_OCFAST_DISABLE 0x00000000U
#define | TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
#define | TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define | TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
#define | TIM_OCPOLARITY_HIGH 0x00000000U
#define | TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
#define | TIM_OCNPOLARITY_HIGH 0x00000000U
#define | TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
#define | TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
#define | TIM_OCIDLESTATE_RESET 0x00000000U
#define | TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
#define | TIM_OCNIDLESTATE_RESET 0x00000000U
#define | TIM_CHANNEL_1 0x00000000U
#define | TIM_CHANNEL_2 0x00000004U
#define | TIM_CHANNEL_3 0x00000008U
#define | TIM_CHANNEL_4 0x0000000CU
#define | TIM_CHANNEL_ALL 0x00000018U
#define | TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0)
#define | TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1)
#define | TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S)
#define | TIM_ICPSC_DIV1 0x00000000U
#define | TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0)
#define | TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1)
#define | TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC)
#define | TIM_OPMODE_SINGLE (TIM_CR1_OPM)
#define | TIM_OPMODE_REPETITIVE 0x00000000U
#define | TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
#define | TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
#define | TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | TIM_IT_UPDATE (TIM_DIER_UIE)
#define | TIM_IT_CC1 (TIM_DIER_CC1IE)
#define | TIM_IT_CC2 (TIM_DIER_CC2IE)
#define | TIM_IT_CC3 (TIM_DIER_CC3IE)
#define | TIM_IT_CC4 (TIM_DIER_CC4IE)
#define | TIM_IT_COM (TIM_DIER_COMIE)
#define | TIM_IT_TRIGGER (TIM_DIER_TIE)
#define | TIM_IT_BREAK (TIM_DIER_BIE)
#define | TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
#define | TIM_COMMUTATION_SOFTWARE 0x00000000U
#define | TIM_DMA_UPDATE (TIM_DIER_UDE)
#define | TIM_DMA_CC1 (TIM_DIER_CC1DE)
#define | TIM_DMA_CC2 (TIM_DIER_CC2DE)
#define | TIM_DMA_CC3 (TIM_DIER_CC3DE)
#define | TIM_DMA_CC4 (TIM_DIER_CC4DE)
#define | TIM_DMA_COM (TIM_DIER_COMDE)
#define | TIM_DMA_TRIGGER (TIM_DIER_TDE)
#define | TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
#define | TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
#define | TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
#define | TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
#define | TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
#define | TIM_EVENTSOURCE_COM TIM_EGR_COMG
#define | TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
#define | TIM_EVENTSOURCE_BREAK TIM_EGR_BG
#define | TIM_FLAG_UPDATE (TIM_SR_UIF)
#define | TIM_FLAG_CC1 (TIM_SR_CC1IF)
#define | TIM_FLAG_CC2 (TIM_SR_CC2IF)
#define | TIM_FLAG_CC3 (TIM_SR_CC3IF)
#define | TIM_FLAG_CC4 (TIM_SR_CC4IF)
#define | TIM_FLAG_COM (TIM_SR_COMIF)
#define | TIM_FLAG_TRIGGER (TIM_SR_TIF)
#define | TIM_FLAG_BREAK (TIM_SR_BIF)
#define | TIM_FLAG_CC1OF (TIM_SR_CC1OF)
#define | TIM_FLAG_CC2OF (TIM_SR_CC2OF)
#define | TIM_FLAG_CC3OF (TIM_SR_CC3OF)
#define | TIM_FLAG_CC4OF (TIM_SR_CC4OF)
#define | TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define | TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define | TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
#define | TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define | TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define | TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
#define | TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_CLEARINPUTSOURCE_ETR 0x00000001U
#define | TIM_CLEARINPUTSOURCE_NONE 0x00000000U
#define | TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
#define | TIM_OSSR_DISABLE 0x00000000U
#define | TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
#define | TIM_OSSI_DISABLE 0x00000000U
#define | TIM_LOCKLEVEL_OFF 0x00000000U
#define | TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define | TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define | TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
#define | TIM_BREAK_ENABLE (TIM_BDTR_BKE)
#define | TIM_BREAK_DISABLE 0x00000000U
#define | TIM_BREAKPOLARITY_LOW 0x00000000U
#define | TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
#define | TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
#define | TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | TIM_TRGO_RESET 0x00000000U
#define | TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define | TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define | TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define | TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define | TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define | TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define | TIM_SLAVEMODE_DISABLE 0x00000000U
#define | TIM_SLAVEMODE_RESET 0x00000004U
#define | TIM_SLAVEMODE_GATED 0x00000005U
#define | TIM_SLAVEMODE_TRIGGER 0x00000006U
#define | TIM_SLAVEMODE_EXTERNAL1 0x00000007U
#define | TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
#define | TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
#define | TIM_TS_ITR0 0x00000000U
#define | TIM_TS_ITR1 0x00000010U
#define | TIM_TS_ITR2 0x00000020U
#define | TIM_TS_ITR3 0x00000030U
#define | TIM_TS_TI1F_ED 0x00000040U
#define | TIM_TS_TI1FP1 0x00000050U
#define | TIM_TS_TI2FP2 0x00000060U
#define | TIM_TS_ETRF 0x00000070U
#define | TIM_TS_NONE 0x0000FFFFU
#define | TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
#define | TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
#define | TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define | TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
#define | TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
#define | TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
#define | TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
#define | TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
#define | TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
#define | TIM_TI1SELECTION_CH1 0x00000000U
#define | TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
#define | TIM_DMABASE_CR1 0x00000000U
#define | TIM_DMABASE_CR2 0x00000001U
#define | TIM_DMABASE_SMCR 0x00000002U
#define | TIM_DMABASE_DIER 0x00000003U
#define | TIM_DMABASE_SR 0x00000004U
#define | TIM_DMABASE_EGR 0x00000005U
#define | TIM_DMABASE_CCMR1 0x00000006U
#define | TIM_DMABASE_CCMR2 0x00000007U
#define | TIM_DMABASE_CCER 0x00000008U
#define | TIM_DMABASE_CNT 0x00000009U
#define | TIM_DMABASE_PSC 0x0000000AU
#define | TIM_DMABASE_ARR 0x0000000BU
#define | TIM_DMABASE_RCR 0x0000000CU
#define | TIM_DMABASE_CCR1 0x0000000DU
#define | TIM_DMABASE_CCR2 0x0000000EU
#define | TIM_DMABASE_CCR3 0x0000000FU
#define | TIM_DMABASE_CCR4 0x00000010U
#define | TIM_DMABASE_BDTR 0x00000011U
#define | TIM_DMABASE_DCR 0x00000012U
#define | TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
#define | TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
#define | TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
#define | TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
#define | TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
#define | TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
#define | TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
#define | TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
#define | TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
#define | TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
#define | TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
#define | TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
#define | TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
#define | TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
#define | TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
#define | TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
#define | TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
#define | TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
#define | TIM_DMA_ID_UPDATE ((uint16_t)0x0)
#define | TIM_DMA_ID_CC1 ((uint16_t)0x1)
#define | TIM_DMA_ID_CC2 ((uint16_t)0x2)
#define | TIM_DMA_ID_CC3 ((uint16_t)0x3)
#define | TIM_DMA_ID_CC4 ((uint16_t)0x4)
#define | TIM_DMA_ID_COMMUTATION ((uint16_t)0x5)
#define | TIM_DMA_ID_TRIGGER ((uint16_t)0x6)
#define | TIM_CCx_ENABLE 0x00000001U
#define | TIM_CCx_DISABLE 0x00000000U
#define | TIM_CCxN_ENABLE 0x00000004U
#define | TIM_CCxN_DISABLE 0x00000000U
#define | TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define | TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
#define | IS_TIM_COUNTER_MODE(MODE)
#define | IS_TIM_CLOCKDIVISION_DIV(DIV)
#define | IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
#define | IS_TIM_PWM_MODE(MODE)
#define | IS_TIM_OC_MODE(MODE)
#define | IS_TIM_FAST_STATE(STATE)
#define | IS_TIM_OC_POLARITY(POLARITY)
#define | IS_TIM_OCN_POLARITY(POLARITY)
#define | IS_TIM_OCIDLE_STATE(STATE)
#define | IS_TIM_OCNIDLE_STATE(STATE)
#define | IS_TIM_CHANNELS(CHANNEL)
#define | IS_TIM_OPM_CHANNELS(CHANNEL)
#define | IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL)
#define | IS_TIM_IC_POLARITY(POLARITY)
#define | IS_TIM_IC_SELECTION(SELECTION)
#define | IS_TIM_IC_PRESCALER(PRESCALER)
#define | IS_TIM_OPM_MODE(MODE)
#define | IS_TIM_ENCODER_MODE(MODE)
#define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define | IS_TIM_CLOCKSOURCE(CLOCK)
#define | IS_TIM_CLOCKPOLARITY(POLARITY)
#define | IS_TIM_CLOCKPRESCALER(PRESCALER)
#define | IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_CLEARINPUT_SOURCE(SOURCE)
#define | IS_TIM_CLEARINPUT_POLARITY(POLARITY)
#define | IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)
#define | IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_OSSR_STATE(STATE)
#define | IS_TIM_OSSI_STATE(STATE)
#define | IS_TIM_LOCK_LEVEL(LEVEL)
#define | IS_TIM_BREAK_STATE(STATE)
#define | IS_TIM_BREAK_POLARITY(POLARITY)
#define | IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE)
#define | IS_TIM_TRGO_SOURCE(SOURCE)
#define | IS_TIM_SLAVE_MODE(MODE)
#define | IS_TIM_MSM_STATE(STATE)
#define | IS_TIM_TRIGGER_SELECTION(SELECTION)
#define | IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION)
#define | IS_TIM_TRIGGERPOLARITY(POLARITY)
#define | IS_TIM_TRIGGERPRESCALER(PRESCALER)
#define | IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | IS_TIM_TI1SELECTION(TI1SELECTION)
#define | IS_TIM_DMA_BASE(BASE)
#define | IS_TIM_DMA_LENGTH(LENGTH)
#define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define | TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
Set TIM IC prescaler.
#define | TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
Reset TIM IC prescaler.
#define | TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Set TIM IC polarity.
#define | TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
Reset TIM IC polarity.
#define | __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
Reset TIM handle state.
#define | __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
Enable the TIM peripheral.
#define | __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
Enable the TIM main Output.
#define | __HAL_TIM_DISABLE(__HANDLE__)
Disable the TIM peripheral.
#define | __HAL_TIM_MOE_DISABLE(__HANDLE__)
Disable the TIM main Output.
#define | __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
Disable the TIM main Output.
#define | __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
Enables the specified TIM interrupt.
#define | __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
Disables the specified TIM interrupt.
#define | __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
Enables the specified DMA request.
#define | __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
Disables the specified DMA request.
#define | __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
Checks whether the specified TIM interrupt flag is set or not.
#define | __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified TIM interrupt flag.
#define | __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Checks whether the specified TIM interrupt has occurred or not.
#define | __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
Clear the TIM interrupt pending bits.
#define | __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
Indicates whether or not the TIM Counter is used as downcounter.
#define | __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
Sets the TIM active prescaler register value on update event.
#define | __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
Sets the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
#define | __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
Gets the TIM Capture Compare Register value on runtime.
#define | __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
Sets the TIM Counter Register value on runtime.
#define | __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
Gets the TIM Counter Register value on runtime.
#define | __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__)
Sets the TIM Autoreload Register value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
Gets the TIM Autoreload Register value on runtime.
#define | __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__)
Sets the TIM Clock Division value on runtime without calling another time any Init function.
#define | __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
Gets the TIM Clock Division value on runtime.
#define | __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__)
Sets the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
#define | __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)
Gets the TIM Input Capture prescaler on runtime.
#define | __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
Set the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
#define | __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
Sets the TIM Capture x input polarity on runtime.

Enumerations

enum HAL_TIM_StateTypeDef {
HAL_TIM_STATE_RESET = 0x00U, HAL_TIM_STATE_READY = 0x01U, HAL_TIM_STATE_BUSY = 0x02U, HAL_TIM_STATE_TIMEOUT = 0x03U,
HAL_TIM_STATE_ERROR = 0x04U
}
HAL State structures definition. More...
enum HAL_TIM_ActiveChannel {
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
}
HAL Active channel structures definition. More...

Functions

void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 2 configuration.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.

Detailed Description

Header file of TIM HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_tim.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_tim_ex.h File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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Data Structures | Defines | Functions
stm32f1xx_hal_tim_ex.h File Reference

Header file of TIM HAL Extension module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break and Dead time configuration Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...

Defines

#define | IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
#define | __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Sets the TIM Output compare preload.
#define | __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)
Resets the TIM Output compare preload.

Functions

HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.

Detailed Description

Header file of TIM HAL Extension module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_tim_ex.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_uart.h File Reference

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Data Structures | Defines | Enumerations | Functions
stm32f1xx_hal_uart.h File Reference

Header file of UART HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | UART_InitTypeDef
UART Init Structure definition. More...
struct | UART_HandleTypeDef
UART handle Structure definition. More...

Defines

#define | HAL_UART_ERROR_NONE 0x00000000U
#define | HAL_UART_ERROR_PE 0x00000001U
#define | HAL_UART_ERROR_NE 0x00000002U
#define | HAL_UART_ERROR_FE 0x00000004U
#define | HAL_UART_ERROR_ORE 0x00000008U
#define | HAL_UART_ERROR_DMA 0x00000010U
#define | UART_WORDLENGTH_8B 0x00000000U
#define | UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | UART_STOPBITS_1 0x00000000U
#define | UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | UART_PARITY_NONE 0x00000000U
#define | UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | UART_HWCONTROL_NONE 0x00000000U
#define | UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define | UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define | UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
#define | UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | UART_STATE_DISABLE 0x00000000U
#define | UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
#define | UART_OVERSAMPLING_16 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define | UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
#define | UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define | UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
#define | UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
#define | UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
#define | UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define | UART_FLAG_TC ((uint32_t)USART_SR_TC)
#define | UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define | UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define | UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define | UART_FLAG_NE ((uint32_t)USART_SR_NE)
#define | UART_FLAG_FE ((uint32_t)USART_SR_FE)
#define | UART_FLAG_PE ((uint32_t)USART_SR_PE)
#define | UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
#define | __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)
Reset UART handle gstate & RxState.
#define | __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
Flushs the UART DR register.
#define | __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified UART flag is set or not.
#define | __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified UART pending flag.
#define | __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clears the UART PE pending flag.
#define | __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clears the UART FE pending flag.
#define | __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clears the UART NE pending flag.
#define | __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clears the UART ORE pending flag.
#define | __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
Clears the UART IDLE pending flag.
#define | __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified UART interrupt.
#define | __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified UART interrupt.
#define | __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified UART interrupt has occurred or not.
#define | __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)
Enable CTS flow control This macro allows to enable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)
Disable CTS flow control This macro allows to disable CTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)
Enable RTS flow control This macro allows to enable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)
Disable RTS flow control This macro allows to disable RTS hardware flow control for a given UART instance, without need to call HAL_UART_Init() function.
#define | __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
Enable UART.
#define | __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
Disable UART.
#define | UART_IT_MASK 0x0000FFFFU
UART interruptions flag mask.
#define | UART_CR1_REG_INDEX 1U
#define | UART_CR2_REG_INDEX 2U
#define | UART_CR3_REG_INDEX 3U
#define | IS_UART_WORD_LENGTH(LENGTH)
#define | IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
#define | IS_UART_STOPBITS(STOPBITS)
#define | IS_UART_PARITY(PARITY)
#define | IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)
#define | IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
#define | IS_UART_STATE(STATE)
#define | IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
#define | IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH)
#define | IS_UART_WAKEUPMETHOD(WAKEUP)
#define | IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
#define | IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
#define | UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define | UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
#define | UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | UART_BRR_SAMPLING16(_PCLK_, _BAUD_)
#define | UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define | UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
#define | UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
#define | UART_BRR_SAMPLING8(_PCLK_, _BAUD_)

Enumerations

enum HAL_UART_StateTypeDef {
HAL_UART_STATE_RESET = 0x00U, HAL_UART_STATE_READY = 0x20U, HAL_UART_STATE_BUSY = 0x24U, HAL_UART_STATE_BUSY_TX = 0x21U,
HAL_UART_STATE_BUSY_RX = 0x22U, HAL_UART_STATE_BUSY_TX_RX = 0x23U, HAL_UART_STATE_TIMEOUT = 0xA0U, HAL_UART_STATE_ERROR = 0xE0U
}
HAL UART State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initializes the Multi-Processor mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitializes the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
UART MSP Init.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
UART MSP DeInit.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stops the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
This function handles UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callbacks.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callbacks.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callbacks.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callbacks.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callbacks.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmits break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enters the UART in mute mode.
HAL_StatusTypeDef | HAL_MultiProcessor_ExitMuteMode (UART_HandleTypeDef *huart)
Exits the UART mute mode: wake up software.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enables the UART transmitter and disables the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enables the UART receiver and disables the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Returns the UART state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART error code.

Detailed Description

Header file of UART HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_uart.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_usart.h File Reference

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stm32f1xx_hal_usart.h File Reference

Header file of USART HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | USART_InitTypeDef
USART Init Structure definition. More...
struct | USART_HandleTypeDef
USART handle Structure definition. More...

Defines

#define | HAL_USART_ERROR_NONE 0x00000000U
#define | HAL_USART_ERROR_PE 0x00000001U
#define | HAL_USART_ERROR_NE 0x00000002U
#define | HAL_USART_ERROR_FE 0x00000004U
#define | HAL_USART_ERROR_ORE 0x00000008U
#define | HAL_USART_ERROR_DMA 0x00000010U
#define | USART_WORDLENGTH_8B 0x00000000U
#define | USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
#define | USART_STOPBITS_1 0x00000000U
#define | USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define | USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define | USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
#define | USART_PARITY_NONE 0x00000000U
#define | USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define | USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
#define | USART_MODE_RX ((uint32_t)USART_CR1_RE)
#define | USART_MODE_TX ((uint32_t)USART_CR1_TE)
#define | USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
#define | USART_CLOCK_DISABLE 0x00000000U
#define | USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
#define | USART_POLARITY_LOW 0x00000000U
#define | USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
#define | USART_PHASE_1EDGE 0x00000000U
#define | USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
#define | USART_LASTBIT_DISABLE 0x00000000U
#define | USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
#define | USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
#define | USART_NACK_DISABLE 0x00000000U
#define | USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define | USART_FLAG_TC ((uint32_t)USART_SR_TC)
#define | USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define | USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define | USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define | USART_FLAG_NE ((uint32_t)USART_SR_NE)
#define | USART_FLAG_FE ((uint32_t)USART_SR_FE)
#define | USART_FLAG_PE ((uint32_t)USART_SR_PE)
#define | USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define | USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define | USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define | USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define | USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define | USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define | USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define | USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
#define | __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
Reset USART handle state.
#define | __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Checks whether the specified USART flag is set or not.
#define | __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
Clears the specified USART pending flags.
#define | __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART PE pending flag.
#define | __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART FE pending flag.
#define | __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART NE pending flag.
#define | __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART ORE pending flag.
#define | __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
Clear the USART IDLE pending flag.
#define | __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)
Enable the specified USART interrupts.
#define | __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)
Disable the specified USART interrupts.
#define | __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__)
Checks whether the specified USART interrupt has occurred or not.
#define | __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
Enable USART.
#define | __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
Disable USART.
#define | USART_IT_MASK 0x0000FFFFU
USART interruptions flag mask.
#define | USART_CR1_REG_INDEX 1U
#define | USART_CR2_REG_INDEX 2U
#define | USART_CR3_REG_INDEX 3U
#define | IS_USART_NACK_STATE(NACK)
#define | IS_USART_LASTBIT(LASTBIT)
#define | IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
#define | IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
#define | IS_USART_CLOCK(CLOCK)
#define | IS_USART_WORD_LENGTH(LENGTH)
#define | IS_USART_STOPBITS(STOPBITS)
#define | IS_USART_PARITY(PARITY)
#define | IS_USART_MODE(MODE) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U))
#define | IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
#define | USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define | USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
#define | USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define | USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))

Enumerations

enum HAL_USART_StateTypeDef {
HAL_USART_STATE_RESET = 0x00U, HAL_USART_STATE_READY = 0x01U, HAL_USART_STATE_BUSY = 0x02U, HAL_USART_STATE_BUSY_TX = 0x12U,
HAL_USART_STATE_BUSY_RX = 0x22U, HAL_USART_STATE_BUSY_TX_RX = 0x32U, HAL_USART_STATE_TIMEOUT = 0x03U, HAL_USART_STATE_ERROR = 0x04U
}
HAL State structures definition. More...

Functions

HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitializes the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
USART MSP Init.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
USART MSP DeInit.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Simplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Full-Duplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stops the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfer (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
This function handles USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callbacks.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callbacks.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callbacks.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callbacks.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callbacks.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Returns the USART state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

Header file of USART HAL module.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_usart.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_wwdg.h File Reference

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stm32f1xx_hal_wwdg.h File Reference

Header file of WWDG HAL module. More...

#include "stm32f1xx_hal_def.h"

Go to the source code of this file.

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...

Defines

#define | WWDG_IT_EWI WWDG_CFR_EWI
#define | WWDG_FLAG_EWIF WWDG_SR_EWIF
#define | WWDG_PRESCALER_1 0x00000000U
#define | WWDG_PRESCALER_2 WWDG_CFR_WDGTB0
#define | WWDG_PRESCALER_4 WWDG_CFR_WDGTB1
#define | WWDG_PRESCALER_8 WWDG_CFR_WDGTB
#define | WWDG_EWI_DISABLE 0x00000000U
#define | WWDG_EWI_ENABLE WWDG_CFR_EWI
#define | IS_WWDG_PRESCALER(__PRESCALER__)
#define | IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define | IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define | IS_WWDG_EWI_MODE(__MODE__)
#define | __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
Enables the WWDG peripheral.
#define | __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
Enables the WWDG early wakeup interrupt.
#define | __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
Checks whether the selected WWDG interrupt has occurred or not.
#define | __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
Clear the WWDG's interrupt pending bits bits to clear the selected interrupt pending bits.
#define | __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
Check whether the specified WWDG flag is set or not.
#define | __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
Clears the WWDG's pending flags.
#define | __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
Checks if the specified WWDG interrupt source is enabled or disabled.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

Header file of WWDG HAL module.

Author:
MCD Application Team
Version:
V1.5.0
Date:
06-May-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_wwdg.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_adc.h File Reference

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  • STM32F1xx_HAL_Driver
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Data Structures | Defines | Functions
stm32f1xx_ll_adc.h File Reference

Header file of ADC LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...

Defines

#define | ADC_SQR1_REGOFFSET 0x00000000U
#define | ADC_SQR2_REGOFFSET 0x00000100U
#define | ADC_SQR3_REGOFFSET 0x00000200U
#define | ADC_SQR4_REGOFFSET 0x00000300U
#define | ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define | ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
#define | ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
#define | ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
#define | ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
#define | ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
#define | ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
#define | ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
#define | ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
#define | ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
#define | ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
#define | ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
#define | ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
#define | ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
#define | ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
#define | ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
#define | ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
#define | ADC_JDR1_REGOFFSET 0x00000000U
#define | ADC_JDR2_REGOFFSET 0x00000100U
#define | ADC_JDR3_REGOFFSET 0x00000200U
#define | ADC_JDR4_REGOFFSET 0x00000300U
#define | ADC_JOFR1_REGOFFSET 0x00000000U
#define | ADC_JOFR2_REGOFFSET 0x00001000U
#define | ADC_JOFR3_REGOFFSET 0x00002000U
#define | ADC_JOFR4_REGOFFSET 0x00003000U
#define | ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define | ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
#define | ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define | ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
#define | ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
#define | ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
#define | ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
#define | ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
#define | ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define | ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
#define | ADC_SMPR1_REGOFFSET 0x00000000U
#define | ADC_SMPR2_REGOFFSET 0x02000000U
#define | ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define | ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
#define | ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
#define | ADC_CHANNEL_0_NUMBER 0x00000000U
#define | ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
#define | ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
#define | ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
#define | ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
#define | ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
#define | ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
#define | ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
#define | ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
#define | ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
#define | ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
#define | ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
#define | ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
#define | ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
#define | ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
#define | ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
#define | ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
#define | ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
#define | ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
#define | ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
#define | ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
#define | ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
#define | ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
#define | ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
#define | ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
#define | ADC_AWD_CR1_REGOFFSET 0x00000000U
#define | ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
#define | ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
#define | ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
#define | ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
#define | ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
#define | ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
#define | __ADC_MASK_SHIFT(__BITS__, __MASK__) (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
Driver macro reserved for internal use: isolate bits with the selected mask and shift them to the register LSB (shift mask on register position bit 0).
#define | __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
Driver macro reserved for internal use: set a pointer to a register from a register basis from which an offset is applied.
#define | LL_ADC_FLAG_STRT ADC_SR_STRT
#define | LL_ADC_FLAG_EOS ADC_SR_EOC
#define | LL_ADC_FLAG_JSTRT ADC_SR_JSTRT
#define | LL_ADC_FLAG_JEOS ADC_SR_JEOC
#define | LL_ADC_FLAG_AWD1 ADC_SR_AWD
#define | LL_ADC_FLAG_EOS_MST ADC_SR_EOC
#define | LL_ADC_FLAG_EOS_SLV ADC_SR_EOC
#define | LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC
#define | LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC
#define | LL_ADC_FLAG_AWD1_MST ADC_SR_AWD
#define | LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD
#define | LL_ADC_IT_EOS ADC_CR1_EOCIE
#define | LL_ADC_IT_JEOS ADC_CR1_JEOCIE
#define | LL_ADC_IT_AWD1 ADC_CR1_AWDIE
#define | LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#define | LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
#define | LL_ADC_PATH_INTERNAL_NONE 0x00000000U
#define | LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE)
#define | LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE)
#define | LL_ADC_RESOLUTION_12B 0x00000000U
#define | LL_ADC_DATA_ALIGN_RIGHT 0x00000000U
#define | LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN)
#define | LL_ADC_SEQ_SCAN_DISABLE 0x00000000U
#define | LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN)
#define | LL_ADC_GROUP_REGULAR 0x00000001U
#define | LL_ADC_GROUP_INJECTED 0x00000002U
#define | LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U
#define | LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP)
#define | LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP)
#define | LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP)
#define | LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP)
#define | LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP)
#define | LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP)
#define | LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP)
#define | LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP)
#define | LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP)
#define | LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP)
#define | LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP)
#define | LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP)
#define | LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP)
#define | LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP)
#define | LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP)
#define | LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP)
#define | LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP)
#define | LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP)
#define | LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
#define | LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1)
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U
#define | LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2)
#define | LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)
#define | LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)
#define | LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG
#define | LL_ADC_REG_CONV_SINGLE 0x00000000U
#define | LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT)
#define | LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U
#define | LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA)
#define | LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
#define | LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
#define | LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U
#define | LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
#define | LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
#define | LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
#define | LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U
#define | LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1)
#define | LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2)
#define | LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)
#define | LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)
#define | LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG
#define | LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U
#define | LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO)
#define | LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
#define | LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
#define | LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U
#define | LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN)
#define | LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U)
#define | LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U)
#define | LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U)
#define | LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U)
#define | LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U
#define | LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1)
#define | LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2)
#define | LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)
#define | LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)
#define | LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)
#define | LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
#define | LL_ADC_AWD_DISABLE 0x00000000U
#define | LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN )
#define | LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN )
#define | LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN )
#define | LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
#define | LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET)
#define | LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET)
#define | LL_ADC_MULTI_INDEPENDENT 0x00000000U
#define | LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )
#define | LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)
#define | LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 )
#define | LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)
#define | LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0)
#define | LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 )
#define | LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)
#define | LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 )
#define | LL_ADC_MULTI_MASTER ( ADC_DR_DATA)
#define | LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA )
#define | LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA)
#define | LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U)
#define | LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U)
#define | LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U)
#define | LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in ADC register.
#define | LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in ADC register.
#define | __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
Helper macro to get ADC channel number in decimal format from literals LL_ADC_CHANNEL_x.
#define | __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)
Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x from number in decimal format.
#define | __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
Helper macro to determine whether the selected channel corresponds to literal definitions of driver.
#define | __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
Helper macro to convert a channel defined from parameter definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), to its equivalent parameter definition of a ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
#define | __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)
Helper macro to determine whether the internal channel selected is available on the ADC instance selected.
#define | __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)
Helper macro to define ADC analog watchdog parameter: define a single channel to monitor with analog watchdog from sequencer channel and groups definition.
#define | __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) ((__AWD_THRESHOLD__) << (0U))
Helper macro to set the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) (__AWD_THRESHOLD_12_BITS__)
Helper macro to get the value of ADC analog watchdog threshold high or low in function of ADC resolution, when ADC resolution is different of 12 bits.
#define | __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA)
Helper macro to get the ADC multimode conversion data of ADC master or ADC slave from raw value with both ADC conversion data concatenated.
#define | __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
Helper macro to select the ADC common instance to which is belonging the selected ADC instance.
#define | __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)
Helper macro to check if all ADC instances sharing the same ADC common instance are disabled.
#define | __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) (0xFFFU)
Helper macro to define the ADC conversion data full-scale digital value corresponding to the selected ADC resolution.
#define | __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__, __ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the voltage (unit: mVolt) corresponding to a ADC conversion data (unit: digital value).
#define | __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__, __TEMPSENSOR_TYP_CALX_V__, __TEMPSENSOR_CALX_TEMP__, __VREFANALOG_VOLTAGE__, __TEMPSENSOR_ADC_DATA__, __ADC_RESOLUTION__)
Helper macro to calculate the temperature (unit: degree Celsius) from ADC conversion data of internal temperature sensor.

Functions

__STATIC_INLINE uint32_t | LL_ADC_DMA_GetRegAddr (ADC_TypeDef *ADCx, uint32_t Register)
Function to help to configure DMA transfer from ADC: retrieve the ADC register address from ADC instance and a list of ADC registers intended to be used (most commonly) with DMA transfer.
__STATIC_INLINE void | LL_ADC_SetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
Set parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE uint32_t | LL_ADC_GetCommonPathInternalCh (ADC_Common_TypeDef *ADCxy_COMMON)
Get parameter common to several ADC: measurement path to internal channels (VrefInt, temperature sensor, ...).
__STATIC_INLINE void | LL_ADC_SetDataAlignment (ADC_TypeDef *ADCx, uint32_t DataAlignment)
Set ADC conversion data alignment.
__STATIC_INLINE uint32_t | LL_ADC_GetDataAlignment (ADC_TypeDef *ADCx)
Get ADC conversion data alignment.
__STATIC_INLINE void | LL_ADC_SetSequencersScanMode (ADC_TypeDef *ADCx, uint32_t ScanMode)
Set ADC sequencers scan mode, for all ADC groups (group regular, group injected).
__STATIC_INLINE uint32_t | LL_ADC_GetSequencersScanMode (ADC_TypeDef *ADCx)
Get ADC sequencers scan mode, for all ADC groups (group regular, group injected).
__STATIC_INLINE void | LL_ADC_REG_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_REG_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group regular conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group regular sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group regular sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_REG_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular sequence: channel on the selected scan sequence rank.
__STATIC_INLINE void | LL_ADC_REG_SetContinuousMode (ADC_TypeDef *ADCx, uint32_t Continuous)
Set ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetContinuousMode (ADC_TypeDef *ADCx)
Get ADC continuous conversion mode on ADC group regular.
__STATIC_INLINE void | LL_ADC_REG_SetDMATransfer (ADC_TypeDef *ADCx, uint32_t DMATransfer)
Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE uint32_t | LL_ADC_REG_GetDMATransfer (ADC_TypeDef *ADCx)
Get ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
__STATIC_INLINE void | LL_ADC_INJ_SetTriggerSource (ADC_TypeDef *ADCx, uint32_t TriggerSource)
Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTriggerSource (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
__STATIC_INLINE uint32_t | LL_ADC_INJ_IsTriggerSourceSWStart (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger source internal (SW start) or external.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerLength (ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
Set ADC group injected sequencer length and scan direction.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerLength (ADC_TypeDef *ADCx)
Get ADC group injected sequencer length and scan direction.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerDiscont (ADC_TypeDef *ADCx, uint32_t SeqDiscont)
Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerDiscont (ADC_TypeDef *ADCx)
Get ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
__STATIC_INLINE void | LL_ADC_INJ_SetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
Set ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetSequencerRanks (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected sequence: channel on the selected sequence rank.
__STATIC_INLINE void | LL_ADC_INJ_SetTrigAuto (ADC_TypeDef *ADCx, uint32_t TrigAuto)
Set ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetTrigAuto (ADC_TypeDef *ADCx)
Get ADC group injected conversion trigger: independent or from ADC group regular.
__STATIC_INLINE void | LL_ADC_INJ_SetOffset (ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
Set ADC group injected offset.
__STATIC_INLINE uint32_t | LL_ADC_INJ_GetOffset (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected offset.
__STATIC_INLINE void | LL_ADC_SetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
Set sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE uint32_t | LL_ADC_GetChannelSamplingTime (ADC_TypeDef *ADCx, uint32_t Channel)
Get sampling time of the selected ADC channel Unit: ADC clock cycles.
__STATIC_INLINE void | LL_ADC_SetAnalogWDMonitChannels (ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
Set ADC analog watchdog monitored channels: a single channel or all channels, on ADC groups regular and-or injected.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDMonitChannels (ADC_TypeDef *ADCx)
Get ADC analog watchdog monitored channel.
__STATIC_INLINE void | LL_ADC_SetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
Set ADC analog watchdog threshold value of threshold high or low.
__STATIC_INLINE uint32_t | LL_ADC_GetAnalogWDThresholds (ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
Get ADC analog watchdog threshold value of threshold high or threshold low.
__STATIC_INLINE void | LL_ADC_SetMultimode (ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE uint32_t | LL_ADC_GetMultimode (ADC_Common_TypeDef *ADCxy_COMMON)
Get ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
__STATIC_INLINE void | LL_ADC_Enable (ADC_TypeDef *ADCx)
Enable the selected ADC instance.
__STATIC_INLINE void | LL_ADC_Disable (ADC_TypeDef *ADCx)
Disable the selected ADC instance.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabled (ADC_TypeDef *ADCx)
Get the selected ADC instance enable state.
__STATIC_INLINE void | LL_ADC_StartCalibration (ADC_TypeDef *ADCx)
Start ADC calibration in the mode single-ended or differential (for devices with differential mode available).
__STATIC_INLINE uint32_t | LL_ADC_IsCalibrationOnGoing (ADC_TypeDef *ADCx)
Get ADC calibration state.
__STATIC_INLINE void | LL_ADC_REG_StartConversionSWStart (ADC_TypeDef *ADCx)
Start ADC group regular conversion.
__STATIC_INLINE void | LL_ADC_REG_StartConversionExtTrig (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Start ADC group regular conversion from external trigger.
__STATIC_INLINE void | LL_ADC_REG_StopConversionExtTrig (ADC_TypeDef *ADCx)
Stop ADC group regular conversion from external trigger.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadConversionData32 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_REG_ReadConversionData12 (ADC_TypeDef *ADCx)
Get ADC group regular conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint32_t | LL_ADC_REG_ReadMultiConversionData32 (ADC_TypeDef *ADCx, uint32_t ConversionData)
Get ADC multimode conversion data of ADC master, ADC slave or raw data with ADC master and slave concatenated.
__STATIC_INLINE void | LL_ADC_INJ_StartConversionSWStart (ADC_TypeDef *ADCx)
Start ADC group injected conversion.
__STATIC_INLINE void | LL_ADC_INJ_StartConversionExtTrig (ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
Start ADC group injected conversion from external trigger.
__STATIC_INLINE void | LL_ADC_INJ_StopConversionExtTrig (ADC_TypeDef *ADCx)
Stop ADC group injected conversion from external trigger.
__STATIC_INLINE uint32_t | LL_ADC_INJ_ReadConversionData32 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group regular conversion data, range fit for all ADC configurations: all ADC resolutions and all oversampling increased data width (for devices with feature oversampling).
__STATIC_INLINE uint16_t | LL_ADC_INJ_ReadConversionData12 (ADC_TypeDef *ADCx, uint32_t Rank)
Get ADC group injected conversion data, range fit for ADC resolution 12 bits.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_EOS (ADC_TypeDef *ADCx)
Get flag ADC group regular end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_JEOS (ADC_TypeDef *ADCx)
Get flag ADC group injected end of sequence conversions.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_AWD1 (ADC_TypeDef *ADCx)
Get flag ADC analog watchdog 1 flag.
__STATIC_INLINE void | LL_ADC_ClearFlag_EOS (ADC_TypeDef *ADCx)
Clear flag ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_JEOS (ADC_TypeDef *ADCx)
Clear flag ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_ClearFlag_AWD1 (ADC_TypeDef *ADCx)
Clear flag ADC analog watchdog 1.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_EOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_JEOS (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_MST_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode ADC analog watchdog 1 of the ADC master.
__STATIC_INLINE uint32_t | LL_ADC_IsActiveFlag_SLV_AWD1 (ADC_Common_TypeDef *ADCxy_COMMON)
Get flag multimode analog watchdog 1 of the ADC slave.
__STATIC_INLINE void | LL_ADC_EnableIT_EOS (ADC_TypeDef *ADCx)
Enable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_JEOS (ADC_TypeDef *ADCx)
Enable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_EnableIT_AWD1 (ADC_TypeDef *ADCx)
Enable interruption ADC analog watchdog 1.
__STATIC_INLINE void | LL_ADC_DisableIT_EOS (ADC_TypeDef *ADCx)
Disable interruption ADC group regular end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_JEOS (ADC_TypeDef *ADCx)
Disable interruption ADC group injected end of sequence conversions.
__STATIC_INLINE void | LL_ADC_DisableIT_AWD1 (ADC_TypeDef *ADCx)
Disable interruption ADC analog watchdog 1.
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_EOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group regular end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_JEOS (ADC_TypeDef *ADCx)
Get state of interruption ADC group injected end of sequence conversions (0: interrupt disabled, 1: interrupt enabled).
__STATIC_INLINE uint32_t | LL_ADC_IsEnabledIT_AWD1 (ADC_TypeDef *ADCx)
Get state of interruption ADC analog watchdog 1 (0: interrupt disabled, 1: interrupt enabled).
ErrorStatus | LL_ADC_CommonDeInit (ADC_Common_TypeDef *ADCxy_COMMON)
De-initialize registers of all ADC instances belonging to the same ADC common instance to their default reset values.
ErrorStatus | LL_ADC_CommonInit (ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Initialize some features of ADC common parameters (all ADC instances belonging to the same ADC common instance) and multimode (for devices with several ADC instances available).
void | LL_ADC_CommonStructInit (LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
Set each LL_ADC_CommonInitTypeDef field to default value.
ErrorStatus | LL_ADC_DeInit (ADC_TypeDef *ADCx)
De-initialize registers of the selected ADC instance to their default reset values.
ErrorStatus | LL_ADC_Init (ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
Initialize some features of ADC instance.
void | LL_ADC_StructInit (LL_ADC_InitTypeDef *ADC_InitStruct)
Set each LL_ADC_InitTypeDef field to default value.
ErrorStatus | LL_ADC_REG_Init (ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Initialize some features of ADC group regular.
void | LL_ADC_REG_StructInit (LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
Set each LL_ADC_REG_InitTypeDef field to default value.
ErrorStatus | LL_ADC_INJ_Init (ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Initialize some features of ADC group injected.
void | LL_ADC_INJ_StructInit (LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
Set each LL_ADC_INJ_InitTypeDef field to default value.

Detailed Description

Header file of ADC LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_adc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_bus.h File Reference

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stm32f1xx_ll_bus.h File Reference

Header file of BUS LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Defines

#define | LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
#define | LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
#define | LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
#define | LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
#define | LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
#define | LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
#define | LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
#define | LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
#define | LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
#define | LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
#define | LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
#define | LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
#define | LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
#define | LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
#define | LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
#define | LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
#define | LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
#define | LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
#define | LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
#define | LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
#define | LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
#define | LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
#define | LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
#define | LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
#define | LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
#define | LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
#define | LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
#define | LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define | LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define | LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN

Functions

__STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
Enable AHB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if AHB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
Disable AHB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs)
Enable APB1 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB1 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs)
Disable APB1 peripherals clock.
__STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs)
Force APB1 peripherals reset.
__STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs)
Release APB1 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs)
Enable APB2 peripherals clock.
__STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs)
Check if APB2 peripheral clock is enabled or not.
__STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs)
Disable APB2 peripherals clock.
__STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs)
Force APB2 peripherals reset.
__STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs)
Release APB2 peripherals reset.

Detailed Description

Header file of BUS LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_bus.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_cortex.h File Reference

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stm32f1xx_ll_cortex.h File Reference

Header file of CORTEX LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Defines

#define | LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define | LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk
#define | LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk
#define | LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk
#define | LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk

Functions

__STATIC_INLINE uint32_t | LL_SYSTICK_IsActiveCounterFlag (void)
This function checks if the Systick counter flag is active or not.
__STATIC_INLINE void | LL_SYSTICK_SetClkSource (uint32_t Source)
Configures the SysTick clock source.
__STATIC_INLINE uint32_t | LL_SYSTICK_GetClkSource (void)
Get the SysTick clock source.
__STATIC_INLINE void | LL_SYSTICK_EnableIT (void)
Enable SysTick exception request.
__STATIC_INLINE void | LL_SYSTICK_DisableIT (void)
Disable SysTick exception request.
__STATIC_INLINE uint32_t | LL_SYSTICK_IsEnabledIT (void)
Checks if the SYSTICK interrupt is enabled or disabled.
__STATIC_INLINE void | LL_LPM_EnableSleep (void)
Processor uses sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableDeepSleep (void)
Processor uses deep sleep as its low power mode.
__STATIC_INLINE void | LL_LPM_EnableSleepOnExit (void)
Configures sleep-on-exit when returning from Handler mode to Thread mode.
__STATIC_INLINE void | LL_LPM_DisableSleepOnExit (void)
Do not sleep when returning to Thread mode.
__STATIC_INLINE void | LL_LPM_EnableEventOnPend (void)
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
__STATIC_INLINE void | LL_LPM_DisableEventOnPend (void)
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
__STATIC_INLINE void | LL_HANDLER_EnableFault (uint32_t Fault)
Enable a fault in System handler control register (SHCSR)
__STATIC_INLINE void | LL_HANDLER_DisableFault (uint32_t Fault)
Disable a fault in System handler control register (SHCSR)
__STATIC_INLINE uint32_t | LL_CPUID_GetImplementer (void)
Get Implementer code.
__STATIC_INLINE uint32_t | LL_CPUID_GetVariant (void)
Get Variant number (The r value in the rnpn product revision identifier)
__STATIC_INLINE uint32_t | LL_CPUID_GetConstant (void)
Get Constant number.
__STATIC_INLINE uint32_t | LL_CPUID_GetParNo (void)
Get Part number.
__STATIC_INLINE uint32_t | LL_CPUID_GetRevision (void)
Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

Detailed Description

Header file of CORTEX LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL CORTEX driver contains a set of generic APIs that can be
    used by user:
      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
          functions
      (+) Low power mode configuration (SCB register of Cortex-MCU)
      (+) MPU API to configure and enable regions
          (MPU services provided only on some devices)
      (+) API to access to MCU info (CPUID register)
      (+) API to enable fault handler (SHCSR accesses)
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_cortex.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_crc.h File Reference

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stm32f1xx_ll_crc.h File Reference

Header file of CRC LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Defines

#define | LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in CRC register.
#define | LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in CRC register.

Functions

__STATIC_INLINE void | LL_CRC_ResetCRCCalculationUnit (CRC_TypeDef *CRCx)
Reset the CRC calculation unit.
__STATIC_INLINE void | LL_CRC_FeedData32 (CRC_TypeDef *CRCx, uint32_t InData)
Write given 32-bit data to the CRC calculator.
__STATIC_INLINE uint32_t | LL_CRC_ReadData32 (CRC_TypeDef *CRCx)
Return current CRC calculation result.
__STATIC_INLINE uint32_t | LL_CRC_Read_IDR (CRC_TypeDef *CRCx)
Return data stored in the Independent Data(IDR) register.
__STATIC_INLINE void | LL_CRC_Write_IDR (CRC_TypeDef *CRCx, uint32_t InData)
Store data in the Independent Data(IDR) register.
ErrorStatus | LL_CRC_DeInit (CRC_TypeDef *CRCx)
De-initialize CRC registers (Registers restored to their default values).

Detailed Description

Header file of CRC LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_crc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_dma.h File Reference

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stm32f1xx_ll_dma.h File Reference

Header file of DMA LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_DMA_InitTypeDef

Defines

#define | LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1
#define | LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1
#define | LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1
#define | LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1
#define | LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2
#define | LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2
#define | LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2
#define | LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2
#define | LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3
#define | LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3
#define | LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3
#define | LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3
#define | LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4
#define | LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4
#define | LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4
#define | LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4
#define | LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5
#define | LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5
#define | LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5
#define | LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5
#define | LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6
#define | LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6
#define | LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6
#define | LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6
#define | LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7
#define | LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7
#define | LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7
#define | LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7
#define | LL_DMA_ISR_GIF1 DMA_ISR_GIF1
#define | LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1
#define | LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1
#define | LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1
#define | LL_DMA_ISR_GIF2 DMA_ISR_GIF2
#define | LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2
#define | LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2
#define | LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2
#define | LL_DMA_ISR_GIF3 DMA_ISR_GIF3
#define | LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3
#define | LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3
#define | LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3
#define | LL_DMA_ISR_GIF4 DMA_ISR_GIF4
#define | LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4
#define | LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4
#define | LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4
#define | LL_DMA_ISR_GIF5 DMA_ISR_GIF5
#define | LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5
#define | LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5
#define | LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5
#define | LL_DMA_ISR_GIF6 DMA_ISR_GIF6
#define | LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6
#define | LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6
#define | LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6
#define | LL_DMA_ISR_GIF7 DMA_ISR_GIF7
#define | LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7
#define | LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7
#define | LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7
#define | LL_DMA_CCR_TCIE DMA_CCR_TCIE
#define | LL_DMA_CCR_HTIE DMA_CCR_HTIE
#define | LL_DMA_CCR_TEIE DMA_CCR_TEIE
#define | LL_DMA_CHANNEL_1 0x00000001U
#define | LL_DMA_CHANNEL_2 0x00000002U
#define | LL_DMA_CHANNEL_3 0x00000003U
#define | LL_DMA_CHANNEL_4 0x00000004U
#define | LL_DMA_CHANNEL_5 0x00000005U
#define | LL_DMA_CHANNEL_6 0x00000006U
#define | LL_DMA_CHANNEL_7 0x00000007U
#define | LL_DMA_CHANNEL_ALL 0xFFFF0000U
#define | LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U
#define | LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR
#define | LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM
#define | LL_DMA_MODE_NORMAL 0x00000000U
#define | LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC
#define | LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC
#define | LL_DMA_PERIPH_NOINCREMENT 0x00000000U
#define | LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC
#define | LL_DMA_MEMORY_NOINCREMENT 0x00000000U
#define | LL_DMA_PDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0
#define | LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1
#define | LL_DMA_MDATAALIGN_BYTE 0x00000000U
#define | LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0
#define | LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1
#define | LL_DMA_PRIORITY_LOW 0x00000000U
#define | LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0
#define | LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1
#define | LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL
#define | LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in DMA register.
#define | LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in DMA register.
#define | __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
Convert DMAx_Channely into DMAx.
#define | __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)
Convert DMAx_Channely into LL_DMA_CHANNEL_y.
#define | __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)
Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely.

Functions

__STATIC_INLINE void | LL_DMA_EnableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Enable DMA channel.
__STATIC_INLINE void | LL_DMA_DisableChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Disable DMA channel.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledChannel (DMA_TypeDef *DMAx, uint32_t Channel)
Check if DMA channel is enabled or disabled.
__STATIC_INLINE void | LL_DMA_ConfigTransfer (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
Configure all parameters link to DMA transfer.
__STATIC_INLINE void | LL_DMA_SetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
Set Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE uint32_t | LL_DMA_GetDataTransferDirection (DMA_TypeDef *DMAx, uint32_t Channel)
Get Data transfer direction (read from peripheral or from memory).
__STATIC_INLINE void | LL_DMA_SetMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
Set DMA mode circular or normal.
__STATIC_INLINE uint32_t | LL_DMA_GetMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get DMA mode circular or normal.
__STATIC_INLINE void | LL_DMA_SetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
Set Peripheral increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral increment mode.
__STATIC_INLINE void | LL_DMA_SetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
Set Memory increment mode.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryIncMode (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory increment mode.
__STATIC_INLINE void | LL_DMA_SetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
Set Peripheral size.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphSize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral size.
__STATIC_INLINE void | LL_DMA_SetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
Set Memory size.
__STATIC_INLINE uint32_t | LL_DMA_GetMemorySize (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory size.
__STATIC_INLINE void | LL_DMA_SetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
Set Channel priority level.
__STATIC_INLINE uint32_t | LL_DMA_GetChannelPriorityLevel (DMA_TypeDef *DMAx, uint32_t Channel)
Get Channel priority level.
__STATIC_INLINE void | LL_DMA_SetDataLength (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
Set Number of data to transfer.
__STATIC_INLINE uint32_t | LL_DMA_GetDataLength (DMA_TypeDef *DMAx, uint32_t Channel)
Get Number of data to transfer.
__STATIC_INLINE void | LL_DMA_ConfigAddresses (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
Configure the Source and Destination addresses.
__STATIC_INLINE void | LL_DMA_SetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory address.
__STATIC_INLINE void | LL_DMA_SetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
Set the Peripheral address.
__STATIC_INLINE uint32_t | LL_DMA_GetMemoryAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Memory address.
__STATIC_INLINE uint32_t | LL_DMA_GetPeriphAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get Peripheral address.
__STATIC_INLINE void | LL_DMA_SetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Source address.
__STATIC_INLINE void | LL_DMA_SetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
Set the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MSrcAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Source address.
__STATIC_INLINE uint32_t | LL_DMA_GetM2MDstAddress (DMA_TypeDef *DMAx, uint32_t Channel)
Get the Memory to Memory Destination address.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI1 (DMA_TypeDef *DMAx)
Get Channel 1 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI2 (DMA_TypeDef *DMAx)
Get Channel 2 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI3 (DMA_TypeDef *DMAx)
Get Channel 3 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI4 (DMA_TypeDef *DMAx)
Get Channel 4 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI5 (DMA_TypeDef *DMAx)
Get Channel 5 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI6 (DMA_TypeDef *DMAx)
Get Channel 6 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_GI7 (DMA_TypeDef *DMAx)
Get Channel 7 global interrupt flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TC7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer complete flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT1 (DMA_TypeDef *DMAx)
Get Channel 1 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT2 (DMA_TypeDef *DMAx)
Get Channel 2 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT3 (DMA_TypeDef *DMAx)
Get Channel 3 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT4 (DMA_TypeDef *DMAx)
Get Channel 4 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT5 (DMA_TypeDef *DMAx)
Get Channel 5 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT6 (DMA_TypeDef *DMAx)
Get Channel 6 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_HT7 (DMA_TypeDef *DMAx)
Get Channel 7 half transfer flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE1 (DMA_TypeDef *DMAx)
Get Channel 1 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE2 (DMA_TypeDef *DMAx)
Get Channel 2 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE3 (DMA_TypeDef *DMAx)
Get Channel 3 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE4 (DMA_TypeDef *DMAx)
Get Channel 4 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE5 (DMA_TypeDef *DMAx)
Get Channel 5 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE6 (DMA_TypeDef *DMAx)
Get Channel 6 transfer error flag.
__STATIC_INLINE uint32_t | LL_DMA_IsActiveFlag_TE7 (DMA_TypeDef *DMAx)
Get Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI1 (DMA_TypeDef *DMAx)
Clear Channel 1 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI2 (DMA_TypeDef *DMAx)
Clear Channel 2 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI3 (DMA_TypeDef *DMAx)
Clear Channel 3 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI4 (DMA_TypeDef *DMAx)
Clear Channel 4 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI5 (DMA_TypeDef *DMAx)
Clear Channel 5 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI6 (DMA_TypeDef *DMAx)
Clear Channel 6 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_GI7 (DMA_TypeDef *DMAx)
Clear Channel 7 global interrupt flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TC7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer complete flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT1 (DMA_TypeDef *DMAx)
Clear Channel 1 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT2 (DMA_TypeDef *DMAx)
Clear Channel 2 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT3 (DMA_TypeDef *DMAx)
Clear Channel 3 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT4 (DMA_TypeDef *DMAx)
Clear Channel 4 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT5 (DMA_TypeDef *DMAx)
Clear Channel 5 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT6 (DMA_TypeDef *DMAx)
Clear Channel 6 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_HT7 (DMA_TypeDef *DMAx)
Clear Channel 7 half transfer flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE1 (DMA_TypeDef *DMAx)
Clear Channel 1 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE2 (DMA_TypeDef *DMAx)
Clear Channel 2 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE3 (DMA_TypeDef *DMAx)
Clear Channel 3 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE4 (DMA_TypeDef *DMAx)
Clear Channel 4 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE5 (DMA_TypeDef *DMAx)
Clear Channel 5 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE6 (DMA_TypeDef *DMAx)
Clear Channel 6 transfer error flag.
__STATIC_INLINE void | LL_DMA_ClearFlag_TE7 (DMA_TypeDef *DMAx)
Clear Channel 7 transfer error flag.
__STATIC_INLINE void | LL_DMA_EnableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_EnableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Enable Transfer error interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer complete interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Half transfer interrupt.
__STATIC_INLINE void | LL_DMA_DisableIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Disable Transfer error interrupt.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TC (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer complete Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_HT (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Half transfer Interrupt is enabled.
__STATIC_INLINE uint32_t | LL_DMA_IsEnabledIT_TE (DMA_TypeDef *DMAx, uint32_t Channel)
Check if Transfer error Interrupt is enabled.
uint32_t | LL_DMA_Init (DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
uint32_t | LL_DMA_DeInit (DMA_TypeDef *DMAx, uint32_t Channel)
De-initialize the DMA registers to their default reset values.
void | LL_DMA_StructInit (LL_DMA_InitTypeDef *DMA_InitStruct)
Set each LL_DMA_InitTypeDef field to default value.

Variables

static const uint8_t | CHANNEL_OFFSET_TAB []

Detailed Description

Header file of DMA LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_dma.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_exti.h File Reference

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stm32f1xx_ll_exti.h File Reference

Header file of EXTI LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_EXTI_InitTypeDef

Defines

#define | LL_EXTI_LINE_0 EXTI_IMR_IM0
#define | LL_EXTI_LINE_1 EXTI_IMR_IM1
#define | LL_EXTI_LINE_2 EXTI_IMR_IM2
#define | LL_EXTI_LINE_3 EXTI_IMR_IM3
#define | LL_EXTI_LINE_4 EXTI_IMR_IM4
#define | LL_EXTI_LINE_5 EXTI_IMR_IM5
#define | LL_EXTI_LINE_6 EXTI_IMR_IM6
#define | LL_EXTI_LINE_7 EXTI_IMR_IM7
#define | LL_EXTI_LINE_8 EXTI_IMR_IM8
#define | LL_EXTI_LINE_9 EXTI_IMR_IM9
#define | LL_EXTI_LINE_10 EXTI_IMR_IM10
#define | LL_EXTI_LINE_11 EXTI_IMR_IM11
#define | LL_EXTI_LINE_12 EXTI_IMR_IM12
#define | LL_EXTI_LINE_13 EXTI_IMR_IM13
#define | LL_EXTI_LINE_14 EXTI_IMR_IM14
#define | LL_EXTI_LINE_15 EXTI_IMR_IM15
#define | LL_EXTI_LINE_16 EXTI_IMR_IM16
#define | LL_EXTI_LINE_17 EXTI_IMR_IM17
#define | LL_EXTI_LINE_18 EXTI_IMR_IM18
#define | LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM
#define | LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU)
#define | LL_EXTI_LINE_NONE ((uint32_t)0x00000000U)
#define | LL_EXTI_MODE_IT ((uint8_t)0x00U)
#define | LL_EXTI_MODE_EVENT ((uint8_t)0x01U)
#define | LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U)
#define | LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U)
#define | LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U)
#define | LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U)
#define | LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
Write a value in EXTI register.
#define | LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
Read a value in EXTI register.

Functions

__STATIC_INLINE void | LL_EXTI_EnableIT_0_31 (uint32_t ExtiLine)
Enable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableIT_0_31 (uint32_t ExtiLine)
Disable ExtiLine Interrupt request for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledIT_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableEvent_0_31 (uint32_t ExtiLine)
Enable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableEvent_0_31 (uint32_t ExtiLine)
Disable ExtiLine Event request for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledEvent_0_31 (uint32_t ExtiLine)
Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableRisingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableRisingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledRisingTrig_0_31 (uint32_t ExtiLine)
Check if rising edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_EnableFallingTrig_0_31 (uint32_t ExtiLine)
Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_DisableFallingTrig_0_31 (uint32_t ExtiLine)
Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsEnabledFallingTrig_0_31 (uint32_t ExtiLine)
Check if falling edge trigger is enabled for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_GenerateSWI_0_31 (uint32_t ExtiLine)
Generate a software Interrupt Event for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_IsActiveFlag_0_31 (uint32_t ExtiLine)
Check if the ExtLine Flag is set or not for Lines in range 0 to 31.
__STATIC_INLINE uint32_t | LL_EXTI_ReadFlag_0_31 (uint32_t ExtiLine)
Read ExtLine Combination Flag for Lines in range 0 to 31.
__STATIC_INLINE void | LL_EXTI_ClearFlag_0_31 (uint32_t ExtiLine)
Clear ExtLine Flags for Lines in range 0 to 31.
uint32_t | LL_EXTI_Init (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
uint32_t | LL_EXTI_DeInit (void)
De-initialize the EXTI registers to their default reset values.
void | LL_EXTI_StructInit (LL_EXTI_InitTypeDef *EXTI_InitStruct)
Set each LL_EXTI_InitTypeDef field to default value.

Detailed Description

Header file of EXTI LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_exti.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_gpio.h File Reference

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stm32f1xx_ll_gpio.h File Reference

Header file of GPIO LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...

Defines

#define | LL_GPIO_PIN_0 (GPIO_BSRR_BS0 << 8) | 0x00000001U
#define | LL_GPIO_PIN_1 (GPIO_BSRR_BS1 << 8) | 0x00000002U
#define | LL_GPIO_PIN_2 (GPIO_BSRR_BS2 << 8) | 0x00000004U
#define | LL_GPIO_PIN_3 (GPIO_BSRR_BS3 << 8) | 0x00000008U
#define | LL_GPIO_PIN_4 (GPIO_BSRR_BS4 << 8) | 0x00000010U
#define | LL_GPIO_PIN_5 (GPIO_BSRR_BS5 << 8) | 0x00000020U
#define | LL_GPIO_PIN_6 (GPIO_BSRR_BS6 << 8) | 0x00000040U
#define | LL_GPIO_PIN_7 (GPIO_BSRR_BS7 << 8) | 0x00000080U
#define | LL_GPIO_PIN_8 (GPIO_BSRR_BS8 << 8) | 0x04000001U
#define | LL_GPIO_PIN_9 (GPIO_BSRR_BS9 << 8) | 0x04000002U
#define | LL_GPIO_PIN_10 (GPIO_BSRR_BS10 << 8) | 0x04000004U
#define | LL_GPIO_PIN_11 (GPIO_BSRR_BS11 << 8) | 0x04000008U
#define | LL_GPIO_PIN_12 (GPIO_BSRR_BS12 << 8) | 0x04000010U
#define | LL_GPIO_PIN_13 (GPIO_BSRR_BS13 << 8) | 0x04000020U
#define | LL_GPIO_PIN_14 (GPIO_BSRR_BS14 << 8) | 0x04000040U
#define | LL_GPIO_PIN_15 (GPIO_BSRR_BS15 << 8) | 0x04000080U
#define | LL_GPIO_PIN_ALL
#define | LL_GPIO_MODE_ANALOG 0x00000000U
#define | LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0
#define | LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1
#define | LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0
#define | LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0)
#define | LL_GPIO_OUTPUT_PUSHPULL 0x00000000U
#define | LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0
#define | LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0
#define | LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1
#define | LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0
#define | LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz
#define | LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz
#define | LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz
#define | LL_GPIO_PULL_DOWN 0x00000000U
#define | LL_GPIO_PULL_UP GPIO_ODR_ODR0
#define | LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0
#define | LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1
#define | LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2
#define | LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3
#define | LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4
#define | LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5
#define | LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6
#define | LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7
#define | LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8
#define | LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9
#define | LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10
#define | LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11
#define | LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12
#define | LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13
#define | LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14
#define | LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15
#define | LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA
#define | LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB
#define | LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC
#define | LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD
#define | LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE
#define | LL_GPIO_AF_EXTI_PORTA (uint32_t)0
#define | LL_GPIO_AF_EXTI_PORTB (uint32_t)1
#define | LL_GPIO_AF_EXTI_PORTC (uint32_t)2
#define | LL_GPIO_AF_EXTI_PORTD (uint32_t)3
#define | LL_GPIO_AF_EXTI_PORTE (uint32_t)4
#define | LL_GPIO_AF_EXTI_PORTF (uint32_t)5
#define | LL_GPIO_AF_EXTI_PORTG (uint32_t)6
#define | LL_GPIO_AF_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0)
#define | LL_GPIO_AF_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0)
#define | LL_GPIO_AF_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0)
#define | LL_GPIO_AF_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0)
#define | LL_GPIO_AF_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1)
#define | LL_GPIO_AF_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1)
#define | LL_GPIO_AF_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1)
#define | LL_GPIO_AF_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1)
#define | LL_GPIO_AF_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2)
#define | LL_GPIO_AF_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2)
#define | LL_GPIO_AF_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2)
#define | LL_GPIO_AF_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2)
#define | LL_GPIO_AF_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3)
#define | LL_GPIO_AF_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3)
#define | LL_GPIO_AF_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3)
#define | LL_GPIO_AF_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3)
#define | LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in GPIO register.
#define | LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in GPIO register.

Functions

__STATIC_INLINE void | LL_GPIO_SetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
Configure gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinMode (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio mode for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
Configure gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinSpeed (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio speed for a dedicated pin on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
Configure gpio output type for several pins on dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinOutputType (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio output type for several pins on dedicated port.
__STATIC_INLINE void | LL_GPIO_SetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_GetPinPull (GPIO_TypeDef *GPIOx, uint32_t Pin)
Return gpio pull-up or pull-down for a dedicated pin on a dedicated port.
__STATIC_INLINE void | LL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Lock configuration of several pins for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsPinLocked (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return 1 if all pins passed as parameter, of a dedicated port, are locked.
__STATIC_INLINE uint32_t | LL_GPIO_IsAnyPinLocked (GPIO_TypeDef *GPIOx)
Return 1 if one of the pin of a dedicated port is locked.
__STATIC_INLINE uint32_t | LL_GPIO_ReadInputPort (GPIO_TypeDef *GPIOx)
Return full input data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsInputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_WriteOutputPort (GPIO_TypeDef *GPIOx, uint32_t PortValue)
Write output data register for the port.
__STATIC_INLINE uint32_t | LL_GPIO_ReadOutputPort (GPIO_TypeDef *GPIOx)
Return full output data register value for a dedicated port.
__STATIC_INLINE uint32_t | LL_GPIO_IsOutputPinSet (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Return if input data level for several pins of dedicated port is high or low.
__STATIC_INLINE void | LL_GPIO_SetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to high level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_ResetOutputPin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Set several pins to low level on dedicated gpio port.
__STATIC_INLINE void | LL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint32_t PinMask)
Toggle data value for several pin of dedicated port.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_SPI1 (void)
Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_SPI1 (void)
Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_SPI1 (void)
Check if SPI1 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_I2C1 (void)
Enable the remapping of I2C1 alternate function SCL and SDA.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_I2C1 (void)
Disable the remapping of I2C1 alternate function SCL and SDA.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_I2C1 (void)
Check if I2C1 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_USART1 (void)
Enable the remapping of USART1 alternate function TX and RX.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_USART1 (void)
Disable the remapping of USART1 alternate function TX and RX.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_USART1 (void)
Check if USART1 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_USART2 (void)
Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_USART2 (void)
Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_USART2 (void)
Check if USART2 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_USART3 (void)
Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial_USART3 (void)
Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_USART3 (void)
Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_TIM1 (void)
Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial_TIM1 (void)
Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_TIM1 (void)
Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_TIM2 (void)
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial2_TIM2 (void)
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial1_TIM2 (void)
Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_TIM2 (void)
Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_TIM3 (void)
Enable the remapping of TIM3 alternate function channels 1 to 4.
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial_TIM3 (void)
Enable the remapping of TIM3 alternate function channels 1 to 4.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_TIM3 (void)
Disable the remapping of TIM3 alternate function channels 1 to 4.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_TIM4 (void)
Enable the remapping of TIM4 alternate function channels 1 to 4.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_TIM4 (void)
Disable the remapping of TIM4 alternate function channels 1 to 4.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_TIM4 (void)
Check if TIM4 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial1_CAN1 (void)
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial2_CAN1 (void)
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
__STATIC_INLINE void | LL_GPIO_AF_RemapPartial3_CAN1 (void)
Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_PD01 (void)
Enable the remapping of PD0 and PD1.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_PD01 (void)
Disable the remapping of PD0 and PD1.
__STATIC_INLINE uint32_t | LL_GPIO_AF_IsEnabledRemap_PD01 (void)
Check if PD01 has been remaped or not.
__STATIC_INLINE void | LL_GPIO_AF_EnableRemap_SWJ (void)
Enable the Serial wire JTAG configuration.
__STATIC_INLINE void | LL_GPIO_AF_Remap_SWJ_NONJTRST (void)
Enable the Serial wire JTAG configuration.
__STATIC_INLINE void | LL_GPIO_AF_Remap_SWJ_NOJTAG (void)
Enable the Serial wire JTAG configuration.
__STATIC_INLINE void | LL_GPIO_AF_DisableRemap_SWJ (void)
Disable the Serial wire JTAG configuration.
__STATIC_INLINE void | LL_GPIO_AF_ConfigEventout (uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
__STATIC_INLINE void | LL_GPIO_AF_EnableEventout (void)
Enables the Event Output.
__STATIC_INLINE void | LL_GPIO_AF_DisableEventout (void)
Disables the Event Output.
__STATIC_INLINE void | LL_GPIO_AF_SetEXTISource (uint32_t Port, uint32_t Line)
Configure source input for the EXTI external interrupt.
__STATIC_INLINE uint32_t | LL_GPIO_AF_GetEXTISource (uint32_t Line)
Get the configured defined for specific EXTI Line.
ErrorStatus | LL_GPIO_DeInit (GPIO_TypeDef *GPIOx)
De-initialize GPIO registers (Registers restored to their default values).
ErrorStatus | LL_GPIO_Init (GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
void | LL_GPIO_StructInit (LL_GPIO_InitTypeDef *GPIO_InitStruct)
Set each LL_GPIO_InitTypeDef field to default value.

Detailed Description

Header file of GPIO LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_gpio.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_i2c.h File Reference

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Data Structures | Defines | Functions
stm32f1xx_ll_i2c.h File Reference

Header file of I2C LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_I2C_InitTypeDef

Defines

#define | LL_I2C_MAX_SPEED_STANDARD 100000U
#define | LL_I2C_MAX_SPEED_FAST 400000U
#define | LL_I2C_SR1_SB I2C_SR1_SB
#define | LL_I2C_SR1_ADDR I2C_SR1_ADDR
#define | LL_I2C_SR1_BTF I2C_SR1_BTF
#define | LL_I2C_SR1_ADD10 I2C_SR1_ADD10
#define | LL_I2C_SR1_STOPF I2C_SR1_STOPF
#define | LL_I2C_SR1_RXNE I2C_SR1_RXNE
#define | LL_I2C_SR1_TXE I2C_SR1_TXE
#define | LL_I2C_SR1_BERR I2C_SR1_BERR
#define | LL_I2C_SR1_ARLO I2C_SR1_ARLO
#define | LL_I2C_SR1_AF I2C_SR1_AF
#define | LL_I2C_SR1_OVR I2C_SR1_OVR
#define | LL_I2C_SR1_PECERR I2C_ISR_PECERR
#define | LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT
#define | LL_I2C_SR1_SMALERT I2C_ISR_SMALERT
#define | LL_I2C_SR2_MSL I2C_SR2_MSL
#define | LL_I2C_SR2_BUSY I2C_SR2_BUSY
#define | LL_I2C_SR2_TRA I2C_SR2_TRA
#define | LL_I2C_SR2_GENCALL I2C_SR2_GENCALL
#define | LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT
#define | LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST
#define | LL_I2C_SR2_DUALF I2C_SR2_DUALF
#define | LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN
#define | LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN
#define | LL_I2C_CR2_ITERREN I2C_CR2_ITERREN
#define | LL_I2C_OWNADDRESS1_7BIT 0x00004000U
#define | LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U)
#define | LL_I2C_DUTYCYCLE_2 0x00000000U
#define | LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
#define | LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U
#define | LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS
#define | LL_I2C_MODE_I2C 0x00000000U
#define | LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP)
#define | LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS
#define | LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP)
#define | LL_I2C_ACK I2C_CR1_ACK
#define | LL_I2C_NACK 0x00000000U
#define | LL_I2C_DIRECTION_WRITE I2C_SR2_TRA
#define | LL_I2C_DIRECTION_READ 0x00000000U
#define | LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2C register.
#define | LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2C register.
#define | __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
Convert Peripheral Clock Frequency in Mhz.
#define | __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
Convert Peripheral Clock Frequency in Hz.
#define | __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
Compute I2C Clock rising time.
#define | __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__)
Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
#define | __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
#define | __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__)
Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
#define | __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
Get the Least significant bits of a 10-Bits address.
#define | __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
Convert a 10-Bits address to a 10-Bits header with Write direction.
#define | __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
Convert a 10-Bits address to a 10-Bits header with Read direction.

Functions

__STATIC_INLINE void | LL_I2C_Enable (I2C_TypeDef *I2Cx)
Enable I2C peripheral (PE = 1).
__STATIC_INLINE void | LL_I2C_Disable (I2C_TypeDef *I2Cx)
Disable I2C peripheral (PE = 0).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_TX (I2C_TypeDef *I2Cx)
Enable DMA transmission requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_TX (I2C_TypeDef *I2Cx)
Disable DMA transmission requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_TX (I2C_TypeDef *I2Cx)
Check if DMA transmission requests are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableDMAReq_RX (I2C_TypeDef *I2Cx)
Enable DMA reception requests.
__STATIC_INLINE void | LL_I2C_DisableDMAReq_RX (I2C_TypeDef *I2Cx)
Disable DMA reception requests.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledDMAReq_RX (I2C_TypeDef *I2Cx)
Check if DMA reception requests are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_DMA_GetRegAddr (I2C_TypeDef *I2Cx)
Get the data register address used for DMA transfer.
__STATIC_INLINE void | LL_I2C_EnableClockStretching (I2C_TypeDef *I2Cx)
Enable Clock stretching.
__STATIC_INLINE void | LL_I2C_DisableClockStretching (I2C_TypeDef *I2Cx)
Disable Clock stretching.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledClockStretching (I2C_TypeDef *I2Cx)
Check if Clock stretching is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableGeneralCall (I2C_TypeDef *I2Cx)
Enable General Call.
__STATIC_INLINE void | LL_I2C_DisableGeneralCall (I2C_TypeDef *I2Cx)
Disable General Call.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledGeneralCall (I2C_TypeDef *I2Cx)
Check if General Call is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetOwnAddress1 (I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
Set the Own Address1.
__STATIC_INLINE void | LL_I2C_SetOwnAddress2 (I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
Set the 7bits Own Address2.
__STATIC_INLINE void | LL_I2C_EnableOwnAddress2 (I2C_TypeDef *I2Cx)
Enable acknowledge on Own Address2 match address.
__STATIC_INLINE void | LL_I2C_DisableOwnAddress2 (I2C_TypeDef *I2Cx)
Disable acknowledge on Own Address2 match address.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledOwnAddress2 (I2C_TypeDef *I2Cx)
Check if Own Address1 acknowledge is enabled or disabled.
__STATIC_INLINE void | LL_I2C_SetPeriphClock (I2C_TypeDef *I2Cx, uint32_t PeriphClock)
Configure the Peripheral clock frequency.
__STATIC_INLINE uint32_t | LL_I2C_GetPeriphClock (I2C_TypeDef *I2Cx)
Get the Peripheral clock frequency.
__STATIC_INLINE void | LL_I2C_SetDutyCycle (I2C_TypeDef *I2Cx, uint32_t DutyCycle)
Configure the Duty cycle (Fast mode only).
__STATIC_INLINE uint32_t | LL_I2C_GetDutyCycle (I2C_TypeDef *I2Cx)
Get the Duty cycle (Fast mode only).
__STATIC_INLINE void | LL_I2C_SetClockSpeedMode (I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
Configure the I2C master clock speed mode.
__STATIC_INLINE uint32_t | LL_I2C_GetClockSpeedMode (I2C_TypeDef *I2Cx)
Get the the I2C master speed mode.
__STATIC_INLINE void | LL_I2C_SetRiseTime (I2C_TypeDef *I2Cx, uint32_t RiseTime)
Configure the SCL, SDA rising time.
__STATIC_INLINE uint32_t | LL_I2C_GetRiseTime (I2C_TypeDef *I2Cx)
Get the SCL, SDA rising time.
__STATIC_INLINE void | LL_I2C_SetClockPeriod (I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
Configure the SCL high and low period.
__STATIC_INLINE uint32_t | LL_I2C_GetClockPeriod (I2C_TypeDef *I2Cx)
Get the SCL high and low period.
__STATIC_INLINE void | LL_I2C_ConfigSpeed (I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed, uint32_t DutyCycle)
Configure the SCL speed.
__STATIC_INLINE void | LL_I2C_SetMode (I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
Configure peripheral mode.
__STATIC_INLINE uint32_t | LL_I2C_GetMode (I2C_TypeDef *I2Cx)
Get peripheral mode.
__STATIC_INLINE void | LL_I2C_EnableSMBusAlert (I2C_TypeDef *I2Cx)
Enable SMBus alert (Host or Device mode)
__STATIC_INLINE void | LL_I2C_DisableSMBusAlert (I2C_TypeDef *I2Cx)
Disable SMBus alert (Host or Device mode)
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusAlert (I2C_TypeDef *I2Cx)
Check if SMBus alert (Host or Device mode) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPEC (I2C_TypeDef *I2Cx)
Enable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE void | LL_I2C_DisableSMBusPEC (I2C_TypeDef *I2Cx)
Disable SMBus Packet Error Calculation (PEC).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPEC (I2C_TypeDef *I2Cx)
Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_TX (I2C_TypeDef *I2Cx)
Enable TXE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_TX (I2C_TypeDef *I2Cx)
Disable TXE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_TX (I2C_TypeDef *I2Cx)
Check if the TXE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_RX (I2C_TypeDef *I2Cx)
Enable RXNE interrupt.
__STATIC_INLINE void | LL_I2C_DisableIT_RX (I2C_TypeDef *I2Cx)
Disable RXNE interrupt.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_RX (I2C_TypeDef *I2Cx)
Check if the RXNE Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_EVT (I2C_TypeDef *I2Cx)
Enable Events interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_EVT (I2C_TypeDef *I2Cx)
Disable Events interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_EVT (I2C_TypeDef *I2Cx)
Check if Events interrupts are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_BUF (I2C_TypeDef *I2Cx)
Enable Buffer interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_BUF (I2C_TypeDef *I2Cx)
Disable Buffer interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_BUF (I2C_TypeDef *I2Cx)
Check if Buffer interrupts are enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableIT_ERR (I2C_TypeDef *I2Cx)
Enable Error interrupts.
__STATIC_INLINE void | LL_I2C_DisableIT_ERR (I2C_TypeDef *I2Cx)
Disable Error interrupts.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledIT_ERR (I2C_TypeDef *I2Cx)
Check if Error interrupts are enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_TXE (I2C_TypeDef *I2Cx)
Indicate the status of Transmit data register empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BTF (I2C_TypeDef *I2Cx)
Indicate the status of Byte Transfer Finished flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_RXNE (I2C_TypeDef *I2Cx)
Indicate the status of Receive data register not empty flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_SB (I2C_TypeDef *I2Cx)
Indicate the status of Start Bit (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADDR (I2C_TypeDef *I2Cx)
Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ADD10 (I2C_TypeDef *I2Cx)
Indicate the status of 10-bit header sent (master mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_AF (I2C_TypeDef *I2Cx)
Indicate the status of Acknowledge failure flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_STOP (I2C_TypeDef *I2Cx)
Indicate the status of Stop detection flag (slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BERR (I2C_TypeDef *I2Cx)
Indicate the status of Bus error flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_ARLO (I2C_TypeDef *I2Cx)
Indicate the status of Arbitration lost flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_OVR (I2C_TypeDef *I2Cx)
Indicate the status of Overrun/Underrun flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Indicate the status of SMBus PEC error flag in reception.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Timeout detection flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus alert flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_BUSY (I2C_TypeDef *I2Cx)
Indicate the status of Bus Busy flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_DUAL (I2C_TypeDef *I2Cx)
Indicate the status of Dual flag.
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_SMBHOST (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Host address reception (Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveSMBusFlag_SMBDEFAULT (I2C_TypeDef *I2Cx)
Indicate the status of SMBus Device default address reception (Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_GENCALL (I2C_TypeDef *I2Cx)
Indicate the status of General call address reception (Slave mode).
__STATIC_INLINE uint32_t | LL_I2C_IsActiveFlag_MSL (I2C_TypeDef *I2Cx)
Indicate the status of Master/Slave flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ADDR (I2C_TypeDef *I2Cx)
Clear Address Matched flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_AF (I2C_TypeDef *I2Cx)
Clear Acknowledge failure flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_STOP (I2C_TypeDef *I2Cx)
Clear Stop detection flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_BERR (I2C_TypeDef *I2Cx)
Clear Bus error flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_ARLO (I2C_TypeDef *I2Cx)
Clear Arbitration lost flag.
__STATIC_INLINE void | LL_I2C_ClearFlag_OVR (I2C_TypeDef *I2Cx)
Clear Overrun/Underrun flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_PECERR (I2C_TypeDef *I2Cx)
Clear SMBus PEC error flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_TIMEOUT (I2C_TypeDef *I2Cx)
Clear SMBus Timeout detection flag.
__STATIC_INLINE void | LL_I2C_ClearSMBusFlag_ALERT (I2C_TypeDef *I2Cx)
Clear SMBus Alert flag.
__STATIC_INLINE void | LL_I2C_EnableReset (I2C_TypeDef *I2Cx)
Enable Reset of I2C peripheral.
__STATIC_INLINE void | LL_I2C_DisableReset (I2C_TypeDef *I2Cx)
Disable Reset of I2C peripheral.
__STATIC_INLINE uint32_t | LL_I2C_IsResetEnabled (I2C_TypeDef *I2Cx)
Check if the I2C peripheral is under reset state or not.
__STATIC_INLINE void | LL_I2C_AcknowledgeNextData (I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
__STATIC_INLINE void | LL_I2C_GenerateStartCondition (I2C_TypeDef *I2Cx)
Generate a START or RESTART condition.
__STATIC_INLINE void | LL_I2C_GenerateStopCondition (I2C_TypeDef *I2Cx)
Generate a STOP condition after the current byte transfer (master mode).
__STATIC_INLINE void | LL_I2C_EnableBitPOS (I2C_TypeDef *I2Cx)
Enable bit POS (master/host mode).
__STATIC_INLINE void | LL_I2C_DisableBitPOS (I2C_TypeDef *I2Cx)
Disable bit POS (master/host mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledBitPOS (I2C_TypeDef *I2Cx)
Check if bit POS is enabled or disabled.
__STATIC_INLINE uint32_t | LL_I2C_GetTransferDirection (I2C_TypeDef *I2Cx)
Indicate the value of transfer direction.
__STATIC_INLINE void | LL_I2C_EnableLastDMA (I2C_TypeDef *I2Cx)
Enable DMA last transfer.
__STATIC_INLINE void | LL_I2C_DisableLastDMA (I2C_TypeDef *I2Cx)
Disable DMA last transfer.
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledLastDMA (I2C_TypeDef *I2Cx)
Check if DMA last transfer is enabled or disabled.
__STATIC_INLINE void | LL_I2C_EnableSMBusPECCompare (I2C_TypeDef *I2Cx)
Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE void | LL_I2C_DisableSMBusPECCompare (I2C_TypeDef *I2Cx)
Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
__STATIC_INLINE uint32_t | LL_I2C_IsEnabledSMBusPECCompare (I2C_TypeDef *I2Cx)
Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
__STATIC_INLINE uint32_t | LL_I2C_GetSMBusPEC (I2C_TypeDef *I2Cx)
Get the SMBus Packet Error byte calculated.
__STATIC_INLINE uint8_t | LL_I2C_ReceiveData8 (I2C_TypeDef *I2Cx)
Read Receive Data register.
__STATIC_INLINE void | LL_I2C_TransmitData8 (I2C_TypeDef *I2Cx, uint8_t Data)
Write in Transmit Data Register .
uint32_t | LL_I2C_Init (I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
uint32_t | LL_I2C_DeInit (I2C_TypeDef *I2Cx)
De-initialize the I2C registers to their default reset values.
void | LL_I2C_StructInit (LL_I2C_InitTypeDef *I2C_InitStruct)
Set each LL_I2C_InitTypeDef field to default value.

Detailed Description

Header file of I2C LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_i2c.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_i2s.h File Reference

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stm32f1xx_ll_i2s.h File Reference
#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_I2S_InitTypeDef
I2S Init structure definition. More...

Defines

#define | LL_I2S_SR_RXNE LL_SPI_SR_RXNE
#define | LL_I2S_SR_TXE LL_SPI_SR_TXE
#define | LL_I2S_SR_BSY LL_SPI_SR_BSY
#define | LL_I2S_SR_UDR SPI_SR_UDR
#define | LL_I2S_SR_OVR LL_SPI_SR_OVR
#define | LL_I2S_SR_FRE LL_SPI_SR_FRE
#define | LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE
#define | LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE
#define | LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE
#define | LL_I2S_DATAFORMAT_16B 0x00000000U
#define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
#define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
#define | LL_I2S_POLARITY_LOW 0x00000000U
#define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
#define | LL_I2S_STANDARD_PHILIPS 0x00000000U
#define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
#define | LL_I2S_MODE_SLAVE_TX 0x00000000U
#define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
#define | LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U
#define | LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)
#define | LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U
#define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define | LL_I2S_AUDIOFREQ_192K 192000U
#define | LL_I2S_AUDIOFREQ_96K 96000U
#define | LL_I2S_AUDIOFREQ_48K 48000U
#define | LL_I2S_AUDIOFREQ_44K 44100U
#define | LL_I2S_AUDIOFREQ_32K 32000U
#define | LL_I2S_AUDIOFREQ_22K 22050U
#define | LL_I2S_AUDIOFREQ_16K 16000U
#define | LL_I2S_AUDIOFREQ_11K 11025U
#define | LL_I2S_AUDIOFREQ_8K 8000U
#define | LL_I2S_AUDIOFREQ_DEFAULT 2U
#define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in I2S register.
#define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in I2S register.

Functions

__STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx)
Select I2S mode and Enable I2S peripheral.
__STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx)
Disable I2S peripheral.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabled (SPI_TypeDef *SPIx)
Check if I2S peripheral is enabled.
__STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataFormat)
Set I2S data frame length.
__STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx)
Get I2S data frame length.
__STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set I2S clock polarity.
__STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx)
Get I2S clock polarity.
__STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard)
Set I2S standard protocol.
__STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx)
Get I2S standard protocol.
__STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set I2S transfer mode.
__STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx)
Get I2S transfer mode.
__STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
Set I2S linear prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx)
Get I2S linear prescaler.
__STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity)
Set I2S parity prescaler.
__STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx)
Get I2S parity prescaler.
__STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx)
Enable the master clock ouput (Pin MCK)
__STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx)
Disable the master clock ouput (Pin MCK)
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx)
Check if the master clock ouput (Pin MCK) is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx)
Get underrun error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx)
Get frame format error flag.
__STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_CHSIDE (SPI_TypeDef *SPIx)
Get channel side flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx)
Clear underrun error flag.
__STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx)
Clear frame format error flag.
__STATIC_INLINE void | LL_I2S_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error IT.
__STATIC_INLINE void | LL_I2S_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error IT.
__STATIC_INLINE void | LL_I2S_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty IT.
__STATIC_INLINE void | LL_I2S_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty IT.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if ERR IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if RXNE IT is enabled.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if TXE IT is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in data register.
__STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in data register.
ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI/I2S registers to their default reset values.
ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct)
Set each LL_I2S_InitTypeDef field to default value.
void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
Set linear and parity prescaler.
Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_iwdg.h File Reference

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  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_ll_iwdg.h File Reference

Header file of IWDG LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Defines

#define | LL_IWDG_KEY_RELOAD 0x0000AAAAU
#define | LL_IWDG_KEY_ENABLE 0x0000CCCCU
#define | LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
#define | LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U
#define | LL_IWDG_SR_PVU IWDG_SR_PVU
#define | LL_IWDG_SR_RVU IWDG_SR_RVU
#define | LL_IWDG_PRESCALER_4 0x00000000U
#define | LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
#define | LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
#define | LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
#define | LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
#define | LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in IWDG register.
#define | LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in IWDG register.

Functions

__STATIC_INLINE void | LL_IWDG_Enable (IWDG_TypeDef *IWDGx)
Start the Independent Watchdog.
__STATIC_INLINE void | LL_IWDG_ReloadCounter (IWDG_TypeDef *IWDGx)
Reloads IWDG counter with value defined in the reload register.
__STATIC_INLINE void | LL_IWDG_EnableWriteAccess (IWDG_TypeDef *IWDGx)
Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_DisableWriteAccess (IWDG_TypeDef *IWDGx)
Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
__STATIC_INLINE void | LL_IWDG_SetPrescaler (IWDG_TypeDef *IWDGx, uint32_t Prescaler)
Select the prescaler of the IWDG.
__STATIC_INLINE uint32_t | LL_IWDG_GetPrescaler (IWDG_TypeDef *IWDGx)
Get the selected prescaler of the IWDG.
__STATIC_INLINE void | LL_IWDG_SetReloadCounter (IWDG_TypeDef *IWDGx, uint32_t Counter)
Specify the IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_GetReloadCounter (IWDG_TypeDef *IWDGx)
Get the specified IWDG down-counter reload value.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_PVU (IWDG_TypeDef *IWDGx)
Check if flag Prescaler Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsActiveFlag_RVU (IWDG_TypeDef *IWDGx)
Check if flag Reload Value Update is set or not.
__STATIC_INLINE uint32_t | LL_IWDG_IsReady (IWDG_TypeDef *IWDGx)
Check if all flags Prescaler, Reload & Window Value Update are reset or not.

Detailed Description

Header file of IWDG LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_iwdg.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_pwr.h File Reference

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stm32f1xx_ll_pwr.h File Reference

Header file of PWR LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Defines

#define | LL_PWR_CR_CSBF PWR_CR_CSBF
#define | LL_PWR_CR_CWUF PWR_CR_CWUF
#define | LL_PWR_CSR_WUF PWR_CSR_WUF
#define | LL_PWR_CSR_SBF PWR_CSR_SBF
#define | LL_PWR_CSR_PVDO PWR_CSR_PVDO
#define | LL_PWR_CSR_EWUP1 PWR_CSR_EWUP
#define | LL_PWR_MODE_STOP_MAINREGU 0x00000000U
#define | LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS)
#define | LL_PWR_MODE_STANDBY (PWR_CR_PDDS)
#define | LL_PWR_REGU_DSMODE_MAIN 0x00000000U
#define | LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS)
#define | LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0)
#define | LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1)
#define | LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2)
#define | LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3)
#define | LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4)
#define | LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5)
#define | LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6)
#define | LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7)
#define | LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP)
#define | LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
Write a value in PWR register.
#define | LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
Read a value in PWR register.

Functions

__STATIC_INLINE void | LL_PWR_EnableBkUpAccess (void)
Enable access to the backup domain.
__STATIC_INLINE void | LL_PWR_DisableBkUpAccess (void)
Disable access to the backup domain.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledBkUpAccess (void)
Check if the backup domain is enabled.
__STATIC_INLINE void | LL_PWR_SetRegulModeDS (uint32_t RegulMode)
Set voltage Regulator mode during deep sleep mode.
__STATIC_INLINE uint32_t | LL_PWR_GetRegulModeDS (void)
Get voltage Regulator mode during deep sleep mode.
__STATIC_INLINE void | LL_PWR_SetPowerMode (uint32_t PDMode)
Set Power Down mode when CPU enters deepsleep.
__STATIC_INLINE uint32_t | LL_PWR_GetPowerMode (void)
Get Power Down mode when CPU enters deepsleep.
__STATIC_INLINE void | LL_PWR_SetPVDLevel (uint32_t PVDLevel)
Configure the voltage threshold detected by the Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_GetPVDLevel (void)
Get the voltage threshold detection.
__STATIC_INLINE void | LL_PWR_EnablePVD (void)
Enable Power Voltage Detector.
__STATIC_INLINE void | LL_PWR_DisablePVD (void)
Disable Power Voltage Detector.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledPVD (void)
Check if Power Voltage Detector is enabled.
__STATIC_INLINE void | LL_PWR_EnableWakeUpPin (uint32_t WakeUpPin)
Enable the WakeUp PINx functionality.
__STATIC_INLINE void | LL_PWR_DisableWakeUpPin (uint32_t WakeUpPin)
Disable the WakeUp PINx functionality.
__STATIC_INLINE uint32_t | LL_PWR_IsEnabledWakeUpPin (uint32_t WakeUpPin)
Check if the WakeUp PINx functionality is enabled.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_WU (void)
Get Wake-up Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_SB (void)
Get Standby Flag.
__STATIC_INLINE uint32_t | LL_PWR_IsActiveFlag_PVDO (void)
Indicate whether VDD voltage is below the selected PVD threshold.
__STATIC_INLINE void | LL_PWR_ClearFlag_SB (void)
Clear Standby Flag.
__STATIC_INLINE void | LL_PWR_ClearFlag_WU (void)
Clear Wake-up Flags.
ErrorStatus | LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

Header file of PWR LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_pwr.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_rcc.h File Reference

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  • STM32F1xx_HAL_Driver
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Data Structures | Defines | Functions
stm32f1xx_ll_rcc.h File Reference

Header file of RCC LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...

Defines

#define | HSE_VALUE 8000000U
#define | HSI_VALUE 8000000U
#define | LSE_VALUE 32768U
#define | LSI_VALUE 32000U
#define | LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC
#define | LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC
#define | LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC
#define | LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC
#define | LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC
#define | LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC
#define | LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC
#define | LL_RCC_CIR_CSSC RCC_CIR_CSSC
#define | LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF
#define | LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF
#define | LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF
#define | LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF
#define | LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF
#define | LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF
#define | LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF
#define | LL_RCC_CIR_CSSF RCC_CIR_CSSF
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
#define | LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
#define | LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE
#define | LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE
#define | LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE
#define | LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE
#define | LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE
#define | LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE
#define | LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE
#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL
#define | LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
#define | LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
#define | LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
#define | LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
#define | LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
#define | LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
#define | LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
#define | LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512
#define | LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
#define | LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
#define | LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
#define | LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16
#define | LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
#define | LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
#define | LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
#define | LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16
#define | LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
#define | LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
#define | LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI
#define | LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE
#define | LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2
#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
#define | LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE
#define | LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/
#define | LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/
#define | LL_RCC_USB_CLKSOURCE 0x00400000U
#define | LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE
#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
#define | LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL
#define | LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2
#define | LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3
#define | LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4
#define | LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5
#define | LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6
#define | LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7
#define | LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8
#define | LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9
#define | LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10
#define | LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11
#define | LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12
#define | LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13
#define | LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14
#define | LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15
#define | LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16
#define | LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U
#define | LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC
#define | LL_RCC_PLLSOURCE_HSE_DIV_1 RCC_CFGR_PLLSRC
#define | LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)
#define | LL_RCC_PREDIV_DIV_1 0x00000000U
#define | LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE
#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
Write a value in RCC register.
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
Read a value in RCC register.
#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))
Helper macro to calculate the PLLCLK frequency.
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
Helper macro to calculate the HCLK frequency.
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
Helper macro to calculate the PCLK1 frequency (ABP1)
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
Helper macro to calculate the PCLK2 frequency (ABP2)

Functions

__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void)
Enable the Clock Security System.
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void)
Enable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void)
Disable HSE external oscillator (HSE Bypass)
__STATIC_INLINE void | LL_RCC_HSE_Enable (void)
Enable HSE crystal oscillator (HSE ON)
__STATIC_INLINE void | LL_RCC_HSE_Disable (void)
Disable HSE crystal oscillator (HSE ON)
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void)
Check if HSE oscillator Ready.
__STATIC_INLINE void | LL_RCC_HSI_Enable (void)
Enable HSI oscillator.
__STATIC_INLINE void | LL_RCC_HSI_Disable (void)
Disable HSI oscillator.
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void)
Check if HSI clock is ready.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void)
Get HSI Calibration value.
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value)
Set HSI Calibration trimming.
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void)
Get HSI Calibration trimming.
__STATIC_INLINE void | LL_RCC_LSE_Enable (void)
Enable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_Disable (void)
Disable Low Speed External (LSE) crystal.
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void)
Enable external clock source (LSE bypass).
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void)
Disable external clock source (LSE bypass).
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void)
Check if LSE oscillator Ready.
__STATIC_INLINE void | LL_RCC_LSI_Enable (void)
Enable LSI Oscillator.
__STATIC_INLINE void | LL_RCC_LSI_Disable (void)
Disable LSI Oscillator.
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void)
Check if LSI is Ready.
__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source)
Configure the system clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void)
Get the system clock source.
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler)
Set AHB prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler)
Set APB1 prescaler.
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler)
Set APB2 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void)
Get AHB prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void)
Get APB1 prescaler.
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void)
Get APB2 prescaler.
__STATIC_INLINE void | LL_RCC_ConfigMCO (uint32_t MCOxSource)
Configure MCOx.
__STATIC_INLINE void | LL_RCC_SetUSBClockSource (uint32_t USBxSource)
Configure USB clock source.
__STATIC_INLINE void | LL_RCC_SetADCClockSource (uint32_t ADCxSource)
Configure ADC clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetUSBClockSource (uint32_t USBx)
Get USBx clock source.
__STATIC_INLINE uint32_t | LL_RCC_GetADCClockSource (uint32_t ADCx)
Get ADCx clock source.
__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source)
Set RTC Clock Source.
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void)
Get RTC Clock Source.
__STATIC_INLINE void | LL_RCC_EnableRTC (void)
Enable RTC.
__STATIC_INLINE void | LL_RCC_DisableRTC (void)
Disable RTC.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void)
Check if RTC has been enabled or not.
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void)
Force the Backup domain reset.
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void)
Release the Backup domain reset.
__STATIC_INLINE void | LL_RCC_PLL_Enable (void)
Enable PLL.
__STATIC_INLINE void | LL_RCC_PLL_Disable (void)
Disable PLL.
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void)
Check if PLL Ready.
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLMul)
Configure PLL used for SYSCLK Domain.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void)
Get the oscillator used as PLL clock source.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMultiplicator (void)
Get PLL multiplication Factor.
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetPrediv (void)
Get PREDIV1 division factor for the main PLL.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void)
Clear LSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void)
Clear LSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void)
Clear HSI ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void)
Clear HSE ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void)
Clear PLL ready interrupt flag.
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void)
Clear Clock security system interrupt flag.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void)
Check if LSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void)
Check if LSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void)
Check if HSI ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void)
Check if HSE ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void)
Check if PLL ready interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void)
Check if Clock security system interrupt occurred or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void)
Check if RCC flag Independent Watchdog reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void)
Check if RCC flag Low Power reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void)
Check if RCC flag Pin reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PORRST (void)
Check if RCC flag POR/PDR reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void)
Check if RCC flag Software reset is set or not.
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void)
Check if RCC flag Window Watchdog reset is set or not.
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void)
Set RMVF bit to clear the reset flags.
__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void)
Enable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void)
Enable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void)
Enable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void)
Enable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void)
Enable PLL ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void)
Disable LSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void)
Disable LSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void)
Disable HSI ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void)
Disable HSE ready interrupt.
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void)
Disable PLL ready interrupt.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void)
Checks if LSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void)
Checks if LSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void)
Checks if HSI ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void)
Checks if HSE ready interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void)
Checks if PLL ready interrupt source is enabled or disabled.
ErrorStatus | LL_RCC_DeInit (void)
Reset the RCC clock configuration to the default reset state.
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks)
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks.
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource)
Return USBx clock frequency.
uint32_t | LL_RCC_GetADCClockFreq (uint32_t ADCxSource)
Return ADCx clock frequency.

Detailed Description

Header file of RCC LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_rcc.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_spi.h File Reference

  • File List
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Data Structures | Defines | Functions
stm32f1xx_ll_spi.h File Reference

Header file of SPI LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_SPI_InitTypeDef
SPI Init structures definition. More...

Defines

#define | LL_SPI_SR_RXNE SPI_SR_RXNE
#define | LL_SPI_SR_TXE SPI_SR_TXE
#define | LL_SPI_SR_BSY SPI_SR_BSY
#define | LL_SPI_SR_CRCERR SPI_SR_CRCERR
#define | LL_SPI_SR_MODF SPI_SR_MODF
#define | LL_SPI_SR_OVR SPI_SR_OVR
#define | LL_SPI_SR_FRE SPI_SR_FRE
#define | LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
#define | LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
#define | LL_SPI_CR2_ERRIE SPI_CR2_ERRIE
#define | LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
#define | LL_SPI_MODE_SLAVE 0x00000000U
#define | LL_SPI_PHASE_1EDGE 0x00000000U
#define | LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)
#define | LL_SPI_POLARITY_LOW 0x00000000U
#define | LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)
#define | LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
#define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
#define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define | LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
#define | LL_SPI_MSB_FIRST 0x00000000U
#define | LL_SPI_FULL_DUPLEX 0x00000000U
#define | LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
#define | LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
#define | LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)
#define | LL_SPI_NSS_SOFT (SPI_CR1_SSM)
#define | LL_SPI_NSS_HARD_INPUT 0x00000000U
#define | LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))
#define | LL_SPI_DATAWIDTH_8BIT 0x00000000U
#define | LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF)
#define | LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
#define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)
#define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in SPI register.
#define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in SPI register.

Functions

__STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx)
Enable SPI peripheral.
__STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx)
Disable SPI peripheral.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx)
Check if SPI peripheral is enabled.
__STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode)
Set SPI operation mode to Master or Slave.
__STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx)
Get SPI operation mode (Master or Slave)
__STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase)
Set clock phase.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx)
Get clock phase.
__STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity)
Set clock polarity.
__STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx)
Get clock polarity.
__STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t BaudRate)
Set baud rate prescaler.
__STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx)
Get baud rate prescaler.
__STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder)
Set transfer bit order.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx)
Get transfer bit order.
__STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection)
Set transfer direction mode.
__STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx)
Get transfer direction mode.
__STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth)
Set frame data width.
__STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx)
Get frame data width.
__STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx)
Enable CRC.
__STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx)
Disable CRC.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx)
Check if CRC is enabled.
__STATIC_INLINE void | LL_SPI_SetCRCNext (SPI_TypeDef *SPIx)
Set CRCNext to transfer CRC on the line.
__STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly)
Set polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx)
Get polynomial for CRC calculation.
__STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx)
Get Rx CRC.
__STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx)
Get Tx CRC.
__STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS)
Set NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx)
Get NSS mode.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer is not empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer is empty.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx)
Get CRC error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx)
Get mode fault error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx)
Get overrun error flag.
__STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_BSY (SPI_TypeDef *SPIx)
Get busy flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx)
Clear CRC error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx)
Clear mode fault error flag.
__STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx)
Clear overrun error flag.
__STATIC_INLINE void | LL_SPI_EnableIT_ERR (SPI_TypeDef *SPIx)
Enable error interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_RXNE (SPI_TypeDef *SPIx)
Enable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableIT_TXE (SPI_TypeDef *SPIx)
Enable Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_ERR (SPI_TypeDef *SPIx)
Disable error interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_RXNE (SPI_TypeDef *SPIx)
Disable Rx buffer not empty interrupt.
__STATIC_INLINE void | LL_SPI_DisableIT_TXE (SPI_TypeDef *SPIx)
Disable Tx buffer empty interrupt.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_ERR (SPI_TypeDef *SPIx)
Check if error interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXNE (SPI_TypeDef *SPIx)
Check if Rx buffer not empty interrupt is enabled.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXE (SPI_TypeDef *SPIx)
Check if Tx buffer empty interrupt.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx)
Enable DMA Rx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx)
Disable DMA Rx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx)
Check if DMA Rx is enabled.
__STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx)
Enable DMA Tx.
__STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx)
Disable DMA Tx.
__STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx)
Check if DMA Tx is enabled.
__STATIC_INLINE uint32_t | LL_SPI_DMA_GetRegAddr (SPI_TypeDef *SPIx)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx)
Read 8-Bits in the data register.
__STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx)
Read 16-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData)
Write 8-Bits in the data register.
__STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData)
Write 16-Bits in the data register.
ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx)
De-initialize the SPI registers to their default reset values.
ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct)
Set each LL_SPI_InitTypeDef field to default value.

Detailed Description

Header file of SPI LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_spi.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_system.h File Reference

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stm32f1xx_ll_system.h File Reference

Header file of SYSTEM LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Defines

#define | LL_DBGMCU_TRACE_NONE 0x00000000U
#define | LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
#define | LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
#define | LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)
#define | LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP
#define | LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP
#define | LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_CR_DBG_RTC_STOP
#define | LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_STOP
#define | LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_STOP
#define | LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP
#define | LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP
#define | LL_FLASH_LATENCY_0 0x00000000U
#define | LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0
#define | LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1

Functions

__STATIC_INLINE uint32_t | LL_DBGMCU_GetDeviceID (void)
Return the device identifier.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetRevisionID (void)
Return the device revision identifier.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode.
__STATIC_INLINE void | LL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode.
__STATIC_INLINE void | LL_DBGMCU_SetTracePinAssignment (uint32_t PinAssignment)
Set Trace pin assignment control.
__STATIC_INLINE uint32_t | LL_DBGMCU_GetTracePinAssignment (void)
Get Trace pin assignment control.
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB1_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB1 peripherals (group1 peripherals)
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_FreezePeriph (uint32_t Periphs)
Freeze APB2 peripherals.
__STATIC_INLINE void | LL_DBGMCU_APB2_GRP1_UnFreezePeriph (uint32_t Periphs)
Unfreeze APB2 peripherals.
__STATIC_INLINE void | LL_FLASH_SetLatency (uint32_t Latency)
Set FLASH Latency.
__STATIC_INLINE uint32_t | LL_FLASH_GetLatency (void)
Get FLASH Latency.
__STATIC_INLINE void | LL_FLASH_EnablePrefetch (void)
Enable Prefetch.
__STATIC_INLINE void | LL_FLASH_DisablePrefetch (void)
Disable Prefetch.
__STATIC_INLINE uint32_t | LL_FLASH_IsPrefetchEnabled (void)
Check if Prefetch buffer is enabled.
__STATIC_INLINE void | LL_FLASH_EnableHalfCycleAccess (void)
Enable Flash Half Cycle Access.
__STATIC_INLINE void | LL_FLASH_DisableHalfCycleAccess (void)
Disable Flash Half Cycle Access.
__STATIC_INLINE uint32_t | LL_FLASH_IsHalfCycleAccessEnabled (void)
Check if Flash Half Cycle Access is enabled or not.

Detailed Description

Header file of SYSTEM LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL SYSTEM driver contains a set of generic APIs that can be
    used by user:
      (+) Some of the FLASH features need to be handled in the SYSTEM file.
      (+) Access to DBGCMU registers
      (+) Access to SYSCFG registers
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_system.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_tim.h File Reference

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Data Structures | Defines | Functions | Variables
stm32f1xx_ll_tim.h File Reference

Header file of TIM LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...

Defines

#define | DT_DELAY_1 ((uint8_t)0x7FU)
#define | DT_DELAY_2 ((uint8_t)0x3FU)
#define | DT_DELAY_3 ((uint8_t)0x1FU)
#define | DT_DELAY_4 ((uint8_t)0x1FU)
#define | DT_RANGE_1 ((uint8_t)0x00U)
#define | DT_RANGE_2 ((uint8_t)0x80U)
#define | DT_RANGE_3 ((uint8_t)0xC0U)
#define | DT_RANGE_4 ((uint8_t)0xE0U)
#define | TIM_GET_CHANNEL_INDEX(__CHANNEL__)
Convert channel id into channel index.
#define | TIM_CALC_DTS(__TIMCLK__, __CKD__)
Calculate the deadtime sampling period(in ps).
#define | LL_TIM_SR_UIF TIM_SR_UIF
#define | LL_TIM_SR_CC1IF TIM_SR_CC1IF
#define | LL_TIM_SR_CC2IF TIM_SR_CC2IF
#define | LL_TIM_SR_CC3IF TIM_SR_CC3IF
#define | LL_TIM_SR_CC4IF TIM_SR_CC4IF
#define | LL_TIM_SR_COMIF TIM_SR_COMIF
#define | LL_TIM_SR_TIF TIM_SR_TIF
#define | LL_TIM_SR_BIF TIM_SR_BIF
#define | LL_TIM_SR_CC1OF TIM_SR_CC1OF
#define | LL_TIM_SR_CC2OF TIM_SR_CC2OF
#define | LL_TIM_SR_CC3OF TIM_SR_CC3OF
#define | LL_TIM_SR_CC4OF TIM_SR_CC4OF
#define | LL_TIM_BREAK_DISABLE 0x00000000U
#define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE
#define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
#define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
#define | LL_TIM_DIER_UIE TIM_DIER_UIE
#define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
#define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
#define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
#define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
#define | LL_TIM_DIER_COMIE TIM_DIER_COMIE
#define | LL_TIM_DIER_TIE TIM_DIER_TIE
#define | LL_TIM_DIER_BIE TIM_DIER_BIE
#define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U
#define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS
#define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM
#define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U
#define | LL_TIM_COUNTERMODE_UP 0x00000000U
#define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0
#define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1
#define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS
#define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U
#define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
#define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
#define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U
#define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR
#define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U
#define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS
#define | LL_TIM_CCDMAREQUEST_CC 0x00000000U
#define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS
#define | LL_TIM_LOCKLEVEL_OFF 0x00000000U
#define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
#define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
#define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
#define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E
#define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE
#define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E
#define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE
#define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E
#define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE
#define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E
#define | LL_TIM_OCSTATE_DISABLE 0x00000000U
#define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E
#define | LL_TIM_OCMODE_FROZEN 0x00000000U
#define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
#define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
#define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
#define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
#define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
#define | LL_TIM_OCPOLARITY_HIGH 0x00000000U
#define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P
#define | LL_TIM_OCIDLESTATE_LOW 0x00000000U
#define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1
#define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U)
#define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U)
#define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U)
#define | LL_TIM_ICPSC_DIV1 0x00000000U
#define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U)
#define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U)
#define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U)
#define | LL_TIM_IC_FILTER_FDIV1 0x00000000U
#define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U)
#define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U)
#define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U)
#define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)
#define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U)
#define | LL_TIM_IC_POLARITY_RISING 0x00000000U
#define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P
#define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U
#define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE
#define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0
#define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1
#define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
#define | LL_TIM_TRGO_RESET 0x00000000U
#define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0
#define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1
#define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2
#define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
#define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
#define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
#define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U
#define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
#define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
#define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
#define | LL_TIM_TS_ITR0 0x00000000U
#define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0
#define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1
#define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2
#define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)
#define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)
#define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)
#define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U
#define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP
#define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U
#define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0
#define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1
#define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS
#define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U
#define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0
#define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1
#define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2
#define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3
#define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)
#define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)
#define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)
#define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF
#define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U
#define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP
#define | LL_TIM_OSSI_DISABLE 0x00000000U
#define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI
#define | LL_TIM_OSSR_DISABLE 0x00000000U
#define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR
#define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U
#define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0
#define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1
#define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2
#define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3
#define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)
#define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)
#define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4
#define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)
#define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U
#define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0
#define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1
#define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2
#define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3
#define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)
#define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)
#define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)
#define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4
#define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0)
#define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in TIM register.
#define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in TIM register.
#define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)
HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
#define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
#define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
#define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)
HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
#define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)
HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
#define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
HELPER macro retrieving the ratio of the input capture prescaler.

Functions

__STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx)
Enable timer counter.
__STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx)
Disable timer counter.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx)
Indicates whether the timer counter is enabled.
__STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx)
Enable update event generation.
__STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx)
Disable update event generation.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx)
Indicates whether update event generation is enabled.
__STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource)
Set update event source.
__STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx)
Get actual event update source.
__STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode)
Set one pulse mode (one shot v.s.
__STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx)
Get actual one pulse mode.
__STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode)
Set the timer counter counting mode.
__STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx)
Get actual counter mode.
__STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx)
Enable auto-reload (ARR) preload.
__STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx)
Disable auto-reload (ARR) preload.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx)
Indicates whether auto-reload (ARR) preload is enabled.
__STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision)
Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx)
Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
__STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter)
Set the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx)
Get the counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx)
Get the current direction of the counter.
__STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler)
Set the prescaler value.
__STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx)
Get the prescaler value.
__STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload)
Set the auto-reload value.
__STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx)
Get the auto-reload value.
__STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
Set the repetition counter value.
__STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx)
Get the repetition counter value.
__STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx)
Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx)
Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
__STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
__STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
Set the trigger of the capture/compare DMA request.
__STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx)
Get actual trigger of the capture/compare DMA request.
__STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel)
Set the lock level to freeze the configuration of several capture/compare parameters.
__STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Enable capture/compare channels.
__STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Disable capture/compare channels.
__STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels)
Indicate whether channel(s) is(are) enabled.
__STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel)
Get the output compare mode of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
Set the polarity of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the polarity of an output channel.
__STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
Set the IDLE state of an output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel)
Get the IDLE state of an output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Enable fast mode for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel)
Disable fast mode for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether fast mode is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Enable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel)
Disable compare register (TIMx_CCRx) preload for the output channel.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Enable clearing the output channel on an external event.
__STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel)
Disable clearing the output channel on an external event.
__STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel)
Indicates clearing the output channel on an external event is enabled for the output channel.
__STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime)
Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 1 (TIMx_CCR1).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 2 (TIMx_CCR2).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 3 (TIMx_CCR3).
__STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue)
Set compare value for output channel 4 (TIMx_CCR4).
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR1) set for output channel 1.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR2) set for output channel 2.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR3) set for output channel 3.
__STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx)
Get compare value (TIMx_CCR4) set for output channel 4.
__STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
Configure input channel.
__STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
Set the active input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current active input.
__STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
Set the prescaler of input channel.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current prescaler value acting on an input channel.
__STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
Set the input filter duration.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel)
Get the input filter duration.
__STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
Set the input channel polarity.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel)
Get the current input channel polarity.
__STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx)
Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
__STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx)
Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx)
Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx)
Get captured value for input channel 1.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx)
Get captured value for input channel 2.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx)
Get captured value for input channel 3.
__STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx)
Get captured value for input channel 4.
__STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx)
Enable external clock mode 2.
__STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx)
Disable external clock mode 2.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx)
Indicate whether external clock mode 2 is enabled.
__STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource)
Set the clock source of the counter clock.
__STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode)
Set the encoder interface mode.
__STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
Set the trigger output (TRGO) used for timer synchronization .
__STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode)
Set the synchronization mode of a slave timer.
__STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput)
Set the selects the trigger input to be used to synchronize the counter.
__STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx)
Enable the Master/Slave mode.
__STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx)
Disable the Master/Slave mode.
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx)
Indicates whether the Master/Slave mode is enabled.
__STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
Configure the external trigger (ETR) input.
__STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx)
Enable the break function.
__STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx)
Disable the break function.
__STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity)
Configure the break input.
__STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
Select the outputs off state (enabled v.s.
__STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx)
Enable automatic output (MOE can be set by software or automatically when a break input is active).
__STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx)
Disable automatic output (MOE can be set only by software).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx)
Indicate whether automatic output is enabled.
__STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx)
Enable the outputs (set the MOE bit in TIMx_BDTR register).
__STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx)
Disable the outputs (reset the MOE bit in TIMx_BDTR register).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx)
Indicates whether outputs are enabled.
__STATIC_INLINE void | LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
Configures the timer DMA burst feature.
__STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx)
Clear the update interrupt flag (UIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx)
Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 interrupt flag (CC1F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 interrupt flag (CC2F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 interrupt flag (CC3F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 interrupt flag (CC4F).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx)
Clear the commutation interrupt flag (COMIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx)
Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx)
Clear the trigger interrupt flag (TIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx)
Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx)
Clear the break interrupt flag (BIF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx)
Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx)
Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
__STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx)
Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
__STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx)
Enable update interrupt (UIE).
__STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx)
Disable update interrupt (UIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update interrupt (UIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 interrupt (CC1IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 interrupt (CC2IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 interrupt (CC3IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 interrupt (CC4IE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx)
Enable commutation interrupt (COMIE).
__STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx)
Disable commutation interrupt (COMIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation interrupt (COMIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TIE).
__STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx)
Enable break interrupt (BIE).
__STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx)
Disable break interrupt (BIE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx)
Indicates whether the break interrupt (BIE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Enable update DMA request (UDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx)
Disable update DMA request (UDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx)
Indicates whether the update DMA request (UDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx)
Enable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx)
Disable capture/compare 1 DMA request (CC1DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx)
Enable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx)
Disable capture/compare 2 DMA request (CC2DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx)
Enable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx)
Disable capture/compare 3 DMA request (CC3DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx)
Enable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx)
Disable capture/compare 4 DMA request (CC4DE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx)
Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx)
Enable commutation DMA request (COMDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx)
Disable commutation DMA request (COMDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx)
Indicates whether the commutation DMA request (COMDE) is enabled.
__STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx)
Enable trigger interrupt (TDE).
__STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx)
Disable trigger interrupt (TDE).
__STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx)
Indicates whether the trigger interrupt (TDE) is enabled.
__STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx)
Generate an update event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx)
Generate Capture/Compare 1 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx)
Generate Capture/Compare 2 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx)
Generate Capture/Compare 3 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx)
Generate Capture/Compare 4 event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx)
Generate commutation event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx)
Generate trigger event.
__STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx)
Generate break event.
ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx)
Set TIMx registers to their reset values.
void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct)
Set the fields of the time base unit configuration data structure to their default values.
ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
Configure the TIMx time base unit.
void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Set the fields of the TIMx output channel configuration data structure to their default values.
ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
Configure the TIMx output channel.
void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
Set the fields of the TIMx input channel configuration data structure to their default values.
ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
Configure the TIMx input channel.
void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Fills each TIM_EncoderInitStruct field with its default value.
ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
Configure the encoder interface of the timer instance.
void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Set the fields of the TIMx Hall sensor interface configuration data structure to their default values.
ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
Configure the Hall sensor interface of the timer instance.
void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Set the fields of the Break and Dead Time configuration data structure to their default values.
ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
Configure the Break and Dead Time feature of the timer instance.

Variables

static const uint8_t | OFFSET_TAB_CCMRx []
static const uint8_t | SHIFT_TAB_OCxx []
static const uint8_t | SHIFT_TAB_ICxx []
static const uint8_t | SHIFT_TAB_CCxP []
static const uint8_t | SHIFT_TAB_OISx []

Detailed Description

Header file of TIM LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_tim.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_usart.h File Reference

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Data Structures | Defines | Functions
stm32f1xx_ll_usart.h File Reference

Header file of USART LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...

Defines

#define | USART_POSITION_GTPR_GT USART_GTPR_GT_Pos
#define | LL_USART_SR_PE USART_SR_PE
#define | LL_USART_SR_FE USART_SR_FE
#define | LL_USART_SR_NE USART_SR_NE
#define | LL_USART_SR_ORE USART_SR_ORE
#define | LL_USART_SR_IDLE USART_SR_IDLE
#define | LL_USART_SR_RXNE USART_SR_RXNE
#define | LL_USART_SR_TC USART_SR_TC
#define | LL_USART_SR_TXE USART_SR_TXE
#define | LL_USART_SR_LBD USART_SR_LBD
#define | LL_USART_SR_CTS USART_SR_CTS
#define | LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
#define | LL_USART_CR1_RXNEIE USART_CR1_RXNEIE
#define | LL_USART_CR1_TCIE USART_CR1_TCIE
#define | LL_USART_CR1_TXEIE USART_CR1_TXEIE
#define | LL_USART_CR1_PEIE USART_CR1_PEIE
#define | LL_USART_CR2_LBDIE USART_CR2_LBDIE
#define | LL_USART_CR3_EIE USART_CR3_EIE
#define | LL_USART_CR3_CTSIE USART_CR3_CTSIE
#define | LL_USART_DIRECTION_NONE 0x00000000U
#define | LL_USART_DIRECTION_RX USART_CR1_RE
#define | LL_USART_DIRECTION_TX USART_CR1_TE
#define | LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
#define | LL_USART_PARITY_NONE 0x00000000U
#define | LL_USART_PARITY_EVEN USART_CR1_PCE
#define | LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define | LL_USART_WAKEUP_IDLELINE 0x00000000U
#define | LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
#define | LL_USART_DATAWIDTH_8B 0x00000000U
#define | LL_USART_DATAWIDTH_9B USART_CR1_M
#define | LL_USART_CLOCK_DISABLE 0x00000000U
#define | LL_USART_CLOCK_ENABLE USART_CR2_CLKEN
#define | LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
#define | LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL
#define | LL_USART_PHASE_1EDGE 0x00000000U
#define | LL_USART_PHASE_2EDGE USART_CR2_CPHA
#define | LL_USART_POLARITY_LOW 0x00000000U
#define | LL_USART_POLARITY_HIGH USART_CR2_CPOL
#define | LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
#define | LL_USART_STOPBITS_1 0x00000000U
#define | LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define | LL_USART_STOPBITS_2 USART_CR2_STOP_1
#define | LL_USART_HWCONTROL_NONE 0x00000000U
#define | LL_USART_HWCONTROL_RTS USART_CR3_RTSE
#define | LL_USART_HWCONTROL_CTS USART_CR3_CTSE
#define | LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define | LL_USART_IRDA_POWER_NORMAL 0x00000000U
#define | LL_USART_IRDA_POWER_LOW USART_CR3_IRLP
#define | LL_USART_LINBREAK_DETECT_10B 0x00000000U
#define | LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL
#define | LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in USART register.
#define | LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in USART register.
#define | __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
#define | __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
#define | __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)
#define | __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
Compute USARTDIV value according to Peripheral Clock and expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
#define | __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
#define | __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
#define | __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)

Functions

__STATIC_INLINE void | LL_USART_Enable (USART_TypeDef *USARTx)
USART Enable.
__STATIC_INLINE void | LL_USART_Disable (USART_TypeDef *USARTx)
USART Disable (all USART prescalers and outputs are disabled)
__STATIC_INLINE uint32_t | LL_USART_IsEnabled (USART_TypeDef *USARTx)
Indicate if USART is enabled.
__STATIC_INLINE void | LL_USART_EnableDirectionRx (USART_TypeDef *USARTx)
Receiver Enable (Receiver is enabled and begins searching for a start bit)
__STATIC_INLINE void | LL_USART_DisableDirectionRx (USART_TypeDef *USARTx)
Receiver Disable.
__STATIC_INLINE void | LL_USART_EnableDirectionTx (USART_TypeDef *USARTx)
Transmitter Enable.
__STATIC_INLINE void | LL_USART_DisableDirectionTx (USART_TypeDef *USARTx)
Transmitter Disable.
__STATIC_INLINE void | LL_USART_SetTransferDirection (USART_TypeDef *USARTx, uint32_t TransferDirection)
Configure simultaneously enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE uint32_t | LL_USART_GetTransferDirection (USART_TypeDef *USARTx)
Return enabled/disabled states of Transmitter and Receiver.
__STATIC_INLINE void | LL_USART_SetParity (USART_TypeDef *USARTx, uint32_t Parity)
Configure Parity (enabled/disabled and parity mode if enabled).
__STATIC_INLINE uint32_t | LL_USART_GetParity (USART_TypeDef *USARTx)
Return Parity configuration (enabled/disabled and parity mode if enabled)
__STATIC_INLINE void | LL_USART_SetWakeUpMethod (USART_TypeDef *USARTx, uint32_t Method)
Set Receiver Wake Up method from Mute mode.
__STATIC_INLINE uint32_t | LL_USART_GetWakeUpMethod (USART_TypeDef *USARTx)
Return Receiver Wake Up method from Mute mode.
__STATIC_INLINE void | LL_USART_SetDataWidth (USART_TypeDef *USARTx, uint32_t DataWidth)
Set Word length (i.e.
__STATIC_INLINE uint32_t | LL_USART_GetDataWidth (USART_TypeDef *USARTx)
Return Word length (i.e.
__STATIC_INLINE void | LL_USART_SetLastClkPulseOutput (USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
Configure if Clock pulse of the last data bit is output to the SCLK pin or not.
__STATIC_INLINE uint32_t | LL_USART_GetLastClkPulseOutput (USART_TypeDef *USARTx)
Retrieve Clock pulse of the last data bit output configuration (Last bit Clock pulse output to the SCLK pin or not)
__STATIC_INLINE void | LL_USART_SetClockPhase (USART_TypeDef *USARTx, uint32_t ClockPhase)
Select the phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPhase (USART_TypeDef *USARTx)
Return phase of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_SetClockPolarity (USART_TypeDef *USARTx, uint32_t ClockPolarity)
Select the polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE uint32_t | LL_USART_GetClockPolarity (USART_TypeDef *USARTx)
Return polarity of the clock output on the SCLK pin in synchronous mode.
__STATIC_INLINE void | LL_USART_ConfigClock (USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
__STATIC_INLINE void | LL_USART_EnableSCLKOutput (USART_TypeDef *USARTx)
Enable Clock output on SCLK pin.
__STATIC_INLINE void | LL_USART_DisableSCLKOutput (USART_TypeDef *USARTx)
Disable Clock output on SCLK pin.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSCLKOutput (USART_TypeDef *USARTx)
Indicate if Clock output on SCLK pin is enabled.
__STATIC_INLINE void | LL_USART_SetStopBitsLength (USART_TypeDef *USARTx, uint32_t StopBits)
Set the length of the stop bits.
__STATIC_INLINE uint32_t | LL_USART_GetStopBitsLength (USART_TypeDef *USARTx)
Retrieve the length of the stop bits.
__STATIC_INLINE void | LL_USART_ConfigCharacter (USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, uint32_t StopBits)
Configure Character frame format (Datawidth, Parity control, Stop Bits)
__STATIC_INLINE void | LL_USART_SetNodeAddress (USART_TypeDef *USARTx, uint32_t NodeAddress)
Set Address of the USART node.
__STATIC_INLINE uint32_t | LL_USART_GetNodeAddress (USART_TypeDef *USARTx)
Return 4 bit Address of the USART node as set in ADD field of CR2.
__STATIC_INLINE void | LL_USART_EnableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableRTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable RTS HW Flow Control.
__STATIC_INLINE void | LL_USART_EnableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Enable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_DisableCTSHWFlowCtrl (USART_TypeDef *USARTx)
Disable CTS HW Flow Control.
__STATIC_INLINE void | LL_USART_SetHWFlowCtrl (USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
Configure HW Flow Control mode (both CTS and RTS)
__STATIC_INLINE uint32_t | LL_USART_GetHWFlowCtrl (USART_TypeDef *USARTx)
Return HW Flow Control configuration (both CTS and RTS)
__STATIC_INLINE void | LL_USART_SetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaudRate)
Configure USART BRR register for achieving expected Baud Rate value.
__STATIC_INLINE uint32_t | LL_USART_GetBaudRate (USART_TypeDef *USARTx, uint32_t PeriphClk)
Return current Baud Rate value, according to USARTDIV present in BRR register (full BRR content), and to used Peripheral Clock and Oversampling mode values.
__STATIC_INLINE void | LL_USART_EnableIrda (USART_TypeDef *USARTx)
Enable IrDA mode.
__STATIC_INLINE void | LL_USART_DisableIrda (USART_TypeDef *USARTx)
Disable IrDA mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIrda (USART_TypeDef *USARTx)
Indicate if IrDA mode is enabled.
__STATIC_INLINE void | LL_USART_SetIrdaPowerMode (USART_TypeDef *USARTx, uint32_t PowerMode)
Configure IrDA Power Mode (Normal or Low Power)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPowerMode (USART_TypeDef *USARTx)
Retrieve IrDA Power Mode configuration (Normal or Low Power)
__STATIC_INLINE void | LL_USART_SetIrdaPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetIrdaPrescaler (USART_TypeDef *USARTx)
Return Irda prescaler value, used for dividing the USART clock source to achieve the Irda Low Power frequency (8 bits value)
__STATIC_INLINE void | LL_USART_EnableSmartcardNACK (USART_TypeDef *USARTx)
Enable Smartcard NACK transmission.
__STATIC_INLINE void | LL_USART_DisableSmartcardNACK (USART_TypeDef *USARTx)
Disable Smartcard NACK transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcardNACK (USART_TypeDef *USARTx)
Indicate if Smartcard NACK transmission is enabled.
__STATIC_INLINE void | LL_USART_EnableSmartcard (USART_TypeDef *USARTx)
Enable Smartcard mode.
__STATIC_INLINE void | LL_USART_DisableSmartcard (USART_TypeDef *USARTx)
Disable Smartcard mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledSmartcard (USART_TypeDef *USARTx)
Indicate if Smartcard mode is enabled.
__STATIC_INLINE void | LL_USART_SetSmartcardPrescaler (USART_TypeDef *USARTx, uint32_t PrescalerValue)
Set Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardPrescaler (USART_TypeDef *USARTx)
Return Smartcard prescaler value, used for dividing the USART clock source to provide the SMARTCARD Clock (5 bits value)
__STATIC_INLINE void | LL_USART_SetSmartcardGuardTime (USART_TypeDef *USARTx, uint32_t GuardTime)
Set Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE uint32_t | LL_USART_GetSmartcardGuardTime (USART_TypeDef *USARTx)
Return Smartcard Guard time value, expressed in nb of baud clocks periods (GT[7:0] bits : Guard time value)
__STATIC_INLINE void | LL_USART_EnableHalfDuplex (USART_TypeDef *USARTx)
Enable Single Wire Half-Duplex mode.
__STATIC_INLINE void | LL_USART_DisableHalfDuplex (USART_TypeDef *USARTx)
Disable Single Wire Half-Duplex mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledHalfDuplex (USART_TypeDef *USARTx)
Indicate if Single Wire Half-Duplex mode is enabled.
__STATIC_INLINE void | LL_USART_SetLINBrkDetectionLen (USART_TypeDef *USARTx, uint32_t LINBDLength)
Set LIN Break Detection Length.
__STATIC_INLINE uint32_t | LL_USART_GetLINBrkDetectionLen (USART_TypeDef *USARTx)
Return LIN Break Detection Length.
__STATIC_INLINE void | LL_USART_EnableLIN (USART_TypeDef *USARTx)
Enable LIN mode.
__STATIC_INLINE void | LL_USART_DisableLIN (USART_TypeDef *USARTx)
Disable LIN mode.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledLIN (USART_TypeDef *USARTx)
Indicate if LIN mode is enabled.
__STATIC_INLINE void | LL_USART_ConfigAsyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
__STATIC_INLINE void | LL_USART_ConfigSyncMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Synchronous Mode.
__STATIC_INLINE void | LL_USART_ConfigLINMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in LIN Mode.
__STATIC_INLINE void | LL_USART_ConfigHalfDuplexMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Half Duplex Mode.
__STATIC_INLINE void | LL_USART_ConfigSmartcardMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Smartcard Mode.
__STATIC_INLINE void | LL_USART_ConfigIrdaMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Irda Mode.
__STATIC_INLINE void | LL_USART_ConfigMultiProcessMode (USART_TypeDef *USARTx)
Perform basic configuration of USART for enabling use in Multi processor Mode (several USARTs connected in a network, one of the USARTs can be the master, its TX output connected to the RX inputs of the other slaves USARTs).
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_FE (USART_TypeDef *USARTx)
Check if the USART Framing Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_NE (USART_TypeDef *USARTx)
Check if the USART Noise error detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_ORE (USART_TypeDef *USARTx)
Check if the USART OverRun Error Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE line detected Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RXNE (USART_TypeDef *USARTx)
Check if the USART Read Data Register Not Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_TXE (USART_TypeDef *USARTx)
Check if the USART Transmit Data Register Empty Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_nCTS (USART_TypeDef *USARTx)
Check if the USART CTS Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_SBK (USART_TypeDef *USARTx)
Check if the USART Send Break Flag is set or not.
__STATIC_INLINE uint32_t | LL_USART_IsActiveFlag_RWU (USART_TypeDef *USARTx)
Check if the USART Receive Wake Up from mute mode Flag is set or not.
__STATIC_INLINE void | LL_USART_ClearFlag_PE (USART_TypeDef *USARTx)
Clear Parity Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_FE (USART_TypeDef *USARTx)
Clear Framing Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_NE (USART_TypeDef *USARTx)
Clear Noise detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_ORE (USART_TypeDef *USARTx)
Clear OverRun Error Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_IDLE (USART_TypeDef *USARTx)
Clear IDLE line detected Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_TC (USART_TypeDef *USARTx)
Clear Transmission Complete Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_RXNE (USART_TypeDef *USARTx)
Clear RX Not Empty Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_LBD (USART_TypeDef *USARTx)
Clear LIN Break Detection Flag.
__STATIC_INLINE void | LL_USART_ClearFlag_nCTS (USART_TypeDef *USARTx)
Clear CTS Interrupt Flag.
__STATIC_INLINE void | LL_USART_EnableIT_IDLE (USART_TypeDef *USARTx)
Enable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_RXNE (USART_TypeDef *USARTx)
Enable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TC (USART_TypeDef *USARTx)
Enable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_TXE (USART_TypeDef *USARTx)
Enable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_PE (USART_TypeDef *USARTx)
Enable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_LBD (USART_TypeDef *USARTx)
Enable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_ERROR (USART_TypeDef *USARTx)
Enable Error Interrupt.
__STATIC_INLINE void | LL_USART_EnableIT_CTS (USART_TypeDef *USARTx)
Enable CTS Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_IDLE (USART_TypeDef *USARTx)
Disable IDLE Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_RXNE (USART_TypeDef *USARTx)
Disable RX Not Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TC (USART_TypeDef *USARTx)
Disable Transmission Complete Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_TXE (USART_TypeDef *USARTx)
Disable TX Empty Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_PE (USART_TypeDef *USARTx)
Disable Parity Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_LBD (USART_TypeDef *USARTx)
Disable LIN Break Detection Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_ERROR (USART_TypeDef *USARTx)
Disable Error Interrupt.
__STATIC_INLINE void | LL_USART_DisableIT_CTS (USART_TypeDef *USARTx)
Disable CTS Interrupt.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_IDLE (USART_TypeDef *USARTx)
Check if the USART IDLE Interrupt source is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_RXNE (USART_TypeDef *USARTx)
Check if the USART RX Not Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TC (USART_TypeDef *USARTx)
Check if the USART Transmission Complete Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_TXE (USART_TypeDef *USARTx)
Check if the USART TX Empty Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_PE (USART_TypeDef *USARTx)
Check if the USART Parity Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_LBD (USART_TypeDef *USARTx)
Check if the USART LIN Break Detection Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_ERROR (USART_TypeDef *USARTx)
Check if the USART Error Interrupt is enabled or disabled.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledIT_CTS (USART_TypeDef *USARTx)
Check if the USART CTS Interrupt is enabled or disabled.
__STATIC_INLINE void | LL_USART_EnableDMAReq_RX (USART_TypeDef *USARTx)
Enable DMA Mode for reception.
__STATIC_INLINE void | LL_USART_DisableDMAReq_RX (USART_TypeDef *USARTx)
Disable DMA Mode for reception.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_RX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for reception.
__STATIC_INLINE void | LL_USART_EnableDMAReq_TX (USART_TypeDef *USARTx)
Enable DMA Mode for transmission.
__STATIC_INLINE void | LL_USART_DisableDMAReq_TX (USART_TypeDef *USARTx)
Disable DMA Mode for transmission.
__STATIC_INLINE uint32_t | LL_USART_IsEnabledDMAReq_TX (USART_TypeDef *USARTx)
Check if DMA Mode is enabled for transmission.
__STATIC_INLINE uint32_t | LL_USART_DMA_GetRegAddr (USART_TypeDef *USARTx)
Get the data register address used for DMA transfer.
__STATIC_INLINE uint8_t | LL_USART_ReceiveData8 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 8 bits)
__STATIC_INLINE uint16_t | LL_USART_ReceiveData9 (USART_TypeDef *USARTx)
Read Receiver Data register (Receive Data value, 9 bits)
__STATIC_INLINE void | LL_USART_TransmitData8 (USART_TypeDef *USARTx, uint8_t Value)
Write in Transmitter Data Register (Transmit Data value, 8 bits)
__STATIC_INLINE void | LL_USART_TransmitData9 (USART_TypeDef *USARTx, uint16_t Value)
Write in Transmitter Data Register (Transmit Data value, 9 bits)
__STATIC_INLINE void | LL_USART_RequestBreakSending (USART_TypeDef *USARTx)
Request Break sending.
__STATIC_INLINE void | LL_USART_RequestEnterMuteMode (USART_TypeDef *USARTx)
Put USART in Mute mode.
__STATIC_INLINE void | LL_USART_RequestExitMuteMode (USART_TypeDef *USARTx)
Put USART in Active mode.
ErrorStatus | LL_USART_DeInit (USART_TypeDef *USARTx)
De-initialize USART registers (Registers restored to their default values).
ErrorStatus | LL_USART_Init (USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
Initialize USART registers according to the specified parameters in USART_InitStruct.
void | LL_USART_StructInit (LL_USART_InitTypeDef *USART_InitStruct)
Set each LL_USART_InitTypeDef field to default value.
ErrorStatus | LL_USART_ClockInit (USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Initialize USART Clock related settings according to the specified parameters in the USART_ClockInitStruct.
void | LL_USART_ClockStructInit (LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
Set each field of a LL_USART_ClockInitTypeDef type structure to default value.

Detailed Description

Header file of USART LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_usart.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_utils.h File Reference

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Data Structures | Defines | Functions
stm32f1xx_ll_utils.h File Reference

Header file of UTILS LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...

Defines

#define | LL_MAX_DELAY 0xFFFFFFFFU
#define | UID_BASE_ADDRESS UID_BASE
Unique device ID register base address.
#define | FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
Flash size data register base address.
#define | LL_UTILS_HSEBYPASS_OFF 0x00000000U
#define | LL_UTILS_HSEBYPASS_ON 0x00000001U

Functions

__STATIC_INLINE uint32_t | LL_GetUID_Word0 (void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word1 (void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetUID_Word2 (void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t | LL_GetFlashSize (void)
Get Flash memory size.
__STATIC_INLINE void | LL_InitTick (uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
void | LL_Init1msTick (uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void | LL_mDelay (uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
void | LL_SetSystemCoreClock (uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus | LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSI as clock source of the PLL.
ErrorStatus | LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.

Detailed Description

Header file of UTILS LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The LL UTILS driver contains a set of generic APIs that can be
    used by user:
      (+) Device electronic signature
      (+) Timing functions
      (+) PLL configuration functions
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_utils.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_wwdg.h File Reference

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stm32f1xx_ll_wwdg.h File Reference

Header file of WWDG LL module. More...

#include "stm32f1xx.h"

Go to the source code of this file.

Defines

#define | LL_WWDG_CFR_EWI WWDG_CFR_EWI
#define | LL_WWDG_PRESCALER_1 0x00000000U
#define | LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0
#define | LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1
#define | LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)
#define | LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
Write a value in WWDG register.
#define | LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
Read a value in WWDG register.

Functions

__STATIC_INLINE void | LL_WWDG_Enable (WWDG_TypeDef *WWDGx)
Enable Window Watchdog.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabled (WWDG_TypeDef *WWDGx)
Checks if Window Watchdog is enabled.
__STATIC_INLINE void | LL_WWDG_SetCounter (WWDG_TypeDef *WWDGx, uint32_t Counter)
Set the Watchdog counter value to provided value (7-bits T[6:0])
__STATIC_INLINE uint32_t | LL_WWDG_GetCounter (WWDG_TypeDef *WWDGx)
Return current Watchdog Counter Value (7 bits counter value)
__STATIC_INLINE void | LL_WWDG_SetPrescaler (WWDG_TypeDef *WWDGx, uint32_t Prescaler)
Set the time base of the prescaler (WDGTB).
__STATIC_INLINE uint32_t | LL_WWDG_GetPrescaler (WWDG_TypeDef *WWDGx)
Return current Watchdog Prescaler Value.
__STATIC_INLINE void | LL_WWDG_SetWindow (WWDG_TypeDef *WWDGx, uint32_t Window)
Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
__STATIC_INLINE uint32_t | LL_WWDG_GetWindow (WWDG_TypeDef *WWDGx)
Return current Watchdog Window Value (7 bits value)
__STATIC_INLINE uint32_t | LL_WWDG_IsActiveFlag_EWKUP (WWDG_TypeDef *WWDGx)
Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
__STATIC_INLINE void | LL_WWDG_ClearFlag_EWKUP (WWDG_TypeDef *WWDGx)
Clear WWDG Early Wakeup Interrupt Flag (EWIF)
__STATIC_INLINE void | LL_WWDG_EnableIT_EWKUP (WWDG_TypeDef *WWDGx)
Enable the Early Wakeup Interrupt.
__STATIC_INLINE uint32_t | LL_WWDG_IsEnabledIT_EWKUP (WWDG_TypeDef *WWDGx)
Check if Early Wakeup Interrupt is enabled.

Detailed Description

Header file of WWDG LL module.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_wwdg.h.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal.c File Reference

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  • STM32F1xx_HAL_Driver
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Defines | Functions | Variables
stm32f1xx_hal.c File Reference

HAL module driver. This is the common part of the HAL initialization. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | __STM32F1xx_HAL_VERSION_MAIN (0x01U)
STM32F1xx HAL Driver version number.
#define | __STM32F1xx_HAL_VERSION_SUB1 (0x00U)
#define | __STM32F1xx_HAL_VERSION_SUB2 (0x05U)
#define | __STM32F1xx_HAL_VERSION_RC (0x00U)
#define | __STM32F1xx_HAL_VERSION
#define | IDCODE_DEVID_MASK 0x00000FFFU

Functions

HAL_StatusTypeDef | HAL_Init (void)
This function is used to initialize the HAL Library; it must be the first instruction to be executed in the main program (before to call any other HAL function), it performs the following: Configure the Flash prefetch.
HAL_StatusTypeDef | HAL_DeInit (void)
This function de-Initializes common part of the HAL and stops the source of time base.
__weak void | HAL_MspInit (void)
Initializes the MSP.
__weak void | HAL_MspDeInit (void)
DeInitializes the MSP.
__weak HAL_StatusTypeDef | HAL_InitTick (uint32_t TickPriority)
This function configures the source of the time base.
__weak void | HAL_IncTick (void)
This function is called to increment a global variable "uwTick" used as application time base.
__weak uint32_t | HAL_GetTick (void)
Provides a tick value in millisecond.
__weak void | HAL_Delay (__IO uint32_t Delay)
This function provides minimum delay (in milliseconds) based on variable incremented.
__weak void | HAL_SuspendTick (void)
Suspend Tick increment.
__weak void | HAL_ResumeTick (void)
Resume Tick increment.
uint32_t | HAL_GetHalVersion (void)
Returns the HAL revision.
uint32_t | HAL_GetREVID (void)
Returns the device revision identifier.
uint32_t | HAL_GetDEVID (void)
Returns the device identifier.
void | HAL_DBGMCU_EnableDBGSleepMode (void)
Enable the Debug Module during SLEEP mode.
void | HAL_DBGMCU_DisableDBGSleepMode (void)
Disable the Debug Module during SLEEP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_EnableDBGStopMode (void)
Enable the Debug Module during STOP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_DisableDBGStopMode (void)
Disable the Debug Module during STOP mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_EnableDBGStandbyMode (void)
Enable the Debug Module during STANDBY mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_DBGMCU_DisableDBGStandbyMode (void)
Disable the Debug Module during STANDBY mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).
void | HAL_GetUID (uint32_t *UID)
Return the unique device identifier (UID based on 96 bits)

Variables

__IO uint32_t | uwTick

Detailed Description

HAL module driver. This is the common part of the HAL initialization.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
    The common HAL driver contains a set of generic and common APIs that can be
    used by the PPP peripheral drivers and the user to start using the HAL.
    [..]
    The HAL contains two APIs' categories:
         (+) Common HAL APIs
         (+) Services HAL APIs
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_adc.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_hal_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Channels configuration on injected group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32f1xx_hal_adc_ex.c". More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_ENABLE_TIMEOUT 2U
#define | ADC_DISABLE_TIMEOUT 2U
#define | ADC_STAB_DELAY_US 1U
#define | ADC_TEMPSENSOR_DELAY_US 10U

Functions

HAL_StatusTypeDef | HAL_ADC_Init (ADC_HandleTypeDef *hadc)
Initializes the ADC peripheral and regular group according to parameters specified in structure "ADC_InitTypeDef".
HAL_StatusTypeDef | HAL_ADC_DeInit (ADC_HandleTypeDef *hadc)
Deinitialize the ADC peripheral registers to their default reset values, with deinitialization of the ADC MSP.
__weak void | HAL_ADC_MspInit (ADC_HandleTypeDef *hadc)
Initializes the ADC MSP.
__weak void | HAL_ADC_MspDeInit (ADC_HandleTypeDef *hadc)
DeInitializes the ADC MSP.
HAL_StatusTypeDef | HAL_ADC_Start (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group.
HAL_StatusTypeDef | HAL_ADC_Stop (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_PollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for regular group conversion to be completed.
HAL_StatusTypeDef | HAL_ADC_PollForEvent (ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
Poll for conversion event.
HAL_StatusTypeDef | HAL_ADC_Start_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of regular group with interruption.
HAL_StatusTypeDef | HAL_ADC_Stop_IT (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
HAL_StatusTypeDef | HAL_ADC_Start_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
HAL_StatusTypeDef | HAL_ADC_Stop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected group in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADC_GetValue (ADC_HandleTypeDef *hadc)
Get ADC regular group conversion result.
void | HAL_ADC_IRQHandler (ADC_HandleTypeDef *hadc)
Handles ADC interrupt request.
__weak void | HAL_ADC_ConvCpltCallback (ADC_HandleTypeDef *hadc)
Conversion complete callback in non blocking mode.
__weak void | HAL_ADC_ConvHalfCpltCallback (ADC_HandleTypeDef *hadc)
Conversion DMA half-transfer callback in non blocking mode.
__weak void | HAL_ADC_LevelOutOfWindowCallback (ADC_HandleTypeDef *hadc)
Analog watchdog callback in non blocking mode.
__weak void | HAL_ADC_ErrorCallback (ADC_HandleTypeDef *hadc)
ADC error callback in non blocking mode (ADC conversion with interruption or transfer by DMA)
HAL_StatusTypeDef | HAL_ADC_ConfigChannel (ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
Configures the the selected channel to be linked to the regular group.
HAL_StatusTypeDef | HAL_ADC_AnalogWDGConfig (ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
Configures the analog watchdog.
uint32_t | HAL_ADC_GetState (ADC_HandleTypeDef *hadc)
return the ADC state
uint32_t | HAL_ADC_GetError (ADC_HandleTypeDef *hadc)
Return the ADC error code.
HAL_StatusTypeDef | ADC_Enable (ADC_HandleTypeDef *hadc)
Enable the selected ADC.
HAL_StatusTypeDef | ADC_ConversionStop_Disable (ADC_HandleTypeDef *hadc)
Stop ADC conversion and disable the selected ADC.
void | ADC_DMAConvCplt (DMA_HandleTypeDef *hdma)
DMA transfer complete callback.
void | ADC_DMAHalfConvCplt (DMA_HandleTypeDef *hdma)
DMA half transfer complete callback.
void | ADC_DMAError (DMA_HandleTypeDef *hdma)
DMA error callback.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Channels configuration on injected group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32f1xx_hal_adc_ex.c".

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                     ##### ADC peripheral features #####
  ==============================================================================
  [..]
  (+) 12-bit resolution

  (+) Interrupt generation at the end of regular conversion, end of injected
      conversion, and in case of analog watchdog or overrun events.

  (+) Single and continuous conversion modes.

  (+) Scan mode for conversion of several channels sequentially.

  (+) Data alignment with in-built data coherency.

  (+) Programmable sampling time (channel wise)

  (+) ADC conversion of regular group and injected group.

  (+) External trigger (timer or EXTI)
      for both regular and injected groups.

  (+) DMA request generation for transfer of conversions data of regular group.

  (+) Multimode Dual mode (available on devices with 2 ADCs or more).

  (+) Configurable DMA data storage in Multimode Dual mode (available on devices
      with 2 DCs or more).

  (+) Configurable delay between conversions in Dual interleaved mode (available
      on devices with 2 DCs or more).

  (+) ADC calibration

  (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
      slower speed.

  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
      Vdda or to an external voltage reference).

                     ##### How to use this driver #####
  ==============================================================================
    [..]

     *** Configuration of top level parameters related to ADC ***
     ============================================================
     [..]

    (#) Enable the ADC interface
      (++) As prerequisite, ADC clock must be configured at RCC top level.
           Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
                    to device datasheet).
                    Therefore, ADC clock prescaler must be configured in
                    function of ADC clock source frequency to remain below
                    this maximum frequency.
        (++) One clock setting is mandatory:
             ADC clock (core clock, also possibly conversion clock).
             (+++) Example:
                   Into HAL_ADC_MspInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) RCC_PeriphCLKInitTypeDef  PeriphClkInit;
               (+++) __ADC1_CLK_ENABLE();
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
               (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);

    (#) ADC pins configuration
         (++) Enable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
         (++) Configure these ADC pins in analog mode
              using function HAL_GPIO_Init()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Configure the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding ADC interruption vector
              ADCx_IRQHandler().

    (#) Optionally, in case of usage of DMA:
         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
              using function HAL_DMA_Init().
         (++) Configure the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
              into the function of corresponding DMA interruption vector
              DMAx_Channelx_IRQHandler().

     *** Configuration of ADC, groups regular/injected, channels parameters ***
     ==========================================================================
     [..]

    (#) Configure the ADC parameters (resolution, data alignment, ...)
        and regular group parameters (conversion trigger, sequencer, ...)
        using function HAL_ADC_Init().

    (#) Configure the channels for regular group parameters (channel number,
        channel rank into sequencer, ..., into regular group)
        using function HAL_ADC_ConfigChannel().

    (#) Optionally, configure the injected group parameters (conversion trigger,
        sequencer, ..., of injected group)
        and the channels for injected group parameters (channel number,
        channel rank into sequencer, ..., into injected group)
        using function HAL_ADCEx_InjectedConfigChannel().

    (#) Optionally, configure the analog watchdog parameters (channels
        monitored, thresholds, ...)
        using function HAL_ADC_AnalogWDGConfig().

    (#) Optionally, for devices with several ADC instances: configure the
        multimode parameters
        using function HAL_ADCEx_MultiModeConfigChannel().

     *** Execution of ADC conversions ***
     ====================================
     [..]

    (#) Optionally, perform an automatic ADC calibration to improve the
        conversion accuracy
        using function HAL_ADCEx_Calibration_Start().

    (#) ADC driver can be used among three modes: polling, interruption,
        transfer by DMA.

        (++) ADC conversion by polling:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start()
          (+++) Wait for ADC conversion completion
                using function HAL_ADC_PollForConversion()
                (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
                (or for injected group: HAL_ADCEx_InjectedGetValue() )
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop()

        (++) ADC conversion by interruption:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_IT()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback()
                (this function must be implemented in user program)
                (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
          (+++) Retrieve conversion results
                using function HAL_ADC_GetValue()
                (or for injected group: HAL_ADCEx_InjectedGetValue() )
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_IT()

        (++) ADC conversion with transfer by DMA:
          (+++) Activate the ADC peripheral and start conversions
                using function HAL_ADC_Start_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral
                using function HAL_ADC_Stop_DMA()

        (++) For devices with several ADCs: ADC multimode conversion
             with transfer by DMA:
          (+++) Activate the ADC peripheral (slave) and start conversions
                using function HAL_ADC_Start()
          (+++) Activate the ADC peripheral (master) and start conversions
                using function HAL_ADCEx_MultiModeStart_DMA()
          (+++) Wait for ADC conversion completion by call of function
                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
                (these functions must be implemented in user program)
          (+++) Conversion results are automatically transferred by DMA into
                destination variable address.
          (+++) Stop conversion and disable the ADC peripheral (master)
                using function HAL_ADCEx_MultiModeStop_DMA()
          (+++) Stop conversion and disable the ADC peripheral (slave)
                using function HAL_ADC_Stop_IT()

     [..]

    (@) Callback functions must be implemented in user program:
      (+@) HAL_ADC_ErrorCallback()
      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
      (+@) HAL_ADC_ConvCpltCallback()
      (+@) HAL_ADC_ConvHalfCpltCallback
      (+@) HAL_ADCEx_InjectedConvCpltCallback()

     *** Deinitialization of ADC ***
     ============================================================
     [..]

    (#) Disable the ADC interface
      (++) ADC clock can be hard reset and disabled at RCC top level.
        (++) Hard reset of ADC peripherals
             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
        (++) ADC clock disable
             using the equivalent macro/functions as configuration step.
             (+++) Example:
                   Into HAL_ADC_MspDeInit() (recommended code location) or with
                   other device clock parameters configuration:
               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
               (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)

    (#) ADC pins configuration
         (++) Disable the clock for the ADC GPIOs
              using macro __HAL_RCC_GPIOx_CLK_DISABLE()

    (#) Optionally, in case of usage of ADC with interruptions:
         (++) Disable the NVIC for ADC
              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)

    (#) Optionally, in case of usage of DMA:
         (++) Deinitialize the DMA
              using function HAL_DMA_Init().
         (++) Disable the NVIC for DMA
              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)

    [..]
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_adc.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_adc_ex.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_hal_adc_ex.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Multimode feature (available on devices with 2 ADCs or more) ++ Calibration (ADC automatic self-calibration) + Control functions ++ Channels configuration on injected group Other functions (generic functions) are available in file "stm32f1xx_hal_adc.c". More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U
#define | ADC_CALIBRATION_TIMEOUT 10U
#define | ADC_TEMPSENSOR_DELAY_US 10U

Functions

HAL_StatusTypeDef | HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef *hadc)
Perform an ADC automatic self-calibration Calibration prerequisite: ADC must be disabled (execute this function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels.
HAL_StatusTypeDef | HAL_ADCEx_InjectedPollForConversion (ADC_HandleTypeDef *hadc, uint32_t Timeout)
Wait for injected group conversion to be completed.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStart_IT (ADC_HandleTypeDef *hadc)
Enables ADC, starts conversion of injected group with interruption.
HAL_StatusTypeDef | HAL_ADCEx_InjectedStop_IT (ADC_HandleTypeDef *hadc)
Stop conversion of injected channels, disable interruption of end-of-conversion.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStart_DMA (ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
Enables ADC, starts conversion of regular group and transfers result through DMA.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeStop_DMA (ADC_HandleTypeDef *hadc)
Stop ADC conversion of regular group (and injected channels in case of auto_injection mode), disable ADC DMA transfer, disable ADC peripheral.
uint32_t | HAL_ADCEx_InjectedGetValue (ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
Get ADC injected group conversion result.
uint32_t | HAL_ADCEx_MultiModeGetValue (ADC_HandleTypeDef *hadc)
Returns the last ADC Master&Slave regular conversions results data in the selected multi mode.
__weak void | HAL_ADCEx_InjectedConvCpltCallback (ADC_HandleTypeDef *hadc)
Injected conversion complete callback in non blocking mode.
HAL_StatusTypeDef | HAL_ADCEx_InjectedConfigChannel (ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
Configures the ADC injected group and the selected channel to be linked to the injected group.
HAL_StatusTypeDef | HAL_ADCEx_MultiModeConfigChannel (ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
Enable ADC multimode and configure multimode parameters.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Multimode feature (available on devices with 2 ADCs or more) ++ Calibration (ADC automatic self-calibration) + Control functions ++ Channels configuration on injected group Other functions (generic functions) are available in file "stm32f1xx_hal_adc.c".

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  [..]
  (@) Sections "ADC peripheral features" and "How to use this driver" are
      available in file of generic functions "stm32f1xx_hal_adc.c".
  [..]
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_adc_ex.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_can.c File Reference

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  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_hal_can.c File Reference

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | CAN_TIMEOUT_VALUE 10U

Functions

static HAL_StatusTypeDef | CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
static HAL_StatusTypeDef | CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Init (CAN_HandleTypeDef *hcan)
Initializes the CAN peripheral according to the specified parameters in the CAN_InitStruct.
HAL_StatusTypeDef | HAL_CAN_ConfigFilter (CAN_HandleTypeDef *hcan, CAN_FilterConfTypeDef *sFilterConfig)
Configures the CAN reception filter according to the specified parameters in the CAN_FilterInitStruct.
HAL_StatusTypeDef | HAL_CAN_DeInit (CAN_HandleTypeDef *hcan)
Deinitializes the CANx peripheral registers to their default reset values.
__weak void | HAL_CAN_MspInit (CAN_HandleTypeDef *hcan)
Initializes the CAN MSP.
__weak void | HAL_CAN_MspDeInit (CAN_HandleTypeDef *hcan)
DeInitializes the CAN MSP.
HAL_StatusTypeDef | HAL_CAN_Transmit (CAN_HandleTypeDef *hcan, uint32_t Timeout)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Transmit_IT (CAN_HandleTypeDef *hcan)
Initiates and transmits a CAN frame message.
HAL_StatusTypeDef | HAL_CAN_Receive (CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Receive_IT (CAN_HandleTypeDef *hcan, uint8_t FIFONumber)
Receives a correct CAN frame.
HAL_StatusTypeDef | HAL_CAN_Sleep (CAN_HandleTypeDef *hcan)
Enters the Sleep (low power) mode.
HAL_StatusTypeDef | HAL_CAN_WakeUp (CAN_HandleTypeDef *hcan)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.
void | HAL_CAN_IRQHandler (CAN_HandleTypeDef *hcan)
Handles CAN interrupt request.
__weak void | HAL_CAN_TxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_RxCpltCallback (CAN_HandleTypeDef *hcan)
Transmission complete callback in non blocking mode.
__weak void | HAL_CAN_ErrorCallback (CAN_HandleTypeDef *hcan)
Error CAN callback.
HAL_CAN_StateTypeDef | HAL_CAN_GetState (CAN_HandleTypeDef *hcan)
return the CAN state
uint32_t | HAL_CAN_GetError (CAN_HandleTypeDef *hcan)
Return the CAN error code.

Detailed Description

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      (#) Enable the CAN controller interface clock using
          __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
      -@- In case you are using CAN2 only, you have to enable the CAN1 clock.

      (#) CAN pins configuration
        (++) Enable the clock for the CAN GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
        (++) Connect and configure the involved CAN pins using the
              following function HAL_GPIO_Init();

      (#) Initialize and configure the CAN using HAL_CAN_Init() function.

      (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.

      (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.

      (#) Receive a CAN frame using HAL_CAN_Receive() function.

      (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Start the CAN peripheral transmission and wait the end of this operation
           using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
           according to his end application
       (+) Start the CAN peripheral reception and wait the end of this operation
           using HAL_CAN_Receive(), at this stage user can specify the value of timeout
           according to his end application

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
       (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
       (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
       (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
            add his own code by customization of function pointer HAL_CAN_TxCpltCallback
       (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_CAN_ErrorCallback

     *** CAN HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in CAN HAL driver.

      (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
      (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
      (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
      (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
      (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status

     [..]
      (@) You can refer to the CAN HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_can.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_cortex.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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Functions
stm32f1xx_hal_cortex.c File Reference

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence.
void | HAL_NVIC_SetPriority (IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
Sets the priority of an interrupt.
void | HAL_NVIC_EnableIRQ (IRQn_Type IRQn)
Enables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_DisableIRQ (IRQn_Type IRQn)
Disables a device specific interrupt in the NVIC interrupt controller.
void | HAL_NVIC_SystemReset (void)
Initiates a system reset request to reset the MCU.
uint32_t | HAL_SYSTICK_Config (uint32_t TicksNumb)
Initializes the System Timer and its interrupt, and starts the System Tick Timer.
uint32_t | HAL_NVIC_GetPriorityGrouping (void)
Gets the priority grouping field from the NVIC Interrupt Controller.
void | HAL_NVIC_GetPriority (IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
Gets the priority of an interrupt.
void | HAL_NVIC_SetPendingIRQ (IRQn_Type IRQn)
Sets Pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetPendingIRQ (IRQn_Type IRQn)
Gets Pending Interrupt (reads the pending register in the NVIC and returns the pending bit for the specified interrupt).
void | HAL_NVIC_ClearPendingIRQ (IRQn_Type IRQn)
Clears the pending bit of an external interrupt.
uint32_t | HAL_NVIC_GetActive (IRQn_Type IRQn)
Gets active interrupt ( reads the active register in NVIC and returns the active bit).
void | HAL_SYSTICK_CLKSourceConfig (uint32_t CLKSource)
Configures the SysTick clock source.
void | HAL_SYSTICK_IRQHandler (void)
This function handles SYSTICK interrupt request.
__weak void | HAL_SYSTICK_Callback (void)
SYSTICK callback.

Detailed Description

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================

    [..]
    *** How to configure Interrupts using CORTEX HAL driver ***
    ===========================================================
    [..]
    This section provides functions allowing to configure the NVIC interrupts (IRQ).
    The Cortex-M3 exceptions are managed by CMSIS functions.

    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
        function according to the following table.
    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
    (#) please refer to programming manual for details in how to configure priority.

     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
         The pending IRQ priority will be managed only by the sub priority.

     -@- IRQ priority order (sorted by highest to lowest priority):
        (+@) Lowest preemption priority
        (+@) Lowest sub priority
        (+@) Lowest hardware priority (IRQ number)

    [..]
    *** How to configure Systick using CORTEX HAL driver ***
    ========================================================
    [..]
    Setup SysTick Timer for time base.

   (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
       is a CMSIS function that:
        (++) Configures the SysTick Reload register with value passed as function parameter.
        (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
        (++) Resets the SysTick Counter register.
        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
        (++) Enables the SysTick Interrupt.
        (++) Starts the SysTick Counter.

   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
       inside the stm32f1xx_hal_cortex.h file.

   (+) You can change the SysTick IRQ priority by calling the
       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.

   (+) To adjust the SysTick time base, use the following formula:

       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
       (++) Reload Value should not exceed 0xFFFFFF
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_cortex.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_crc.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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Functions
stm32f1xx_hal_crc.c File Reference

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_CRC_Init (CRC_HandleTypeDef *hcrc)
Initializes the CRC according to the specified parameters in the CRC_InitTypeDef and creates the associated handle.
HAL_StatusTypeDef | HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC peripheral.
__weak void | HAL_CRC_MspInit (CRC_HandleTypeDef *hcrc)
Initializes the CRC MSP.
__weak void | HAL_CRC_MspDeInit (CRC_HandleTypeDef *hcrc)
DeInitializes the CRC MSP.
uint32_t | HAL_CRC_Accumulate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer using combination of the previous CRC value and the new one.
uint32_t | HAL_CRC_Calculate (CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
Computes the 32-bit CRC of 32-bit data buffer independently of the previous CRC value.
HAL_CRC_StateTypeDef | HAL_CRC_GetState (CRC_HandleTypeDef *hcrc)
Returns the CRC state.

Detailed Description

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                     ##### How to use this driver #####
  ==============================================================================
    [..]
      The CRC HAL driver can be used as follows:

      (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();

      (#) Use HAL_CRC_Accumulate() function to compute the CRC value of
          a 32-bit data buffer using combination of the previous CRC value
          and the new one.

      (#) Use HAL_CRC_Calculate() function to compute the CRC Value of
          a new 32-bit data buffer. This function resets the CRC computation
          unit before starting the computation to avoid getting wrong CRC values.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_crc.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dma.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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Functions
stm32f1xx_hal_dma.c File Reference

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

static void | DMA_SetConfig (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Sets the DMA Transfer parameter.
HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma)
Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma)
DeInitialize the DMA peripheral.
HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma)
Abort the DMA Transfer.
HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
Polling for transfer complete.
void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma)
Handles DMA interrupt request.
HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma))
Register callbacks.
HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
UnRegister callbacks.
HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma)
Return the DMA hande state.
uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma)
Return the DMA error code.

Detailed Description

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
   (#) Enable and configure the peripheral to be connected to the DMA Channel
       (except for internal SRAM / FLASH memories: no initialization is
       necessary). Please refer to the Reference manual for connection between peripherals
       and DMA requests.

   (#) For a given Channel, program the required configuration through the following parameters:
       Channel request, Transfer Direction, Source and Destination data formats,
       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
       using HAL_DMA_Init() function.

   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
       detection.

   (#) Use HAL_DMA_Abort() function to abort the current transfer

     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
     *** Polling mode IO operation ***
     =================================
    [..]
          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
              address and destination address and the Length of data to be transferred
          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
              case a fixed Timeout can be configured by User depending from his application.

     *** Interrupt mode IO operation ***
     ===================================
    [..]
          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
              Source address and destination address and the Length of data to be transferred.
              In this case the DMA interrupt is configured
          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
              add his own function by customization of function pointer XferCpltCallback and
              XferErrorCallback (i.e. a member of DMA handle structure).

     *** DMA HAL driver macros list ***
     =============================================
      [..]
       Below the list of most used macros in DMA HAL driver.

       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.

     [..]
      (@) You can refer to the DMA HAL driver header file for more useful macros
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_dma.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_flash.c File Reference

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stm32f1xx_hal_flash.c File Reference

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral State functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

static void | FLASH_Program_HalfWord (uint32_t Address, uint16_t Data)
Program a half-word (16-bit) at a specified address.
static void | FLASH_SetErrorCode (void)
Set the specific FLASH error flag.
void | FLASH_PageErase (uint32_t PageAddress)
Erase the specified FLASH memory page.
HAL_StatusTypeDef | HAL_FLASH_Program (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address.
HAL_StatusTypeDef | HAL_FLASH_Program_IT (uint32_t TypeProgram, uint32_t Address, uint64_t Data)
Program halfword, word or double word at a specified address with interrupt enabled.
void | HAL_FLASH_IRQHandler (void)
This function handles FLASH interrupt request.
__weak void | HAL_FLASH_EndOfOperationCallback (uint32_t ReturnValue)
FLASH end of operation interrupt callback.
__weak void | HAL_FLASH_OperationErrorCallback (uint32_t ReturnValue)
FLASH operation error interrupt callback.
HAL_StatusTypeDef | HAL_FLASH_Unlock (void)
Unlock the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_Lock (void)
Locks the FLASH control register access.
HAL_StatusTypeDef | HAL_FLASH_OB_Unlock (void)
Unlock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Lock (void)
Lock the FLASH Option Control Registers access.
HAL_StatusTypeDef | HAL_FLASH_OB_Launch (void)
Launch the option byte loading.
uint32_t | HAL_FLASH_GetError (void)
Get the specific FLASH error flag.
HAL_StatusTypeDef | FLASH_WaitForLastOperation (uint32_t Timeout)
Wait for a FLASH operation to complete.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                        ##### FLASH peripheral features #####
  ==============================================================================
  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
       to the Flash memory. It implements the erase and program Flash memory operations
       and the read and write protection mechanisms.

  [..] The Flash memory interface accelerates code execution with a system of instruction
      prefetch.

  [..] The FLASH main features are:
      (+) Flash memory read operations
      (+) Flash memory program/erase operations
      (+) Read / write protections
      (+) Prefetch on I-Code
      (+) Option Bytes programming

                     ##### How to use this driver #####
  ==============================================================================
  [..]
      This driver provides functions and macros to configure and program the FLASH
      memory of all STM32F1xx devices.

      (#) FLASH Memory I/O Programming functions: this group includes all needed
          functions to erase and program the main memory:
        (++) Lock and Unlock the FLASH interface
        (++) Erase function: Erase page, erase all pages
        (++) Program functions: half word, word and doubleword
      (#) FLASH Option Bytes Programming functions: this group includes all needed
          functions to manage the Option Bytes:
        (++) Lock and Unlock the Option Bytes
        (++) Set/Reset the write protection
        (++) Set the Read protection Level
        (++) Program the user Option Bytes
        (++) Launch the Option Bytes loader
        (++) Erase Option Bytes
        (++) Program the data Option Bytes
        (++) Get the Write protection.
        (++) Get the user option bytes.

      (#) Interrupts and flags management functions : this group
          includes all needed functions to:
        (++) Handle FLASH interrupts
        (++) Wait for last FLASH operation according to its status
        (++) Get error flag status

  [..] In addition to these function, this driver includes a set of macros allowing
       to handle the following operations:

      (+) Set/Get the latency
      (+) Enable/Disable the prefetch buffer
      (+) Enable/Disable the half cycle access
      (+) Enable/Disable the FLASH interrupts
      (+) Monitor the FLASH flags status
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_flash.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_flash_ex.c File Reference

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Defines | Functions | Variables
stm32f1xx_hal_flash_ex.c File Reference

Extended FLASH HAL module driver. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos
#define | FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos
#define | FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos

Functions

static void | FLASH_MassErase (uint32_t Banks)
Full erase of FLASH memory Bank.
void | FLASH_PageErase (uint32_t PageAddress)
Erase the specified FLASH memory page.
static HAL_StatusTypeDef | FLASH_OB_EnableWRP (uint32_t WriteProtectPage)
Enable the write protection of the desired pages.
static HAL_StatusTypeDef | FLASH_OB_DisableWRP (uint32_t WriteProtectPage)
Disable the write protection of the desired pages.
static HAL_StatusTypeDef | FLASH_OB_RDP_LevelConfig (uint8_t ReadProtectLevel)
Set the read protection level.
static HAL_StatusTypeDef | FLASH_OB_UserConfig (uint8_t UserConfig)
Program the FLASH User Option Byte.
static HAL_StatusTypeDef | FLASH_OB_ProgramData (uint32_t Address, uint8_t Data)
Programs a half word at a specified Option Byte Data address.
static uint32_t | FLASH_OB_GetWRP (void)
Return the FLASH Write Protection Option Bytes value.
static uint32_t | FLASH_OB_GetRDP (void)
Returns the FLASH Read Protection level.
static uint8_t | FLASH_OB_GetUser (void)
Return the FLASH User Option Byte value.
HAL_StatusTypeDef | HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
Perform a mass erase or erase the specified FLASH memory pages.
HAL_StatusTypeDef | HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)
Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
HAL_StatusTypeDef | HAL_FLASHEx_OBErase (void)
Erases the FLASH option bytes.
HAL_StatusTypeDef | HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)
Program option bytes.
void | HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)
Get the Option byte configuration.
uint32_t | HAL_FLASHEx_OBGetUserData (uint32_t DATAAdress)
Get the Option byte user data.
void | FLASH_PageErase (uint32_t PageAddress)
Erase the specified FLASH memory page.

Variables

FLASH_ProcessTypeDef pFlash

Detailed Description

Extended FLASH HAL module driver.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016 This file provides firmware functions to manage the following functionalities of the FLASH peripheral: + Extended Initialization/de-initialization functions + Extended I/O operation functions + Extended Peripheral Control functions
  ==============================================================================
               ##### Flash peripheral extended features  #####
  ==============================================================================

                      ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to configure and program the FLASH memory
       of all STM32F1xxx devices. It includes

        (++) Set/Reset the write protection
        (++) Program the user Option Bytes
        (++) Get the Read protection Level
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_flash_ex.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_gpio.c File Reference

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Defines | Functions
stm32f1xx_hal_gpio.c File Reference

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | GPIO_MODE 0x00000003U
#define | EXTI_MODE 0x10000000U
#define | GPIO_MODE_IT 0x00010000U
#define | GPIO_MODE_EVT 0x00020000U
#define | RISING_EDGE 0x00100000U
#define | FALLING_EDGE 0x00200000U
#define | GPIO_OUTPUT_TYPE 0x00000010U
#define | GPIO_NUMBER 16U
#define | GPIO_CR_MODE_INPUT 0x00000000U
#define | GPIO_CR_CNF_ANALOG 0x00000000U
#define | GPIO_CR_CNF_INPUT_FLOATING 0x00000004U
#define | GPIO_CR_CNF_INPUT_PU_PD 0x00000008U
#define | GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U
#define | GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U
#define | GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U
#define | GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU

Functions

void | HAL_GPIO_Init (GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
void | HAL_GPIO_DeInit (GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
De-initializes the GPIOx peripheral registers to their default reset values.
GPIO_PinState | HAL_GPIO_ReadPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Reads the specified input port pin.
void | HAL_GPIO_WritePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
Sets or clears the selected data port bit.
void | HAL_GPIO_TogglePin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Toggles the specified GPIO pin.
HAL_StatusTypeDef | HAL_GPIO_LockPin (GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
Locks GPIO Pins configuration registers.
void | HAL_GPIO_EXTI_IRQHandler (uint16_t GPIO_Pin)
This function handles EXTI interrupt request.
__weak void | HAL_GPIO_EXTI_Callback (uint16_t GPIO_Pin)
EXTI line detection callbacks.

Detailed Description

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                    ##### GPIO Peripheral features #####
  ==============================================================================
  [..]
  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
  in several modes:
  (+) Input mode
  (+) Analog mode
  (+) Output mode
  (+) Alternate function mode
  (+) External interrupt/event lines

  [..]
  During and just after reset, the alternate functions and external interrupt
  lines are not active and the I/O ports are configured in input floating mode.

  [..]
  All GPIO pins have weak internal pull-up and pull-down resistors, which can be
  activated or not.

  [..]
  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
  type and the IO speed can be selected depending on the VDD value.

  [..]
  All ports have external interrupt/event capability. To use external interrupt
  lines, the port must be configured in input mode. All available GPIO pins are
  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

  [..]
  The external interrupt/event controller consists of up to 20 edge detectors in connectivity
  line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
  Each input line can be independently configured to select the type (event or interrupt) and
  the corresponding trigger event (rising or falling or both). Each line can also masked
  independently. A pending register maintains the status line of the interrupt requests

                     ##### How to use this driver #####
  ==============================================================================
 [..]
   (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().

   (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
       (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
       (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
            structure.
       (++) In case of Output or alternate function mode selection: the speed is
            configured through "Speed" member from GPIO_InitTypeDef structure
       (++) Analog mode is required when a pin is to be used as ADC channel
            or DAC output.
       (++) In case of external interrupt/event selection the "Mode" member from
            GPIO_InitTypeDef structure select the type (interrupt or event) and
            the corresponding trigger event (rising or falling or both).

   (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
       mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
       HAL_NVIC_EnableIRQ().

   (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().

   (#) To set/reset the level of a pin configured in output mode use
       HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().

   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().

   (#) During and just after reset, the alternate functions are not
       active and the GPIO pins are configured in input floating mode (except JTAG
       pins).

   (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
       (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
       priority over the GPIO function.

   (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
       general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
       The HSE has priority over the GPIO function.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_gpio.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_gpio_ex.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F1xx_HAL_Driver
  • Src
Functions
stm32f1xx_hal_gpio_ex.c File Reference

GPIO Extension HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) extension peripheral. + Extended features functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

void | HAL_GPIOEx_ConfigEventout (uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
void | HAL_GPIOEx_EnableEventout (void)
Enables the Event Output.
void | HAL_GPIOEx_DisableEventout (void)
Disables the Event Output.

Detailed Description

GPIO Extension HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) extension peripheral. + Extended features functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                    ##### GPIO Peripheral extension features #####
  ==============================================================================
  [..] GPIO module on STM32F1 family, manage also the AFIO register:
       (+) Possibility to use the EVENTOUT Cortex feature

                     ##### How to use this driver #####
  ==============================================================================
  [..] This driver provides functions to use EVENTOUT Cortex feature
    (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
    (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
    (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_gpio_ex.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_i2c.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F1xx_HAL_Driver
  • Src
Defines | Functions
stm32f1xx_hal_i2c.c File Reference

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State, Mode and Error functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | I2C_TIMEOUT_FLAG 35U
#define | I2C_TIMEOUT_BUSY_FLAG 25U
#define | I2C_NO_OPTION_FRAME 0xFFFF0000U
#define | I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY)))
#define | I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
#define | I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))
#define | I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))
#define | I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))

Functions

static void | I2C_DMAXferCplt (DMA_HandleTypeDef *hdma)
DMA I2C process complete callback.
static void | I2C_DMAError (DMA_HandleTypeDef *hdma)
DMA I2C communication error callback.
static void | I2C_DMAAbort (DMA_HandleTypeDef *hdma)
DMA I2C communication abort callback (To be called at end of DMA Abort procedure).
static void | I2C_ITError (I2C_HandleTypeDef *hi2c)
I2C interrupts error process.
static HAL_StatusTypeDef | I2C_MasterRequestWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
static HAL_StatusTypeDef | I2C_MasterRequestRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address for read request.
static HAL_StatusTypeDef | I2C_RequestMemoryWrite (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for write request.
static HAL_StatusTypeDef | I2C_RequestMemoryRead (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
Master sends target device address followed by internal memory address for read request.
static HAL_StatusTypeDef | I2C_WaitOnFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout.
static HAL_StatusTypeDef | I2C_WaitOnMasterAddressFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for Master addressing phase.
static HAL_StatusTypeDef | I2C_WaitOnTXEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of TXE flag.
static HAL_StatusTypeDef | I2C_WaitOnBTFFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of BTF flag.
static HAL_StatusTypeDef | I2C_WaitOnRXNEFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of RXNE flag.
static HAL_StatusTypeDef | I2C_WaitOnSTOPFlagUntilTimeout (I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
This function handles I2C Communication Timeout for specific usage of STOP flag.
static HAL_StatusTypeDef | I2C_IsAcknowledgeFailed (I2C_HandleTypeDef *hi2c)
This function handles Acknowledge failed detection during an I2C Communication.
static HAL_StatusTypeDef | I2C_MasterTransmit_TXE (I2C_HandleTypeDef *hi2c)
Handle TXE flag for Master.
static HAL_StatusTypeDef | I2C_MasterTransmit_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Master transmitter.
static HAL_StatusTypeDef | I2C_MasterReceive_RXNE (I2C_HandleTypeDef *hi2c)
Handle RXNE flag for Master.
static HAL_StatusTypeDef | I2C_MasterReceive_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Master receiver.
static HAL_StatusTypeDef | I2C_Master_SB (I2C_HandleTypeDef *hi2c)
Handle SB flag for Master.
static HAL_StatusTypeDef | I2C_Master_ADD10 (I2C_HandleTypeDef *hi2c)
Handle ADD10 flag for Master.
static HAL_StatusTypeDef | I2C_Master_ADDR (I2C_HandleTypeDef *hi2c)
Handle ADDR flag for Master.
static HAL_StatusTypeDef | I2C_SlaveTransmit_TXE (I2C_HandleTypeDef *hi2c)
Handle TXE flag for Slave.
static HAL_StatusTypeDef | I2C_SlaveTransmit_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Slave transmitter.
static HAL_StatusTypeDef | I2C_SlaveReceive_RXNE (I2C_HandleTypeDef *hi2c)
Handle RXNE flag for Slave.
static HAL_StatusTypeDef | I2C_SlaveReceive_BTF (I2C_HandleTypeDef *hi2c)
Handle BTF flag for Slave receiver.
static HAL_StatusTypeDef | I2C_Slave_ADDR (I2C_HandleTypeDef *hi2c)
Handle ADD flag for Slave.
static HAL_StatusTypeDef | I2C_Slave_STOPF (I2C_HandleTypeDef *hi2c)
Handle STOPF flag for Slave.
static HAL_StatusTypeDef | I2C_Slave_AF (I2C_HandleTypeDef *hi2c)
HAL_StatusTypeDef | HAL_I2C_Init (I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c)
DeInitializes the I2C peripheral.
__weak void | HAL_I2C_MspInit (I2C_HandleTypeDef *hi2c)
I2C MSP Init.
__weak void | HAL_I2C_MspDeInit (I2C_HandleTypeDef *hi2c)
I2C MSP DeInit.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Receive (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Transmit_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Sequential_Receive_IT (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_EnableListen_IT (I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_DisableListen_IT (I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Master_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Receive_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Master_Abort_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master I2C process communication with Interrupt.
HAL_StatusTypeDef | HAL_I2C_Slave_Transmit_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Slave_Receive_DMA (I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_I2C_Mem_Write (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_IT (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Write_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
HAL_StatusTypeDef | HAL_I2C_Mem_Read_DMA (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
HAL_StatusTypeDef | HAL_I2C_IsDeviceReady (I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
void | HAL_I2C_EV_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
void | HAL_I2C_ER_IRQHandler (I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
__weak void | HAL_I2C_MasterTxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
__weak void | HAL_I2C_MasterRxCpltCallback (I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
__weak void | HAL_I2C_SlaveTxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
__weak void | HAL_I2C_SlaveRxCpltCallback (I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
__weak void | HAL_I2C_AddrCallback (I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
__weak void | HAL_I2C_ListenCpltCallback (I2C_HandleTypeDef *hi2c)
Listen Complete callback.
__weak void | HAL_I2C_MemTxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
__weak void | HAL_I2C_MemRxCpltCallback (I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
__weak void | HAL_I2C_ErrorCallback (I2C_HandleTypeDef *hi2c)
I2C error callback.
__weak void | HAL_I2C_AbortCpltCallback (I2C_HandleTypeDef *hi2c)
I2C abort callback.
HAL_I2C_StateTypeDef | HAL_I2C_GetState (I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
HAL_I2C_ModeTypeDef | HAL_I2C_GetMode (I2C_HandleTypeDef *hi2c)
Return the I2C Master, Slave, Memory or no mode.
uint32_t | HAL_I2C_GetError (I2C_HandleTypeDef *hi2c)
Return the I2C error code.

Detailed Description

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State, Mode and Error functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The I2C HAL driver can be used as follows:

    (#) Declare a I2C_HandleTypeDef handle structure, for example:
        I2C_HandleTypeDef  hi2c;

    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
        (##) Enable the I2Cx interface clock
        (##) I2C pins configuration
            (+++) Enable the clock for the I2C GPIOs
            (+++) Configure I2C pins as alternate function open-drain
        (##) NVIC configuration if you need to use interrupt process
            (+++) Configure the I2Cx interrupt priority
            (+++) Enable the NVIC I2C IRQ Channel
        (##) DMA Configuration if you need to use DMA process
            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
            (+++) Enable the DMAx interface clock using
            (+++) Configure the DMA handle parameters
            (+++) Configure the DMA Tx or Rx channel
            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
                  the DMA Tx or Rx channel

    (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
        Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.

    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.

    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()

    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()

    *** Polling mode IO MEM operation ***
    =====================================
    [..]
      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()

    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
      (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
      (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
      (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()

    *** Interrupt mode IO sequential operation ***
    ==============================================
    [..]
      (@) These interfaces allow to manage a sequential transfer with a repeated start condition
          when a direction change during transfer
    [..]
      (+) A specific option field manage the different steps of a sequential transfer
      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
                            and data to transfer without a final stop condition
      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and without a final stop condition in both cases
      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
                            and with new data to transfer if the direction change or manage only the new data to transfer
                            if no direction change and with a final stop condition in both cases

      (+) Differents sequential I2C interfaces are listed below:
      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
      (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback()

    *** Interrupt mode IO MEM operation ***
    =======================================
    [..]
      (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
          HAL_I2C_Mem_Write_IT()
      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
      (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
          HAL_I2C_Mem_Read_IT()
      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Master_Transmit_DMA()
      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
      (+) Receive in master mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Master_Receive_DMA()
      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
      (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Slave_Transmit_DMA()
      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
      (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
          HAL_I2C_Slave_Receive_DMA()
      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback
      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
           add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()

    *** DMA mode IO MEM operation ***
    =================================
    [..]
      (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
          HAL_I2C_Mem_Write_DMA()
      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
      (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
          HAL_I2C_Mem_Read_DMA()
      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
           add his own code by customization of function pointer HAL_I2C_ErrorCallback

     *** I2C HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in I2C HAL driver.

      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
      (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
      (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt

     [..]
       (@) You can refer to the I2C HAL driver header file for more useful macros

     *** I2C Workarounds linked to Silicon Limitation ***
     ====================================================
     [..]
       Below the list of all silicon limitations implemented for HAL on STM32F1xx product.
       (@) See ErrataSheet to know full silicon limitation list of your product.

       (#) Workarounds Implemented inside I2C HAL Driver
          (##) Wrong data read into data register (Polling and Interrupt mode)
          (##) Start cannot be generated after a misplaced Stop
          (##) Some software events must be managed before the current byte is being transferred:
               Workaround: Use DMA in general, except when the Master is receiving a single byte.
               For Interupt mode, I2C should have the highest priority in the application.
          (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter:
               Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if
               supported by the slave.
          (##) Data valid time (tVD;DAT) violated without the OVR flag being set:
               Workaround: If the slave device allows it, use the clock stretching mechanism
               by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in HAL_I2C_Init.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_i2c.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_irda.c File Reference

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Functions
stm32f1xx_hal_irda.c File Reference

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

static void | IRDA_SetConfig (IRDA_HandleTypeDef *hirda)
Configures the IRDA peripheral.
static HAL_StatusTypeDef | IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | IRDA_EndTransmit_IT (IRDA_HandleTypeDef *hirda)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | IRDA_Receive_IT (IRDA_HandleTypeDef *hirda)
Receives an amount of data in non blocking mode.
static void | IRDA_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA IRDA transmit process complete callback.
static void | IRDA_DMATransmitHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process complete callback.
static void | IRDA_DMAReceiveHalfCplt (DMA_HandleTypeDef *hdma)
DMA IRDA receive process half complete callback.
static void | IRDA_DMAError (DMA_HandleTypeDef *hdma)
DMA IRDA communication error callback.
static void | IRDA_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA IRDA communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | IRDA_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | IRDA_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | IRDA_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Tx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | IRDA_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA IRDA Rx communication abort callback, when initiated by user by a call to HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | IRDA_WaitOnFlagUntilTimeout (IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles IRDA Communication Timeout.
static void | IRDA_EndTxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
static void | IRDA_EndRxTransfer (IRDA_HandleTypeDef *hirda)
End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
HAL_StatusTypeDef | HAL_IRDA_Init (IRDA_HandleTypeDef *hirda)
Initializes the IRDA mode according to the specified parameters in the IRDA_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_IRDA_DeInit (IRDA_HandleTypeDef *hirda)
DeInitializes the IRDA peripheral.
__weak void | HAL_IRDA_MspInit (IRDA_HandleTypeDef *hirda)
IRDA MSP Init.
__weak void | HAL_IRDA_MspDeInit (IRDA_HandleTypeDef *hirda)
IRDA MSP DeInit.
HAL_StatusTypeDef | HAL_IRDA_Transmit (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_IT (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Transmit_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_Receive_DMA (IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_IRDA_DMAPause (IRDA_HandleTypeDef *hirda)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAResume (IRDA_HandleTypeDef *hirda)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_DMAStop (IRDA_HandleTypeDef *hirda)
Stops the DMA Transfer.
HAL_StatusTypeDef | HAL_IRDA_Abort (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_IRDA_Abort_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortTransmit_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_IRDA_AbortReceive_IT (IRDA_HandleTypeDef *hirda)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_IRDA_IRQHandler (IRDA_HandleTypeDef *hirda)
This function handles IRDA interrupt request.
__weak void | HAL_IRDA_TxCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Transfer complete callbacks.
__weak void | HAL_IRDA_TxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Tx Half Transfer completed callbacks.
__weak void | HAL_IRDA_RxCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Transfer complete callbacks.
__weak void | HAL_IRDA_RxHalfCpltCallback (IRDA_HandleTypeDef *hirda)
Rx Half Transfer complete callbacks.
__weak void | HAL_IRDA_ErrorCallback (IRDA_HandleTypeDef *hirda)
IRDA error callbacks.
__weak void | HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Complete callback.
__weak void | HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort Transmit Complete callback.
__weak void | HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
IRDA Abort ReceiveComplete callback.
HAL_IRDA_StateTypeDef | HAL_IRDA_GetState (IRDA_HandleTypeDef *hirda)
Returns the IRDA state.
uint32_t | HAL_IRDA_GetError (IRDA_HandleTypeDef *hirda)
Return the IRDA error code.

Detailed Description

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The IRDA HAL driver can be used as follows:

    (#) Declare a IRDA_HandleTypeDef handle structure.
    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
        (##) Enable the USARTx interface clock.
        (##) IRDA pins configuration:
            (+++) Enable the clock for the IRDA GPIOs.
            (+++) Configure the IRDA pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
             and HAL_IRDA_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
             and HAL_IRDA_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
            (+++) Configure the IRDAx interrupt priority and enable the NVIC USART IRQ handle
                  (used for last byte sending completion detection in DMA non circular mode)

    (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
        and Mode(Receiver/Transmitter) in the hirda Init structure.

    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_IRDA_MspInit() API.
     [..]
        (@) The specific IRDA interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
     [..]
        Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
       (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
       (+) At transmission end of half transfer HAL_IRDA_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback
       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
       (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
       (+) At reception end of half transfer HAL_IRDA_RxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback
       (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_IRDA_ErrorCallback
       (+) Pause the DMA Transfer using HAL_IRDA_DMAPause()
       (+) Resume the DMA Transfer using HAL_IRDA_DMAResume()
       (+) Stop the DMA Transfer using HAL_IRDA_DMAStop()

     *** IRDA HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IRDA HAL driver.

       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
       (+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not

     [..]
       (@) You can refer to the IRDA HAL driver header file for more useful macros
[..] (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), the possible IRDA frame formats are as listed in the following table: +-------------------------------------------------------------+ | M bit | PCE bit | IRDA frame | |---------------------|---------------------------------------| | 0 | 0 | | SB | 8 bit data | 1 STB | | |---------|-----------|---------------------------------------| | 0 | 1 | | SB | 7 bit data | PB | 1 STB | | |---------|-----------|---------------------------------------| | 1 | 0 | | SB | 9 bit data | 1 STB | | |---------|-----------|---------------------------------------| | 1 | 1 | | SB | 8 bit data | PB | 1 STB | | +-------------------------------------------------------------+
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_irda.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_iwdg.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_hal_iwdg.c File Reference

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | HAL_IWDG_DEFAULT_TIMEOUT 48U

Functions

HAL_StatusTypeDef | HAL_IWDG_Init (IWDG_HandleTypeDef *hiwdg)
Initialize the IWDG according to the specified parameters in the IWDG_InitTypeDef and start watchdog.
HAL_StatusTypeDef | HAL_IWDG_Refresh (IWDG_HandleTypeDef *hiwdg)
Refresh the IWDG.

Detailed Description

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

Author:
MCD Application Team
Version:
V1.5.0
Date:
06-May-2016
  ==============================================================================
                    ##### IWDG Generic features #####
  ==============================================================================
  [..]
    (+) The IWDG can be started by either software or hardware (configurable
        through option byte).

    (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
        if the main clock fails.

    (+) Once the IWDG is started, the LSI is forced ON and both can not be
        disabled. The counter starts counting down from the reset value (0xFFF).
        When it reaches the end of count value (0x000) a reset signal is
        generated (IWDG reset).

    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
        the IWDG_RLR value is reloaded in the counter and the watchdog reset is
        prevented.

    (+) The IWDG is implemented in the VDD voltage domain that is still functional
        in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
        reset occurs.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the IWDG counter either continues to work normally or stops, depending
        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros

    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
         The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
         devices provide the capability to measure the LSI frequency (LSI clock
         connected internally to TIM5 CH4 input capture). The measured value
         can be used to have an IWDG timeout with an acceptable accuracy.

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (#) Use IWDG using HAL_IWDG_Init() function to :
      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
           clock is forced ON and IWDG counter starts downcounting.
      (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
      (++) Configure the IWDG prescaler and counter reload value. This reload
           value will be loaded in the IWDG counter each time the watchdog is
           reloaded, then the IWDG will start counting down from this value.
      (++) wait for status flags to be reset"

    (#) Then the application program must refresh the IWDG counter at regular
        intervals during normal operation to prevent an MCU reset, using
        HAL_IWDG_Refresh() function.

     *** IWDG HAL driver macros list ***
     ====================================
     [..]
       Below the list of most used macros in IWDG HAL driver:
      (+) __HAL_IWDG_START: Enable the IWDG peripheral
      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
          the reload register
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_iwdg.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pcd.c File Reference

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Defines | Functions
stm32f1xx_hal_pcd.c File Reference

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define | PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))

Functions

static HAL_StatusTypeDef | PCD_EP_ISR_Handler (PCD_HandleTypeDef *hpcd)
This function handles PCD Endpoint interrupt request.
HAL_StatusTypeDef | HAL_PCD_Init (PCD_HandleTypeDef *hpcd)
Initializes the PCD according to the specified parameters in the PCD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd)
DeInitializes the PCD peripheral.
__weak void | HAL_PCD_MspInit (PCD_HandleTypeDef *hpcd)
Initializes the PCD MSP.
__weak void | HAL_PCD_MspDeInit (PCD_HandleTypeDef *hpcd)
DeInitializes PCD MSP.
HAL_StatusTypeDef | HAL_PCD_Start (PCD_HandleTypeDef *hpcd)
Start The USB Device.
HAL_StatusTypeDef | HAL_PCD_Stop (PCD_HandleTypeDef *hpcd)
Stop The USB Device.
void | HAL_PCD_IRQHandler (PCD_HandleTypeDef *hpcd)
This function handles PCD interrupt request.
__weak void | HAL_PCD_DataOutStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data out stage callbacks.
__weak void | HAL_PCD_DataInStageCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Data IN stage callbacks.
__weak void | HAL_PCD_SetupStageCallback (PCD_HandleTypeDef *hpcd)
Setup stage callback.
__weak void | HAL_PCD_SOFCallback (PCD_HandleTypeDef *hpcd)
USB Start Of Frame callbacks.
__weak void | HAL_PCD_ResetCallback (PCD_HandleTypeDef *hpcd)
USB Reset callbacks.
__weak void | HAL_PCD_SuspendCallback (PCD_HandleTypeDef *hpcd)
Suspend event callbacks.
__weak void | HAL_PCD_ResumeCallback (PCD_HandleTypeDef *hpcd)
Resume event callbacks.
__weak void | HAL_PCD_ISOOUTIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO OUT callbacks.
__weak void | HAL_PCD_ISOINIncompleteCallback (PCD_HandleTypeDef *hpcd, uint8_t epnum)
Incomplete ISO IN callbacks.
__weak void | HAL_PCD_ConnectCallback (PCD_HandleTypeDef *hpcd)
Connection event callbacks.
__weak void | HAL_PCD_DisconnectCallback (PCD_HandleTypeDef *hpcd)
Disconnection event callbacks.
HAL_StatusTypeDef | HAL_PCD_DevConnect (PCD_HandleTypeDef *hpcd)
Connect the USB device.
HAL_StatusTypeDef | HAL_PCD_DevDisconnect (PCD_HandleTypeDef *hpcd)
Disconnect the USB device.
HAL_StatusTypeDef | HAL_PCD_SetAddress (PCD_HandleTypeDef *hpcd, uint8_t address)
Set the USB Device address.
HAL_StatusTypeDef | HAL_PCD_EP_Open (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
Open and configure an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Close (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Deactivate an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Receive (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Receive an amount of data.
uint16_t | HAL_PCD_EP_GetRxCount (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Get Received Data Size.
HAL_StatusTypeDef | HAL_PCD_EP_Transmit (PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
Send an amount of data.
HAL_StatusTypeDef | HAL_PCD_EP_SetStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Set a STALL condition over an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_ClrStall (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Clear a STALL condition over in an endpoint.
HAL_StatusTypeDef | HAL_PCD_EP_Flush (PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
Flush an endpoint.
HAL_StatusTypeDef | HAL_PCD_ActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling.
HAL_StatusTypeDef | HAL_PCD_DeActivateRemoteWakeup (PCD_HandleTypeDef *hpcd)
HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling.
PCD_StateTypeDef | HAL_PCD_GetState (PCD_HandleTypeDef *hpcd)
Return the PCD state.

Detailed Description

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                    ##### How to use this driver #####
  ==============================================================================
    [..]
      The PCD HAL driver can be used as follows:

     (#) Declare a PCD_HandleTypeDef handle structure, for example:
         PCD_HandleTypeDef  hpcd;

     (#) Fill parameters of Init structure in HCD handle

     (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)

     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
         (##) Enable the PCD/USB Low Level interface clock using the following macro
              (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral available
                    on STM32F102xx and STM32F103xx devices
              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); For USB OTG FS peripheral available
                    on STM32F105xx and STM32F107xx devices

         (##) Initialize the related GPIO clocks
         (##) Configure PCD pin-out
         (##) Configure PCD NVIC interrupt

     (#)Associate the Upper USB device stack to the HAL PCD Driver:
         (##) hpcd.pData = pdev;

     (#)Enable HCD transmission and reception:
         (##) HAL_PCD_Start();
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_pcd.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pcd_ex.c File Reference

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  • STM32F1xx_HAL_Driver
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Functions
stm32f1xx_hal_pcd_ex.c File Reference

Extended PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions: Update FIFO configuration, PMA configuration for EPs. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_PCDEx_PMAConfig (PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress)
Configure PMA for EP.
__weak void | HAL_PCDEx_SetConnectionState (PCD_HandleTypeDef *hpcd, uint8_t state)
Software Device Connection, this function is not required by USB OTG FS peripheral, it is used only by USB Device FS peripheral.

Detailed Description

Extended PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions: Update FIFO configuration, PMA configuration for EPs.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_pcd_ex.c.

Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pwr.c File Reference

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Defines | Functions
stm32f1xx_hal_pwr.c File Reference

PWR HAL module driver. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | PVD_MODE_IT 0x00010000U
#define | PVD_MODE_EVT 0x00020000U
#define | PVD_RISING_EDGE 0x00000001U
#define | PVD_FALLING_EDGE 0x00000002U
#define | PWR_OFFSET (PWR_BASE - PERIPH_BASE)
#define | PWR_CR_OFFSET 0x00U
#define | PWR_CSR_OFFSET 0x04U
#define | PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
#define | PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
#define | LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
#define | CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))
#define | DBP_BIT_NUMBER PWR_CR_DBP_Pos
#define | CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))
#define | PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
#define | CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))
#define | CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))

Functions

static void | PWR_OverloadWfe (void)
void | HAL_PWR_DeInit (void)
Deinitializes the PWR peripheral registers to their default reset values.
void | HAL_PWR_EnableBkUpAccess (void)
Enables access to the backup domain (RTC registers, RTC backup data registers ).
void | HAL_PWR_DisableBkUpAccess (void)
Disables access to the backup domain (RTC registers, RTC backup data registers).
void | HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
Configures the voltage threshold detected by the Power Voltage Detector(PVD).
void | HAL_PWR_EnablePVD (void)
Enables the Power Voltage Detector(PVD).
void | HAL_PWR_DisablePVD (void)
Disables the Power Voltage Detector(PVD).
void | HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinx)
Enables the WakeUp PINx functionality.
void | HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx)
Disables the WakeUp PINx functionality.
void | HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
Enters Sleep mode.
void | HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry)
Enters Stop mode.
void | HAL_PWR_EnterSTANDBYMode (void)
Enters Standby mode.
void | HAL_PWR_EnableSleepOnExit (void)
Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
void | HAL_PWR_DisableSleepOnExit (void)
Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
void | HAL_PWR_EnableSEVOnPend (void)
Enables CORTEX M3 SEVONPEND bit.
void | HAL_PWR_DisableSEVOnPend (void)
Disables CORTEX M3 SEVONPEND bit.
void | HAL_PWR_PVD_IRQHandler (void)
This function handles the PWR PVD interrupt request.
__weak void | HAL_PWR_PVDCallback (void)
PWR PVD interrupt callback.

Detailed Description

PWR HAL module driver.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016 This file provides firmware functions to manage the following functionalities of the Power Controller (PWR) peripheral: + Initialization/de-initialization functions + Peripheral Control functions
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_pwr.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rcc.c File Reference

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Defines | Functions
stm32f1xx_hal_rcc.c File Reference

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define | MCO1_GPIO_PORT GPIOA
#define | MCO1_PIN GPIO_PIN_8

Functions

void | HAL_RCC_DeInit (void)
Resets the RCC clock configuration to the default reset state.
HAL_StatusTypeDef | HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.
HAL_StatusTypeDef | HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
Initializes the CPU, AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct.
void | HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
Selects the clock source to output on MCO pin.
void | HAL_RCC_EnableCSS (void)
Enables the Clock Security System.
void | HAL_RCC_DisableCSS (void)
Disables the Clock Security System.
uint32_t | HAL_RCC_GetSysClockFreq (void)
Returns the SYSCLK frequency.
uint32_t | HAL_RCC_GetHCLKFreq (void)
Returns the HCLK frequency.
uint32_t | HAL_RCC_GetPCLK1Freq (void)
Returns the PCLK1 frequency.
uint32_t | HAL_RCC_GetPCLK2Freq (void)
Returns the PCLK2 frequency.
void | HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
Configures the RCC_OscInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
void | HAL_RCC_NMI_IRQHandler (void)
This function handles the RCC CSS interrupt request.
__weak void | HAL_RCC_CSSCallback (void)
RCC Clock Security System interrupt callback.

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]
      After reset the device is running from Internal High Speed oscillator
      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
      and all peripherals are off except internal SRAM, Flash and JTAG.
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
          all peripherals mapped on these buses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in input floating state, except the JTAG pins which
          are assigned to be used for debug purpose.
    [..] Once the device started from reset, the user application has to:
      (+) Configure the clock source to be used to drive the System clock
          (if the application needs higher frequency/performance)
      (+) Configure the System clock frequency and Flash settings
      (+) Configure the AHB and APB buses prescalers
      (+) Enable the clock for the peripheral(s) to be used
      (+) Configure the clock source(s) for peripherals whose clocks are not
          derived from the System clock (I2S, RTC, ADC, USB OTG FS)

                      ##### RCC Limitations #####
  ==============================================================================
    [..]
      A delay between an RCC peripheral clock enable and the effective peripheral
      enabling should be taken into account in order to manage the peripheral read/write
      from/to registers.
      (+) This delay depends on the peripheral mapping.
        (++) AHB & APB peripherals, 1 dummy read is necessary

    [..]
      Workarounds:
      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_rcc.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rcc_ex.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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Functions
stm32f1xx_hal_rcc_ex.c File Reference

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RCCEx_PeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Initializes the RCC extended peripherals clocks according to the specified parameters in the RCC_PeriphCLKInitTypeDef.
void | HAL_RCCEx_GetPeriphCLKConfig (RCC_PeriphCLKInitTypeDef *PeriphClkInit)
Get the PeriphClkInit according to the internal RCC configuration registers.
uint32_t | HAL_RCCEx_GetPeriphCLKFreq (uint32_t PeriphClk)
Returns the peripheral clock frequency.

Detailed Description

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_rcc_ex.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rtc.c File Reference

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Defines | Functions
stm32f1xx_hal_rtc.c File Reference

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF
#define | RTC_ALARM_RESETVALUE 0xFFFFFFFFU

Functions

static uint32_t | RTC_ReadTimeCounter (RTC_HandleTypeDef *hrtc)
Read the time counter available in RTC_CNT registers.
static HAL_StatusTypeDef | RTC_WriteTimeCounter (RTC_HandleTypeDef *hrtc, uint32_t TimeCounter)
Write the time counter in RTC_CNT registers.
static uint32_t | RTC_ReadAlarmCounter (RTC_HandleTypeDef *hrtc)
Read the time counter available in RTC_ALR registers.
static HAL_StatusTypeDef | RTC_WriteAlarmCounter (RTC_HandleTypeDef *hrtc, uint32_t AlarmCounter)
Write the time counter in RTC_ALR registers.
static HAL_StatusTypeDef | RTC_EnterInitMode (RTC_HandleTypeDef *hrtc)
Enters the RTC Initialization mode.
static HAL_StatusTypeDef | RTC_ExitInitMode (RTC_HandleTypeDef *hrtc)
Exit the RTC Initialization mode.
static uint8_t | RTC_ByteToBcd2 (uint8_t Value)
Converts a 2 digit decimal to BCD format.
static uint8_t | RTC_Bcd2ToByte (uint8_t Value)
Converts from 2 digit BCD to Binary.
static uint8_t | RTC_IsLeapYear (uint16_t nYear)
Check whether the passed year is Leap or not.
static void | RTC_DateUpdate (RTC_HandleTypeDef *hrtc, uint32_t DayElapsed)
Updates date when time is 23:59:59.
static uint8_t | RTC_WeekDayNum (uint32_t nYear, uint8_t nMonth, uint8_t nDay)
Determines the week number, the day number and the week day number.
HAL_StatusTypeDef | HAL_RTC_Init (RTC_HandleTypeDef *hrtc)
Initializes the RTC peripheral.
HAL_StatusTypeDef | HAL_RTC_DeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC peripheral.
__weak void | HAL_RTC_MspInit (RTC_HandleTypeDef *hrtc)
Initializes the RTC MSP.
__weak void | HAL_RTC_MspDeInit (RTC_HandleTypeDef *hrtc)
DeInitializes the RTC MSP.
HAL_StatusTypeDef | HAL_RTC_SetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Sets RTC current time.
HAL_StatusTypeDef | HAL_RTC_GetTime (RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
Gets RTC current time.
HAL_StatusTypeDef | HAL_RTC_SetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Sets RTC current date.
HAL_StatusTypeDef | HAL_RTC_GetDate (RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
Gets RTC current date.
HAL_StatusTypeDef | HAL_RTC_SetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm.
HAL_StatusTypeDef | HAL_RTC_SetAlarm_IT (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
Sets the specified RTC Alarm with Interrupt.
HAL_StatusTypeDef | HAL_RTC_GetAlarm (RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
Gets the RTC Alarm value and masks.
HAL_StatusTypeDef | HAL_RTC_DeactivateAlarm (RTC_HandleTypeDef *hrtc, uint32_t Alarm)
Deactive the specified RTC Alarm.
void | HAL_RTC_AlarmIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Alarm interrupt request.
__weak void | HAL_RTC_AlarmAEventCallback (RTC_HandleTypeDef *hrtc)
Alarm A callback.
HAL_StatusTypeDef | HAL_RTC_PollForAlarmAEvent (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles AlarmA Polling request.
HAL_RTCStateTypeDef | HAL_RTC_GetState (RTC_HandleTypeDef *hrtc)
Returns the RTC state.
HAL_StatusTypeDef | HAL_RTC_WaitForSynchro (RTC_HandleTypeDef *hrtc)
Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) are synchronized with RTC APB clock.

Detailed Description

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                  ##### How to use this driver #####
  ==================================================================
  [..]
    (+) Enable the RTC domain access (see description in the section above).
    (+) Configure the RTC Prescaler (Asynchronous prescaler to generate RTC 1Hz time base)
        using the HAL_RTC_Init() function.

  *** Time and Date configuration ***
  ===================================
  [..]
    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
        and HAL_RTC_SetDate() functions.
    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.

  *** Alarm configuration ***
  ===========================
  [..]
    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
        You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.

  *** Tamper configuration ***
  ============================
  [..]
    (+) Enable the RTC Tamper and configure the Tamper Level using the
        HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
        mode using HAL_RTCEx_SetTamper_IT() function.
    (+) The TAMPER1 alternate function can be mapped to PC13

  *** Backup Data Registers configuration ***
  ===========================================
  [..]
    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
        function.
    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
        function.

                  ##### WARNING: Drivers Restrictions  #####
  ==================================================================
  [..] RTC version used on STM32F1 families is version V1. All the features supported by V2
       (other families) will be not supported on F1.
  [..] As on V2, main RTC features are managed by HW. But on F1, date feature is completely
       managed by SW.
  [..] Then, there are some restrictions compared to other families:
    (+) Only format 24 hours supported in HAL (format 12 hours not supported)
    (+) Date is saved in SRAM. Then, when MCU is in STOP or STANDBY mode, date will be lost.
        User should implement a way to save date before entering in low power mode (an
        example is provided with firmware package based on backup registers)
    (+) Date is automatically updated each time a HAL_RTC_GetTime or HAL_RTC_GetDate is called.
    (+) Alarm detection is limited to 1 day. It will expire only 1 time (no alarm repetition, need
        to program a new alarm)

              ##### Backup Domain Operating Condition #####
  ==============================================================================
  [..] The real-time clock (RTC) and the RTC backup registers can be powered
       from the VBAT voltage when the main VDD supply is powered off.
       To retain the content of the RTC backup registers and supply the RTC
       when VDD is turned off, VBAT pin can be connected to an optional
       standby voltage supplied by a battery or by another source.

  [..] To allow the RTC operating even when the main digital supply (VDD) is turned
       off, the VBAT pin powers the following blocks:
    (+) The RTC
    (+) The LSE oscillator
    (+) PC13 I/O

  [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
       the following pins are available:
    (+) PC13 can be used as a Tamper pin

  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
       because VDD is not present), the following pins are available:
    (+) PC13 can be used as the Tamper pin

                   ##### Backup Domain Reset #####
  ==================================================================
  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
       to their reset values.
  [..] A backup domain reset is generated when one of the following events occurs:
    (#) Software reset, triggered by setting the BDRST bit in the
        RCC Backup domain control register (RCC_BDCR).
    (#) VDD or VBAT power on, if both supplies have previously been powered off.
    (#) Tamper detection event resets all data backup registers.

                   ##### Backup Domain Access #####
  ==================================================================
  [..] After reset, the backup domain (RTC registers, RTC backup data
       registers and backup SRAM) is protected against possible unwanted write
       accesses.
  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
    (+) Call the function HAL_RCCEx_PeriphCLKConfig in using RCC_PERIPHCLK_RTC for
        PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSE)
    (+) Enable the BKP clock in using __HAL_RCC_BKP_CLK_ENABLE()

                  ##### RTC and low power modes #####
  ==================================================================
  [..] The MCU can be woken up from a low power mode by an RTC alternate
       function.
  [..] The RTC alternate functions are the RTC alarms (Alarm A),
       and RTC tamper event detection.
       These RTC alternate functions can wake up the system from the Stop and
       Standby low power modes.
  [..] The system can also wake up from low power modes without depending
       on an external interrupt (Auto-wakeup mode), by using the RTC alarm.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_rtc.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rtc_ex.c File Reference

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  • STM32F1xx_HAL_Driver
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Functions
stm32f1xx_hal_rtc_ex.c File Reference

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Tamper functions + Extension Control functions + Extension RTC features functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_RTCEx_SetTamper (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper.
HAL_StatusTypeDef | HAL_RTCEx_SetTamper_IT (RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
Sets Tamper with interrupt.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateTamper (RTC_HandleTypeDef *hrtc, uint32_t Tamper)
Deactivates Tamper.
void | HAL_RTCEx_TamperIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles Tamper interrupt request.
__weak void | HAL_RTCEx_Tamper1EventCallback (RTC_HandleTypeDef *hrtc)
Tamper 1 callback.
HAL_StatusTypeDef | HAL_RTCEx_PollForTamper1Event (RTC_HandleTypeDef *hrtc, uint32_t Timeout)
This function handles Tamper1 Polling.
HAL_StatusTypeDef | HAL_RTCEx_SetSecond_IT (RTC_HandleTypeDef *hrtc)
Sets Interrupt for second.
HAL_StatusTypeDef | HAL_RTCEx_DeactivateSecond (RTC_HandleTypeDef *hrtc)
Deactivates Second.
void | HAL_RTCEx_RTCIRQHandler (RTC_HandleTypeDef *hrtc)
This function handles second interrupt request.
__weak void | HAL_RTCEx_RTCEventCallback (RTC_HandleTypeDef *hrtc)
Second event callback.
__weak void | HAL_RTCEx_RTCEventErrorCallback (RTC_HandleTypeDef *hrtc)
Second event error callback.
void | HAL_RTCEx_BKUPWrite (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
Writes a data in a specified RTC Backup data register.
uint32_t | HAL_RTCEx_BKUPRead (RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
Reads data from the specified RTC Backup data Register.
HAL_StatusTypeDef | HAL_RTCEx_SetSmoothCalib (RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
Sets the Smooth calibration parameters.

Detailed Description

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Tamper functions + Extension Control functions + Extension RTC features functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_rtc_ex.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_smartcard.c File Reference

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Functions
stm32f1xx_hal_smartcard.c File Reference

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

static void | SMARTCARD_EndTxTransfer (SMARTCARD_HandleTypeDef *hsc)
End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
static void | SMARTCARD_EndRxTransfer (SMARTCARD_HandleTypeDef *hsc)
End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
static void | SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc)
Configure the SMARTCARD peripheral.
static HAL_StatusTypeDef | SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc)
Send an amount of data in non blocking mode.
static HAL_StatusTypeDef | SMARTCARD_EndTransmit_IT (SMARTCARD_HandleTypeDef *hsmartcard)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc)
Receive an amount of data in non blocking mode.
static void | SMARTCARD_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD transmit process complete callback.
static void | SMARTCARD_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SMARTCARD receive process complete callback.
static void | SMARTCARD_DMAError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication error callback.
static void | SMARTCARD_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SMARTCARD communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SMARTCARD_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SMARTCARD_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | SMARTCARD_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | SMARTCARD_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | SMARTCARD_WaitOnFlagUntilTimeout (SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles SMARTCARD Communication Timeout.
HAL_StatusTypeDef | HAL_SMARTCARD_Init (SMARTCARD_HandleTypeDef *hsc)
Initializes the SmartCard mode according to the specified parameters in the SMARTCARD_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_SMARTCARD_DeInit (SMARTCARD_HandleTypeDef *hsc)
DeInitializes the USART SmartCard peripheral.
__weak void | HAL_SMARTCARD_MspInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP Init.
__weak void | HAL_SMARTCARD_MspDeInit (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD MSP DeInit.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_IT (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Transmit_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Send an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Receive_DMA (SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
Receive an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_SMARTCARD_Abort (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_SMARTCARD_Abort_IT (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortTransmit_IT (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SMARTCARD_AbortReceive_IT (SMARTCARD_HandleTypeDef *hsc)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_SMARTCARD_IRQHandler (SMARTCARD_HandleTypeDef *hsc)
This function handles SMARTCARD interrupt request.
__weak void | HAL_SMARTCARD_TxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Tx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_RxCpltCallback (SMARTCARD_HandleTypeDef *hsc)
Rx Transfer completed callbacks.
__weak void | HAL_SMARTCARD_ErrorCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD error callbacks.
__weak void | HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD Abort Complete callback.
__weak void | HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD Abort Transmit Complete callback.
__weak void | HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
SMARTCARD Abort ReceiveComplete callback.
HAL_SMARTCARD_StateTypeDef | HAL_SMARTCARD_GetState (SMARTCARD_HandleTypeDef *hsc)
return the SMARTCARD state
uint32_t | HAL_SMARTCARD_GetError (SMARTCARD_HandleTypeDef *hsc)
Return the SMARTCARD error code.

Detailed Description

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.5.0
Date:
06-May-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The SMARTCARD HAL driver can be used as follows:

    (#) Declare a SMARTCARD_HandleTypeDef handle structure.
    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
        (##) Enable the USARTx interface clock.
        (##) SMARTCARD pins configuration:
            (+++) Enable the clock for the SMARTCARD GPIOs.
            (+++) Configure the SMARTCARD pins as alternate function pull-up.
        (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
             and HAL_SMARTCARD_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
             and HAL_SMARTCARD_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
                  (used for last byte sending completion detection in DMA non circular mode)

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
        flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.

    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
        (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_SMARTCARD_MspInit() API.
     [..]
       (@)The specific SMARTCARD interrupts (Transmission complete interrupt,
          RXNE interrupt and Error Interrupts) will be managed using the macros
          __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.

     [..]
        Three operation modes are available within this driver:

    *** Polling mode IO operation ***
    =================================
    [..]
      (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
      (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
    *** Interrupt mode IO operation ***
    ===================================
    [..]
      (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
      (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback

    *** DMA mode IO operation ***
    ==============================
    [..]
      (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
      (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
      (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
      (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
      (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
          add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback

    *** SMARTCARD HAL driver macros list ***
    =============================================
    [..]
      Below the list of most used macros in SMARTCARD HAL driver.

      (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
      (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
      (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
      (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
      (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
      (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt

    [..]
      (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
[..] (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), the possible SMARTCARD frame formats are as listed in the following table: +-------------------------------------------------------------+ | M bit | PCE bit | SMARTCARD frame | |---------------------|---------------------------------------| | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_smartcard.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_spi.c File Reference

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Defines | Functions
stm32f1xx_hal_spi.c File Reference

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | SPI_DEFAULT_TIMEOUT 100U

Functions

static void | SPI_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit process complete callback.
static void | SPI_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI receive process complete callback.
static void | SPI_DMATransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI transmit receive process complete callback.
static void | SPI_DMAHalfTransmitCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit process complete callback.
static void | SPI_DMAHalfReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half receive process complete callback.
static void | SPI_DMAHalfTransmitReceiveCplt (DMA_HandleTypeDef *hdma)
DMA SPI half transmit receive process complete callback.
static void | SPI_DMAError (DMA_HandleTypeDef *hdma)
DMA SPI communication error callback.
static void | SPI_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA SPI communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | SPI_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | SPI_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA SPI Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | SPI_WaitFlagStateUntilTimeout (SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
Handle SPI Communication Timeout.
static void | SPI_TxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 8-bit transmit in Interrupt mode.
static void | SPI_TxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Handle the data 16-bit transmit in Interrupt mode.
static void | SPI_RxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Manage the receive 8-bit in Interrupt context.
static void | SPI_RxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Manage the 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_8BIT (struct __SPI_HandleTypeDef *hspi)
Tx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesTxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Tx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BIT (struct __SPI_HandleTypeDef *hspi)
Rx 16-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_RxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 8-bit receive in Interrupt context.
static void | SPI_RxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive in Interrupt context.
static void | SPI_2linesRxISR_8BITCRC (struct __SPI_HandleTypeDef *hspi)
Rx 8-bit handler for Transmit and Receive in Interrupt mode.
static void | SPI_2linesRxISR_16BITCRC (struct __SPI_HandleTypeDef *hspi)
Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
static void | SPI_AbortRx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx transaction.
static void | SPI_AbortTx_ISR (SPI_HandleTypeDef *hspi)
Handle abort a Tx or Rx transaction.
static void | SPI_CloseRxTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RXTX transaction.
static void | SPI_CloseRx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the RX transaction.
static void | SPI_CloseTx_ISR (SPI_HandleTypeDef *hspi)
Handle the end of the TX transaction.
static HAL_StatusTypeDef | SPI_CheckFlag_BSY (SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
Handle to check BSY flag before start a new transaction.
__weak HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
HAL_StatusTypeDef | HAL_SPI_DeInit (SPI_HandleTypeDef *hspi)
De Initialize the SPI peripheral.
__weak void | HAL_SPI_MspInit (SPI_HandleTypeDef *hspi)
Initialize the SPI MSP.
__weak void | HAL_SPI_MspDeInit (SPI_HandleTypeDef *hspi)
De-Initialize the SPI MSP.
HAL_StatusTypeDef | HAL_SPI_Transmit (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmit an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Transmit and Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_SPI_Transmit_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_IT (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with Interrupt.
HAL_StatusTypeDef | HAL_SPI_Transmit_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Transmit an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_TransmitReceive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Transmit and Receive an amount of data in non-blocking mode with DMA.
HAL_StatusTypeDef | HAL_SPI_Abort (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_SPI_Abort_IT (SPI_HandleTypeDef *hspi)
Abort ongoing transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_SPI_DMAPause (SPI_HandleTypeDef *hspi)
Pause the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAResume (SPI_HandleTypeDef *hspi)
Resume the DMA Transfer.
HAL_StatusTypeDef | HAL_SPI_DMAStop (SPI_HandleTypeDef *hspi)
Stop the DMA Transfer.
void | HAL_SPI_IRQHandler (SPI_HandleTypeDef *hspi)
Handle SPI interrupt request.
__weak void | HAL_SPI_TxCpltCallback (SPI_HandleTypeDef *hspi)
Tx Transfer completed callback.
__weak void | HAL_SPI_RxCpltCallback (SPI_HandleTypeDef *hspi)
Rx Transfer completed callback.
__weak void | HAL_SPI_TxRxCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Transfer completed callback.
__weak void | HAL_SPI_TxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx Half Transfer completed callback.
__weak void | HAL_SPI_RxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Rx Half Transfer completed callback.
__weak void | HAL_SPI_TxRxHalfCpltCallback (SPI_HandleTypeDef *hspi)
Tx and Rx Half Transfer callback.
__weak void | HAL_SPI_ErrorCallback (SPI_HandleTypeDef *hspi)
SPI error callback.
__weak void | HAL_SPI_AbortCpltCallback (SPI_HandleTypeDef *hspi)
SPI Abort Complete callback.
HAL_SPI_StateTypeDef | HAL_SPI_GetState (SPI_HandleTypeDef *hspi)
Return the SPI handle state.
uint32_t | HAL_SPI_GetError (SPI_HandleTypeDef *hspi)
Return the SPI error code.
__weak uint8_t | SPI_ISCRCErrorValid (SPI_HandleTypeDef *hspi)
Checks if encountered CRC error could be corresponding to wrongly detected errors according to SPI instance, Device type, and revision ID.

Detailed Description

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
    [..]
      The SPI HAL driver can be used as follows:

      (#) Declare a SPI_HandleTypeDef handle structure, for example:
          SPI_HandleTypeDef  hspi;

      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
          (##) Enable the SPIx interface clock
          (##) SPI pins configuration
              (+++) Enable the clock for the SPI GPIOs
              (+++) Configure these SPI pins as alternate function push-pull
          (##) NVIC configuration if you need to use interrupt process
              (+++) Configure the SPIx interrupt priority
              (+++) Enable the NVIC SPI IRQ handle
          (##) DMA Configuration if you need to use DMA process
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
              (+++) Enable the DMAx clock
              (+++) Configure the DMA handle parameters
              (+++) Configure the DMA Tx or Rx Channel
              (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel

      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
              by calling the customized HAL_SPI_MspInit() API.
     [..]
       Circular mode restriction:
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
          (##) Master 2Lines RxOnly
          (##) Master 1Line Rx
      (#) The CRC feature is not managed when the DMA circular mode is enabled
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
     [..]
       Master Receive mode restriction:
      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
          does not initiate a new transfer the following procedure has to be respected:
          (##) HAL_SPI_DeInit()
          (##) HAL_SPI_Init()

Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, the following tables resume the max SPI frequency reached with data size 8bits/16bits, according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :

DataSize = SPI_DATASIZE_8BIT: +--------------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==================================================================================================| | T | Polling | fPCLK/8 | fPCLK/8 | NA | NA | NA | NA | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA | | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | |=========|================|===========|===========|===========|===========|===========|===========| | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/8 | | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | R | Interrupt | fPCLK/32 | fPCLK/16 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/16 | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/2 | |=========|================|===========|===========|===========|===========|===========|===========| | | Polling | fPCLK/4 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/64 | | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/128 | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | +--------------------------------------------------------------------------------------------------+

DataSize = SPI_DATASIZE_16BIT: +--------------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==================================================================================================| | T | Polling | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | / | Interrupt | fPCLK/16 | fPCLK/16 | NA | NA | NA | NA | | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | |=========|================|===========|===========|===========|===========|===========|===========| | | Polling | fPCLK/2 | fPCLK/4 | fPCLK/64 | fPCLK/8 | fPCLK/64 | fPCLK/4 | | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | R | Interrupt | fPCLK/16 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/8 | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/2 | |=========|================|===========|===========|===========|===========|===========|===========| | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/256 | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 | +--------------------------------------------------------------------------------------------------+ [..] (@) The max SPI frequency depend on SPI data size (8bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). (@) (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()

Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_spi.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_spi_ex.c File Reference

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Functions | Variables
stm32f1xx_hal_spi_ex.c File Reference

Extended SPI HAL module driver. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

__weak HAL_StatusTypeDef | HAL_SPI_Init (SPI_HandleTypeDef *hspi)
Initialize the SPI according to the specified parameters in the SPI_InitTypeDef and initialize the associated handle.
uint8_t | SPI_ISCRCErrorValid (SPI_HandleTypeDef *hspi)
Checks if encountered CRC error could be corresponding to wrongly detected errors according to SPI instance, Device type, and revision ID.

Variables

uint8_t | uCRCErrorWorkaroundCheck = 0U

Detailed Description

Extended SPI HAL module driver.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016 This file provides firmware functions to manage the following functionalities SPI extension peripheral: + Extended Peripheral Control functions
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_spi_ex.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_tim.c File Reference

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stm32f1xx_hal_tim.c File Reference

TIM HAL module driver This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_OC1_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 1 configuration.
static void | TIM_OC3_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 3 configuration.
static void | TIM_OC4_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 4 configuration.
static void | TIM_TI1_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI1.
static void | TIM_TI2_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI2 as Input.
static void | TIM_TI2_ConfigInputStage (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
Configure the Polarity and Filter for TI2.
static void | TIM_TI3_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI3 as Input.
static void | TIM_TI4_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI4 as Input.
static void | TIM_ETR_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
Configures the TIMx External Trigger (ETR).
static void | TIM_ITRx_SetConfig (TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
Selects the Input Trigger source.
static void | TIM_DMAPeriodElapsedCplt (DMA_HandleTypeDef *hdma)
TIM DMA Period Elapse complete callback.
static void | TIM_DMATriggerCplt (DMA_HandleTypeDef *hdma)
TIM DMA Trigger callback.
static void | TIM_SlaveTimer_SetConfig (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Time Slave configuration.
HAL_StatusTypeDef | HAL_TIM_Base_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Time base Unit according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Base_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Base peripheral.
__weak void | HAL_TIM_Base_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Base MSP.
__weak void | HAL_TIM_Base_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Base MSP.
HAL_StatusTypeDef | HAL_TIM_Base_Start (TIM_HandleTypeDef *htim)
Starts the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Base generation.
HAL_StatusTypeDef | HAL_TIM_Base_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Base_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Base_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Base generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_OC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Output Compare MSP.
__weak void | HAL_TIM_OC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Output Compare MSP.
HAL_StatusTypeDef | HAL_TIM_OC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation.
HAL_StatusTypeDef | HAL_TIM_OC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Init (TIM_HandleTypeDef *htim)
Initializes the TIM PWM Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_PWM_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_PWM_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM PWM MSP.
__weak void | HAL_TIM_PWM_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM PWM MSP.
HAL_StatusTypeDef | HAL_TIM_PWM_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_PWM_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Init (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture Time base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_IC_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM peripheral.
__weak void | HAL_TIM_IC_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Input Capture MSP.
__weak void | HAL_TIM_IC_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Input Capture MSP.
HAL_StatusTypeDef | HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement.
HAL_StatusTypeDef | HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_IC_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_IC_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Input Capture measurement in DMA mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Init (TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
Initializes the TIM One Pulse Time Base according to the specified parameters in the TIM_HandleTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_OnePulse_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM One Pulse.
__weak void | HAL_TIM_OnePulse_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM One Pulse MSP.
__weak void | HAL_TIM_OnePulse_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM One Pulse MSP.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_OnePulse_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Init (TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
Initializes the TIM Encoder Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIM_Encoder_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Encoder interface.
__weak void | HAL_TIM_Encoder_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Encoder Interface MSP.
__weak void | HAL_TIM_Encoder_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Encoder Interface MSP.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
Starts the TIM Encoder Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIM_Encoder_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Encoder Interface in DMA mode.
void | HAL_TIM_IRQHandler (TIM_HandleTypeDef *htim)
This function handles TIM interrupts requests.
HAL_StatusTypeDef | HAL_TIM_OC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Output Compare Channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_IC_ConfigChannel (TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM Input Capture Channels according to the specified parameters in the TIM_IC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_PWM_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel)
Initializes the TIM PWM channels according to the specified parameters in the TIM_OC_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_OnePulse_ConfigChannel (TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
Initializes the TIM One Pulse Channels according to the specified parameters in the TIM_OnePulse_InitTypeDef.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the memory to the TIM peripheral.
HAL_StatusTypeDef | HAL_TIM_DMABurst_WriteStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stops the TIM DMA Burst mode.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStart (TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
Configure the DMA Burst to transfer Data from the TIM peripheral to the memory.
HAL_StatusTypeDef | HAL_TIM_DMABurst_ReadStop (TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
Stop the DMA burst reading.
HAL_StatusTypeDef | HAL_TIM_GenerateEvent (TIM_HandleTypeDef *htim, uint32_t EventSource)
Generate a software event.
HAL_StatusTypeDef | HAL_TIM_ConfigOCrefClear (TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel)
Configures the OCRef clear feature.
HAL_StatusTypeDef | HAL_TIM_ConfigClockSource (TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
Configures the clock source to be used.
HAL_StatusTypeDef | HAL_TIM_ConfigTI1Input (TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode.
HAL_StatusTypeDef | HAL_TIM_SlaveConfigSynchronization_IT (TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
Configures the TIM in Slave mode in interrupt mode.
uint32_t | HAL_TIM_ReadCapturedValue (TIM_HandleTypeDef *htim, uint32_t Channel)
Read the captured value from Capture Compare unit.
__weak void | HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
__weak void | HAL_TIM_OC_DelayElapsedCallback (TIM_HandleTypeDef *htim)
Output Compare callback in non blocking mode.
__weak void | HAL_TIM_IC_CaptureCallback (TIM_HandleTypeDef *htim)
Input Capture callback in non blocking mode.
__weak void | HAL_TIM_PWM_PulseFinishedCallback (TIM_HandleTypeDef *htim)
PWM Pulse finished callback in non blocking mode.
__weak void | HAL_TIM_TriggerCallback (TIM_HandleTypeDef *htim)
Hall Trigger detection callback in non blocking mode.
__weak void | HAL_TIM_ErrorCallback (TIM_HandleTypeDef *htim)
Timer error callback in non blocking mode.
HAL_TIM_StateTypeDef | HAL_TIM_Base_GetState (TIM_HandleTypeDef *htim)
Return the TIM Base state.
HAL_TIM_StateTypeDef | HAL_TIM_OC_GetState (TIM_HandleTypeDef *htim)
Return the TIM OC state.
HAL_TIM_StateTypeDef | HAL_TIM_PWM_GetState (TIM_HandleTypeDef *htim)
Return the TIM PWM state.
HAL_TIM_StateTypeDef | HAL_TIM_IC_GetState (TIM_HandleTypeDef *htim)
Return the TIM Input Capture state.
HAL_TIM_StateTypeDef | HAL_TIM_OnePulse_GetState (TIM_HandleTypeDef *htim)
Return the TIM One Pulse Mode state.
HAL_TIM_StateTypeDef | HAL_TIM_Encoder_GetState (TIM_HandleTypeDef *htim)
Return the TIM Encoder Mode state.
void | TIM_DMAError (DMA_HandleTypeDef *hdma)
TIM DMA error callback.
void | TIM_DMADelayPulseCplt (DMA_HandleTypeDef *hdma)
TIM DMA Delay Pulse complete callback.
void | TIM_DMACaptureCplt (DMA_HandleTypeDef *hdma)
TIM DMA Capture complete callback.
void | TIM_Base_SetConfig (TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
Time Base configuration.
void | TIM_OC2_SetConfig (TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
Time Ouput Compare 2 configuration.
void | TIM_TI1_SetConfig (TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter)
Configure the TI1 as Input.
void | TIM_CCxChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
Enables or disables the TIM Capture Compare Channel x.

Detailed Description

TIM HAL module driver This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                      ##### TIMER Generic features #####
  ==============================================================================
  [..] The Timer features include:
       (#) 16-bit up, down, up/down auto-reload counter.
       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
           counter clock frequency either by any factor between 1 and 65536.
       (#) Up to 4 independent channels for:
           (++) Input Capture
           (++) Output Compare
           (++) PWM generation (Edge and Center-aligned Mode)
           (++) One-pulse mode output

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending from feature used :
           (++) Time Base : HAL_TIM_Base_MspInit()
           (++) Input Capture : HAL_TIM_IC_MspInit()
           (++) Output Compare : HAL_TIM_OC_MspInit()
           (++) PWM generation : HAL_TIM_PWM_MspInit()
           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
             __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
       Initialization function of this driver:
       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
            Output Compare signal.
       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
            PWM signal.
       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
            external signal.
         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
              in One Pulse Mode.
       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.

     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().

     (#) The DMA Burst is managed with the two following functions:
         HAL_TIM_DMABurst_WriteStart()
         HAL_TIM_DMABurst_ReadStart()
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_tim.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_tim_ex.c File Reference

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stm32f1xx_hal_tim_ex.c File Reference

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Timer remapping capabilities configuration. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

static void | TIM_CCxNChannelCmd (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
Enables or disables the TIM Capture Compare Channel xN.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Init (TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Initializes the TIM Hall Sensor Interface and create the associated handle.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_DeInit (TIM_HandleTypeDef *htim)
DeInitializes the TIM Hall Sensor interface.
__weak void | HAL_TIMEx_HallSensor_MspInit (TIM_HandleTypeDef *htim)
Initializes the TIM Hall Sensor MSP.
__weak void | HAL_TIMEx_HallSensor_MspDeInit (TIM_HandleTypeDef *htim)
DeInitializes TIM Hall Sensor MSP.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop (TIM_HandleTypeDef *htim)
Stops the TIM Hall sensor Interface.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_IT (TIM_HandleTypeDef *htim)
Starts the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_IT (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in interrupt mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Start_DMA (TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
Starts the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_HallSensor_Stop_DMA (TIM_HandleTypeDef *htim)
Stops the TIM Hall Sensor Interface in DMA mode.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OCN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM Output Compare signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Starts the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the PWM signal generation in interrupt mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Start_DMA (TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
Starts the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_PWMN_Stop_DMA (TIM_HandleTypeDef *htim, uint32_t Channel)
Stops the TIM PWM signal generation in DMA mode on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation on the complemetary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation on the complementary output.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Start_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Starts the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_OnePulseN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t OutputChannel)
Stops the TIM One Pulse signal generation in interrupt mode on the complementary channel.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_IT (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with interrupt.
HAL_StatusTypeDef | HAL_TIMEx_ConfigCommutationEvent_DMA (TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
Configure the TIM commutation event sequence with DMA.
HAL_StatusTypeDef | HAL_TIMEx_ConfigBreakDeadTime (TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable).
HAL_StatusTypeDef | HAL_TIMEx_MasterConfigSynchronization (TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig)
Configures the TIM in master mode.
__weak void | HAL_TIMEx_CommutationCallback (TIM_HandleTypeDef *htim)
Hall commutation changed callback in non blocking mode.
__weak void | HAL_TIMEx_BreakCallback (TIM_HandleTypeDef *htim)
Hall Break detection callback in non blocking mode.
void | TIMEx_DMACommutationCplt (DMA_HandleTypeDef *hdma)
TIM DMA Commutation callback.
HAL_TIM_StateTypeDef | HAL_TIMEx_HallSensor_GetState (TIM_HandleTypeDef *htim)
Return the TIM Hall Sensor interface state.

Detailed Description

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Timer remapping capabilities configuration.

Author:
MCD Application Team
Version:
V1.0.5
Date:
06-December-2016
  ==============================================================================
                      ##### TIMER Extended features #####
  ==============================================================================
  [..]
    The Timer Extended features include:
    (#) Complementary outputs with programmable dead-time for :
        (++) Output Compare
        (++) PWM generation (Edge and Center-aligned Mode)
        (++) One-pulse mode output
    (#) Synchronization circuit to control the timer with external signals and to
        interconnect several timers together.
    (#) Break input to put the timer output signals in reset state or in a known state.
    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
        positioning purposes

            ##### How to use this driver #####
  ==============================================================================
    [..]
     (#) Initialize the TIM low level resources by implementing the following functions
         depending from feature used :
           (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
           (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
           (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()

     (#) Initialize the TIM low level resources :
        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
        (##) TIM pins configuration
            (+++) Enable the clock for the TIM GPIOs using the following function:
              __HAL_RCC_GPIOx_CLK_ENABLE();
            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();

     (#) The external Clock can be configured, if needed (the default clock is the
         internal clock from the APBx), using the following function:
         HAL_TIM_ConfigClockSource, the clock configuration should be done before
         any start function.

     (#) Configure the TIM in the desired functioning mode using one of the
         initialization function of this driver:
          (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
              Timer Hall Sensor Interface and the commutation event with the corresponding
              Interrupt and DMA request if needed (Note that One Timer is used to interface
             with the Hall sensor Interface and another Timer should be used to use
             the commutation event).

     (#) Activate the TIM peripheral using one of the start functions:
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_tim_ex.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_uart.c File Reference

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stm32f1xx_hal_uart.c File Reference

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

static void | UART_EndTxTransfer (UART_HandleTypeDef *huart)
End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
static void | UART_EndRxTransfer (UART_HandleTypeDef *huart)
End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
static void | UART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process complete callback.
static void | UART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process complete callback.
static void | UART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART transmit process half complete callback.
static void | UART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA UART receive process half complete callback.
static void | UART_DMAError (DMA_HandleTypeDef *hdma)
DMA UART communication error callback.
static void | UART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA UART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | UART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | UART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static void | UART_DMATxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Tx communication abort callback, when initiated by user by a call to HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) (This callback is executed at end of DMA Tx Abort procedure following user abort request, and leads to user Tx Abort Complete callback execution).
static void | UART_DMARxOnlyAbortCallback (DMA_HandleTypeDef *hdma)
DMA UART Rx communication abort callback, when initiated by user by a call to HAL_UART_AbortReceive_IT API (Abort only Rx transfer) (This callback is executed at end of DMA Rx Abort procedure following user abort request, and leads to user Rx Abort Complete callback execution).
static HAL_StatusTypeDef | UART_Transmit_IT (UART_HandleTypeDef *huart)
Sends an amount of data in non blocking mode.
static HAL_StatusTypeDef | UART_EndTransmit_IT (UART_HandleTypeDef *huart)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | UART_Receive_IT (UART_HandleTypeDef *huart)
Receives an amount of data in non blocking mode.
static HAL_StatusTypeDef | UART_WaitOnFlagUntilTimeout (UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles UART Communication Timeout.
static void | UART_SetConfig (UART_HandleTypeDef *huart)
Configures the UART peripheral.
HAL_StatusTypeDef | HAL_UART_Init (UART_HandleTypeDef *huart)
Initializes the UART mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_HalfDuplex_Init (UART_HandleTypeDef *huart)
Initializes the half-duplex mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_LIN_Init (UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
Initializes the LIN mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_MultiProcessor_Init (UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
Initializes the Multi-Processor mode according to the specified parameters in the UART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_UART_DeInit (UART_HandleTypeDef *huart)
DeInitializes the UART peripheral.
__weak void | HAL_UART_MspInit (UART_HandleTypeDef *huart)
UART MSP Init.
__weak void | HAL_UART_MspDeInit (UART_HandleTypeDef *huart)
UART MSP DeInit.
HAL_StatusTypeDef | HAL_UART_Transmit (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Sends an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_IT (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Transmit_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Sends an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_Receive_DMA (UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
Receives an amount of data in non blocking mode.
HAL_StatusTypeDef | HAL_UART_DMAPause (UART_HandleTypeDef *huart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAResume (UART_HandleTypeDef *huart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_DMAStop (UART_HandleTypeDef *huart)
Stops the DMA Transfer.
HAL_StatusTypeDef | HAL_UART_Abort (UART_HandleTypeDef *huart)
Abort ongoing transfers (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (blocking mode).
HAL_StatusTypeDef | HAL_UART_Abort_IT (UART_HandleTypeDef *huart)
Abort ongoing transfers (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortTransmit_IT (UART_HandleTypeDef *huart)
Abort ongoing Transmit transfer (Interrupt mode).
HAL_StatusTypeDef | HAL_UART_AbortReceive_IT (UART_HandleTypeDef *huart)
Abort ongoing Receive transfer (Interrupt mode).
void | HAL_UART_IRQHandler (UART_HandleTypeDef *huart)
This function handles UART interrupt request.
__weak void | HAL_UART_TxCpltCallback (UART_HandleTypeDef *huart)
Tx Transfer completed callbacks.
__weak void | HAL_UART_TxHalfCpltCallback (UART_HandleTypeDef *huart)
Tx Half Transfer completed callbacks.
__weak void | HAL_UART_RxCpltCallback (UART_HandleTypeDef *huart)
Rx Transfer completed callbacks.
__weak void | HAL_UART_RxHalfCpltCallback (UART_HandleTypeDef *huart)
Rx Half Transfer completed callbacks.
__weak void | HAL_UART_ErrorCallback (UART_HandleTypeDef *huart)
UART error callbacks.
__weak void | HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
UART Abort Complete callback.
__weak void | HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
UART Abort Receive Complete callback.
HAL_StatusTypeDef | HAL_LIN_SendBreak (UART_HandleTypeDef *huart)
Transmits break characters.
HAL_StatusTypeDef | HAL_MultiProcessor_EnterMuteMode (UART_HandleTypeDef *huart)
Enters the UART in mute mode.
HAL_StatusTypeDef | HAL_MultiProcessor_ExitMuteMode (UART_HandleTypeDef *huart)
Exits the UART mute mode: wake up software.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableTransmitter (UART_HandleTypeDef *huart)
Enables the UART transmitter and disables the UART receiver.
HAL_StatusTypeDef | HAL_HalfDuplex_EnableReceiver (UART_HandleTypeDef *huart)
Enables the UART receiver and disables the UART transmitter.
HAL_UART_StateTypeDef | HAL_UART_GetState (UART_HandleTypeDef *huart)
Returns the UART state.
uint32_t | HAL_UART_GetError (UART_HandleTypeDef *huart)
Return the UART error code.

Detailed Description

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

Author:
MCD Application Team
Version:
V1.5.0
Date:
13-february-2017
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The UART HAL driver can be used as follows:

    (#) Declare a UART_HandleTypeDef handle structure.
    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
        (##) Enable the USARTx interface clock.
        (##) UART pins configuration:
            (+++) Enable the clock for the UART GPIOs.
            (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input).
        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
             and HAL_UART_Receive_IT() APIs):
            (+++) Configure the USARTx interrupt priority.
            (+++) Enable the NVIC USART IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
             and HAL_UART_Receive_DMA() APIs):
            (+++) Declare a DMA handle structure for the Tx/Rx channel.
            (+++) Enable the DMAx interface clock.
            (+++) Configure the declared DMA handle structure with the required
                  Tx/Rx parameters.
            (+++) Configure the DMA Tx/Rx channel.
            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
            (+++) Configure the priority and enable the NVIC for the transfer complete
                  interrupt on the DMA Tx/Rx channel.
            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
                  (used for last byte sending completion detection in DMA non circular mode)

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
        flow control and Mode(Receiver/Transmitter) in the huart Init structure.

    (#) For the UART asynchronous mode, initialize the UART registers by calling
        the HAL_UART_Init() API.

    (#) For the UART Half duplex mode, initialize the UART registers by calling
        the HAL_HalfDuplex_Init() API.

    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.

    (#) For the Multi-Processor mode, initialize the UART registers by calling
        the HAL_MultiProcessor_Init() API.

     [..]
       (@) The specific UART interrupts (Transmission complete interrupt,
            RXNE interrupt and Error Interrupts) will be managed using the macros
            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
            and receive process.

     [..]
       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
            HAL_UART_MspInit() API.

     [..]
        Three operation modes are available within this driver:

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxCpltCallback
       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_UART_ErrorCallback

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_UART_RxCpltCallback
       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_UART_ErrorCallback
       (+) Pause the DMA Transfer using HAL_UART_DMAPause()
       (+) Resume the DMA Transfer using HAL_UART_DMAResume()
       (+) Stop the DMA Transfer using HAL_UART_DMAStop()

     *** UART HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in UART HAL driver.

      (+) __HAL_UART_ENABLE: Enable the UART peripheral
      (+) __HAL_UART_DISABLE: Disable the UART peripheral
      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not

     [..]
       (@) You can refer to the UART HAL driver header file for more useful macros
[..] (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), the possible UART frame formats are as listed in the following table: +-------------------------------------------------------------+ | M bit | PCE bit | UART frame | |---------------------|---------------------------------------| | 0 | 0 | | SB | 8 bit data | STB | | |---------|-----------|---------------------------------------| | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|-----------|---------------------------------------| | 1 | 0 | | SB | 9 bit data | STB | | |---------|-----------|---------------------------------------| | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_uart.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_usart.c File Reference

  • File List
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  • STM32F1xx_HAL_Driver
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Defines | Functions
stm32f1xx_hal_usart.c File Reference

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Defines

#define | DUMMY_DATA 0xFFFFU
#define | USART_TIMEOUT_VALUE 22000U

Functions

static void | USART_EndTxTransfer (USART_HandleTypeDef *husart)
End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
static void | USART_EndRxTransfer (USART_HandleTypeDef *husart)
End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
static HAL_StatusTypeDef | USART_Transmit_IT (USART_HandleTypeDef *husart)
Simplex Send an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_EndTransmit_IT (USART_HandleTypeDef *husart)
Wraps up transmission in non blocking mode.
static HAL_StatusTypeDef | USART_Receive_IT (USART_HandleTypeDef *husart)
Simplex Receive an amount of data in non-blocking mode.
static HAL_StatusTypeDef | USART_TransmitReceive_IT (USART_HandleTypeDef *husart)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
static void | USART_SetConfig (USART_HandleTypeDef *husart)
Configures the USART pferipheral.
static void | USART_DMATransmitCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process complete callback.
static void | USART_DMATxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART transmit process half complete callback.
static void | USART_DMAReceiveCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process complete callback.
static void | USART_DMARxHalfCplt (DMA_HandleTypeDef *hdma)
DMA USART receive process half complete callback.
static void | USART_DMAError (DMA_HandleTypeDef *hdma)
DMA USART communication error callback.
static void | USART_DMAAbortOnError (DMA_HandleTypeDef *hdma)
DMA USART communication abort callback, when initiated by HAL services on Error (To be called at end of DMA Abort procedure following error occurrence).
static void | USART_DMATxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Tx communication abort callback, when initiated by user (To be called at end of DMA Tx Abort procedure following user abort request).
static void | USART_DMARxAbortCallback (DMA_HandleTypeDef *hdma)
DMA USART Rx communication abort callback, when initiated by user (To be called at end of DMA Rx Abort procedure following user abort request).
static HAL_StatusTypeDef | USART_WaitOnFlagUntilTimeout (USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
This function handles USART Communication Timeout.
HAL_StatusTypeDef | HAL_USART_Init (USART_HandleTypeDef *husart)
Initializes the USART mode according to the specified parameters in the USART_InitTypeDef and create the associated handle.
HAL_StatusTypeDef | HAL_USART_DeInit (USART_HandleTypeDef *husart)
DeInitializes the USART peripheral.
__weak void | HAL_USART_MspInit (USART_HandleTypeDef *husart)
USART MSP Init.
__weak void | HAL_USART_MspDeInit (USART_HandleTypeDef *husart)
USART MSP DeInit.
HAL_StatusTypeDef | HAL_USART_Transmit (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
Simplex Send an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Receive an amount of data in blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
HAL_StatusTypeDef | HAL_USART_Transmit_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_IT (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Simplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_IT (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
HAL_StatusTypeDef | HAL_USART_Transmit_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
Simplex Send an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_Receive_DMA (USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
Full-Duplex Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_TransmitReceive_DMA (USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
Full-Duplex Transmit Receive an amount of data in non-blocking mode.
HAL_StatusTypeDef | HAL_USART_DMAPause (USART_HandleTypeDef *husart)
Pauses the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAResume (USART_HandleTypeDef *husart)
Resumes the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_DMAStop (USART_HandleTypeDef *husart)
Stops the DMA Transfer.
HAL_StatusTypeDef | HAL_USART_Abort (USART_HandleTypeDef *husart)
Abort ongoing transfer (blocking mode).
HAL_StatusTypeDef | HAL_USART_Abort_IT (USART_HandleTypeDef *husart)
Abort ongoing transfer (Interrupt mode).
void | HAL_USART_IRQHandler (USART_HandleTypeDef *husart)
This function handles USART interrupt request.
__weak void | HAL_USART_TxCpltCallback (USART_HandleTypeDef *husart)
Tx Transfer completed callbacks.
__weak void | HAL_USART_TxHalfCpltCallback (USART_HandleTypeDef *husart)
Tx Half Transfer completed callbacks.
__weak void | HAL_USART_RxCpltCallback (USART_HandleTypeDef *husart)
Rx Transfer completed callbacks.
__weak void | HAL_USART_RxHalfCpltCallback (USART_HandleTypeDef *husart)
Rx Half Transfer completed callbacks.
__weak void | HAL_USART_TxRxCpltCallback (USART_HandleTypeDef *husart)
Tx/Rx Transfers completed callback for the non-blocking process.
__weak void | HAL_USART_ErrorCallback (USART_HandleTypeDef *husart)
USART error callbacks.
__weak void | HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
USART Abort Complete callback.
HAL_USART_StateTypeDef | HAL_USART_GetState (USART_HandleTypeDef *husart)
Returns the USART state.
uint32_t | HAL_USART_GetError (USART_HandleTypeDef *husart)
Return the USART error code.

Detailed Description

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

Author:
MCD Application Team
Version:
V1.5.0
Date:
15-February-217
  ==============================================================================
                        ##### How to use this driver #####
  ==============================================================================
  [..]
    The USART HAL driver can be used as follows:

    (#) Declare a USART_HandleTypeDef handle structure.
    (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
        (##) Enable the USARTx interface clock.
        (##) USART pins configuration:
             (+++) Enable the clock for the USART GPIOs.
             (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
        (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
             HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
             (+++) Configure the USARTx interrupt priority.
             (+++) Enable the NVIC USART IRQ handle.
        (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
             HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
             (+++) Declare a DMA handle structure for the Tx/Rx channel.
             (+++) Enable the DMAx interface clock.
             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
             (+++) Configure the DMA Tx/Rx channel.
             (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
            (+++) Configure the priority and enable the NVIC for the transfer complete
                  interrupt on the DMA Tx/Rx channel.
            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
                  (used for last byte sending completion detection in DMA non circular mode)

    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
        flow control and Mode(Receiver/Transmitter) in the husart Init structure.

    (#) Initialize the USART registers by calling the HAL_USART_Init() API:
        (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
             by calling the customized HAL_USART_MspInit(&husart) API.

        -@@- The specific USART interrupts (Transmission complete interrupt,
             RXNE interrupt and Error Interrupts) will be managed using the macros
             __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.

    (#) Three operation modes are available within this driver :

     *** Polling mode IO operation ***
     =================================
     [..]
       (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
       (+) Receive an amount of data in blocking mode using HAL_USART_Receive()

     *** Interrupt mode IO operation ***
     ===================================
     [..]
       (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
       (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_RxCpltCallback
       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_USART_ErrorCallback

     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_TxCpltCallback
       (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
            add his own code by customization of function pointer HAL_USART_RxCpltCallback
       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
            add his own code by customization of function pointer HAL_USART_ErrorCallback
       (+) Pause the DMA Transfer using HAL_USART_DMAPause()
       (+) Resume the DMA Transfer using HAL_USART_DMAResume()
       (+) Stop the DMA Transfer using HAL_USART_DMAStop()

     *** USART HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in USART HAL driver.

       (+) __HAL_USART_ENABLE: Enable the USART peripheral
       (+) __HAL_USART_DISABLE: Disable the USART peripheral
       (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
       (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
       (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
       (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt

     [..]
       (@) You can refer to the USART HAL driver header file for more useful macros
[..] (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), the possible USART frame formats are as listed in the following table: +-------------------------------------------------------------+ | M bit | PCE bit | USART frame | |---------------------|---------------------------------------| | 0 | 0 | | SB | 8 bit data | STB | | |---------|-----------|---------------------------------------| | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|-----------|---------------------------------------| | 1 | 0 | | SB | 9 bit data | STB | | |---------|-----------|---------------------------------------| | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+
Attention:

© COPYRIGHT(c) 2017 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_usart.c.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_wwdg.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F1xx_HAL_Driver
  • Src
Functions
stm32f1xx_hal_wwdg.c File Reference

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions. More...

#include "stm32f1xx_hal.h"

Go to the source code of this file.

Functions

HAL_StatusTypeDef | HAL_WWDG_Init (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG according to the specified.
__weak void | HAL_WWDG_MspInit (WWDG_HandleTypeDef *hwwdg)
Initialize the WWDG MSP.
HAL_StatusTypeDef | HAL_WWDG_Refresh (WWDG_HandleTypeDef *hwwdg)
Refresh the WWDG.
void | HAL_WWDG_IRQHandler (WWDG_HandleTypeDef *hwwdg)
Handle WWDG interrupt request.
__weak void | HAL_WWDG_EarlyWakeupCallback (WWDG_HandleTypeDef *hwwdg)
WWDG Early Wakeup callback.

Detailed Description

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions.

Author:
MCD Application Team
Version:
V1.5.0
Date:
06-May-2016
  ==============================================================================
                      ##### WWDG specific features #####
  ==============================================================================
  [..]
    Once enabled the WWDG generates a system reset on expiry of a programmed
    time period, unless the program refreshes the counter (downcounter)
    before reaching 0x3F value (i.e. a reset is generated when the counter
    value rolls over from 0x40 to 0x3F).

    (+) An MCU reset is also generated if the counter value is refreshed
        before the counter has reached the refresh window value. This
        implies that the counter must be refreshed in a limited window.
    (+) Once enabled the WWDG cannot be disabled except by a system reset.
    (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
        reset occurs.
    (+) The WWDG counter input clock is derived from the APB clock divided
        by a programmable prescaler.
    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
    (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
    (+) WWDG Counter refresh is allowed between the following limits :
        (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
        (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock

    (+) Min-max timeout value at 36 MHz(PCLK1): 910 us / 58.25 ms

    (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
        operations or data logging must be performed before the actual reset is
        generated. When the downcounter reaches the value 0x40, an EWI interrupt
        is generated and the corresponding interrupt service routine (ISR) can
        be used to trigger specific actions (such as communications or data
        logging), before resetting the device.
        In some applications, the EWI interrupt can be used to manage a software
        system check and/or system recovery/graceful degradation, without
        generating a WWDG reset. In this case, the corresponding interrupt
        service routine (ISR) should reload the WWDG counter to avoid the WWDG
        reset, then trigger the required actions.
        Note:When the EWI interrupt cannot be served, e.g. due to a system lock
        in a higher priority task, the WWDG reset will eventually be generated.

    (+) Debug mode : When the microcontroller enters debug mode (core halted),
        the WWDG counter either continues to work normally or stops, depending
        on DBG_WWDG_STOP configuration bit in DBG module, accessible through
        __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros

                     ##### How to use this driver #####
  ==============================================================================
  [..]
    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().

    (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
        Interrupt mode using using HAL_WWDG_Init() function.
        This enables WWDG peripheral and the downcounter starts downcounting
        from given counter value.
        Init function can be called again to modify all watchdog parameters,
        however if EWI mode has been set once, it can't be clear until next
        reset.

    (+) The application program must refresh the WWDG counter at regular
        intervals during normal operation to prevent an MCU reset using
        HAL_WWDG_Refresh() function. This operation must occur only when
        the counter is lower than the window value already programmed.

    (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
        the counter reaches 0x40. User can add his own code in weak function
        HAL_WWDG_EarlyWakeupCallback().

     *** WWDG HAL driver macros list ***
     ==================================
     [..]
       Below the list of most used macros in WWDG HAL driver.

      (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_hal_wwdg.c.

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STM32F103xB HAL User Manual: stm32f1xx_ll_pwr.c File Reference

  • File List
  • Globals
  • Drivers
  • STM32F1xx_HAL_Driver
  • Src
Functions
stm32f1xx_ll_pwr.c File Reference

PWR LL module driver. More...

#include "stm32f1xx_ll_pwr.h"
#include "stm32f1xx_ll_bus.h"

Go to the source code of this file.

Functions

ErrorStatus LL_PWR_DeInit (void)
De-initialize the PWR registers to their default reset values.

Detailed Description

PWR LL module driver.

Author:
MCD Application Team
Version:
$VERSION$
Date:
$DATE$
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f1xx_ll_pwr.c.

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STM32F103xB HAL User Manual: ADC_rmtollPages.txt File Reference

  • File List
  • Globals
ADC_rmtollPages.txt File Reference
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Structures

  • Data Structure Index
  • Data Fields
Data Structures
Here are the data structures with brief descriptions:
__DMA_HandleTypeDef | DMA handle Structure definition
__SPI_HandleTypeDef | SPI handle Structure definition
ADC_AnalogWDGConfTypeDef | ADC Configuration analog watchdog definition
ADC_ChannelConfTypeDef | Structure definition of ADC channel for regular group
ADC_HandleTypeDef | ADC handle Structure definition
ADC_InitTypeDef | Structure definition of ADC and regular group initialization
ADC_InjectionConfTypeDef | ADC Configuration injected Channel structure definition
ADC_MultiModeTypeDef | Structure definition of ADC multimode
CAN_FilterConfTypeDef | CAN filter configuration structure definition
CAN_HandleTypeDef | CAN handle Structure definition
CAN_InitTypeDef | CAN init structure definition
CanRxMsgTypeDef | CAN Rx message structure definition
CanTxMsgTypeDef | CAN Tx message structure definition
CRC_HandleTypeDef | CRC handle Structure definition
DMA_InitTypeDef | DMA Configuration Structure definition
FLASH_EraseInitTypeDef | FLASH Erase structure definition
FLASH_OBProgramInitTypeDef | FLASH Options bytes program structure definition
FLASH_ProcessTypeDef | FLASH handle Structure definition
GPIO_InitTypeDef | GPIO Init structure definition
I2C_HandleTypeDef | I2C handle Structure definition
I2C_InitTypeDef | I2C Configuration Structure definition
IRDA_HandleTypeDef | IRDA handle Structure definition
IRDA_InitTypeDef | IRDA Init Structure definition
IWDG_HandleTypeDef | IWDG Handle Structure definition
IWDG_InitTypeDef | IWDG Init structure definition
LL_ADC_CommonInitTypeDef | Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance)
LL_ADC_InitTypeDef | Structure definition of some features of ADC instance
LL_ADC_INJ_InitTypeDef | Structure definition of some features of ADC group injected
LL_ADC_REG_InitTypeDef | Structure definition of some features of ADC group regular
LL_DMA_InitTypeDef |
LL_EXTI_InitTypeDef |
LL_GPIO_InitTypeDef | LL GPIO Init Structure definition
LL_I2C_InitTypeDef |
LL_I2S_InitTypeDef | I2S Init structure definition
LL_RCC_ClocksTypeDef | RCC Clocks Frequency Structure
LL_SPI_InitTypeDef | SPI Init structures definition
LL_TIM_BDTR_InitTypeDef | BDTR (Break and Dead Time) structure definition
LL_TIM_ENCODER_InitTypeDef | TIM Encoder interface configuration structure definition
LL_TIM_HALLSENSOR_InitTypeDef | TIM Hall sensor interface configuration structure definition
LL_TIM_IC_InitTypeDef | TIM Input Capture configuration structure definition
LL_TIM_InitTypeDef | TIM Time Base configuration structure definition
LL_TIM_OC_InitTypeDef | TIM Output Compare configuration structure definition
LL_USART_ClockInitTypeDef | LL USART Clock Init Structure definition
LL_USART_InitTypeDef | LL USART Init Structure definition
LL_UTILS_ClkInitTypeDef | UTILS System, AHB and APB buses clock configuration structure definition
LL_UTILS_PLLInitTypeDef | UTILS PLL structure definition
PCD_HandleTypeDef | PCD Handle Structure definition
PWR_PVDTypeDef | PWR PVD configuration structure definition
RCC_ClkInitTypeDef | RCC System, AHB and APB busses clock configuration structure definition
RCC_OscInitTypeDef | RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
RCC_PeriphCLKInitTypeDef | RCC extended clocks structure definition
RCC_PLLInitTypeDef | RCC PLL configuration structure definition
RTC_AlarmTypeDef | RTC Alarm structure definition
RTC_DateTypeDef | RTC Date structure definition
RTC_HandleTypeDef | Time Handle Structure definition
RTC_InitTypeDef | RTC Configuration Structure definition
RTC_TamperTypeDef | RTC Tamper structure definition
RTC_TimeTypeDef | RTC Time structure definition
SMARTCARD_HandleTypeDef | SMARTCARD handle Structure definition
SMARTCARD_InitTypeDef | SMARTCARD Init Structure definition
SPI_InitTypeDef | SPI Configuration Structure definition
TIM_Base_InitTypeDef | TIM Time base Configuration Structure definition
TIM_BreakDeadTimeConfigTypeDef | TIM Break and Dead time configuration Structure definition
TIM_ClearInputConfigTypeDef | TIM Clear Input Configuration Handle Structure definition
TIM_ClockConfigTypeDef | TIM Clock Configuration Handle Structure definition
TIM_Encoder_InitTypeDef | TIM Encoder Configuration Structure definition
TIM_HallSensor_InitTypeDef | TIM Hall sensor Configuration Structure definition
TIM_HandleTypeDef | TIM Time Base Handle Structure definition
TIM_IC_InitTypeDef | TIM Input Capture Configuration Structure definition
TIM_MasterConfigTypeDef | TIM Master configuration Structure definition
TIM_OC_InitTypeDef | TIM Output Compare Configuration Structure definition
TIM_OnePulse_InitTypeDef | TIM One Pulse Mode Configuration Structure definition
TIM_SlaveConfigTypeDef | TIM Slave configuration Structure definition
UART_HandleTypeDef | UART handle Structure definition
UART_InitTypeDef | UART Init Structure definition
USART_HandleTypeDef | USART handle Structure definition
USART_InitTypeDef | USART Init Structure definition
WWDG_HandleTypeDef | WWDG handle Structure definition
WWDG_InitTypeDef | WWDG Init structure definition
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: BUS_rmtollPages.txt File Reference

  • File List
  • Globals
BUS_rmtollPages.txt File Reference
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Data Structure Index

  • Data Structure Index
  • Data Fields
Data Structure Index
A | C | D | F | G | I | L | P | R | S | T | U | W | _
A
FLASH_OBProgramInitTypeDef LL_I2C_InitTypeDef RCC_PeriphCLKInitTypeDef TIM_IC_InitTypeDef
FLASH_ProcessTypeDef LL_I2S_InitTypeDef RCC_PLLInitTypeDef TIM_MasterConfigTypeDef
ADC_AnalogWDGConfTypeDef
G
LL_RCC_ClocksTypeDef RTC_AlarmTypeDef TIM_OC_InitTypeDef
ADC_ChannelConfTypeDef LL_SPI_InitTypeDef RTC_DateTypeDef TIM_OnePulse_InitTypeDef
ADC_HandleTypeDef GPIO_InitTypeDef LL_TIM_BDTR_InitTypeDef RTC_HandleTypeDef TIM_SlaveConfigTypeDef
ADC_InitTypeDef
I
LL_TIM_ENCODER_InitTypeDef RTC_InitTypeDef
U
ADC_InjectionConfTypeDef LL_TIM_HALLSENSOR_InitTypeDef RTC_TamperTypeDef
ADC_MultiModeTypeDef I2C_HandleTypeDef LL_TIM_IC_InitTypeDef RTC_TimeTypeDef UART_HandleTypeDef
C
I2C_InitTypeDef LL_TIM_InitTypeDef
S
UART_InitTypeDef
IRDA_HandleTypeDef LL_TIM_OC_InitTypeDef USART_HandleTypeDef
CAN_FilterConfTypeDef IRDA_InitTypeDef LL_USART_ClockInitTypeDef SMARTCARD_HandleTypeDef USART_InitTypeDef
CAN_HandleTypeDef IWDG_HandleTypeDef LL_USART_InitTypeDef SMARTCARD_InitTypeDef
W
CAN_InitTypeDef IWDG_InitTypeDef LL_UTILS_ClkInitTypeDef SPI_InitTypeDef
CanRxMsgTypeDef
L
LL_UTILS_PLLInitTypeDef
T
WWDG_HandleTypeDef
CanTxMsgTypeDef
P
WWDG_InitTypeDef
CRC_HandleTypeDef LL_ADC_CommonInitTypeDef TIM_Base_InitTypeDef
_
D
LL_ADC_InitTypeDef PCD_HandleTypeDef TIM_BreakDeadTimeConfigTypeDef
LL_ADC_INJ_InitTypeDef PWR_PVDTypeDef TIM_ClearInputConfigTypeDef __DMA_HandleTypeDef
DMA_InitTypeDef LL_ADC_REG_InitTypeDef
R
TIM_ClockConfigTypeDef __SPI_HandleTypeDef
F
LL_DMA_InitTypeDef TIM_Encoder_InitTypeDef
LL_EXTI_InitTypeDef RCC_ClkInitTypeDef TIM_HallSensor_InitTypeDef
FLASH_EraseInitTypeDef LL_GPIO_InitTypeDef RCC_OscInitTypeDef TIM_HandleTypeDef
A | C | D | F | G | I | L | P | R | S | T | U | W | _
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STM32F103xB HAL User Manual: CORTEX_rmtollPages.txt File Reference

  • File List
  • Globals
CORTEX_rmtollPages.txt File Reference
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CRC_rmtollPages.txt File Reference

  • File List
  • Globals
CRC_rmtollPages.txt File Reference
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: B:/Drivers/STM32F1xx_HAL_Driver/ Directory Reference

  • Drivers
  • STM32F1xx_HAL_Driver
STM32F1xx_HAL_Driver Directory Reference

Directories

directory | Inc
directory | Src
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: B:/Drivers/ Directory Reference

  • Drivers
Drivers Directory Reference

Directories

directory STM32F1xx_HAL_Driver
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: B:/Drivers/STM32F1xx_HAL_Driver/Src/ Directory Reference

  • Drivers
  • STM32F1xx_HAL_Driver
  • Src
Src Directory Reference

Files

file | stm32f1xx_hal.c [code]

HAL module driver. This is the common part of the HAL initialization.

file | stm32f1xx_hal_adc.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Channels configuration on injected group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32f1xx_hal_adc_ex.c".

file | stm32f1xx_hal_adc_ex.c [code]

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Multimode feature (available on devices with 2 ADCs or more) ++ Calibration (ADC automatic self-calibration) + Control functions ++ Channels configuration on injected group Other functions (generic functions) are available in file "stm32f1xx_hal_adc.c".

file | stm32f1xx_hal_can.c [code]

CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions.

file | stm32f1xx_hal_cec.c [code]

CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function.

file | stm32f1xx_hal_cortex.c [code]

CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f1xx_hal_crc.c [code]

CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions.

file | stm32f1xx_hal_dac.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f1xx_hal_dac_ex.c [code]

DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions.

file | stm32f1xx_hal_dma.c [code]

DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions.

file | stm32f1xx_hal_eth.c [code]

ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f1xx_hal_flash.c [code]

FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral State functions.

file | stm32f1xx_hal_flash_ex.c [code]

Extended FLASH HAL module driver.

file | stm32f1xx_hal_gpio.c [code]

GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions.

file | stm32f1xx_hal_gpio_ex.c [code]

GPIO Extension HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) extension peripheral. + Extended features functions.

file | stm32f1xx_hal_hcd.c [code]

HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f1xx_hal_i2c.c [code]

I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State, Mode and Error functions.

file | stm32f1xx_hal_i2s.c [code]

I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions.

file | stm32f1xx_hal_irda.c [code]

IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f1xx_hal_iwdg.c [code]

IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions.

file | stm32f1xx_hal_nand.c [code]

NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device.

file | stm32f1xx_hal_nor.c [code]

NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device.

file | stm32f1xx_hal_pccard.c [code]

PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device.

file | stm32f1xx_hal_pcd.c [code]

PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f1xx_hal_pcd_ex.c [code]

Extended PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions: Update FIFO configuration, PMA configuration for EPs.

file | stm32f1xx_hal_pwr.c [code]

PWR HAL module driver.

file | stm32f1xx_hal_rcc.c [code]

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions.

file | stm32f1xx_hal_rcc_ex.c [code]

Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions.

file | stm32f1xx_hal_rtc.c [code]

RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions.

file | stm32f1xx_hal_rtc_ex.c [code]

Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Tamper functions + Extension Control functions + Extension RTC features functions.

file | stm32f1xx_hal_sd.c [code]

SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + SD card Control functions.

file | stm32f1xx_hal_smartcard.c [code]

SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f1xx_hal_spi.c [code]

SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions.

file | stm32f1xx_hal_spi_ex.c [code]

Extended SPI HAL module driver.

file | stm32f1xx_hal_sram.c [code]

SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device.

file | stm32f1xx_hal_tim.c [code]

TIM HAL module driver This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration.

file | stm32f1xx_hal_tim_ex.c [code]

TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Timer remapping capabilities configuration.

file | stm32f1xx_hal_uart.c [code]

UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions.

file | stm32f1xx_hal_usart.c [code]

USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions.

file | stm32f1xx_hal_wwdg.c [code]

WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions.

file | stm32f1xx_ll_adc.c [code]

ADC LL module driver.

file | stm32f1xx_ll_crc.c [code]

CRC LL module driver.

file | stm32f1xx_ll_dac.c [code]

DAC LL module driver.

file | stm32f1xx_ll_dma.c [code]

DMA LL module driver.

file | stm32f1xx_ll_exti.c [code]

EXTI LL module driver.

file | stm32f1xx_ll_gpio.c [code]

GPIO LL module driver.

file | stm32f1xx_ll_i2c.c [code]

I2C LL module driver.

file | stm32f1xx_ll_i2s.c [code]
file | stm32f1xx_ll_pwr.c [code]

PWR LL module driver.

file | stm32f1xx_ll_rcc.c [code]

RCC LL module driver.

file | stm32f1xx_ll_spi.c [code]

SPI LL module driver.

file | stm32f1xx_ll_tim.c [code]

TIM LL module driver.

file | stm32f1xx_ll_usart.c [code]

USART LL module driver.

file | stm32f1xx_ll_utils.c [code]

UTILS LL module driver.

Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: B:/Drivers/STM32F1xx_HAL_Driver/Inc/ Directory Reference

  • Drivers
  • STM32F1xx_HAL_Driver
  • Inc
Inc Directory Reference

Files

file | stm32f1xx_hal.h [code]

This file contains all the functions prototypes for the HAL module driver.

file | stm32f1xx_hal_adc.h [code]

Header file containing functions prototypes of ADC HAL library.

file | stm32f1xx_hal_adc_ex.h [code]

Header file of ADC HAL extension module.

file | stm32f1xx_hal_can.h [code]

Header file of CAN HAL module.

file | stm32f1xx_hal_can_ex.h [code]

Header file of CAN HAL Extension module.

file | stm32f1xx_hal_cec.h [code]

Header file of CEC HAL module.

file | stm32f1xx_hal_cortex.h [code]

Header file of CORTEX HAL module.

file | stm32f1xx_hal_crc.h [code]

Header file of CRC HAL module.

file | stm32f1xx_hal_dac.h [code]

Header file of DAC HAL module.

file | stm32f1xx_hal_dac_ex.h [code]

Header file of DAC HAL Extension module.

file | stm32f1xx_hal_dma.h [code]

Header file of DMA HAL module.

file | stm32f1xx_hal_dma_ex.h [code]

Header file of DMA HAL extension module.

file | stm32f1xx_hal_eth.h [code]

Header file of ETH HAL module.

file | stm32f1xx_hal_flash.h [code]

Header file of Flash HAL module.

file | stm32f1xx_hal_flash_ex.h [code]

Header file of Flash HAL Extended module.

file | stm32f1xx_hal_gpio.h [code]

Header file of GPIO HAL module.

file | stm32f1xx_hal_gpio_ex.h [code]

Header file of GPIO HAL Extension module.

file | stm32f1xx_hal_hcd.h [code]

Header file of HCD HAL module.

file | stm32f1xx_hal_i2c.h [code]

Header file of I2C HAL module.

file | stm32f1xx_hal_i2s.h [code]

Header file of I2S HAL module.

file | stm32f1xx_hal_irda.h [code]

Header file of IRDA HAL module.

file | stm32f1xx_hal_iwdg.h [code]

Header file of IWDG HAL module.

file | stm32f1xx_hal_nand.h [code]

Header file of NAND HAL module.

file | stm32f1xx_hal_nor.h [code]

Header file of NOR HAL module.

file | stm32f1xx_hal_pccard.h [code]

Header file of PCCARD HAL module.

file | stm32f1xx_hal_pcd.h [code]

Header file of PCD HAL module.

file | stm32f1xx_hal_pcd_ex.h [code]

Header file of Extended PCD HAL module.

file | stm32f1xx_hal_pwr.h [code]

Header file of PWR HAL module.

file | stm32f1xx_hal_rcc.h [code]

Header file of RCC HAL module.

file | stm32f1xx_hal_rcc_ex.h [code]

Header file of RCC HAL Extension module.

file | stm32f1xx_hal_rtc.h [code]

Header file of RTC HAL module.

file | stm32f1xx_hal_rtc_ex.h [code]

Header file of RTC HAL Extension module.

file | stm32f1xx_hal_sd.h [code]

Header file of SD HAL module.

file | stm32f1xx_hal_smartcard.h [code]

Header file of SMARTCARD HAL module.

file | stm32f1xx_hal_spi.h [code]

Header file of SPI HAL module.

file | stm32f1xx_hal_sram.h [code]

Header file of SRAM HAL module.

file | stm32f1xx_hal_tim.h [code]

Header file of TIM HAL module.

file | stm32f1xx_hal_tim_ex.h [code]

Header file of TIM HAL Extension module.

file | stm32f1xx_hal_uart.h [code]

Header file of UART HAL module.

file | stm32f1xx_hal_usart.h [code]

Header file of USART HAL module.

file | stm32f1xx_hal_wwdg.h [code]

Header file of WWDG HAL module.

file | stm32f1xx_ll_adc.h [code]

Header file of ADC LL module.

file | stm32f1xx_ll_bus.h [code]

Header file of BUS LL module.

file | stm32f1xx_ll_cortex.h [code]

Header file of CORTEX LL module.

file | stm32f1xx_ll_crc.h [code]

Header file of CRC LL module.

file | stm32f1xx_ll_dac.h [code]

Header file of DAC LL module.

file | stm32f1xx_ll_dma.h [code]

Header file of DMA LL module.

file | stm32f1xx_ll_exti.h [code]

Header file of EXTI LL module.

file | stm32f1xx_ll_gpio.h [code]

Header file of GPIO LL module.

file | stm32f1xx_ll_i2c.h [code]

Header file of I2C LL module.

file | stm32f1xx_ll_i2s.h [code]
file | stm32f1xx_ll_iwdg.h [code]

Header file of IWDG LL module.

file | stm32f1xx_ll_pwr.h [code]

Header file of PWR LL module.

file | stm32f1xx_ll_rcc.h [code]

Header file of RCC LL module.

file | stm32f1xx_ll_spi.h [code]

Header file of SPI LL module.

file | stm32f1xx_ll_system.h [code]

Header file of SYSTEM LL module.

file | stm32f1xx_ll_tim.h [code]

Header file of TIM LL module.

file | stm32f1xx_ll_usart.h [code]

Header file of USART LL module.

file | stm32f1xx_ll_utils.h [code]

Header file of UTILS LL module.

file | stm32f1xx_ll_wwdg.h [code]

Header file of WWDG LL module.

Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Directories

Directories
This directory hierarchy is sorted roughly, but not completely, alphabetically:
  • Drivers
    • STM32F1xx_HAL_Driver
      • Inc
      • Src
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: DMA_rmtollPages.txt File Reference

  • File List
  • Globals
DMA_rmtollPages.txt File Reference
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: EXTI_rmtollPages.txt File Reference

  • File List
  • Globals
EXTI_rmtollPages.txt File Reference
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: File List

  • File List
  • Globals
File List
Here is a list of all files with brief descriptions:
stm32f1xx_hal.c [code] | HAL module driver. This is the common part of the HAL initialization
stm32f1xx_hal.h [code] | This file contains all the functions prototypes for the HAL module driver
stm32f1xx_hal_adc.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Initialization and de-initialization functions ++ Initialization and Configuration of ADC + Operation functions ++ Start, stop, get result of conversions of regular group, using 3 possible modes: polling, interruption or DMA. + Control functions ++ Channels configuration on regular group ++ Channels configuration on injected group ++ Analog Watchdog configuration + State functions ++ ADC state machine management ++ Interrupts and flags management Other functions (extended functions) are available in file "stm32f1xx_hal_adc_ex.c"
stm32f1xx_hal_adc.h [code] | Header file containing functions prototypes of ADC HAL library
stm32f1xx_hal_adc_ex.c [code] | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: + Operation functions ++ Start, stop, get result of conversions of injected group, using 2 possible modes: polling, interruption. ++ Multimode feature (available on devices with 2 ADCs or more) ++ Calibration (ADC automatic self-calibration) + Control functions ++ Channels configuration on injected group Other functions (generic functions) are available in file "stm32f1xx_hal_adc.c"
stm32f1xx_hal_adc_ex.h [code] | Header file of ADC HAL extension module
stm32f1xx_hal_can.c [code] | CAN HAL module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Error functions
stm32f1xx_hal_can.h [code] | Header file of CAN HAL module
stm32f1xx_hal_can_ex.h [code] | Header file of CAN HAL Extension module
stm32f1xx_hal_cec.c [code] | CEC HAL module driver. This file provides firmware functions to manage the following functionalities of the High Definition Multimedia Interface Consumer Electronics Control Peripheral (CEC). + Initialization and de-initialization function + IO operation function + Peripheral Control function
stm32f1xx_hal_cec.h [code] | Header file of CEC HAL module
stm32f1xx_hal_conf.h [code] | HAL configuration template file. This file should be copied to the application folder and renamed to stm32f1xx_hal_conf.h
stm32f1xx_hal_cortex.c [code] | CORTEX HAL module driver. This file provides firmware functions to manage the following functionalities of the CORTEX: + Initialization and de-initialization functions + Peripheral Control functions
stm32f1xx_hal_cortex.h [code] | Header file of CORTEX HAL module
stm32f1xx_hal_crc.c [code] | CRC HAL module driver. This file provides firmware functions to manage the following functionalities of the Cyclic Redundancy Check (CRC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions + Peripheral State functions
stm32f1xx_hal_crc.h [code] | Header file of CRC HAL module
stm32f1xx_hal_dac.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of the Digital to Analog Converter (DAC) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f1xx_hal_dac.h [code] | Header file of DAC HAL module
stm32f1xx_hal_dac_ex.c [code] | DAC HAL module driver. This file provides firmware functions to manage the following functionalities of DAC extension peripheral: + Extended features functions
stm32f1xx_hal_dac_ex.h [code] | Header file of DAC HAL Extension module
stm32f1xx_hal_dma.c [code] | DMA HAL module driver. This file provides firmware functions to manage the following functionalities of the Direct Memory Access (DMA) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and errors functions
stm32f1xx_hal_dma.h [code] | Header file of DMA HAL module
stm32f1xx_hal_dma_ex.h [code] | Header file of DMA HAL extension module
stm32f1xx_hal_eth.c [code] | ETH HAL module driver. This file provides firmware functions to manage the following functionalities of the Ethernet (ETH) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f1xx_hal_eth.h [code] | Header file of ETH HAL module
stm32f1xx_hal_flash.c [code] | FLASH HAL module driver. This file provides firmware functions to manage the following functionalities of the internal FLASH memory: + Program operations functions + Memory Control functions + Peripheral State functions
stm32f1xx_hal_flash.h [code] | Header file of Flash HAL module
stm32f1xx_hal_flash_ex.c [code] | Extended FLASH HAL module driver
stm32f1xx_hal_flash_ex.h [code] | Header file of Flash HAL Extended module
stm32f1xx_hal_gpio.c [code] | GPIO HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: + Initialization and de-initialization functions + IO operation functions
stm32f1xx_hal_gpio.h [code] | Header file of GPIO HAL module
stm32f1xx_hal_gpio_ex.c [code] | GPIO Extension HAL module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) extension peripheral. + Extended features functions
stm32f1xx_hal_gpio_ex.h [code] | Header file of GPIO HAL Extension module
stm32f1xx_hal_hcd.c [code] | HCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f1xx_hal_hcd.h [code] | Header file of HCD HAL module
stm32f1xx_hal_i2c.c [code] | I2C HAL module driver. This file provides firmware functions to manage the following functionalities of the Inter Integrated Circuit (I2C) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State, Mode and Error functions
stm32f1xx_hal_i2c.h [code] | Header file of I2C HAL module
stm32f1xx_hal_i2s.c [code] | I2S HAL module driver. This file provides firmware functions to manage the following functionalities of the Integrated Interchip Sound (I2S) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State and Errors functions
stm32f1xx_hal_i2s.h [code] | Header file of I2S HAL module
stm32f1xx_hal_irda.c [code] | IRDA HAL module driver. This file provides firmware functions to manage the following functionalities of the IrDA SIR ENDEC block (IrDA): + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f1xx_hal_irda.h [code] | Header file of IRDA HAL module
stm32f1xx_hal_iwdg.c [code] | IWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Independent Watchdog (IWDG) peripheral: + Initialization and Start functions + IO operation functions
stm32f1xx_hal_iwdg.h [code] | Header file of IWDG HAL module
stm32f1xx_hal_nand.c [code] | NAND HAL module driver. This file provides a generic firmware to drive NAND memories mounted as external device
stm32f1xx_hal_nand.h [code] | Header file of NAND HAL module
stm32f1xx_hal_nor.c [code] | NOR HAL module driver. This file provides a generic firmware to drive NOR memories mounted as external device
stm32f1xx_hal_nor.h [code] | Header file of NOR HAL module
stm32f1xx_hal_pccard.c [code] | PCCARD HAL module driver. This file provides a generic firmware to drive PCCARD memories mounted as external device
stm32f1xx_hal_pccard.h [code] | Header file of PCCARD HAL module
stm32f1xx_hal_pcd.c [code] | PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f1xx_hal_pcd.h [code] | Header file of PCD HAL module
stm32f1xx_hal_pcd_ex.c [code] | Extended PCD HAL module driver. This file provides firmware functions to manage the following functionalities of the USB Peripheral Controller: + Extended features functions: Update FIFO configuration, PMA configuration for EPs
stm32f1xx_hal_pcd_ex.h [code] | Header file of Extended PCD HAL module
stm32f1xx_hal_pwr.c [code] | PWR HAL module driver
stm32f1xx_hal_pwr.h [code] | Header file of PWR HAL module
stm32f1xx_hal_rcc.c [code] | RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: + Initialization and de-initialization functions + Peripheral Control functions
stm32f1xx_hal_rcc.h [code] | Header file of RCC HAL module
stm32f1xx_hal_rcc_ex.c [code] | Extended RCC HAL module driver. This file provides firmware functions to manage the following functionalities RCC extension peripheral: + Extended Peripheral Control functions
stm32f1xx_hal_rcc_ex.h [code] | Header file of RCC HAL Extension module
stm32f1xx_hal_rtc.c [code] | RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) peripheral: + Initialization and de-initialization functions + RTC Time and Date functions + RTC Alarm functions + Peripheral Control functions + Peripheral State functions
stm32f1xx_hal_rtc.h [code] | Header file of RTC HAL module
stm32f1xx_hal_rtc_ex.c [code] | Extended RTC HAL module driver. This file provides firmware functions to manage the following functionalities of the Real Time Clock (RTC) Extension peripheral: + RTC Tamper functions + Extension Control functions + Extension RTC features functions
stm32f1xx_hal_rtc_ex.h [code] | Header file of RTC HAL Extension module
stm32f1xx_hal_sd.c [code] | SD card HAL module driver. This file provides firmware functions to manage the following functionalities of the Secure Digital (SD) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + SD card Control functions
stm32f1xx_hal_sd.h [code] | Header file of SD HAL module
stm32f1xx_hal_smartcard.c [code] | SMARTCARD HAL module driver. This file provides firmware functions to manage the following functionalities of the SMARTCARD peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f1xx_hal_smartcard.h [code] | Header file of SMARTCARD HAL module
stm32f1xx_hal_spi.c [code] | SPI HAL module driver. This file provides firmware functions to manage the following functionalities of the Serial Peripheral Interface (SPI) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State functions
stm32f1xx_hal_spi.h [code] | Header file of SPI HAL module
stm32f1xx_hal_spi_ex.c [code] | Extended SPI HAL module driver
stm32f1xx_hal_sram.c [code] | SRAM HAL module driver. This file provides a generic firmware to drive SRAM memories mounted as external device
stm32f1xx_hal_sram.h [code] | Header file of SRAM HAL module
stm32f1xx_hal_tim.c [code] | TIM HAL module driver This file provides firmware functions to manage the following functionalities of the Timer (TIM) peripheral: + Time Base Initialization + Time Base Start + Time Base Start Interruption + Time Base Start DMA + Time Output Compare/PWM Initialization + Time Output Compare/PWM Channel Configuration + Time Output Compare/PWM Start + Time Output Compare/PWM Start Interruption + Time Output Compare/PWM Start DMA + Time Input Capture Initialization + Time Input Capture Channel Configuration + Time Input Capture Start + Time Input Capture Start Interruption + Time Input Capture Start DMA + Time One Pulse Initialization + Time One Pulse Channel Configuration + Time One Pulse Start + Time Encoder Interface Initialization + Time Encoder Interface Start + Time Encoder Interface Start Interruption + Time Encoder Interface Start DMA + Commutation Event configuration with Interruption and DMA + Time OCRef clear configuration + Time External Clock configuration
stm32f1xx_hal_tim.h [code] | Header file of TIM HAL module
stm32f1xx_hal_tim_ex.c [code] | TIM HAL module driver. This file provides firmware functions to manage the following functionalities of the Timer Extended peripheral: + Time Hall Sensor Interface Initialization + Time Hall Sensor Interface Start + Time Complementary signal bread and dead time configuration + Time Master and Slave synchronization configuration + Timer remapping capabilities configuration
stm32f1xx_hal_tim_ex.h [code] | Header file of TIM HAL Extension module
stm32f1xx_hal_uart.c [code] | UART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions + Peripheral State and Errors functions
stm32f1xx_hal_uart.h [code] | Header file of UART HAL module
stm32f1xx_hal_usart.c [code] | USART HAL module driver. This file provides firmware functions to manage the following functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral Control functions
stm32f1xx_hal_usart.h [code] | Header file of USART HAL module
stm32f1xx_hal_wwdg.c [code] | WWDG HAL module driver. This file provides firmware functions to manage the following functionalities of the Window Watchdog (WWDG) peripheral: + Initialization and de-initialization functions + IO operation functions + Peripheral State functions
stm32f1xx_hal_wwdg.h [code] | Header file of WWDG HAL module
stm32f1xx_ll_adc.c [code] | ADC LL module driver
stm32f1xx_ll_adc.h [code] | Header file of ADC LL module
stm32f1xx_ll_bus.h [code] | Header file of BUS LL module
stm32f1xx_ll_cortex.h [code] | Header file of CORTEX LL module
stm32f1xx_ll_crc.c [code] | CRC LL module driver
stm32f1xx_ll_crc.h [code] | Header file of CRC LL module
stm32f1xx_ll_dac.c [code] | DAC LL module driver
stm32f1xx_ll_dac.h [code] | Header file of DAC LL module
stm32f1xx_ll_dma.c [code] | DMA LL module driver
stm32f1xx_ll_dma.h [code] | Header file of DMA LL module
stm32f1xx_ll_exti.c [code] | EXTI LL module driver
stm32f1xx_ll_exti.h [code] | Header file of EXTI LL module
stm32f1xx_ll_gpio.c [code] | GPIO LL module driver
stm32f1xx_ll_gpio.h [code] | Header file of GPIO LL module
stm32f1xx_ll_i2c.c [code] | I2C LL module driver
stm32f1xx_ll_i2c.h [code] | Header file of I2C LL module
stm32f1xx_ll_i2s.c [code] |
stm32f1xx_ll_i2s.h [code] |
stm32f1xx_ll_iwdg.h [code] | Header file of IWDG LL module
stm32f1xx_ll_pwr.c [code] | PWR LL module driver
stm32f1xx_ll_pwr.h [code] | Header file of PWR LL module
stm32f1xx_ll_rcc.c [code] | RCC LL module driver
stm32f1xx_ll_rcc.h [code] | Header file of RCC LL module
stm32f1xx_ll_spi.c [code] | SPI LL module driver
stm32f1xx_ll_spi.h [code] | Header file of SPI LL module
stm32f1xx_ll_system.h [code] | Header file of SYSTEM LL module
stm32f1xx_ll_tim.c [code] | TIM LL module driver
stm32f1xx_ll_tim.h [code] | Header file of TIM LL module
stm32f1xx_ll_usart.c [code] | USART LL module driver
stm32f1xx_ll_usart.h [code] | Header file of USART LL module
stm32f1xx_ll_utils.c [code] | UTILS LL module driver
stm32f1xx_ll_utils.h [code] | Header file of UTILS LL module
stm32f1xx_ll_wwdg.h [code] | Header file of WWDG LL module
Generated on Thu Mar 23 2017 15:22:31 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO_rmtollPages.txt File Reference

  • File List
  • Globals
GPIO_rmtollPages.txt File Reference
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC

Modules
ADC
STM32F1xx_HAL_Driver

ADC HAL module driver. More...

Modules

ADC Private Constants
ADC Private Functions
ADC Exported Functions
ADC Exported Types
ADC Exported Constants
ADC Exported Macros
ADC Private Macros

Detailed Description

ADC HAL module driver.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC Error Code
ADC data alignment
ADC scan mode
ADC external trigger enable for regular group
ADC channels
ADC sampling times
ADC rank into regular group
ADC analog watchdog mode
ADC conversion group
ADC Event type
ADC interrupts definition
ADC flags definition
Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

Initialization/de-initialization functions

Initialization and Configuration functions.

IO operation functions

Input and Output operation functions.

Peripheral Control functions

Peripheral Control functions.

Peripheral State functions

Peripheral State functions.

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STM32F103xB HAL User Manual: ADC Exported Init structure

Data Structures
ADC Exported Init structure
ADC

Data Structures

struct | LL_ADC_CommonInitTypeDef
Structure definition of some features of ADC common parameters and multimode (all ADC instances belonging to the same ADC common instance). More...
struct | LL_ADC_InitTypeDef
Structure definition of some features of ADC instance. More...
struct | LL_ADC_REG_InitTypeDef
Structure definition of some features of ADC group regular. More...
struct | LL_ADC_INJ_InitTypeDef
Structure definition of some features of ADC group injected. More...
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STM32F103xB HAL User Manual: ADC Exported Constants

Modules
ADC Exported Constants
ADC

Modules

ADC flags

Flags defines which can be used with LL_ADC_ReadReg function.

ADC interruptions for configuration (interruption enable or disable)

IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions.

ADC registers compliant with specific purpose
ADC common - Measurement path to internal channels
ADC instance - Resolution
ADC instance - Data alignment
ADC instance - Scan selection
ADC instance - Groups
ADC instance - Channel number
ADC group regular - Trigger source
ADC group regular - Trigger edge
ADC group regular - Continuous mode
ADC group regular - DMA transfer of ADC conversion data
ADC group regular - Sequencer scan length
ADC group regular - Sequencer discontinuous mode
ADC group regular - Sequencer ranks
ADC group injected - Trigger source
ADC group injected - Trigger edge
ADC group injected - Automatic trigger mode
ADC group injected - Sequencer scan length
ADC group injected - Sequencer discontinuous mode
ADC group injected - Sequencer ranks
Channel - Sampling time
Analog watchdog - Analog watchdog number
Analog watchdog - Monitored channels
Analog watchdog - Thresholds
Multimode - Mode
Multimode - ADC master or slave
Definitions of ADC hardware constraints delays
Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Exported Functions

Modules
ADC Exported Functions
ADC

Modules

ADC DMA management
Configuration of ADC hierarchical scope: common to several ADC instances
Configuration of ADC hierarchical scope: ADC instance
Configuration of ADC hierarchical scope: group regular
Configuration of ADC hierarchical scope: group injected
Configuration of ADC hierarchical scope: channels
Configuration of ADC transversal scope: analog watchdog
Configuration of ADC hierarchical scope: multimode
Operation on ADC hierarchical scope: ADC instance
Operation on ADC hierarchical scope: group regular
Operation on ADC hierarchical scope: group injected
ADC flag management
ADC IT management
Initialization and de-initialization functions
Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADC Exported Macros

Modules
ADC Exported Macros
ADC

Modules

Common write and read registers Macros
ADC helper macro
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STM32F103xB HAL User Manual: ADCEx

Modules
ADCEx
STM32F1xx_HAL_Driver

ADC Extension HAL module driver. More...

Modules

ADCEx Private Constants
ADCEx Exported Functions
ADCEx Exported Types
ADCEx Exported Constants
ADCEx Private Macro

Detailed Description

ADC Extension HAL module driver.

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STM32F103xB HAL User Manual: ADCEx Exported Constants

Modules
ADCEx Exported Constants
ADCEx

Modules

ADCEx rank into injected group
ADCEx external trigger enable for injected group
ADC External trigger selection for regular group
ADCEx External trigger selection for injected group
ADC Extended Dual ADC Mode
Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: ADCEx Exported Functions

Modules
ADCEx Exported Functions
ADCEx

Modules

Extended Extended IO operation functions

Extended Extended Input and Output operation functions.

Extended Peripheral Control functions

Extended Peripheral Control functions.

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STM32F103xB HAL User Manual: ADCEx Exported Types

Data Structures
ADCEx Exported Types
ADCEx

Data Structures

struct | ADC_InjectionConfTypeDef
ADC Configuration injected Channel structure definition. More...
struct | ADC_MultiModeTypeDef
Structure definition of ADC multimode. More...
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STM32F103xB HAL User Manual: BUS Exported Constants

Modules
BUS Exported Constants
BUS

Modules

AHB1 GRP1 PERIPH
APB1 GRP1 PERIPH
APB2 GRP1 PERIPH
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STM32F103xB HAL User Manual: BUS Exported Functions

Modules
BUS Exported Functions
BUS

Modules

AHB1
APB1
APB2
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STM32F103xB HAL User Manual: CAN

Modules
CAN
STM32F1xx_HAL_Driver

CAN driver modules. More...

Modules

CAN Private Constants
CAN Private Functions
CAN Exported Functions
CAN Exported Types
CAN Exported Constants
CAN Exported Macros
CAN Private Macros

Detailed Description

CAN driver modules.

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STM32F103xB HAL User Manual: CAN Exported Constants

Modules
CAN Exported Constants
CAN

Modules

CAN Error Code
CAN initialization Status
CAN Operating Mode
CAN Synchronization Jump Width
CAN Time Quantum in Bit Segment 1
CAN Time Quantum in bit segment 2
CAN Filter Mode
CAN Filter Scale
CAN Filter FIFO
CAN Identifier Type
CAN Remote Transmission Request
CAN Transmit Constants
CAN Receive FIFO Number
CAN Flags
CAN Interrupts
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STM32F103xB HAL User Manual: CAN Exported Functions

Modules
CAN Exported Functions
CAN

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Input and Output operation functions

I/O operation functions.

Peripheral State and Error functions

CAN Peripheral State functions.

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STM32F103xB HAL User Manual: CANEx

Data Structures | Modules
CANEx
STM32F1xx_HAL_Driver

Data Structures

struct CAN_FilterConfTypeDef
CAN filter configuration structure definition. More...

Modules

CAN Extended Private Macros
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STM32F103xB HAL User Manual: CORTEX

Modules
CORTEX
STM32F1xx_HAL_Driver

CORTEX HAL module driver. More...

Modules

CORTEX Exported Functions
Cortex Exported Types
CORTEX Exported Constants
CORTEX Private Macros

Detailed Description

CORTEX HAL module driver.

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STM32F103xB HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

CORTEX Preemption Priority Group
CORTEX _SysTick clock source
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STM32F103xB HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

Cortex control functions.

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STM32F103xB HAL User Manual: CORTEX Exported Constants

Modules
CORTEX Exported Constants
CORTEX

Modules

SYSTICK Clock Source
Handler Fault type
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STM32F103xB HAL User Manual: CORTEX Exported Functions

Modules
CORTEX Exported Functions
CORTEX

Modules

SYSTICK
LOW POWER MODE
HANDLER
MCU INFO
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STM32F103xB HAL User Manual: CRC

Modules
CRC
STM32F1xx_HAL_Driver

CRC HAL module driver. More...

Modules

CRC Exported Functions
CRC Exported Types
CRC Exported Macros

Detailed Description

CRC HAL module driver.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

management functions.

Peripheral State functions

Peripheral State functions.

Generated on Thu Mar 23 2017 15:22:25 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: CRC Exported Functions

Modules
CRC Exported Functions
CRC

Modules

CRC Configuration functions
Data_Management
Initialization and de-initialization functions
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STM32F103xB HAL User Manual: CRC Exported Macros

Modules
CRC Exported Macros
CRC

Modules

Common Write and read registers Macros
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STM32F103xB HAL User Manual: DMA

Modules
DMA
STM32F1xx_HAL_Driver

DMA HAL module driver. More...

Modules

DMA Private Functions
DMA Exported Functions
DMA Exported Types
DMA Exported Constants
DMA Exported Macros
DMA Private Macros

Detailed Description

DMA HAL module driver.

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STM32F103xB HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

DMA Error Code
DMA Data transfer direction
DMA Peripheral incremented mode
DMA Memory incremented mode
DMA Peripheral data size
DMA Memory data size
DMA mode
DMA Priority level
DMA interrupt enable definitions
DMA flag definitions
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STM32F103xB HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Input and Output operation functions

Input and Output operation functions.

Peripheral State and Errors functions

Peripheral State and Errors functions.

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STM32F103xB HAL User Manual: DMA Exported Init structure

Data Structures
DMA Exported Init structure
DMA

Data Structures

struct LL_DMA_InitTypeDef
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STM32F103xB HAL User Manual: DMA Exported Constants

Modules
DMA Exported Constants
DMA

Modules

Clear Flags Defines

Flags defines which can be used with LL_DMA_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_DMA_ReadReg function.

IT Defines

IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions.

CHANNEL
Transfer Direction
Transfer mode
Peripheral increment mode
Memory increment mode
Peripheral data alignment
Memory data alignment
Transfer Priority level
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STM32F103xB HAL User Manual: DMA Exported Functions

Modules
DMA Exported Functions
DMA

Modules

Configuration
FLAG_Management
IT_Management
Initialization and de-initialization functions
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STM32F103xB HAL User Manual: DMA Exported Macros

Modules
DMA Exported Macros
DMA

Modules

Common Write and read registers macros
Convert DMAxChannely
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STM32F103xB HAL User Manual: DMAEx

Modules
DMAEx
STM32F1xx_HAL_Driver

Modules

DMA Extended Exported Macros
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STM32F103xB HAL User Manual: DMA Extended Exported Macros

Modules
DMA Extended Exported Macros
DMAEx

Modules

DMA Low density and Medium density product devices
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STM32F103xB HAL User Manual: EXTI Exported Init structure

Data Structures
EXTI Exported Init structure
EXTI

Data Structures

struct LL_EXTI_InitTypeDef
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STM32F103xB HAL User Manual: EXTI Exported Constants

Modules
EXTI Exported Constants
EXTI

Modules

LINE
Mode
Edge Trigger
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STM32F103xB HAL User Manual: EXTI Exported Functions

Modules
EXTI Exported Functions
EXTI

Modules

IT_Management
Event_Management
Rising_Trigger_Management
Falling_Trigger_Management
Software_Interrupt_Management
Flag_Management
Initialization and de-initialization functions
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STM32F103xB HAL User Manual: EXTI Exported Macros

Modules
EXTI Exported Macros
EXTI

Modules

Common Write and read registers Macros
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STM32F103xB HAL User Manual: FLASH

Modules
FLASH
STM32F1xx_HAL_Driver

FLASH HAL module driver. More...

Modules

FLASH Private Constants
FLASH Private Macros
FLASH Private Variables
FLASH Private Functions
FLASH Exported Functions
FLASH Exported Types
FLASH Exported Constants
FLASH Exported Macros

macros to control FLASH features

Detailed Description

FLASH HAL module driver.

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STM32F103xB HAL User Manual: FLASH Exported Constants

Modules
FLASH Exported Constants
FLASH

Modules

FLASH Error Codes
FLASH Type Program
FLASH Latency
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STM32F103xB HAL User Manual: FLASH Exported Functions

Modules
FLASH Exported Functions
FLASH

Modules

Programming operation functions

Programming operation functions.

Peripheral Control functions

management functions

Peripheral errors functions

Peripheral errors functions.

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STM32F103xB HAL User Manual: FLASH Exported Macros

Modules
FLASH Exported Macros
FLASH

macros to control FLASH features More...

Modules

FLASH Half Cycle

macros to handle FLASH half cycle

FLASH Latency

macros to handle FLASH Latency

FLASH Prefetch

macros to handle FLASH Prefetch buffer

Detailed Description

macros to control FLASH features

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASHEx

Modules
FLASHEx
STM32F1xx_HAL_Driver

FLASH HAL Extension module driver. More...

Modules

FLASHEx Private Constants
FLASHEx Private Macros
FLASHEx Private Functions
FLASHEx Exported Functions
FLASHEx Exported Types
FLASHEx Exported Constants
FLASHEx Exported Macros

Detailed Description

FLASH HAL Extension module driver.

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STM32F103xB HAL User Manual: FLASH Constants

Modules
FLASH Constants
FLASHEx Exported Constants

Modules

Page Size
Type Erase
Banks
Flag definition

Flag definition.

Interrupt definition

FLASH Interrupt definition.

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STM32F103xB HAL User Manual: FLASHEx Exported Constants

Modules
FLASHEx Exported Constants
FLASHEx

Modules

FLASH Constants
Option Byte Constants
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STM32F103xB HAL User Manual: FLASHEx Exported Functions

Modules
FLASHEx Exported Functions
FLASHEx

Modules

FLASHEx Memory Erasing functions

FLASH Memory Erasing functions.

Option Bytes Programming functions

Option Bytes Programming functions.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASHEx Exported Macros

Modules
FLASHEx Exported Macros
FLASHEx

Modules

Interrupt

macros to handle FLASH interrupts

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: FLASHEx Exported Types

Data Structures
FLASHEx Exported Types
FLASHEx

Data Structures

struct | FLASH_EraseInitTypeDef
FLASH Erase structure definition. More...
struct | FLASH_OBProgramInitTypeDef
FLASH Options bytes program structure definition. More...
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STM32F103xB HAL User Manual: Option Byte Constants

Modules
Option Byte Constants
FLASHEx Exported Constants

Modules

Option Bytes Type
Option Byte WRP State
Option Bytes Write Protection
Option Byte Read Protection
Option Byte IWatchdog
Option Byte nRST STOP
Option Byte nRST STDBY
Option Byte Data Address
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STM32F103xB HAL User Manual: GPIO

Modules
GPIO
STM32F1xx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIO Exported Functions
GPIO Exported Types
GPIO Exported Constants
GPIO Exported Macros
GPIO Private Constants
GPIO Private Macros
GPIO Private Functions

Detailed Description

GPIO HAL module driver.

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STM32F103xB HAL User Manual: GPIO Exported Constants

Modules
GPIO Exported Constants
GPIO

Modules

GPIO pins define
GPIO mode define

GPIO Configuration Mode Elements values convention: 0xX0yz00YZ.

GPIO speed define

GPIO Output Maximum frequency.

GPIO pull define

GPIO Pull-Up or Pull-Down Activation.

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STM32F103xB HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

GPIO Read and Write.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: GPIO Exported Init structures

Data Structures
GPIO Exported Init structures
GPIO

Data Structures

struct LL_GPIO_InitTypeDef
LL GPIO Init Structure definition. More...
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STM32F103xB HAL User Manual: GPIO Exported Functions

Modules
GPIO Exported Functions
GPIO

Modules

Port Configuration
Data Access
Alternate Function Remapping

This section propose definition to remap the alternate function to some other port/pins.

Output Event configuration

This section propose definition to Configure EVENTOUT Cortex feature .

EXTI external interrupt

This section Configure source input for the EXTI external interrupt .

Initialization and de-initialization functions
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STM32F103xB HAL User Manual: GPIO Exported Macros

Modules
GPIO Exported Macros
GPIO

Modules

Common Write and read registers Macros
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STM32F103xB HAL User Manual: GPIOEx

Modules
GPIOEx
STM32F1xx_HAL_Driver

GPIO HAL module driver. More...

Modules

GPIOEx Exported Functions
GPIOEx Exported Constants
GPIOEx Private Macros

Detailed Description

GPIO HAL module driver.

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STM32F103xB HAL User Manual: EVENTOUT Cortex Configuration

Modules
EVENTOUT Cortex Configuration
GPIOEx Exported Constants

This section propose definition to use the Cortex EVENTOUT signal. More...

Modules

EVENTOUT Pin
EVENTOUT Port

Detailed Description

This section propose definition to use the Cortex EVENTOUT signal.

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STM32F103xB HAL User Manual: GPIOEx Exported Constants

Modules
GPIOEx Exported Constants
GPIOEx

Modules

EVENTOUT Cortex Configuration

This section propose definition to use the Cortex EVENTOUT signal.

Alternate Function Remapping

This section propose definition to remap the alternate function to some other port/pins.

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STM32F103xB HAL User Manual: GPIOEx Exported Functions

Modules
GPIOEx Exported Functions
GPIOEx

Modules

Extended features functions

Extended features functions.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: HAL

Modules
HAL
STM32F1xx_HAL_Driver

HAL module driver. More...

Modules

HAL Private Constants
HAL Private Variables
HAL Exported Functions
HAL Exported Macros

Detailed Description

HAL module driver.

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STM32F103xB HAL User Manual: HAL Exported Functions

Modules
HAL Exported Functions
HAL

Modules

Initialization and de-initialization Functions

Initialization and de-initialization functions.

HAL Control functions

HAL Control functions.

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STM32F103xB HAL User Manual: HAL Exported Macros

Modules
HAL Exported Macros
HAL

Modules

Freeze Unfreeze Peripherals in Debug mode

Freeze/Unfreeze Peripherals in Debug mode Note: On devices STM32F10xx8 and STM32F10xxB, STM32F101xC/D/E and STM32F103xC/D/E, STM32F101xF/G and STM32F103xF/G STM32F10xx4 and STM32F10xx6 Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in debug mode (not accessible by the user software in normal mode).

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STM32F103xB HAL User Manual: I2C

Modules
I2C
STM32F1xx_HAL_Driver

I2C HAL module driver. More...

Modules

I2C Exported Functions
I2C Exported Types
I2C Exported Constants
I2C Exported Macros
I2C Private Constants
I2C Private Macros
I2C Private Functions
I2C_Private_Define

Detailed Description

I2C HAL module driver.

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STM32F103xB HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

I2C Error Code

I2C Error Code.

I2C duty cycle in fast mode
I2C addressing mode
I2C dual addressing mode
I2C general call addressing mode
I2C nostretch mode
I2C Memory Address Size
I2C XferDirection definition
I2C XferOptions definition
I2C Interrupt configuration definition
I2C Flag definition
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STM32F103xB HAL User Manual: I2C Exported Init structure

Data Structures
I2C Exported Init structure
I2C

Data Structures

struct LL_I2C_InitTypeDef
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STM32F103xB HAL User Manual: I2C Exported Constants

Modules
I2C Exported Constants
I2C

Modules

Get Flags Defines

Flags defines which can be used with LL_I2C_ReadReg function.

IT Defines

IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions.

Own Address 1 Length
Fast Mode Duty Cycle
Master Clock Speed Mode
Peripheral Mode
Acknowledge Generation
Read Write Direction
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STM32F103xB HAL User Manual: I2C Exported Functions

Modules
I2C Exported Functions
I2C

Modules

Configuration
IT_Management
FLAG_management
Data_Management
Initialization and de-initialization functions
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STM32F103xB HAL User Manual: I2C Exported Macros

Modules
I2C Exported Macros
I2C

Modules

Common Write and read registers Macros
Exported_Macros_Helper
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STM32F103xB HAL User Manual: I2S Exported Init structure

Data Structures
I2S Exported Init structure
I2S

Data Structures

struct LL_I2S_InitTypeDef
I2S Init structure definition. More...
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STM32F103xB HAL User Manual: I2S Exported Constants

Modules
I2S Exported Constants
I2S

Modules

Get Flags Defines

Flags defines which can be used with LL_I2S_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Data format
Clock Polarity
I2s Standard
Operation Mode
Prescaler Factor
MCLK Output
Audio Frequency
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2S Exported Functions

Modules
I2S Exported Functions
I2S

Modules

Configuration
FLAG Management
Interrupt Management
DMA Management
DATA Management
Initialization and de-initialization functions
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2S Exported Macros

Modules
I2S Exported Macros
I2S

Modules

Common Write and read registers Macros
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA

Modules
IRDA
STM32F1xx_HAL_Driver

HAL IRDA module driver. More...

Modules

IrDA Exported Functions
IRDA Exported Types
IRDA Exported constants
IRDA Exported Macros
IRDA Private Constants
IRDA Private Macros
IRDA Private Functions

Detailed Description

HAL IRDA module driver.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IRDA Exported constants

Modules
IRDA Exported constants
IRDA

Modules

IRDA Error Code
IRDA Word Length
IRDA Parity
IRDA Transfer Mode
IRDA Low Power
IRDA Flags

Elements values convention: 0xXXXX.

IRDA Interrupt Definitions

Elements values convention: 0xY000XXXX.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG

Modules
IWDG
STM32F1xx_HAL_Driver

IWDG HAL module driver. More...

Modules

IWDG Private Defines
IWDG Exported Types
IWDG Exported Constants
IWDG Exported Macros
IWDG Exported Functions
IWDG Private Constants
IWDG Private Macros

Detailed Description

IWDG HAL module driver.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

IWDG Prescaler
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STM32F103xB HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Initialization and Start functions

Initialization and Start functions.

IO operation functions

IO operation functions.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG Exported Types

Data Structures
IWDG Exported Types
IWDG

Data Structures

struct | IWDG_InitTypeDef
IWDG Init structure definition. More...
struct | IWDG_HandleTypeDef
IWDG Handle Structure definition. More...
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STM32F103xB HAL User Manual: IWDG Exported Constants

Modules
IWDG Exported Constants
IWDG

Modules

Get Flags Defines

Flags defines which can be used with LL_IWDG_ReadReg function.

Prescaler Divider
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: IWDG Exported Functions

Modules
IWDG Exported Functions
IWDG

Modules

Configuration
FLAG_Management
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STM32F103xB HAL User Manual: IWDG Exported Macros

Modules
IWDG Exported Macros
IWDG

Modules

Common Write and read registers Macros
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: Clocks Frequency Structure

Data Structures
Clocks Frequency Structure
RCC Exported Types

Data Structures

struct LL_RCC_ClocksTypeDef
RCC Clocks Frequency Structure. More...
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STM32F103xB HAL User Manual: PCD

Modules
PCD
STM32F1xx_HAL_Driver

PCD HAL module driver. More...

Modules

PCD Private Macros
PCD Private Functions
PCD Exported Functions
PCD Exported Types
PCD Exported Constants
PCD Exported Macros

macros to handle interrupts and specific clock configurations

PCD Private Constants

Detailed Description

PCD HAL module driver.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PCD Exported Constants

Modules
PCD Exported Constants
PCD

Modules

PCD Speed
PCD PHY Module
Turnaround Timeout Value
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STM32F103xB HAL User Manual: PCD Exported Functions

Modules
PCD Exported Functions
PCD

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral Control functions

management functions

Peripheral State functions

Peripheral State functions.

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STM32F103xB HAL User Manual: PCD Private Constants

Modules
PCD Private Constants
PCD

Modules

USB EXTI line interrupt
PCD EP0 MPS
PCD ENDP
PCD Endpoint Kind
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PCDEx

Modules
PCDEx
STM32F1xx_HAL_Driver

PCD Extended HAL module driver. More...

Modules

PCDEx Exported Functions

Detailed Description

PCD Extended HAL module driver.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PCDEx Exported Functions

Modules
PCDEx Exported Functions
PCDEx

Modules

Peripheral Control functions

PCDEx control functions.

Peripheral State functions

Manage device connection state.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR

Modules
PWR
STM32F1xx_HAL_Driver

PWR HAL module driver. More...

Modules

PWR Private Constants
PWR Private Functions

brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)

PWR Exported Functions
PWR Exported Types
PWR Exported Constants
PWR Exported Macros
PWR Private Macros

Detailed Description

PWR HAL module driver.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

PWR PVD detection level
PWR PVD Mode
PWR WakeUp Pins
PWR Regulator state in SLEEP/STOP mode
PWR SLEEP mode entry
PWR STOP mode entry
PWR Flag
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STM32F103xB HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Initialization and de-initialization functions

Initialization and de-initialization functions.

Peripheral Control functions

Low Power modes configuration functions.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR Exported Types

Data Structures
PWR Exported Types
PWR

Data Structures

struct PWR_PVDTypeDef
PWR PVD configuration structure definition. More...
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STM32F103xB HAL User Manual: PWR Exported Constants

Modules
PWR Exported Constants
PWR

Modules

Clear Flags Defines

Flags defines which can be used with LL_PWR_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_PWR_ReadReg function.

Mode Power
Regulator Mode In Deep Sleep Mode
Power Voltage Detector Level
Wakeup Pins
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR Exported Functions

Modules
PWR Exported Functions
PWR

Modules

Configuration
FLAG_Management
De-initialization function
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: PWR Exported Macros

Modules
PWR Exported Macros
PWR

Modules

Common write and read registers Macros
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STM32F103xB HAL User Manual: RCC

Modules
RCC
STM32F1xx_HAL_Driver

RCC HAL module driver. More...

Modules

RCC Private Constants
RCC Private Macros
RCC Private Variables
RCC Exported Functions
RCC Exported Types
RCC Exported Constants
RCC Exported Macros

Detailed Description

RCC HAL module driver.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

PLL Clock Source
Oscillator Type
HSE Config
LSE Config
HSI Config
LSI Config
PLL Config
System Clock Type
System Clock Source
System Clock Source Status
AHB Clock Source
APB1 APB2 Clock Source
RTC Clock Source
MCO Index
MCO Clock Prescaler
Interrupts
Flags

Elements values convention: XXXYYYYYb.

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STM32F103xB HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Peripheral Control functions

RCC clocks control functions.

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STM32F103xB HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

Peripheral Clock Enable Disable

Enable or disable the AHB1 peripheral clock.

AHB Peripheral Clock Enable Disable Status

Get the enable or disable status of the AHB peripheral clock.

APB1 Clock Enable Disable

Enable or disable the Low Speed APB (APB1) peripheral clock.

APB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB1 peripheral clock.

APB2 Clock Enable Disable

Enable or disable the High Speed APB (APB2) peripheral clock.

APB2 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB2 peripheral clock.

APB1 Force Release Reset

Force or release APB1 peripheral reset.

APB2 Force Release Reset

Force or release APB2 peripheral reset.

HSI Configuration
LSI Configuration
HSE Configuration
LSE Configuration
PLL Configuration
Get Clock source
RCC Extended MCOx Clock Config
RCC RTC Clock Configuration
Flags Interrupts Management

macros to manage the specified RCC Flags and interrupts.

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STM32F103xB HAL User Manual: RCC Exported Types

Data Structures
RCC Exported Types
RCC

Data Structures

struct | RCC_PLLInitTypeDef
RCC PLL configuration structure definition. More...
struct | RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition. More...
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STM32F103xB HAL User Manual: RCC Exported Constants

Modules
RCC Exported Constants
RCC

Modules

Oscillator Values adaptation

Defines used to adapt values of different oscillators.

Clear Flags Defines

Flags defines which can be used with LL_RCC_WriteReg function.

Get Flags Defines

Flags defines which can be used with LL_RCC_ReadReg function.

IT Defines

IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions.

System clock switch
System clock switch status
AHB prescaler
APB low-speed prescaler (APB1)
APB high-speed prescaler (APB2)
MCO1 SOURCE selection
Peripheral clock frequency
Peripheral USB clock source selection
Peripheral ADC clock source selection
Peripheral USB get clock source
Peripheral ADC get clock source
RTC clock source selection
PLL Multiplicator factor
PLL SOURCE
PREDIV Division factor
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STM32F103xB HAL User Manual: RCC Exported Functions

Modules
RCC Exported Functions
RCC

Modules

HSE
HSI
LSE
LSI
System
MCO
Peripheral Clock Source
RTC
PLL
FLAG Management
IT Management
De-initialization function
Get system and peripherals clocks frequency functions

Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks and different peripheral clocks available on the device.

Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCC Exported Macros

Modules
RCC Exported Macros
RCC

Modules

Common Write and read registers Macros
Calculate frequencies
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STM32F103xB HAL User Manual: RCC Exported Types

Modules
RCC Exported Types
RCC

Modules

Clocks Frequency Structure
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STM32F103xB HAL User Manual: RCCEx

Modules
RCCEx
STM32F1xx_HAL_Driver

RCC Extension HAL module driver. More...

Modules

RCCEx Private Constants
RCCEx Private Macros
RCCEx Exported Functions
RCCEx Exported Types
RCCEx Exported Constants
RCCEx Exported Macros

Detailed Description

RCC Extension HAL module driver.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCCEx Exported Constants

Modules
RCCEx Exported Constants
RCCEx

Modules

Periph Clock Selection
ADC Prescaler
USB Prescaler
HSE Prediv1 Factor
PLL Multiplication Factor
MCO1 Clock Source
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCCEx Exported Functions

Modules
RCCEx Exported Functions
RCCEx

Modules

Peripheral Control functions

Extended Peripheral Control functions.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCCEx Exported Macros

Modules
RCCEx Exported Macros
RCCEx

Modules

Peripheral Clock Enable Disable

Enable or disable the AHB1 peripheral clock.

AHB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the AHB1 peripheral clock.

APB1 Clock Enable Disable

Enable or disable the Low Speed APB (APB1) peripheral clock.

APB1 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB1 peripheral clock.

APB2 Clock Enable Disable

Enable or disable the High Speed APB (APB2) peripheral clock.

APB2 Peripheral Clock Enable Disable Status

Get the enable or disable status of the APB2 peripheral clock.

APB1 Force Release Reset

Force or release APB1 peripheral reset.

APB2 Force Release Reset

Force or release APB2 peripheral reset.

HSE Configuration
Peripheral Configuration

Macros to configure clock source of different peripherals.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RCCEx Exported Types

Data Structures
RCCEx Exported Types
RCCEx

Data Structures

struct | RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition. More...
struct | RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition. More...
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC

Modules
RTC
STM32F1xx_HAL_Driver

RTC HAL module driver. More...

Modules

RTC Private Constants
RTC Private Macros
RTC Private Functions
RTC Exported Functions
RTC Exported Types
RTC Exported Constants
RTC Exported Macros

Detailed Description

RTC HAL module driver.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC Exported Constants

Modules
RTC Exported Constants
RTC

Modules

Automatic calculation of prediv for 1sec timebase
Input Parameter Format
Month Definitions
WeekDay Definitions
Alarms Definitions
Output source to output on the Tamper pin
Interrupts Definitions
Flags Definitions
Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTC Exported Functions

Modules
RTC Exported Functions
RTC

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

Time and Date functions

RTC Time and Date functions.

Alarm functions

RTC Alarm functions.

Peripheral State functions

Peripheral State functions.

Peripheral Control functions

Peripheral Control functions.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTCEx

Modules
RTCEx
STM32F1xx_HAL_Driver

RTC Extended HAL module driver. More...

Modules

RTCEx Private Macros
RTCEx Exported Functions
RTCEx Exported Types
RTCEx Exported Constants
RTCEx Exported Macros

Detailed Description

RTC Extended HAL module driver.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTCEx Exported Constants

Modules
RTCEx Exported Constants
RTCEx

Modules

Tamper Pins Definitions
Tamper Trigger Definitions
Backup Registers Definitions
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STM32F103xB HAL User Manual: RTCEx Exported Functions

Modules
RTCEx Exported Functions
RTCEx

Modules

RTC Tamper functions

RTC Tamper functions.

RTC Second functions

RTC Second functions.

Extended Peripheral Control functions

Extended Peripheral Control functions.

Generated on Thu Mar 23 2017 15:22:26 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: RTCEx Exported Types

Data Structures
RTCEx Exported Types
RTCEx

Data Structures

struct RTC_TamperTypeDef
RTC Tamper structure definition. More...
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STM32F103xB HAL User Manual: RTCEx Private Macros

Modules
RTCEx Private Macros
RTCEx

Modules

Alias define maintained for legacy
Private macros to check input parameters
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STM32F103xB HAL User Manual: SMARTCARD

Modules
SMARTCARD
STM32F1xx_HAL_Driver

HAL SMARTCARD module driver. More...

Modules

SMARTCARD Exported Functions
SMARTCARD Exported Types
SMARTCARD Exported constants
SMARTCARD Exported Macros
SMARTCARD Private Constants
SMARTCARD Private Macros
SMARTCARD Private Functions

Detailed Description

HAL SMARTCARD module driver.

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STM32F103xB HAL User Manual: SMARTCARD Exported constants

Modules
SMARTCARD Exported constants
SMARTCARD

Modules

SMARTCARD Error Code
SMARTCARD Word Length
SMARTCARD Number of Stop Bits
SMARTCARD Parity
SMARTCARD Mode
SMARTCARD Clock Polarity
SMARTCARD Clock Phase
SMARTCARD Last Bit
SMARTCARD NACK State
SMARTCARD DMA requests
SMARTCARD Prescaler
SMARTCARD Flags

Elements values convention: 0xXXXX.

SMARTCARD Interrupts Definition

Elements values convention: 0xY000XXXX.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

SPI Error Code
SPI Mode
SPI Direction Mode
SPI Data Size
SPI Clock Polarity
SPI Clock Phase
SPI Slave Select Management
SPI BaudRate Prescaler
SPI MSB LSB Transmission
SPI TI Mode
SPI CRC Calculation
SPI Interrupt Definition
SPI Flags Definition
Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

Data transfers functions.

Peripheral State and Errors functions

SPI control functions.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Exported Init structure

Data Structures
SPI Exported Init structure
SPI

Data Structures

struct LL_SPI_InitTypeDef
SPI Init structures definition. More...
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STM32F103xB HAL User Manual: SPI Exported Constants

Modules
SPI Exported Constants
SPI

Modules

Get Flags Defines

Flags defines which can be used with LL_SPI_ReadReg function.

IT Defines

IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions.

Operation Mode
Clock Phase
Clock Polarity
Baud Rate Prescaler
Transmission Bit Order
Transfer Mode
Slave Select Pin Mode
Datawidth
CRC Calculation
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Exported Functions

Modules
SPI Exported Functions
SPI

Modules

Configuration
CRC Management
Slave Select Pin Management
FLAG Management
Interrupt Management
DMA Management
DATA Management
Initialization and de-initialization functions
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SPI Exported Macros

Modules
SPI Exported Macros
SPI

Modules

Common Write and read registers Macros
Generated on Thu Mar 23 2017 15:22:28 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: STM32F1xx_HAL_Driver

Modules
STM32F1xx_HAL_Driver

Modules

HAL

HAL module driver.

ADC

ADC HAL module driver.

ADCEx

ADC Extension HAL module driver.

CAN

CAN driver modules.

CANEx
CORTEX

CORTEX HAL module driver.

CRC

CRC HAL module driver.

DAC

DAC driver modules.

DACEx

DACEx driver module.

DMA

DMA HAL module driver.

DMAEx
FLASH

FLASH HAL module driver.

FLASHEx

FLASH HAL Extension module driver.

GPIO

GPIO HAL module driver.

GPIOEx

GPIO HAL module driver.

I2C

I2C HAL module driver.

IRDA

HAL IRDA module driver.

IWDG

IWDG HAL module driver.

PCD

PCD HAL module driver.

PCDEx

PCD Extended HAL module driver.

PWR

PWR HAL module driver.

RCC

RCC HAL module driver.

RCCEx

RCC Extension HAL module driver.

RTC

RTC HAL module driver.

RTCEx

RTC Extended HAL module driver.

SMARTCARD

HAL SMARTCARD module driver.

SPI

SPI HAL module driver.

TIM

TIM HAL module driver.

TIMEx

TIM Extended HAL module driver.

UART

HAL UART module driver.

USART

HAL USART Synchronous module driver.

WWDG

WWDG HAL module driver.

Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: STM32F1xx_LL_Driver

Modules
STM32F1xx_LL_Driver

Modules

ADC
BUS
CORTEX
CRC
DMA
EXTI
GPIO
I2C
I2S
IWDG
PWR
RCC
SPI
SYSTEM
TIM
USART
UTILS
WWDG
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: SYSTEM Exported Constants

Modules
SYSTEM Exported Constants
SYSTEM

Modules

DBGMCU TRACE Pin Assignment
DBGMCU APB1 GRP1 STOP IP
DBGMCU APB2 GRP1 STOP IP
FLASH LATENCY
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STM32F103xB HAL User Manual: SYSTEM Exported Functions

Modules
SYSTEM Exported Functions
SYSTEM

Modules

DBGMCU
FLASH
Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM

Modules
TIM
STM32F1xx_HAL_Driver

TIM HAL module driver. More...

Modules

TIM Private Functions
TIM Exported Functions
TIM Exported Types
TIM Exported Constants
TIM Private Constants
TIM Private Macros
TIM Exported Macros

Detailed Description

TIM HAL module driver.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

TIM Input Channel Polarity
TIM ETR Polarity
TIM ETR Prescaler
TIM Counter Mode
TIM ClockDivision
TIM Auto-Reload Preload
TIM Output Compare and PWM modes
TIM Output Compare State
TIM Output Fast State
TIM Complementary Output Compare State
TIM Output Compare Polarity
TIM Complementary Output Compare Polarity
TIM Output Compare Idle State
TIM Complementary Output Compare Idle State
TIM Channel
TIM Input Capture Polarity
TIM Input Capture Selection
TIM Input Capture Prescaler
TIM One Pulse Mode
TIM Encoder Mode
TIM Interrupt Definition
TIM Commutation Source
TIM DMA Sources
TIM Event Source
TIM Flag Definition
TIM Clock Source
TIM Clock Polarity
TIM Clock Prescaler
TIM ClearInput Source
TIM Clear Input Polarity
TIM Clear Input Prescaler
TIM OSSR Off State Selection for Run mode state
TIM OSSI Off State Selection for Idle mode state
TIM Lock level
TIM Break Input Enable Disable
TIM Break Input Polarity
TIM Automatic Output Enable
TIM Master Mode Selection
TIM Slave Mode
TIM Master Slave Mode
TIM Trigger Selection
TIM Trigger Polarity
TIM Trigger Prescaler
TIM TI1 Input Selection
TIM DMA Base Address
TIM DMA Burst Length
TIM DMA Handle Index
TIM Capture/Compare Channel State
Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

Time Base functions

Time Base functions.

Time Output Compare functions

Time Output Compare functions.

Time PWM functions

Time PWM functions.

Time Input Capture functions

Time Input Capture functions.

Time One Pulse functions

Time One Pulse functions.

Time Encoder functions

Time Encoder functions.

TIM IRQ handler management

IRQ handler management.

Peripheral Control functions

Peripheral Control functions.

TIM Callbacks functions

TIM Callbacks functions.

Peripheral State functions

Peripheral State functions.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Exported Init structure

Data Structures
TIM Exported Init structure
TIM

Data Structures

struct | LL_TIM_InitTypeDef
TIM Time Base configuration structure definition. More...
struct | LL_TIM_OC_InitTypeDef
TIM Output Compare configuration structure definition. More...
struct | LL_TIM_IC_InitTypeDef
TIM Input Capture configuration structure definition. More...
struct | LL_TIM_ENCODER_InitTypeDef
TIM Encoder interface configuration structure definition. More...
struct | LL_TIM_HALLSENSOR_InitTypeDef
TIM Hall sensor interface configuration structure definition. More...
struct | LL_TIM_BDTR_InitTypeDef
BDTR (Break and Dead Time) structure definition. More...
Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Exported Constants

Modules
TIM Exported Constants
TIM

Modules

Get Flags Defines

Flags defines which can be used with LL_TIM_ReadReg function.

Break Enable
Automatic output enable
IT Defines

IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.

Update Source
One Pulse Mode
Counter Mode
Clock Division
Counter Direction
Capture Compare Update Source
Capture Compare DMA Request
Lock Level
Channel
Output Configuration State
Output Configuration Mode
Output Configuration Polarity
Output Configuration Idle State
Active Input Selection
Input Configuration Prescaler
Input Configuration Filter
Input Configuration Polarity
Clock Source
Encoder Mode
Trigger Output
Slave Mode
Trigger Selection
External Trigger Polarity
External Trigger Prescaler
External Trigger Filter
break polarity
OSSI
OSSR
DMA Burst Base Address
DMA Burst Length
Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Exported Functions

Modules
TIM Exported Functions
TIM

Modules

Time Base configuration
Capture Compare configuration
Output channel configuration
Input channel configuration
Counter clock selection
Timer synchronisation configuration
Break function configuration
DMA burst mode configuration
Initialisation and deinitialisation functions
Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIM Exported Macros

Modules
TIM Exported Macros
TIM

Modules

Common Write and read registers Macros
Exported_Macros
Generated on Thu Mar 23 2017 15:22:29 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIMEx Exported Constants

Modules
TIMEx Exported Constants
TIMEx

Modules

TIMEx Clock Filter
Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIMEx Exported Functions

Modules
TIMEx Exported Functions
TIMEx

Modules

Timer Hall Sensor functions

Timer Hall Sensor functions.

Timer Complementary Output Compare functions

Timer Complementary Output Compare functions.

Timer Complementary PWM functions

Timer Complementary PWM functions.

Timer Complementary One Pulse functions

Timer Complementary One Pulse functions.

Peripheral Control functions

Peripheral Control functions.

Extension Callbacks functions

Extension Callbacks functions.

Extension Peripheral State functions

Extension Peripheral State functions.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: TIMEx Exported Types

Data Structures
TIMEx Exported Types
TIMEx

Data Structures

struct | TIM_HallSensor_InitTypeDef
TIM Hall sensor Configuration Structure definition. More...
struct | TIM_BreakDeadTimeConfigTypeDef
TIM Break and Dead time configuration Structure definition. More...
struct | TIM_MasterConfigTypeDef
TIM Master configuration Structure definition. More...
Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART

Modules
UART
STM32F1xx_HAL_Driver

HAL UART module driver. More...

Modules

UART Exported Functions
UART Exported Types
UART Exported constants
UART Exported Macros
UART Private Constants
UART Private Macros
UART Private Functions

Detailed Description

HAL UART module driver.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UART Exported constants

Modules
UART Exported constants
UART

Modules

UART Error Code
UART Word Length
UART Number of Stop Bits
UART Parity
UART Hardware Flow Control
UART Transfer Mode
UART State
UART Over Sampling
UART LIN Break Detection Length
UART Wakeup Functions
UART FLags

Elements values convention: 0xXXXX.

UART Interrupt Definitions

Elements values convention: 0xY000XXXX.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART

Modules
USART
STM32F1xx_HAL_Driver

HAL USART Synchronous module driver. More...

Modules

USART Exported Functions
USART Private Functions

USART Private functions.

USART Exported Types
USART Exported Constants
USART Exported Macros
USART Private Constants
USART Private Macros

Detailed Description

HAL USART Synchronous module driver.

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STM32F103xB HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

USART Error Code

USART Error Code.

USART Word Length
USART Number of Stop Bits
USART Parity
USART Mode
USART Clock
USART Clock Polarity
USART Clock Phase
USART Last Bit
USART NACK State
USART Flags

Elements values convention: 0xXXXX.

USART Interrupts Definition

Elements values convention: 0xY000XXXX.

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STM32F103xB HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

USART Initialization and de-initialization functions

Initialization and Configuration functions.

IO operation functions

USART Transmit and Receive functions.

Peripheral State and Errors functions

USART State and Errors functions.

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STM32F103xB HAL User Manual: USART Exported Init structures

Data Structures
USART Exported Init structures
USART

Data Structures

struct | LL_USART_InitTypeDef
LL USART Init Structure definition. More...
struct | LL_USART_ClockInitTypeDef
LL USART Clock Init Structure definition. More...
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STM32F103xB HAL User Manual: USART Exported Constants

Modules
USART Exported Constants
USART

Modules

Get Flags Defines

Flags defines which can be used with LL_USART_ReadReg function.

IT Defines

IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions.

Communication Direction
Parity Control
Wakeup
Datawidth
Clock Signal
Last Clock Pulse
Clock Phase
Clock Polarity
Stop Bits
Hardware Control
IrDA Power
LIN Break Detection Length
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STM32F103xB HAL User Manual: USART Exported Functions

Modules
USART Exported Functions
USART

Modules

Configuration functions
Configuration functions related to Irda feature
Configuration functions related to Smartcard feature
Configuration functions related to Half Duplex feature
Configuration functions related to LIN feature
Advanced Configurations services
FLAG_Management
IT_Management
DMA_Management
Data_Management
Execution
Initialization and de-initialization functions
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: USART Exported Macros

Modules
USART Exported Macros
USART

Modules

Common Write and read registers Macros
Exported_Macros_Helper
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STM32F103xB HAL User Manual: UTILS

Modules
UTILS
STM32F1xx_LL_Driver

Modules

UTILS Private functions
UTILS Private Constants
UTILS Private Macros
UTILS Exported structures
UTILS Exported Constants
UTILS Exported Functions
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STM32F103xB HAL User Manual: UTILS Exported structures

Data Structures
UTILS Exported structures
UTILS

Data Structures

struct | LL_UTILS_PLLInitTypeDef
UTILS PLL structure definition. More...
struct | LL_UTILS_ClkInitTypeDef
UTILS System, AHB and APB buses clock configuration structure definition. More...
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: UTILS Exported Constants

Modules
UTILS Exported Constants
UTILS

Modules

HSE Bypass activation
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STM32F103xB HAL User Manual: UTILS Exported Functions

Modules
UTILS Exported Functions
UTILS

Modules

DEVICE ELECTRONIC SIGNATURE
DELAY
SYSTEM

System Configuration functions.

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STM32F103xB HAL User Manual: WWDG

Modules
WWDG
STM32F1xx_HAL_Driver

WWDG HAL module driver. More...

Modules

WWDG Exported Functions
WWDG Exported Types
WWDG Exported Constants
WWDG Private Macros
WWDG Exported Macros

Detailed Description

WWDG HAL module driver.

Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

WWDG Interrupt definition
WWDG Flag definition

WWDG Flag definition.

WWDG Prescaler
WWDG Early Wakeup Interrupt Mode
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STM32F103xB HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Initialization and Configuration functions

Initialization and Configuration functions.

IO operation functions

IO operation functions.

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STM32F103xB HAL User Manual: WWDG Exported Types

Data Structures
WWDG Exported Types
WWDG

Data Structures

struct | WWDG_InitTypeDef
WWDG Init structure definition. More...
struct | WWDG_HandleTypeDef
WWDG handle Structure definition. More...
Generated on Thu Mar 23 2017 15:22:27 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: WWDG Exported Constants

Modules
WWDG Exported Constants
WWDG

Modules

IT Defines

IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions.

PRESCALER
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STM32F103xB HAL User Manual: WWDG Exported Functions

Modules
WWDG Exported Functions
WWDG

Modules

Configuration
FLAG_Management
IT_Management
Generated on Thu Mar 23 2017 15:22:30 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: WWDG Exported Macros

Modules
WWDG Exported Macros
WWDG

Modules

Common Write and read registers macros
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STM32F103xB HAL User Manual: I2C_rmtollPages.txt File Reference

  • File List
  • Globals
I2C_rmtollPages.txt File Reference
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: I2S_rmtollPages.txt File Reference

  • File List
  • Globals
I2S_rmtollPages.txt File Reference
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STM32F103xB HAL User Manual: IWDG_rmtollPages.txt File Reference

  • File List
  • Globals
IWDG_rmtollPages.txt File Reference
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STM32F103xB HAL User Manual: Modules

Modules
Here is a list of all modules:
  • STM32F1xx_LL_Driver
    • ADC
      • ADC Private Constants
      • ADC Private Macros
      • ADC Exported Init structure
      • ADC Exported Constants
        • ADC flags
        • ADC interruptions for configuration (interruption enable or disable)
        • ADC registers compliant with specific purpose
        • ADC common - Measurement path to internal channels
        • ADC instance - Resolution
        • ADC instance - Data alignment
        • ADC instance - Scan selection
        • ADC instance - Groups
        • ADC instance - Channel number
        • ADC group regular - Trigger source
        • ADC group regular - Trigger edge
        • ADC group regular - Continuous mode
        • ADC group regular - DMA transfer of ADC conversion data
        • ADC group regular - Sequencer scan length
        • ADC group regular - Sequencer discontinuous mode
        • ADC group regular - Sequencer ranks
        • ADC group injected - Trigger source
        • ADC group injected - Trigger edge
        • ADC group injected - Automatic trigger mode
        • ADC group injected - Sequencer scan length
        • ADC group injected - Sequencer discontinuous mode
        • ADC group injected - Sequencer ranks
        • Channel - Sampling time
        • Analog watchdog - Analog watchdog number
        • Analog watchdog - Monitored channels
        • Analog watchdog - Thresholds
        • Multimode - Mode
        • Multimode - ADC master or slave
        • Definitions of ADC hardware constraints delays
      • ADC Exported Macros
        • Common write and read registers Macros
        • ADC helper macro
      • ADC Exported Functions
        • ADC DMA management
        • Configuration of ADC hierarchical scope: common to several ADC instances
        • Configuration of ADC hierarchical scope: ADC instance
        • Configuration of ADC hierarchical scope: group regular
        • Configuration of ADC hierarchical scope: group injected
        • Configuration of ADC hierarchical scope: channels
        • Configuration of ADC transversal scope: analog watchdog
        • Configuration of ADC hierarchical scope: multimode
        • Operation on ADC hierarchical scope: ADC instance
        • Operation on ADC hierarchical scope: group regular
        • Operation on ADC hierarchical scope: group injected
        • ADC flag management
        • ADC IT management
        • Initialization and de-initialization functions
    • BUS
      • BUS Exported Constants
        • AHB1 GRP1 PERIPH
        • APB1 GRP1 PERIPH
        • APB2 GRP1 PERIPH
      • BUS Exported Functions
        • AHB1
        • APB1
        • APB2
    • CORTEX
      • CORTEX Exported Constants
        • SYSTICK Clock Source
        • Handler Fault type
      • CORTEX Exported Functions
        • SYSTICK
        • LOW POWER MODE
        • HANDLER
        • MCU INFO
    • CRC
      • CRC Exported Macros
        • Common Write and read registers Macros
      • CRC Exported Functions
        • CRC Configuration functions
        • Data_Management
        • Initialization and de-initialization functions
    • DMA
      • DMA Private Variables
      • DMA Private Macros
      • DMA Exported Init structure
      • DMA Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • CHANNEL
        • Transfer Direction
        • Transfer mode
        • Peripheral increment mode
        • Memory increment mode
        • Peripheral data alignment
        • Memory data alignment
        • Transfer Priority level
      • DMA Exported Macros
        • Common Write and read registers macros
        • Convert DMAxChannely
      • DMA Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
        • Initialization and de-initialization functions
    • EXTI
      • EXTI Private Macros
      • EXTI Exported Init structure
      • EXTI Exported Constants
        • LINE
        • Mode
        • Edge Trigger
      • EXTI Exported Macros
        • Common Write and read registers Macros
      • EXTI Exported Functions
        • IT_Management
        • Event_Management
        • Rising_Trigger_Management
        • Falling_Trigger_Management
        • Software_Interrupt_Management
        • Flag_Management
        • Initialization and de-initialization functions
    • GPIO
      • GPIO Private Constants
      • GPIO Private Macros
      • GPIO Exported Init structures
      • GPIO Exported Constants
        • PIN
        • Mode
        • Output Type
        • Output Speed
        • Pull Up Pull Down
        • EVENTOUT Pin
        • EVENTOUT Port
        • GPIO EXTI PORT
        • GPIO EXTI LINE
      • GPIO Exported Macros
        • Common Write and read registers Macros
      • GPIO Exported Functions
        • Port Configuration
        • Data Access
        • Alternate Function Remapping
        • Output Event configuration
        • EXTI external interrupt
        • Initialization and de-initialization functions
    • I2C
      • I2C Private Constants
      • I2C Private Macros
      • I2C Exported Init structure
      • I2C Exported Constants
        • Get Flags Defines
        • IT Defines
        • Own Address 1 Length
        • Fast Mode Duty Cycle
        • Master Clock Speed Mode
        • Peripheral Mode
        • Acknowledge Generation
        • Read Write Direction
      • I2C Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Helper
      • I2C Exported Functions
        • Configuration
        • IT_Management
        • FLAG_management
        • Data_Management
        • Initialization and de-initialization functions
    • I2S
      • I2S Private Constants
      • I2S Private Macros
      • I2S Exported Init structure
      • I2S Exported Constants
        • Get Flags Defines
        • IT Defines
        • Data format
        • Clock Polarity
        • I2s Standard
        • Operation Mode
        • Prescaler Factor
        • MCLK Output
        • Audio Frequency
      • I2S Exported Macros
        • Common Write and read registers Macros
      • I2S Exported Functions
        • Configuration
        • FLAG Management
        • Interrupt Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • IWDG
      • IWDG Private Constants
      • IWDG Exported Constants
        • Get Flags Defines
        • Prescaler Divider
      • IWDG Exported Macros
        • Common Write and read registers Macros
      • IWDG Exported Functions
        • Configuration
        • FLAG_Management
    • PWR
      • PWR Exported Constants
        • Clear Flags Defines
        • Get Flags Defines
        • Mode Power
        • Regulator Mode In Deep Sleep Mode
        • Power Voltage Detector Level
        • Wakeup Pins
      • PWR Exported Macros
        • Common write and read registers Macros
      • PWR Exported Functions
        • Configuration
        • FLAG_Management
        • De-initialization function
    • RCC
      • RCC Private functions
      • RCC Private Macros
      • RCC Exported Types
        • Clocks Frequency Structure
      • RCC Exported Constants
        • Oscillator Values adaptation
        • Clear Flags Defines
        • Get Flags Defines
        • IT Defines
        • System clock switch
        • System clock switch status
        • AHB prescaler
        • APB low-speed prescaler (APB1)
        • APB high-speed prescaler (APB2)
        • MCO1 SOURCE selection
        • Peripheral clock frequency
        • Peripheral USB clock source selection
        • Peripheral ADC clock source selection
        • Peripheral USB get clock source
        • Peripheral ADC get clock source
        • RTC clock source selection
        • PLL Multiplicator factor
        • PLL SOURCE
        • PREDIV Division factor
      • RCC Exported Macros
        • Common Write and read registers Macros
        • Calculate frequencies
      • RCC Exported Functions
        • HSE
        • HSI
        • LSE
        • LSI
        • System
        • MCO
        • Peripheral Clock Source
        • RTC
        • PLL
        • FLAG Management
        • IT Management
        • De-initialization function
        • Get system and peripherals clocks frequency functions
    • SPI
      • SPI Private Constants
      • SPI Private Macros
      • SPI Exported Init structure
      • SPI Exported Constants
        • Get Flags Defines
        • IT Defines
        • Operation Mode
        • Clock Phase
        • Clock Polarity
        • Baud Rate Prescaler
        • Transmission Bit Order
        • Transfer Mode
        • Slave Select Pin Mode
        • Datawidth
        • CRC Calculation
      • SPI Exported Macros
        • Common Write and read registers Macros
      • SPI Exported Functions
        • Configuration
        • CRC Management
        • Slave Select Pin Management
        • FLAG Management
        • Interrupt Management
        • DMA Management
        • DATA Management
        • Initialization and de-initialization functions
    • SYSTEM
      • SYSTEM Private Constants
      • SYSTEM Exported Constants
        • DBGMCU TRACE Pin Assignment
        • DBGMCU APB1 GRP1 STOP IP
        • DBGMCU APB2 GRP1 STOP IP
        • FLASH LATENCY
      • SYSTEM Exported Functions
        • DBGMCU
        • FLASH
    • TIM
      • TIM Private Functions
      • TIM Private Variables
      • TIM Private Constants
      • TIM Private Macros
      • TIM Exported Init structure
      • TIM Exported Constants
        • Get Flags Defines
        • Break Enable
        • Automatic output enable
        • IT Defines
        • Update Source
        • One Pulse Mode
        • Counter Mode
        • Clock Division
        • Counter Direction
        • Capture Compare Update Source
        • Capture Compare DMA Request
        • Lock Level
        • Channel
        • Output Configuration State
        • Output Configuration Mode
        • Output Configuration Polarity
        • Output Configuration Idle State
        • Active Input Selection
        • Input Configuration Prescaler
        • Input Configuration Filter
        • Input Configuration Polarity
        • Clock Source
        • Encoder Mode
        • Trigger Output
        • Slave Mode
        • Trigger Selection
        • External Trigger Polarity
        • External Trigger Prescaler
        • External Trigger Filter
        • break polarity
        • OSSI
        • OSSR
        • DMA Burst Base Address
        • DMA Burst Length
      • TIM Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros
      • TIM Exported Functions
        • Time Base configuration
        • Capture Compare configuration
        • Output channel configuration
        • Input channel configuration
        • Counter clock selection
        • Timer synchronisation configuration
        • Break function configuration
        • DMA burst mode configuration
        • Initialisation and deinitialisation functions
      • FLAG-Management
      • IT-Management
      • DMA-Management
      • EVENT-Management
      • Initialisation and deinitialisation functions
    • USART
      • USART Private Constants
      • USART Private Macros
      • USART Exported Init structures
      • USART Exported Constants
        • Get Flags Defines
        • IT Defines
        • Communication Direction
        • Parity Control
        • Wakeup
        • Datawidth
        • Clock Signal
        • Last Clock Pulse
        • Clock Phase
        • Clock Polarity
        • Stop Bits
        • Hardware Control
        • IrDA Power
        • LIN Break Detection Length
      • USART Exported Macros
        • Common Write and read registers Macros
        • Exported_Macros_Helper
      • USART Exported Functions
        • Configuration functions
        • Configuration functions related to Irda feature
        • Configuration functions related to Smartcard feature
        • Configuration functions related to Half Duplex feature
        • Configuration functions related to LIN feature
        • Advanced Configurations services
        • FLAG_Management
        • IT_Management
        • DMA_Management
        • Data_Management
        • Execution
        • Initialization and de-initialization functions
    • UTILS
      • UTILS Private functions
      • UTILS Private Constants
      • UTILS Private Macros
      • UTILS Exported structures
      • UTILS Exported Constants
        • HSE Bypass activation
      • UTILS Exported Functions
        • DEVICE ELECTRONIC SIGNATURE
        • DELAY
        • SYSTEM
    • WWDG
      • WWDG Exported Constants
        • IT Defines
        • PRESCALER
      • WWDG Exported Macros
        • Common Write and read registers macros
      • WWDG Exported Functions
        • Configuration
        • FLAG_Management
        • IT_Management
  • STM32F1xx_HAL_Driver
    • HAL
      • HAL Private Constants
      • HAL Private Variables
      • HAL Exported Functions
        • Initialization and de-initialization Functions
        • HAL Control functions
      • HAL Exported Macros
        • Freeze Unfreeze Peripherals in Debug mode
    • ADC
      • ADC Private Constants
        • ADC conversion cycles
        • ADC sampling times all channels
      • ADC Private Functions
      • ADC Exported Functions
        • Initialization/de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • ADC Exported Types
      • ADC Exported Constants
        • ADC Error Code
        • ADC data alignment
        • ADC scan mode
        • ADC external trigger enable for regular group
        • ADC channels
        • ADC sampling times
        • ADC rank into regular group
        • ADC analog watchdog mode
        • ADC conversion group
        • ADC Event type
        • ADC interrupts definition
        • ADC flags definition
      • ADC Exported Macros
      • ADC Private Macros
        • ADC range verification
        • ADC regular nb conv verification
        • ADC regular discontinuous mode number verification
    • ADCEx
      • ADCEx Private Constants
        • ADC Extended Internal HAL driver trigger selection for regular group
        • ADC Extended Internal HAL driver trigger selection for injected group
      • ADCEx Exported Functions
        • Extended Extended IO operation functions
        • Extended Peripheral Control functions
      • ADCEx Exported Types
      • ADCEx Exported Constants
        • ADCEx rank into injected group
        • ADCEx external trigger enable for injected group
        • ADC External trigger selection for regular group
        • ADCEx External trigger selection for injected group
        • ADC Extended Dual ADC Mode
      • ADCEx Private Macro
        • ADCEx injected nb conv verification
    • CAN
      • CAN Private Constants
      • CAN Private Functions
      • CAN Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral State and Error functions
      • CAN Exported Types
      • CAN Exported Constants
        • CAN Error Code
        • CAN initialization Status
        • CAN Operating Mode
        • CAN Synchronization Jump Width
        • CAN Time Quantum in Bit Segment 1
        • CAN Time Quantum in bit segment 2
        • CAN Filter Mode
        • CAN Filter Scale
        • CAN Filter FIFO
        • CAN Identifier Type
        • CAN Remote Transmission Request
        • CAN Transmit Constants
        • CAN Receive FIFO Number
        • CAN Flags
        • CAN Interrupts
      • CAN Exported Macros
      • CAN Private Macros
    • CANEx
      • CAN Extended Private Macros
    • CORTEX
      • CORTEX Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • Cortex Exported Types
      • CORTEX Exported Constants
        • CORTEX Preemption Priority Group
        • CORTEX _SysTick clock source
      • CORTEX Private Macros
    • CRC
      • CRC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
        • Peripheral State functions
      • CRC Exported Types
      • CRC Exported Macros
    • DAC
    • DACEx
    • DMA
      • DMA Private Functions
      • DMA Exported Functions
        • Initialization and de-initialization functions
        • Input and Output operation functions
        • Peripheral State and Errors functions
      • DMA Exported Types
      • DMA Exported Constants
        • DMA Error Code
        • DMA Data transfer direction
        • DMA Peripheral incremented mode
        • DMA Memory incremented mode
        • DMA Peripheral data size
        • DMA Memory data size
        • DMA mode
        • DMA Priority level
        • DMA interrupt enable definitions
        • DMA flag definitions
      • DMA Exported Macros
      • DMA Private Macros
    • DMAEx
      • DMA Extended Exported Macros
        • DMA Low density and Medium density product devices
    • FLASH
      • FLASH Private Constants
      • FLASH Private Macros
      • FLASH Private Variables
      • FLASH Private Functions
      • FLASH Exported Functions
        • Programming operation functions
        • Peripheral Control functions
        • Peripheral errors functions
      • FLASH Exported Types
      • FLASH Exported Constants
        • FLASH Error Codes
        • FLASH Type Program
        • FLASH Latency
      • FLASH Exported Macros
        • FLASH Half Cycle
        • FLASH Latency
        • FLASH Prefetch
    • FLASHEx
      • FLASHEx Private Constants
      • FLASHEx Private Macros
      • FLASHEx Private Functions
      • FLASHEx Exported Functions
        • FLASHEx Memory Erasing functions
        • Option Bytes Programming functions
      • FLASHEx Exported Types
      • FLASHEx Exported Constants
        • FLASH Constants
          • Page Size
          • Type Erase
          • Banks
          • Flag definition
          • Interrupt definition
        • Option Byte Constants
          • Option Bytes Type
          • Option Byte WRP State
          • Option Bytes Write Protection
          • Option Byte Read Protection
          • Option Byte IWatchdog
          • Option Byte nRST STOP
          • Option Byte nRST STDBY
          • Option Byte Data Address
      • FLASHEx Exported Macros
        • Interrupt
    • GPIO
      • GPIO Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
      • GPIO Exported Types
      • GPIO Exported Constants
        • GPIO pins define
        • GPIO mode define
        • GPIO speed define
        • GPIO pull define
      • GPIO Exported Macros
      • GPIO Private Constants
      • GPIO Private Macros
      • GPIO Private Functions
    • GPIOEx
      • GPIOEx Exported Functions
        • Extended features functions
      • GPIOEx Exported Constants
        • EVENTOUT Cortex Configuration
          • EVENTOUT Pin
          • EVENTOUT Port
        • Alternate Function Remapping
      • GPIOEx Private Macros
    • I2C
      • I2C Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State, Mode and Error functions
      • I2C Exported Types
      • I2C Exported Constants
        • I2C Error Code
        • I2C duty cycle in fast mode
        • I2C addressing mode
        • I2C dual addressing mode
        • I2C general call addressing mode
        • I2C nostretch mode
        • I2C Memory Address Size
        • I2C XferDirection definition
        • I2C XferOptions definition
        • I2C Interrupt configuration definition
        • I2C Flag definition
      • I2C Exported Macros
      • I2C Private Constants
      • I2C Private Macros
        • I2C Private macros to check input parameters
      • I2C Private Functions
      • I2C_Private_Define
    • IRDA
      • IrDA Exported Functions
        • IrDA Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • IRDA Exported Types
      • IRDA Exported constants
        • IRDA Error Code
        • IRDA Word Length
        • IRDA Parity
        • IRDA Transfer Mode
        • IRDA Low Power
        • IRDA Flags
        • IRDA Interrupt Definitions
      • IRDA Exported Macros
      • IRDA Private Constants
      • IRDA Private Macros
      • IRDA Private Functions
    • IWDG
      • IWDG Private Defines
      • IWDG Exported Types
      • IWDG Exported Constants
        • IWDG Prescaler
      • IWDG Exported Macros
      • IWDG Exported Functions
        • Initialization and Start functions
        • IO operation functions
      • IWDG Private Constants
      • IWDG Private Macros
    • PCD
      • PCD Private Macros
        • PCD Instance definition
      • PCD Private Functions
      • PCD Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State functions
      • PCD Exported Types
      • PCD Exported Constants
        • PCD Speed
        • PCD PHY Module
        • Turnaround Timeout Value
      • PCD Exported Macros
      • PCD Private Constants
        • USB EXTI line interrupt
        • PCD EP0 MPS
        • PCD ENDP
        • PCD Endpoint Kind
    • PCDEx
      • PCDEx Exported Functions
        • Peripheral Control functions
        • Peripheral State functions
    • PWR
      • PWR Private Constants
        • PWR PVD Mode Mask
        • PWR Register alias address
        • PWR CR Register alias address
        • PWR CSR Register alias address
      • PWR Private Functions
      • PWR Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • PWR Exported Types
      • PWR Exported Constants
        • PWR PVD detection level
        • PWR PVD Mode
        • PWR WakeUp Pins
        • PWR Regulator state in SLEEP/STOP mode
        • PWR SLEEP mode entry
        • PWR STOP mode entry
        • PWR Flag
      • PWR Exported Macros
      • PWR Private Macros
    • RCC
      • RCC Private Constants
        • RCC Timeout
        • Register offsets
        • BitAddress AliasRegion
      • RCC Private Macros
        • Alias define maintained for legacy
      • RCC Private Variables
      • RCC Exported Functions
        • Initialization and de-initialization functions
        • Peripheral Control functions
      • RCC Exported Types
      • RCC Exported Constants
        • PLL Clock Source
        • Oscillator Type
        • HSE Config
        • LSE Config
        • HSI Config
        • LSI Config
        • PLL Config
        • System Clock Type
        • System Clock Source
        • System Clock Source Status
        • AHB Clock Source
        • APB1 APB2 Clock Source
        • RTC Clock Source
        • MCO Index
        • MCO Clock Prescaler
        • Interrupts
        • Flags
      • RCC Exported Macros
        • Peripheral Clock Enable Disable
        • AHB Peripheral Clock Enable Disable Status
        • APB1 Clock Enable Disable
        • APB1 Peripheral Clock Enable Disable Status
        • APB2 Clock Enable Disable
        • APB2 Peripheral Clock Enable Disable Status
        • APB1 Force Release Reset
        • APB2 Force Release Reset
        • HSI Configuration
        • LSI Configuration
        • HSE Configuration
        • LSE Configuration
        • PLL Configuration
        • Get Clock source
        • RCC Extended MCOx Clock Config
        • RCC RTC Clock Configuration
        • Flags Interrupts Management
    • RCCEx
      • RCCEx Private Constants
      • RCCEx Private Macros
      • RCCEx Exported Functions
        • Peripheral Control functions
      • RCCEx Exported Types
      • RCCEx Exported Constants
        • Periph Clock Selection
        • ADC Prescaler
        • USB Prescaler
        • HSE Prediv1 Factor
        • PLL Multiplication Factor
        • MCO1 Clock Source
      • RCCEx Exported Macros
        • Peripheral Clock Enable Disable
        • AHB1 Peripheral Clock Enable Disable Status
        • APB1 Clock Enable Disable
        • APB1 Peripheral Clock Enable Disable Status
        • APB2 Clock Enable Disable
        • APB2 Peripheral Clock Enable Disable Status
        • APB1 Force Release Reset
        • APB2 Force Release Reset
        • HSE Configuration
        • Peripheral Configuration
    • RTC
      • RTC Private Constants
        • Default Timeout Value
        • RTC EXTI Line event
      • RTC Private Macros
      • RTC Private Functions
      • RTC Exported Functions
        • Initialization and de-initialization functions
        • Time and Date functions
        • Alarm functions
        • Peripheral State functions
        • Peripheral Control functions
      • RTC Exported Types
      • RTC Exported Constants
        • Automatic calculation of prediv for 1sec timebase
        • Input Parameter Format
        • Month Definitions
        • WeekDay Definitions
        • Alarms Definitions
        • Output source to output on the Tamper pin
        • Interrupts Definitions
        • Flags Definitions
      • RTC Exported Macros
    • RTCEx
      • RTCEx Private Macros
        • Alias define maintained for legacy
        • Private macros to check input parameters
      • RTCEx Exported Functions
        • RTC Tamper functions
        • RTC Second functions
        • Extended Peripheral Control functions
      • RTCEx Exported Types
      • RTCEx Exported Constants
        • Tamper Pins Definitions
        • Tamper Trigger Definitions
        • Backup Registers Definitions
      • RTCEx Exported Macros
    • SMARTCARD
      • SMARTCARD Exported Functions
        • SmartCard Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SMARTCARD Exported Types
      • SMARTCARD Exported constants
        • SMARTCARD Error Code
        • SMARTCARD Word Length
        • SMARTCARD Number of Stop Bits
        • SMARTCARD Parity
        • SMARTCARD Mode
        • SMARTCARD Clock Polarity
        • SMARTCARD Clock Phase
        • SMARTCARD Last Bit
        • SMARTCARD NACK State
        • SMARTCARD DMA requests
        • SMARTCARD Prescaler
        • SMARTCARD Flags
        • SMARTCARD Interrupts Definition
      • SMARTCARD Exported Macros
      • SMARTCARD Private Constants
      • SMARTCARD Private Macros
      • SMARTCARD Private Functions
    • SPI
      • SPI Private Constants
      • SPI Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • SPI Exported Types
      • SPI Exported Constants
        • SPI Error Code
        • SPI Mode
        • SPI Direction Mode
        • SPI Data Size
        • SPI Clock Polarity
        • SPI Clock Phase
        • SPI Slave Select Management
        • SPI BaudRate Prescaler
        • SPI MSB LSB Transmission
        • SPI TI Mode
        • SPI CRC Calculation
        • SPI Interrupt Definition
        • SPI Flags Definition
      • SPI Exported Macros
      • SPI Private Macros
      • SPI Private Functions
      • SPI Private Variables
    • TIM
      • TIM Private Functions
      • TIM Exported Functions
        • Time Base functions
        • Time Output Compare functions
        • Time PWM functions
        • Time Input Capture functions
        • Time One Pulse functions
        • Time Encoder functions
        • TIM IRQ handler management
        • Peripheral Control functions
        • TIM Callbacks functions
        • Peripheral State functions
      • TIM Exported Types
      • TIM Exported Constants
        • TIM Input Channel Polarity
        • TIM ETR Polarity
        • TIM ETR Prescaler
        • TIM Counter Mode
        • TIM ClockDivision
        • TIM Auto-Reload Preload
        • TIM Output Compare and PWM modes
        • TIM Output Compare State
        • TIM Output Fast State
        • TIM Complementary Output Compare State
        • TIM Output Compare Polarity
        • TIM Complementary Output Compare Polarity
        • TIM Output Compare Idle State
        • TIM Complementary Output Compare Idle State
        • TIM Channel
        • TIM Input Capture Polarity
        • TIM Input Capture Selection
        • TIM Input Capture Prescaler
        • TIM One Pulse Mode
        • TIM Encoder Mode
        • TIM Interrupt Definition
        • TIM Commutation Source
        • TIM DMA Sources
        • TIM Event Source
        • TIM Flag Definition
        • TIM Clock Source
        • TIM Clock Polarity
        • TIM Clock Prescaler
        • TIM ClearInput Source
        • TIM Clear Input Polarity
        • TIM Clear Input Prescaler
        • TIM OSSR Off State Selection for Run mode state
        • TIM OSSI Off State Selection for Idle mode state
        • TIM Lock level
        • TIM Break Input Enable Disable
        • TIM Break Input Polarity
        • TIM Automatic Output Enable
        • TIM Master Mode Selection
        • TIM Slave Mode
        • TIM Master Slave Mode
        • TIM Trigger Selection
        • TIM Trigger Polarity
        • TIM Trigger Prescaler
        • TIM TI1 Input Selection
        • TIM DMA Base Address
        • TIM DMA Burst Length
        • TIM DMA Handle Index
        • TIM Capture/Compare Channel State
      • TIM Private Constants
      • TIM Private Macros
      • TIM Exported Macros
    • TIMEx
      • TIMEx Private Functions
      • TIMEx Exported Functions
        • Timer Hall Sensor functions
        • Timer Complementary Output Compare functions
        • Timer Complementary PWM functions
        • Timer Complementary One Pulse functions
        • Peripheral Control functions
        • Extension Callbacks functions
        • Extension Peripheral State functions
      • TIMEx Exported Types
      • TIMEx Exported Constants
        • TIMEx Clock Filter
    • UART
      • UART Exported Functions
        • Initialization and de-initialization functions
        • IO operation functions
        • Peripheral Control functions
        • Peripheral State and Errors functions
      • UART Exported Types
      • UART Exported constants
        • UART Error Code
        • UART Word Length
        • UART Number of Stop Bits
        • UART Parity
        • UART Hardware Flow Control
        • UART Transfer Mode
        • UART State
        • UART Over Sampling
        • UART LIN Break Detection Length
        • UART Wakeup Functions
        • UART FLags
        • UART Interrupt Definitions
      • UART Exported Macros
      • UART Private Constants
      • UART Private Macros
      • UART Private Functions
    • USART
      • USART Exported Functions
        • USART Initialization and de-initialization functions
        • IO operation functions
        • Peripheral State and Errors functions
      • USART Private Functions
      • USART Exported Types
      • USART Exported Constants
        • USART Error Code
        • USART Word Length
        • USART Number of Stop Bits
        • USART Parity
        • USART Mode
        • USART Clock
        • USART Clock Polarity
        • USART Clock Phase
        • USART Last Bit
        • USART NACK State
        • USART Flags
        • USART Interrupts Definition
      • USART Exported Macros
      • USART Private Constants
      • USART Private Macros
    • WWDG
      • WWDG Exported Functions
        • Initialization and Configuration functions
        • IO operation functions
      • WWDG Exported Types
      • WWDG Exported Constants
        • WWDG Interrupt definition
        • WWDG Flag definition
        • WWDG Prescaler
        • WWDG Early Wakeup Interrupt Mode
      • WWDG Private Macros
      • WWDG Exported Macros
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STM32F103xB HAL User Manual: PWR_rmtollPages.txt File Reference

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PWR_rmtollPages.txt File Reference
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STM32F103xB HAL User Manual: RCC_rmtollPages.txt File Reference

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RCC_rmtollPages.txt File Reference
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STM32F103xB HAL User Manual: SPI_rmtollPages.txt File Reference

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STM32F103xB HAL User Manual: stm32f1xx_hal.c Source File

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  • STM32F1xx_HAL_Driver
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stm32f1xx_hal.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   HAL module driver.
00008   *          This is the common part of the HAL initialization
00009   *
00010   @verbatim
00011   ==============================================================================
00012                      ##### How to use this driver #####
00013   ==============================================================================
00014     [..]
00015     The common HAL driver contains a set of generic and common APIs that can be
00016     used by the PPP peripheral drivers and the user to start using the HAL.
00017     [..]
00018     The HAL contains two APIs' categories:
00019          (+) Common HAL APIs
00020          (+) Services HAL APIs
00021
00022   @endverbatim
00023   ******************************************************************************
00024   * @attention
00025   *
00026   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00027   *
00028   * Redistribution and use in source and binary forms, with or without modification,
00029   * are permitted provided that the following conditions are met:
00030   *   1. Redistributions of source code must retain the above copyright notice,
00031   *      this list of conditions and the following disclaimer.
00032   *   2. Redistributions in binary form must reproduce the above copyright notice,
00033   *      this list of conditions and the following disclaimer in the documentation
00034   *      and/or other materials provided with the distribution.
00035   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00036   *      may be used to endorse or promote products derived from this software
00037   *      without specific prior written permission.
00038   *
00039   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00040   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00041   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00042   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00043   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00044   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00045   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00046   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00047   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00048   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00049   *
00050   ******************************************************************************
00051   */
00052
00053 /* Includes ------------------------------------------------------------------*/
00054 #include "stm32f1xx_hal.h"
00055
00056 /** @addtogroup STM32F1xx_HAL_Driver
00057   * @{
00058   */
00059
00060 /** @defgroup HAL HAL
00061   * @brief HAL module driver.
00062   * @{
00063   */
00064
00065 #ifdef HAL_MODULE_ENABLED
00066
00067 /* Private typedef -----------------------------------------------------------*/
00068 /* Private define ------------------------------------------------------------*/
00069
00070 /** @defgroup HAL_Private_Constants HAL Private Constants
00071   * @{
00072   */
00073 /**
00074  * @brief STM32F1xx HAL Driver version number
00075    */
00076 #define __STM32F1xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
00077 #define __STM32F1xx_HAL_VERSION_SUB1   (0x00U) /*!< [23:16] sub1 version */
00078 #define __STM32F1xx_HAL_VERSION_SUB2   (0x05U) /*!< [15:8]  sub2 version */
00079 #define __STM32F1xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
00080 #define __STM32F1xx_HAL_VERSION         ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
00081                                         |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
00082                                         |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
00083                                         |(__STM32F1xx_HAL_VERSION_RC))
00084
00085 #define IDCODE_DEVID_MASK    0x00000FFFU
00086
00087 /**
00088   * @}
00089   */
00090
00091 /* Private macro -------------------------------------------------------------*/
00092 /* Private variables ---------------------------------------------------------*/
00093
00094 /** @defgroup HAL_Private_Variables HAL Private Variables
00095   * @{
00096   */
00097 __IO uint32_t uwTick;
00098 /**
00099   * @}
00100   */
00101 /* Private function prototypes -----------------------------------------------*/
00102 /* Exported functions ---------------------------------------------------------*/
00103
00104 /** @defgroup HAL_Exported_Functions HAL Exported Functions
00105   * @{
00106   */
00107
00108 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
00109  *  @brief    Initialization and de-initialization functions
00110  *
00111 @verbatim
00112  ===============================================================================
00113               ##### Initialization and de-initialization functions #####
00114  ===============================================================================
00115    [..]  This section provides functions allowing to:
00116       (+) Initializes the Flash interface, the NVIC allocation and initial clock
00117           configuration. It initializes the source of time base also when timeout
00118           is needed and the backup domain when enabled.
00119       (+) de-Initializes common part of the HAL.
00120       (+) Configure The time base source to have 1ms time base with a dedicated
00121           Tick interrupt priority.
00122         (++) Systick timer is used by default as source of time base, but user
00123              can eventually implement his proper time base source (a general purpose
00124              timer for example or other time source), keeping in mind that Time base
00125              duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
00126              handled in milliseconds basis.
00127         (++) Time base configuration function (HAL_InitTick ()) is called automatically
00128              at the beginning of the program after reset by HAL_Init() or at any time
00129              when clock is configured, by HAL_RCC_ClockConfig().
00130         (++) Source of time base is configured  to generate interrupts at regular
00131              time intervals. Care must be taken if HAL_Delay() is called from a
00132              peripheral ISR process, the Tick interrupt line must have higher priority
00133             (numerically lower) than the peripheral interrupt. Otherwise the caller
00134             ISR process will be blocked.
00135        (++) functions affecting time base configurations are declared as __weak
00136              to make  override possible  in case of other  implementations in user file.
00137 @endverbatim
00138   * @{
00139   */
00140
00141 /**
00142   * @brief  This function is used to initialize the HAL Library; it must be the first
00143   *         instruction to be executed in the main program (before to call any other
00144   *         HAL function), it performs the following:
00145   *           Configure the Flash prefetch.
00146   *           Configures the SysTick to generate an interrupt each 1 millisecond,
00147   *           which is clocked by the HSI (at this stage, the clock is not yet
00148   *           configured and thus the system is running from the internal HSI at 16 MHz).
00149   *           Set NVIC Group Priority to 4.
00150   *           Calls the HAL_MspInit() callback function defined in user file
00151   *           "stm32f1xx_hal_msp.c" to do the global low level hardware initialization
00152   *
00153   * @note   SysTick is used as time base for the HAL_Delay() function, the application
00154   *         need to ensure that the SysTick time base is always set to 1 millisecond
00155   *         to have correct HAL operation.
00156   * @retval HAL status
00157   */
00158 HAL_StatusTypeDef HAL_Init(void)
00159 {
00160   /* Configure Flash prefetch */
00161 #if (PREFETCH_ENABLE != 0)
00162 #if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
00163     defined(STM32F102x6) || defined(STM32F102xB) || \
00164     defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
00165     defined(STM32F105xC) || defined(STM32F107xC)
00166
00167   /* Prefetch buffer is not available on value line devices */
00168   __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
00169 #endif
00170 #endif /* PREFETCH_ENABLE */
00171
00172   /* Set Interrupt Group Priority */
00173   HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
00174
00175   /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
00176   HAL_InitTick(TICK_INT_PRIORITY);
00177
00178   /* Init the low level hardware */
00179   HAL_MspInit();
00180
00181   /* Return function status */
00182   return HAL_OK;
00183 }
00184
00185 /**
00186   * @brief This function de-Initializes common part of the HAL and stops the source
00187   *        of time base.
00188   * @note This function is optional.
00189   * @retval HAL status
00190   */
00191 HAL_StatusTypeDef HAL_DeInit(void)
00192 {
00193   /* Reset of all peripherals */
00194   __HAL_RCC_APB1_FORCE_RESET();
00195   __HAL_RCC_APB1_RELEASE_RESET();
00196
00197   __HAL_RCC_APB2_FORCE_RESET();
00198   __HAL_RCC_APB2_RELEASE_RESET();
00199
00200 #if defined(STM32F105xC) || defined(STM32F107xC)
00201   __HAL_RCC_AHB_FORCE_RESET();
00202   __HAL_RCC_AHB_RELEASE_RESET();
00203 #endif
00204
00205   /* De-Init the low level hardware */
00206   HAL_MspDeInit();
00207
00208   /* Return function status */
00209   return HAL_OK;
00210 }
00211
00212 /**
00213   * @brief  Initializes the MSP.
00214   * @retval None
00215   */
00216 __weak void HAL_MspInit(void)
00217 {
00218   /* NOTE : This function Should not be modified, when the callback is needed,
00219             the HAL_MspInit could be implemented in the user file
00220    */
00221 }
00222
00223 /**
00224   * @brief  DeInitializes the MSP.
00225   * @retval None
00226   */
00227 __weak void HAL_MspDeInit(void)
00228 {
00229   /* NOTE : This function Should not be modified, when the callback is needed,
00230             the HAL_MspDeInit could be implemented in the user file
00231    */
00232 }
00233
00234 /**
00235   * @brief This function configures the source of the time base.
00236   *        The time source is configured  to have 1ms time base with a dedicated
00237   *        Tick interrupt priority.
00238   * @note This function is called  automatically at the beginning of program after
00239   *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
00240   * @note In the default implementation, SysTick timer is the source of time base.
00241   *       It is used to generate interrupts at regular time intervals.
00242   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
00243   *       The the SysTick interrupt must have higher priority (numerically lower)
00244   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
00245   *       The function is declared as __weak  to be overwritten  in case of other
00246   *       implementation  in user file.
00247   * @param TickPriority: Tick interrupt priority.
00248   * @retval HAL status
00249   */
00250 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
00251 {
00252   /*Configure the SysTick to have interrupt in 1ms time basis*/
00253   HAL_SYSTICK_Config(SystemCoreClock/1000U);
00254
00255   /*Configure the SysTick IRQ priority */
00256   HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
00257
00258   /* Return function status */
00259   return HAL_OK;
00260 }
00261
00262 /**
00263   * @}
00264   */
00265
00266 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
00267   *  @brief    HAL Control functions
00268   *
00269 @verbatim
00270  ===============================================================================
00271                       ##### HAL Control functions #####
00272  ===============================================================================
00273     [..]  This section provides functions allowing to:
00274       (+) Provide a tick value in millisecond
00275       (+) Provide a blocking delay in millisecond
00276       (+) Suspend the time base source interrupt
00277       (+) Resume the time base source interrupt
00278       (+) Get the HAL API driver version
00279       (+) Get the device identifier
00280       (+) Get the device revision identifier
00281       (+) Enable/Disable Debug module during SLEEP mode
00282       (+) Enable/Disable Debug module during STOP mode
00283       (+) Enable/Disable Debug module during STANDBY mode
00284
00285 @endverbatim
00286   * @{
00287   */
00288
00289 /**
00290   * @brief This function is called to increment  a global variable "uwTick"
00291   *        used as application time base.
00292   * @note In the default implementation, this variable is incremented each 1ms
00293   *       in Systick ISR.
00294   * @note This function is declared as __weak to be overwritten in case of other
00295   *      implementations in user file.
00296   * @retval None
00297   */
00298 __weak void HAL_IncTick(void)
00299 {
00300   uwTick++;
00301 }
00302
00303 /**
00304   * @brief Provides a tick value in millisecond.
00305   * @note  This function is declared as __weak  to be overwritten  in case of other
00306   *       implementations in user file.
00307   * @retval tick value
00308   */
00309 __weak uint32_t HAL_GetTick(void)
00310 {
00311   return uwTick;
00312 }
00313
00314 /**
00315   * @brief This function provides minimum delay (in milliseconds) based
00316   *        on variable incremented.
00317   * @note In the default implementation , SysTick timer is the source of time base.
00318   *       It is used to generate interrupts at regular time intervals where uwTick
00319   *       is incremented.
00320   * @note This function is declared as __weak to be overwritten in case of other
00321   *       implementations in user file.
00322   * @param Delay: specifies the delay time length, in milliseconds.
00323   * @retval None
00324   */
00325 __weak void HAL_Delay(__IO uint32_t Delay)
00326 {
00327   uint32_t tickstart = HAL_GetTick();
00328   uint32_t wait = Delay;
00329
00330   /* Add a period to guarantee minimum wait */
00331   if (wait < HAL_MAX_DELAY)
00332   {
00333      wait++;
00334   }
00335
00336   while((HAL_GetTick() - tickstart) < wait)
00337   {
00338   }
00339 }
00340
00341 /**
00342   * @brief Suspend Tick increment.
00343   * @note In the default implementation , SysTick timer is the source of time base. It is
00344   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
00345   *       is called, the SysTick interrupt will be disabled and so Tick increment
00346   *       is suspended.
00347   * @note This function is declared as __weak to be overwritten in case of other
00348   *       implementations in user file.
00349   * @retval None
00350   */
00351 __weak void HAL_SuspendTick(void)
00352 {
00353   /* Disable SysTick Interrupt */
00354   CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
00355 }
00356
00357 /**
00358   * @brief Resume Tick increment.
00359   * @note In the default implementation , SysTick timer is the source of time base. It is
00360   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
00361   *       is called, the SysTick interrupt will be enabled and so Tick increment
00362   *       is resumed.
00363   * @note This function is declared as __weak to be overwritten in case of other
00364   *       implementations in user file.
00365   * @retval None
00366   */
00367 __weak void HAL_ResumeTick(void)
00368 {
00369   /* Enable SysTick Interrupt */
00370   SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
00371 }
00372
00373 /**
00374   * @brief  Returns the HAL revision
00375   * @retval version : 0xXYZR (8bits for each decimal, R for RC)
00376   */
00377 uint32_t HAL_GetHalVersion(void)
00378 {
00379  return __STM32F1xx_HAL_VERSION;
00380 }
00381
00382 /**
00383   * @brief Returns the device revision identifier.
00384   * Note: On devices STM32F10xx8 and STM32F10xxB,
00385   *                  STM32F101xC/D/E and STM32F103xC/D/E,
00386   *                  STM32F101xF/G and STM32F103xF/G
00387   *                  STM32F10xx4 and STM32F10xx6
00388   *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
00389   *       debug mode (not accessible by the user software in normal mode).
00390   *       Refer to errata sheet of these devices for more details.
00391   * @retval Device revision identifier
00392   */
00393 uint32_t HAL_GetREVID(void)
00394 {
00395   return((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos);
00396 }
00397
00398 /**
00399   * @brief  Returns the device identifier.
00400   * Note: On devices STM32F10xx8 and STM32F10xxB,
00401   *                  STM32F101xC/D/E and STM32F103xC/D/E,
00402   *                  STM32F101xF/G and STM32F103xF/G
00403   *                  STM32F10xx4 and STM32F10xx6
00404   *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
00405   *       debug mode (not accessible by the user software in normal mode).
00406   *       Refer to errata sheet of these devices for more details.
00407   * @retval Device identifier
00408   */
00409 uint32_t HAL_GetDEVID(void)
00410 {
00411    return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
00412 }
00413
00414 /**
00415   * @brief  Enable the Debug Module during SLEEP mode
00416   * @retval None
00417   */
00418 void HAL_DBGMCU_EnableDBGSleepMode(void)
00419 {
00420   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00421 }
00422
00423 /**
00424   * @brief  Disable the Debug Module during SLEEP mode
00425   * Note: On devices STM32F10xx8 and STM32F10xxB,
00426   *                  STM32F101xC/D/E and STM32F103xC/D/E,
00427   *                  STM32F101xF/G and STM32F103xF/G
00428   *                  STM32F10xx4 and STM32F10xx6
00429   *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
00430   *       debug mode (not accessible by the user software in normal mode).
00431   *       Refer to errata sheet of these devices for more details.
00432   * @retval None
00433   */
00434 void HAL_DBGMCU_DisableDBGSleepMode(void)
00435 {
00436   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00437 }
00438
00439 /**
00440   * @brief  Enable the Debug Module during STOP mode
00441   * Note: On devices STM32F10xx8 and STM32F10xxB,
00442   *                  STM32F101xC/D/E and STM32F103xC/D/E,
00443   *                  STM32F101xF/G and STM32F103xF/G
00444   *                  STM32F10xx4 and STM32F10xx6
00445   *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
00446   *       debug mode (not accessible by the user software in normal mode).
00447   *       Refer to errata sheet of these devices for more details.
00448   * Note: On all STM32F1 devices:
00449   *       If the system tick timer interrupt is enabled during the Stop mode
00450   *       debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
00451   *       the system from Stop mode.
00452   *       Workaround: To debug the Stop mode, disable the system tick timer
00453   *       interrupt.
00454   *       Refer to errata sheet of these devices for more details.
00455   * Note: On all STM32F1 devices:
00456   *       If the system tick timer interrupt is enabled during the Stop mode
00457   *       debug (DBG_STOP bit set in the DBGMCU_CR register ), it will wakeup
00458   *       the system from Stop mode.
00459   *       Workaround: To debug the Stop mode, disable the system tick timer
00460   *       interrupt.
00461   *       Refer to errata sheet of these devices for more details.
00462   * @retval None
00463   */
00464 void HAL_DBGMCU_EnableDBGStopMode(void)
00465 {
00466   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00467 }
00468
00469 /**
00470   * @brief  Disable the Debug Module during STOP mode
00471   * Note: On devices STM32F10xx8 and STM32F10xxB,
00472   *                  STM32F101xC/D/E and STM32F103xC/D/E,
00473   *                  STM32F101xF/G and STM32F103xF/G
00474   *                  STM32F10xx4 and STM32F10xx6
00475   *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
00476   *       debug mode (not accessible by the user software in normal mode).
00477   *       Refer to errata sheet of these devices for more details.
00478   * @retval None
00479   */
00480 void HAL_DBGMCU_DisableDBGStopMode(void)
00481 {
00482   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00483 }
00484
00485 /**
00486   * @brief  Enable the Debug Module during STANDBY mode
00487   * Note: On devices STM32F10xx8 and STM32F10xxB,
00488   *                  STM32F101xC/D/E and STM32F103xC/D/E,
00489   *                  STM32F101xF/G and STM32F103xF/G
00490   *                  STM32F10xx4 and STM32F10xx6
00491   *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
00492   *       debug mode (not accessible by the user software in normal mode).
00493   *       Refer to errata sheet of these devices for more details.
00494   * @retval None
00495   */
00496 void HAL_DBGMCU_EnableDBGStandbyMode(void)
00497 {
00498   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00499 }
00500
00501 /**
00502   * @brief  Disable the Debug Module during STANDBY mode
00503   * Note: On devices STM32F10xx8 and STM32F10xxB,
00504   *                  STM32F101xC/D/E and STM32F103xC/D/E,
00505   *                  STM32F101xF/G and STM32F103xF/G
00506   *                  STM32F10xx4 and STM32F10xx6
00507   *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
00508   *       debug mode (not accessible by the user software in normal mode).
00509   *       Refer to errata sheet of these devices for more details.
00510   * @retval None
00511   */
00512 void HAL_DBGMCU_DisableDBGStandbyMode(void)
00513 {
00514   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00515 }
00516
00517 /**
00518   * @brief Return the unique device identifier (UID based on 96 bits)
00519   * @param UID: pointer to 3 words array.
00520   * @retval Device identifier
00521   */
00522 void HAL_GetUID(uint32_t *UID)
00523 {
00524   UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
00525   UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
00526   UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
00527 }
00528
00529 /**
00530   * @}
00531   */
00532
00533 /**
00534   * @}
00535   */
00536
00537 #endif /* HAL_MODULE_ENABLED */
00538 /**
00539   * @}
00540   */
00541
00542 /**
00543   * @}
00544   */
00545
00546 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal.h Source File

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stm32f1xx_hal.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   This file contains all the functions prototypes for the HAL
00008   *          module driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */
00038
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef __STM32F1xx_HAL_H
00041 #define __STM32F1xx_HAL_H
00042
00043 #ifdef __cplusplus
00044  extern "C" {
00045 #endif
00046
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f1xx_hal_conf.h"
00049
00050 /** @addtogroup STM32F1xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup HAL
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060
00061 /* Exported macro ------------------------------------------------------------*/
00062 /** @defgroup HAL_Exported_Macros HAL Exported Macros
00063   * @{
00064   */
00065
00066 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
00067   * @brief   Freeze/Unfreeze Peripherals in Debug mode
00068   * Note: On devices STM32F10xx8 and STM32F10xxB,
00069   *                  STM32F101xC/D/E and STM32F103xC/D/E,
00070   *                  STM32F101xF/G and STM32F103xF/G
00071   *                  STM32F10xx4 and STM32F10xx6
00072   *       Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
00073   *       debug mode (not accessible by the user software in normal mode).
00074   *       Refer to errata sheet of these devices for more details.
00075   * @{
00076   */
00077
00078 /* Peripherals on APB1 */
00079 /**
00080   * @brief  TIM2 Peripherals Debug mode
00081   */
00082 #define __HAL_DBGMCU_FREEZE_TIM2()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
00083 #define __HAL_DBGMCU_UNFREEZE_TIM2()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
00084
00085 /**
00086   * @brief  TIM3 Peripherals Debug mode
00087   */
00088 #define __HAL_DBGMCU_FREEZE_TIM3()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
00089 #define __HAL_DBGMCU_UNFREEZE_TIM3()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
00090
00091 #if defined (DBGMCU_CR_DBG_TIM4_STOP)
00092 /**
00093   * @brief  TIM4 Peripherals Debug mode
00094   */
00095 #define __HAL_DBGMCU_FREEZE_TIM4()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
00096 #define __HAL_DBGMCU_UNFREEZE_TIM4()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
00097 #endif
00098
00099 #if defined (DBGMCU_CR_DBG_TIM5_STOP)
00100 /**
00101   * @brief  TIM5 Peripherals Debug mode
00102   */
00103 #define __HAL_DBGMCU_FREEZE_TIM5()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
00104 #define __HAL_DBGMCU_UNFREEZE_TIM5()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
00105 #endif
00106
00107 #if defined (DBGMCU_CR_DBG_TIM6_STOP)
00108 /**
00109   * @brief  TIM6 Peripherals Debug mode
00110   */
00111 #define __HAL_DBGMCU_FREEZE_TIM6()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
00112 #define __HAL_DBGMCU_UNFREEZE_TIM6()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
00113 #endif
00114
00115 #if defined (DBGMCU_CR_DBG_TIM7_STOP)
00116 /**
00117   * @brief  TIM7 Peripherals Debug mode
00118   */
00119 #define __HAL_DBGMCU_FREEZE_TIM7()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
00120 #define __HAL_DBGMCU_UNFREEZE_TIM7()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
00121 #endif
00122
00123 #if defined (DBGMCU_CR_DBG_TIM12_STOP)
00124 /**
00125   * @brief  TIM12 Peripherals Debug mode
00126   */
00127 #define __HAL_DBGMCU_FREEZE_TIM12()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
00128 #define __HAL_DBGMCU_UNFREEZE_TIM12()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
00129 #endif
00130
00131 #if defined (DBGMCU_CR_DBG_TIM13_STOP)
00132 /**
00133   * @brief  TIM13 Peripherals Debug mode
00134   */
00135 #define __HAL_DBGMCU_FREEZE_TIM13()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
00136 #define __HAL_DBGMCU_UNFREEZE_TIM13()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
00137 #endif
00138
00139 #if defined (DBGMCU_CR_DBG_TIM14_STOP)
00140 /**
00141   * @brief  TIM14 Peripherals Debug mode
00142   */
00143 #define __HAL_DBGMCU_FREEZE_TIM14()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
00144 #define __HAL_DBGMCU_UNFREEZE_TIM14()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
00145 #endif
00146
00147 /**
00148   * @brief  WWDG Peripherals Debug mode
00149   */
00150 #define __HAL_DBGMCU_FREEZE_WWDG()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
00151 #define __HAL_DBGMCU_UNFREEZE_WWDG()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
00152
00153 /**
00154   * @brief  IWDG Peripherals Debug mode
00155   */
00156 #define __HAL_DBGMCU_FREEZE_IWDG()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
00157 #define __HAL_DBGMCU_UNFREEZE_IWDG()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
00158
00159 /**
00160   * @brief  I2C1 Peripherals Debug mode
00161   */
00162 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()    SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
00163 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
00164
00165 #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
00166 /**
00167   * @brief  I2C2 Peripherals Debug mode
00168   */
00169 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()    SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
00170 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
00171 #endif
00172
00173 #if defined (DBGMCU_CR_DBG_CAN1_STOP)
00174 /**
00175   * @brief  CAN1 Peripherals Debug mode
00176   */
00177 #define __HAL_DBGMCU_FREEZE_CAN1()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
00178 #define __HAL_DBGMCU_UNFREEZE_CAN1()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
00179 #endif
00180
00181 #if defined (DBGMCU_CR_DBG_CAN2_STOP)
00182 /**
00183   * @brief  CAN2 Peripherals Debug mode
00184   */
00185 #define __HAL_DBGMCU_FREEZE_CAN2()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
00186 #define __HAL_DBGMCU_UNFREEZE_CAN2()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
00187 #endif
00188
00189 /* Peripherals on APB2 */
00190 #if defined (DBGMCU_CR_DBG_TIM1_STOP)
00191 /**
00192   * @brief  TIM1 Peripherals Debug mode
00193   */
00194 #define __HAL_DBGMCU_FREEZE_TIM1()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
00195 #define __HAL_DBGMCU_UNFREEZE_TIM1()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
00196 #endif
00197
00198 #if defined (DBGMCU_CR_DBG_TIM8_STOP)
00199 /**
00200   * @brief  TIM8 Peripherals Debug mode
00201   */
00202 #define __HAL_DBGMCU_FREEZE_TIM8()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
00203 #define __HAL_DBGMCU_UNFREEZE_TIM8()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
00204 #endif
00205
00206 #if defined (DBGMCU_CR_DBG_TIM9_STOP)
00207 /**
00208   * @brief  TIM9 Peripherals Debug mode
00209   */
00210 #define __HAL_DBGMCU_FREEZE_TIM9()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
00211 #define __HAL_DBGMCU_UNFREEZE_TIM9()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
00212 #endif
00213
00214 #if defined (DBGMCU_CR_DBG_TIM10_STOP)
00215 /**
00216   * @brief  TIM10 Peripherals Debug mode
00217   */
00218 #define __HAL_DBGMCU_FREEZE_TIM10()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
00219 #define __HAL_DBGMCU_UNFREEZE_TIM10()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
00220 #endif
00221
00222 #if defined (DBGMCU_CR_DBG_TIM11_STOP)
00223 /**
00224   * @brief  TIM11 Peripherals Debug mode
00225   */
00226 #define __HAL_DBGMCU_FREEZE_TIM11()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
00227 #define __HAL_DBGMCU_UNFREEZE_TIM11()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
00228 #endif
00229
00230
00231 #if defined (DBGMCU_CR_DBG_TIM15_STOP)
00232 /**
00233   * @brief  TIM15 Peripherals Debug mode
00234   */
00235 #define __HAL_DBGMCU_FREEZE_TIM15()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
00236 #define __HAL_DBGMCU_UNFREEZE_TIM15()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
00237 #endif
00238
00239 #if defined (DBGMCU_CR_DBG_TIM16_STOP)
00240 /**
00241   * @brief  TIM16 Peripherals Debug mode
00242   */
00243 #define __HAL_DBGMCU_FREEZE_TIM16()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
00244 #define __HAL_DBGMCU_UNFREEZE_TIM16()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
00245 #endif
00246
00247 #if defined (DBGMCU_CR_DBG_TIM17_STOP)
00248 /**
00249   * @brief  TIM17 Peripherals Debug mode
00250   */
00251 #define __HAL_DBGMCU_FREEZE_TIM17()            SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
00252 #define __HAL_DBGMCU_UNFREEZE_TIM17()          CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
00253 #endif
00254
00255 /**
00256   * @}
00257   */
00258
00259 /**
00260   * @}
00261   */
00262
00263 /* Exported functions --------------------------------------------------------*/
00264 /** @addtogroup HAL_Exported_Functions
00265   * @{
00266   */
00267 /** @addtogroup HAL_Exported_Functions_Group1
00268   * @{
00269   */
00270 /* Initialization and de-initialization functions  ******************************/
00271 HAL_StatusTypeDef HAL_Init(void);
00272 HAL_StatusTypeDef HAL_DeInit(void);
00273 void HAL_MspInit(void);
00274 void HAL_MspDeInit(void);
00275 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
00276 /**
00277   * @}
00278   */
00279
00280 /** @addtogroup HAL_Exported_Functions_Group2
00281   * @{
00282   */
00283 /* Peripheral Control functions  ************************************************/
00284 void HAL_IncTick(void);
00285 void HAL_Delay(__IO uint32_t Delay);
00286 uint32_t HAL_GetTick(void);
00287 void HAL_SuspendTick(void);
00288 void HAL_ResumeTick(void);
00289 uint32_t HAL_GetHalVersion(void);
00290 uint32_t HAL_GetREVID(void);
00291 uint32_t HAL_GetDEVID(void);
00292 void HAL_DBGMCU_EnableDBGSleepMode(void);
00293 void HAL_DBGMCU_DisableDBGSleepMode(void);
00294 void HAL_DBGMCU_EnableDBGStopMode(void);
00295 void HAL_DBGMCU_DisableDBGStopMode(void);
00296 void HAL_DBGMCU_EnableDBGStandbyMode(void);
00297 void HAL_DBGMCU_DisableDBGStandbyMode(void);
00298 void HAL_GetUID(uint32_t *UID);
00299 /**
00300   * @}
00301   */
00302
00303 /**
00304   * @}
00305   */
00306 /* Private types -------------------------------------------------------------*/
00307 /* Private variables ---------------------------------------------------------*/
00308 /** @defgroup HAL_Private_Variables HAL Private Variables
00309   * @{
00310   */
00311 /**
00312   * @}
00313   */
00314 /* Private constants ---------------------------------------------------------*/
00315 /** @defgroup HAL_Private_Constants HAL Private Constants
00316   * @{
00317   */
00318 /**
00319   * @}
00320   */
00321 /* Private macros ------------------------------------------------------------*/
00322 /* Private functions ---------------------------------------------------------*/
00323 /**
00324   * @}
00325   */
00326
00327 /**
00328   * @}
00329   */
00330
00331 #ifdef __cplusplus
00332 }
00333 #endif
00334
00335 #endif /* __STM32F1xx_HAL_H */
00336
00337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_adc.c Source File

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stm32f1xx_hal_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_adc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Analog to Digital Convertor (ADC)
00009   *          peripheral:
00010   *           + Initialization and de-initialization functions
00011   *             ++ Initialization and Configuration of ADC
00012   *           + Operation functions
00013   *             ++ Start, stop, get result of conversions of regular
00014   *                group, using 3 possible modes: polling, interruption or DMA.
00015   *           + Control functions
00016   *             ++ Channels configuration on regular group
00017   *             ++ Channels configuration on injected group
00018   *             ++ Analog Watchdog configuration
00019   *           + State functions
00020   *             ++ ADC state machine management
00021   *             ++ Interrupts and flags management
00022   *          Other functions (extended functions) are available in file
00023   *          "stm32f1xx_hal_adc_ex.c".
00024   *
00025   @verbatim
00026   ==============================================================================
00027                      ##### ADC peripheral features #####
00028   ==============================================================================
00029   [..]
00030   (+) 12-bit resolution
00031
00032   (+) Interrupt generation at the end of regular conversion, end of injected
00033       conversion, and in case of analog watchdog or overrun events.
00034
00035   (+) Single and continuous conversion modes.
00036
00037   (+) Scan mode for conversion of several channels sequentially.
00038
00039   (+) Data alignment with in-built data coherency.
00040
00041   (+) Programmable sampling time (channel wise)
00042
00043   (+) ADC conversion of regular group and injected group.
00044
00045   (+) External trigger (timer or EXTI)
00046       for both regular and injected groups.
00047
00048   (+) DMA request generation for transfer of conversions data of regular group.
00049
00050   (+) Multimode Dual mode (available on devices with 2 ADCs or more).
00051
00052   (+) Configurable DMA data storage in Multimode Dual mode (available on devices
00053       with 2 DCs or more).
00054
00055   (+) Configurable delay between conversions in Dual interleaved mode (available
00056       on devices with 2 DCs or more).
00057
00058   (+) ADC calibration
00059
00060   (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
00061       slower speed.
00062
00063   (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
00064       Vdda or to an external voltage reference).
00065
00066
00067                      ##### How to use this driver #####
00068   ==============================================================================
00069     [..]
00070
00071      *** Configuration of top level parameters related to ADC ***
00072      ============================================================
00073      [..]
00074
00075     (#) Enable the ADC interface
00076       (++) As prerequisite, ADC clock must be configured at RCC top level.
00077            Caution: On STM32F1, ADC clock frequency max is 14MHz (refer
00078                     to device datasheet).
00079                     Therefore, ADC clock prescaler must be configured in
00080                     function of ADC clock source frequency to remain below
00081                     this maximum frequency.
00082         (++) One clock setting is mandatory:
00083              ADC clock (core clock, also possibly conversion clock).
00084              (+++) Example:
00085                    Into HAL_ADC_MspInit() (recommended code location) or with
00086                    other device clock parameters configuration:
00087                (+++) RCC_PeriphCLKInitTypeDef  PeriphClkInit;
00088                (+++) __ADC1_CLK_ENABLE();
00089                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
00090                (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
00091                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
00092
00093     (#) ADC pins configuration
00094          (++) Enable the clock for the ADC GPIOs
00095               using macro __HAL_RCC_GPIOx_CLK_ENABLE()
00096          (++) Configure these ADC pins in analog mode
00097               using function HAL_GPIO_Init()
00098
00099     (#) Optionally, in case of usage of ADC with interruptions:
00100          (++) Configure the NVIC for ADC
00101               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00102          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00103               into the function of corresponding ADC interruption vector
00104               ADCx_IRQHandler().
00105
00106     (#) Optionally, in case of usage of DMA:
00107          (++) Configure the DMA (DMA channel, mode normal or circular, ...)
00108               using function HAL_DMA_Init().
00109          (++) Configure the NVIC for DMA
00110               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00111          (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
00112               into the function of corresponding DMA interruption vector
00113               DMAx_Channelx_IRQHandler().
00114
00115      *** Configuration of ADC, groups regular/injected, channels parameters ***
00116      ==========================================================================
00117      [..]
00118
00119     (#) Configure the ADC parameters (resolution, data alignment, ...)
00120         and regular group parameters (conversion trigger, sequencer, ...)
00121         using function HAL_ADC_Init().
00122
00123     (#) Configure the channels for regular group parameters (channel number,
00124         channel rank into sequencer, ..., into regular group)
00125         using function HAL_ADC_ConfigChannel().
00126
00127     (#) Optionally, configure the injected group parameters (conversion trigger,
00128         sequencer, ..., of injected group)
00129         and the channels for injected group parameters (channel number,
00130         channel rank into sequencer, ..., into injected group)
00131         using function HAL_ADCEx_InjectedConfigChannel().
00132
00133     (#) Optionally, configure the analog watchdog parameters (channels
00134         monitored, thresholds, ...)
00135         using function HAL_ADC_AnalogWDGConfig().
00136
00137     (#) Optionally, for devices with several ADC instances: configure the
00138         multimode parameters
00139         using function HAL_ADCEx_MultiModeConfigChannel().
00140
00141      *** Execution of ADC conversions ***
00142      ====================================
00143      [..]
00144
00145     (#) Optionally, perform an automatic ADC calibration to improve the
00146         conversion accuracy
00147         using function HAL_ADCEx_Calibration_Start().
00148
00149     (#) ADC driver can be used among three modes: polling, interruption,
00150         transfer by DMA.
00151
00152         (++) ADC conversion by polling:
00153           (+++) Activate the ADC peripheral and start conversions
00154                 using function HAL_ADC_Start()
00155           (+++) Wait for ADC conversion completion
00156                 using function HAL_ADC_PollForConversion()
00157                 (or for injected group: HAL_ADCEx_InjectedPollForConversion() )
00158           (+++) Retrieve conversion results
00159                 using function HAL_ADC_GetValue()
00160                 (or for injected group: HAL_ADCEx_InjectedGetValue() )
00161           (+++) Stop conversion and disable the ADC peripheral
00162                 using function HAL_ADC_Stop()
00163
00164         (++) ADC conversion by interruption:
00165           (+++) Activate the ADC peripheral and start conversions
00166                 using function HAL_ADC_Start_IT()
00167           (+++) Wait for ADC conversion completion by call of function
00168                 HAL_ADC_ConvCpltCallback()
00169                 (this function must be implemented in user program)
00170                 (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() )
00171           (+++) Retrieve conversion results
00172                 using function HAL_ADC_GetValue()
00173                 (or for injected group: HAL_ADCEx_InjectedGetValue() )
00174           (+++) Stop conversion and disable the ADC peripheral
00175                 using function HAL_ADC_Stop_IT()
00176
00177         (++) ADC conversion with transfer by DMA:
00178           (+++) Activate the ADC peripheral and start conversions
00179                 using function HAL_ADC_Start_DMA()
00180           (+++) Wait for ADC conversion completion by call of function
00181                 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
00182                 (these functions must be implemented in user program)
00183           (+++) Conversion results are automatically transferred by DMA into
00184                 destination variable address.
00185           (+++) Stop conversion and disable the ADC peripheral
00186                 using function HAL_ADC_Stop_DMA()
00187
00188         (++) For devices with several ADCs: ADC multimode conversion
00189              with transfer by DMA:
00190           (+++) Activate the ADC peripheral (slave) and start conversions
00191                 using function HAL_ADC_Start()
00192           (+++) Activate the ADC peripheral (master) and start conversions
00193                 using function HAL_ADCEx_MultiModeStart_DMA()
00194           (+++) Wait for ADC conversion completion by call of function
00195                 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
00196                 (these functions must be implemented in user program)
00197           (+++) Conversion results are automatically transferred by DMA into
00198                 destination variable address.
00199           (+++) Stop conversion and disable the ADC peripheral (master)
00200                 using function HAL_ADCEx_MultiModeStop_DMA()
00201           (+++) Stop conversion and disable the ADC peripheral (slave)
00202                 using function HAL_ADC_Stop_IT()
00203
00204      [..]
00205
00206     (@) Callback functions must be implemented in user program:
00207       (+@) HAL_ADC_ErrorCallback()
00208       (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
00209       (+@) HAL_ADC_ConvCpltCallback()
00210       (+@) HAL_ADC_ConvHalfCpltCallback
00211       (+@) HAL_ADCEx_InjectedConvCpltCallback()
00212
00213      *** Deinitialization of ADC ***
00214      ============================================================
00215      [..]
00216
00217     (#) Disable the ADC interface
00218       (++) ADC clock can be hard reset and disabled at RCC top level.
00219         (++) Hard reset of ADC peripherals
00220              using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
00221         (++) ADC clock disable
00222              using the equivalent macro/functions as configuration step.
00223              (+++) Example:
00224                    Into HAL_ADC_MspDeInit() (recommended code location) or with
00225                    other device clock parameters configuration:
00226                (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
00227                (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF
00228                (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)
00229
00230     (#) ADC pins configuration
00231          (++) Disable the clock for the ADC GPIOs
00232               using macro __HAL_RCC_GPIOx_CLK_DISABLE()
00233
00234     (#) Optionally, in case of usage of ADC with interruptions:
00235          (++) Disable the NVIC for ADC
00236               using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
00237
00238     (#) Optionally, in case of usage of DMA:
00239          (++) Deinitialize the DMA
00240               using function HAL_DMA_Init().
00241          (++) Disable the NVIC for DMA
00242               using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
00243
00244     [..]
00245
00246     @endverbatim
00247   ******************************************************************************
00248   * @attention
00249   *
00250   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00251   *
00252   * Redistribution and use in source and binary forms, with or without modification,
00253   * are permitted provided that the following conditions are met:
00254   *   1. Redistributions of source code must retain the above copyright notice,
00255   *      this list of conditions and the following disclaimer.
00256   *   2. Redistributions in binary form must reproduce the above copyright notice,
00257   *      this list of conditions and the following disclaimer in the documentation
00258   *      and/or other materials provided with the distribution.
00259   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00260   *      may be used to endorse or promote products derived from this software
00261   *      without specific prior written permission.
00262   *
00263   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00264   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00265   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00266   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00267   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00268   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00269   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00270   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00271   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00272   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00273   *
00274   ******************************************************************************
00275   */
00276
00277 /* Includes ------------------------------------------------------------------*/
00278 #include "stm32f1xx_hal.h"
00279
00280 /** @addtogroup STM32F1xx_HAL_Driver
00281   * @{
00282   */
00283
00284 /** @defgroup ADC ADC
00285   * @brief ADC HAL module driver
00286   * @{
00287   */
00288
00289 #ifdef HAL_ADC_MODULE_ENABLED
00290
00291 /* Private typedef -----------------------------------------------------------*/
00292 /* Private define ------------------------------------------------------------*/
00293 /** @defgroup ADC_Private_Constants ADC Private Constants
00294   * @{
00295   */
00296
00297   /* Timeout values for ADC enable and disable settling time.                 */
00298   /* Values defined to be higher than worst cases: low clocks freq,           */
00299   /* maximum prescaler.                                                       */
00300   /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
00301   /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits.    */
00302   /* Unit: ms                                                                 */
00303   #define ADC_ENABLE_TIMEOUT              2U
00304   #define ADC_DISABLE_TIMEOUT             2U
00305
00306   /* Delay for ADC stabilization time.                                        */
00307   /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
00308   /* Unit: us                                                                 */
00309   #define ADC_STAB_DELAY_US               1U
00310
00311   /* Delay for temperature sensor stabilization time.                         */
00312   /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
00313   /* Unit: us                                                                 */
00314   #define ADC_TEMPSENSOR_DELAY_US         10U
00315
00316 /**
00317   * @}
00318   */
00319
00320 /* Private macro -------------------------------------------------------------*/
00321 /* Private variables ---------------------------------------------------------*/
00322 /* Private function prototypes -----------------------------------------------*/
00323 /** @defgroup ADC_Private_Functions ADC Private Functions
00324   * @{
00325   */
00326 /**
00327   * @}
00328   */
00329
00330 /* Exported functions --------------------------------------------------------*/
00331
00332 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00333   * @{
00334   */
00335
00336 /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions
00337   * @brief    Initialization and Configuration functions
00338   *
00339 @verbatim
00340  ===============================================================================
00341               ##### Initialization and de-initialization functions #####
00342  ===============================================================================
00343     [..]  This section provides functions allowing to:
00344       (+) Initialize and configure the ADC.
00345       (+) De-initialize the ADC.
00346
00347 @endverbatim
00348   * @{
00349   */
00350
00351 /**
00352   * @brief  Initializes the ADC peripheral and regular group according to
00353   *         parameters specified in structure "ADC_InitTypeDef".
00354   * @note   As prerequisite, ADC clock must be configured at RCC top level
00355   *         (clock source APB2).
00356   *         See commented example code below that can be copied and uncommented
00357   *         into HAL_ADC_MspInit().
00358   * @note   Possibility to update parameters on the fly:
00359   *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00360   *         coming from ADC state reset. Following calls to this function can
00361   *         be used to reconfigure some parameters of ADC_InitTypeDef
00362   *         structure on the fly, without modifying MSP configuration. If ADC
00363   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00364   *         before HAL_ADC_Init().
00365   *         The setting of these parameters is conditioned to ADC state.
00366   *         For parameters constraints, see comments of structure
00367   *         "ADC_InitTypeDef".
00368   * @note   This function configures the ADC within 2 scopes: scope of entire
00369   *         ADC and scope of regular group. For parameters details, see comments
00370   *         of structure "ADC_InitTypeDef".
00371   * @param  hadc: ADC handle
00372   * @retval HAL status
00373   */
00374 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
00375 {
00376   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00377   uint32_t tmp_cr1 = 0U;
00378   uint32_t tmp_cr2 = 0U;
00379   uint32_t tmp_sqr1 = 0U;
00380
00381   /* Check ADC handle */
00382   if(hadc == NULL)
00383   {
00384     return HAL_ERROR;
00385   }
00386
00387   /* Check the parameters */
00388   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00389   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
00390   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
00391   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00392   assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
00393
00394   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
00395   {
00396     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
00397     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00398     if(hadc->Init.DiscontinuousConvMode != DISABLE)
00399     {
00400       assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
00401     }
00402   }
00403
00404   /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured    */
00405   /* at RCC top level.                                                        */
00406   /* Refer to header of this file for more details on clock enabling          */
00407   /* procedure.                                                               */
00408
00409   /* Actions performed only if ADC is coming from state reset:                */
00410   /* - Initialization of ADC MSP                                              */
00411   if (hadc->State == HAL_ADC_STATE_RESET)
00412   {
00413     /* Initialize ADC error code */
00414     ADC_CLEAR_ERRORCODE(hadc);
00415
00416     /* Allocate lock resource and initialize it */
00417     hadc->Lock = HAL_UNLOCKED;
00418
00419     /* Init the low level hardware */
00420     HAL_ADC_MspInit(hadc);
00421   }
00422
00423   /* Stop potential conversion on going, on regular and injected groups */
00424   /* Disable ADC peripheral */
00425   /* Note: In case of ADC already enabled, precaution to not launch an        */
00426   /*       unwanted conversion while modifying register CR2 by writing 1 to   */
00427   /*       bit ADON.                                                          */
00428   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
00429
00430
00431   /* Configuration of ADC parameters if previous preliminary actions are      */
00432   /* correctly completed.                                                     */
00433   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
00434       (tmp_hal_status == HAL_OK)                                  )
00435   {
00436     /* Set ADC state */
00437     ADC_STATE_CLR_SET(hadc->State,
00438                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00439                       HAL_ADC_STATE_BUSY_INTERNAL);
00440
00441     /* Set ADC parameters */
00442
00443     /* Configuration of ADC:                                                  */
00444     /*  - data alignment                                                      */
00445     /*  - external trigger to start conversion                                */
00446     /*  - external trigger polarity (always set to 1, because needed for all  */
00447     /*    triggers: external trigger of SW start)                             */
00448     /*  - continuous conversion mode                                          */
00449     /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into          */
00450     /*       HAL_ADC_Start_xxx functions because if set in this function,     */
00451     /*       a conversion on injected group would start a conversion also on  */
00452     /*       regular group after ADC enabling.                                */
00453     tmp_cr2 |= (hadc->Init.DataAlign                               |
00454                 ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
00455                 ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode)   );
00456
00457     /* Configuration of ADC:                                                  */
00458     /*  - scan mode                                                           */
00459     /*  - discontinuous mode disable/enable                                   */
00460     /*  - discontinuous mode number of conversions                            */
00461     tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode));
00462
00463     /* Enable discontinuous mode only if continuous mode is disabled */
00464     /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter    */
00465     /*       discontinuous is set anyway, but will have no effect on ADC HW.  */
00466     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00467     {
00468       if (hadc->Init.ContinuousConvMode == DISABLE)
00469       {
00470         /* Enable the selected ADC regular discontinuous mode */
00471         /* Set the number of channels to be converted in discontinuous mode */
00472         SET_BIT(tmp_cr1, ADC_CR1_DISCEN                                            |
00473                          ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion)  );
00474       }
00475       else
00476       {
00477         /* ADC regular group settings continuous and sequencer discontinuous*/
00478         /* cannot be enabled simultaneously.                                */
00479
00480         /* Update ADC state machine to error */
00481         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00482
00483         /* Set ADC error code to ADC IP internal error */
00484         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00485       }
00486     }
00487
00488     /* Update ADC configuration register CR1 with previous settings */
00489       MODIFY_REG(hadc->Instance->CR1,
00490                  ADC_CR1_SCAN    |
00491                  ADC_CR1_DISCEN  |
00492                  ADC_CR1_DISCNUM    ,
00493                  tmp_cr1             );
00494
00495     /* Update ADC configuration register CR2 with previous settings */
00496       MODIFY_REG(hadc->Instance->CR2,
00497                  ADC_CR2_ALIGN   |
00498                  ADC_CR2_EXTSEL  |
00499                  ADC_CR2_EXTTRIG |
00500                  ADC_CR2_CONT       ,
00501                  tmp_cr2             );
00502
00503     /* Configuration of regular group sequencer:                              */
00504     /* - if scan mode is disabled, regular channels sequence length is set to */
00505     /*   0x00: 1 channel converted (channel on regular rank 1)                */
00506     /*   Parameter "NbrOfConversion" is discarded.                            */
00507     /*   Note: Scan mode is present by hardware on this device and, if        */
00508     /*   disabled, discards automatically nb of conversions. Anyway, nb of    */
00509     /*   conversions is forced to 0x00 for alignment over all STM32 devices.  */
00510     /* - if scan mode is enabled, regular channels sequence length is set to  */
00511     /*   parameter "NbrOfConversion"                                          */
00512     if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
00513     {
00514       tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion);
00515     }
00516
00517     MODIFY_REG(hadc->Instance->SQR1,
00518                ADC_SQR1_L          ,
00519                tmp_sqr1             );
00520
00521     /* Check back that ADC registers have effectively been configured to      */
00522     /* ensure of no potential problem of ADC core IP clocking.                */
00523     /* Check through register CR2 (excluding bits set in other functions:     */
00524     /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits   */
00525     /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal    */
00526     /* measurement path bit (TSVREFE).                                        */
00527     if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA |
00528                                         ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
00529                                         ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL |
00530                                         ADC_CR2_TSVREFE                     ))
00531          == tmp_cr2)
00532     {
00533       /* Set ADC error code to none */
00534       ADC_CLEAR_ERRORCODE(hadc);
00535
00536       /* Set the ADC state */
00537       ADC_STATE_CLR_SET(hadc->State,
00538                         HAL_ADC_STATE_BUSY_INTERNAL,
00539                         HAL_ADC_STATE_READY);
00540     }
00541     else
00542     {
00543       /* Update ADC state machine to error */
00544       ADC_STATE_CLR_SET(hadc->State,
00545                         HAL_ADC_STATE_BUSY_INTERNAL,
00546                         HAL_ADC_STATE_ERROR_INTERNAL);
00547
00548       /* Set ADC error code to ADC IP internal error */
00549       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00550
00551       tmp_hal_status = HAL_ERROR;
00552     }
00553
00554   }
00555   else
00556   {
00557     /* Update ADC state machine to error */
00558     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00559
00560     tmp_hal_status = HAL_ERROR;
00561   }
00562
00563   /* Return function status */
00564   return tmp_hal_status;
00565 }
00566
00567 /**
00568   * @brief  Deinitialize the ADC peripheral registers to their default reset
00569   *         values, with deinitialization of the ADC MSP.
00570   *         If needed, the example code can be copied and uncommented into
00571   *         function HAL_ADC_MspDeInit().
00572   * @param  hadc: ADC handle
00573   * @retval HAL status
00574   */
00575 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
00576 {
00577   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00578
00579   /* Check ADC handle */
00580   if(hadc == NULL)
00581   {
00582      return HAL_ERROR;
00583   }
00584
00585   /* Check the parameters */
00586   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00587
00588   /* Set ADC state */
00589   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00590
00591   /* Stop potential conversion on going, on regular and injected groups */
00592   /* Disable ADC peripheral */
00593   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
00594
00595
00596   /* Configuration of ADC parameters if previous preliminary actions are      */
00597   /* correctly completed.                                                     */
00598   if (tmp_hal_status == HAL_OK)
00599   {
00600     /* ========== Reset ADC registers ========== */
00601
00602
00603
00604
00605     /* Reset register SR */
00606     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
00607                                 ADC_FLAG_JSTRT | ADC_FLAG_STRT));
00608
00609     /* Reset register CR1 */
00610     CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN   | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
00611                                     ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO   |
00612                                     ADC_CR1_AWDSGL  | ADC_CR1_SCAN   | ADC_CR1_JEOCIE  |
00613                                     ADC_CR1_AWDIE   | ADC_CR1_EOCIE  | ADC_CR1_AWDCH    ));
00614
00615     /* Reset register CR2 */
00616     CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
00617                                     ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL  | ADC_CR2_JEXTTRIG |
00618                                     ADC_CR2_JEXTSEL | ADC_CR2_ALIGN   | ADC_CR2_DMA      |
00619                                     ADC_CR2_RSTCAL  | ADC_CR2_CAL     | ADC_CR2_CONT     |
00620                                     ADC_CR2_ADON                                          ));
00621
00622     /* Reset register SMPR1 */
00623     CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 |
00624                                       ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 |
00625                                       ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10                    ));
00626
00627     /* Reset register SMPR2 */
00628     CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
00629                                       ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
00630                                       ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
00631                                       ADC_SMPR2_SMP0                                    ));
00632
00633     /* Reset register JOFR1 */
00634     CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
00635     /* Reset register JOFR2 */
00636     CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
00637     /* Reset register JOFR3 */
00638     CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
00639     /* Reset register JOFR4 */
00640     CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
00641
00642     /* Reset register HTR */
00643     CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
00644     /* Reset register LTR */
00645     CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
00646
00647     /* Reset register SQR1 */
00648     CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L    |
00649                                     ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
00650                                     ADC_SQR1_SQ14 | ADC_SQR1_SQ13  );
00651
00652     /* Reset register SQR1 */
00653     CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L    |
00654                                     ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
00655                                     ADC_SQR1_SQ14 | ADC_SQR1_SQ13  );
00656
00657     /* Reset register SQR2 */
00658     CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
00659                                     ADC_SQR2_SQ9  | ADC_SQR2_SQ8  | ADC_SQR2_SQ7   );
00660
00661     /* Reset register SQR3 */
00662     CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
00663                                     ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1  );
00664
00665     /* Reset register JSQR */
00666     CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
00667                                     ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
00668                                     ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  );
00669
00670     /* Reset register JSQR */
00671     CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL |
00672                                     ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
00673                                     ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  );
00674
00675     /* Reset register DR */
00676     /* bits in access mode read only, no direct reset applicable*/
00677
00678     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00679     /* bits in access mode read only, no direct reset applicable*/
00680
00681     /* ========== Hard reset ADC peripheral ========== */
00682     /* Performs a global reset of the entire ADC peripheral: ADC state is     */
00683     /* forced to a similar state after device power-on.                       */
00684     /* If needed, copy-paste and uncomment the following reset code into      */
00685     /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)":              */
00686     /*                                                                        */
00687     /*  __HAL_RCC_ADC1_FORCE_RESET()                                          */
00688     /*  __HAL_RCC_ADC1_RELEASE_RESET()                                        */
00689
00690     /* DeInit the low level hardware */
00691     HAL_ADC_MspDeInit(hadc);
00692
00693     /* Set ADC error code to none */
00694     ADC_CLEAR_ERRORCODE(hadc);
00695
00696     /* Set ADC state */
00697     hadc->State = HAL_ADC_STATE_RESET;
00698
00699   }
00700
00701   /* Process unlocked */
00702   __HAL_UNLOCK(hadc);
00703
00704   /* Return function status */
00705   return tmp_hal_status;
00706 }
00707
00708 /**
00709   * @brief  Initializes the ADC MSP.
00710   * @param  hadc: ADC handle
00711   * @retval None
00712   */
00713 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
00714 {
00715   /* Prevent unused argument(s) compilation warning */
00716   UNUSED(hadc);
00717   /* NOTE : This function should not be modified. When the callback is needed,
00718             function HAL_ADC_MspInit must be implemented in the user file.
00719    */
00720 }
00721
00722 /**
00723   * @brief  DeInitializes the ADC MSP.
00724   * @param  hadc: ADC handle
00725   * @retval None
00726   */
00727 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
00728 {
00729   /* Prevent unused argument(s) compilation warning */
00730   UNUSED(hadc);
00731   /* NOTE : This function should not be modified. When the callback is needed,
00732             function HAL_ADC_MspDeInit must be implemented in the user file.
00733    */
00734 }
00735
00736 /**
00737   * @}
00738   */
00739
00740 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions
00741  *  @brief    Input and Output operation functions
00742  *
00743 @verbatim
00744  ===============================================================================
00745                       ##### IO operation functions #####
00746  ===============================================================================
00747     [..]  This section provides functions allowing to:
00748       (+) Start conversion of regular group.
00749       (+) Stop conversion of regular group.
00750       (+) Poll for conversion complete on regular group.
00751       (+) Poll for conversion event.
00752       (+) Get result of regular channel conversion.
00753       (+) Start conversion of regular group and enable interruptions.
00754       (+) Stop conversion of regular group and disable interruptions.
00755       (+) Handle ADC interrupt request
00756       (+) Start conversion of regular group and enable DMA transfer.
00757       (+) Stop conversion of regular group and disable ADC DMA transfer.
00758 @endverbatim
00759   * @{
00760   */
00761
00762 /**
00763   * @brief  Enables ADC, starts conversion of regular group.
00764   *         Interruptions enabled in this function: None.
00765   * @param  hadc: ADC handle
00766   * @retval HAL status
00767   */
00768 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
00769 {
00770   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00771
00772   /* Check the parameters */
00773   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00774
00775   /* Process locked */
00776   __HAL_LOCK(hadc);
00777
00778   /* Enable the ADC peripheral */
00779   tmp_hal_status = ADC_Enable(hadc);
00780
00781   /* Start conversion if ADC is effectively enabled */
00782   if (tmp_hal_status == HAL_OK)
00783   {
00784     /* Set ADC state                                                          */
00785     /* - Clear state bitfield related to regular group conversion results     */
00786     /* - Set state bitfield related to regular operation                      */
00787     ADC_STATE_CLR_SET(hadc->State,
00788                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC,
00789                       HAL_ADC_STATE_REG_BUSY);
00790
00791     /* Set group injected state (from auto-injection) and multimode state     */
00792     /* for all cases of multimode: independent mode, multimode ADC master     */
00793     /* or multimode ADC slave (for devices with several ADCs):                */
00794     if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00795     {
00796       /* Set ADC state (ADC independent or master) */
00797       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00798
00799       /* If conversions on group regular are also triggering group injected,  */
00800       /* update ADC state.                                                    */
00801       if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
00802       {
00803         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00804       }
00805     }
00806     else
00807     {
00808       /* Set ADC state (ADC slave) */
00809       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00810
00811       /* If conversions on group regular are also triggering group injected,  */
00812       /* update ADC state.                                                    */
00813       if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
00814       {
00815         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00816       }
00817     }
00818
00819     /* State machine update: Check if an injected conversion is ongoing */
00820     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00821     {
00822       /* Reset ADC error code fields related to conversions on group regular */
00823       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
00824     }
00825     else
00826     {
00827       /* Reset ADC all error code fields */
00828       ADC_CLEAR_ERRORCODE(hadc);
00829     }
00830
00831     /* Process unlocked */
00832     /* Unlock before starting ADC conversions: in case of potential           */
00833     /* interruption, to let the process to ADC IRQ Handler.                   */
00834     __HAL_UNLOCK(hadc);
00835
00836     /* Clear regular group conversion flag */
00837     /* (To ensure of no unknown state from potential previous ADC operations) */
00838     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00839
00840     /* Enable conversion of regular group.                                    */
00841     /* If software start has been selected, conversion starts immediately.    */
00842     /* If external trigger has been selected, conversion will start at next   */
00843     /* trigger event.                                                         */
00844     /* Case of multimode enabled:                                             */
00845     /*  - if ADC is slave, ADC is enabled only (conversion is not started).   */
00846     /*  - if ADC is master, ADC is enabled and conversion is started.         */
00847     /* If ADC is master, ADC is enabled and conversion is started.            */
00848     /* Note: Alternate trigger for single conversion could be to force an     */
00849     /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
00850     if (ADC_IS_SOFTWARE_START_REGULAR(hadc)      &&
00851         ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
00852     {
00853       /* Start ADC conversion on regular group with SW start */
00854       SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
00855     }
00856     else
00857     {
00858       /* Start ADC conversion on regular group with external trigger */
00859       SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
00860     }
00861   }
00862   else
00863   {
00864     /* Process unlocked */
00865     __HAL_UNLOCK(hadc);
00866   }
00867
00868   /* Return function status */
00869   return tmp_hal_status;
00870 }
00871
00872 /**
00873   * @brief  Stop ADC conversion of regular group (and injected channels in
00874   *         case of auto_injection mode), disable ADC peripheral.
00875   * @note:  ADC peripheral disable is forcing stop of potential
00876   *         conversion on injected group. If injected group is under use, it
00877   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
00878   * @param  hadc: ADC handle
00879   * @retval HAL status.
00880   */
00881 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
00882 {
00883   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00884
00885   /* Check the parameters */
00886   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00887
00888   /* Process locked */
00889   __HAL_LOCK(hadc);
00890
00891   /* Stop potential conversion on going, on regular and injected groups */
00892   /* Disable ADC peripheral */
00893   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
00894
00895   /* Check if ADC is effectively disabled */
00896   if (tmp_hal_status == HAL_OK)
00897   {
00898     /* Set ADC state */
00899     ADC_STATE_CLR_SET(hadc->State,
00900                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00901                       HAL_ADC_STATE_READY);
00902   }
00903
00904   /* Process unlocked */
00905   __HAL_UNLOCK(hadc);
00906
00907   /* Return function status */
00908   return tmp_hal_status;
00909 }
00910
00911 /**
00912   * @brief  Wait for regular group conversion to be completed.
00913   * @note   This function cannot be used in a particular setup: ADC configured
00914   *         in DMA mode.
00915   *         In this case, DMA resets the flag EOC and polling cannot be
00916   *         performed on each conversion.
00917   * @note   On STM32F1 devices, limitation in case of sequencer enabled
00918   *         (several ranks selected): polling cannot be done on each
00919   *         conversion inside the sequence. In this case, polling is replaced by
00920   *         wait for maximum conversion time.
00921   * @param  hadc: ADC handle
00922   * @param  Timeout: Timeout value in millisecond.
00923   * @retval HAL status
00924   */
00925 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00926 {
00927   uint32_t tickstart = 0U;
00928
00929   /* Variables for polling in case of scan mode enabled and polling for each  */
00930   /* conversion.                                                              */
00931   __IO uint32_t Conversion_Timeout_CPU_cycles = 0U;
00932   uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
00933
00934   /* Check the parameters */
00935   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00936
00937   /* Get tick count */
00938   tickstart = HAL_GetTick();
00939
00940   /* Verification that ADC configuration is compliant with polling for        */
00941   /* each conversion:                                                         */
00942   /* Particular case is ADC configured in DMA mode                            */
00943   if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA))
00944   {
00945     /* Update ADC state machine to error */
00946     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00947
00948     /* Process unlocked */
00949     __HAL_UNLOCK(hadc);
00950
00951     return HAL_ERROR;
00952   }
00953
00954   /* Polling for end of conversion: differentiation if single/sequence        */
00955   /* conversion.                                                              */
00956   /*  - If single conversion for regular group (Scan mode disabled or enabled */
00957   /*    with NbrOfConversion =1), flag EOC is used to determine the           */
00958   /*    conversion completion.                                                */
00959   /*  - If sequence conversion for regular group (scan mode enabled and       */
00960   /*    NbrOfConversion >=2), flag EOC is set only at the end of the          */
00961   /*    sequence.                                                             */
00962   /*    To poll for each conversion, the maximum conversion time is computed  */
00963   /*    from ADC conversion time (selected sampling time + conversion time of */
00964   /*    12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on    */
00965   /*    settings, conversion time range can be from 28 to 32256 CPU cycles).  */
00966   /*    As flag EOC is not set after each conversion, no timeout status can   */
00967   /*    be set.                                                               */
00968   if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) &&
00969       HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L)    )
00970   {
00971     /* Wait until End of Conversion flag is raised */
00972     while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
00973     {
00974       /* Check if timeout is disabled (set to infinite wait) */
00975       if(Timeout != HAL_MAX_DELAY)
00976       {
00977         if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
00978         {
00979           /* Update ADC state machine to timeout */
00980           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00981
00982           /* Process unlocked */
00983           __HAL_UNLOCK(hadc);
00984
00985           return HAL_TIMEOUT;
00986         }
00987       }
00988     }
00989   }
00990   else
00991   {
00992     /* Replace polling by wait for maximum conversion time */
00993     /*  - Computation of CPU clock cycles corresponding to ADC clock cycles   */
00994     /*    and ADC maximum conversion cycles on all channels.                  */
00995     /*  - Wait for the expected ADC clock cycles delay                        */
00996     Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
00997                                           / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
00998                                          * ADC_CONVCYCLES_MAX_RANGE(hadc)                 );
00999
01000     while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
01001     {
01002       /* Check if timeout is disabled (set to infinite wait) */
01003       if(Timeout != HAL_MAX_DELAY)
01004       {
01005         if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
01006         {
01007           /* Update ADC state machine to timeout */
01008           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01009
01010           /* Process unlocked */
01011           __HAL_UNLOCK(hadc);
01012
01013           return HAL_TIMEOUT;
01014         }
01015       }
01016       Conversion_Timeout_CPU_cycles ++;
01017     }
01018   }
01019
01020   /* Clear regular group conversion flag */
01021   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
01022
01023   /* Update ADC state machine */
01024   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01025
01026   /* Determine whether any further conversion upcoming on group regular       */
01027   /* by external trigger, continuous mode or scan sequence on going.          */
01028   /* Note: On STM32F1 devices, in case of sequencer enabled                   */
01029   /*       (several ranks selected), end of conversion flag is raised         */
01030   /*       at the end of the sequence.                                        */
01031   if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
01032      (hadc->Init.ContinuousConvMode == DISABLE)   )
01033   {
01034     /* Set ADC state */
01035     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01036
01037     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01038     {
01039       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01040     }
01041   }
01042
01043   /* Return ADC state */
01044   return HAL_OK;
01045 }
01046
01047 /**
01048   * @brief  Poll for conversion event.
01049   * @param  hadc: ADC handle
01050   * @param  EventType: the ADC event type.
01051   *          This parameter can be one of the following values:
01052   *            @arg ADC_AWD_EVENT: ADC Analog watchdog event.
01053   * @param  Timeout: Timeout value in millisecond.
01054   * @retval HAL status
01055   */
01056 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
01057 {
01058   uint32_t tickstart = 0U;
01059
01060   /* Check the parameters */
01061   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01062   assert_param(IS_ADC_EVENT_TYPE(EventType));
01063
01064   /* Get tick count */
01065   tickstart = HAL_GetTick();
01066
01067   /* Check selected event flag */
01068   while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
01069   {
01070     /* Check if timeout is disabled (set to infinite wait) */
01071     if(Timeout != HAL_MAX_DELAY)
01072     {
01073       if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
01074       {
01075         /* Update ADC state machine to timeout */
01076         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01077
01078         /* Process unlocked */
01079         __HAL_UNLOCK(hadc);
01080
01081         return HAL_TIMEOUT;
01082       }
01083     }
01084   }
01085
01086   /* Analog watchdog (level out of window) event */
01087   /* Set ADC state */
01088   SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01089
01090   /* Clear ADC analog watchdog flag */
01091   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
01092
01093   /* Return ADC state */
01094   return HAL_OK;
01095 }
01096
01097 /**
01098   * @brief  Enables ADC, starts conversion of regular group with interruption.
01099   *         Interruptions enabled in this function:
01100   *          - EOC (end of conversion of regular group)
01101   *         Each of these interruptions has its dedicated callback function.
01102   * @param  hadc: ADC handle
01103   * @retval HAL status
01104   */
01105 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
01106 {
01107   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01108
01109   /* Check the parameters */
01110   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01111
01112   /* Process locked */
01113   __HAL_LOCK(hadc);
01114
01115   /* Enable the ADC peripheral */
01116   tmp_hal_status = ADC_Enable(hadc);
01117
01118   /* Start conversion if ADC is effectively enabled */
01119   if (tmp_hal_status == HAL_OK)
01120   {
01121     /* Set ADC state                                                          */
01122     /* - Clear state bitfield related to regular group conversion results     */
01123     /* - Set state bitfield related to regular operation                      */
01124     ADC_STATE_CLR_SET(hadc->State,
01125                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01126                       HAL_ADC_STATE_REG_BUSY);
01127
01128     /* Set group injected state (from auto-injection) and multimode state     */
01129     /* for all cases of multimode: independent mode, multimode ADC master     */
01130     /* or multimode ADC slave (for devices with several ADCs):                */
01131     if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
01132     {
01133       /* Set ADC state (ADC independent or master) */
01134       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01135
01136       /* If conversions on group regular are also triggering group injected,  */
01137       /* update ADC state.                                                    */
01138       if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
01139       {
01140         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01141       }
01142     }
01143     else
01144     {
01145       /* Set ADC state (ADC slave) */
01146       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01147
01148       /* If conversions on group regular are also triggering group injected,  */
01149       /* update ADC state.                                                    */
01150       if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
01151       {
01152         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01153       }
01154     }
01155
01156     /* State machine update: Check if an injected conversion is ongoing */
01157     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01158     {
01159       /* Reset ADC error code fields related to conversions on group regular */
01160       CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01161     }
01162     else
01163     {
01164       /* Reset ADC all error code fields */
01165       ADC_CLEAR_ERRORCODE(hadc);
01166     }
01167
01168     /* Process unlocked */
01169     /* Unlock before starting ADC conversions: in case of potential           */
01170     /* interruption, to let the process to ADC IRQ Handler.                   */
01171     __HAL_UNLOCK(hadc);
01172
01173     /* Clear regular group conversion flag and overrun flag */
01174     /* (To ensure of no unknown state from potential previous ADC operations) */
01175     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
01176
01177     /* Enable end of conversion interrupt for regular group */
01178     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
01179
01180     /* Enable conversion of regular group.                                    */
01181     /* If software start has been selected, conversion starts immediately.    */
01182     /* If external trigger has been selected, conversion will start at next   */
01183     /* trigger event.                                                         */
01184     /* Case of multimode enabled:                                             */
01185     /*  - if ADC is slave, ADC is enabled only (conversion is not started).   */
01186     /*  - if ADC is master, ADC is enabled and conversion is started.         */
01187     if (ADC_IS_SOFTWARE_START_REGULAR(hadc)      &&
01188         ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
01189     {
01190       /* Start ADC conversion on regular group with SW start */
01191       SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
01192     }
01193     else
01194     {
01195       /* Start ADC conversion on regular group with external trigger */
01196       SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
01197     }
01198   }
01199   else
01200   {
01201     /* Process unlocked */
01202     __HAL_UNLOCK(hadc);
01203   }
01204
01205   /* Return function status */
01206   return tmp_hal_status;
01207 }
01208
01209 /**
01210   * @brief  Stop ADC conversion of regular group (and injected group in
01211   *         case of auto_injection mode), disable interrution of
01212   *         end-of-conversion, disable ADC peripheral.
01213   * @param  hadc: ADC handle
01214   * @retval None
01215   */
01216 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
01217 {
01218   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01219
01220   /* Check the parameters */
01221   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01222
01223   /* Process locked */
01224   __HAL_LOCK(hadc);
01225
01226   /* Stop potential conversion on going, on regular and injected groups */
01227   /* Disable ADC peripheral */
01228   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
01229
01230   /* Check if ADC is effectively disabled */
01231   if (tmp_hal_status == HAL_OK)
01232   {
01233     /* Disable ADC end of conversion interrupt for regular group */
01234     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
01235
01236     /* Set ADC state */
01237     ADC_STATE_CLR_SET(hadc->State,
01238                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01239                       HAL_ADC_STATE_READY);
01240   }
01241
01242   /* Process unlocked */
01243   __HAL_UNLOCK(hadc);
01244
01245   /* Return function status */
01246   return tmp_hal_status;
01247 }
01248
01249 /**
01250   * @brief  Enables ADC, starts conversion of regular group and transfers result
01251   *         through DMA.
01252   *         Interruptions enabled in this function:
01253   *          - DMA transfer complete
01254   *          - DMA half transfer
01255   *         Each of these interruptions has its dedicated callback function.
01256   * @note   For devices with several ADCs: This function is for single-ADC mode
01257   *         only. For multimode, use the dedicated MultimodeStart function.
01258   * @note   On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
01259   *         on devices) have DMA capability.
01260   *         ADC2 converted data can be transferred in dual ADC mode using DMA
01261   *         of ADC1 (ADC master in multimode).
01262   *         In case of using ADC1 with DMA on a device featuring 2 ADC
01263   *         instances: ADC1 conversion register DR contains ADC1 conversion
01264   *         result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last
01265   *         conversion result (ADC1 register DR bits 16 to 27). Therefore, to
01266   *         have DMA transferring the conversion results of ADC1 only, DMA must
01267   *         be configured to transfer size: half word.
01268   * @param  hadc: ADC handle
01269   * @param  pData: The destination Buffer address.
01270   * @param  Length: The length of data to be transferred from ADC peripheral to memory.
01271   * @retval None
01272   */
01273 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
01274 {
01275   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01276
01277   /* Check the parameters */
01278   assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
01279
01280   /* Verification if multimode is disabled (for devices with several ADC)     */
01281   /* If multimode is enabled, dedicated function multimode conversion         */
01282   /* start DMA must be used.                                                  */
01283   if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET)
01284   {
01285     /* Process locked */
01286     __HAL_LOCK(hadc);
01287
01288     /* Enable the ADC peripheral */
01289     tmp_hal_status = ADC_Enable(hadc);
01290
01291     /* Start conversion if ADC is effectively enabled */
01292     if (tmp_hal_status == HAL_OK)
01293     {
01294       /* Set ADC state                                                        */
01295       /* - Clear state bitfield related to regular group conversion results   */
01296       /* - Set state bitfield related to regular operation                    */
01297       ADC_STATE_CLR_SET(hadc->State,
01298                         HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
01299                         HAL_ADC_STATE_REG_BUSY);
01300
01301     /* Set group injected state (from auto-injection) and multimode state     */
01302     /* for all cases of multimode: independent mode, multimode ADC master     */
01303     /* or multimode ADC slave (for devices with several ADCs):                */
01304     if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
01305     {
01306       /* Set ADC state (ADC independent or master) */
01307       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01308
01309       /* If conversions on group regular are also triggering group injected,  */
01310       /* update ADC state.                                                    */
01311       if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
01312       {
01313         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01314       }
01315     }
01316     else
01317     {
01318       /* Set ADC state (ADC slave) */
01319       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01320
01321       /* If conversions on group regular are also triggering group injected,  */
01322       /* update ADC state.                                                    */
01323       if (ADC_MULTIMODE_AUTO_INJECTED(hadc))
01324       {
01325         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01326       }
01327     }
01328
01329       /* State machine update: Check if an injected conversion is ongoing */
01330       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01331       {
01332         /* Reset ADC error code fields related to conversions on group regular */
01333         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
01334       }
01335       else
01336       {
01337         /* Reset ADC all error code fields */
01338         ADC_CLEAR_ERRORCODE(hadc);
01339       }
01340
01341       /* Process unlocked */
01342       /* Unlock before starting ADC conversions: in case of potential         */
01343       /* interruption, to let the process to ADC IRQ Handler.                 */
01344       __HAL_UNLOCK(hadc);
01345
01346       /* Set the DMA transfer complete callback */
01347       hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
01348
01349       /* Set the DMA half transfer complete callback */
01350       hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
01351
01352       /* Set the DMA error callback */
01353       hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
01354
01355
01356       /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC   */
01357       /* start (in case of SW start):                                         */
01358
01359       /* Clear regular group conversion flag and overrun flag */
01360       /* (To ensure of no unknown state from potential previous ADC           */
01361       /* operations)                                                          */
01362       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
01363
01364       /* Enable ADC DMA mode */
01365       SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
01366
01367       /* Start the DMA channel */
01368       HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
01369
01370       /* Enable conversion of regular group.                                  */
01371       /* If software start has been selected, conversion starts immediately.  */
01372       /* If external trigger has been selected, conversion will start at next */
01373       /* trigger event.                                                       */
01374       if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
01375       {
01376         /* Start ADC conversion on regular group with SW start */
01377         SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
01378       }
01379       else
01380       {
01381         /* Start ADC conversion on regular group with external trigger */
01382         SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
01383       }
01384     }
01385     else
01386     {
01387       /* Process unlocked */
01388       __HAL_UNLOCK(hadc);
01389     }
01390   }
01391   else
01392   {
01393     tmp_hal_status = HAL_ERROR;
01394   }
01395
01396   /* Return function status */
01397   return tmp_hal_status;
01398 }
01399
01400 /**
01401   * @brief  Stop ADC conversion of regular group (and injected group in
01402   *         case of auto_injection mode), disable ADC DMA transfer, disable
01403   *         ADC peripheral.
01404   * @note:  ADC peripheral disable is forcing stop of potential
01405   *         conversion on injected group. If injected group is under use, it
01406   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
01407   * @note   For devices with several ADCs: This function is for single-ADC mode
01408   *         only. For multimode, use the dedicated MultimodeStop function.
01409   * @note   On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending
01410   *         on devices) have DMA capability.
01411   * @param  hadc: ADC handle
01412   * @retval HAL status.
01413   */
01414 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
01415 {
01416   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01417
01418   /* Check the parameters */
01419   assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance));
01420
01421   /* Process locked */
01422   __HAL_LOCK(hadc);
01423
01424   /* Stop potential conversion on going, on regular and injected groups */
01425   /* Disable ADC peripheral */
01426   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
01427
01428   /* Check if ADC is effectively disabled */
01429   if (tmp_hal_status == HAL_OK)
01430   {
01431     /* Disable ADC DMA mode */
01432     CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
01433
01434     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01435     /* DMA transfer is on going)                                              */
01436     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
01437
01438     /* Check if DMA channel effectively disabled */
01439     if (tmp_hal_status == HAL_OK)
01440     {
01441       /* Set ADC state */
01442       ADC_STATE_CLR_SET(hadc->State,
01443                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
01444                         HAL_ADC_STATE_READY);
01445     }
01446     else
01447     {
01448       /* Update ADC state machine to error */
01449       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
01450     }
01451   }
01452
01453   /* Process unlocked */
01454   __HAL_UNLOCK(hadc);
01455
01456   /* Return function status */
01457   return tmp_hal_status;
01458 }
01459
01460 /**
01461   * @brief  Get ADC regular group conversion result.
01462   * @note   Reading register DR automatically clears ADC flag EOC
01463   *         (ADC group regular end of unitary conversion).
01464   * @note   This function does not clear ADC flag EOS
01465   *         (ADC group regular end of sequence conversion).
01466   *         Occurrence of flag EOS rising:
01467   *          - If sequencer is composed of 1 rank, flag EOS is equivalent
01468   *            to flag EOC.
01469   *          - If sequencer is composed of several ranks, during the scan
01470   *            sequence flag EOC only is raised, at the end of the scan sequence
01471   *            both flags EOC and EOS are raised.
01472   *         To clear this flag, either use function:
01473   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
01474   *         model polling: @ref HAL_ADC_PollForConversion()
01475   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
01476   * @param  hadc: ADC handle
01477   * @retval ADC group regular conversion data
01478   */
01479 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
01480 {
01481   /* Check the parameters */
01482   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01483
01484   /* Note: EOC flag is not cleared here by software because automatically     */
01485   /*       cleared by hardware when reading register DR.                      */
01486
01487   /* Return ADC converted value */
01488   return hadc->Instance->DR;
01489 }
01490
01491 /**
01492   * @brief  Handles ADC interrupt request
01493   * @param  hadc: ADC handle
01494   * @retval None
01495   */
01496 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
01497 {
01498   /* Check the parameters */
01499   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01500   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
01501   assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
01502
01503
01504   /* ========== Check End of Conversion flag for regular group ========== */
01505   if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
01506   {
01507     if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
01508     {
01509       /* Update state machine on conversion status if not in error state */
01510       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01511       {
01512         /* Set ADC state */
01513         SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01514       }
01515
01516       /* Determine whether any further conversion upcoming on group regular   */
01517       /* by external trigger, continuous mode or scan sequence on going.      */
01518       /* Note: On STM32F1 devices, in case of sequencer enabled               */
01519       /*       (several ranks selected), end of conversion flag is raised     */
01520       /*       at the end of the sequence.                                    */
01521       if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
01522          (hadc->Init.ContinuousConvMode == DISABLE)   )
01523       {
01524         /* Disable ADC end of conversion interrupt on group regular */
01525         __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
01526
01527         /* Set ADC state */
01528         CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01529
01530         if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01531         {
01532           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01533         }
01534       }
01535
01536       /* Conversion complete callback */
01537       HAL_ADC_ConvCpltCallback(hadc);
01538
01539       /* Clear regular group conversion flag */
01540       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
01541     }
01542   }
01543
01544   /* ========== Check End of Conversion flag for injected group ========== */
01545   if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
01546   {
01547     if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
01548     {
01549       /* Update state machine on conversion status if not in error state */
01550       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01551       {
01552         /* Set ADC state */
01553         SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
01554       }
01555
01556       /* Determine whether any further conversion upcoming on group injected  */
01557       /* by external trigger, scan sequence on going or by automatic injected */
01558       /* conversion from group regular (same conditions as group regular      */
01559       /* interruption disabling above).                                       */
01560       /* Note: On STM32F1 devices, in case of sequencer enabled               */
01561       /*       (several ranks selected), end of conversion flag is raised     */
01562       /*       at the end of the sequence.                                    */
01563       if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     ||
01564          (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
01565          (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
01566           (hadc->Init.ContinuousConvMode == DISABLE)   )        )   )
01567       {
01568         /* Disable ADC end of conversion interrupt on group injected */
01569         __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01570
01571         /* Set ADC state */
01572         CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01573
01574         if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
01575         {
01576           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01577         }
01578       }
01579
01580       /* Conversion complete callback */
01581       HAL_ADCEx_InjectedConvCpltCallback(hadc);
01582
01583       /* Clear injected group conversion flag */
01584       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
01585     }
01586   }
01587
01588   /* ========== Check Analog watchdog flags ========== */
01589   if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
01590   {
01591     if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
01592     {
01593       /* Set ADC state */
01594       SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01595
01596       /* Level out of window callback */
01597       HAL_ADC_LevelOutOfWindowCallback(hadc);
01598
01599       /* Clear the ADC analog watchdog flag */
01600       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
01601     }
01602   }
01603
01604 }
01605
01606 /**
01607   * @brief  Conversion complete callback in non blocking mode
01608   * @param  hadc: ADC handle
01609   * @retval None
01610   */
01611 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
01612 {
01613   /* Prevent unused argument(s) compilation warning */
01614   UNUSED(hadc);
01615   /* NOTE : This function should not be modified. When the callback is needed,
01616             function HAL_ADC_ConvCpltCallback must be implemented in the user file.
01617    */
01618 }
01619
01620 /**
01621   * @brief  Conversion DMA half-transfer callback in non blocking mode
01622   * @param  hadc: ADC handle
01623   * @retval None
01624   */
01625 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
01626 {
01627   /* Prevent unused argument(s) compilation warning */
01628   UNUSED(hadc);
01629   /* NOTE : This function should not be modified. When the callback is needed,
01630             function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
01631   */
01632 }
01633
01634 /**
01635   * @brief  Analog watchdog callback in non blocking mode.
01636   * @param  hadc: ADC handle
01637   * @retval None
01638   */
01639 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
01640 {
01641   /* Prevent unused argument(s) compilation warning */
01642   UNUSED(hadc);
01643   /* NOTE : This function should not be modified. When the callback is needed,
01644             function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
01645   */
01646 }
01647
01648 /**
01649   * @brief  ADC error callback in non blocking mode
01650   *        (ADC conversion with interruption or transfer by DMA)
01651   * @param  hadc: ADC handle
01652   * @retval None
01653   */
01654 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
01655 {
01656   /* Prevent unused argument(s) compilation warning */
01657   UNUSED(hadc);
01658   /* NOTE : This function should not be modified. When the callback is needed,
01659             function HAL_ADC_ErrorCallback must be implemented in the user file.
01660   */
01661 }
01662
01663
01664 /**
01665   * @}
01666   */
01667
01668 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
01669  *  @brief    Peripheral Control functions
01670  *
01671 @verbatim
01672  ===============================================================================
01673              ##### Peripheral Control functions #####
01674  ===============================================================================
01675     [..]  This section provides functions allowing to:
01676       (+) Configure channels on regular group
01677       (+) Configure the analog watchdog
01678
01679 @endverbatim
01680   * @{
01681   */
01682
01683 /**
01684   * @brief  Configures the the selected channel to be linked to the regular
01685   *         group.
01686   * @note   In case of usage of internal measurement channels:
01687   *         Vbat/VrefInt/TempSensor.
01688   *         These internal paths can be be disabled using function
01689   *         HAL_ADC_DeInit().
01690   * @note   Possibility to update parameters on the fly:
01691   *         This function initializes channel into regular group, following
01692   *         calls to this function can be used to reconfigure some parameters
01693   *         of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
01694   *         the ADC.
01695   *         The setting of these parameters is conditioned to ADC state.
01696   *         For parameters constraints, see comments of structure
01697   *         "ADC_ChannelConfTypeDef".
01698   * @param  hadc: ADC handle
01699   * @param  sConfig: Structure of ADC channel for regular group.
01700   * @retval HAL status
01701   */
01702 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
01703 {
01704   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01705   __IO uint32_t wait_loop_index = 0U;
01706
01707   /* Check the parameters */
01708   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01709   assert_param(IS_ADC_CHANNEL(sConfig->Channel));
01710   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
01711   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
01712
01713   /* Process locked */
01714   __HAL_LOCK(hadc);
01715
01716
01717   /* Regular sequence configuration */
01718   /* For Rank 1 to 6 */
01719   if (sConfig->Rank < 7U)
01720   {
01721     MODIFY_REG(hadc->Instance->SQR3                        ,
01722                ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank)    ,
01723                ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
01724   }
01725   /* For Rank 7 to 12 */
01726   else if (sConfig->Rank < 13U)
01727   {
01728     MODIFY_REG(hadc->Instance->SQR2                        ,
01729                ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank)    ,
01730                ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
01731   }
01732   /* For Rank 13 to 16 */
01733   else
01734   {
01735     MODIFY_REG(hadc->Instance->SQR1                        ,
01736                ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank)   ,
01737                ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
01738   }
01739
01740
01741   /* Channel sampling time configuration */
01742   /* For channels 10 to 17 */
01743   if (sConfig->Channel >= ADC_CHANNEL_10)
01744   {
01745     MODIFY_REG(hadc->Instance->SMPR1                             ,
01746                ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel)      ,
01747                ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
01748   }
01749   else /* For channels 0 to 9 */
01750   {
01751     MODIFY_REG(hadc->Instance->SMPR2                             ,
01752                ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel)       ,
01753                ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
01754   }
01755
01756   /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
01757   /* and VREFINT measurement path.                                            */
01758   if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
01759       (sConfig->Channel == ADC_CHANNEL_VREFINT)      )
01760   {
01761     /* For STM32F1 devices with several ADC: Only ADC1 can access internal    */
01762     /* measurement channels (VrefInt/TempSensor). If these channels are       */
01763     /* intended to be set on other ADC instances, an error is reported.       */
01764     if (hadc->Instance == ADC1)
01765     {
01766       if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
01767       {
01768         SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
01769
01770         if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
01771         {
01772           /* Delay for temperature sensor stabilization time */
01773           /* Compute number of CPU cycles to wait for */
01774           wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
01775           while(wait_loop_index != 0U)
01776           {
01777             wait_loop_index--;
01778           }
01779         }
01780       }
01781     }
01782     else
01783     {
01784       /* Update ADC state machine to error */
01785       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01786
01787       tmp_hal_status = HAL_ERROR;
01788     }
01789   }
01790
01791   /* Process unlocked */
01792   __HAL_UNLOCK(hadc);
01793
01794   /* Return function status */
01795   return tmp_hal_status;
01796 }
01797
01798 /**
01799   * @brief  Configures the analog watchdog.
01800   * @note   Analog watchdog thresholds can be modified while ADC conversion
01801   *         is on going.
01802   *         In this case, some constraints must be taken into account:
01803   *         the programmed threshold values are effective from the next
01804   *         ADC EOC (end of unitary conversion).
01805   *         Considering that registers write delay may happen due to
01806   *         bus activity, this might cause an uncertainty on the
01807   *         effective timing of the new programmed threshold values.
01808   * @param  hadc: ADC handle
01809   * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
01810   * @retval HAL status
01811   */
01812 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
01813 {
01814   /* Check the parameters */
01815   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01816   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
01817   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
01818   assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
01819   assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
01820
01821   if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
01822      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
01823      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
01824   {
01825     assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
01826   }
01827
01828   /* Process locked */
01829   __HAL_LOCK(hadc);
01830
01831   /* Analog watchdog configuration */
01832
01833   /* Configure ADC Analog watchdog interrupt */
01834   if(AnalogWDGConfig->ITMode == ENABLE)
01835   {
01836     /* Enable the ADC Analog watchdog interrupt */
01837     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
01838   }
01839   else
01840   {
01841     /* Disable the ADC Analog watchdog interrupt */
01842     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
01843   }
01844
01845   /* Configuration of analog watchdog:                                        */
01846   /*  - Set the analog watchdog enable mode: regular and/or injected groups,  */
01847   /*    one or all channels.                                                  */
01848   /*  - Set the Analog watchdog channel (is not used if watchdog              */
01849   /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                             */
01850   MODIFY_REG(hadc->Instance->CR1            ,
01851              ADC_CR1_AWDSGL |
01852              ADC_CR1_JAWDEN |
01853              ADC_CR1_AWDEN  |
01854              ADC_CR1_AWDCH                  ,
01855              AnalogWDGConfig->WatchdogMode |
01856              AnalogWDGConfig->Channel        );
01857
01858   /* Set the high threshold */
01859   WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold);
01860
01861   /* Set the low threshold */
01862   WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold);
01863
01864   /* Process unlocked */
01865   __HAL_UNLOCK(hadc);
01866
01867   /* Return function status */
01868   return HAL_OK;
01869 }
01870
01871
01872 /**
01873   * @}
01874   */
01875
01876
01877 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
01878  *  @brief    Peripheral State functions
01879  *
01880 @verbatim
01881  ===============================================================================
01882             ##### Peripheral State and Errors functions #####
01883  ===============================================================================
01884     [..]
01885     This subsection provides functions to get in run-time the status of the
01886     peripheral.
01887       (+) Check the ADC state
01888       (+) Check the ADC error code
01889
01890 @endverbatim
01891   * @{
01892   */
01893
01894 /**
01895   * @brief  return the ADC state
01896   * @param  hadc: ADC handle
01897   * @retval HAL state
01898   */
01899 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
01900 {
01901   /* Return ADC state */
01902   return hadc->State;
01903 }
01904
01905 /**
01906   * @brief  Return the ADC error code
01907   * @param  hadc: ADC handle
01908   * @retval ADC Error Code
01909   */
01910 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
01911 {
01912   return hadc->ErrorCode;
01913 }
01914
01915 /**
01916   * @}
01917   */
01918
01919 /**
01920   * @}
01921   */
01922
01923 /** @defgroup ADC_Private_Functions ADC Private Functions
01924   * @{
01925   */
01926
01927 /**
01928   * @brief  Enable the selected ADC.
01929   * @note   Prerequisite condition to use this function: ADC must be disabled
01930   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
01931   * @param  hadc: ADC handle
01932   * @retval HAL status.
01933   */
01934 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
01935 {
01936   uint32_t tickstart = 0U;
01937   __IO uint32_t wait_loop_index = 0U;
01938
01939   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
01940   /* enabling phase not yet completed: flag ADC ready not yet set).           */
01941   /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
01942   /* causes: ADC clock not running, ...).                                     */
01943   if (ADC_IS_ENABLE(hadc) == RESET)
01944   {
01945     /* Enable the Peripheral */
01946     __HAL_ADC_ENABLE(hadc);
01947
01948     /* Delay for ADC stabilization time */
01949     /* Compute number of CPU cycles to wait for */
01950     wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
01951     while(wait_loop_index != 0U)
01952     {
01953       wait_loop_index--;
01954     }
01955
01956     /* Get tick count */
01957     tickstart = HAL_GetTick();
01958
01959     /* Wait for ADC effectively enabled */
01960     while(ADC_IS_ENABLE(hadc) == RESET)
01961     {
01962       if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
01963       {
01964         /* Update ADC state machine to error */
01965         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01966
01967         /* Set ADC error code to ADC IP internal error */
01968         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
01969
01970         /* Process unlocked */
01971         __HAL_UNLOCK(hadc);
01972
01973         return HAL_ERROR;
01974       }
01975     }
01976   }
01977
01978   /* Return HAL status */
01979   return HAL_OK;
01980 }
01981
01982 /**
01983   * @brief  Stop ADC conversion and disable the selected ADC
01984   * @note   Prerequisite condition to use this function: ADC conversions must be
01985   *         stopped to disable the ADC.
01986   * @param  hadc: ADC handle
01987   * @retval HAL status.
01988   */
01989 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
01990 {
01991   uint32_t tickstart = 0U;
01992
01993   /* Verification if ADC is not already disabled */
01994   if (ADC_IS_ENABLE(hadc) != RESET)
01995   {
01996     /* Disable the ADC peripheral */
01997     __HAL_ADC_DISABLE(hadc);
01998
01999     /* Get tick count */
02000     tickstart = HAL_GetTick();
02001
02002     /* Wait for ADC effectively disabled */
02003     while(ADC_IS_ENABLE(hadc) != RESET)
02004     {
02005       if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
02006       {
02007         /* Update ADC state machine to error */
02008         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02009
02010         /* Set ADC error code to ADC IP internal error */
02011         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02012
02013         return HAL_ERROR;
02014       }
02015     }
02016   }
02017
02018   /* Return HAL status */
02019   return HAL_OK;
02020 }
02021
02022 /**
02023   * @brief  DMA transfer complete callback.
02024   * @param  hdma: pointer to DMA handle.
02025   * @retval None
02026   */
02027 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
02028 {
02029   /* Retrieve ADC handle corresponding to current DMA handle */
02030   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02031
02032   /* Update state machine on conversion status if not in error state */
02033   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))
02034   {
02035     /* Update ADC state machine */
02036     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
02037
02038     /* Determine whether any further conversion upcoming on group regular     */
02039     /* by external trigger, continuous mode or scan sequence on going.        */
02040     /* Note: On STM32F1 devices, in case of sequencer enabled                 */
02041     /*       (several ranks selected), end of conversion flag is raised       */
02042     /*       at the end of the sequence.                                      */
02043     if(ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
02044        (hadc->Init.ContinuousConvMode == DISABLE)   )
02045     {
02046       /* Set ADC state */
02047       CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
02048
02049       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
02050       {
02051         SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02052       }
02053     }
02054
02055     /* Conversion complete callback */
02056     HAL_ADC_ConvCpltCallback(hadc);
02057   }
02058   else
02059   {
02060     /* Call DMA error callback */
02061     hadc->DMA_Handle->XferErrorCallback(hdma);
02062   }
02063 }
02064
02065 /**
02066   * @brief  DMA half transfer complete callback.
02067   * @param  hdma: pointer to DMA handle.
02068   * @retval None
02069   */
02070 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
02071 {
02072   /* Retrieve ADC handle corresponding to current DMA handle */
02073   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02074
02075   /* Half conversion callback */
02076   HAL_ADC_ConvHalfCpltCallback(hadc);
02077 }
02078
02079 /**
02080   * @brief  DMA error callback
02081   * @param  hdma: pointer to DMA handle.
02082   * @retval None
02083   */
02084 void ADC_DMAError(DMA_HandleTypeDef *hdma)
02085 {
02086   /* Retrieve ADC handle corresponding to current DMA handle */
02087   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02088
02089   /* Set ADC state */
02090   SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
02091
02092   /* Set ADC error code to DMA error */
02093   SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
02094
02095   /* Error callback */
02096   HAL_ADC_ErrorCallback(hadc);
02097 }
02098
02099 /**
02100   * @}
02101   */
02102
02103 #endif /* HAL_ADC_MODULE_ENABLED */
02104 /**
02105   * @}
02106   */
02107
02108 /**
02109   * @}
02110   */
02111
02112 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_adc.h Source File

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stm32f1xx_hal_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_adc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file containing functions prototypes of ADC HAL library.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_ADC_H
00040 #define __STM32F1xx_HAL_ADC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048 /** @addtogroup STM32F1xx_HAL_Driver
00049   * @{
00050   */
00051
00052 /** @addtogroup ADC
00053   * @{
00054   */
00055
00056 /* Exported types ------------------------------------------------------------*/
00057 /** @defgroup ADC_Exported_Types ADC Exported Types
00058   * @{
00059   */
00060
00061 /**
00062   * @brief  Structure definition of ADC and regular group initialization
00063   * @note   Parameters of this structure are shared within 2 scopes:
00064   *          - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
00065   *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
00066   * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
00067   *         ADC can be either disabled or enabled without conversion on going on regular group.
00068   */
00069 typedef struct
00070 {
00071   uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
00072                                        or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
00073                                        This parameter can be a value of @ref ADC_Data_align */
00074   uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
00075                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
00076                                        If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
00077                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
00078                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
00079                                                     Scan direction is upward: from rank1 to rank 'n'.
00080                                        This parameter can be a value of @ref ADC_Scan_mode
00081                                        Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
00082                                              or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
00083                                              the last conversion of the sequence. All previous conversions would be overwritten by the last one.
00084                                              Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
00085   uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
00086                                        after the selected trigger occurred (software start or external trigger).
00087                                        This parameter can be set to ENABLE or DISABLE. */
00088   uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
00089                                        To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00090                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
00091   uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
00092                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00093                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00094                                        This parameter can be set to ENABLE or DISABLE. */
00095   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
00096                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
00097                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
00098   uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
00099                                        If set to ADC_SOFTWARE_START, external triggers are disabled.
00100                                        If set to external trigger source, triggering is on event rising edge.
00101                                        This parameter can be a value of @ref ADC_External_trigger_source_Regular */
00102 }ADC_InitTypeDef;
00103
00104 /**
00105   * @brief  Structure definition of ADC channel for regular group
00106   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
00107   *         ADC can be either disabled or enabled without conversion on going on regular group.
00108   */
00109 typedef struct
00110 {
00111   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
00112                                         This parameter can be a value of @ref ADC_channels
00113                                         Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
00114                                         Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
00115                                         Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
00116                                               It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
00117                                               Refer to errata sheet of these devices for more details. */
00118   uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer
00119                                         This parameter can be a value of @ref ADC_regular_rank
00120                                         Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
00121   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
00122                                         Unit: ADC clock cycles
00123                                         Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
00124                                         This parameter can be a value of @ref ADC_sampling_times
00125                                         Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00126                                                  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00127                                         Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
00128                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00129                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
00130 }ADC_ChannelConfTypeDef;
00131
00132 /**
00133   * @brief  ADC Configuration analog watchdog definition
00134   * @note   The setting of these parameters with function is conditioned to ADC state.
00135   *         ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
00136   */
00137 typedef struct
00138 {
00139   uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
00140                                    This parameter can be a value of @ref ADC_analog_watchdog_mode. */
00141   uint32_t Channel;           /*!< Selects which ADC channel to monitor by analog watchdog.
00142                                    This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
00143                                    This parameter can be a value of @ref ADC_channels. */
00144   uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
00145                                    This parameter can be set to ENABLE or DISABLE */
00146   uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
00147                                    This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00148   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
00149                                    This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
00150   uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
00151 }ADC_AnalogWDGConfTypeDef;
00152
00153 /**
00154   * @brief  HAL ADC state machine: ADC states definition (bitfields)
00155   */
00156 /* States of ADC global scope */
00157 #define HAL_ADC_STATE_RESET             0x00000000U    /*!< ADC not yet initialized or disabled */
00158 #define HAL_ADC_STATE_READY             0x00000001U    /*!< ADC peripheral ready for use */
00159 #define HAL_ADC_STATE_BUSY_INTERNAL     0x00000002U    /*!< ADC is busy to internal process (initialization, calibration) */
00160 #define HAL_ADC_STATE_TIMEOUT           0x00000004U    /*!< TimeOut occurrence */
00161
00162 /* States of ADC errors */
00163 #define HAL_ADC_STATE_ERROR_INTERNAL    0x00000010U    /*!< Internal error occurrence */
00164 #define HAL_ADC_STATE_ERROR_CONFIG      0x00000020U    /*!< Configuration error occurrence */
00165 #define HAL_ADC_STATE_ERROR_DMA         0x00000040U    /*!< DMA error occurrence */
00166
00167 /* States of ADC group regular */
00168 #define HAL_ADC_STATE_REG_BUSY          0x00000100U    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
00169                                                            external trigger, low power auto power-on, multimode ADC master control) */
00170 #define HAL_ADC_STATE_REG_EOC           0x00000200U    /*!< Conversion data available on group regular */
00171 #define HAL_ADC_STATE_REG_OVR           0x00000400U    /*!< Not available on STM32F1 device: Overrun occurrence */
00172 #define HAL_ADC_STATE_REG_EOSMP         0x00000800U    /*!< Not available on STM32F1 device: End Of Sampling flag raised  */
00173
00174 /* States of ADC group injected */
00175 #define HAL_ADC_STATE_INJ_BUSY          0x00001000U    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
00176                                                            external trigger, low power auto power-on, multimode ADC master control) */
00177 #define HAL_ADC_STATE_INJ_EOC           0x00002000U    /*!< Conversion data available on group injected */
00178 #define HAL_ADC_STATE_INJ_JQOVF         0x00004000U    /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
00179
00180 /* States of ADC analog watchdogs */
00181 #define HAL_ADC_STATE_AWD1              0x00010000U    /*!< Out-of-window occurrence of analog watchdog 1 */
00182 #define HAL_ADC_STATE_AWD2              0x00020000U    /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
00183 #define HAL_ADC_STATE_AWD3              0x00040000U    /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
00184
00185 /* States of ADC multi-mode */
00186 #define HAL_ADC_STATE_MULTIMODE_SLAVE   0x00100000U    /*!< ADC in multimode slave state, controlled by another ADC master ( */
00187
00188
00189 /**
00190   * @brief  ADC handle Structure definition
00191   */
00192 typedef struct
00193 {
00194   ADC_TypeDef                   *Instance;              /*!< Register base address */
00195
00196   ADC_InitTypeDef               Init;                   /*!< ADC required parameters */
00197
00198   DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
00199
00200   HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
00201
00202   __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
00203
00204   __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
00205 }ADC_HandleTypeDef;
00206 /**
00207   * @}
00208   */
00209
00210
00211
00212 /* Exported constants --------------------------------------------------------*/
00213
00214 /** @defgroup ADC_Exported_Constants ADC Exported Constants
00215   * @{
00216   */
00217
00218 /** @defgroup ADC_Error_Code ADC Error Code
00219   * @{
00220   */
00221 #define HAL_ADC_ERROR_NONE                0x00U   /*!< No error                                              */
00222 #define HAL_ADC_ERROR_INTERNAL            0x01U   /*!< ADC IP internal error: if problem of clocking,
00223                                                        enable/disable, erroneous state                       */
00224 #define HAL_ADC_ERROR_OVR                 0x02U   /*!< Overrun error                                         */
00225 #define HAL_ADC_ERROR_DMA                 0x04U   /*!< DMA transfer error                                    */
00226
00227 /**
00228   * @}
00229   */
00230
00231
00232 /** @defgroup ADC_Data_align ADC data alignment
00233   * @{
00234   */
00235 #define ADC_DATAALIGN_RIGHT      0x00000000U
00236 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup ADC_Scan_mode ADC scan mode
00242   * @{
00243   */
00244 /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for     */
00245 /*       compatibility with other STM32 devices having a sequencer with       */
00246 /*       additional options.                                                  */
00247 #define ADC_SCAN_DISABLE         0x00000000U
00248 #define ADC_SCAN_ENABLE          ((uint32_t)ADC_CR1_SCAN)
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
00254   * @{
00255   */
00256 #define ADC_EXTERNALTRIGCONVEDGE_NONE           0x00000000U
00257 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTTRIG)
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup ADC_channels ADC channels
00263   * @{
00264   */
00265 /* Note: Depending on devices, some channels may not be available on package  */
00266 /*       pins. Refer to device datasheet for channels availability.           */
00267 #define ADC_CHANNEL_0                       0x00000000U
00268 #define ADC_CHANNEL_1           ((uint32_t)(                                                                    ADC_SQR3_SQ1_0))
00269 #define ADC_CHANNEL_2           ((uint32_t)(                                                   ADC_SQR3_SQ1_1                 ))
00270 #define ADC_CHANNEL_3           ((uint32_t)(                                                   ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
00271 #define ADC_CHANNEL_4           ((uint32_t)(                                  ADC_SQR3_SQ1_2                                  ))
00272 #define ADC_CHANNEL_5           ((uint32_t)(                                  ADC_SQR3_SQ1_2                  | ADC_SQR3_SQ1_0))
00273 #define ADC_CHANNEL_6           ((uint32_t)(                                  ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1                 ))
00274 #define ADC_CHANNEL_7           ((uint32_t)(                                  ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
00275 #define ADC_CHANNEL_8           ((uint32_t)(                 ADC_SQR3_SQ1_3                                                   ))
00276 #define ADC_CHANNEL_9           ((uint32_t)(                 ADC_SQR3_SQ1_3                                   | ADC_SQR3_SQ1_0))
00277 #define ADC_CHANNEL_10          ((uint32_t)(                 ADC_SQR3_SQ1_3                  | ADC_SQR3_SQ1_1                 ))
00278 #define ADC_CHANNEL_11          ((uint32_t)(                 ADC_SQR3_SQ1_3                  | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
00279 #define ADC_CHANNEL_12          ((uint32_t)(                 ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2                                  ))
00280 #define ADC_CHANNEL_13          ((uint32_t)(                 ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2                  | ADC_SQR3_SQ1_0))
00281 #define ADC_CHANNEL_14          ((uint32_t)(                 ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1                 ))
00282 #define ADC_CHANNEL_15          ((uint32_t)(                 ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
00283 #define ADC_CHANNEL_16          ((uint32_t)(ADC_SQR3_SQ1_4                                                                    ))
00284 #define ADC_CHANNEL_17          ((uint32_t)(ADC_SQR3_SQ1_4                                                    | ADC_SQR3_SQ1_0))
00285
00286 #define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_16  /* ADC internal channel (no connection on device pin) */
00287 #define ADC_CHANNEL_VREFINT     ADC_CHANNEL_17  /* ADC internal channel (no connection on device pin) */
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup ADC_sampling_times ADC sampling times
00293   * @{
00294   */
00295 #define ADC_SAMPLETIME_1CYCLE_5                   0x00000000U                                              /*!< Sampling time 1.5 ADC clock cycle */
00296 #define ADC_SAMPLETIME_7CYCLES_5      ((uint32_t)(                                      ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */
00297 #define ADC_SAMPLETIME_13CYCLES_5     ((uint32_t)(                   ADC_SMPR2_SMP0_1                   )) /*!< Sampling time 13.5 ADC clock cycles */
00298 #define ADC_SAMPLETIME_28CYCLES_5     ((uint32_t)(                   ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
00299 #define ADC_SAMPLETIME_41CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP0_2                                      )) /*!< Sampling time 41.5 ADC clock cycles */
00300 #define ADC_SAMPLETIME_55CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP0_2                    | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
00301 #define ADC_SAMPLETIME_71CYCLES_5     ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1                   )) /*!< Sampling time 71.5 ADC clock cycles */
00302 #define ADC_SAMPLETIME_239CYCLES_5    ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup ADC_regular_rank ADC rank into regular group
00308   * @{
00309   */
00310 #define ADC_REGULAR_RANK_1                 0x00000001U
00311 #define ADC_REGULAR_RANK_2                 0x00000002U
00312 #define ADC_REGULAR_RANK_3                 0x00000003U
00313 #define ADC_REGULAR_RANK_4                 0x00000004U
00314 #define ADC_REGULAR_RANK_5                 0x00000005U
00315 #define ADC_REGULAR_RANK_6                 0x00000006U
00316 #define ADC_REGULAR_RANK_7                 0x00000007U
00317 #define ADC_REGULAR_RANK_8                 0x00000008U
00318 #define ADC_REGULAR_RANK_9                 0x00000009U
00319 #define ADC_REGULAR_RANK_10                0x0000000AU
00320 #define ADC_REGULAR_RANK_11                0x0000000BU
00321 #define ADC_REGULAR_RANK_12                0x0000000CU
00322 #define ADC_REGULAR_RANK_13                0x0000000DU
00323 #define ADC_REGULAR_RANK_14                0x0000000EU
00324 #define ADC_REGULAR_RANK_15                0x0000000FU
00325 #define ADC_REGULAR_RANK_16                0x00000010U
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
00331   * @{
00332   */
00333 #define ADC_ANALOGWATCHDOG_NONE                             0x00000000U
00334 #define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
00335 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
00336 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
00337 #define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t)ADC_CR1_AWDEN)
00338 #define ADC_ANALOGWATCHDOG_ALL_INJEC            ((uint32_t)ADC_CR1_JAWDEN)
00339 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC         ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
00340 /**
00341   * @}
00342   */
00343
00344 /** @defgroup ADC_conversion_group ADC conversion group
00345   * @{
00346   */
00347 #define ADC_REGULAR_GROUP             ((uint32_t)(ADC_FLAG_EOC))
00348 #define ADC_INJECTED_GROUP            ((uint32_t)(ADC_FLAG_JEOC))
00349 #define ADC_REGULAR_INJECTED_GROUP    ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
00350 /**
00351   * @}
00352   */
00353
00354 /** @defgroup ADC_Event_type ADC Event type
00355   * @{
00356   */
00357 #define ADC_AWD_EVENT               ((uint32_t)ADC_FLAG_AWD)   /*!< ADC Analog watchdog event */
00358
00359 #define ADC_AWD1_EVENT              ADC_AWD_EVENT              /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup ADC_interrupts_definition ADC interrupts definition
00365   * @{
00366   */
00367 #define ADC_IT_EOC           ADC_CR1_EOCIE        /*!< ADC End of Regular Conversion interrupt source */
00368 #define ADC_IT_JEOC          ADC_CR1_JEOCIE       /*!< ADC End of Injected Conversion interrupt source */
00369 #define ADC_IT_AWD           ADC_CR1_AWDIE        /*!< ADC Analog watchdog interrupt source */
00370 /**
00371   * @}
00372   */
00373
00374 /** @defgroup ADC_flags_definition ADC flags definition
00375   * @{
00376   */
00377 #define ADC_FLAG_STRT          ADC_SR_STRT     /*!< ADC Regular group start flag */
00378 #define ADC_FLAG_JSTRT         ADC_SR_JSTRT    /*!< ADC Injected group start flag */
00379 #define ADC_FLAG_EOC           ADC_SR_EOC      /*!< ADC End of Regular conversion flag */
00380 #define ADC_FLAG_JEOC          ADC_SR_JEOC     /*!< ADC End of Injected conversion flag */
00381 #define ADC_FLAG_AWD           ADC_SR_AWD      /*!< ADC Analog watchdog flag */
00382 /**
00383   * @}
00384   */
00385
00386
00387 /**
00388   * @}
00389   */
00390
00391 /* Private constants ---------------------------------------------------------*/
00392
00393 /** @addtogroup ADC_Private_Constants ADC Private Constants
00394   * @{
00395   */
00396
00397 /** @defgroup ADC_conversion_cycles ADC conversion cycles
00398   * @{
00399   */
00400 /* ADC conversion cycles (unit: ADC clock cycles)                           */
00401 /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
00402 /* resolution 12 bits)                                                      */
00403 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5                  14U
00404 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5                 20U
00405 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5                26U
00406 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5                41U
00407 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5                54U
00408 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5                68U
00409 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5                84U
00410 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5              252U
00411 /**
00412   * @}
00413   */
00414
00415 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
00416   * @{
00417   */
00418 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2                                          \
00419      (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 |     \
00420       ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 |     \
00421       ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
00422 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2                                          \
00423      (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
00424       ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
00425
00426 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1                                          \
00427      (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 |     \
00428       ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 |     \
00429       ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
00430 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1                                          \
00431      (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
00432       ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
00433
00434 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0                                          \
00435      (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 |     \
00436       ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 |     \
00437       ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
00438 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0                                          \
00439      (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
00440       ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
00441
00442 #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS    0x00000000U
00443 #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
00444 #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
00445 #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
00446 #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
00447 #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
00448 #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
00449 #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
00450
00451 #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS    0x00000000U
00452 #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS   (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
00453 #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
00454 #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
00455 #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
00456 #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
00457 #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS  (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
00458 #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
00459 /**
00460   * @}
00461   */
00462
00463 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
00464 #define ADC_FLAG_POSTCONV_ALL   (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
00465
00466 /**
00467   * @}
00468   */
00469
00470
00471 /* Exported macro ------------------------------------------------------------*/
00472
00473 /** @defgroup ADC_Exported_Macros ADC Exported Macros
00474   * @{
00475   */
00476 /* Macro for internal HAL driver usage, and possibly can be used into code of */
00477 /* final user.                                                                */
00478
00479 /**
00480   * @brief Enable the ADC peripheral
00481   * @note ADC enable requires a delay for ADC stabilization time
00482   *       (refer to device datasheet, parameter tSTAB)
00483   * @note On STM32F1, if ADC is already enabled this macro trigs a conversion
00484   *       SW start on regular group.
00485   * @param __HANDLE__: ADC handle
00486   * @retval None
00487   */
00488 #define __HAL_ADC_ENABLE(__HANDLE__)                                           \
00489   (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
00490
00491 /**
00492   * @brief Disable the ADC peripheral
00493   * @param __HANDLE__: ADC handle
00494   * @retval None
00495   */
00496 #define __HAL_ADC_DISABLE(__HANDLE__)                                          \
00497   (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
00498
00499 /** @brief Enable the ADC end of conversion interrupt.
00500   * @param __HANDLE__: ADC handle
00501   * @param __INTERRUPT__: ADC Interrupt
00502   *          This parameter can be any combination of the following values:
00503   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
00504   *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
00505   *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
00506   * @retval None
00507   */
00508 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
00509   (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
00510
00511 /** @brief Disable the ADC end of conversion interrupt.
00512   * @param __HANDLE__: ADC handle
00513   * @param __INTERRUPT__: ADC Interrupt
00514   *          This parameter can be any combination of the following values:
00515   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
00516   *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
00517   *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
00518   * @retval None
00519   */
00520 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
00521   (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
00522
00523 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
00524   * @param __HANDLE__: ADC handle
00525   * @param __INTERRUPT__: ADC interrupt source to check
00526   *          This parameter can be any combination of the following values:
00527   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
00528   *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
00529   *            @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
00530   * @retval None
00531   */
00532 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
00533   (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
00534
00535 /** @brief Get the selected ADC's flag status.
00536   * @param __HANDLE__: ADC handle
00537   * @param __FLAG__: ADC flag
00538   *          This parameter can be any combination of the following values:
00539   *            @arg ADC_FLAG_STRT: ADC Regular group start flag
00540   *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
00541   *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
00542   *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
00543   *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
00544   * @retval None
00545   */
00546 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
00547   ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00548
00549 /** @brief Clear the ADC's pending flags
00550   * @param __HANDLE__: ADC handle
00551   * @param __FLAG__: ADC flag
00552   *          This parameter can be any combination of the following values:
00553   *            @arg ADC_FLAG_STRT: ADC Regular group start flag
00554   *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
00555   *            @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
00556   *            @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
00557   *            @arg ADC_FLAG_AWD: ADC Analog watchdog flag
00558   * @retval None
00559   */
00560 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
00561   (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
00562
00563 /** @brief  Reset ADC handle state
00564   * @param  __HANDLE__: ADC handle
00565   * @retval None
00566   */
00567 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
00568   ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
00569
00570 /**
00571   * @}
00572   */
00573
00574 /* Private macro ------------------------------------------------------------*/
00575
00576 /** @defgroup ADC_Private_Macros ADC Private Macros
00577   * @{
00578   */
00579 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
00580 /* code of final user.                                                        */
00581
00582 /**
00583   * @brief Verification of ADC state: enabled or disabled
00584   * @param __HANDLE__: ADC handle
00585   * @retval SET (ADC enabled) or RESET (ADC disabled)
00586   */
00587 #define ADC_IS_ENABLE(__HANDLE__)                                              \
00588   ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON )           \
00589    ) ? SET : RESET)
00590
00591 /**
00592   * @brief Test if conversion trigger of regular group is software start
00593   *        or external trigger.
00594   * @param __HANDLE__: ADC handle
00595   * @retval SET (software start) or RESET (external trigger)
00596   */
00597 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
00598   (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
00599
00600 /**
00601   * @brief Test if conversion trigger of injected group is software start
00602   *        or external trigger.
00603   * @param __HANDLE__: ADC handle
00604   * @retval SET (software start) or RESET (external trigger)
00605   */
00606 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
00607   (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
00608
00609 /**
00610   * @brief Simultaneously clears and sets specific bits of the handle State
00611   * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
00612   *        the first parameter is the ADC handle State, the second parameter is the
00613   *        bit field to clear, the third and last parameter is the bit field to set.
00614   * @retval None
00615   */
00616 #define ADC_STATE_CLR_SET MODIFY_REG
00617
00618 /**
00619   * @brief Clear ADC error code (set it to error code: "no error")
00620   * @param __HANDLE__: ADC handle
00621   * @retval None
00622   */
00623 #define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
00624   ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
00625
00626 /**
00627   * @brief Set ADC number of conversions into regular channel sequence length.
00628   * @param _NbrOfConversion_: Regular channel sequence length
00629   * @retval None
00630   */
00631 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_)                                    \
00632   (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
00633
00634 /**
00635   * @brief Set the ADC's sample time for channel numbers between 10 and 18.
00636   * @param _SAMPLETIME_: Sample time parameter.
00637   * @param _CHANNELNB_: Channel number.
00638   * @retval None
00639   */
00640 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_)                                   \
00641   ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
00642
00643 /**
00644   * @brief Set the ADC's sample time for channel numbers between 0 and 9.
00645   * @param _SAMPLETIME_: Sample time parameter.
00646   * @param _CHANNELNB_: Channel number.
00647   * @retval None
00648   */
00649 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_)                                   \
00650   ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
00651
00652 /**
00653   * @brief Set the selected regular channel rank for rank between 1 and 6.
00654   * @param _CHANNELNB_: Channel number.
00655   * @param _RANKNB_: Rank number.
00656   * @retval None
00657   */
00658 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_)                                     \
00659   ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
00660
00661 /**
00662   * @brief Set the selected regular channel rank for rank between 7 and 12.
00663   * @param _CHANNELNB_: Channel number.
00664   * @param _RANKNB_: Rank number.
00665   * @retval None
00666   */
00667 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_)                                     \
00668   ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
00669
00670 /**
00671   * @brief Set the selected regular channel rank for rank between 13 and 16.
00672   * @param _CHANNELNB_: Channel number.
00673   * @param _RANKNB_: Rank number.
00674   * @retval None
00675   */
00676 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_)                                     \
00677   ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
00678
00679 /**
00680   * @brief Set the injected sequence length.
00681   * @param _JSQR_JL_: Sequence length.
00682   * @retval None
00683   */
00684 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_)                                           \
00685   (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
00686
00687 /**
00688   * @brief Set the selected injected channel rank
00689   *        Note: on STM32F1 devices, channel rank position in JSQR register
00690   *              is depending on total number of ranks selected into
00691   *              injected sequencer (ranks sequence starting from 4-JL)
00692   * @param _CHANNELNB_: Channel number.
00693   * @param _RANKNB_: Rank number.
00694   * @param _JSQR_JL_: Sequence length.
00695   * @retval None
00696   */
00697 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_)                       \
00698   ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
00699
00700 /**
00701   * @brief Enable ADC continuous conversion mode.
00702   * @param _CONTINUOUS_MODE_: Continuous mode.
00703   * @retval None
00704   */
00705 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_)                                  \
00706   ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
00707
00708 /**
00709   * @brief Configures the number of discontinuous conversions for the regular group channels.
00710   * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
00711   * @retval None
00712   */
00713 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_)                    \
00714   (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
00715
00716 /**
00717   * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
00718   * @param _SCAN_MODE_: Scan conversion mode.
00719   * @retval None
00720   */
00721 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter   */
00722 /*       is equivalent to ADC_SCAN_ENABLE.                                    */
00723 #define ADC_CR1_SCAN_SET(_SCAN_MODE_)                                          \
00724   (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE)           \
00725    )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE)                                   \
00726   )
00727
00728 /**
00729   * @brief Get the maximum ADC conversion cycles on all channels.
00730   * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
00731   * Approximation of sampling time within 4 ranges, returns the highest value:
00732   *   below 7.5 cycles {1.5 cycle; 7.5 cycles},
00733   *   between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
00734   *   between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
00735   *   equal to 239.5 cycles
00736   * Unit: ADC clock cycles
00737   * @param __HANDLE__: ADC handle
00738   * @retval ADC conversion cycles on all channels
00739   */
00740 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                                     \
00741     (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&                     \
00742        (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ?                     \
00743                                                                                                                  \
00744           (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
00745              (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ?               \
00746                ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5)   \
00747           :                                                                                                      \
00748           ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET)  &&               \
00749              (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) ||               \
00750             ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET)  &&               \
00751              (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ?               \
00752                ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
00753      )
00754
00755 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
00756                                   ((ALIGN) == ADC_DATAALIGN_LEFT)    )
00757
00758 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
00759                                      ((SCAN_MODE) == ADC_SCAN_ENABLE)    )
00760
00761 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)  || \
00762                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  )
00763
00764 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
00765                                  ((CHANNEL) == ADC_CHANNEL_1)           || \
00766                                  ((CHANNEL) == ADC_CHANNEL_2)           || \
00767                                  ((CHANNEL) == ADC_CHANNEL_3)           || \
00768                                  ((CHANNEL) == ADC_CHANNEL_4)           || \
00769                                  ((CHANNEL) == ADC_CHANNEL_5)           || \
00770                                  ((CHANNEL) == ADC_CHANNEL_6)           || \
00771                                  ((CHANNEL) == ADC_CHANNEL_7)           || \
00772                                  ((CHANNEL) == ADC_CHANNEL_8)           || \
00773                                  ((CHANNEL) == ADC_CHANNEL_9)           || \
00774                                  ((CHANNEL) == ADC_CHANNEL_10)          || \
00775                                  ((CHANNEL) == ADC_CHANNEL_11)          || \
00776                                  ((CHANNEL) == ADC_CHANNEL_12)          || \
00777                                  ((CHANNEL) == ADC_CHANNEL_13)          || \
00778                                  ((CHANNEL) == ADC_CHANNEL_14)          || \
00779                                  ((CHANNEL) == ADC_CHANNEL_15)          || \
00780                                  ((CHANNEL) == ADC_CHANNEL_16)          || \
00781                                  ((CHANNEL) == ADC_CHANNEL_17)            )
00782
00783 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
00784                                   ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
00785                                   ((TIME) == ADC_SAMPLETIME_13CYCLES_5)  || \
00786                                   ((TIME) == ADC_SAMPLETIME_28CYCLES_5)  || \
00787                                   ((TIME) == ADC_SAMPLETIME_41CYCLES_5)  || \
00788                                   ((TIME) == ADC_SAMPLETIME_55CYCLES_5)  || \
00789                                   ((TIME) == ADC_SAMPLETIME_71CYCLES_5)  || \
00790                                   ((TIME) == ADC_SAMPLETIME_239CYCLES_5)   )
00791
00792 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
00793                                       ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
00794                                       ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
00795                                       ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
00796                                       ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
00797                                       ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
00798                                       ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
00799                                       ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
00800                                       ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
00801                                       ((CHANNEL) == ADC_REGULAR_RANK_10) || \
00802                                       ((CHANNEL) == ADC_REGULAR_RANK_11) || \
00803                                       ((CHANNEL) == ADC_REGULAR_RANK_12) || \
00804                                       ((CHANNEL) == ADC_REGULAR_RANK_13) || \
00805                                       ((CHANNEL) == ADC_REGULAR_RANK_14) || \
00806                                       ((CHANNEL) == ADC_REGULAR_RANK_15) || \
00807                                       ((CHANNEL) == ADC_REGULAR_RANK_16)   )
00808
00809 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
00810                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
00811                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
00812                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
00813                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
00814                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
00815                                                ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
00816
00817 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP)         || \
00818                                              ((CONVERSION) == ADC_INJECTED_GROUP)        || \
00819                                              ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP)  )
00820
00821 #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
00822
00823
00824 /** @defgroup ADC_range_verification ADC range verification
00825   * For a unique ADC resolution: 12 bits
00826   * @{
00827   */
00828 #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
00829 /**
00830   * @}
00831   */
00832
00833 /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
00834   * @{
00835   */
00836 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
00837 /**
00838   * @}
00839   */
00840
00841 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
00842   * @{
00843   */
00844 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
00845 /**
00846   * @}
00847   */
00848
00849 /**
00850   * @}
00851   */
00852
00853 /* Include ADC HAL Extension module */
00854 #include "stm32f1xx_hal_adc_ex.h"
00855
00856 /* Exported functions --------------------------------------------------------*/
00857 /** @addtogroup ADC_Exported_Functions
00858   * @{
00859   */
00860
00861 /** @addtogroup ADC_Exported_Functions_Group1
00862   * @{
00863   */
00864
00865
00866 /* Initialization and de-initialization functions  **********************************/
00867 HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
00868 HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
00869 void                    HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
00870 void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
00871 /**
00872   * @}
00873   */
00874
00875 /* IO operation functions  *****************************************************/
00876
00877 /** @addtogroup ADC_Exported_Functions_Group2
00878   * @{
00879   */
00880
00881
00882 /* Blocking mode: Polling */
00883 HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
00884 HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
00885 HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
00886 HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
00887
00888 /* Non-blocking mode: Interruption */
00889 HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
00890 HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
00891
00892 /* Non-blocking mode: DMA */
00893 HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
00894 HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
00895
00896 /* ADC retrieve conversion value intended to be used with polling or interruption */
00897 uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
00898
00899 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
00900 void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
00901 void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
00902 void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
00903 void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
00904 void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
00905 /**
00906   * @}
00907   */
00908
00909
00910 /* Peripheral Control functions ***********************************************/
00911 /** @addtogroup ADC_Exported_Functions_Group3
00912   * @{
00913   */
00914 HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
00915 HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
00916 /**
00917   * @}
00918   */
00919
00920
00921 /* Peripheral State functions *************************************************/
00922 /** @addtogroup ADC_Exported_Functions_Group4
00923   * @{
00924   */
00925 uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
00926 uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
00927 /**
00928   * @}
00929   */
00930
00931
00932 /**
00933   * @}
00934   */
00935
00936
00937 /* Internal HAL driver functions **********************************************/
00938 /** @addtogroup ADC_Private_Functions
00939   * @{
00940   */
00941 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
00942 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
00943 void              ADC_StabilizationTime(uint32_t DelayUs);
00944 void              ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
00945 void              ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
00946 void              ADC_DMAError(DMA_HandleTypeDef *hdma);
00947 /**
00948   * @}
00949   */
00950
00951
00952 /**
00953   * @}
00954   */
00955
00956 /**
00957   * @}
00958   */
00959
00960 #ifdef __cplusplus
00961 }
00962 #endif
00963
00964
00965 #endif /* __STM32F1xx_HAL_ADC_H */
00966
00967 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_adc_ex.c Source File

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stm32f1xx_hal_adc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   This file provides firmware functions to manage the following
00008   *          functionalities of the Analog to Digital Convertor (ADC)
00009   *          peripheral:
00010   *           + Operation functions
00011   *             ++ Start, stop, get result of conversions of injected
00012   *                group, using 2 possible modes: polling, interruption.
00013   *             ++ Multimode feature (available on devices with 2 ADCs or more)
00014   *             ++ Calibration (ADC automatic self-calibration)
00015   *           + Control functions
00016   *             ++ Channels configuration on injected group
00017   *          Other functions (generic functions) are available in file
00018   *          "stm32f1xx_hal_adc.c".
00019   *
00020   @verbatim
00021   [..]
00022   (@) Sections "ADC peripheral features" and "How to use this driver" are
00023       available in file of generic functions "stm32f1xx_hal_adc.c".
00024   [..]
00025   @endverbatim
00026   ******************************************************************************
00027   * @attention
00028   *
00029   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00030   *
00031   * Redistribution and use in source and binary forms, with or without modification,
00032   * are permitted provided that the following conditions are met:
00033   *   1. Redistributions of source code must retain the above copyright notice,
00034   *      this list of conditions and the following disclaimer.
00035   *   2. Redistributions in binary form must reproduce the above copyright notice,
00036   *      this list of conditions and the following disclaimer in the documentation
00037   *      and/or other materials provided with the distribution.
00038   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00039   *      may be used to endorse or promote products derived from this software
00040   *      without specific prior written permission.
00041   *
00042   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00043   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00044   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00045   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00046   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00047   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00048   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00049   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00050   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00051   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00052   *
00053   ******************************************************************************
00054   */
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32f1xx_hal.h"
00058
00059 /** @addtogroup STM32F1xx_HAL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup ADCEx ADCEx
00064   * @brief ADC Extension HAL module driver
00065   * @{
00066   */
00067
00068 #ifdef HAL_ADC_MODULE_ENABLED
00069
00070 /* Private typedef -----------------------------------------------------------*/
00071 /* Private define ------------------------------------------------------------*/
00072 /** @defgroup ADCEx_Private_Constants ADCEx Private Constants
00073   * @{
00074   */
00075
00076   /* Delay for ADC calibration:                                               */
00077   /* Hardware prerequisite before starting a calibration: the ADC must have   */
00078   /* been in power-on state for at least two ADC clock cycles.                */
00079   /* Unit: ADC clock cycles                                                   */
00080   #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES       2U
00081
00082   /* Timeout value for ADC calibration                                        */
00083   /* Value defined to be higher than worst cases: low clocks freq,            */
00084   /* maximum prescaler.                                                       */
00085   /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
00086   /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits.    */
00087   /* Unit: ms                                                                 */
00088   #define ADC_CALIBRATION_TIMEOUT          10U
00089
00090   /* Delay for temperature sensor stabilization time.                         */
00091   /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
00092   /* Unit: us                                                                 */
00093   #define ADC_TEMPSENSOR_DELAY_US         10U
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Private macro -------------------------------------------------------------*/
00100 /* Private variables ---------------------------------------------------------*/
00101 /* Private function prototypes -----------------------------------------------*/
00102 /* Private functions ---------------------------------------------------------*/
00103
00104 /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
00105   * @{
00106   */
00107
00108 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions
00109  *  @brief    Extended Extended Input and Output operation functions
00110  *
00111 @verbatim
00112  ===============================================================================
00113                       ##### IO operation functions #####
00114  ===============================================================================
00115     [..]  This section provides functions allowing to:
00116       (+) Start conversion of injected group.
00117       (+) Stop conversion of injected group.
00118       (+) Poll for conversion complete on injected group.
00119       (+) Get result of injected channel conversion.
00120       (+) Start conversion of injected group and enable interruptions.
00121       (+) Stop conversion of injected group and disable interruptions.
00122
00123       (+) Start multimode and enable DMA transfer.
00124       (+) Stop multimode and disable ADC DMA transfer.
00125       (+) Get result of multimode conversion.
00126
00127       (+) Perform the ADC self-calibration for single or differential ending.
00128       (+) Get calibration factors for single or differential ending.
00129       (+) Set calibration factors for single or differential ending.
00130
00131 @endverbatim
00132   * @{
00133   */
00134
00135 /**
00136   * @brief  Perform an ADC automatic self-calibration
00137   *         Calibration prerequisite: ADC must be disabled (execute this
00138   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
00139   *         During calibration process, ADC is enabled. ADC is let enabled at
00140   *         the completion of this function.
00141   * @param  hadc: ADC handle
00142   * @retval HAL status
00143   */
00144 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
00145 {
00146   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00147   uint32_t tickstart;
00148   __IO uint32_t wait_loop_index = 0U;
00149
00150   /* Check the parameters */
00151   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00152
00153   /* Process locked */
00154   __HAL_LOCK(hadc);
00155
00156   /* 1. Calibration prerequisite:                                             */
00157   /*    - ADC must be disabled for at least two ADC clock cycles in disable   */
00158   /*      mode before ADC enable                                              */
00159   /* Stop potential conversion on going, on regular and injected groups       */
00160   /* Disable ADC peripheral */
00161   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
00162
00163   /* Check if ADC is effectively disabled */
00164   if (tmp_hal_status == HAL_OK)
00165   {
00166     /* Set ADC state */
00167     ADC_STATE_CLR_SET(hadc->State,
00168                       HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00169                       HAL_ADC_STATE_BUSY_INTERNAL);
00170
00171     /* Hardware prerequisite: delay before starting the calibration.          */
00172     /*  - Computation of CPU clock cycles corresponding to ADC clock cycles.  */
00173     /*  - Wait for the expected ADC clock cycles delay */
00174     wait_loop_index = ((SystemCoreClock
00175                         / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
00176                        * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES        );
00177
00178     while(wait_loop_index != 0U)
00179     {
00180       wait_loop_index--;
00181     }
00182
00183     /* 2. Enable the ADC peripheral */
00184     ADC_Enable(hadc);
00185
00186     /* 3. Resets ADC calibration registers */
00187     SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
00188
00189     tickstart = HAL_GetTick();
00190
00191     /* Wait for calibration reset completion */
00192     while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
00193     {
00194       if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
00195       {
00196         /* Update ADC state machine to error */
00197         ADC_STATE_CLR_SET(hadc->State,
00198                           HAL_ADC_STATE_BUSY_INTERNAL,
00199                           HAL_ADC_STATE_ERROR_INTERNAL);
00200
00201         /* Process unlocked */
00202         __HAL_UNLOCK(hadc);
00203
00204         return HAL_ERROR;
00205       }
00206     }
00207
00208
00209     /* 4. Start ADC calibration */
00210     SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
00211
00212     tickstart = HAL_GetTick();
00213
00214     /* Wait for calibration completion */
00215     while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
00216     {
00217       if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
00218       {
00219         /* Update ADC state machine to error */
00220         ADC_STATE_CLR_SET(hadc->State,
00221                           HAL_ADC_STATE_BUSY_INTERNAL,
00222                           HAL_ADC_STATE_ERROR_INTERNAL);
00223
00224         /* Process unlocked */
00225         __HAL_UNLOCK(hadc);
00226
00227         return HAL_ERROR;
00228       }
00229     }
00230
00231     /* Set ADC state */
00232     ADC_STATE_CLR_SET(hadc->State,
00233                       HAL_ADC_STATE_BUSY_INTERNAL,
00234                       HAL_ADC_STATE_READY);
00235   }
00236
00237   /* Process unlocked */
00238   __HAL_UNLOCK(hadc);
00239
00240   /* Return function status */
00241   return tmp_hal_status;
00242 }
00243
00244 /**
00245   * @brief  Enables ADC, starts conversion of injected group.
00246   *         Interruptions enabled in this function: None.
00247   * @param  hadc: ADC handle
00248   * @retval HAL status
00249   */
00250 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
00251 {
00252   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00253
00254   /* Check the parameters */
00255   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00256
00257   /* Process locked */
00258   __HAL_LOCK(hadc);
00259
00260   /* Enable the ADC peripheral */
00261   tmp_hal_status = ADC_Enable(hadc);
00262
00263   /* Start conversion if ADC is effectively enabled */
00264   if (tmp_hal_status == HAL_OK)
00265   {
00266     /* Set ADC state                                                          */
00267     /* - Clear state bitfield related to injected group conversion results    */
00268     /* - Set state bitfield related to injected operation                     */
00269     ADC_STATE_CLR_SET(hadc->State,
00270                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00271                       HAL_ADC_STATE_INJ_BUSY);
00272
00273     /* Case of independent mode or multimode (for devices with several ADCs): */
00274     /* Set multimode state.                                                   */
00275     if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00276     {
00277       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00278     }
00279     else
00280     {
00281       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00282     }
00283
00284     /* Check if a regular conversion is ongoing */
00285     /* Note: On this device, there is no ADC error code fields related to     */
00286     /*       conversions on group injected only. In case of conversion on     */
00287     /*       going on group regular, no error code is reset.                  */
00288     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00289     {
00290       /* Reset ADC all error code fields */
00291       ADC_CLEAR_ERRORCODE(hadc);
00292     }
00293
00294     /* Process unlocked */
00295     /* Unlock before starting ADC conversions: in case of potential           */
00296     /* interruption, to let the process to ADC IRQ Handler.                   */
00297     __HAL_UNLOCK(hadc);
00298
00299     /* Clear injected group conversion flag */
00300     /* (To ensure of no unknown state from potential previous ADC operations) */
00301     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00302
00303     /* Enable conversion of injected group.                                   */
00304     /* If software start has been selected, conversion starts immediately.    */
00305     /* If external trigger has been selected, conversion will start at next   */
00306     /* trigger event.                                                         */
00307     /* If automatic injected conversion is enabled, conversion will start     */
00308     /* after next regular group conversion.                                   */
00309     /* Case of multimode enabled (for devices with several ADCs): if ADC is   */
00310     /* slave, ADC is enabled only (conversion is not started). If ADC is      */
00311     /* master, ADC is enabled and conversion is started.                      */
00312     if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
00313     {
00314       if (ADC_IS_SOFTWARE_START_INJECTED(hadc)     &&
00315           ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
00316       {
00317         /* Start ADC conversion on injected group with SW start */
00318         SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
00319       }
00320       else
00321       {
00322         /* Start ADC conversion on injected group with external trigger */
00323         SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
00324       }
00325     }
00326   }
00327   else
00328   {
00329     /* Process unlocked */
00330     __HAL_UNLOCK(hadc);
00331   }
00332
00333   /* Return function status */
00334   return tmp_hal_status;
00335 }
00336
00337 /**
00338   * @brief  Stop conversion of injected channels. Disable ADC peripheral if
00339   *         no regular conversion is on going.
00340   * @note   If ADC must be disabled and if conversion is on going on
00341   *         regular group, function HAL_ADC_Stop must be used to stop both
00342   *         injected and regular groups, and disable the ADC.
00343   * @note   If injected group mode auto-injection is enabled,
00344   *         function HAL_ADC_Stop must be used.
00345   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
00346   * @param  hadc: ADC handle
00347   * @retval None
00348   */
00349 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
00350 {
00351   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00352
00353   /* Check the parameters */
00354   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00355
00356   /* Process locked */
00357   __HAL_LOCK(hadc);
00358
00359   /* Stop potential conversion and disable ADC peripheral                     */
00360   /* Conditioned to:                                                          */
00361   /* - No conversion on the other group (regular group) is intended to        */
00362   /*   continue (injected and regular groups stop conversion and ADC disable  */
00363   /*   are common)                                                            */
00364   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
00365   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
00366      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
00367   {
00368     /* Stop potential conversion on going, on regular and injected groups */
00369     /* Disable ADC peripheral */
00370     tmp_hal_status = ADC_ConversionStop_Disable(hadc);
00371
00372     /* Check if ADC is effectively disabled */
00373     if (tmp_hal_status == HAL_OK)
00374     {
00375       /* Set ADC state */
00376       ADC_STATE_CLR_SET(hadc->State,
00377                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00378                         HAL_ADC_STATE_READY);
00379     }
00380   }
00381   else
00382   {
00383     /* Update ADC state machine to error */
00384     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00385
00386     tmp_hal_status = HAL_ERROR;
00387   }
00388
00389   /* Process unlocked */
00390   __HAL_UNLOCK(hadc);
00391
00392   /* Return function status */
00393   return tmp_hal_status;
00394 }
00395
00396 /**
00397   * @brief  Wait for injected group conversion to be completed.
00398   * @param  hadc: ADC handle
00399   * @param  Timeout: Timeout value in millisecond.
00400   * @retval HAL status
00401   */
00402 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00403 {
00404   uint32_t tickstart;
00405
00406   /* Variables for polling in case of scan mode enabled and polling for each  */
00407   /* conversion.                                                              */
00408   __IO uint32_t Conversion_Timeout_CPU_cycles = 0U;
00409   uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
00410
00411   /* Check the parameters */
00412   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00413
00414   /* Get timeout */
00415   tickstart = HAL_GetTick();
00416
00417   /* Polling for end of conversion: differentiation if single/sequence        */
00418   /* conversion.                                                              */
00419   /* For injected group, flag JEOC is set only at the end of the sequence,    */
00420   /* not for each conversion within the sequence.                             */
00421   /*  - If single conversion for injected group (scan mode disabled or        */
00422   /*    InjectedNbrOfConversion ==1), flag JEOC is used to determine the      */
00423   /*    conversion completion.                                                */
00424   /*  - If sequence conversion for injected group (scan mode enabled and      */
00425   /*    InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
00426   /*    sequence.                                                             */
00427   /*    To poll for each conversion, the maximum conversion time is computed  */
00428   /*    from ADC conversion time (selected sampling time + conversion time of */
00429   /*    12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on    */
00430   /*    settings, conversion time range can be from 28 to 32256 CPU cycles).  */
00431   /*    As flag JEOC is not set after each conversion, no timeout status can  */
00432   /*    be set.                                                               */
00433   if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
00434   {
00435     /* Wait until End of Conversion flag is raised */
00436     while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
00437     {
00438       /* Check if timeout is disabled (set to infinite wait) */
00439       if(Timeout != HAL_MAX_DELAY)
00440       {
00441         if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
00442         {
00443           /* Update ADC state machine to timeout */
00444           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00445
00446           /* Process unlocked */
00447           __HAL_UNLOCK(hadc);
00448
00449           return HAL_TIMEOUT;
00450         }
00451       }
00452     }
00453   }
00454   else
00455   {
00456     /* Replace polling by wait for maximum conversion time */
00457     /*  - Computation of CPU clock cycles corresponding to ADC clock cycles   */
00458     /*    and ADC maximum conversion cycles on all channels.                  */
00459     /*  - Wait for the expected ADC clock cycles delay                        */
00460     Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
00461                                           / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
00462                                          * ADC_CONVCYCLES_MAX_RANGE(hadc)                 );
00463
00464     while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
00465     {
00466       /* Check if timeout is disabled (set to infinite wait) */
00467       if(Timeout != HAL_MAX_DELAY)
00468       {
00469         if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
00470         {
00471           /* Update ADC state machine to timeout */
00472           SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00473
00474           /* Process unlocked */
00475           __HAL_UNLOCK(hadc);
00476
00477           return HAL_TIMEOUT;
00478         }
00479       }
00480       Conversion_Timeout_CPU_cycles ++;
00481     }
00482   }
00483
00484   /* Clear injected group conversion flag */
00485   /* Note: On STM32F1 ADC, clear regular conversion flag raised               */
00486   /* simultaneously.                                                          */
00487   __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
00488
00489   /* Update ADC state machine */
00490   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
00491
00492   /* Determine whether any further conversion upcoming on group injected      */
00493   /* by external trigger or by automatic injected conversion                  */
00494   /* from group regular.                                                      */
00495   if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                     ||
00496      (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
00497      (ADC_IS_SOFTWARE_START_REGULAR(hadc)        &&
00498       (hadc->Init.ContinuousConvMode == DISABLE)   )        )   )
00499   {
00500     /* Set ADC state */
00501     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
00502
00503     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00504     {
00505       SET_BIT(hadc->State, HAL_ADC_STATE_READY);
00506     }
00507   }
00508
00509   /* Return ADC state */
00510   return HAL_OK;
00511 }
00512
00513 /**
00514   * @brief  Enables ADC, starts conversion of injected group with interruption.
00515   *          - JEOC (end of conversion of injected group)
00516   *         Each of these interruptions has its dedicated callback function.
00517   * @param  hadc: ADC handle
00518   * @retval HAL status.
00519   */
00520 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
00521 {
00522   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00523
00524   /* Check the parameters */
00525   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00526
00527   /* Process locked */
00528   __HAL_LOCK(hadc);
00529
00530   /* Enable the ADC peripheral */
00531   tmp_hal_status = ADC_Enable(hadc);
00532
00533   /* Start conversion if ADC is effectively enabled */
00534   if (tmp_hal_status == HAL_OK)
00535   {
00536     /* Set ADC state                                                          */
00537     /* - Clear state bitfield related to injected group conversion results    */
00538     /* - Set state bitfield related to injected operation                     */
00539     ADC_STATE_CLR_SET(hadc->State,
00540                       HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
00541                       HAL_ADC_STATE_INJ_BUSY);
00542
00543     /* Case of independent mode or multimode (for devices with several ADCs): */
00544     /* Set multimode state.                                                   */
00545     if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00546     {
00547       CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00548     }
00549     else
00550     {
00551       SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00552     }
00553
00554     /* Check if a regular conversion is ongoing */
00555     /* Note: On this device, there is no ADC error code fields related to     */
00556     /*       conversions on group injected only. In case of conversion on     */
00557     /*       going on group regular, no error code is reset.                  */
00558     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00559     {
00560       /* Reset ADC all error code fields */
00561       ADC_CLEAR_ERRORCODE(hadc);
00562     }
00563
00564     /* Process unlocked */
00565     /* Unlock before starting ADC conversions: in case of potential           */
00566     /* interruption, to let the process to ADC IRQ Handler.                   */
00567     __HAL_UNLOCK(hadc);
00568
00569     /* Clear injected group conversion flag */
00570     /* (To ensure of no unknown state from potential previous ADC operations) */
00571     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
00572
00573     /* Enable end of conversion interrupt for injected channels */
00574     __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
00575
00576     /* Start conversion of injected group if software start has been selected */
00577     /* and if automatic injected conversion is disabled.                      */
00578     /* If external trigger has been selected, conversion will start at next   */
00579     /* trigger event.                                                         */
00580     /* If automatic injected conversion is enabled, conversion will start     */
00581     /* after next regular group conversion.                                   */
00582     if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
00583     {
00584       if (ADC_IS_SOFTWARE_START_INJECTED(hadc)     &&
00585           ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)  )
00586       {
00587         /* Start ADC conversion on injected group with SW start */
00588         SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
00589       }
00590       else
00591       {
00592         /* Start ADC conversion on injected group with external trigger */
00593         SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
00594       }
00595     }
00596   }
00597   else
00598   {
00599     /* Process unlocked */
00600     __HAL_UNLOCK(hadc);
00601   }
00602
00603   /* Return function status */
00604   return tmp_hal_status;
00605 }
00606
00607 /**
00608   * @brief  Stop conversion of injected channels, disable interruption of
00609   *         end-of-conversion. Disable ADC peripheral if no regular conversion
00610   *         is on going.
00611   * @note   If ADC must be disabled and if conversion is on going on
00612   *         regular group, function HAL_ADC_Stop must be used to stop both
00613   *         injected and regular groups, and disable the ADC.
00614   * @note   If injected group mode auto-injection is enabled,
00615   *         function HAL_ADC_Stop must be used.
00616   * @param  hadc: ADC handle
00617   * @retval None
00618   */
00619 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
00620 {
00621   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00622
00623   /* Check the parameters */
00624   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00625
00626   /* Process locked */
00627   __HAL_LOCK(hadc);
00628
00629   /* Stop potential conversion and disable ADC peripheral                     */
00630   /* Conditioned to:                                                          */
00631   /* - No conversion on the other group (regular group) is intended to        */
00632   /*   continue (injected and regular groups stop conversion and ADC disable  */
00633   /*   are common)                                                            */
00634   /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
00635   if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&
00636      HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
00637   {
00638     /* Stop potential conversion on going, on regular and injected groups */
00639     /* Disable ADC peripheral */
00640     tmp_hal_status = ADC_ConversionStop_Disable(hadc);
00641
00642     /* Check if ADC is effectively disabled */
00643     if (tmp_hal_status == HAL_OK)
00644     {
00645       /* Disable ADC end of conversion interrupt for injected channels */
00646       __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00647
00648       /* Set ADC state */
00649       ADC_STATE_CLR_SET(hadc->State,
00650                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00651                         HAL_ADC_STATE_READY);
00652     }
00653   }
00654   else
00655   {
00656     /* Update ADC state machine to error */
00657     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00658
00659     tmp_hal_status = HAL_ERROR;
00660   }
00661
00662   /* Process unlocked */
00663   __HAL_UNLOCK(hadc);
00664
00665   /* Return function status */
00666   return tmp_hal_status;
00667 }
00668
00669 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00670 /**
00671   * @brief  Enables ADC, starts conversion of regular group and transfers result
00672   *         through DMA.
00673   *         Multimode must have been previously configured using
00674   *         HAL_ADCEx_MultiModeConfigChannel() function.
00675   *         Interruptions enabled in this function:
00676   *          - DMA transfer complete
00677   *          - DMA half transfer
00678   *         Each of these interruptions has its dedicated callback function.
00679   * @note:  On STM32F1 devices, ADC slave regular group must be configured
00680   *         with conversion trigger ADC_SOFTWARE_START.
00681   * @note:  ADC slave can be enabled preliminarily using single-mode
00682   *         HAL_ADC_Start() function.
00683   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
00684   * @param  pData: The destination Buffer address.
00685   * @param  Length: The length of data to be transferred from ADC peripheral to memory.
00686   * @retval None
00687   */
00688 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
00689 {
00690   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00691   ADC_HandleTypeDef tmphadcSlave;
00692
00693   /* Check the parameters */
00694   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
00695   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00696
00697   /* Process locked */
00698   __HAL_LOCK(hadc);
00699
00700   /* Set a temporary handle of the ADC slave associated to the ADC master     */
00701   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
00702
00703   /* On STM32F1 devices, ADC slave regular group must be configured with      */
00704   /* conversion trigger ADC_SOFTWARE_START.                                   */
00705   /* Note: External trigger of ADC slave must be enabled, it is already done  */
00706   /*       into function "HAL_ADC_Init()".                                    */
00707   if ((tmphadcSlave.Instance == NULL)                 ||
00708       (! ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave))  )
00709   {
00710     /* Update ADC state machine to error */
00711     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00712
00713     /* Process unlocked */
00714     __HAL_UNLOCK(hadc);
00715
00716     return HAL_ERROR;
00717   }
00718
00719   /* Enable the ADC peripherals: master and slave (in case if not already     */
00720   /* enabled previously)                                                      */
00721   tmp_hal_status = ADC_Enable(hadc);
00722   if (tmp_hal_status == HAL_OK)
00723   {
00724     tmp_hal_status = ADC_Enable(&tmphadcSlave);
00725   }
00726
00727   /* Start conversion if all ADCs of multimode are effectively enabled */
00728   if (tmp_hal_status == HAL_OK)
00729   {
00730     /* Set ADC state (ADC master)                                             */
00731     /* - Clear state bitfield related to regular group conversion results     */
00732     /* - Set state bitfield related to regular operation                      */
00733     ADC_STATE_CLR_SET(hadc->State,
00734                       HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE,
00735                       HAL_ADC_STATE_REG_BUSY);
00736
00737     /* If conversions on group regular are also triggering group injected,    */
00738     /* update ADC state.                                                      */
00739     if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
00740     {
00741       ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00742     }
00743
00744     /* Process unlocked */
00745     /* Unlock before starting ADC conversions: in case of potential           */
00746     /* interruption, to let the process to ADC IRQ Handler.                   */
00747     __HAL_UNLOCK(hadc);
00748
00749     /* Set ADC error code to none */
00750     ADC_CLEAR_ERRORCODE(hadc);
00751
00752
00753     /* Set the DMA transfer complete callback */
00754     hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
00755
00756     /* Set the DMA half transfer complete callback */
00757     hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
00758
00759     /* Set the DMA error callback */
00760     hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
00761
00762
00763     /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
00764     /* start (in case of SW start):                                           */
00765
00766     /* Clear regular group conversion flag and overrun flag */
00767     /* (To ensure of no unknown state from potential previous ADC operations) */
00768     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00769
00770     /* Enable ADC DMA mode of ADC master */
00771     SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
00772
00773     /* Start the DMA channel */
00774     HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
00775
00776     /* Start conversion of regular group if software start has been selected. */
00777     /* If external trigger has been selected, conversion will start at next   */
00778     /* trigger event.                                                         */
00779     /* Note: Alternate trigger for single conversion could be to force an     */
00780     /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
00781     if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
00782     {
00783       /* Start ADC conversion on regular group with SW start */
00784       SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
00785     }
00786     else
00787     {
00788       /* Start ADC conversion on regular group with external trigger */
00789       SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
00790     }
00791   }
00792   else
00793   {
00794     /* Process unlocked */
00795     __HAL_UNLOCK(hadc);
00796   }
00797
00798   /* Return function status */
00799   return tmp_hal_status;
00800 }
00801
00802 /**
00803   * @brief  Stop ADC conversion of regular group (and injected channels in
00804   *         case of auto_injection mode), disable ADC DMA transfer, disable
00805   *         ADC peripheral.
00806   * @note   Multimode is kept enabled after this function. To disable multimode
00807   *         (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be
00808   *         reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
00809   * @note   In case of DMA configured in circular mode, function
00810   *         HAL_ADC_Stop_DMA must be called after this function with handle of
00811   *         ADC slave, to properly disable the DMA channel.
00812   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
00813   * @retval None
00814   */
00815 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
00816 {
00817   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
00818   ADC_HandleTypeDef tmphadcSlave;
00819
00820   /* Check the parameters */
00821   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
00822
00823   /* Process locked */
00824   __HAL_LOCK(hadc);
00825
00826
00827   /* Stop potential conversion on going, on regular and injected groups */
00828   /* Disable ADC master peripheral */
00829   tmp_hal_status = ADC_ConversionStop_Disable(hadc);
00830
00831   /* Check if ADC is effectively disabled */
00832   if (tmp_hal_status == HAL_OK)
00833   {
00834     /* Set a temporary handle of the ADC slave associated to the ADC master   */
00835     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
00836
00837     if (tmphadcSlave.Instance == NULL)
00838     {
00839       /* Update ADC state machine to error */
00840       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
00841
00842       /* Process unlocked */
00843       __HAL_UNLOCK(hadc);
00844
00845       return HAL_ERROR;
00846     }
00847     else
00848     {
00849       /* Disable ADC slave peripheral */
00850       tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
00851
00852       /* Check if ADC is effectively disabled */
00853       if (tmp_hal_status != HAL_OK)
00854       {
00855         /* Update ADC state machine to error */
00856         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00857
00858         /* Process unlocked */
00859         __HAL_UNLOCK(hadc);
00860
00861         return HAL_ERROR;
00862       }
00863     }
00864
00865     /* Disable ADC DMA mode */
00866     CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
00867
00868     /* Reset configuration of ADC DMA continuous request for dual mode */
00869     CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD);
00870
00871     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
00872     /* while DMA transfer is on going)                                        */
00873     tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
00874
00875
00876     /* Check if DMA channel effectively disabled */
00877     if (tmp_hal_status == HAL_OK)
00878     {
00879       /* Change ADC state (ADC master) */
00880       ADC_STATE_CLR_SET(hadc->State,
00881                         HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
00882                         HAL_ADC_STATE_READY);
00883     }
00884     else
00885     {
00886       /* Update ADC state machine to error */
00887       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
00888     }
00889   }
00890
00891   /* Process unlocked */
00892   __HAL_UNLOCK(hadc);
00893
00894   /* Return function status */
00895   return tmp_hal_status;
00896 }
00897 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00898
00899 /**
00900   * @brief  Get ADC injected group conversion result.
00901   * @note   Reading register JDRx automatically clears ADC flag JEOC
00902   *         (ADC group injected end of unitary conversion).
00903   * @note   This function does not clear ADC flag JEOS
00904   *         (ADC group injected end of sequence conversion)
00905   *         Occurrence of flag JEOS rising:
00906   *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
00907   *            to flag JEOC.
00908   *          - If sequencer is composed of several ranks, during the scan
00909   *            sequence flag JEOC only is raised, at the end of the scan sequence
00910   *            both flags JEOC and EOS are raised.
00911   *         Flag JEOS must not be cleared by this function because
00912   *         it would not be compliant with low power features
00913   *         (feature low power auto-wait, not available on all STM32 families).
00914   *         To clear this flag, either use function:
00915   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
00916   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
00917   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
00918   * @param  hadc: ADC handle
00919   * @param  InjectedRank: the converted ADC injected rank.
00920   *          This parameter can be one of the following values:
00921   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
00922   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
00923   *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
00924   *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
00925   * @retval ADC group injected conversion data
00926   */
00927 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
00928 {
00929   uint32_t tmp_jdr = 0U;
00930
00931   /* Check the parameters */
00932   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00933   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
00934
00935   /* Get ADC converted value */
00936   switch(InjectedRank)
00937   {
00938     case ADC_INJECTED_RANK_4:
00939       tmp_jdr = hadc->Instance->JDR4;
00940       break;
00941     case ADC_INJECTED_RANK_3:
00942       tmp_jdr = hadc->Instance->JDR3;
00943       break;
00944     case ADC_INJECTED_RANK_2:
00945       tmp_jdr = hadc->Instance->JDR2;
00946       break;
00947     case ADC_INJECTED_RANK_1:
00948     default:
00949       tmp_jdr = hadc->Instance->JDR1;
00950       break;
00951   }
00952
00953   /* Return ADC converted value */
00954   return tmp_jdr;
00955 }
00956
00957 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00958 /**
00959   * @brief  Returns the last ADC Master&Slave regular conversions results data
00960   *         in the selected multi mode.
00961   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
00962   * @retval The converted data value.
00963   */
00964 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
00965 {
00966   uint32_t tmpDR = 0U;
00967
00968   /* Check the parameters */
00969   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
00970
00971   /* Check the parameters */
00972   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00973
00974   /* Note: EOC flag is not cleared here by software because automatically     */
00975   /*       cleared by hardware when reading register DR.                      */
00976
00977   /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions      */
00978   /* only if ADC1 DMA mode is enabled.                                        */
00979   tmpDR = hadc->Instance->DR;
00980
00981   if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA))
00982   {
00983     tmpDR |= (ADC2->DR << 16U);
00984   }
00985
00986   /* Return ADC converted value */
00987   return tmpDR;
00988 }
00989 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00990
00991 /**
00992   * @brief  Injected conversion complete callback in non blocking mode
00993   * @param  hadc: ADC handle
00994   * @retval None
00995   */
00996 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
00997 {
00998   /* Prevent unused argument(s) compilation warning */
00999   UNUSED(hadc);
01000   /* NOTE : This function Should not be modified, when the callback is needed,
01001             the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
01002   */
01003 }
01004
01005 /**
01006   * @}
01007   */
01008
01009 /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
01010   * @brief    Extended Peripheral Control functions
01011   *
01012 @verbatim
01013  ===============================================================================
01014              ##### Peripheral Control functions #####
01015  ===============================================================================
01016     [..]  This section provides functions allowing to:
01017       (+) Configure channels on injected group
01018       (+) Configure multimode
01019
01020 @endverbatim
01021   * @{
01022   */
01023
01024 /**
01025   * @brief  Configures the ADC injected group and the selected channel to be
01026   *         linked to the injected group.
01027   * @note   Possibility to update parameters on the fly:
01028   *         This function initializes injected group, following calls to this
01029   *         function can be used to reconfigure some parameters of structure
01030   *         "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
01031   *         The setting of these parameters is conditioned to ADC state:
01032   *         this function must be called when ADC is not under conversion.
01033   * @param  hadc: ADC handle
01034   * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
01035   *         injected group.
01036   * @retval None
01037   */
01038 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
01039 {
01040   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01041   __IO uint32_t wait_loop_index = 0U;
01042
01043   /* Check the parameters */
01044   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01045   assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
01046   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
01047   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
01048   assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
01049   assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
01050
01051   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
01052   {
01053     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
01054     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
01055     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
01056   }
01057
01058   /* Process locked */
01059   __HAL_LOCK(hadc);
01060
01061   /* Configuration of injected group sequencer:                               */
01062   /* - if scan mode is disabled, injected channels sequence length is set to  */
01063   /*   0x00: 1 channel converted (channel on regular rank 1)                  */
01064   /*   Parameter "InjectedNbrOfConversion" is discarded.                      */
01065   /*   Note: Scan mode is present by hardware on this device and, if          */
01066   /*   disabled, discards automatically nb of conversions. Anyway, nb of      */
01067   /*   conversions is forced to 0x00 for alignment over all STM32 devices.    */
01068   /* - if scan mode is enabled, injected channels sequence length is set to   */
01069   /*   parameter "InjectedNbrOfConversion".                                   */
01070   if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
01071   {
01072     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
01073     {
01074       /* Clear the old SQx bits for all injected ranks */
01075       MODIFY_REG(hadc->Instance->JSQR                             ,
01076                  ADC_JSQR_JL   |
01077                  ADC_JSQR_JSQ4 |
01078                  ADC_JSQR_JSQ3 |
01079                  ADC_JSQR_JSQ2 |
01080                  ADC_JSQR_JSQ1                                    ,
01081                  ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
01082                                   ADC_INJECTED_RANK_1,
01083                                   0x01U));
01084     }
01085     /* If another injected rank than rank1 was intended to be set, and could  */
01086     /* not due to ScanConvMode disabled, error is reported.                   */
01087     else
01088     {
01089       /* Update ADC state machine to error */
01090       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01091
01092       tmp_hal_status = HAL_ERROR;
01093     }
01094   }
01095   else
01096   {
01097     /* Since injected channels rank conv. order depends on total number of   */
01098     /* injected conversions, selected rank must be below or equal to total   */
01099     /* number of injected conversions to be updated.                         */
01100     if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
01101     {
01102       /* Clear the old SQx bits for the selected rank */
01103       /* Set the SQx bits for the selected rank */
01104       MODIFY_REG(hadc->Instance->JSQR                                         ,
01105
01106                  ADC_JSQR_JL                                               |
01107                  ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
01108                                   sConfigInjected->InjectedRank,
01109                                   sConfigInjected->InjectedNbrOfConversion)   ,
01110
01111                  ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
01112                  ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
01113                                   sConfigInjected->InjectedRank,
01114                                   sConfigInjected->InjectedNbrOfConversion)    );
01115     }
01116     else
01117     {
01118       /* Clear the old SQx bits for the selected rank */
01119       MODIFY_REG(hadc->Instance->JSQR                                       ,
01120
01121                  ADC_JSQR_JL                                               |
01122                  ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
01123                                   sConfigInjected->InjectedRank,
01124                                   sConfigInjected->InjectedNbrOfConversion) ,
01125
01126                  0x00000000U);
01127     }
01128   }
01129
01130   /* Configuration of injected group                                          */
01131   /* Parameters update conditioned to ADC state:                              */
01132   /* Parameters that can be updated only when ADC is disabled:                */
01133   /*  - external trigger to start conversion                                  */
01134   /* Parameters update not conditioned to ADC state:                          */
01135   /*  - Automatic injected conversion                                         */
01136   /*  - Injected discontinuous mode                                           */
01137   /* Note: In case of ADC already enabled, caution to not launch an unwanted  */
01138   /*       conversion while modifying register CR2 by writing 1 to bit ADON.  */
01139   if (ADC_IS_ENABLE(hadc) == RESET)
01140   {
01141     MODIFY_REG(hadc->Instance->CR2                                           ,
01142                ADC_CR2_JEXTSEL |
01143                ADC_CR2_ADON                                                  ,
01144                ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) );
01145   }
01146
01147
01148   /* Configuration of injected group                                          */
01149   /*  - Automatic injected conversion                                         */
01150   /*  - Injected discontinuous mode                                           */
01151
01152     /* Automatic injected conversion can be enabled if injected group         */
01153     /* external triggers are disabled.                                        */
01154     if (sConfigInjected->AutoInjectedConv == ENABLE)
01155     {
01156       if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
01157       {
01158         SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
01159       }
01160       else
01161       {
01162         /* Update ADC state machine to error */
01163         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01164
01165         tmp_hal_status = HAL_ERROR;
01166       }
01167     }
01168
01169     /* Injected discontinuous can be enabled only if auto-injected mode is    */
01170     /* disabled.                                                              */
01171     if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
01172     {
01173       if (sConfigInjected->AutoInjectedConv == DISABLE)
01174       {
01175         SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
01176       }
01177       else
01178       {
01179         /* Update ADC state machine to error */
01180         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01181
01182         tmp_hal_status = HAL_ERROR;
01183       }
01184     }
01185
01186
01187   /* InjectedChannel sampling time configuration */
01188   /* For channels 10 to 17 */
01189   if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
01190   {
01191     MODIFY_REG(hadc->Instance->SMPR1                                                             ,
01192                ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel)                      ,
01193                ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
01194   }
01195   else /* For channels 0 to 9 */
01196   {
01197     MODIFY_REG(hadc->Instance->SMPR2                                                             ,
01198                ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel)                       ,
01199                ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
01200   }
01201
01202   /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor  */
01203   /* and VREFINT measurement path.                                            */
01204   if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
01205       (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
01206   {
01207     SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
01208   }
01209
01210
01211   /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
01212   switch(sConfigInjected->InjectedRank)
01213   {
01214     case 1:
01215       /* Set injected channel 1 offset */
01216       MODIFY_REG(hadc->Instance->JOFR1,
01217                  ADC_JOFR1_JOFFSET1,
01218                  sConfigInjected->InjectedOffset);
01219       break;
01220     case 2:
01221       /* Set injected channel 2 offset */
01222       MODIFY_REG(hadc->Instance->JOFR2,
01223                  ADC_JOFR2_JOFFSET2,
01224                  sConfigInjected->InjectedOffset);
01225       break;
01226     case 3:
01227       /* Set injected channel 3 offset */
01228       MODIFY_REG(hadc->Instance->JOFR3,
01229                  ADC_JOFR3_JOFFSET3,
01230                  sConfigInjected->InjectedOffset);
01231       break;
01232     case 4:
01233     default:
01234       MODIFY_REG(hadc->Instance->JOFR4,
01235                  ADC_JOFR4_JOFFSET4,
01236                  sConfigInjected->InjectedOffset);
01237       break;
01238   }
01239
01240   /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
01241   /* and VREFINT measurement path.                                            */
01242   if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
01243       (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
01244   {
01245     /* For STM32F1 devices with several ADC: Only ADC1 can access internal    */
01246     /* measurement channels (VrefInt/TempSensor). If these channels are       */
01247     /* intended to be set on other ADC instances, an error is reported.       */
01248     if (hadc->Instance == ADC1)
01249     {
01250       if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
01251       {
01252         SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
01253
01254         if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
01255         {
01256           /* Delay for temperature sensor stabilization time */
01257           /* Compute number of CPU cycles to wait for */
01258           wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
01259           while(wait_loop_index != 0U)
01260           {
01261             wait_loop_index--;
01262           }
01263         }
01264       }
01265     }
01266     else
01267     {
01268       /* Update ADC state machine to error */
01269       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01270
01271       tmp_hal_status = HAL_ERROR;
01272     }
01273   }
01274
01275   /* Process unlocked */
01276   __HAL_UNLOCK(hadc);
01277
01278   /* Return function status */
01279   return tmp_hal_status;
01280 }
01281
01282 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
01283 /**
01284   * @brief  Enable ADC multimode and configure multimode parameters
01285   * @note   Possibility to update parameters on the fly:
01286   *         This function initializes multimode parameters, following
01287   *         calls to this function can be used to reconfigure some parameters
01288   *         of structure "ADC_MultiModeTypeDef" on the fly, without reseting
01289   *         the ADCs (both ADCs of the common group).
01290   *         The setting of these parameters is conditioned to ADC state.
01291   *         For parameters constraints, see comments of structure
01292   *         "ADC_MultiModeTypeDef".
01293   * @note   To change back configuration from multimode to single mode, ADC must
01294   *         be reset (using function HAL_ADC_Init() ).
01295   * @param  hadc: ADC handle
01296   * @param  multimode: Structure of ADC multimode configuration
01297   * @retval HAL status
01298   */
01299 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
01300 {
01301   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
01302   ADC_HandleTypeDef tmphadcSlave;
01303
01304   /* Check the parameters */
01305   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01306   assert_param(IS_ADC_MODE(multimode->Mode));
01307
01308   /* Process locked */
01309   __HAL_LOCK(hadc);
01310
01311   /* Set a temporary handle of the ADC slave associated to the ADC master     */
01312   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01313
01314   /* Parameters update conditioned to ADC state:                              */
01315   /* Parameters that can be updated when ADC is disabled or enabled without   */
01316   /* conversion on going on regular group:                                    */
01317   /*  - ADC master and ADC slave DMA configuration                            */
01318   /* Parameters that can be updated only when ADC is disabled:                */
01319   /*  - Multimode mode selection                                              */
01320   /* To optimize code, all multimode settings can be set when both ADCs of    */
01321   /* the common group are in state: disabled.                                 */
01322   if ((ADC_IS_ENABLE(hadc) == RESET)                     &&
01323       (ADC_IS_ENABLE(&tmphadcSlave) == RESET)            &&
01324       (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance))   )
01325   {
01326     MODIFY_REG(hadc->Instance->CR1,
01327                ADC_CR1_DUALMOD    ,
01328                multimode->Mode     );
01329   }
01330   /* If one of the ADC sharing the same common group is enabled, no update    */
01331   /* could be done on neither of the multimode structure parameters.          */
01332   else
01333   {
01334     /* Update ADC state machine to error */
01335     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01336
01337     tmp_hal_status = HAL_ERROR;
01338   }
01339
01340
01341   /* Process unlocked */
01342   __HAL_UNLOCK(hadc);
01343
01344   /* Return function status */
01345   return tmp_hal_status;
01346 }
01347 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
01348 /**
01349   * @}
01350   */
01351
01352 /**
01353   * @}
01354   */
01355
01356 #endif /* HAL_ADC_MODULE_ENABLED */
01357 /**
01358   * @}
01359   */
01360
01361 /**
01362   * @}
01363   */
01364
01365 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_adc_ex.h Source File

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stm32f1xx_hal_adc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_adc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of ADC HAL extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_ADC_EX_H
00040 #define __STM32F1xx_HAL_ADC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup ADCEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  ADC Configuration injected Channel structure definition
00064   * @note   Parameters of this structure are shared within 2 scopes:
00065   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
00066   *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
00067   *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
00068   * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
00069   *         ADC state can be either:
00070   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
00071   *          - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
00072   */
00073 typedef struct
00074 {
00075   uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
00076                                                This parameter can be a value of @ref ADC_channels
00077                                                Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
00078                                                Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
00079                                                Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
00080                                                      It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
00081                                                      Refer to errata sheet of these devices for more details. */
00082   uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
00083                                                This parameter must be a value of @ref ADCEx_injected_rank
00084                                                Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
00085   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
00086                                                Unit: ADC clock cycles
00087                                                Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
00088                                                This parameter can be a value of @ref ADC_sampling_times
00089                                                Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
00090                                                         If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
00091                                                Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
00092                                                      sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
00093                                                      Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
00094   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
00095                                                Offset value must be a positive number.
00096                                                Depending of ADC resolution selected (12, 10, 8 or 6 bits),
00097                                                this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
00098   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
00099                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
00100                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
00101                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00102                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00103   uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
00104                                                Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
00105                                                Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
00106                                                This parameter can be set to ENABLE or DISABLE.
00107                                                Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
00108                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00109                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00110   uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
00111                                                This parameter can be set to ENABLE or DISABLE.
00112                                                Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
00113                                                Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
00114                                                Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
00115                                                      To maintain JAUTO always enabled, DMA must be configured in circular mode.
00116                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00117                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00118   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
00119                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
00120                                                If set to external trigger source, triggering is on event rising edge.
00121                                                This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
00122                                                Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
00123                                                      If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
00124                                                Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
00125                                                         configure a channel on injected group can impact the configuration of other channels previously set. */
00126 }ADC_InjectionConfTypeDef;
00127
00128 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00129 /**
00130   * @brief  Structure definition of ADC multimode
00131   * @note   The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
00132   *         State of ADCs of the common group must be: disabled.
00133   */
00134 typedef struct
00135 {
00136   uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode.
00137                                    This parameter can be a value of @ref ADCEx_Common_mode
00138                                    Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change.
00139                                    Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2.
00140                                    Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode.
00141                                    Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters).
00142                                          The equivalences are:
00143                                            - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
00144                                            - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
00145
00146
00147 }ADC_MultiModeTypeDef;
00148 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00149
00150 /**
00151   * @}
00152   */
00153
00154
00155 /* Exported constants --------------------------------------------------------*/
00156
00157 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
00158   * @{
00159   */
00160
00161 /** @defgroup ADCEx_injected_rank ADCEx rank into injected group
00162   * @{
00163   */
00164 #define ADC_INJECTED_RANK_1                           0x00000001U
00165 #define ADC_INJECTED_RANK_2                           0x00000002U
00166 #define ADC_INJECTED_RANK_3                           0x00000003U
00167 #define ADC_INJECTED_RANK_4                           0x00000004U
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
00173   * @{
00174   */
00175 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           0x00000000U
00176 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_CR2_JEXTTRIG)
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
00182   * @{
00183   */
00184 /*!< List of external triggers with generic trigger name, independently of    */
00185 /* ADC target, sorted by trigger name:                                        */
00186
00187 /*!< External triggers of regular group for ADC1&ADC2 only */
00188 #define ADC_EXTERNALTRIGCONV_T1_CC1         ADC1_2_EXTERNALTRIG_T1_CC1
00189 #define ADC_EXTERNALTRIGCONV_T1_CC2         ADC1_2_EXTERNALTRIG_T1_CC2
00190 #define ADC_EXTERNALTRIGCONV_T2_CC2         ADC1_2_EXTERNALTRIG_T2_CC2
00191 #define ADC_EXTERNALTRIGCONV_T3_TRGO        ADC1_2_EXTERNALTRIG_T3_TRGO
00192 #define ADC_EXTERNALTRIGCONV_T4_CC4         ADC1_2_EXTERNALTRIG_T4_CC4
00193 #define ADC_EXTERNALTRIGCONV_EXT_IT11       ADC1_2_EXTERNALTRIG_EXT_IT11
00194
00195 #if defined (STM32F103xE) || defined (STM32F103xG)
00196 /*!< External triggers of regular group for ADC3 only */
00197 #define ADC_EXTERNALTRIGCONV_T2_CC3         ADC3_EXTERNALTRIG_T2_CC3
00198 #define ADC_EXTERNALTRIGCONV_T3_CC1         ADC3_EXTERNALTRIG_T3_CC1
00199 #define ADC_EXTERNALTRIGCONV_T5_CC1         ADC3_EXTERNALTRIG_T5_CC1
00200 #define ADC_EXTERNALTRIGCONV_T5_CC3         ADC3_EXTERNALTRIG_T5_CC3
00201 #define ADC_EXTERNALTRIGCONV_T8_CC1         ADC3_EXTERNALTRIG_T8_CC1
00202 #endif /* STM32F103xE || defined STM32F103xG */
00203
00204 /*!< External triggers of regular group for all ADC instances */
00205 #define ADC_EXTERNALTRIGCONV_T1_CC3         ADC1_2_3_EXTERNALTRIG_T1_CC3
00206
00207 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
00208 /*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and   */
00209 /*         XL-density devices.                                                */
00210 /*         To use it on ADC or ADC2, a remap of trigger must be done from     */
00211 /*         EXTI line 11 to TIM8_TRGO with macro:                              */
00212 /*           __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()                           */
00213 /*           __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()                           */
00214
00215 /* Note for internal constant value management: If TIM8_TRGO is available,    */
00216 /* its definition is set to value for ADC1&ADC2 by default and changed to     */
00217 /* value for ADC3 by HAL ADC driver if ADC3 is selected.                      */
00218 #define ADC_EXTERNALTRIGCONV_T8_TRGO        ADC1_2_EXTERNALTRIG_T8_TRGO
00219 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00220
00221 #define ADC_SOFTWARE_START                  ADC1_2_3_SWSTART
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
00227   * @{
00228   */
00229 /*!< List of external triggers with generic trigger name, independently of    */
00230 /* ADC target, sorted by trigger name:                                        */
00231
00232 /*!< External triggers of injected group for ADC1&ADC2 only */
00233 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO        ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
00234 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1         ADC1_2_EXTERNALTRIGINJEC_T2_CC1
00235 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4         ADC1_2_EXTERNALTRIGINJEC_T3_CC4
00236 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO        ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
00237 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15       ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
00238
00239 #if defined (STM32F103xE) || defined (STM32F103xG)
00240 /*!< External triggers of injected group for ADC3 only */
00241 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3         ADC3_EXTERNALTRIGINJEC_T4_CC3
00242 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2         ADC3_EXTERNALTRIGINJEC_T8_CC2
00243 #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO        ADC3_EXTERNALTRIGINJEC_T5_TRGO
00244 #define ADC_EXTERNALTRIGINJECCONV_T5_CC4         ADC3_EXTERNALTRIGINJEC_T5_CC4
00245 #endif /* STM32F103xE || defined STM32F103xG */
00246
00247 /*!< External triggers of injected group for all ADC instances */
00248 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4         ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
00249 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO        ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
00250
00251 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
00252 /*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and    */
00253 /*         XL-density devices.                                                */
00254 /*         To use it on ADC1 or ADC2, a remap of trigger must be done from    */
00255 /*         EXTI line 11 to TIM8_CC4 with macro:                               */
00256 /*           __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()                           */
00257 /*           __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()                           */
00258
00259 /* Note for internal constant value management: If TIM8_CC4 is available,     */
00260 /* its definition is set to value for ADC1&ADC2 by default and changed to     */
00261 /* value for ADC3 by HAL ADC driver if ADC3 is selected.                      */
00262 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4         ADC1_2_EXTERNALTRIGINJEC_T8_CC4
00263 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00264
00265 #define ADC_INJECTED_SOFTWARE_START              ADC1_2_3_JSWSTART
00266 /**
00267   * @}
00268   */
00269
00270 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00271 /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
00272   * @{
00273   */
00274 #define ADC_MODE_INDEPENDENT                              0x00000000U                                                                     /*!< ADC dual mode disabled (ADC independent mode) */
00275 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)(                                                            ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
00276 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)(                                        ADC_CR1_DUALMOD_1                    )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
00277 #define ADC_DUALMODE_INJECSIMULT_INTERLFAST   ((uint32_t)(                                        ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
00278 #define ADC_DUALMODE_INJECSIMULT_INTERLSLOW   ((uint32_t)(                    ADC_CR1_DUALMOD_2                                        )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
00279 #define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(                    ADC_CR1_DUALMOD_2 |                     ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
00280 #define ADC_DUALMODE_REGSIMULT                ((uint32_t)(                    ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1                    )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
00281 #define ADC_DUALMODE_INTERLFAST               ((uint32_t)(                    ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
00282 #define ADC_DUALMODE_INTERLSLOW               ((uint32_t)(ADC_CR1_DUALMOD_3                                                            )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
00283 #define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CR1_DUALMOD_3 |                                         ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
00284 /**
00285   * @}
00286   */
00287 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00288
00289 /**
00290   * @}
00291   */
00292
00293
00294 /* Private constants ---------------------------------------------------------*/
00295
00296 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
00297   * @{
00298   */
00299
00300 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
00301   * @{
00302   */
00303 /* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC    */
00304 /* instance is available on the selected device).                             */
00305 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
00306
00307 /* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
00308 #define ADC1_2_EXTERNALTRIG_T1_CC1                       0x00000000U
00309 #define ADC1_2_EXTERNALTRIG_T1_CC2           ((uint32_t)(                                      ADC_CR2_EXTSEL_0))
00310 #define ADC1_2_EXTERNALTRIG_T2_CC2           ((uint32_t)(                   ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
00311 #define ADC1_2_EXTERNALTRIG_T3_TRGO          ((uint32_t)(ADC_CR2_EXTSEL_2                                      ))
00312 #define ADC1_2_EXTERNALTRIG_T4_CC4           ((uint32_t)(ADC_CR2_EXTSEL_2 |                    ADC_CR2_EXTSEL_0))
00313 #define ADC1_2_EXTERNALTRIG_EXT_IT11         ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1                   ))
00314 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
00315 /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and     */
00316 /* XL-density devices.                                                        */
00317 #define ADC1_2_EXTERNALTRIG_T8_TRGO          ADC1_2_EXTERNALTRIG_EXT_IT11
00318 #endif
00319
00320 #if defined (STM32F103xE) || defined (STM32F103xG)
00321 /* External triggers of regular group for ADC3 */
00322 #define ADC3_EXTERNALTRIG_T3_CC1             ADC1_2_EXTERNALTRIG_T1_CC1
00323 #define ADC3_EXTERNALTRIG_T2_CC3             ADC1_2_EXTERNALTRIG_T1_CC2
00324 #define ADC3_EXTERNALTRIG_T8_CC1             ADC1_2_EXTERNALTRIG_T2_CC2
00325 #define ADC3_EXTERNALTRIG_T8_TRGO            ADC1_2_EXTERNALTRIG_T3_TRGO
00326 #define ADC3_EXTERNALTRIG_T5_CC1             ADC1_2_EXTERNALTRIG_T4_CC4
00327 #define ADC3_EXTERNALTRIG_T5_CC3             ADC1_2_EXTERNALTRIG_EXT_IT11
00328 #endif
00329
00330 /* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
00331 #define ADC1_2_3_EXTERNALTRIG_T1_CC3         ((uint32_t)(                   ADC_CR2_EXTSEL_1                   ))
00332 #define ADC1_2_3_SWSTART                     ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
00333 /**
00334   * @}
00335   */
00336
00337 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
00338   * @{
00339   */
00340 /* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC    */
00341 /* instance is available on the selected device).                             */
00342 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
00343
00344 /* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
00345 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO          ((uint32_t)(                    ADC_CR2_JEXTSEL_1                    ))
00346 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1           ((uint32_t)(                    ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
00347 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_2                                        ))
00348 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_2 |                     ADC_CR2_JEXTSEL_0))
00349 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15         ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1                    ))
00350 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
00351 /* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and      */
00352 /* XL-density devices.                                                        */
00353 #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4           ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
00354 #endif
00355
00356 #if defined (STM32F103xE) || defined (STM32F103xG)
00357 /* External triggers of injected group for ADC3 */
00358 #define ADC3_EXTERNALTRIGINJEC_T4_CC3             ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
00359 #define ADC3_EXTERNALTRIGINJEC_T8_CC2             ADC1_2_EXTERNALTRIGINJEC_T2_CC1
00360 #define ADC3_EXTERNALTRIGINJEC_T8_CC4             ADC1_2_EXTERNALTRIGINJEC_T3_CC4
00361 #define ADC3_EXTERNALTRIGINJEC_T5_TRGO            ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
00362 #define ADC3_EXTERNALTRIGINJEC_T5_CC4             ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
00363 #endif /* STM32F103xE || defined STM32F103xG */
00364
00365 /* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
00366 #define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO                    0x00000000U
00367 #define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4         ((uint32_t)(                                        ADC_CR2_JEXTSEL_0))
00368 #define ADC1_2_3_JSWSTART                         ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
00369 /**
00370   * @}
00371   */
00372
00373 /**
00374   * @}
00375   */
00376
00377
00378 /* Exported macro ------------------------------------------------------------*/
00379
00380 /* Private macro -------------------------------------------------------------*/
00381
00382 /** @defgroup ADCEx_Private_Macro ADCEx Private Macro
00383   * @{
00384   */
00385 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
00386 /* code of final user.                                                        */
00387
00388
00389 /**
00390   * @brief For devices with 3 ADCs: Defines the external trigger source
00391   *        for regular group according to ADC into common group ADC1&ADC2 or
00392   *        ADC3 (some triggers with same source have different value to
00393   *        be programmed into ADC EXTSEL bits of CR2 register).
00394   *        For devices with 2 ADCs or less: this macro makes no change.
00395   * @param __HANDLE__: ADC handle
00396   * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
00397   * @retval External trigger to be programmed into EXTSEL bits of CR2 register
00398   */
00399 #if defined (STM32F103xE) || defined (STM32F103xG)
00400 #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__)                         \
00401  (( (((__HANDLE__)->Instance) == ADC3)                                         \
00402   )?                                                                           \
00403    ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO                     \
00404      )?                                                                        \
00405       (ADC3_EXTERNALTRIG_T8_TRGO)                                              \
00406       :                                                                        \
00407       (__EXT_TRIG_CONV__)                                                      \
00408    )                                                                           \
00409    :                                                                           \
00410    (__EXT_TRIG_CONV__)                                                         \
00411  )
00412 #else
00413 #define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__)                         \
00414   (__EXT_TRIG_CONV__)
00415 #endif /* STM32F103xE || STM32F103xG */
00416
00417 /**
00418   * @brief For devices with 3 ADCs: Defines the external trigger source
00419   *        for injected group according to ADC into common group ADC1&ADC2 or
00420   *        ADC3 (some triggers with same source have different value to
00421   *        be programmed into ADC JEXTSEL bits of CR2 register).
00422   *        For devices with 2 ADCs or less: this macro makes no change.
00423   * @param __HANDLE__: ADC handle
00424   * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
00425   * @retval External trigger to be programmed into JEXTSEL bits of CR2 register
00426   */
00427 #if defined (STM32F103xE) || defined (STM32F103xG)
00428 #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__)                  \
00429  (( (((__HANDLE__)->Instance) == ADC3)                                         \
00430   )?                                                                           \
00431    ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4           \
00432      )?                                                                        \
00433       (ADC3_EXTERNALTRIGINJEC_T8_CC4)                                          \
00434       :                                                                        \
00435       (__EXT_TRIG_INJECTCONV__)                                                \
00436    )                                                                           \
00437    :                                                                           \
00438    (__EXT_TRIG_INJECTCONV__)                                                   \
00439  )
00440 #else
00441 #define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__)                  \
00442    (__EXT_TRIG_INJECTCONV__)
00443 #endif /* STM32F103xE || STM32F103xG */
00444
00445
00446 /**
00447   * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
00448   * @param __HANDLE__: ADC handle
00449   * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
00450   */
00451 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00452 #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__)                                    \
00453  (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)   \
00454   )?                                                                           \
00455    (ADC1->CR1 & ADC_CR1_DUALMOD)                                               \
00456    :                                                                           \
00457    (RESET)                                                                     \
00458  )
00459 #else
00460 #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__)                                    \
00461   (RESET)
00462 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00463
00464 /**
00465   * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
00466   * @param __HANDLE__: ADC handle
00467   * @retval None
00468   */
00469 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00470 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
00471   (( (((__HANDLE__)->Instance) == ADC2)                                        \
00472    )?                                                                          \
00473     ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET)                                   \
00474     :                                                                          \
00475     (!RESET)                                                                   \
00476   )
00477 #else
00478 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \
00479   (!RESET)
00480 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00481
00482 /**
00483   * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
00484   * @param __HANDLE__: ADC handle
00485   * @retval None
00486   */
00487 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00488 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)                                \
00489   (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)  \
00490    )?                                                                          \
00491     (ADC1->CR1 & ADC_CR1_JAUTO)                                                \
00492     :                                                                          \
00493     (RESET)                                                                    \
00494   )
00495 #else
00496 #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__)                                \
00497   (RESET)
00498 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00499
00500 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00501 /**
00502   * @brief Set handle of the other ADC sharing the common multimode settings
00503   * @param __HANDLE__: ADC handle
00504   * @param __HANDLE_OTHER_ADC__: other ADC handle
00505   * @retval None
00506   */
00507 #define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__)                 \
00508   ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
00509
00510 /**
00511   * @brief Set handle of the ADC slave associated to the ADC master
00512   * On STM32F1 devices, ADC slave is always ADC2 (this can be different
00513   * on other STM32 devices)
00514   * @param __HANDLE_MASTER__: ADC master handle
00515   * @param __HANDLE_SLAVE__: ADC slave handle
00516   * @retval None
00517   */
00518 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)                   \
00519   ((__HANDLE_SLAVE__)->Instance = ADC2)
00520
00521 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00522
00523 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
00524                                        ((CHANNEL) == ADC_INJECTED_RANK_2) || \
00525                                        ((CHANNEL) == ADC_INJECTED_RANK_3) || \
00526                                        ((CHANNEL) == ADC_INJECTED_RANK_4))
00527
00528 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)  || \
00529                                         ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
00530
00531 /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
00532   * @{
00533   */
00534 #define IS_ADC_INJECTED_NB_CONV(LENGTH)  (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
00535 /**
00536   * @}
00537   */
00538
00539 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
00540 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
00541                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
00542                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
00543                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
00544                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
00545                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
00546                                  ((REGTRIG) == ADC_SOFTWARE_START))
00547 #endif
00548 #if defined (STM32F101xE)
00549 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
00550                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
00551                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
00552                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
00553                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
00554                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
00555                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO)   || \
00556                                  ((REGTRIG) == ADC_SOFTWARE_START))
00557 #endif
00558 #if defined (STM32F101xG)
00559 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
00560                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
00561                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
00562                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
00563                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
00564                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
00565                                  ((REGTRIG) == ADC_SOFTWARE_START))
00566 #endif
00567 #if defined (STM32F103xE) || defined (STM32F103xG)
00568 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)    || \
00569                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)    || \
00570                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)    || \
00571                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)   || \
00572                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)    || \
00573                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11)  || \
00574                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)    || \
00575                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)    || \
00576                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)    || \
00577                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)    || \
00578                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)    || \
00579                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)    || \
00580                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO)   || \
00581                                  ((REGTRIG) == ADC_SOFTWARE_START))
00582 #endif
00583
00584 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
00585 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
00586                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
00587                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
00588                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
00589                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
00590                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
00591                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
00592                                       ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
00593 #endif
00594 #if defined (STM32F101xE)
00595 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
00596                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
00597                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
00598                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
00599                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
00600                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
00601                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
00602                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
00603                                       ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
00604 #endif
00605 #if defined (STM32F101xG)
00606 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
00607                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
00608                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
00609                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
00610                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
00611                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
00612                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
00613                                       ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
00614 #endif
00615 #if defined (STM32F103xE) || defined (STM32F103xG)
00616 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
00617                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
00618                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
00619                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
00620                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)   || \
00621                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
00622                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)   || \
00623                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)   || \
00624                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO)  || \
00625                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)   || \
00626                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)   || \
00627                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO)  || \
00628                                       ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)   || \
00629                                       ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
00630 #endif
00631
00632 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00633 #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT)                || \
00634                            ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)  || \
00635                            ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)    || \
00636                            ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
00637                            ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
00638                            ((MODE) == ADC_DUALMODE_INJECSIMULT)            || \
00639                            ((MODE) == ADC_DUALMODE_REGSIMULT)              || \
00640                            ((MODE) == ADC_DUALMODE_INTERLFAST)             || \
00641                            ((MODE) == ADC_DUALMODE_INTERLSLOW)             || \
00642                            ((MODE) == ADC_DUALMODE_ALTERTRIG) )
00643 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00644
00645 /**
00646   * @}
00647   */
00648
00649
00650
00651
00652
00653
00654 /* Exported functions --------------------------------------------------------*/
00655 /** @addtogroup ADCEx_Exported_Functions
00656   * @{
00657   */
00658
00659 /* IO operation functions  *****************************************************/
00660 /** @addtogroup ADCEx_Exported_Functions_Group1
00661   * @{
00662   */
00663
00664 /* ADC calibration */
00665 HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
00666
00667 /* Blocking mode: Polling */
00668 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
00669 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
00670 HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
00671
00672 /* Non-blocking mode: Interruption */
00673 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
00674 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
00675
00676 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00677 /* ADC multimode */
00678 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
00679 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
00680 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00681
00682 /* ADC retrieve conversion value intended to be used with polling or interruption */
00683 uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
00684 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00685 uint32_t                HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
00686 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00687
00688 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
00689 void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
00690 /**
00691   * @}
00692   */
00693
00694
00695 /* Peripheral Control functions ***********************************************/
00696 /** @addtogroup ADCEx_Exported_Functions_Group2
00697   * @{
00698   */
00699 HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
00700 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00701 HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
00702 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
00703 /**
00704   * @}
00705   */
00706
00707
00708 /**
00709   * @}
00710   */
00711
00712
00713 /**
00714   * @}
00715   */
00716
00717 /**
00718   * @}
00719   */
00720
00721 #ifdef __cplusplus
00722 }
00723 #endif
00724
00725 #endif /* __STM32F1xx_HAL_ADC_EX_H */
00726
00727
00728 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_can.c Source File

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stm32f1xx_hal_can.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_can.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   CAN HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Controller Area Network (CAN) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Error functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       (#) Enable the CAN controller interface clock using
00021           __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
00022       -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
00023
00024       (#) CAN pins configuration
00025         (++) Enable the clock for the CAN GPIOs using the following function:
00026              __HAL_RCC_GPIOx_CLK_ENABLE();
00027         (++) Connect and configure the involved CAN pins using the
00028               following function HAL_GPIO_Init();
00029
00030       (#) Initialize and configure the CAN using HAL_CAN_Init() function.
00031
00032       (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
00033
00034       (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
00035
00036       (#) Receive a CAN frame using HAL_CAN_Receive() function.
00037
00038       (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
00039
00040      *** Polling mode IO operation ***
00041      =================================
00042      [..]
00043        (+) Start the CAN peripheral transmission and wait the end of this operation
00044            using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
00045            according to his end application
00046        (+) Start the CAN peripheral reception and wait the end of this operation
00047            using HAL_CAN_Receive(), at this stage user can specify the value of timeout
00048            according to his end application
00049
00050      *** Interrupt mode IO operation ***
00051      ===================================
00052      [..]
00053        (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
00054        (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
00055        (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
00056        (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
00057             add his own code by customization of function pointer HAL_CAN_TxCpltCallback
00058        (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
00059             add his own code by customization of function pointer HAL_CAN_ErrorCallback
00060
00061      *** CAN HAL driver macros list ***
00062      =============================================
00063      [..]
00064        Below the list of most used macros in CAN HAL driver.
00065
00066       (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
00067       (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
00068       (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
00069       (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
00070       (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
00071
00072      [..]
00073       (@) You can refer to the CAN HAL driver header file for more useful macros
00074
00075   @endverbatim
00076
00077   ******************************************************************************
00078   * @attention
00079   *
00080   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00081   *
00082   * Redistribution and use in source and binary forms, with or without modification,
00083   * are permitted provided that the following conditions are met:
00084   *   1. Redistributions of source code must retain the above copyright notice,
00085   *      this list of conditions and the following disclaimer.
00086   *   2. Redistributions in binary form must reproduce the above copyright notice,
00087   *      this list of conditions and the following disclaimer in the documentation
00088   *      and/or other materials provided with the distribution.
00089   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00090   *      may be used to endorse or promote products derived from this software
00091   *      without specific prior written permission.
00092   *
00093   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00094   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00095   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00096   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00097   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00098   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00099   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00100   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00101   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00102   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00103   *
00104   ******************************************************************************
00105   */
00106
00107 /* Includes ------------------------------------------------------------------*/
00108 #include "stm32f1xx_hal.h"
00109
00110 /** @addtogroup STM32F1xx_HAL_Driver
00111   * @{
00112   */
00113
00114 /** @defgroup CAN CAN
00115   * @brief CAN driver modules
00116   * @{
00117   */
00118
00119 #ifdef HAL_CAN_MODULE_ENABLED
00120
00121 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
00122     defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
00123
00124
00125 /* Private typedef -----------------------------------------------------------*/
00126 /* Private define ------------------------------------------------------------*/
00127 /** @defgroup CAN_Private_Constants CAN Private Constants
00128   * @{
00129   */
00130 #define CAN_TIMEOUT_VALUE  10U
00131 /**
00132   * @}
00133   */
00134 /* Private macro -------------------------------------------------------------*/
00135 /* Private variables ---------------------------------------------------------*/
00136 /* Private function prototypes -----------------------------------------------*/
00137 /** @defgroup CAN_Private_Functions CAN Private Functions
00138   * @{
00139   */
00140 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
00141 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
00142 /**
00143   * @}
00144   */
00145
00146 /* Exported functions --------------------------------------------------------*/
00147 /** @defgroup CAN_Exported_Functions CAN Exported Functions
00148   * @{
00149   */
00150
00151 /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
00152  *  @brief    Initialization and Configuration functions
00153  *
00154 @verbatim
00155   ==============================================================================
00156               ##### Initialization and de-initialization functions #####
00157   ==============================================================================
00158     [..]  This section provides functions allowing to:
00159       (+) Initialize and configure the CAN.
00160       (+) De-initialize the CAN.
00161
00162 @endverbatim
00163   * @{
00164   */
00165
00166 /**
00167   * @brief  Initializes the CAN peripheral according to the specified
00168   *         parameters in the CAN_InitStruct.
00169   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00170   *         the configuration information for the specified CAN.
00171   * @retval HAL status
00172   */
00173 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
00174 {
00175   uint32_t status = CAN_INITSTATUS_FAILED;  /* Default init status */
00176   uint32_t tickstart = 0U;
00177   uint32_t tmp_mcr = 0U;
00178
00179   /* Check CAN handle */
00180   if(hcan == NULL)
00181   {
00182      return HAL_ERROR;
00183   }
00184
00185   /* Check the parameters */
00186   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00187   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
00188   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
00189   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
00190   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
00191   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
00192   assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
00193   assert_param(IS_CAN_MODE(hcan->Init.Mode));
00194   assert_param(IS_CAN_SJW(hcan->Init.SJW));
00195   assert_param(IS_CAN_BS1(hcan->Init.BS1));
00196   assert_param(IS_CAN_BS2(hcan->Init.BS2));
00197   assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
00198
00199   if(hcan->State == HAL_CAN_STATE_RESET)
00200   {
00201     /* Allocate lock resource and initialize it */
00202     hcan->Lock = HAL_UNLOCKED;
00203     /* Init the low level hardware */
00204     HAL_CAN_MspInit(hcan);
00205   }
00206
00207   /* Initialize the CAN state*/
00208   hcan->State = HAL_CAN_STATE_BUSY;
00209
00210   /* Exit from sleep mode */
00211   CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
00212
00213   /* Request initialisation */
00214   SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
00215
00216   /* Get timeout */
00217   tickstart = HAL_GetTick();
00218
00219   /* Wait the acknowledge */
00220   while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
00221   {
00222     if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
00223     {
00224       hcan->State= HAL_CAN_STATE_TIMEOUT;
00225       /* Process unlocked */
00226       __HAL_UNLOCK(hcan);
00227       return HAL_TIMEOUT;
00228     }
00229   }
00230
00231   /* Check acknowledge */
00232   if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
00233   {
00234     /* Set the time triggered communication mode */
00235     if (hcan->Init.TTCM == ENABLE)
00236     {
00237       SET_BIT(tmp_mcr, CAN_MCR_TTCM);
00238     }
00239     else
00240     {
00241       CLEAR_BIT(tmp_mcr, CAN_MCR_TTCM);
00242     }
00243
00244     /* Set the automatic bus-off management */
00245     if (hcan->Init.ABOM == ENABLE)
00246     {
00247       SET_BIT(tmp_mcr, CAN_MCR_ABOM);
00248     }
00249     else
00250     {
00251       CLEAR_BIT(tmp_mcr, CAN_MCR_ABOM);
00252     }
00253
00254     /* Set the automatic wake-up mode */
00255     if (hcan->Init.AWUM == ENABLE)
00256     {
00257       SET_BIT(tmp_mcr, CAN_MCR_AWUM);
00258     }
00259     else
00260     {
00261       CLEAR_BIT(tmp_mcr, CAN_MCR_AWUM);
00262     }
00263     /* Set the no automatic retransmission */
00264     if (hcan->Init.NART == ENABLE)
00265     {
00266       SET_BIT(tmp_mcr, CAN_MCR_NART);
00267     }
00268     else
00269     {
00270       CLEAR_BIT(tmp_mcr, CAN_MCR_NART);
00271     }
00272
00273     /* Set the receive FIFO locked mode */
00274     if (hcan->Init.RFLM == ENABLE)
00275     {
00276       SET_BIT(tmp_mcr, CAN_MCR_RFLM);
00277     }
00278     else
00279     {
00280       CLEAR_BIT(tmp_mcr, CAN_MCR_RFLM);
00281     }
00282     /* Set the transmit FIFO priority */
00283     if (hcan->Init.TXFP == ENABLE)
00284     {
00285       SET_BIT(tmp_mcr, CAN_MCR_TXFP);
00286     }
00287     else
00288     {
00289       CLEAR_BIT(tmp_mcr, CAN_MCR_TXFP);
00290     }
00291
00292     /* Update register MCR */
00293     MODIFY_REG(hcan->Instance->MCR,
00294                CAN_MCR_TTCM |
00295                CAN_MCR_ABOM |
00296                CAN_MCR_AWUM |
00297                CAN_MCR_NART |
00298                CAN_MCR_RFLM |
00299                CAN_MCR_TXFP,
00300                tmp_mcr);
00301
00302     /* Set the bit timing register */
00303     WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |
00304                                               hcan->Init.SJW            |
00305                                               hcan->Init.BS1            |
00306                                               hcan->Init.BS2            |
00307                                               (hcan->Init.Prescaler - 1U) ));
00308
00309     /* Request leave initialisation */
00310     CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
00311
00312     /* Get timeout */
00313     tickstart = HAL_GetTick();
00314
00315     /* Wait the acknowledge */
00316     while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
00317     {
00318       if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
00319       {
00320         hcan->State= HAL_CAN_STATE_TIMEOUT;
00321
00322         /* Process unlocked */
00323         __HAL_UNLOCK(hcan);
00324
00325         return HAL_TIMEOUT;
00326       }
00327     }
00328
00329     /* Check acknowledged */
00330     if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
00331     {
00332       status = CAN_INITSTATUS_SUCCESS;
00333     }
00334   }
00335
00336   if(status == CAN_INITSTATUS_SUCCESS)
00337   {
00338     /* Set CAN error code to none */
00339     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00340
00341     /* Initialize the CAN state */
00342     hcan->State = HAL_CAN_STATE_READY;
00343
00344     /* Return function status */
00345     return HAL_OK;
00346   }
00347   else
00348   {
00349     /* Initialize the CAN state */
00350     hcan->State = HAL_CAN_STATE_ERROR;
00351
00352     /* Return function status */
00353     return HAL_ERROR;
00354   }
00355 }
00356
00357 /**
00358   * @brief  Configures the CAN reception filter according to the specified
00359   *         parameters in the CAN_FilterInitStruct.
00360   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00361   *         the configuration information for the specified CAN.
00362   * @param  sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
00363   *         contains the filter configuration information.
00364   * @retval None
00365   */
00366 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
00367 {
00368   uint32_t filternbrbitpos = 0U;
00369
00370   /* Prevent unused argument(s) compilation warning */
00371   UNUSED(hcan);
00372
00373   /* Check the parameters */
00374   assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
00375   assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
00376   assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
00377   assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
00378   assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
00379   assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
00380
00381   filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
00382
00383   /* Initialisation mode for the filter */
00384   /* Select the start slave bank */
00385   MODIFY_REG(hcan->Instance->FMR                         ,
00386              CAN_FMR_CAN2SB                              ,
00387              CAN_FMR_FINIT                              |
00388              (uint32_t)(sFilterConfig->BankNumber << 8U)   );
00389
00390   /* Filter Deactivation */
00391   CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
00392
00393   /* Filter Scale */
00394   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
00395   {
00396     /* 16-bit scale for the filter */
00397     CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
00398
00399     /* First 16-bit identifier and First 16-bit mask */
00400     /* Or First 16-bit identifier and Second 16-bit identifier */
00401     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00402        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
00403         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
00404
00405     /* Second 16-bit identifier and Second 16-bit mask */
00406     /* Or Third 16-bit identifier and Fourth 16-bit identifier */
00407     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00408        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
00409         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
00410   }
00411
00412   if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
00413   {
00414     /* 32-bit scale for the filter */
00415     SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
00416     /* 32-bit identifier or First 32-bit identifier */
00417     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
00418        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
00419         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
00420     /* 32-bit mask or Second 32-bit identifier */
00421     hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
00422        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
00423         (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
00424   }
00425
00426   /* Filter Mode */
00427   if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
00428   {
00429     /*Id/Mask mode for the filter*/
00430     CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
00431   }
00432   else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
00433   {
00434     /*Identifier list mode for the filter*/
00435     SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
00436   }
00437
00438   /* Filter FIFO assignment */
00439   if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
00440   {
00441     /* FIFO 0 assignation for the filter */
00442     CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
00443   }
00444   else
00445   {
00446     /* FIFO 1 assignation for the filter */
00447     SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
00448   }
00449
00450   /* Filter activation */
00451   if (sFilterConfig->FilterActivation == ENABLE)
00452   {
00453     SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
00454   }
00455
00456   /* Leave the initialisation mode for the filter */
00457   CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
00458
00459   /* Return function status */
00460   return HAL_OK;
00461 }
00462
00463 /**
00464   * @brief  Deinitializes the CANx peripheral registers to their default reset values.
00465   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00466   *         the configuration information for the specified CAN.
00467   * @retval HAL status
00468   */
00469 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
00470 {
00471   /* Check CAN handle */
00472   if(hcan == NULL)
00473   {
00474      return HAL_ERROR;
00475   }
00476
00477   /* Check the parameters */
00478   assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
00479
00480   /* Change CAN state */
00481   hcan->State = HAL_CAN_STATE_BUSY;
00482
00483   /* DeInit the low level hardware */
00484   HAL_CAN_MspDeInit(hcan);
00485
00486   /* Change CAN state */
00487   hcan->State = HAL_CAN_STATE_RESET;
00488
00489   /* Release Lock */
00490   __HAL_UNLOCK(hcan);
00491
00492   /* Return function status */
00493   return HAL_OK;
00494 }
00495
00496 /**
00497   * @brief  Initializes the CAN MSP.
00498   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00499   *         the configuration information for the specified CAN.
00500   * @retval None
00501   */
00502 __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
00503 {
00504   /* Prevent unused argument(s) compilation warning */
00505   UNUSED(hcan);
00506   /* NOTE : This function Should not be modified, when the callback is needed,
00507             the HAL_CAN_MspInit can be implemented in the user file
00508    */
00509 }
00510
00511 /**
00512   * @brief  DeInitializes the CAN MSP.
00513   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00514   *         the configuration information for the specified CAN.
00515   * @retval None
00516   */
00517 __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
00518 {
00519   /* Prevent unused argument(s) compilation warning */
00520   UNUSED(hcan);
00521   /* NOTE : This function Should not be modified, when the callback is needed,
00522             the HAL_CAN_MspDeInit can be implemented in the user file
00523    */
00524 }
00525
00526 /**
00527   * @}
00528   */
00529
00530 /** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
00531   *  @brief    I/O operation functions
00532   *
00533 @verbatim
00534   ==============================================================================
00535                       ##### IO operation functions #####
00536   ==============================================================================
00537     [..]  This section provides functions allowing to:
00538       (+) Transmit a CAN frame message.
00539       (+) Receive a CAN frame message.
00540       (+) Enter CAN peripheral in sleep mode.
00541       (+) Wake up the CAN peripheral from sleep mode.
00542
00543 @endverbatim
00544   * @{
00545   */
00546
00547 /**
00548   * @brief  Initiates and transmits a CAN frame message.
00549   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00550   *         the configuration information for the specified CAN.
00551   * @param  Timeout: Specify Timeout value
00552   * @retval HAL status
00553   */
00554 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
00555 {
00556   uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
00557   uint32_t tickstart = 0U;
00558
00559   /* Check the parameters */
00560   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00561   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00562   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00563
00564   if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
00565      ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
00566      ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
00567   {
00568     /* Process locked */
00569     __HAL_LOCK(hcan);
00570
00571     if(hcan->State == HAL_CAN_STATE_BUSY_RX)
00572     {
00573       /* Change CAN state */
00574       hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00575     }
00576     else
00577     {
00578       /* Change CAN state */
00579       hcan->State = HAL_CAN_STATE_BUSY_TX;
00580     }
00581
00582     /* Select one empty transmit mailbox */
00583     if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
00584     {
00585       transmitmailbox = CAN_TXMAILBOX_0;
00586     }
00587     else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
00588     {
00589       transmitmailbox = CAN_TXMAILBOX_1;
00590     }
00591     else
00592     {
00593       transmitmailbox = CAN_TXMAILBOX_2;
00594     }
00595
00596     /* Set up the Id */
00597     hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00598     if (hcan->pTxMsg->IDE == CAN_ID_STD)
00599     {
00600       assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00601       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) |
00602                                                            hcan->pTxMsg->RTR);
00603     }
00604     else
00605     {
00606       assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00607       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) |
00608                                                            hcan->pTxMsg->IDE |
00609                                                            hcan->pTxMsg->RTR);
00610     }
00611
00612     /* Set up the DLC */
00613     hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
00614     hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
00615     hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00616
00617     /* Set up the data field */
00618     WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
00619                                                                 ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
00620                                                                 ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
00621                                                                 ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
00622     WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
00623                                                                 ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
00624                                                                 ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
00625                                                                 ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
00626     /* Request transmission */
00627     SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
00628
00629     /* Get tick */
00630     tickstart = HAL_GetTick();
00631
00632     /* Check End of transmission flag */
00633     while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
00634     {
00635       /* Check for the Timeout */
00636       if(Timeout != HAL_MAX_DELAY)
00637       {
00638         if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00639         {
00640           hcan->State = HAL_CAN_STATE_TIMEOUT;
00641           /* Process unlocked */
00642           __HAL_UNLOCK(hcan);
00643           __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
00644           return HAL_TIMEOUT;
00645         }
00646       }
00647     }
00648     if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
00649     {
00650       /* Change CAN state */
00651       hcan->State = HAL_CAN_STATE_BUSY_RX;
00652     }
00653     else
00654     {
00655       /* Change CAN state */
00656       hcan->State = HAL_CAN_STATE_READY;
00657     }
00658
00659     /* Process unlocked */
00660     __HAL_UNLOCK(hcan);
00661
00662     /* Return function status */
00663     return HAL_OK;
00664   }
00665   else
00666   {
00667     /* Change CAN state */
00668     hcan->State = HAL_CAN_STATE_ERROR;
00669
00670     /* Return function status */
00671     return HAL_ERROR;
00672   }
00673 }
00674
00675 /**
00676   * @brief  Initiates and transmits a CAN frame message.
00677   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00678   *         the configuration information for the specified CAN.
00679   * @retval HAL status
00680   */
00681 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
00682 {
00683   uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
00684
00685   /* Check the parameters */
00686   assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
00687   assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
00688   assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
00689
00690   if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
00691      ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
00692      ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
00693   {
00694
00695     /* Select one empty transmit mailbox */
00696     if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
00697     {
00698       transmitmailbox = CAN_TXMAILBOX_0;
00699     }
00700     else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
00701     {
00702       transmitmailbox = CAN_TXMAILBOX_1;
00703     }
00704     else
00705     {
00706       transmitmailbox = CAN_TXMAILBOX_2;
00707     }
00708
00709     /* Set up the Id */
00710     hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
00711     if(hcan->pTxMsg->IDE == CAN_ID_STD)
00712     {
00713       assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
00714       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
00715                                                            hcan->pTxMsg->RTR);
00716     }
00717     else
00718     {
00719       assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
00720       hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
00721                                                            hcan->pTxMsg->IDE |
00722                                                            hcan->pTxMsg->RTR);
00723     }
00724
00725     /* Set up the DLC */
00726     hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
00727     hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
00728     hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
00729
00730     /* Set up the data field */
00731     WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3U] << CAN_TDL0R_DATA3_Pos) |
00732                                                                 ((uint32_t)hcan->pTxMsg->Data[2U] << CAN_TDL0R_DATA2_Pos) |
00733                                                                 ((uint32_t)hcan->pTxMsg->Data[1U] << CAN_TDL0R_DATA1_Pos) |
00734                                                                 ((uint32_t)hcan->pTxMsg->Data[0U] << CAN_TDL0R_DATA0_Pos));
00735     WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7U] << CAN_TDL0R_DATA3_Pos) |
00736                                                                 ((uint32_t)hcan->pTxMsg->Data[6U] << CAN_TDL0R_DATA2_Pos) |
00737                                                                 ((uint32_t)hcan->pTxMsg->Data[5U] << CAN_TDL0R_DATA1_Pos) |
00738                                                                 ((uint32_t)hcan->pTxMsg->Data[4U] << CAN_TDL0R_DATA0_Pos));
00739
00740     if(hcan->State == HAL_CAN_STATE_BUSY_RX)
00741     {
00742       /* Change CAN state */
00743       hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00744     }
00745     else
00746     {
00747       /* Change CAN state */
00748       hcan->State = HAL_CAN_STATE_BUSY_TX;
00749     }
00750
00751     /* Set CAN error code to none */
00752     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00753
00754     /* Enable interrupts: */
00755     /*  - Enable Error warning Interrupt */
00756     /*  - Enable Error passive Interrupt */
00757     /*  - Enable Bus-off Interrupt */
00758     /*  - Enable Last error code Interrupt */
00759     /*  - Enable Error Interrupt */
00760     /*  - Enable Transmit mailbox empty Interrupt */
00761     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
00762                               CAN_IT_EPV |
00763                               CAN_IT_BOF |
00764                               CAN_IT_LEC |
00765                               CAN_IT_ERR |
00766                               CAN_IT_TME  );
00767
00768     /* Request transmission */
00769     hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
00770   }
00771   else
00772   {
00773     /* Change CAN state */
00774     hcan->State = HAL_CAN_STATE_ERROR;
00775
00776     /* Return function status */
00777     return HAL_ERROR;
00778   }
00779
00780   return HAL_OK;
00781 }
00782
00783 /**
00784   * @brief  Receives a correct CAN frame.
00785   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00786   *         the configuration information for the specified CAN.
00787   * @param  FIFONumber: FIFO Number value
00788   * @param  Timeout: Specify Timeout value
00789   * @retval HAL status
00790   */
00791 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
00792 {
00793   uint32_t tickstart = 0U;
00794
00795   /* Check the parameters */
00796   assert_param(IS_CAN_FIFO(FIFONumber));
00797
00798   /* Process locked */
00799   __HAL_LOCK(hcan);
00800
00801   if(hcan->State == HAL_CAN_STATE_BUSY_TX)
00802   {
00803     /* Change CAN state */
00804     hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00805   }
00806   else
00807   {
00808     /* Change CAN state */
00809     hcan->State = HAL_CAN_STATE_BUSY_RX;
00810   }
00811
00812   /* Get tick */
00813   tickstart = HAL_GetTick();
00814
00815   /* Check pending message */
00816   while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
00817   {
00818     /* Check for the Timeout */
00819     if(Timeout != HAL_MAX_DELAY)
00820     {
00821       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00822       {
00823         hcan->State = HAL_CAN_STATE_TIMEOUT;
00824         /* Process unlocked */
00825         __HAL_UNLOCK(hcan);
00826         return HAL_TIMEOUT;
00827       }
00828     }
00829   }
00830
00831   /* Get the Id */
00832   hcan->pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
00833   if (hcan->pRxMsg->IDE == CAN_ID_STD)
00834   {
00835     hcan->pRxMsg->StdId = (uint32_t)0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
00836   }
00837   else
00838   {
00839     hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
00840   }
00841
00842   hcan->pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
00843   /* Get the DLC */
00844   hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
00845   /* Get the FMI */
00846   hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
00847   /* Get the FIFONumber */
00848   hcan->pRxMsg->FIFONumber = FIFONumber;
00849   /* Get the data field */
00850   hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
00851   hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
00852   hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
00853   hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
00854   hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
00855   hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
00856   hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
00857   hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
00858
00859   /* Release the FIFO */
00860   if(FIFONumber == CAN_FIFO0)
00861   {
00862     /* Release FIFO0 */
00863     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
00864   }
00865   else /* FIFONumber == CAN_FIFO1 */
00866   {
00867     /* Release FIFO1 */
00868     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
00869   }
00870
00871   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
00872   {
00873     /* Change CAN state */
00874     hcan->State = HAL_CAN_STATE_BUSY_TX;
00875   }
00876   else
00877   {
00878     /* Change CAN state */
00879     hcan->State = HAL_CAN_STATE_READY;
00880   }
00881
00882   /* Process unlocked */
00883   __HAL_UNLOCK(hcan);
00884
00885   /* Return function status */
00886   return HAL_OK;
00887 }
00888
00889 /**
00890   * @brief  Receives a correct CAN frame.
00891   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00892   *         the configuration information for the specified CAN.
00893   * @param  FIFONumber: Specify the FIFO number
00894   * @retval HAL status
00895   */
00896 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
00897 {
00898   uint32_t tmp = 0U;
00899
00900   /* Check the parameters */
00901   assert_param(IS_CAN_FIFO(FIFONumber));
00902
00903   tmp = hcan->State;
00904   if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_TX))
00905   {
00906     if(hcan->State == HAL_CAN_STATE_BUSY_TX)
00907     {
00908       /* Change CAN state */
00909       hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
00910     }
00911     else
00912     {
00913       /* Change CAN state */
00914       hcan->State = HAL_CAN_STATE_BUSY_RX;
00915     }
00916
00917     /* Set CAN error code to none */
00918     hcan->ErrorCode = HAL_CAN_ERROR_NONE;
00919
00920     /* Enable interrupts: */
00921     /*  - Enable Error warning Interrupt */
00922     /*  - Enable Error passive Interrupt */
00923     /*  - Enable Bus-off Interrupt */
00924     /*  - Enable Last error code Interrupt */
00925     /*  - Enable Error Interrupt */
00926     /*  - Enable Transmit mailbox empty Interrupt */
00927     __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
00928                               CAN_IT_EPV |
00929                               CAN_IT_BOF |
00930                               CAN_IT_LEC |
00931                               CAN_IT_ERR |
00932                               CAN_IT_TME  );
00933
00934     if(FIFONumber == CAN_FIFO0)
00935     {
00936       /* Enable FIFO 0 overrun and message pending Interrupt */
00937       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
00938     }
00939     else
00940     {
00941       /* Enable FIFO 1 overrun and message pending Interrupt */
00942       __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
00943     }
00944
00945   }
00946   else
00947   {
00948     return HAL_BUSY;
00949   }
00950
00951   /* Return function status */
00952   return HAL_OK;
00953 }
00954
00955 /**
00956   * @brief  Enters the Sleep (low power) mode.
00957   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
00958   *         the configuration information for the specified CAN.
00959   * @retval HAL status.
00960   */
00961 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
00962 {
00963   uint32_t tickstart = 0U;
00964
00965   /* Process locked */
00966   __HAL_LOCK(hcan);
00967
00968   /* Change CAN state */
00969   hcan->State = HAL_CAN_STATE_BUSY;
00970
00971   /* Request Sleep mode */
00972   MODIFY_REG(hcan->Instance->MCR,
00973              CAN_MCR_INRQ       ,
00974              CAN_MCR_SLEEP       );
00975
00976   /* Sleep mode status */
00977   if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
00978       HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)   )
00979   {
00980     /* Process unlocked */
00981     __HAL_UNLOCK(hcan);
00982
00983     /* Return function status */
00984     return HAL_ERROR;
00985   }
00986
00987   /* Get tick */
00988   tickstart = HAL_GetTick();
00989
00990   /* Wait the acknowledge */
00991   while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
00992          HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)   )
00993   {
00994     if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
00995     {
00996       hcan->State = HAL_CAN_STATE_TIMEOUT;
00997
00998       /* Process unlocked */
00999       __HAL_UNLOCK(hcan);
01000
01001       return HAL_TIMEOUT;
01002     }
01003   }
01004
01005   /* Change CAN state */
01006   hcan->State = HAL_CAN_STATE_READY;
01007
01008   /* Process unlocked */
01009   __HAL_UNLOCK(hcan);
01010
01011   /* Return function status */
01012   return HAL_OK;
01013 }
01014
01015 /**
01016   * @brief  Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
01017   *         is in the normal mode.
01018   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01019   *         the configuration information for the specified CAN.
01020   * @retval HAL status.
01021   */
01022 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
01023 {
01024   uint32_t tickstart = 0U;
01025
01026   /* Process locked */
01027   __HAL_LOCK(hcan);
01028
01029   /* Change CAN state */
01030   hcan->State = HAL_CAN_STATE_BUSY;
01031
01032   /* Wake up request */
01033   CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
01034
01035   /* Get timeout */
01036   tickstart = HAL_GetTick();
01037
01038   /* Sleep mode status */
01039   while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
01040   {
01041     if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
01042     {
01043       hcan->State= HAL_CAN_STATE_TIMEOUT;
01044       /* Process unlocked */
01045       __HAL_UNLOCK(hcan);
01046       return HAL_TIMEOUT;
01047     }
01048   }
01049   if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
01050   {
01051     /* Process unlocked */
01052     __HAL_UNLOCK(hcan);
01053
01054     /* Return function status */
01055     return HAL_ERROR;
01056   }
01057
01058   /* Change CAN state */
01059   hcan->State = HAL_CAN_STATE_READY;
01060
01061   /* Process unlocked */
01062   __HAL_UNLOCK(hcan);
01063
01064   /* Return function status */
01065   return HAL_OK;
01066 }
01067
01068 /**
01069   * @brief  Handles CAN interrupt request
01070   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01071   *         the configuration information for the specified CAN.
01072   * @retval None
01073   */
01074 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
01075 {
01076   uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
01077   uint32_t errorcode = HAL_CAN_ERROR_NONE;
01078
01079   /* Check Overrun flag for FIFO0 */
01080   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
01081   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
01082   if((tmp1 != 0U) && tmp2)
01083   {
01084     /* Set CAN error code to FOV0 error */
01085     errorcode |= HAL_CAN_ERROR_FOV0;
01086
01087     /* Clear FIFO0 Overrun Flag */
01088     __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
01089   }
01090
01091   /* Check Overrun flag for FIFO1 */
01092   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
01093   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
01094   if((tmp1 != 0U) && tmp2)
01095   {
01096     /* Set CAN error code to FOV1 error */
01097     errorcode |= HAL_CAN_ERROR_FOV1;
01098
01099     /* Clear FIFO1 Overrun Flag */
01100     __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
01101   }
01102
01103   /* Check End of transmission flag */
01104   if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
01105   {
01106     tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
01107     tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
01108     tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
01109     if(tmp1 || tmp2 || tmp3)
01110     {
01111       /* Call transmit function */
01112       CAN_Transmit_IT(hcan);
01113     }
01114   }
01115
01116   tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
01117   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
01118   /* Check End of reception flag for FIFO0 */
01119   if((tmp1 != 0U) && tmp2)
01120   {
01121     /* Call receive function */
01122     CAN_Receive_IT(hcan, CAN_FIFO0);
01123   }
01124
01125   tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
01126   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
01127   /* Check End of reception flag for FIFO1 */
01128   if((tmp1 != 0U) && tmp2)
01129   {
01130     /* Call receive function */
01131     CAN_Receive_IT(hcan, CAN_FIFO1);
01132   }
01133
01134   /* Set error code in handle */
01135   hcan->ErrorCode |= errorcode;
01136
01137   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
01138   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
01139   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01140   /* Check Error Warning Flag */
01141   if(tmp1 && tmp2 && tmp3)
01142   {
01143     /* Set CAN error code to EWG error */
01144     hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
01145     /* No need for clear of Error Warning Flag as read-only */
01146   }
01147
01148   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
01149   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
01150   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01151   /* Check Error Passive Flag */
01152   if(tmp1 && tmp2 && tmp3)
01153   {
01154     /* Set CAN error code to EPV error */
01155     hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
01156     /* No need for clear of Error Passive Flag as read-only */
01157   }
01158
01159   tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
01160   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
01161   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01162   /* Check Bus-Off Flag */
01163   if(tmp1 && tmp2 && tmp3)
01164   {
01165     /* Set CAN error code to BOF error */
01166     hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
01167     /* No need for clear of Bus-Off Flag as read-only */
01168   }
01169
01170   tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
01171   tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
01172   tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
01173   /* Check Last error code Flag */
01174   if((!tmp1) && tmp2 && tmp3)
01175   {
01176     tmp1 = (hcan->Instance->ESR & CAN_ESR_LEC);
01177     switch(tmp1)
01178     {
01179       case(CAN_ESR_LEC_0):
01180           /* Set CAN error code to STF error */
01181           hcan->ErrorCode |= HAL_CAN_ERROR_STF;
01182           break;
01183       case(CAN_ESR_LEC_1):
01184           /* Set CAN error code to FOR error */
01185           hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
01186           break;
01187       case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
01188           /* Set CAN error code to ACK error */
01189           hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
01190           break;
01191       case(CAN_ESR_LEC_2):
01192           /* Set CAN error code to BR error */
01193           hcan->ErrorCode |= HAL_CAN_ERROR_BR;
01194           break;
01195       case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
01196           /* Set CAN error code to BD error */
01197           hcan->ErrorCode |= HAL_CAN_ERROR_BD;
01198           break;
01199       case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
01200           /* Set CAN error code to CRC error */
01201           hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
01202           break;
01203       default:
01204           break;
01205     }
01206
01207     /* Clear Last error code Flag */
01208     CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
01209   }
01210
01211   /* Call the Error call Back in case of Errors */
01212   if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
01213   {
01214     /* Clear ERRI Flag */
01215     hcan->Instance->MSR = CAN_MSR_ERRI;
01216     /* Set the CAN state ready to be able to start again the process */
01217     hcan->State = HAL_CAN_STATE_READY;
01218
01219     /* Disable interrupts: */
01220     /*  - Disable Error warning Interrupt */
01221     /*  - Disable Error passive Interrupt */
01222     /*  - Disable Bus-off Interrupt */
01223     /*  - Disable Last error code Interrupt */
01224     /*  - Disable Error Interrupt */
01225     /*  - Disable FIFO 0 message pending Interrupt */
01226     /*  - Disable FIFO 0 Overrun Interrupt */
01227     /*  - Disable FIFO 1 message pending Interrupt */
01228     /*  - Disable FIFO 1 Overrun Interrupt */
01229     /*  - Disable Transmit mailbox empty Interrupt */
01230     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
01231                                CAN_IT_EPV |
01232                                CAN_IT_BOF |
01233                                CAN_IT_LEC |
01234                                CAN_IT_ERR |
01235                                CAN_IT_FMP0|
01236                                CAN_IT_FOV0|
01237                                CAN_IT_FMP1|
01238                                CAN_IT_FOV1|
01239                                CAN_IT_TME  );
01240
01241     /* Call Error callback function */
01242     HAL_CAN_ErrorCallback(hcan);
01243   }
01244 }
01245
01246 /**
01247   * @brief  Transmission  complete callback in non blocking mode
01248   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01249   *         the configuration information for the specified CAN.
01250   * @retval None
01251   */
01252 __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
01253 {
01254   /* Prevent unused argument(s) compilation warning */
01255   UNUSED(hcan);
01256   /* NOTE : This function Should not be modified, when the callback is needed,
01257             the HAL_CAN_TxCpltCallback can be implemented in the user file
01258    */
01259 }
01260
01261 /**
01262   * @brief  Transmission  complete callback in non blocking mode
01263   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01264   *         the configuration information for the specified CAN.
01265   * @retval None
01266   */
01267 __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
01268 {
01269   /* Prevent unused argument(s) compilation warning */
01270   UNUSED(hcan);
01271   /* NOTE : This function Should not be modified, when the callback is needed,
01272             the HAL_CAN_RxCpltCallback can be implemented in the user file
01273    */
01274 }
01275
01276 /**
01277   * @brief  Error CAN callback.
01278   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01279   *         the configuration information for the specified CAN.
01280   * @retval None
01281   */
01282 __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
01283 {
01284   /* Prevent unused argument(s) compilation warning */
01285   UNUSED(hcan);
01286   /* NOTE : This function Should not be modified, when the callback is needed,
01287             the HAL_CAN_ErrorCallback can be implemented in the user file
01288    */
01289 }
01290
01291 /**
01292   * @}
01293   */
01294
01295 /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
01296  *  @brief   CAN Peripheral State functions
01297  *
01298 @verbatim
01299   ==============================================================================
01300             ##### Peripheral State and Error functions #####
01301   ==============================================================================
01302     [..]
01303     This subsection provides functions allowing to :
01304       (+) Check the CAN state.
01305       (+) Check CAN Errors detected during interrupt process
01306
01307 @endverbatim
01308   * @{
01309   */
01310
01311 /**
01312   * @brief  return the CAN state
01313   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01314   *         the configuration information for the specified CAN.
01315   * @retval HAL state
01316   */
01317 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
01318 {
01319   /* Return CAN state */
01320   return hcan->State;
01321 }
01322
01323 /**
01324   * @brief  Return the CAN error code
01325   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01326   *         the configuration information for the specified CAN.
01327   * @retval CAN Error Code
01328   */
01329 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
01330 {
01331   return hcan->ErrorCode;
01332 }
01333
01334 /**
01335   * @}
01336   */
01337
01338 /**
01339   * @}
01340   */
01341
01342 /** @addtogroup CAN_Private_Functions
01343   * @{
01344   */
01345 /**
01346   * @brief  Initiates and transmits a CAN frame message.
01347   * @param  hcan: pointer to a CAN_HandleTypeDef structure that contains
01348   *         the configuration information for the specified CAN.
01349   * @retval HAL status
01350   */
01351 static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
01352 {
01353   /* Disable Transmit mailbox empty Interrupt */
01354   __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
01355
01356   if(hcan->State == HAL_CAN_STATE_BUSY_TX)
01357   {
01358     /* Disable interrupts: */
01359     /*  - Disable Error warning Interrupt */
01360     /*  - Disable Error passive Interrupt */
01361     /*  - Disable Bus-off Interrupt */
01362     /*  - Disable Last error code Interrupt */
01363     /*  - Disable Error Interrupt */
01364     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
01365                                CAN_IT_EPV |
01366                                CAN_IT_BOF |
01367                                CAN_IT_LEC |
01368                                CAN_IT_ERR);
01369   }
01370
01371   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
01372   {
01373     /* Change CAN state */
01374     hcan->State = HAL_CAN_STATE_BUSY_RX;
01375   }
01376   else
01377   {
01378     /* Change CAN state */
01379     hcan->State = HAL_CAN_STATE_READY;
01380   }
01381
01382   /* Transmission complete callback */
01383   HAL_CAN_TxCpltCallback(hcan);
01384
01385   return HAL_OK;
01386 }
01387
01388 /**
01389   * @brief  Receives a correct CAN frame.
01390   * @param  hcan:       Pointer to a CAN_HandleTypeDef structure that contains
01391   *         the configuration information for the specified CAN.
01392   * @param  FIFONumber: Specify the FIFO number
01393   * @retval HAL status
01394   * @retval None
01395   */
01396 static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
01397 {
01398   /* Get the Id */
01399   hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
01400   if (hcan->pRxMsg->IDE == CAN_ID_STD)
01401   {
01402     hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
01403   }
01404   else
01405   {
01406     hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
01407   }
01408
01409   hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
01410   /* Get the DLC */
01411   hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
01412   /* Get the FIFONumber */
01413   hcan->pRxMsg->FIFONumber = FIFONumber;
01414   /* Get the FMI */
01415   hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
01416   /* Get the data field */
01417   hcan->pRxMsg->Data[0U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
01418   hcan->pRxMsg->Data[1U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
01419   hcan->pRxMsg->Data[2U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
01420   hcan->pRxMsg->Data[3U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
01421   hcan->pRxMsg->Data[4U] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
01422   hcan->pRxMsg->Data[5U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
01423   hcan->pRxMsg->Data[6U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
01424   hcan->pRxMsg->Data[7U] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
01425   /* Release the FIFO */
01426   /* Release FIFO0 */
01427   if (FIFONumber == CAN_FIFO0)
01428   {
01429     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
01430
01431     /* Disable FIFO 0 overrun and message pending Interrupt */
01432     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
01433   }
01434   /* Release FIFO1 */
01435   else /* FIFONumber == CAN_FIFO1 */
01436   {
01437     __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
01438
01439     /* Disable FIFO 1 overrun and message pending Interrupt */
01440     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
01441   }
01442
01443   if(hcan->State == HAL_CAN_STATE_BUSY_RX)
01444   {
01445     /* Disable interrupts: */
01446     /*  - Disable Error warning Interrupt */
01447     /*  - Disable Error passive Interrupt */
01448     /*  - Disable Bus-off Interrupt */
01449     /*  - Disable Last error code Interrupt */
01450     /*  - Disable Error Interrupt */
01451     __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
01452                                CAN_IT_EPV |
01453                                CAN_IT_BOF |
01454                                CAN_IT_LEC |
01455                                CAN_IT_ERR);
01456   }
01457
01458   if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
01459   {
01460     /* Disable CAN state */
01461     hcan->State = HAL_CAN_STATE_BUSY_TX;
01462   }
01463   else
01464   {
01465     /* Change CAN state */
01466     hcan->State = HAL_CAN_STATE_READY;
01467   }
01468
01469   /* Receive complete callback */
01470   HAL_CAN_RxCpltCallback(hcan);
01471
01472   /* Return function status */
01473   return HAL_OK;
01474 }
01475
01476 /**
01477   * @}
01478   */
01479 #endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
01480
01481 #endif /* HAL_CAN_MODULE_ENABLED */
01482 /**
01483   * @}
01484   */
01485
01486 /**
01487   * @}
01488   */
01489
01490 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_can.h Source File

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stm32f1xx_hal_can.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_can.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of CAN HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_CAN_H
00040 #define __STM32F1xx_HAL_CAN_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
00047     defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f1xx_hal_def.h"
00051
00052 /** @addtogroup STM32F1xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup CAN
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup CAN_Exported_Types CAN Exported Types
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  HAL State structures definition
00067   */
00068 typedef enum
00069 {
00070   HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
00071   HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
00072   HAL_CAN_STATE_BUSY              = 0x02U,  /*!< CAN process is ongoing              */
00073   HAL_CAN_STATE_BUSY_TX           = 0x12U,  /*!< CAN process is ongoing              */
00074   HAL_CAN_STATE_BUSY_RX           = 0x22U,  /*!< CAN process is ongoing              */
00075   HAL_CAN_STATE_BUSY_TX_RX        = 0x32U,  /*!< CAN process is ongoing              */
00076   HAL_CAN_STATE_TIMEOUT           = 0x03U,  /*!< CAN in Timeout state                */
00077   HAL_CAN_STATE_ERROR             = 0x04U   /*!< CAN error state                     */
00078
00079 }HAL_CAN_StateTypeDef;
00080
00081 /**
00082   * @brief  CAN init structure definition
00083   */
00084 typedef struct
00085 {
00086   uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
00087                             This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
00088
00089   uint32_t Mode;       /*!< Specifies the CAN operating mode.
00090                             This parameter can be a value of @ref CAN_operating_mode */
00091
00092   uint32_t SJW;        /*!< Specifies the maximum number of time quanta
00093                             the CAN hardware is allowed to lengthen or
00094                             shorten a bit to perform resynchronization.
00095                             This parameter can be a value of @ref CAN_synchronisation_jump_width */
00096
00097   uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
00098                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
00099
00100   uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
00101                             This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
00102
00103   uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
00104                             This parameter can be set to ENABLE or DISABLE. */
00105
00106   uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
00107                             This parameter can be set to ENABLE or DISABLE */
00108
00109   uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
00110                             This parameter can be set to ENABLE or DISABLE */
00111
00112   uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
00113                             This parameter can be set to ENABLE or DISABLE */
00114
00115   uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
00116                             This parameter can be set to ENABLE or DISABLE */
00117
00118   uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
00119                             This parameter can be set to ENABLE or DISABLE */
00120 }CAN_InitTypeDef;
00121
00122 /**
00123   * @brief  CAN Tx message structure definition
00124   */
00125 typedef struct
00126 {
00127   uint32_t StdId;    /*!< Specifies the standard identifier.
00128                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
00129
00130   uint32_t ExtId;    /*!< Specifies the extended identifier.
00131                           This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
00132
00133   uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
00134                           This parameter can be a value of @ref CAN_Identifier_Type */
00135
00136   uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
00137                           This parameter can be a value of @ref CAN_remote_transmission_request */
00138
00139   uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
00140                           This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
00141
00142   uint8_t Data[8];   /*!< Contains the data to be transmitted.
00143                           This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00144
00145 }CanTxMsgTypeDef;
00146
00147 /**
00148   * @brief  CAN Rx message structure definition
00149   */
00150 typedef struct
00151 {
00152   uint32_t StdId;       /*!< Specifies the standard identifier.
00153                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
00154
00155   uint32_t ExtId;       /*!< Specifies the extended identifier.
00156                              This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
00157
00158   uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
00159                              This parameter can be a value of @ref CAN_Identifier_Type */
00160
00161   uint32_t RTR;         /*!< Specifies the type of frame for the received message.
00162                              This parameter can be a value of @ref CAN_remote_transmission_request */
00163
00164   uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
00165                              This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
00166
00167   uint8_t Data[8];      /*!< Contains the data to be received.
00168                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00169
00170   uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
00171                              This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
00172
00173   uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
00174                              This parameter can be CAN_FIFO0 or CAN_FIFO1 */
00175
00176 }CanRxMsgTypeDef;
00177
00178 /**
00179   * @brief  CAN handle Structure definition
00180   */
00181 typedef struct
00182 {
00183   CAN_TypeDef                 *Instance;  /*!< Register base address          */
00184
00185   CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
00186
00187   CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
00188
00189   CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
00190
00191   __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
00192
00193   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
00194
00195   __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
00196
00197 }CAN_HandleTypeDef;
00198
00199 /**
00200   * @}
00201   */
00202
00203 /* Exported constants --------------------------------------------------------*/
00204 /** @defgroup CAN_Exported_Constants CAN Exported Constants
00205   * @{
00206   */
00207
00208 /** @defgroup CAN_Error_Code CAN Error Code
00209   * @{
00210   */
00211 #define   HAL_CAN_ERROR_NONE      0x00U    /*!< No error             */
00212 #define   HAL_CAN_ERROR_EWG       0x01U    /*!< EWG error            */
00213 #define   HAL_CAN_ERROR_EPV       0x02U    /*!< EPV error            */
00214 #define   HAL_CAN_ERROR_BOF       0x04U    /*!< BOF error            */
00215 #define   HAL_CAN_ERROR_STF       0x08U    /*!< Stuff error          */
00216 #define   HAL_CAN_ERROR_FOR       0x10U    /*!< Form error           */
00217 #define   HAL_CAN_ERROR_ACK       0x20U    /*!< Acknowledgment error */
00218 #define   HAL_CAN_ERROR_BR        0x40U    /*!< Bit recessive        */
00219 #define   HAL_CAN_ERROR_BD        0x80U    /*!< LEC dominant         */
00220 #define   HAL_CAN_ERROR_CRC       0x100U   /*!< LEC transfer error   */
00221 #define   HAL_CAN_ERROR_FOV0      0x200U   /*!< FIFO0 overrun error  */
00222 #define   HAL_CAN_ERROR_FOV1      0x400U   /*!< FIFO1 overrun error  */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup CAN_InitStatus CAN initialization Status
00228   * @{
00229   */
00230 #define CAN_INITSTATUS_FAILED       0x00000000U  /*!< CAN initialization failed */
00231 #define CAN_INITSTATUS_SUCCESS      0x00000001U  /*!< CAN initialization OK */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup CAN_operating_mode CAN Operating Mode
00237   * @{
00238   */
00239 #define CAN_MODE_NORMAL             0x00000000U                                /*!< Normal mode   */
00240 #define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
00241 #define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
00242 #define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
00248   * @{
00249   */
00250 #define CAN_SJW_1TQ                 0x00000000U                /*!< 1 time quantum */
00251 #define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
00252 #define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
00253 #define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
00259   * @{
00260   */
00261 #define CAN_BS1_1TQ                 0x00000000U                                                  /*!< 1 time quantum  */
00262 #define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
00263 #define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
00264 #define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
00265 #define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
00266 #define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
00267 #define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
00268 #define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
00269 #define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
00270 #define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
00271 #define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
00272 #define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
00273 #define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
00274 #define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
00275 #define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
00276 #define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
00277 /**
00278   * @}
00279   */
00280
00281 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
00282   * @{
00283   */
00284 #define CAN_BS2_1TQ                 0x00000000U                                  /*!< 1 time quantum */
00285 #define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
00286 #define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
00287 #define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
00288 #define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
00289 #define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
00290 #define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
00291 #define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
00292 /**
00293   * @}
00294   */
00295
00296 /** @defgroup CAN_filter_mode  CAN Filter Mode
00297   * @{
00298   */
00299 #define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
00300 #define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
00301 /**
00302   * @}
00303   */
00304
00305 /** @defgroup CAN_filter_scale CAN Filter Scale
00306   * @{
00307   */
00308 #define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
00309 #define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
00310 /**
00311   * @}
00312   */
00313
00314 /** @defgroup CAN_filter_FIFO CAN Filter FIFO
00315   * @{
00316   */
00317 #define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
00318 #define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup CAN_Identifier_Type CAN Identifier Type
00324   * @{
00325   */
00326 #define CAN_ID_STD                  0x00000000U  /*!< Standard Id */
00327 #define CAN_ID_EXT                  0x00000004U  /*!< Extended Id */
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
00333   * @{
00334   */
00335 #define CAN_RTR_DATA                0x00000000U  /*!< Data frame */
00336 #define CAN_RTR_REMOTE              0x00000002U  /*!< Remote frame */
00337 /**
00338   * @}
00339   */
00340
00341 /** @defgroup CAN_transmit_constants CAN Transmit Constants
00342   * @{
00343   */
00344 #define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
00345 /**
00346   * @}
00347   */
00348
00349 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
00350   * @{
00351   */
00352 #define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
00353 #define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
00354 /**
00355   * @}
00356   */
00357
00358 /** @defgroup CAN_flags CAN Flags
00359   * @{
00360   */
00361 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
00362    and CAN_ClearFlag() functions. */
00363 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
00364    CAN_GetFlagStatus() function.  */
00365
00366 /* Transmit Flags */
00367 #define CAN_FLAG_RQCP0             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))  /*!< Request MailBox0 flag         */
00368 #define CAN_FLAG_RQCP1             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION))  /*!< Request MailBox1 flag         */
00369 #define CAN_FLAG_RQCP2             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION))  /*!< Request MailBox2 flag         */
00370 #define CAN_FLAG_TXOK0             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION))  /*!< Transmission OK MailBox0 flag */
00371 #define CAN_FLAG_TXOK1             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION))  /*!< Transmission OK MailBox1 flag */
00372 #define CAN_FLAG_TXOK2             ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION))  /*!< Transmission OK MailBox2 flag */
00373 #define CAN_FLAG_TME0              ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION))   /*!< Transmit mailbox 0 empty flag */
00374 #define CAN_FLAG_TME1              ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION))   /*!< Transmit mailbox 0 empty flag */
00375 #define CAN_FLAG_TME2              ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION))   /*!< Transmit mailbox 0 empty flag */
00376
00377 /* Receive Flags */
00378 #define CAN_FLAG_FF0               ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION))  /*!< FIFO 0 Full flag    */
00379 #define CAN_FLAG_FOV0              ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
00380
00381 #define CAN_FLAG_FF1               ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION))  /*!< FIFO 1 Full flag    */
00382 #define CAN_FLAG_FOV1              ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
00383
00384 /* Operating Mode Flags */
00385 #define CAN_FLAG_WKU               ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION))    /*!< Wake up flag           */
00386 #define CAN_FLAG_SLAK              ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION))   /*!< Sleep acknowledge flag */
00387 #define CAN_FLAG_SLAKI             ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION))  /*!< Sleep acknowledge flag */
00388
00389 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
00390          In this case the SLAK bit can be polled.*/
00391
00392 /* Error Flags */
00393 #define CAN_FLAG_EWG               ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION))    /*!< Error warning flag   */
00394 #define CAN_FLAG_EPV               ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION))    /*!< Error passive flag   */
00395 #define CAN_FLAG_BOF               ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION))    /*!< Bus-Off flag         */
00396
00397 /**
00398   * @}
00399   */
00400
00401 /** @defgroup CAN_Interrupts CAN Interrupts
00402   * @{
00403   */
00404 #define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
00405
00406 /* Receive Interrupts */
00407 #define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
00408 #define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
00409 #define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
00410 #define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
00411 #define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
00412 #define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
00413
00414 /* Operating Mode Interrupts */
00415 #define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
00416 #define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
00417
00418 /* Error Interrupts */
00419 #define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
00420 #define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
00421 #define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
00422 #define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
00423 #define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
00424 /**
00425   * @}
00426   */
00427
00428 /**
00429   * @}
00430   */
00431
00432 /** @defgroup CAN_Private_Constants CAN Private Constants
00433   * @{
00434   */
00435
00436 /* CAN intermediate shift values used for CAN flags */
00437 #define TSR_REGISTER_INDEX      0x5U
00438 #define RF0R_REGISTER_INDEX     0x2U
00439 #define RF1R_REGISTER_INDEX     0x4U
00440 #define MSR_REGISTER_INDEX      0x1U
00441 #define ESR_REGISTER_INDEX      0x3U
00442
00443 /* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
00444 /* Transmit Flags */
00445 #define CAN_TSR_RQCP0_BIT_POSITION     0x00000000U
00446 #define CAN_TSR_RQCP1_BIT_POSITION     0x00000008U
00447 #define CAN_TSR_RQCP2_BIT_POSITION     0x00000010U
00448 #define CAN_TSR_TXOK0_BIT_POSITION     0x00000001U
00449 #define CAN_TSR_TXOK1_BIT_POSITION     0x00000009U
00450 #define CAN_TSR_TXOK2_BIT_POSITION     0x00000011U
00451 #define CAN_TSR_TME0_BIT_POSITION      0x0000001AU
00452 #define CAN_TSR_TME1_BIT_POSITION      0x0000001BU
00453 #define CAN_TSR_TME2_BIT_POSITION      0x0000001CU
00454
00455 /* Receive Flags */
00456 #define CAN_RF0R_FF0_BIT_POSITION      0x00000003U
00457 #define CAN_RF0R_FOV0_BIT_POSITION     0x00000004U
00458
00459 #define CAN_RF1R_FF1_BIT_POSITION      0x00000003U
00460 #define CAN_RF1R_FOV1_BIT_POSITION     0x00000004U
00461
00462 /* Operating Mode Flags */
00463 #define CAN_MSR_WKU_BIT_POSITION       0x00000003U
00464 #define CAN_MSR_SLAK_BIT_POSITION      0x00000001U
00465 #define CAN_MSR_SLAKI_BIT_POSITION     0x00000004U
00466
00467 /* Error Flags */
00468 #define CAN_ESR_EWG_BIT_POSITION       0x00000000U
00469 #define CAN_ESR_EPV_BIT_POSITION       0x00000001U
00470 #define CAN_ESR_BOF_BIT_POSITION       0x00000002U
00471
00472 /* Mask used by macro to get/clear CAN flags*/
00473 #define CAN_FLAG_MASK                  0x000000FFU
00474
00475 /* Mailboxes definition */
00476 #define CAN_TXMAILBOX_0   ((uint8_t)0x00)
00477 #define CAN_TXMAILBOX_1   ((uint8_t)0x01)
00478 #define CAN_TXMAILBOX_2   ((uint8_t)0x02)
00479 /**
00480   * @}
00481   */
00482
00483 /* Exported macros -----------------------------------------------------------*/
00484 /** @defgroup CAN_Exported_Macros CAN Exported Macros
00485   * @{
00486   */
00487
00488 /** @brief  Reset CAN handle state
00489   * @param  __HANDLE__: CAN handle.
00490   * @retval None
00491   */
00492 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
00493
00494 /**
00495   * @brief  Enable the specified CAN interrupts
00496   * @param  __HANDLE__: CAN handle.
00497   * @param  __INTERRUPT__: CAN Interrupt.
00498   *         This parameter can be one of the following values:
00499   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
00500   *            @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
00501   *            @arg CAN_IT_FF0 : FIFO 0 full interrupt
00502   *            @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
00503   *            @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
00504   *            @arg CAN_IT_FF1 : FIFO 1 full interrupt
00505   *            @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
00506   *            @arg CAN_IT_WKU : Wake-up interrupt
00507   *            @arg CAN_IT_SLK : Sleep acknowledge interrupt
00508   *            @arg CAN_IT_EWG : Error warning interrupt
00509   *            @arg CAN_IT_EPV : Error passive interrupt
00510   *            @arg CAN_IT_BOF : Bus-off interrupt
00511   *            @arg CAN_IT_LEC : Last error code interrupt
00512   *            @arg CAN_IT_ERR : Error Interrupt
00513   * @retval None.
00514   */
00515 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
00516
00517 /**
00518   * @brief  Disable the specified CAN interrupts
00519   * @param  __HANDLE__: CAN handle.
00520   * @param  __INTERRUPT__: CAN Interrupt.
00521   *         This parameter can be one of the following values:
00522   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
00523   *            @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
00524   *            @arg CAN_IT_FF0 : FIFO 0 full interrupt
00525   *            @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
00526   *            @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
00527   *            @arg CAN_IT_FF1 : FIFO 1 full interrupt
00528   *            @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
00529   *            @arg CAN_IT_WKU : Wake-up interrupt
00530   *            @arg CAN_IT_SLK : Sleep acknowledge interrupt
00531   *            @arg CAN_IT_EWG : Error warning interrupt
00532   *            @arg CAN_IT_EPV : Error passive interrupt
00533   *            @arg CAN_IT_BOF : Bus-off interrupt
00534   *            @arg CAN_IT_LEC : Last error code interrupt
00535   *            @arg CAN_IT_ERR : Error Interrupt
00536   * @retval None.
00537   */
00538 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
00539
00540 /**
00541   * @brief  Return the number of pending received messages.
00542   * @param  __HANDLE__: CAN handle.
00543   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00544   * @retval The number of pending message.
00545   */
00546 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
00547 ((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
00548
00549 /** @brief  Check whether the specified CAN flag is set or not.
00550   * @param  __HANDLE__: specifies the CAN Handle.
00551   * @param  __FLAG__: specifies the flag to check.
00552   *         This parameter can be one of the following values:
00553   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
00554   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
00555   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
00556   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
00557   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
00558   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
00559   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
00560   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
00561   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
00562   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
00563   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
00564   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
00565   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
00566   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
00567   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
00568   *            @arg CAN_FLAG_WKU: Wake up Flag
00569   *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
00570   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
00571   *            @arg CAN_FLAG_EWG: Error Warning Flag
00572   *            @arg CAN_FLAG_EPV: Error Passive Flag
00573   *            @arg CAN_FLAG_BOF: Bus-Off Flag
00574   * @retval The new state of __FLAG__ (TRUE or FALSE).
00575   */
00576 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
00577 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00578  (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00579  (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00580  (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00581  ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
00582
00583 /** @brief  Clear the specified CAN pending flag.
00584   * @param  __HANDLE__: specifies the CAN Handle.
00585   * @param  __FLAG__: specifies the flag to check.
00586   *         This parameter can be one of the following values:
00587   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
00588   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
00589   *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
00590   *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
00591   *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
00592   *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
00593   *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
00594   *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
00595   *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
00596   *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
00597   *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
00598   *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
00599   *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
00600   *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
00601   *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
00602   *            @arg CAN_FLAG_WKU: Wake up Flag
00603   *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
00604   * @retval The new state of __FLAG__ (TRUE or FALSE).
00605   */
00606 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
00607 ((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00608  (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00609  (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
00610  (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR)  = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
00611
00612 /** @brief  Check if the specified CAN interrupt source is enabled or disabled.
00613   * @param  __HANDLE__: specifies the CAN Handle.
00614   * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
00615   *         This parameter can be one of the following values:
00616   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
00617   *            @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
00618   *            @arg CAN_IT_FF0 : FIFO 0 full interrupt
00619   *            @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
00620   *            @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
00621   *            @arg CAN_IT_FF1 : FIFO 1 full interrupt
00622   *            @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
00623   *            @arg CAN_IT_WKU : Wake-up interrupt
00624   *            @arg CAN_IT_SLK : Sleep acknowledge interrupt
00625   *            @arg CAN_IT_EWG : Error warning interrupt
00626   *            @arg CAN_IT_EPV : Error passive interrupt
00627   *            @arg CAN_IT_BOF : Bus-off interrupt
00628   *            @arg CAN_IT_LEC : Last error code interrupt
00629   *            @arg CAN_IT_ERR : Error Interrupt
00630   * @retval The new state of __IT__ (TRUE or FALSE).
00631   */
00632 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00633
00634 /**
00635   * @brief  Check the transmission status of a CAN Frame.
00636   * @param  __HANDLE__: specifies the CAN Handle.
00637   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
00638   * @retval The new status of transmission  (TRUE or FALSE).
00639   */
00640 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
00641 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
00642  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
00643  ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
00644
00645 /**
00646   * @brief  Release the specified receive FIFO.
00647   * @param  __HANDLE__: CAN handle.
00648   * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
00649   * @retval None.
00650   */
00651 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
00652 ((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
00653
00654 /**
00655   * @brief  Cancel a transmit request.
00656   * @param  __HANDLE__: specifies the CAN Handle.
00657   * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
00658   * @retval None.
00659   */
00660 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
00661 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
00662  ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
00663  ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
00664
00665 /**
00666   * @brief  Enable or disables the DBG Freeze for CAN.
00667   * @param  __HANDLE__: specifies the CAN Handle.
00668   * @param  __NEWSTATE__: new state of the CAN peripheral.
00669   *         This parameter can be: ENABLE (CAN reception/transmission is frozen
00670   *         during debug. Reception FIFOs can still be accessed/controlled normally)
00671   *         or DISABLE (CAN is working during debug).
00672   * @retval None
00673   */
00674 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
00675 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
00676
00677 /**
00678   * @}
00679   */
00680
00681 /* Include CAN HAL Extension module */
00682 #include "stm32f1xx_hal_can_ex.h"
00683
00684 /* Exported functions --------------------------------------------------------*/
00685 /** @addtogroup CAN_Exported_Functions
00686   * @{
00687   */
00688
00689 /** @addtogroup CAN_Exported_Functions_Group1
00690   * @brief    Initialization and Configuration functions
00691   * @{
00692   */
00693 /* Initialization and de-initialization functions *****************************/
00694 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
00695 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
00696 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
00697 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
00698 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
00699 /**
00700   * @}
00701   */
00702
00703 /** @addtogroup CAN_Exported_Functions_Group2
00704   * @brief    I/O operation functions
00705   * @{
00706   */
00707 /* I/O operation functions *****************************************************/
00708 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
00709 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
00710 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
00711 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
00712 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
00713 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
00714 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
00715 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
00716 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
00717 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
00718 /**
00719   * @}
00720   */
00721
00722 /** @addtogroup CAN_Exported_Functions_Group3
00723   * @brief   CAN Peripheral State functions
00724   * @{
00725   */
00726 /* Peripheral State and Error functions ***************************************/
00727 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
00728 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
00729 /**
00730   * @}
00731   */
00732
00733 /**
00734   * @}
00735   */
00736
00737 /* Private macros --------------------------------------------------------*/
00738 /** @defgroup CAN_Private_Macros   CAN Private Macros
00739   * @{
00740   */
00741
00742 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
00743                            ((MODE) == CAN_MODE_LOOPBACK)|| \
00744                            ((MODE) == CAN_MODE_SILENT) || \
00745                            ((MODE) == CAN_MODE_SILENT_LOOPBACK))
00746 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
00747                          ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
00748 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
00749 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
00750 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
00751
00752 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
00753                                   ((MODE) == CAN_FILTERMODE_IDLIST))
00754 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
00755                                     ((SCALE) == CAN_FILTERSCALE_32BIT))
00756 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
00757                                   ((FIFO) == CAN_FILTER_FIFO1))
00758 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
00759
00760 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
00761 #define IS_CAN_STDID(STDID)   ((STDID) <= 0x00007FFU)
00762 #define IS_CAN_EXTID(EXTID)   ((EXTID) <= 0x1FFFFFFFU)
00763 #define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
00764
00765 #define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
00766                                 ((IDTYPE) == CAN_ID_EXT))
00767 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
00768 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
00769
00770 /**
00771   * @}
00772   */
00773
00774 /**
00775   * @}
00776   */
00777
00778 /**
00779   * @}
00780   */
00781
00782 #endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
00783
00784 #ifdef __cplusplus
00785 }
00786 #endif
00787
00788 #endif /* __STM32F1xx_HAL_CAN_H */
00789
00790
00791 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_can_ex.h Source File

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stm32f1xx_hal_can_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_can_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of CAN HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_CAN_EX_H
00040 #define __STM32F1xx_HAL_CAN_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
00047     defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f1xx_hal_def.h"
00051
00052 /** @addtogroup STM32F1xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @defgroup CANEx CANEx
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061
00062 /**
00063   * @brief  CAN filter configuration structure definition
00064   */
00065 /* CAN filter banks differences over STM32F1 devices:                         */
00066 /* - STM32F1 Connectivity line: 28 filter banks shared between CAN1 and CAN2  */
00067 /* - Other STM32F10x devices:   14 filter banks                               */
00068
00069 typedef struct
00070 {
00071   uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
00072                                        configuration, first one for a 16-bit configuration).
00073                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00074
00075   uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
00076                                        configuration, second one for a 16-bit configuration).
00077                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00078
00079   uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
00080                                        according to the mode (MSBs for a 32-bit configuration,
00081                                        first one for a 16-bit configuration).
00082                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00083
00084   uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
00085                                        according to the mode (LSBs for a 32-bit configuration,
00086                                        second one for a 16-bit configuration).
00087                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
00088
00089   uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
00090                                        This parameter can be a value of @ref CAN_filter_FIFO */
00091 #if defined(STM32F105xC) || defined(STM32F107xC)
00092   uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
00093                                        This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
00094 #else
00095   uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
00096                                        This parameter must be a number between Min_Data = 0 and Max_Data = 13. */
00097 #endif /* STM32F105xC || STM32F107xC */
00098   uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
00099                                        This parameter can be a value of @ref CAN_filter_mode */
00100
00101   uint32_t FilterScale;           /*!< Specifies the filter scale.
00102                                        This parameter can be a value of @ref CAN_filter_scale */
00103
00104   uint32_t FilterActivation;      /*!< Enable or disable the filter.
00105                                        This parameter can be set to ENABLE or DISABLE. */
00106
00107   uint32_t BankNumber;            /*!< Select the start slave bank filter
00108                                        This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
00109
00110 }CAN_FilterConfTypeDef;
00111
00112 /* Exported constants --------------------------------------------------------*/
00113 /* Exported macro ------------------------------------------------------------*/
00114 /* Private macro -------------------------------------------------------------*/
00115
00116 /** @defgroup CANEx_Private_Macros CAN Extended Private Macros
00117   * @{
00118   */
00119 #if defined(STM32F105xC) || defined(STM32F107xC)
00120 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
00121 #else
00122 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13U)
00123 #endif /* STM32F105xC || STM32F107xC */
00124
00125 /**
00126   * @}
00127   */
00128
00129
00130 /**
00131   * @}
00132   */
00133
00134 /**
00135   * @}
00136   */
00137
00138 #endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC    */
00139
00140 #ifdef __cplusplus
00141 }
00142 #endif
00143
00144 #endif /* __STM32F1xx_HAL_CAN_EX_H */
00145
00146 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_cec.c Source File

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stm32f1xx_hal_cec.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_cec.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   CEC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the High Definition Multimedia Interface
00010   *          Consumer Electronics Control Peripheral (CEC).
00011   *           + Initialization and de-initialization function
00012   *           + IO operation function
00013   *           + Peripheral Control function
00014   *
00015   *
00016   @verbatim
00017  ===============================================================================
00018                         ##### How to use this driver #####
00019  ===============================================================================
00020     [..]
00021     The CEC HAL driver can be used as follow:
00022
00023     (#) Declare a CEC_HandleTypeDef handle structure.
00024     (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
00025         (##) Enable the CEC interface clock.
00026         (##) CEC pins configuration:
00027             (+++) Enable the clock for the CEC GPIOs.
00028             (+++) Configure these CEC pins as alternate function pull-up.
00029         (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
00030              and HAL_CEC_Receive_IT() APIs):
00031             (+++) Configure the CEC interrupt priority.
00032             (+++) Enable the NVIC CEC IRQ handle.
00033             (+++) The specific CEC interrupts (Transmission complete interrupt,
00034                   RXNE interrupt and Error Interrupts) will be managed using the macros
00035                   __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
00036                   and receive process.
00037
00038     (#) Program the Bit Timing Error Mode and the Bit Period Error Mode in the hcec Init structure.
00039
00040     (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
00041
00042   [..]
00043     (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
00044         by calling the customed HAL_CEC_MspInit() API.
00045
00046   @endverbatim
00047   ******************************************************************************
00048   * @attention
00049   *
00050   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00051   *
00052   * Redistribution and use in source and binary forms, with or without modification,
00053   * are permitted provided that the following conditions are met:
00054   *   1. Redistributions of source code must retain the above copyright notice,
00055   *      this list of conditions and the following disclaimer.
00056   *   2. Redistributions in binary form must reproduce the above copyright notice,
00057   *      this list of conditions and the following disclaimer in the documentation
00058   *      and/or other materials provided with the distribution.
00059   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00060   *      may be used to endorse or promote products derived from this software
00061   *      without specific prior written permission.
00062   *
00063   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00064   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00065   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00066   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00067   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00068   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00069   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00070   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00071   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00072   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00073   *
00074   ******************************************************************************
00075   */
00076
00077 /* Includes ------------------------------------------------------------------*/
00078 #include "stm32f1xx_hal.h"
00079
00080 #ifdef HAL_CEC_MODULE_ENABLED
00081
00082 #if defined(STM32F100xB) || defined(STM32F100xE)
00083
00084 /** @addtogroup STM32F1xx_HAL_Driver
00085   * @{
00086   */
00087
00088 /** @defgroup CEC CEC
00089   * @brief HAL CEC module driver
00090   * @{
00091   */
00092
00093 /* Private typedef -----------------------------------------------------------*/
00094 /* Private define ------------------------------------------------------------*/
00095 /** @defgroup CEC_Private_Constants CEC Private Constants
00096   * @{
00097   */
00098 #define CEC_CFGR_FIELDS (CEC_CFGR_BTEM | CEC_CFGR_BPEM )
00099 #define CEC_FLAG_TRANSMIT_MASK (CEC_FLAG_TSOM|CEC_FLAG_TEOM|CEC_FLAG_TBTRF)
00100 #define CEC_FLAG_RECEIVE_MASK (CEC_FLAG_RSOM|CEC_FLAG_REOM|CEC_FLAG_RBTF)
00101 #define CEC_ESR_ALL_ERROR (CEC_ESR_BTE|CEC_ESR_BPE|CEC_ESR_RBTFE|CEC_ESR_SBE|CEC_ESR_ACKE|CEC_ESR_LINE|CEC_ESR_TBTFE)
00102 #define CEC_RXXFERSIZE_INITIALIZE 0xFFFF /*!< Value used to initialise the RxXferSize of the handle */
00103 /**
00104   * @}
00105   */
00106
00107 /* Private macro -------------------------------------------------------------*/
00108 /* Private variables ---------------------------------------------------------*/
00109 /* Private function prototypes -----------------------------------------------*/
00110 /** @defgroup CEC_Private_Functions CEC Private Functions
00111   * @{
00112   */
00113 static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
00114 static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
00115 /**
00116   * @}
00117   */
00118
00119 /* Exported functions ---------------------------------------------------------*/
00120
00121 /** @defgroup CEC_Exported_Functions CEC Exported Functions
00122   * @{
00123   */
00124
00125 /** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
00126   *  @brief    Initialization and Configuration functions
00127   *
00128 @verbatim
00129 ===============================================================================
00130             ##### Initialization and Configuration functions #####
00131  ===============================================================================
00132     [..]
00133     This subsection provides a set of functions allowing to initialize the CEC
00134       (+) The following parameters need to be configured:
00135         (++) TimingErrorFree
00136         (++) PeriodErrorFree
00137         (++) InitiatorAddress
00138
00139 @endverbatim
00140   * @{
00141   */
00142
00143 /**
00144   * @brief Initializes the CEC mode according to the specified
00145   *         parameters in the CEC_InitTypeDef and creates the associated handle .
00146   * @param hcec: CEC handle
00147   * @retval HAL status
00148   */
00149 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
00150 {
00151   /* Check the CEC handle allocation */
00152   if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
00153   {
00154     return HAL_ERROR;
00155   }
00156
00157   /* Check the parameters */
00158   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00159   assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(hcec->Init.TimingErrorFree));
00160   assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(hcec->Init.PeriodErrorFree));
00161   assert_param(IS_CEC_ADDRESS(hcec->Init.OwnAddress));
00162
00163   if(hcec->gState == HAL_CEC_STATE_RESET)
00164   {
00165     /* Allocate lock resource and initialize it */
00166     hcec->Lock = HAL_UNLOCKED;
00167     /* Init the low level hardware : GPIO, CLOCK */
00168     HAL_CEC_MspInit(hcec);
00169   }
00170   hcec->gState = HAL_CEC_STATE_BUSY;
00171
00172   /* Disable the Peripheral */
00173   __HAL_CEC_DISABLE(hcec);
00174
00175   /* Write to CEC Control Register */
00176   MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree | hcec->Init.PeriodErrorFree);
00177
00178   /* Write to CEC Own Address Register */
00179   MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
00180
00181   /* Configure the prescaler to generate the required 50 microseconds time base.*/
00182   MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50U * (HAL_RCC_GetPCLK1Freq()/1000000U) - 1U);
00183
00184   /* Enable the following CEC Interrupt */
00185   __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE);
00186
00187   /* Enable the CEC Peripheral */
00188   __HAL_CEC_ENABLE(hcec);
00189
00190   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00191   hcec->gState = HAL_CEC_STATE_READY;
00192   hcec->RxState = HAL_CEC_STATE_READY;
00193
00194   return HAL_OK;
00195 }
00196
00197 /**
00198   * @brief DeInitializes the CEC peripheral
00199   * @param hcec: CEC handle
00200   * @retval HAL status
00201   */
00202 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
00203 {
00204   /* Check the CEC handle allocation */
00205   if(hcec == NULL)
00206   {
00207     return HAL_ERROR;
00208   }
00209
00210   /* Check the parameters */
00211   assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
00212
00213   hcec->gState = HAL_CEC_STATE_BUSY;
00214
00215   /* DeInit the low level hardware */
00216   HAL_CEC_MspDeInit(hcec);
00217
00218   __HAL_RCC_CEC_FORCE_RESET();
00219   __HAL_RCC_CEC_RELEASE_RESET();
00220
00221   hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00222   hcec->gState = HAL_CEC_STATE_RESET;
00223   hcec->RxState = HAL_CEC_STATE_RESET;
00224
00225   /* Process Unlock */
00226   __HAL_UNLOCK(hcec);
00227
00228   return HAL_OK;
00229 }
00230
00231 /**
00232   * @brief Initializes the Own Address of the CEC device
00233   * @param hcec: CEC handle
00234   * @param  CEC_OwnAddress: The CEC own address.
00235   * @retval HAL status
00236   */
00237 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
00238 {
00239   /* Check the parameters */
00240   assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
00241
00242   if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
00243   {
00244     /* Process Locked */
00245     __HAL_LOCK(hcec);
00246
00247     hcec->gState = HAL_CEC_STATE_BUSY;
00248
00249     /* Disable the Peripheral */
00250     __HAL_CEC_DISABLE(hcec);
00251
00252     if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
00253     {
00254        MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
00255     }
00256     else
00257     {
00258        CLEAR_BIT(hcec->Instance->OAR, CEC_OAR_OA);
00259     }
00260
00261     hcec->gState = HAL_CEC_STATE_READY;
00262     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00263
00264     /* Process Unlocked */
00265     __HAL_UNLOCK(hcec);
00266
00267     /* Enable the Peripheral */
00268     __HAL_CEC_ENABLE(hcec);
00269
00270     return  HAL_OK;
00271   }
00272   else
00273   {
00274     return HAL_BUSY;
00275   }
00276 }
00277
00278 /**
00279   * @brief CEC MSP Init
00280   * @param hcec: CEC handle
00281   * @retval None
00282   */
00283  __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
00284 {
00285   /* Prevent unused argument(s) compilation warning */
00286   UNUSED(hcec);
00287   /* NOTE : This function should not be modified, when the callback is needed,
00288             the HAL_CEC_MspInit can be implemented in the user file
00289    */
00290 }
00291
00292 /**
00293   * @brief CEC MSP DeInit
00294   * @param hcec: CEC handle
00295   * @retval None
00296   */
00297  __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
00298 {
00299   /* Prevent unused argument(s) compilation warning */
00300   UNUSED(hcec);
00301   /* NOTE : This function should not be modified, when the callback is needed,
00302             the HAL_CEC_MspDeInit can be implemented in the user file
00303    */
00304 }
00305
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
00311   *  @brief CEC Transmit/Receive functions
00312   *
00313 @verbatim
00314  ===============================================================================
00315                       ##### IO operation functions #####
00316  ===============================================================================
00317     [..]
00318     This subsection provides a set of functions allowing to manage the CEC data transfers.
00319
00320     (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
00321         logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
00322
00323     (#) The communication is performed using Interrupts.
00324            These API's return the HAL status.
00325            The end of the data processing will be indicated through the
00326            dedicated CEC IRQ when using Interrupt mode.
00327            The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
00328            will be executed respectively at the end of the transmit or Receive process
00329            The HAL_CEC_ErrorCallback() user callback will be executed when a communication
00330            error is detected
00331
00332     (#) API's with Interrupt are :
00333          (+) HAL_CEC_Transmit_IT()
00334          (+) HAL_CEC_IRQHandler()
00335
00336     (#) A set of User Callbacks are provided:
00337          (+) HAL_CEC_TxCpltCallback()
00338          (+) HAL_CEC_RxCpltCallback()
00339          (+) HAL_CEC_ErrorCallback()
00340
00341 @endverbatim
00342   * @{
00343   */
00344
00345 /**
00346   * @brief Send data in interrupt mode
00347   * @param hcec: CEC handle
00348   * @param InitiatorAddress: Initiator address
00349   * @param DestinationAddress: destination logical address
00350   * @param pData: pointer to input byte data buffer
00351   * @param Size: amount of data to be sent in bytes (without counting the header).
00352   *              0 means only the header is sent (ping operation).
00353   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
00354   * @retval HAL status
00355   */
00356 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
00357 {
00358   /* if the IP isn't already busy and if there is no previous transmission
00359      already pending due to arbitration lost */
00360   if(hcec->gState == HAL_CEC_STATE_READY)
00361   {
00362     if((pData == NULL ) && (Size > 0U))
00363     {
00364       return  HAL_ERROR;
00365     }
00366
00367     assert_param(IS_CEC_ADDRESS(DestinationAddress));
00368     assert_param(IS_CEC_ADDRESS(InitiatorAddress));
00369     assert_param(IS_CEC_MSGSIZE(Size));
00370
00371     /* Process Locked */
00372     __HAL_LOCK(hcec);
00373     hcec->pTxBuffPtr = pData;
00374     hcec->gState = HAL_CEC_STATE_BUSY_TX;
00375     hcec->ErrorCode = HAL_CEC_ERROR_NONE;
00376
00377     /* initialize the number of bytes to send,
00378      * 0 means only one header is sent (ping operation) */
00379     hcec->TxXferCount = Size;
00380
00381     /* send header block */
00382     hcec->Instance->TXD = (uint8_t)((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
00383
00384     /* Process Unlocked */
00385     __HAL_UNLOCK(hcec);
00386
00387     /* case no data to be sent, sender is only pinging the system */
00388     if (Size != 0)
00389     {
00390       /* Set TX Start of Message (TXSOM) bit */
00391       MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TSOM);
00392     }
00393     else
00394     {
00395       /* Send a ping command */
00396       MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM|CEC_FLAG_TSOM);
00397     }
00398     return HAL_OK;
00399
00400   }
00401   else
00402   {
00403     return HAL_BUSY;
00404   }
00405 }
00406
00407 /**
00408   * @brief Get size of the received frame.
00409   * @param hcec: CEC handle
00410   * @retval Frame size
00411   */
00412 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
00413 {
00414   return hcec->RxXferSize;
00415 }
00416
00417 /**
00418   * @brief Change Rx Buffer.
00419   * @param hcec: CEC handle
00420   * @param Rxbuffer: Rx Buffer
00421   * @note  This function can be called only inside the HAL_CEC_RxCpltCallback()
00422   * @retval Frame size
00423   */
00424 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
00425 {
00426   hcec->Init.RxBuffer = Rxbuffer;
00427 }
00428
00429 /**
00430   * @brief This function handles CEC interrupt requests.
00431   * @param hcec: CEC handle
00432   * @retval None
00433   */
00434 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
00435 {
00436   /* Save error status register for further error handling purposes */
00437   hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
00438
00439   /* Transmit error */
00440   if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TERR) != RESET)
00441   {
00442     /* Acknowledgement of the error */
00443     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
00444
00445     hcec->gState = HAL_CEC_STATE_READY;
00446   }
00447
00448   /* Receive error */
00449   if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RERR) != RESET)
00450   {
00451     /* Acknowledgement of the error */
00452     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
00453     hcec->Init.RxBuffer-=hcec->RxXferSize;
00454     hcec->RxXferSize = 0U;
00455     hcec->RxState = HAL_CEC_STATE_READY;
00456   }
00457
00458   if((hcec->ErrorCode & CEC_ESR_ALL_ERROR) != 0U)
00459   {
00460     /* Error  Call Back */
00461     HAL_CEC_ErrorCallback(hcec);
00462   }
00463
00464   /* Transmit byte request or block transfer finished */
00465   if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TBTRF) != RESET)
00466   {
00467     CEC_Transmit_IT(hcec);
00468   }
00469
00470   /* Receive byte or block transfer finished */
00471   if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RBTF) != RESET)
00472   {
00473     if(hcec->RxXferSize == 0U)
00474     {
00475       /* reception is starting */
00476       hcec->RxState = HAL_CEC_STATE_BUSY_RX;
00477     }
00478     CEC_Receive_IT(hcec);
00479   }
00480 }
00481
00482
00483 /**
00484   * @brief Tx Transfer completed callback
00485   * @param hcec: CEC handle
00486   * @retval None
00487   */
00488  __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
00489 {
00490   /* Prevent unused argument(s) compilation warning */
00491   UNUSED(hcec);
00492   /* NOTE : This function should not be modified, when the callback is needed,
00493             the HAL_CEC_TxCpltCallback can be implemented in the user file
00494    */
00495 }
00496
00497 /**
00498   * @brief Rx Transfer completed callback
00499   * @param hcec: CEC handle
00500   * @param RxFrameSize: Size of frame
00501   * @retval None
00502   */
00503 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
00504 {
00505   /* Prevent unused argument(s) compilation warning */
00506   UNUSED(hcec);
00507   UNUSED(RxFrameSize);
00508   /* NOTE : This function should not be modified, when the callback is needed,
00509             the HAL_CEC_RxCpltCallback can be implemented in the user file
00510    */
00511 }
00512
00513 /**
00514   * @brief CEC error callbacks
00515   * @param hcec: CEC handle
00516   * @retval None
00517   */
00518  __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
00519 {
00520   /* Prevent unused argument(s) compilation warning */
00521   UNUSED(hcec);
00522   /* NOTE : This function should not be modified, when the callback is needed,
00523             the HAL_CEC_ErrorCallback can be implemented in the user file
00524    */
00525 }
00526 /**
00527   * @}
00528   */
00529
00530 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
00531   *  @brief   CEC control functions
00532   *
00533 @verbatim
00534  ===============================================================================
00535                       ##### Peripheral Control function #####
00536  ===============================================================================
00537     [..]
00538     This subsection provides a set of functions allowing to control the CEC.
00539      (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
00540          (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
00541 @endverbatim
00542   * @{
00543   */
00544 /**
00545   * @brief return the CEC state
00546   * @param hcec: pointer to a CEC_HandleTypeDef structure that contains
00547   *              the configuration information for the specified CEC module.
00548   * @retval HAL state
00549   */
00550 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
00551 {
00552   uint32_t temp1= 0x00U, temp2 = 0x00U;
00553   temp1 = hcec->gState;
00554   temp2 = hcec->RxState;
00555
00556   return (HAL_CEC_StateTypeDef)(temp1 | temp2);
00557 }
00558
00559 /**
00560 * @brief  Return the CEC error code
00561 * @param  hcec : pointer to a CEC_HandleTypeDef structure that contains
00562   *              the configuration information for the specified CEC.
00563 * @retval CEC Error Code
00564 */
00565 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
00566 {
00567   return hcec->ErrorCode;
00568 }
00569
00570 /**
00571   * @}
00572   */
00573
00574 /**
00575   * @}
00576   */
00577
00578 /** @addtogroup CEC_Private_Functions
00579   * @{
00580   */
00581
00582  /**
00583   * @brief Send data in interrupt mode
00584   * @param hcec: CEC handle.
00585   *         Function called under interruption only, once
00586   *         interruptions have been enabled by HAL_CEC_Transmit_IT()
00587   * @retval HAL status
00588   */
00589 static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
00590 {
00591   /* if the IP is already busy or if there is a previous transmission
00592      already pending due to arbitration loss */
00593   if((hcec->gState == HAL_CEC_STATE_BUSY_TX) || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
00594   {
00595     /* if all data have been sent */
00596     if(hcec->TxXferCount == 0U)
00597     {
00598       /* Acknowledge successful completion by writing 0x00 */
00599       MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U);
00600
00601       hcec->gState = HAL_CEC_STATE_READY;
00602
00603       HAL_CEC_TxCpltCallback(hcec);
00604
00605       return HAL_OK;
00606     }
00607     else
00608     {
00609       /* Reduce the number of bytes to transfer by one */
00610       hcec->TxXferCount--;
00611
00612       /* Write data to TX buffer*/
00613       hcec->Instance->TXD = *hcec->pTxBuffPtr++;
00614
00615       /* If this is the last byte of the ongoing transmission */
00616       if(hcec->TxXferCount == 0U)
00617       {
00618         /* Acknowledge byte request and signal end of message */
00619         MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM);
00620       }
00621       else
00622       {
00623         /* Acknowledge byte request by writing 0x00 */
00624         MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U);
00625       }
00626
00627       return HAL_OK;
00628     }
00629   }
00630   else
00631   {
00632     return HAL_BUSY;
00633   }
00634 }
00635
00636 /**
00637   * @brief Receive data in interrupt mode.
00638   * @param hcec: CEC handle.
00639   *         Function called under interruption only, once
00640   *         interruptions have been enabled by HAL_CEC_Receive_IT()
00641   * @retval HAL status
00642   */
00643 static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
00644 {
00645   static uint32_t temp;
00646
00647   if(hcec->RxState == HAL_CEC_STATE_BUSY_RX)
00648   {
00649     temp = hcec->Instance->CSR;
00650
00651     /* Store received data */
00652     hcec->RxXferSize++;
00653     *hcec->Init.RxBuffer++ = hcec->Instance->RXD;
00654
00655     /* Acknowledge received byte by writing 0x00 */
00656     MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK, 0x00U);
00657
00658     /* If the End Of Message is reached */
00659     if(HAL_IS_BIT_SET(temp, CEC_FLAG_REOM))
00660     {
00661       /* Interrupts are not disabled due to transmission still ongoing */
00662       hcec->RxState = HAL_CEC_STATE_READY;
00663
00664       HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
00665
00666       return HAL_OK;
00667     }
00668     else
00669     {
00670       return HAL_BUSY;
00671     }
00672   }
00673   else
00674   {
00675     return HAL_BUSY;
00676   }
00677 }
00678
00679 /**
00680  * @}
00681  */
00682
00683 /**
00684   * @}
00685   */
00686
00687 #endif /* defined(STM32F100xB) || defined(STM32F100xE) */
00688
00689 #endif /* HAL_CEC_MODULE_ENABLED */
00690 /**
00691   * @}
00692   */
00693
00694 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_cec.h Source File

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stm32f1xx_hal_cec.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_cec.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of CEC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_CEC_H
00040 #define __STM32F1xx_HAL_CEC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F100xB) || defined(STM32F100xE)
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32f1xx_hal_def.h"
00049
00050 /** @addtogroup STM32F1xx_HAL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup CEC
00055   * @{
00056   */
00057
00058 /* Exported types ------------------------------------------------------------*/
00059 /** @defgroup CEC_Exported_Types CEC Exported Types
00060   * @{
00061   */
00062 /**
00063   * @brief CEC Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode.
00068                                  This parameter can be a value of @ref CEC_BitTimingErrorMode */
00069   uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode.
00070                                  This parameter can be a value of @ref CEC_BitPeriodErrorMode */
00071   uint16_t  OwnAddress;     /*!< Own addresses configuration
00072                                  This parameter can be a value of @ref CEC_OWN_ADDRESS */
00073   uint8_t  *RxBuffer;       /*!< CEC Rx buffer pointeur */
00074 }CEC_InitTypeDef;
00075
00076 /**
00077   * @brief HAL CEC State structures definition
00078   * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState.
00079   *        - gState contains CEC state information related to global Handle management
00080   *          and also information related to Tx operations.
00081   *          gState value coding follow below described bitmap :
00082   *          b7 (not used)
00083   *             x  : Should be set to 0
00084   *          b6  Error information
00085   *             0  : No Error
00086   *             1  : Error
00087   *          b5     IP initilisation status
00088   *             0  : Reset (IP not initialized)
00089   *             1  : Init done (IP initialized. HAL CEC Init function already called)
00090   *          b4-b3  (not used)
00091   *             xx : Should be set to 00
00092   *          b2     Intrinsic process state
00093   *             0  : Ready
00094   *             1  : Busy (IP busy with some configuration or internal operations)
00095   *          b1     (not used)
00096   *             x  : Should be set to 0
00097   *          b0     Tx state
00098   *             0  : Ready (no Tx operation ongoing)
00099   *             1  : Busy (Tx operation ongoing)
00100   *        - RxState contains information related to Rx operations.
00101   *          RxState value coding follow below described bitmap :
00102   *          b7-b6  (not used)
00103   *             xx : Should be set to 00
00104   *          b5     IP initilisation status
00105   *             0  : Reset (IP not initialized)
00106   *             1  : Init done (IP initialized)
00107   *          b4-b2  (not used)
00108   *            xxx : Should be set to 000
00109   *          b1     Rx state
00110   *             0  : Ready (no Rx operation ongoing)
00111   *             1  : Busy (Rx operation ongoing)
00112   *          b0     (not used)
00113   *             x  : Should be set to 0.
00114   */
00115 typedef enum
00116 {
00117   HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
00118                                                    Value is allowed for gState and RxState             */
00119   HAL_CEC_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
00120                                                    Value is allowed for gState and RxState             */
00121   HAL_CEC_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
00122                                                    Value is allowed for gState only                    */
00123   HAL_CEC_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
00124                                                    Value is allowed for RxState only                   */
00125   HAL_CEC_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
00126                                                    Value is allowed for gState only                    */
00127   HAL_CEC_STATE_BUSY_RX_TX        = 0x23U,    /*!< an internal process is ongoing
00128                                                    Value is allowed for gState only                    */
00129   HAL_CEC_STATE_ERROR             = 0x60U     /*!< Error Value is allowed for gState only              */
00130 }HAL_CEC_StateTypeDef;
00131
00132 /**
00133   * @brief  CEC handle Structure definition
00134   */
00135 typedef struct
00136 {
00137   CEC_TypeDef             *Instance;      /*!< CEC registers base address */
00138
00139   CEC_InitTypeDef         Init;           /*!< CEC communication parameters */
00140
00141   uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */
00142
00143   uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */
00144
00145   uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */
00146
00147   HAL_LockTypeDef         Lock;           /*!< Locking object */
00148
00149   HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management
00150                                                and also related to Tx operations.
00151                                                This parameter can be a value of @ref HAL_CEC_StateTypeDef */
00152
00153   HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.
00154                                                This parameter can be a value of @ref HAL_CEC_StateTypeDef */
00155
00156   uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register
00157                                                in case error is reported */
00158 }CEC_HandleTypeDef;
00159 /**
00160   * @}
00161   */
00162
00163 /* Exported constants --------------------------------------------------------*/
00164 /** @defgroup CEC_Exported_Constants CEC Exported Constants
00165   * @{
00166   */
00167
00168 /** @defgroup CEC_Error_Code CEC Error Code
00169   * @{
00170   */
00171 #define HAL_CEC_ERROR_NONE   0x00000000U    /*!< no error */
00172 #define HAL_CEC_ERROR_BTE    CEC_ESR_BTE    /*!< Bit Timing Error */
00173 #define HAL_CEC_ERROR_BPE    CEC_ESR_BPE    /*!< Bit Period Error */
00174 #define HAL_CEC_ERROR_RBTFE  CEC_ESR_RBTFE  /*!< Rx Block Transfer Finished Error */
00175 #define HAL_CEC_ERROR_SBE    CEC_ESR_SBE    /*!< Start Bit Error */
00176 #define HAL_CEC_ERROR_ACKE   CEC_ESR_ACKE   /*!< Block Acknowledge Error */
00177 #define HAL_CEC_ERROR_LINE   CEC_ESR_LINE   /*!< Line Error */
00178 #define HAL_CEC_ERROR_TBTFE  CEC_ESR_TBTFE  /*!< Tx Block Transfer Finished Error */
00179 /**
00180   * @}
00181   */
00182
00183 /** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
00184   * @{
00185   */
00186 #define CEC_BIT_TIMING_ERROR_MODE_STANDARD  0x00000000U      /*!< Bit timing error Standard Mode */
00187 #define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM    /*!< Bit timing error Free Mode */
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
00193   * @{
00194   */
00195 #define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U      /*!< Bit period error Standard Mode */
00196 #define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM    /*!< Bit period error Flexible Mode */
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header
00202   * @{
00203   */
00204 #define CEC_INITIATOR_LSB_POS                  4U
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup CEC_OWN_ADDRESS   CEC Own Address
00210   * @{
00211   */
00212 #define CEC_OWN_ADDRESS_NONE            CEC_OWN_ADDRESS_0    /* Reset value */
00213 #define CEC_OWN_ADDRESS_0              ((uint16_t)0x0000U)   /* Logical Address 0 */
00214 #define CEC_OWN_ADDRESS_1              ((uint16_t)0x0001U)   /* Logical Address 1 */
00215 #define CEC_OWN_ADDRESS_2              ((uint16_t)0x0002U)   /* Logical Address 2 */
00216 #define CEC_OWN_ADDRESS_3              ((uint16_t)0x0003U)   /* Logical Address 3 */
00217 #define CEC_OWN_ADDRESS_4              ((uint16_t)0x0004U)   /* Logical Address 4 */
00218 #define CEC_OWN_ADDRESS_5              ((uint16_t)0x0005U)   /* Logical Address 5 */
00219 #define CEC_OWN_ADDRESS_6              ((uint16_t)0x0006U)   /* Logical Address 6 */
00220 #define CEC_OWN_ADDRESS_7              ((uint16_t)0x0007U)   /* Logical Address 7 */
00221 #define CEC_OWN_ADDRESS_8              ((uint16_t)0x0008U)   /* Logical Address 8 */
00222 #define CEC_OWN_ADDRESS_9              ((uint16_t)0x0009U)   /* Logical Address 9 */
00223 #define CEC_OWN_ADDRESS_10             ((uint16_t)0x000AU)   /* Logical Address 10 */
00224 #define CEC_OWN_ADDRESS_11             ((uint16_t)0x000BU)   /* Logical Address 11 */
00225 #define CEC_OWN_ADDRESS_12             ((uint16_t)0x000CU)   /* Logical Address 12 */
00226 #define CEC_OWN_ADDRESS_13             ((uint16_t)0x000DU)   /* Logical Address 13 */
00227 #define CEC_OWN_ADDRESS_14             ((uint16_t)0x000EU)   /* Logical Address 14 */
00228 #define CEC_OWN_ADDRESS_15             ((uint16_t)0x000FU)   /* Logical Address 15 */
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup CEC_Interrupts_Definitions  Interrupts definition
00234   * @{
00235   */
00236 #define CEC_IT_IE CEC_CFGR_IE
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup CEC_Flags_Definitions  Flags definition
00242   * @{
00243   */
00244 #define CEC_FLAG_TSOM  CEC_CSR_TSOM
00245 #define CEC_FLAG_TEOM  CEC_CSR_TEOM
00246 #define CEC_FLAG_TERR  CEC_CSR_TERR
00247 #define CEC_FLAG_TBTRF CEC_CSR_TBTRF
00248 #define CEC_FLAG_RSOM  CEC_CSR_RSOM
00249 #define CEC_FLAG_REOM  CEC_CSR_REOM
00250 #define CEC_FLAG_RERR  CEC_CSR_RERR
00251 #define CEC_FLAG_RBTF  CEC_CSR_RBTF
00252 /**
00253   * @}
00254   */
00255
00256 /**
00257   * @}
00258   */
00259
00260 /* Exported macros -----------------------------------------------------------*/
00261 /** @defgroup CEC_Exported_Macros CEC Exported Macros
00262   * @{
00263   */
00264
00265 /** @brief  Reset CEC handle gstate & RxState
00266   * @param  __HANDLE__: CEC handle.
00267   * @retval None
00268   */
00269 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
00270                                                        (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \
00271                                                        (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \
00272                                                      } while(0U)
00273
00274 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
00275   * @param  __HANDLE__: specifies the CEC Handle.
00276   * @param  __FLAG__: specifies the flag to check.
00277   *     @arg CEC_FLAG_TERR: Tx Error
00278   *     @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished
00279   *     @arg CEC_FLAG_RERR: Rx Error
00280   *     @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
00281   * @retval ITStatus
00282   */
00283 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__))
00284
00285 /** @brief  Clears the CEC's pending flags.
00286   * @param  __HANDLE__: specifies the CEC Handle.
00287   * @param  __FLAG__: specifies the flag to clear.
00288   *   This parameter can be any combination of the following values:
00289   *     @arg CEC_CSR_TERR: Tx Error
00290   *     @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished
00291   *     @arg CEC_CSR_RERR: Rx Error
00292   *     @arg CEC_CSR_RBTF: Rx Block Transfer Finished
00293   * @retval none
00294   */
00295 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)                                                                   \
00296                           do {                                                                                       \
00297                             uint32_t tmp = 0x0U;                                                                     \
00298                             tmp = (__HANDLE__)->Instance->CSR & 0x00000002U;                                         \
00299                             (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\
00300                           } while(0U)
00301
00302 /** @brief  Enables the specified CEC interrupt.
00303   * @param  __HANDLE__: specifies the CEC Handle.
00304   * @param  __INTERRUPT__: specifies the CEC interrupt to enable.
00305   *          This parameter can be:
00306   *            @arg CEC_IT_IE         : Interrupt Enable.
00307   * @retval none
00308   */
00309 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
00310
00311 /** @brief  Disables the specified CEC interrupt.
00312   * @param  __HANDLE__: specifies the CEC Handle.
00313   * @param  __INTERRUPT__: specifies the CEC interrupt to disable.
00314   *          This parameter can be:
00315   *            @arg CEC_IT_IE         : Interrupt Enable
00316   * @retval none
00317   */
00318 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
00319
00320 /** @brief  Checks whether or not the specified CEC interrupt is enabled.
00321   * @param  __HANDLE__: specifies the CEC Handle.
00322   * @param  __INTERRUPT__: specifies the CEC interrupt to check.
00323   *          This parameter can be:
00324   *            @arg CEC_IT_IE         : Interrupt Enable
00325   * @retval FlagStatus
00326   */
00327 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
00328
00329 /** @brief  Enables the CEC device
00330   * @param  __HANDLE__: specifies the CEC Handle.
00331   * @retval none
00332   */
00333 #define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
00334
00335 /** @brief  Disables the CEC device
00336   * @param  __HANDLE__: specifies the CEC Handle.
00337   * @retval none
00338   */
00339 #define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
00340
00341 /** @brief  Set Transmission Start flag
00342   * @param  __HANDLE__: specifies the CEC Handle.
00343   * @retval none
00344   */
00345 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
00346
00347 /** @brief  Set Transmission End flag
00348   * @param  __HANDLE__: specifies the CEC Handle.
00349   * @retval none
00350   */
00351 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
00352
00353 /** @brief  Get Transmission Start flag
00354   * @param  __HANDLE__: specifies the CEC Handle.
00355   * @retval FlagStatus
00356   */
00357 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
00358
00359 /** @brief  Get Transmission End flag
00360   * @param  __HANDLE__: specifies the CEC Handle.
00361   * @retval FlagStatus
00362   */
00363 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
00364
00365 /** @brief  Clear OAR register
00366   * @param  __HANDLE__: specifies the CEC Handle.
00367   * @retval none
00368   */
00369 #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
00370
00371 /** @brief  Set OAR register
00372   * @param  __HANDLE__: specifies the CEC Handle.
00373   * @param  __ADDRESS__: Own Address value.
00374   * @retval none
00375   */
00376 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
00377
00378 /**
00379   * @}
00380   */
00381
00382 /* Exported functions --------------------------------------------------------*/
00383 /** @addtogroup CEC_Exported_Functions CEC Exported Functions
00384   * @{
00385   */
00386
00387 /** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
00388   *  @brief    Initialization and Configuration functions
00389   * @{
00390   */
00391 /* Initialization and de-initialization functions  ****************************/
00392 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
00393 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
00394 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
00395 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
00396 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
00397 /**
00398   * @}
00399   */
00400
00401 /** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
00402   *  @brief CEC Transmit/Receive functions
00403   * @{
00404   */
00405 /* I/O operation functions  ***************************************************/
00406 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
00407 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
00408 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
00409 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
00410 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
00411 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
00412 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
00413 /**
00414   * @}
00415   */
00416
00417 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
00418   *  @brief   CEC control functions
00419   * @{
00420   */
00421 /* Peripheral State and Error functions ***************************************/
00422 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
00423 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
00424 /**
00425   * @}
00426   */
00427
00428 /**
00429   * @}
00430   */
00431
00432 /* Private types -------------------------------------------------------------*/
00433 /** @defgroup CEC_Private_Types CEC Private Types
00434   * @{
00435   */
00436
00437 /**
00438   * @}
00439   */
00440
00441 /* Private variables ---------------------------------------------------------*/
00442 /** @defgroup CEC_Private_Variables CEC Private Variables
00443   * @{
00444   */
00445
00446 /**
00447   * @}
00448   */
00449
00450 /* Private constants ---------------------------------------------------------*/
00451 /** @defgroup CEC_Private_Constants CEC Private Constants
00452   * @{
00453   */
00454
00455 /**
00456   * @}
00457   */
00458
00459 /* Private macros ------------------------------------------------------------*/
00460 /** @defgroup CEC_Private_Macros CEC Private Macros
00461   * @{
00462   */
00463 #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
00464                                             ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
00465
00466 #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
00467                                             ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
00468
00469 /** @brief Check CEC message size.
00470   *       The message size is the payload size: without counting the header,
00471   *       it varies from 0 byte (ping operation, one header only, no payload) to
00472   *       15 bytes (1 opcode and up to 14 operands following the header).
00473   * @param  __SIZE__: CEC message size.
00474   * @retval Test result (TRUE or FALSE).
00475   */
00476 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
00477 /** @brief Check CEC device Own Address Register (OAR) setting.
00478   * @param  __ADDRESS__: CEC own address.
00479   * @retval Test result (TRUE or FALSE).
00480   */
00481 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
00482
00483 /** @brief Check CEC initiator or destination logical address setting.
00484   *        Initiator and destination addresses are coded over 4 bits.
00485   * @param  __ADDRESS__: CEC initiator or logical address.
00486   * @retval Test result (TRUE or FALSE).
00487   */
00488 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
00489
00490
00491
00492 /**
00493   * @}
00494   */
00495 /* Private functions ---------------------------------------------------------*/
00496 /** @defgroup CEC_Private_Functions CEC Private Functions
00497   * @{
00498   */
00499
00500 /**
00501   * @}
00502   */
00503
00504 /**
00505   * @}
00506   */
00507
00508 /**
00509   * @}
00510   */
00511 #endif /* defined(STM32F100xB) || defined(STM32F100xE) */
00512 #ifdef __cplusplus
00513 }
00514 #endif
00515
00516 #endif /* __STM32F1xx_HAL_CEC_H */
00517
00518 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_conf.h Source File

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stm32f1xx_hal_conf.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_conf.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   HAL configuration template file.
00008   *          This file should be copied to the application folder and renamed
00009   *          to stm32f1xx_hal_conf.h.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00014   *
00015   * Redistribution and use in source and binary forms, with or without modification,
00016   * are permitted provided that the following conditions are met:
00017   *   1. Redistributions of source code must retain the above copyright notice,
00018   *      this list of conditions and the following disclaimer.
00019   *   2. Redistributions in binary form must reproduce the above copyright notice,
00020   *      this list of conditions and the following disclaimer in the documentation
00021   *      and/or other materials provided with the distribution.
00022   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00023   *      may be used to endorse or promote products derived from this software
00024   *      without specific prior written permission.
00025   *
00026   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00027   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00028   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00029   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00030   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00032   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00033   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00034   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036   *
00037   ******************************************************************************
00038   */
00039
00040 /* Define to prevent recursive inclusion -------------------------------------*/
00041 #ifndef __STM32F1xx_HAL_CONF_H
00042 #define __STM32F1xx_HAL_CONF_H
00043
00044 #ifdef __cplusplus
00045  extern "C" {
00046 #endif
00047
00048 /* Exported types ------------------------------------------------------------*/
00049 /* Exported constants --------------------------------------------------------*/
00050
00051 /* ########################## Module Selection ############################## */
00052 /**
00053   * @brief This is the list of modules to be used in the HAL driver
00054   */
00055 #define HAL_MODULE_ENABLED
00056 #define HAL_ADC_MODULE_ENABLED
00057 #define HAL_CAN_MODULE_ENABLED
00058 #define HAL_CEC_MODULE_ENABLED
00059 #define HAL_CORTEX_MODULE_ENABLED
00060 #define HAL_CRC_MODULE_ENABLED
00061 #define HAL_DAC_MODULE_ENABLED
00062 #define HAL_DMA_MODULE_ENABLED
00063 #define HAL_ETH_MODULE_ENABLED
00064 #define HAL_FLASH_MODULE_ENABLED
00065 #define HAL_GPIO_MODULE_ENABLED
00066 #define HAL_HCD_MODULE_ENABLED
00067 #define HAL_I2C_MODULE_ENABLED
00068 #define HAL_I2S_MODULE_ENABLED
00069 #define HAL_IRDA_MODULE_ENABLED
00070 #define HAL_IWDG_MODULE_ENABLED
00071 #define HAL_NAND_MODULE_ENABLED
00072 #define HAL_NOR_MODULE_ENABLED
00073 #define HAL_PCCARD_MODULE_ENABLED
00074 #define HAL_PCD_MODULE_ENABLED
00075 #define HAL_PWR_MODULE_ENABLED
00076 #define HAL_RCC_MODULE_ENABLED
00077 #define HAL_RTC_MODULE_ENABLED
00078 #define HAL_SD_MODULE_ENABLED
00079 #define HAL_SMARTCARD_MODULE_ENABLED
00080 #define HAL_SPI_MODULE_ENABLED
00081 #define HAL_SRAM_MODULE_ENABLED
00082 #define HAL_TIM_MODULE_ENABLED
00083 #define HAL_UART_MODULE_ENABLED
00084 #define HAL_USART_MODULE_ENABLED
00085 #define HAL_WWDG_MODULE_ENABLED
00086
00087 /* ########################## Oscillator Values adaptation ####################*/
00088 /**
00089   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
00090   *        This value is used by the RCC HAL module to compute the system frequency
00091   *        (when HSE is used as system clock source, directly or through the PLL).
00092   */
00093 #if !defined  (HSE_VALUE)
00094 #if defined(USE_STM3210C_EVAL)
00095   #define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
00096 #else
00097   #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
00098 #endif
00099 #endif /* HSE_VALUE */
00100
00101 #if !defined  (HSE_STARTUP_TIMEOUT)
00102   #define HSE_STARTUP_TIMEOUT    100U      /*!< Time out for HSE start up, in ms */
00103 #endif /* HSE_STARTUP_TIMEOUT */
00104
00105 /**
00106   * @brief Internal High Speed oscillator (HSI) value.
00107   *        This value is used by the RCC HAL module to compute the system frequency
00108   *        (when HSI is used as system clock source, directly or through the PLL).
00109   */
00110 #if !defined  (HSI_VALUE)
00111   #define HSI_VALUE              8000000U  /*!< Value of the Internal oscillator in Hz */
00112 #endif /* HSI_VALUE */
00113
00114 /**
00115   * @brief Internal Low Speed oscillator (LSI) value.
00116   */
00117 #if !defined  (LSI_VALUE)
00118  #define LSI_VALUE               40000U    /*!< LSI Typical Value in Hz */
00119 #endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
00120                                                 The real value may vary depending on the variations
00121                                                 in voltage and temperature. */
00122 /**
00123   * @brief External Low Speed oscillator (LSE) value.
00124   *        This value is used by the UART, RTC HAL module to compute the system frequency
00125   */
00126 #if !defined  (LSE_VALUE)
00127  #define LSE_VALUE               32768U    /*!< Value of the External Low Speed oscillator in Hz */
00128 #endif /* LSE_VALUE */
00129
00130 #if !defined  (LSE_STARTUP_TIMEOUT)
00131   #define LSE_STARTUP_TIMEOUT    5000U     /*!< Time out for LSE start up, in ms */
00132 #endif /* LSE_STARTUP_TIMEOUT */
00133
00134 /* Tip: To avoid modifying this file each time you need to use different HSE,
00135    ===  you can define the HSE value in your toolchain compiler preprocessor. */
00136
00137 /* ########################### System Configuration ######################### */
00138 /**
00139   * @brief This is the HAL system configuration section
00140   */
00141 #define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
00142 #define  TICK_INT_PRIORITY            0x0FU /*!< tick interrupt priority */
00143 #define  USE_RTOS                     0U
00144 #define  PREFETCH_ENABLE              1U
00145
00146 /* ########################## Assert Selection ############################## */
00147 /**
00148   * @brief Uncomment the line below to expanse the "assert_param" macro in the
00149   *        HAL drivers code
00150   */
00151 /* #define USE_FULL_ASSERT    1U */
00152
00153 /* ################## Ethernet peripheral configuration ##################### */
00154
00155 /* Section 1 : Ethernet peripheral configuration */
00156
00157 /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
00158 #define MAC_ADDR0   2U
00159 #define MAC_ADDR1   0U
00160 #define MAC_ADDR2   0U
00161 #define MAC_ADDR3   0U
00162 #define MAC_ADDR4   0U
00163 #define MAC_ADDR5   0U
00164
00165 /* Definition of the Ethernet driver buffers size and count */
00166 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
00167 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
00168 #define ETH_RXBUFNB                    8U                  /* 8 Rx buffers of size ETH_RX_BUF_SIZE  */
00169 #define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
00170
00171 /* Section 2: PHY configuration section */
00172
00173 /* DP83848 PHY Address*/
00174 #define DP83848_PHY_ADDRESS             0x01U
00175 /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
00176 #define PHY_RESET_DELAY                 0x000000FFU
00177 /* PHY Configuration delay */
00178 #define PHY_CONFIG_DELAY                0x00000FFFU
00179
00180 #define PHY_READ_TO                     0x0000FFFFU
00181 #define PHY_WRITE_TO                    0x0000FFFFU
00182
00183 /* Section 3: Common PHY Registers */
00184
00185 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
00186 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
00187
00188 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
00189 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
00190 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
00191 #define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
00192 #define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
00193 #define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
00194 #define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
00195 #define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
00196 #define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
00197 #define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
00198
00199 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
00200 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
00201 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
00202
00203 /* Section 4: Extended PHY Registers */
00204
00205 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
00206 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
00207 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
00208
00209 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
00210 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
00211 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
00212
00213 #define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
00214 #define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
00215
00216 #define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
00217 #define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
00218
00219 /* ################## SPI peripheral configuration ########################## */
00220
00221 /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
00222 * Activated: CRC code is present inside driver
00223 * Deactivated: CRC code cleaned from driver
00224 */
00225
00226 #define USE_SPI_CRC                     1U
00227
00228 /* Includes ------------------------------------------------------------------*/
00229 /**
00230   * @brief Include module's header file
00231   */
00232
00233 #ifdef HAL_RCC_MODULE_ENABLED
00234  #include "stm32f1xx_hal_rcc.h"
00235 #endif /* HAL_RCC_MODULE_ENABLED */
00236
00237 #ifdef HAL_GPIO_MODULE_ENABLED
00238  #include "stm32f1xx_hal_gpio.h"
00239 #endif /* HAL_GPIO_MODULE_ENABLED */
00240
00241 #ifdef HAL_DMA_MODULE_ENABLED
00242   #include "stm32f1xx_hal_dma.h"
00243 #endif /* HAL_DMA_MODULE_ENABLED */
00244
00245 #ifdef HAL_ETH_MODULE_ENABLED
00246   #include "stm32f1xx_hal_eth.h"
00247 #endif /* HAL_ETH_MODULE_ENABLED */
00248
00249 #ifdef HAL_CAN_MODULE_ENABLED
00250  #include "stm32f1xx_hal_can.h"
00251 #endif /* HAL_CAN_MODULE_ENABLED */
00252
00253 #ifdef HAL_CEC_MODULE_ENABLED
00254  #include "stm32f1xx_hal_cec.h"
00255 #endif /* HAL_CEC_MODULE_ENABLED */
00256
00257 #ifdef HAL_CORTEX_MODULE_ENABLED
00258  #include "stm32f1xx_hal_cortex.h"
00259 #endif /* HAL_CORTEX_MODULE_ENABLED */
00260
00261 #ifdef HAL_ADC_MODULE_ENABLED
00262  #include "stm32f1xx_hal_adc.h"
00263 #endif /* HAL_ADC_MODULE_ENABLED */
00264
00265 #ifdef HAL_CRC_MODULE_ENABLED
00266  #include "stm32f1xx_hal_crc.h"
00267 #endif /* HAL_CRC_MODULE_ENABLED */
00268
00269 #ifdef HAL_DAC_MODULE_ENABLED
00270  #include "stm32f1xx_hal_dac.h"
00271 #endif /* HAL_DAC_MODULE_ENABLED */
00272
00273 #ifdef HAL_FLASH_MODULE_ENABLED
00274  #include "stm32f1xx_hal_flash.h"
00275 #endif /* HAL_FLASH_MODULE_ENABLED */
00276
00277 #ifdef HAL_SRAM_MODULE_ENABLED
00278  #include "stm32f1xx_hal_sram.h"
00279 #endif /* HAL_SRAM_MODULE_ENABLED */
00280
00281 #ifdef HAL_NOR_MODULE_ENABLED
00282  #include "stm32f1xx_hal_nor.h"
00283 #endif /* HAL_NOR_MODULE_ENABLED */
00284
00285 #ifdef HAL_I2C_MODULE_ENABLED
00286  #include "stm32f1xx_hal_i2c.h"
00287 #endif /* HAL_I2C_MODULE_ENABLED */
00288
00289 #ifdef HAL_I2S_MODULE_ENABLED
00290  #include "stm32f1xx_hal_i2s.h"
00291 #endif /* HAL_I2S_MODULE_ENABLED */
00292
00293 #ifdef HAL_IWDG_MODULE_ENABLED
00294  #include "stm32f1xx_hal_iwdg.h"
00295 #endif /* HAL_IWDG_MODULE_ENABLED */
00296
00297 #ifdef HAL_PWR_MODULE_ENABLED
00298  #include "stm32f1xx_hal_pwr.h"
00299 #endif /* HAL_PWR_MODULE_ENABLED */
00300
00301 #ifdef HAL_RTC_MODULE_ENABLED
00302  #include "stm32f1xx_hal_rtc.h"
00303 #endif /* HAL_RTC_MODULE_ENABLED */
00304
00305 #ifdef HAL_PCCARD_MODULE_ENABLED
00306  #include "stm32f1xx_hal_pccard.h"
00307 #endif /* HAL_PCCARD_MODULE_ENABLED */
00308
00309 #ifdef HAL_SD_MODULE_ENABLED
00310  #include "stm32f1xx_hal_sd.h"
00311 #endif /* HAL_SD_MODULE_ENABLED */
00312
00313 #ifdef HAL_NAND_MODULE_ENABLED
00314  #include "stm32f1xx_hal_nand.h"
00315 #endif /* HAL_NAND_MODULE_ENABLED */
00316
00317 #ifdef HAL_SPI_MODULE_ENABLED
00318  #include "stm32f1xx_hal_spi.h"
00319 #endif /* HAL_SPI_MODULE_ENABLED */
00320
00321 #ifdef HAL_TIM_MODULE_ENABLED
00322  #include "stm32f1xx_hal_tim.h"
00323 #endif /* HAL_TIM_MODULE_ENABLED */
00324
00325 #ifdef HAL_UART_MODULE_ENABLED
00326  #include "stm32f1xx_hal_uart.h"
00327 #endif /* HAL_UART_MODULE_ENABLED */
00328
00329 #ifdef HAL_USART_MODULE_ENABLED
00330  #include "stm32f1xx_hal_usart.h"
00331 #endif /* HAL_USART_MODULE_ENABLED */
00332
00333 #ifdef HAL_IRDA_MODULE_ENABLED
00334  #include "stm32f1xx_hal_irda.h"
00335 #endif /* HAL_IRDA_MODULE_ENABLED */
00336
00337 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00338  #include "stm32f1xx_hal_smartcard.h"
00339 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
00340
00341 #ifdef HAL_WWDG_MODULE_ENABLED
00342  #include "stm32f1xx_hal_wwdg.h"
00343 #endif /* HAL_WWDG_MODULE_ENABLED */
00344
00345 #ifdef HAL_PCD_MODULE_ENABLED
00346  #include "stm32f1xx_hal_pcd.h"
00347 #endif /* HAL_PCD_MODULE_ENABLED */
00348
00349
00350 #ifdef HAL_HCD_MODULE_ENABLED
00351  #include "stm32f1xx_hal_hcd.h"
00352 #endif /* HAL_HCD_MODULE_ENABLED */
00353
00354
00355 /* Exported macro ------------------------------------------------------------*/
00356 #ifdef  USE_FULL_ASSERT
00357 /**
00358   * @brief  The assert_param macro is used for function's parameters check.
00359   * @param  expr: If expr is false, it calls assert_failed function
00360   *         which reports the name of the source file and the source
00361   *         line number of the call that failed.
00362   *         If expr is true, it returns no value.
00363   * @retval None
00364   */
00365   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
00366 /* Exported functions ------------------------------------------------------- */
00367   void assert_failed(uint8_t* file, uint32_t line);
00368 #else
00369   #define assert_param(expr) ((void)0U)
00370 #endif /* USE_FULL_ASSERT */
00371
00372
00373 #ifdef __cplusplus
00374 }
00375 #endif
00376
00377 #endif /* __STM32F1xx_HAL_CONF_H */
00378
00379
00380 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_cortex.c Source File

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stm32f1xx_hal_cortex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_cortex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   CORTEX HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the CORTEX:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017
00018     [..]
00019     *** How to configure Interrupts using CORTEX HAL driver ***
00020     ===========================================================
00021     [..]
00022     This section provides functions allowing to configure the NVIC interrupts (IRQ).
00023     The Cortex-M3 exceptions are managed by CMSIS functions.
00024
00025     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
00026         function according to the following table.
00027     (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
00028     (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
00029     (#) please refer to programming manual for details in how to configure priority.
00030
00031      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
00032          The pending IRQ priority will be managed only by the sub priority.
00033
00034      -@- IRQ priority order (sorted by highest to lowest priority):
00035         (+@) Lowest preemption priority
00036         (+@) Lowest sub priority
00037         (+@) Lowest hardware priority (IRQ number)
00038
00039     [..]
00040     *** How to configure Systick using CORTEX HAL driver ***
00041     ========================================================
00042     [..]
00043     Setup SysTick Timer for time base.
00044
00045    (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
00046        is a CMSIS function that:
00047         (++) Configures the SysTick Reload register with value passed as function parameter.
00048         (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
00049         (++) Resets the SysTick Counter register.
00050         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
00051         (++) Enables the SysTick Interrupt.
00052         (++) Starts the SysTick Counter.
00053
00054    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
00055        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
00056        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
00057        inside the stm32f1xx_hal_cortex.h file.
00058
00059    (+) You can change the SysTick IRQ priority by calling the
00060        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
00061        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
00062
00063    (+) To adjust the SysTick time base, use the following formula:
00064
00065        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
00066        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
00067        (++) Reload Value should not exceed 0xFFFFFF
00068
00069   @endverbatim
00070   ******************************************************************************
00071   * @attention
00072   *
00073   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00074   *
00075   * Redistribution and use in source and binary forms, with or without modification,
00076   * are permitted provided that the following conditions are met:
00077   *   1. Redistributions of source code must retain the above copyright notice,
00078   *      this list of conditions and the following disclaimer.
00079   *   2. Redistributions in binary form must reproduce the above copyright notice,
00080   *      this list of conditions and the following disclaimer in the documentation
00081   *      and/or other materials provided with the distribution.
00082   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00083   *      may be used to endorse or promote products derived from this software
00084   *      without specific prior written permission.
00085   *
00086   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00087   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00088   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00089   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00090   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00091   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00092   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00093   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00094   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00095   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00096   *
00097   ******************************************************************************
00098   */
00099
00100 /* Includes ------------------------------------------------------------------*/
00101 #include "stm32f1xx_hal.h"
00102
00103 /** @addtogroup STM32F1xx_HAL_Driver
00104   * @{
00105   */
00106
00107 /** @defgroup CORTEX CORTEX
00108   * @brief CORTEX HAL module driver
00109   * @{
00110   */
00111
00112 #ifdef HAL_CORTEX_MODULE_ENABLED
00113
00114 /* Private types -------------------------------------------------------------*/
00115 /* Private variables ---------------------------------------------------------*/
00116 /* Private constants ---------------------------------------------------------*/
00117 /* Private macros ------------------------------------------------------------*/
00118 /* Private functions ---------------------------------------------------------*/
00119 /* Exported functions --------------------------------------------------------*/
00120
00121 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
00122   * @{
00123   */
00124
00125
00126 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
00127   *  @brief    Initialization and Configuration functions
00128   *
00129 @verbatim
00130   ==============================================================================
00131               ##### Initialization and de-initialization functions #####
00132   ==============================================================================
00133     [..]
00134       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
00135       Systick functionalities
00136
00137 @endverbatim
00138   * @{
00139   */
00140
00141
00142 /**
00143   * @brief  Sets the priority grouping field (preemption priority and subpriority)
00144   *         using the required unlock sequence.
00145   * @param  PriorityGroup: The priority grouping bits length.
00146   *         This parameter can be one of the following values:
00147   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
00148   *                                    4 bits for subpriority
00149   *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
00150   *                                    3 bits for subpriority
00151   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
00152   *                                    2 bits for subpriority
00153   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
00154   *                                    1 bits for subpriority
00155   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
00156   *                                    0 bits for subpriority
00157   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
00158   *         The pending IRQ priority will be managed only by the subpriority.
00159   * @retval None
00160   */
00161 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
00162 {
00163   /* Check the parameters */
00164   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00165
00166   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
00167   NVIC_SetPriorityGrouping(PriorityGroup);
00168 }
00169
00170 /**
00171   * @brief  Sets the priority of an interrupt.
00172   * @param  IRQn: External interrupt number.
00173   *         This parameter can be an enumerator of IRQn_Type enumeration
00174   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))
00175   * @param  PreemptPriority: The preemption priority for the IRQn channel.
00176   *         This parameter can be a value between 0 and 15
00177   *         A lower priority value indicates a higher priority
00178   * @param  SubPriority: the subpriority level for the IRQ channel.
00179   *         This parameter can be a value between 0 and 15
00180   *         A lower priority value indicates a higher priority.
00181   * @retval None
00182   */
00183 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
00184 {
00185   uint32_t prioritygroup = 0x00U;
00186
00187   /* Check the parameters */
00188   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
00189   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
00190
00191   prioritygroup = NVIC_GetPriorityGrouping();
00192
00193   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
00194 }
00195
00196 /**
00197   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
00198   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
00199   *         function should be called before.
00200   * @param  IRQn External interrupt number.
00201   *         This parameter can be an enumerator of IRQn_Type enumeration
00202   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
00203   * @retval None
00204   */
00205 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
00206 {
00207   /* Check the parameters */
00208   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00209
00210   /* Enable interrupt */
00211   NVIC_EnableIRQ(IRQn);
00212 }
00213
00214 /**
00215   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
00216   * @param  IRQn External interrupt number.
00217   *         This parameter can be an enumerator of IRQn_Type enumeration
00218   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
00219   * @retval None
00220   */
00221 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
00222 {
00223   /* Check the parameters */
00224   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00225
00226   /* Disable interrupt */
00227   NVIC_DisableIRQ(IRQn);
00228 }
00229
00230 /**
00231   * @brief  Initiates a system reset request to reset the MCU.
00232   * @retval None
00233   */
00234 void HAL_NVIC_SystemReset(void)
00235 {
00236   /* System Reset */
00237   NVIC_SystemReset();
00238 }
00239
00240 /**
00241   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
00242   *         Counter is in free running mode to generate periodic interrupts.
00243   * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
00244   * @retval status:  - 0  Function succeeded.
00245   *                  - 1  Function failed.
00246   */
00247 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
00248 {
00249    return SysTick_Config(TicksNumb);
00250 }
00251 /**
00252   * @}
00253   */
00254
00255 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
00256   *  @brief   Cortex control functions
00257   *
00258 @verbatim
00259   ==============================================================================
00260                       ##### Peripheral Control functions #####
00261   ==============================================================================
00262     [..]
00263       This subsection provides a set of functions allowing to control the CORTEX
00264       (NVIC, SYSTICK, MPU) functionalities.
00265
00266
00267 @endverbatim
00268   * @{
00269   */
00270
00271 #if (__MPU_PRESENT == 1U)
00272 /**
00273   * @brief  Disables the MPU
00274   * @retval None
00275   */
00276 void HAL_MPU_Disable(void)
00277 {
00278   /* Make sure outstanding transfers are done */
00279   __DMB();
00280
00281   /* Disable fault exceptions */
00282   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
00283
00284   /* Disable the MPU and clear the control register*/
00285   MPU->CTRL = 0U;
00286 }
00287
00288 /**
00289   * @brief  Enable the MPU.
00290   * @param  MPU_Control: Specifies the control mode of the MPU during hard fault,
00291   *          NMI, FAULTMASK and privileged access to the default memory
00292   *          This parameter can be one of the following values:
00293   *            @arg MPU_HFNMI_PRIVDEF_NONE
00294   *            @arg MPU_HARDFAULT_NMI
00295   *            @arg MPU_PRIVILEGED_DEFAULT
00296   *            @arg MPU_HFNMI_PRIVDEF
00297   * @retval None
00298   */
00299 void HAL_MPU_Enable(uint32_t MPU_Control)
00300 {
00301   /* Enable the MPU */
00302   MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
00303
00304   /* Enable fault exceptions */
00305   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
00306
00307   /* Ensure MPU setting take effects */
00308   __DSB();
00309   __ISB();
00310 }
00311
00312 /**
00313   * @brief  Initializes and configures the Region and the memory to be protected.
00314   * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
00315   *                the initialization and configuration information.
00316   * @retval None
00317   */
00318 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
00319 {
00320   /* Check the parameters */
00321   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
00322   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
00323
00324   /* Set the Region number */
00325   MPU->RNR = MPU_Init->Number;
00326
00327   if ((MPU_Init->Enable) != RESET)
00328   {
00329     /* Check the parameters */
00330     assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
00331     assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
00332     assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
00333     assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
00334     assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
00335     assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
00336     assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
00337     assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
00338
00339     MPU->RBAR = MPU_Init->BaseAddress;
00340     MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
00341                 ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
00342                 ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
00343                 ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
00344                 ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
00345                 ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
00346                 ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
00347                 ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
00348                 ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
00349   }
00350   else
00351   {
00352     MPU->RBAR = 0x00U;
00353     MPU->RASR = 0x00U;
00354   }
00355 }
00356 #endif /* __MPU_PRESENT */
00357
00358 /**
00359   * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
00360   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
00361   */
00362 uint32_t HAL_NVIC_GetPriorityGrouping(void)
00363 {
00364   /* Get the PRIGROUP[10:8] field value */
00365   return NVIC_GetPriorityGrouping();
00366 }
00367
00368 /**
00369   * @brief  Gets the priority of an interrupt.
00370   * @param  IRQn: External interrupt number.
00371   *         This parameter can be an enumerator of IRQn_Type enumeration
00372   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
00373   * @param   PriorityGroup: the priority grouping bits length.
00374   *         This parameter can be one of the following values:
00375   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
00376   *                                      4 bits for subpriority
00377   *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
00378   *                                      3 bits for subpriority
00379   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
00380   *                                      2 bits for subpriority
00381   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
00382   *                                      1 bits for subpriority
00383   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
00384   *                                      0 bits for subpriority
00385   * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
00386   * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
00387   * @retval None
00388   */
00389 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
00390 {
00391   /* Check the parameters */
00392   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
00393  /* Get priority for Cortex-M system or device specific interrupts */
00394   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
00395 }
00396
00397 /**
00398   * @brief  Sets Pending bit of an external interrupt.
00399   * @param  IRQn External interrupt number
00400   *         This parameter can be an enumerator of IRQn_Type enumeration
00401   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
00402   * @retval None
00403   */
00404 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
00405 {
00406   /* Check the parameters */
00407   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00408
00409   /* Set interrupt pending */
00410   NVIC_SetPendingIRQ(IRQn);
00411 }
00412
00413 /**
00414   * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
00415   *         and returns the pending bit for the specified interrupt).
00416   * @param  IRQn External interrupt number.
00417   *         This parameter can be an enumerator of IRQn_Type enumeration
00418   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
00419   * @retval status: - 0  Interrupt status is not pending.
00420   *                 - 1  Interrupt status is pending.
00421   */
00422 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
00423 {
00424   /* Check the parameters */
00425   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00426
00427   /* Return 1 if pending else 0 */
00428   return NVIC_GetPendingIRQ(IRQn);
00429 }
00430
00431 /**
00432   * @brief  Clears the pending bit of an external interrupt.
00433   * @param  IRQn External interrupt number.
00434   *         This parameter can be an enumerator of IRQn_Type enumeration
00435   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
00436   * @retval None
00437   */
00438 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00439 {
00440   /* Check the parameters */
00441   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00442
00443   /* Clear pending interrupt */
00444   NVIC_ClearPendingIRQ(IRQn);
00445 }
00446
00447 /**
00448   * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
00449   * @param IRQn External interrupt number
00450   *         This parameter can be an enumerator of IRQn_Type enumeration
00451   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
00452   * @retval status: - 0  Interrupt status is not pending.
00453   *                 - 1  Interrupt status is pending.
00454   */
00455 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
00456 {
00457   /* Check the parameters */
00458   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
00459
00460   /* Return 1 if active else 0 */
00461   return NVIC_GetActive(IRQn);
00462 }
00463
00464 /**
00465   * @brief  Configures the SysTick clock source.
00466   * @param  CLKSource: specifies the SysTick clock source.
00467   *         This parameter can be one of the following values:
00468   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
00469   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
00470   * @retval None
00471   */
00472 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
00473 {
00474   /* Check the parameters */
00475   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
00476   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
00477   {
00478     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
00479   }
00480   else
00481   {
00482     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
00483   }
00484 }
00485
00486 /**
00487   * @brief  This function handles SYSTICK interrupt request.
00488   * @retval None
00489   */
00490 void HAL_SYSTICK_IRQHandler(void)
00491 {
00492   HAL_SYSTICK_Callback();
00493 }
00494
00495 /**
00496   * @brief  SYSTICK callback.
00497   * @retval None
00498   */
00499 __weak void HAL_SYSTICK_Callback(void)
00500 {
00501   /* NOTE : This function Should not be modified, when the callback is needed,
00502             the HAL_SYSTICK_Callback could be implemented in the user file
00503    */
00504 }
00505
00506 /**
00507   * @}
00508   */
00509
00510 /**
00511   * @}
00512   */
00513
00514 #endif /* HAL_CORTEX_MODULE_ENABLED */
00515 /**
00516   * @}
00517   */
00518
00519 /**
00520   * @}
00521   */
00522
00523 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_cortex.h Source File

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stm32f1xx_hal_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_cortex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of CORTEX HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_CORTEX_H
00040 #define __STM32F1xx_HAL_CORTEX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CORTEX
00054   * @{
00055   */
00056 /* Exported types ------------------------------------------------------------*/
00057 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
00058   * @{
00059   */
00060
00061 #if (__MPU_PRESENT == 1U)
00062 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
00063   * @brief  MPU Region initialization structure
00064   * @{
00065   */
00066 typedef struct
00067 {
00068   uint8_t                Enable;                /*!< Specifies the status of the region.
00069                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
00070   uint8_t                Number;                /*!< Specifies the number of the region to protect.
00071                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
00072   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
00073   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
00074                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
00075   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
00076                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
00077   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
00078                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
00079   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
00080                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
00081   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
00082                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
00083   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
00084                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
00085   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
00086                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
00087   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
00088                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
00089 }MPU_Region_InitTypeDef;
00090 /**
00091   * @}
00092   */
00093 #endif /* __MPU_PRESENT */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /* Exported constants --------------------------------------------------------*/
00100
00101 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
00102   * @{
00103   */
00104
00105 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
00106   * @{
00107   */
00108 #define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
00109                                                       4 bits for subpriority */
00110 #define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
00111                                                       3 bits for subpriority */
00112 #define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
00113                                                       2 bits for subpriority */
00114 #define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
00115                                                       1 bits for subpriority */
00116 #define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
00117                                                       0 bits for subpriority */
00118 /**
00119   * @}
00120   */
00121
00122 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
00123   * @{
00124   */
00125 #define SYSTICK_CLKSOURCE_HCLK_DIV8    0x00000000U
00126 #define SYSTICK_CLKSOURCE_HCLK         0x00000004U
00127
00128 /**
00129   * @}
00130   */
00131
00132 #if (__MPU_PRESENT == 1)
00133 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
00134   * @{
00135   */
00136 #define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
00137 #define  MPU_HARDFAULT_NMI                MPU_CTRL_HFNMIENA_Msk
00138 #define  MPU_PRIVILEGED_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk
00139 #define  MPU_HFNMI_PRIVDEF               (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
00140
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
00146   * @{
00147   */
00148 #define  MPU_REGION_ENABLE     ((uint8_t)0x01)
00149 #define  MPU_REGION_DISABLE    ((uint8_t)0x00)
00150 /**
00151   * @}
00152   */
00153
00154 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
00155   * @{
00156   */
00157 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
00158 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
00164   * @{
00165   */
00166 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
00167 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
00173   * @{
00174   */
00175 #define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
00176 #define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
00182   * @{
00183   */
00184 #define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
00185 #define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
00191   * @{
00192   */
00193 #define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
00194 #define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
00195 #define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
00201   * @{
00202   */
00203 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
00204 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
00205 #define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
00206 #define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
00207 #define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
00208 #define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
00209 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
00210 #define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
00211 #define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
00212 #define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
00213 #define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
00214 #define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
00215 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
00216 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
00217 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
00218 #define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
00219 #define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
00220 #define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
00221 #define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
00222 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
00223 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
00224 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
00225 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
00226 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
00227 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
00228 #define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
00229 #define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
00230 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
00236   * @{
00237   */
00238 #define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
00239 #define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
00240 #define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
00241 #define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
00242 #define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
00243 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
00249   * @{
00250   */
00251 #define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
00252 #define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
00253 #define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
00254 #define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
00255 #define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
00256 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
00257 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
00258 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
00259 /**
00260   * @}
00261   */
00262 #endif /* __MPU_PRESENT */
00263
00264 /**
00265   * @}
00266   */
00267
00268
00269 /* Exported Macros -----------------------------------------------------------*/
00270
00271 /* Exported functions --------------------------------------------------------*/
00272 /** @addtogroup CORTEX_Exported_Functions
00273   * @{
00274   */
00275
00276 /** @addtogroup CORTEX_Exported_Functions_Group1
00277   * @{
00278   */
00279 /* Initialization and de-initialization functions *****************************/
00280 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
00281 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
00282 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
00283 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
00284 void HAL_NVIC_SystemReset(void);
00285 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
00286 /**
00287   * @}
00288   */
00289
00290 /** @addtogroup CORTEX_Exported_Functions_Group2
00291   * @{
00292   */
00293 /* Peripheral Control functions ***********************************************/
00294 uint32_t HAL_NVIC_GetPriorityGrouping(void);
00295 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
00296 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
00297 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
00298 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
00299 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
00300 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
00301 void HAL_SYSTICK_IRQHandler(void);
00302 void HAL_SYSTICK_Callback(void);
00303
00304 #if (__MPU_PRESENT == 1U)
00305 void HAL_MPU_Enable(uint32_t MPU_Control);
00306 void HAL_MPU_Disable(void);
00307 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
00308 #endif /* __MPU_PRESENT */
00309 /**
00310   * @}
00311   */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /* Private types -------------------------------------------------------------*/
00318 /* Private variables ---------------------------------------------------------*/
00319 /* Private constants ---------------------------------------------------------*/
00320 /* Private macros ------------------------------------------------------------*/
00321 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
00322   * @{
00323   */
00324 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
00325                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
00326                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
00327                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
00328                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
00329
00330 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
00331
00332 #define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
00333
00334 #define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)
00335
00336 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
00337                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
00338
00339 #if (__MPU_PRESENT == 1U)
00340 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
00341                                      ((STATE) == MPU_REGION_DISABLE))
00342
00343 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
00344                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
00345
00346 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
00347                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
00348
00349 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
00350                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
00351
00352 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
00353                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
00354
00355 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
00356                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
00357                                 ((TYPE) == MPU_TEX_LEVEL2))
00358
00359 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
00360                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
00361                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
00362                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
00363                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
00364                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
00365
00366 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
00367                                          ((NUMBER) == MPU_REGION_NUMBER1) || \
00368                                          ((NUMBER) == MPU_REGION_NUMBER2) || \
00369                                          ((NUMBER) == MPU_REGION_NUMBER3) || \
00370                                          ((NUMBER) == MPU_REGION_NUMBER4) || \
00371                                          ((NUMBER) == MPU_REGION_NUMBER5) || \
00372                                          ((NUMBER) == MPU_REGION_NUMBER6) || \
00373                                          ((NUMBER) == MPU_REGION_NUMBER7))
00374
00375 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
00376                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
00377                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
00378                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
00379                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
00380                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
00381                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
00382                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
00383                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
00384                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
00385                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
00386                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
00387                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
00388                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
00389                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
00390                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
00391                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
00392                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
00393                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
00394                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
00395                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
00396                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
00397                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
00398                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
00399                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
00400                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
00401                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
00402                                      ((SIZE) == MPU_REGION_SIZE_4GB))
00403
00404 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
00405 #endif /* __MPU_PRESENT */
00406
00407 /**
00408   * @}
00409   */
00410
00411 /* Private functions ---------------------------------------------------------*/
00412
00413 /**
00414   * @}
00415   */
00416
00417 /**
00418   * @}
00419   */
00420
00421 #ifdef __cplusplus
00422 }
00423 #endif
00424
00425 #endif /* __STM32F1xx_HAL_CORTEX_H */
00426
00427
00428 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_crc.c Source File

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  • STM32F1xx_HAL_Driver
  • Src
stm32f1xx_hal_crc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_crc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   CRC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                      ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019       The CRC HAL driver can be used as follows:
00020
00021       (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
00022
00023       (#) Use HAL_CRC_Accumulate() function to compute the CRC value of
00024           a 32-bit data buffer using combination of the previous CRC value
00025           and the new one.
00026
00027       (#) Use HAL_CRC_Calculate() function to compute the CRC Value of
00028           a new 32-bit data buffer. This function resets the CRC computation
00029           unit before starting the computation to avoid getting wrong CRC values.
00030
00031   @endverbatim
00032   ******************************************************************************
00033   * @attention
00034   *
00035   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00036   *
00037   * Redistribution and use in source and binary forms, with or without modification,
00038   * are permitted provided that the following conditions are met:
00039   *   1. Redistributions of source code must retain the above copyright notice,
00040   *      this list of conditions and the following disclaimer.
00041   *   2. Redistributions in binary form must reproduce the above copyright notice,
00042   *      this list of conditions and the following disclaimer in the documentation
00043   *      and/or other materials provided with the distribution.
00044   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00045   *      may be used to endorse or promote products derived from this software
00046   *      without specific prior written permission.
00047   *
00048   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00049   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00050   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00051   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00052   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00053   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00054   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00055   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00056   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00057   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00058   *
00059   ******************************************************************************
00060   */
00061
00062 /* Includes ------------------------------------------------------------------*/
00063 #include "stm32f1xx_hal.h"
00064
00065 /** @addtogroup STM32F1xx_HAL_Driver
00066   * @{
00067   */
00068
00069 /** @defgroup CRC CRC
00070   * @brief CRC HAL module driver.
00071   * @{
00072   */
00073
00074 #ifdef HAL_CRC_MODULE_ENABLED
00075
00076 /* Private typedef -----------------------------------------------------------*/
00077 /* Private define ------------------------------------------------------------*/
00078 /* Private macro -------------------------------------------------------------*/
00079 /* Private variables ---------------------------------------------------------*/
00080 /* Private function prototypes -----------------------------------------------*/
00081 /* Private functions ---------------------------------------------------------*/
00082
00083 /** @defgroup CRC_Exported_Functions CRC Exported Functions
00084   * @{
00085   */
00086
00087 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
00088  *  @brief    Initialization and Configuration functions.
00089  *
00090 @verbatim
00091   ==============================================================================
00092             ##### Initialization and de-initialization functions #####
00093   ==============================================================================
00094     [..]  This section provides functions allowing to:
00095       (+) Initialize the CRC according to the specified parameters
00096           in the CRC_InitTypeDef and create the associated handle
00097       (+) DeInitialize the CRC peripheral
00098       (+) Initialize the CRC MSP
00099       (+) DeInitialize CRC MSP
00100
00101 @endverbatim
00102   * @{
00103   */
00104
00105 /**
00106   * @brief  Initializes the CRC according to the specified
00107   *         parameters in the CRC_InitTypeDef and creates the associated handle.
00108   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00109   *         the configuration information for CRC
00110   * @retval HAL status
00111   */
00112 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
00113 {
00114   /* Check the CRC handle allocation */
00115   if(hcrc == NULL)
00116   {
00117     return HAL_ERROR;
00118   }
00119
00120   /* Check the parameters */
00121   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00122
00123   if(hcrc->State == HAL_CRC_STATE_RESET)
00124   {
00125     /* Allocate lock resource and initialize it */
00126     hcrc->Lock = HAL_UNLOCKED;
00127
00128     /* Init the low level hardware */
00129     HAL_CRC_MspInit(hcrc);
00130   }
00131
00132   /* Change CRC peripheral state */
00133   hcrc->State = HAL_CRC_STATE_READY;
00134
00135   /* Return function status */
00136   return HAL_OK;
00137 }
00138
00139 /**
00140   * @brief  DeInitializes the CRC peripheral.
00141   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00142   *         the configuration information for CRC
00143   * @retval HAL status
00144   */
00145 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
00146 {
00147   /* Check the CRC handle allocation */
00148   if(hcrc == NULL)
00149   {
00150     return HAL_ERROR;
00151   }
00152
00153   /* Check the parameters */
00154   assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
00155
00156   /* Change CRC peripheral state */
00157   hcrc->State = HAL_CRC_STATE_BUSY;
00158
00159   /* DeInit the low level hardware */
00160   HAL_CRC_MspDeInit(hcrc);
00161
00162   /* Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF */
00163   __HAL_CRC_DR_RESET(hcrc);
00164
00165   /* Reset IDR register content */
00166   CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
00167
00168   /* Change CRC peripheral state */
00169   hcrc->State = HAL_CRC_STATE_RESET;
00170
00171   /* Release Lock */
00172   __HAL_UNLOCK(hcrc);
00173
00174   /* Return function status */
00175   return HAL_OK;
00176 }
00177
00178 /**
00179   * @brief  Initializes the CRC MSP.
00180   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00181   *         the configuration information for CRC
00182   * @retval None
00183   */
00184 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
00185 {
00186   /* Prevent unused argument(s) compilation warning */
00187   UNUSED(hcrc);
00188   /* NOTE : This function Should not be modified, when the callback is needed,
00189             the HAL_CRC_MspInit could be implemented in the user file
00190    */
00191 }
00192
00193 /**
00194   * @brief  DeInitializes the CRC MSP.
00195   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00196   *         the configuration information for CRC
00197   * @retval None
00198   */
00199 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
00200 {
00201   /* Prevent unused argument(s) compilation warning */
00202   UNUSED(hcrc);
00203   /* NOTE : This function Should not be modified, when the callback is needed,
00204             the HAL_CRC_MspDeInit could be implemented in the user file
00205    */
00206 }
00207
00208 /**
00209   * @}
00210   */
00211
00212 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
00213  *  @brief    management functions.
00214  *
00215 @verbatim
00216   ==============================================================================
00217                       ##### Peripheral Control functions #####
00218   ==============================================================================
00219     [..]  This section provides functions allowing to:
00220       (+) Compute the 32-bit CRC value of 32-bit data buffer,
00221           using combination of the previous CRC value and the new one.
00222       (+) Compute the 32-bit CRC value of 32-bit data buffer,
00223           independently of the previous CRC value.
00224
00225 @endverbatim
00226   * @{
00227   */
00228
00229 /**
00230   * @brief  Computes the 32-bit CRC of 32-bit data buffer using combination
00231   *         of the previous CRC value and the new one.
00232   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00233   *         the configuration information for CRC
00234   * @param  pBuffer: pointer to the buffer containing the data to be computed
00235   * @param  BufferLength: length of the buffer to be computed (defined in word, 4 bytes)
00236   * @retval 32-bit CRC
00237   */
00238 uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00239 {
00240   uint32_t index = 0U;
00241
00242   /* Process Locked */
00243   __HAL_LOCK(hcrc);
00244
00245   /* Change CRC peripheral state */
00246   hcrc->State = HAL_CRC_STATE_BUSY;
00247
00248   /* Enter Data to the CRC calculator */
00249   for(index = 0U; index < BufferLength; index++)
00250   {
00251     hcrc->Instance->DR = pBuffer[index];
00252   }
00253
00254   /* Change CRC peripheral state */
00255   hcrc->State = HAL_CRC_STATE_READY;
00256
00257   /* Process Unlocked */
00258   __HAL_UNLOCK(hcrc);
00259
00260   /* Return the CRC computed value */
00261   return hcrc->Instance->DR;
00262 }
00263
00264 /**
00265   * @brief  Computes the 32-bit CRC of 32-bit data buffer independently
00266   *         of the previous CRC value.
00267   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00268   *         the configuration information for CRC
00269   * @param  pBuffer: Pointer to the buffer containing the data to be computed
00270   * @param  BufferLength: Length of the buffer to be computed (defined in word, 4 bytes)
00271   * @retval 32-bit CRC
00272   */
00273 uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
00274 {
00275   uint32_t index = 0U;
00276
00277   /* Process Locked */
00278   __HAL_LOCK(hcrc);
00279
00280   /* Change CRC peripheral state */
00281   hcrc->State = HAL_CRC_STATE_BUSY;
00282
00283   /* Reset CRC Calculation Unit */
00284   __HAL_CRC_DR_RESET(hcrc);
00285
00286   /* Enter Data to the CRC calculator */
00287   for(index = 0U; index < BufferLength; index++)
00288   {
00289     hcrc->Instance->DR = pBuffer[index];
00290   }
00291
00292   /* Change CRC peripheral state */
00293   hcrc->State = HAL_CRC_STATE_READY;
00294
00295   /* Process Unlocked */
00296   __HAL_UNLOCK(hcrc);
00297
00298   /* Return the CRC computed value */
00299   return hcrc->Instance->DR;
00300 }
00301
00302 /**
00303   * @}
00304   */
00305
00306 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
00307  *  @brief    Peripheral State functions.
00308  *
00309 @verbatim
00310   ==============================================================================
00311                       ##### Peripheral State functions #####
00312   ==============================================================================
00313     [..]
00314     This subsection permits to get in run-time the status of the peripheral.
00315
00316 @endverbatim
00317   * @{
00318   */
00319
00320 /**
00321   * @brief  Returns the CRC state.
00322   * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
00323   *         the configuration information for CRC
00324   * @retval HAL state
00325   */
00326 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
00327 {
00328   return hcrc->State;
00329 }
00330
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338
00339 #endif /* HAL_CRC_MODULE_ENABLED */
00340 /**
00341   * @}
00342   */
00343
00344 /**
00345   * @}
00346   */
00347
00348 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_crc.h Source File

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stm32f1xx_hal_crc.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_crc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of CRC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_CRC_H
00040 #define __STM32F1xx_HAL_CRC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup CRC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup CRC_Exported_Types CRC Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  CRC HAL State Structure definition
00065   */
00066 typedef enum
00067 {
00068   HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
00069   HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
00070   HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
00071   HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
00072   HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
00073
00074 }HAL_CRC_StateTypeDef;
00075
00076 /**
00077   * @brief  CRC handle Structure definition
00078   */
00079 typedef struct
00080 {
00081   CRC_TypeDef                 *Instance;  /*!< Register base address   */
00082
00083   HAL_LockTypeDef             Lock;       /*!< CRC locking object      */
00084
00085   __IO HAL_CRC_StateTypeDef   State;      /*!< CRC communication state */
00086
00087 }CRC_HandleTypeDef;
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported constants --------------------------------------------------------*/
00094 /* Exported macro ------------------------------------------------------------*/
00095
00096 /** @defgroup CRC_Exported_Macros CRC Exported Macros
00097   * @{
00098   */
00099
00100 /** @brief Reset CRC handle state
00101   * @param  __HANDLE__: CRC handle
00102   * @retval None
00103   */
00104 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
00105
00106 /**
00107   * @brief  Resets CRC Data Register.
00108   * @param  __HANDLE__: CRC handle
00109   * @retval None
00110   */
00111 #define __HAL_CRC_DR_RESET(__HANDLE__)            (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET))
00112
00113 /**
00114   * @brief Stores a 8-bit data in the Independent Data(ID) register.
00115   * @param __HANDLE__: CRC handle
00116   * @param __VALUE__: 8-bit value to be stored in the ID register
00117   * @retval None
00118   */
00119 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
00120
00121 /**
00122   * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
00123   * @param __HANDLE__: CRC handle
00124   * @retval 8-bit value of the ID register
00125   */
00126 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
00127
00128 /**
00129   * @}
00130   */
00131
00132 /* Exported functions --------------------------------------------------------*/
00133
00134 /** @addtogroup CRC_Exported_Functions
00135   * @{
00136   */
00137
00138 /** @addtogroup CRC_Exported_Functions_Group1
00139   * @{
00140   */
00141
00142 /* Initialization/de-initialization functions  **********************************/
00143 HAL_StatusTypeDef     HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
00144 HAL_StatusTypeDef     HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
00145 void                  HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
00146 void                  HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
00147
00148 /**
00149   * @}
00150   */
00151
00152 /** @addtogroup CRC_Exported_Functions_Group2
00153   * @{
00154   */
00155
00156 /* Peripheral Control functions  ************************************************/
00157 uint32_t              HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00158 uint32_t              HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
00159
00160
00161 /**
00162   * @}
00163   */
00164
00165 /** @addtogroup CRC_Exported_Functions_Group3
00166   ** @{
00167   */
00168
00169 /* Peripheral State functions  **************************************************/
00170 HAL_CRC_StateTypeDef  HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
00171
00172 /**
00173   * @}
00174   */
00175
00176
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 #ifdef __cplusplus
00190 }
00191 #endif
00192
00193 #endif /* __STM32F1xx_HAL_CRC_H */
00194
00195 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dac.c Source File

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stm32f1xx_hal_dac.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_dac.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   DAC HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   *
00016   @verbatim
00017   ==============================================================================
00018                       ##### DAC Peripheral features #####
00019   ==============================================================================
00020     [..]
00021       *** DAC Channels ***
00022       ====================
00023     [..]
00024     The device integrates two 12-bit Digital Analog Converters that can
00025     be used independently or simultaneously (dual mode):
00026       (#) DAC channel1 with DAC_OUT1 (PA4) as output
00027       (#) DAC channel2 with DAC_OUT2 (PA5) as output
00028
00029       *** DAC Triggers ***
00030       ====================
00031     [..]
00032     Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
00033     and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
00034     [..]
00035     Digital to Analog conversion can be triggered by:
00036       (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
00037           The used pin (GPIOx_PIN_9) must be configured in input mode.
00038
00039       (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7
00040           For STM32F10x connectivity line devices and STM32F100x devices: TIM3
00041           For STM32F10x high-density and XL-density devices: TIM8
00042           For STM32F100x high-density value line devices: TIM15 as
00043           replacement of TIM5.
00044           (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
00045
00046       (#) Software using DAC_TRIGGER_SOFTWARE
00047
00048       *** DAC Buffer mode feature ***
00049       ===============================
00050       [..]
00051       Each DAC channel integrates an output buffer that can be used to
00052       reduce the output impedance, and to drive external loads directly
00053       without having to add an external operational amplifier.
00054       To enable, the output buffer use
00055       sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
00056       [..]
00057       (@) Refer to the device datasheet for more details about output
00058           impedance value with and without output buffer.
00059
00060       *** DAC connect feature ***
00061       ===============================
00062       [..]
00063       Each DAC channel can be connected internally.
00064       To connect, use
00065       sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
00066
00067       *** GPIO configurations guidelines ***
00068       =====================
00069       [..]
00070       When a DAC channel is used (ex channel1 on PA4) and the other is not
00071       (ex channel1 on PA5 is configured in Analog and disabled).
00072       Channel1 may disturb channel2 as coupling effect.
00073       Note that there is no coupling on channel2 as soon as channel2 is turned on.
00074       Coupling on adjacent channel could be avoided as follows:
00075       when unused PA5 is configured as INPUT PULL-UP or DOWN.
00076       PA5 is configured in ANALOG just before it is turned on.
00077
00078        *** DAC wave generation feature ***
00079        ===================================
00080        [..]
00081        Both DAC channels can be used to generate
00082          (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
00083          (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
00084
00085        *** DAC data format ***
00086        =======================
00087        [..]
00088        The DAC data format can be:
00089          (#) 8-bit right alignment using DAC_ALIGN_8B_R
00090          (#) 12-bit left alignment using DAC_ALIGN_12B_L
00091          (#) 12-bit right alignment using DAC_ALIGN_12B_R
00092
00093        *** DAC data value to voltage correspondance ***
00094        ================================================
00095        [..]
00096        The analog output voltage on each DAC channel pin is determined
00097        by the following equation:
00098        [..]
00099        DAC_OUTx = VREF+ * DOR / 4095
00100        (+) with  DOR is the Data Output Register
00101        [..]
00102           VEF+ is the input voltage reference (refer to the device datasheet)
00103        [..]
00104         e.g. To set DAC_OUT1 to 0.7V, use
00105        (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
00106
00107        *** DMA requests  ***
00108        =====================
00109        [..]
00110        A DMA1 request can be generated when an external trigger (but not
00111        a software trigger) occurs if DMA1 requests are enabled using
00112        HAL_DAC_Start_DMA()
00113        [..]
00114        DMA requests are mapped as following:
00115          (#) DAC channel1 :
00116              For STM32F100x low-density, medium-density, high-density with DAC
00117              DMA remap:
00118                             mapped on DMA1 channel3 which must be
00119              already configured
00120              For STM32F100x high-density without DAC DMA remap and other
00121              STM32F1 devices:
00122                             mapped on DMA2 channel3 which must be
00123              already configured
00124          (#) DAC channel2 :
00125              For STM32F100x low-density, medium-density, high-density with DAC
00126              DMA remap:
00127                             mapped on DMA1 channel4 which must be
00128              already configured
00129              For STM32F100x high-density without DAC DMA remap and other
00130              STM32F1 devices:
00131                             mapped on DMA2 channel4 which must be
00132              already configured
00133
00134                       ##### How to use this driver #####
00135   ==============================================================================
00136     [..]
00137       (+) DAC APB clock must be enabled to get write access to DAC
00138           registers using HAL_DAC_Init()
00139       (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
00140       (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
00141       (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
00142
00143      *** Polling mode IO operation ***
00144      =================================
00145      [..]
00146        (+) Start the DAC peripheral using HAL_DAC_Start()
00147        (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
00148        (+) Stop the DAC peripheral using HAL_DAC_Stop()
00149
00150      *** DMA mode IO operation ***
00151      ==============================
00152      [..]
00153        (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
00154            of data to be transferred at each end of conversion
00155        (+) At the middle of data transfer HAL_DACEx_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
00156            function is executed and user can add his own code by customization of function pointer
00157            HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2
00158        (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
00159            function is executed and user can add his own code by customization of function pointer
00160            HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
00161        (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() or HAL_DACEx_ErrorCallbackCh2() function is executed and user can
00162            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 or HAL_DACEx_ErrorCallbackCh2
00163        (+) For STM32F100x devices with specific feature: DMA underrun.
00164            In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
00165            HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2()
00166            function is executed and user can add his own code by customization of function pointer
00167            HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DACEx_DMAUnderrunCallbackCh2
00168            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
00169        (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
00170
00171      *** DAC HAL driver macros list ***
00172      =============================================
00173      [..]
00174        Below the list of most used macros in DAC HAL driver.
00175
00176       (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
00177       (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
00178       (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (For STM32F100x devices with specific feature: DMA underrun)
00179       (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status (For STM32F100x devices with specific feature: DMA underrun)
00180
00181      [..]
00182       (@) You can refer to the DAC HAL driver header file for more useful macros
00183
00184  @endverbatim
00185   ******************************************************************************
00186   * @attention
00187   *
00188   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00189   *
00190   * Redistribution and use in source and binary forms, with or without modification,
00191   * are permitted provided that the following conditions are met:
00192   *   1. Redistributions of source code must retain the above copyright notice,
00193   *      this list of conditions and the following disclaimer.
00194   *   2. Redistributions in binary form must reproduce the above copyright notice,
00195   *      this list of conditions and the following disclaimer in the documentation
00196   *      and/or other materials provided with the distribution.
00197   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00198   *      may be used to endorse or promote products derived from this software
00199   *      without specific prior written permission.
00200   *
00201   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00202   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00203   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00204   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00205   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00206   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00207   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00208   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00209   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00210   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00211   *
00212   ******************************************************************************
00213   */
00214
00215
00216 /* Includes ------------------------------------------------------------------*/
00217 #include "stm32f1xx_hal.h"
00218
00219 /** @addtogroup STM32F1xx_HAL_Driver
00220   * @{
00221   */
00222
00223 /** @defgroup DAC DAC
00224   * @brief DAC driver modules
00225   * @{
00226   */
00227
00228 #ifdef HAL_DAC_MODULE_ENABLED
00229 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
00230
00231 /* Private typedef -----------------------------------------------------------*/
00232 /* Private define ------------------------------------------------------------*/
00233 /* Private macro -------------------------------------------------------------*/
00234 /* Private variables ---------------------------------------------------------*/
00235 /* Private function prototypes -----------------------------------------------*/
00236 /* Exported functions -------------------------------------------------------*/
00237
00238 /** @defgroup DAC_Exported_Functions DAC Exported Functions
00239   * @{
00240   */
00241
00242 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
00243  *  @brief    Initialization and Configuration functions
00244  *
00245 @verbatim
00246   ==============================================================================
00247               ##### Initialization and de-initialization functions #####
00248   ==============================================================================
00249     [..]  This section provides functions allowing to:
00250       (+) Initialize and configure the DAC.
00251       (+) De-initialize the DAC.
00252
00253 @endverbatim
00254   * @{
00255   */
00256
00257 /**
00258   * @brief  Initializes the DAC peripheral according to the specified parameters
00259   *         in the DAC_InitStruct.
00260   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00261   *         the configuration information for the specified DAC.
00262   * @retval HAL status
00263   */
00264 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
00265 {
00266   /* Check DAC handle */
00267   if(hdac == NULL)
00268   {
00269      return HAL_ERROR;
00270   }
00271   /* Check the parameters */
00272   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00273
00274   if(hdac->State == HAL_DAC_STATE_RESET)
00275   {
00276     /* Allocate lock resource and initialize it */
00277     hdac->Lock = HAL_UNLOCKED;
00278
00279     /* Init the low level hardware */
00280     HAL_DAC_MspInit(hdac);
00281   }
00282
00283   /* Initialize the DAC state*/
00284   hdac->State = HAL_DAC_STATE_BUSY;
00285
00286   /* Set DAC error code to none */
00287   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00288
00289   /* Initialize the DAC state*/
00290   hdac->State = HAL_DAC_STATE_READY;
00291
00292   /* Return function status */
00293   return HAL_OK;
00294 }
00295
00296 /**
00297   * @brief  Deinitializes the DAC peripheral registers to their default reset values.
00298   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00299   *         the configuration information for the specified DAC.
00300   * @retval HAL status
00301   */
00302 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
00303 {
00304   /* Check DAC handle */
00305   if(hdac == NULL)
00306   {
00307      return HAL_ERROR;
00308   }
00309
00310   /* Check the parameters */
00311   assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
00312
00313   /* Change DAC state */
00314   hdac->State = HAL_DAC_STATE_BUSY;
00315
00316   /* DeInit the low level hardware */
00317   HAL_DAC_MspDeInit(hdac);
00318
00319   /* Set DAC error code to none */
00320   hdac->ErrorCode = HAL_DAC_ERROR_NONE;
00321
00322   /* Change DAC state */
00323   hdac->State = HAL_DAC_STATE_RESET;
00324
00325   /* Release Lock */
00326   __HAL_UNLOCK(hdac);
00327
00328   /* Return function status */
00329   return HAL_OK;
00330 }
00331
00332 /**
00333   * @brief  Initializes the DAC MSP.
00334   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00335   *         the configuration information for the specified DAC.
00336   * @retval None
00337   */
00338 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
00339 {
00340   /* Prevent unused argument(s) compilation warning */
00341   UNUSED(hdac);
00342   /* NOTE : This function Should not be modified, when the callback is needed,
00343             the HAL_DAC_MspInit could be implemented in the user file
00344    */
00345 }
00346
00347 /**
00348   * @brief  DeInitializes the DAC MSP.
00349   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00350   *         the configuration information for the specified DAC.
00351   * @retval None
00352   */
00353 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
00354 {
00355   /* Prevent unused argument(s) compilation warning */
00356   UNUSED(hdac);
00357   /* NOTE : This function Should not be modified, when the callback is needed,
00358             the HAL_DAC_MspDeInit could be implemented in the user file
00359    */
00360 }
00361
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
00367  *  @brief    IO operation functions
00368  *
00369 @verbatim
00370   ==============================================================================
00371              ##### IO operation functions #####
00372   ==============================================================================
00373     [..]  This section provides functions allowing to:
00374       (+) Start conversion.
00375       (+) Stop conversion.
00376       (+) Start conversion and enable DMA transfer.
00377       (+) Stop conversion and disable DMA transfer.
00378       (+) Get result of conversion.
00379
00380 @endverbatim
00381   * @{
00382   */
00383
00384 /**
00385   * @brief  Enables DAC and starts conversion of channel.
00386   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00387   *         the configuration information for the specified DAC.
00388   * @param  Channel: The selected DAC channel.
00389   *          This parameter can be one of the following values:
00390   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00391   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00392   * @retval HAL status
00393   */
00394 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
00395 {
00396   /* Check the parameters */
00397   assert_param(IS_DAC_CHANNEL(Channel));
00398
00399   /* Process locked */
00400   __HAL_LOCK(hdac);
00401
00402   /* Change DAC state */
00403   hdac->State = HAL_DAC_STATE_BUSY;
00404
00405   /* Enable the Peripharal */
00406   __HAL_DAC_ENABLE(hdac, Channel);
00407
00408   if(Channel == DAC_CHANNEL_1)
00409   {
00410     /* Check if software trigger enabled */
00411     if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
00412     {
00413       /* Enable the selected DAC software conversion */
00414       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
00415     }
00416   }
00417   else
00418   {
00419     /* Check if software trigger enabled */
00420     if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
00421     {
00422       /* Enable the selected DAC software conversion*/
00423       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
00424     }
00425   }
00426
00427   /* Change DAC state */
00428   hdac->State = HAL_DAC_STATE_READY;
00429
00430   /* Process unlocked */
00431   __HAL_UNLOCK(hdac);
00432
00433   /* Return function status */
00434   return HAL_OK;
00435 }
00436
00437 /**
00438   * @brief  Disables DAC and stop conversion of channel.
00439   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00440   *         the configuration information for the specified DAC.
00441   * @param  Channel: The selected DAC channel.
00442   *          This parameter can be one of the following values:
00443   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00444   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00445   * @retval HAL status
00446   */
00447 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
00448 {
00449   /* Check the parameters */
00450   assert_param(IS_DAC_CHANNEL(Channel));
00451
00452   /* Disable the Peripheral */
00453   __HAL_DAC_DISABLE(hdac, Channel);
00454
00455   /* Change DAC state */
00456   hdac->State = HAL_DAC_STATE_READY;
00457
00458   /* Return function status */
00459   return HAL_OK;
00460 }
00461
00462 /**
00463   * @brief  Enables DAC and starts conversion of channel.
00464   *         Note: For STM32F100x devices with specific feature: DMA underrun.
00465   *         On these devices, this function enables the interruption of DMA
00466   *         underrun.
00467   *         (refer to redefinition of this function in DAC extended file)
00468   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00469   *         the configuration information for the specified DAC.
00470   * @param  Channel: The selected DAC channel.
00471   *          This parameter can be one of the following values:
00472   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00473   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00474   * @param  pData: The Source memory Buffer address.
00475   * @param  Length: The length of data to be transferred from memory to DAC peripheral
00476   * @param  Alignment: Specifies the data alignment for DAC channel.
00477   *          This parameter can be one of the following values:
00478   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00479   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00480   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00481   * @retval HAL status
00482   */
00483 __weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
00484 {
00485   uint32_t tmpreg = 0U;
00486
00487   /* Check the parameters */
00488   assert_param(IS_DAC_CHANNEL(Channel));
00489   assert_param(IS_DAC_ALIGN(Alignment));
00490
00491   /* Process locked */
00492   __HAL_LOCK(hdac);
00493
00494   /* Change DAC state */
00495   hdac->State = HAL_DAC_STATE_BUSY;
00496
00497   if(Channel == DAC_CHANNEL_1)
00498   {
00499     /* Set the DMA transfer complete callback for channel1 */
00500     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00501
00502     /* Set the DMA half transfer complete callback for channel1 */
00503     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00504
00505     /* Set the DMA error callback for channel1 */
00506     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00507
00508     /* Enable the selected DAC channel1 DMA request */
00509     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00510
00511     /* Case of use of channel 1 */
00512     switch(Alignment)
00513     {
00514       case DAC_ALIGN_12B_R:
00515         /* Get DHR12R1 address */
00516         tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00517         break;
00518       case DAC_ALIGN_12B_L:
00519         /* Get DHR12L1 address */
00520         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00521         break;
00522       case DAC_ALIGN_8B_R:
00523         /* Get DHR8R1 address */
00524         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00525         break;
00526       default:
00527         break;
00528     }
00529   }
00530   else
00531   {
00532     /* Set the DMA transfer complete callback for channel2 */
00533     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00534
00535     /* Set the DMA half transfer complete callback for channel2 */
00536     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00537
00538     /* Set the DMA error callback for channel2 */
00539     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00540
00541     /* Enable the selected DAC channel2 DMA request */
00542     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00543
00544     /* Case of use of channel 2 */
00545     switch(Alignment)
00546     {
00547       case DAC_ALIGN_12B_R:
00548         /* Get DHR12R2 address */
00549         tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
00550         break;
00551       case DAC_ALIGN_12B_L:
00552         /* Get DHR12L2 address */
00553         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
00554         break;
00555       case DAC_ALIGN_8B_R:
00556         /* Get DHR8R2 address */
00557         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
00558         break;
00559       default:
00560         break;
00561     }
00562   }
00563
00564   /* Enable the DMA channel */
00565   if(Channel == DAC_CHANNEL_1)
00566   {
00567     /* Enable the DMA channel */
00568     HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00569   }
00570   else
00571   {
00572     /* Enable the DMA channel */
00573     HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00574   }
00575
00576   /* Process Unlocked */
00577   __HAL_UNLOCK(hdac);
00578
00579   /* Enable the Peripharal */
00580   __HAL_DAC_ENABLE(hdac, Channel);
00581
00582   /* Return function status */
00583   return HAL_OK;
00584 }
00585
00586 /**
00587   * @brief  Disables DAC and stop conversion of channel.
00588   *         Note: For STM32F100x devices with specific feature: DMA underrun.
00589   *         On these devices, this function disables the interruption of DMA
00590   *         underrun.
00591   *         (refer to redefinition of this function in DAC extended file)
00592   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00593   *         the configuration information for the specified DAC.
00594   * @param  Channel: The selected DAC channel.
00595   *          This parameter can be one of the following values:
00596   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00597   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00598   * @retval HAL status
00599   */
00600 __weak HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
00601 {
00602   HAL_StatusTypeDef status = HAL_OK;
00603
00604   /* Check the parameters */
00605   assert_param(IS_DAC_CHANNEL(Channel));
00606
00607   /* Disable the selected DAC channel DMA request */
00608   CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1 << Channel);
00609
00610   /* Disable the Peripharal */
00611   __HAL_DAC_DISABLE(hdac, Channel);
00612
00613   /* Disable the DMA Channel */
00614   /* Channel1 is used */
00615   if (Channel == DAC_CHANNEL_1)
00616   {
00617     status = HAL_DMA_Abort(hdac->DMA_Handle1);
00618   }
00619   else /* Channel2 is used for */
00620   {
00621     status = HAL_DMA_Abort(hdac->DMA_Handle2);
00622   }
00623
00624   /* Check if DMA Channel effectively disabled */
00625   if (status != HAL_OK)
00626   {
00627     /* Update ADC state machine to error */
00628     hdac->State = HAL_DAC_STATE_ERROR;
00629   }
00630   else
00631   {
00632     /* Change DAC state */
00633     hdac->State = HAL_DAC_STATE_READY;
00634   }
00635
00636   /* Return function status */
00637   return status;
00638 }
00639
00640 /**
00641   * @brief  Returns the last data output value of the selected DAC channel.
00642   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00643   *         the configuration information for the specified DAC.
00644   * @param  Channel: The selected DAC channel.
00645   *          This parameter can be one of the following values:
00646   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00647   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00648   * @retval The selected DAC channel data output value.
00649   */
00650 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
00651 {
00652   /* Check the parameters */
00653   assert_param(IS_DAC_CHANNEL(Channel));
00654
00655   /* Returns the DAC channel data output register value */
00656   if(Channel == DAC_CHANNEL_1)
00657   {
00658     return hdac->Instance->DOR1;
00659   }
00660   else
00661   {
00662     return hdac->Instance->DOR2;
00663   }
00664 }
00665
00666 /**
00667   * @brief  Conversion complete callback in non blocking mode for Channel1
00668   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00669   *         the configuration information for the specified DAC.
00670   * @retval None
00671   */
00672 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00673 {
00674   /* Prevent unused argument(s) compilation warning */
00675   UNUSED(hdac);
00676   /* NOTE : This function Should not be modified, when the callback is needed,
00677             the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
00678    */
00679 }
00680
00681 /**
00682   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1
00683   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00684   *         the configuration information for the specified DAC.
00685   * @retval None
00686   */
00687 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
00688 {
00689   /* Prevent unused argument(s) compilation warning */
00690   UNUSED(hdac);
00691   /* NOTE : This function Should not be modified, when the callback is needed,
00692             the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
00693    */
00694 }
00695
00696 /**
00697   * @brief  Error DAC callback for Channel1.
00698   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00699   *         the configuration information for the specified DAC.
00700   * @retval None
00701   */
00702 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
00703 {
00704   /* Prevent unused argument(s) compilation warning */
00705   UNUSED(hdac);
00706   /* NOTE : This function Should not be modified, when the callback is needed,
00707             the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
00708    */
00709 }
00710
00711 /**
00712   * @}
00713   */
00714
00715 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
00716  *  @brief    Peripheral Control functions
00717  *
00718 @verbatim
00719   ==============================================================================
00720              ##### Peripheral Control functions #####
00721   ==============================================================================
00722     [..]  This section provides functions allowing to:
00723       (+) Configure channels.
00724       (+) Set the specified data holding register value for DAC channel.
00725
00726 @endverbatim
00727   * @{
00728   */
00729
00730 /**
00731   * @brief  Configures the selected DAC channel.
00732   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00733   *         the configuration information for the specified DAC.
00734   * @param  sConfig: DAC configuration structure.
00735   * @param  Channel: The selected DAC channel.
00736   *          This parameter can be one of the following values:
00737   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00738   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00739   * @retval HAL status
00740   */
00741 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
00742 {
00743   uint32_t tmpreg1 = 0U;
00744
00745   /* Check the DAC parameters */
00746   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
00747   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
00748   assert_param(IS_DAC_CHANNEL(Channel));
00749
00750   /* Process locked */
00751   __HAL_LOCK(hdac);
00752
00753   /* Change DAC state */
00754   hdac->State = HAL_DAC_STATE_BUSY;
00755
00756   /* Configure for the selected DAC channel: buffer output, trigger */
00757   /* Set TSELx and TENx bits according to DAC_Trigger value */
00758   /* Set BOFFx bit according to DAC_OutputBuffer value */
00759   SET_BIT(tmpreg1, (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer));
00760
00761   /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
00762   /* Calculate CR register value depending on DAC_Channel */
00763   MODIFY_REG(hdac->Instance->CR,
00764              ((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel,
00765              tmpreg1 << Channel);
00766
00767   /* Disable wave generation */
00768   hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
00769
00770   /* Change DAC state */
00771   hdac->State = HAL_DAC_STATE_READY;
00772
00773   /* Process unlocked */
00774   __HAL_UNLOCK(hdac);
00775
00776   /* Return function status */
00777   return HAL_OK;
00778 }
00779
00780 /**
00781   * @brief  Set the specified data holding register value for DAC channel.
00782   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00783   *         the configuration information for the specified DAC.
00784   * @param  Channel: The selected DAC channel.
00785   *          This parameter can be one of the following values:
00786   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00787   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00788   * @param  Alignment: Specifies the data alignment.
00789   *          This parameter can be one of the following values:
00790   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00791   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00792   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00793   * @param  Data: Data to be loaded in the selected data holding register.
00794   * @retval HAL status
00795   */
00796 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
00797 {
00798   __IO uint32_t tmp = 0U;
00799
00800   /* Check the parameters */
00801   assert_param(IS_DAC_CHANNEL(Channel));
00802   assert_param(IS_DAC_ALIGN(Alignment));
00803   assert_param(IS_DAC_DATA(Data));
00804
00805   tmp = (uint32_t)hdac->Instance;
00806   if(Channel == DAC_CHANNEL_1)
00807   {
00808     tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
00809   }
00810   else
00811   {
00812     tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
00813   }
00814
00815   /* Set the DAC channel selected data holding register */
00816   *(__IO uint32_t *) tmp = Data;
00817
00818   /* Return function status */
00819   return HAL_OK;
00820 }
00821
00822 /**
00823   * @}
00824   */
00825
00826 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
00827  *  @brief   Peripheral State and Errors functions
00828  *
00829 @verbatim
00830   ==============================================================================
00831             ##### Peripheral State and Errors functions #####
00832   ==============================================================================
00833     [..]
00834     This subsection provides functions allowing to
00835       (+) Check the DAC state.
00836       (+) Check the DAC Errors.
00837
00838 @endverbatim
00839   * @{
00840   */
00841
00842 /**
00843   * @brief  return the DAC state
00844   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00845   *         the configuration information for the specified DAC.
00846   * @retval HAL state
00847   */
00848 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
00849 {
00850   /* Return DAC state */
00851   return hdac->State;
00852 }
00853
00854
00855 /**
00856   * @brief  Return the DAC error code
00857   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00858   *         the configuration information for the specified DAC.
00859   * @retval DAC Error Code
00860   */
00861 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
00862 {
00863   return hdac->ErrorCode;
00864 }
00865
00866 /**
00867   * @}
00868   */
00869
00870 /**
00871   * @}
00872   */
00873
00874 /** @addtogroup DAC_Private_Functions
00875   * @{
00876   */
00877
00878 /**
00879   * @brief  DMA conversion complete callback.
00880   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00881   *                the configuration information for the specified DMA module.
00882   * @retval None
00883   */
00884 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
00885 {
00886   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00887
00888   HAL_DAC_ConvCpltCallbackCh1(hdac);
00889
00890   hdac->State = HAL_DAC_STATE_READY;
00891 }
00892
00893 /**
00894   * @brief  DMA half transfer complete callback.
00895   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00896   *                the configuration information for the specified DMA module.
00897   * @retval None
00898   */
00899 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
00900 {
00901     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00902     /* Conversion complete callback */
00903     HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
00904 }
00905
00906 /**
00907   * @brief  DMA error callback
00908   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00909   *                the configuration information for the specified DMA module.
00910   * @retval None
00911   */
00912 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
00913 {
00914   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00915
00916   /* Set DAC error code to DMA error */
00917   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00918
00919   HAL_DAC_ErrorCallbackCh1(hdac);
00920
00921   hdac->State = HAL_DAC_STATE_READY;
00922 }
00923
00924 /**
00925   * @}
00926   */
00927
00928 #endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00929 #endif /* HAL_DAC_MODULE_ENABLED */
00930
00931 /**
00932   * @}
00933   */
00934
00935 /**
00936   * @}
00937   */
00938
00939 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dac.h Source File

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stm32f1xx_hal_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_dac.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of DAC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_DAC_H
00040 #define __STM32F1xx_HAL_DAC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f1xx_hal_def.h"
00050
00051 /** @addtogroup STM32F1xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup DAC
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060
00061 /** @defgroup DAC_Exported_Types DAC Exported Types
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  HAL State structures definition
00067   */
00068 typedef enum
00069 {
00070   HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
00071   HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
00072   HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
00073   HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
00074   HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
00075
00076 }HAL_DAC_StateTypeDef;
00077
00078 /**
00079   * @brief  DAC handle Structure definition
00080   */
00081 typedef struct
00082 {
00083   DAC_TypeDef                 *Instance;     /*!< Register base address             */
00084
00085   __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
00086
00087   HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
00088
00089   DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
00090
00091   DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
00092
00093   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
00094
00095 }DAC_HandleTypeDef;
00096
00097 /**
00098   * @brief   DAC Configuration regular Channel structure definition
00099   */
00100 typedef struct
00101 {
00102   uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
00103                                    This parameter can be a value of @ref DACEx_trigger_selection
00104                                    Note: For STM32F100x high-density value line devices, additional trigger sources are available. */
00105
00106   uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
00107                                    This parameter can be a value of @ref DAC_output_buffer */
00108
00109 }DAC_ChannelConfTypeDef;
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Exported constants --------------------------------------------------------*/
00116
00117 /** @defgroup DAC_Exported_Constants DAC Exported Constants
00118   * @{
00119   */
00120
00121 /** @defgroup DAC_Error_Code DAC Error Code
00122   * @{
00123   */
00124 #define  HAL_DAC_ERROR_NONE              0x00000000U    /*!< No error                          */
00125 #define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x00000001U    /*!< DAC channel1 DMA underrun error   */
00126 #define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x00000002U    /*!< DAC channel2 DMA underrun error   */
00127 #define  HAL_DAC_ERROR_DMA               0x00000004U    /*!< DMA error                         */
00128 /**
00129   * @}
00130   */
00131
00132 /** @defgroup DAC_output_buffer DAC output buffer
00133   * @{
00134   */
00135 #define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
00136 #define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
00137
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup DAC_Channel_selection DAC Channel selection
00143   * @{
00144   */
00145 #define DAC_CHANNEL_1                      0x00000000U
00146 #define DAC_CHANNEL_2                      0x00000010U
00147
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup DAC_data_alignement DAC data alignement
00153   * @{
00154   */
00155 #define DAC_ALIGN_12B_R                    0x00000000U
00156 #define DAC_ALIGN_12B_L                    0x00000004U
00157 #define DAC_ALIGN_8B_R                     0x00000008U
00158
00159 /**
00160   * @}
00161   */
00162
00163 /**
00164   * @}
00165   */
00166
00167 /* Exported macro ------------------------------------------------------------*/
00168
00169 /** @defgroup DAC_Exported_Macros DAC Exported Macros
00170   * @{
00171   */
00172
00173 /** @brief Reset DAC handle state
00174   * @param  __HANDLE__: specifies the DAC handle.
00175   * @retval None
00176   */
00177 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
00178
00179 /** @brief Enable the DAC channel
00180   * @param  __HANDLE__: specifies the DAC handle.
00181   * @param  __DAC_Channel__: specifies the DAC channel
00182   * @retval None
00183   */
00184 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
00185 ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
00186
00187 /** @brief Disable the DAC channel
00188   * @param  __HANDLE__: specifies the DAC handle
00189   * @param  __DAC_Channel__: specifies the DAC channel.
00190   * @retval None
00191   */
00192 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
00193 ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
00194
00195
00196 /**
00197   * @}
00198   */
00199
00200 /* Private macro -------------------------------------------------------------*/
00201
00202 /** @defgroup DAC_Private_Macros DAC Private Macros
00203   * @{
00204   */
00205 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
00206                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
00207
00208 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
00209                                  ((CHANNEL) == DAC_CHANNEL_2))
00210
00211 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
00212                              ((ALIGN) == DAC_ALIGN_12B_L) || \
00213                              ((ALIGN) == DAC_ALIGN_8B_R))
00214
00215 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
00216
00217 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
00218
00219 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__))
00220
00221 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
00222
00223 /**
00224   * @}
00225   */
00226
00227
00228 /* Include DAC HAL Extension module */
00229 #include "stm32f1xx_hal_dac_ex.h"
00230
00231 /* Exported functions --------------------------------------------------------*/
00232
00233 /** @addtogroup DAC_Exported_Functions
00234   * @{
00235   */
00236
00237 /** @addtogroup DAC_Exported_Functions_Group1
00238   * @{
00239   */
00240 /* Initialization and de-initialization functions *****************************/
00241 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
00242 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
00243 void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
00244 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
00245
00246 /**
00247   * @}
00248   */
00249
00250 /** @addtogroup DAC_Exported_Functions_Group2
00251   * @{
00252   */
00253 /* IO operation functions *****************************************************/
00254 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
00255 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
00256 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
00257 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
00258 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
00259 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @addtogroup DAC_Exported_Functions_Group3
00266   * @{
00267   */
00268 /* Peripheral Control functions ***********************************************/
00269 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
00270
00271 /**
00272   * @}
00273   */
00274
00275 /** @addtogroup DAC_Exported_Functions_Group4
00276   * @{
00277   */
00278 /* Peripheral State functions *************************************************/
00279 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
00280 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
00281
00282 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00283 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
00284 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
00285
00286
00287 /**
00288   * @}
00289   */
00290
00291 /**
00292   * @}
00293   */
00294
00295 /** @addtogroup DAC_Private_Functions DAC Private Functions
00296   * @{
00297   */
00298 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
00299 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
00300 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
00301
00302 /**
00303   * @}
00304   */
00305
00306 /**
00307   * @}
00308   */
00309
00310 /**
00311   * @}
00312   */
00313
00314 #endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00315
00316 #ifdef __cplusplus
00317 }
00318 #endif
00319
00320
00321 #endif /*__STM32F1xx_HAL_DAC_H */
00322
00323 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00324
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dac_ex.c Source File

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stm32f1xx_hal_dac_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_dac_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   DAC HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of DAC extension peripheral:
00010   *           + Extended features functions
00011   *
00012   *
00013   @verbatim
00014   ==============================================================================
00015                       ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
00019           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
00020           HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
00021       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
00022       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
00023
00024  @endverbatim
00025   ******************************************************************************
00026   * @attention
00027   *
00028   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00029   *
00030   * Redistribution and use in source and binary forms, with or without modification,
00031   * are permitted provided that the following conditions are met:
00032   *   1. Redistributions of source code must retain the above copyright notice,
00033   *      this list of conditions and the following disclaimer.
00034   *   2. Redistributions in binary form must reproduce the above copyright notice,
00035   *      this list of conditions and the following disclaimer in the documentation
00036   *      and/or other materials provided with the distribution.
00037   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00038   *      may be used to endorse or promote products derived from this software
00039   *      without specific prior written permission.
00040   *
00041   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00042   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00043   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00044   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00045   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00046   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00047   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00048   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00049   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00050   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00051   *
00052   ******************************************************************************
00053   */
00054
00055
00056 /* Includes ------------------------------------------------------------------*/
00057 #include "stm32f1xx_hal.h"
00058
00059 /** @addtogroup STM32F1xx_HAL_Driver
00060   * @{
00061   */
00062
00063 /** @defgroup DACEx DACEx
00064   * @brief DACEx driver module
00065   * @{
00066   */
00067
00068 #ifdef HAL_DAC_MODULE_ENABLED
00069 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
00070
00071 /* Private typedef -----------------------------------------------------------*/
00072 /* Private define ------------------------------------------------------------*/
00073 /* Private macro -------------------------------------------------------------*/
00074 /* Private variables ---------------------------------------------------------*/
00075 /* Private function prototypes -----------------------------------------------*/
00076 /* Exported functions --------------------------------------------------------*/
00077
00078 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
00079   * @{
00080   */
00081
00082 /** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
00083  *  @brief    Extended features functions
00084  *
00085 @verbatim
00086   ==============================================================================
00087                  ##### Extended features functions #####
00088   ==============================================================================
00089     [..]  This section provides functions allowing to:
00090       (+) Start conversion.
00091       (+) Stop conversion.
00092       (+) Start conversion and enable DMA transfer.
00093       (+) Stop conversion and disable DMA transfer.
00094       (+) Get result of conversion.
00095       (+) Get result of dual mode conversion.
00096
00097 @endverbatim
00098   * @{
00099   */
00100
00101 /**
00102   * @brief  Returns the last data output value of the selected DAC channel.
00103   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00104   *         the configuration information for the specified DAC.
00105   * @retval The selected DAC channel data output value.
00106   */
00107 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
00108 {
00109   uint32_t tmp = 0U;
00110
00111   tmp |= hdac->Instance->DOR1;
00112
00113   tmp |= hdac->Instance->DOR2 << 16U;
00114
00115   /* Returns the DAC channel data output register value */
00116   return tmp;
00117 }
00118
00119 /**
00120   * @brief  Enables or disables the selected DAC channel wave generation.
00121   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00122   *         the configuration information for the specified DAC.
00123   * @param  Channel: The selected DAC channel.
00124   *          This parameter can be one of the following values:
00125   *            DAC_CHANNEL_1 / DAC_CHANNEL_2
00126   * @param  Amplitude: Select max triangle amplitude.
00127   *          This parameter can be one of the following values:
00128   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
00129   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
00130   *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
00131   *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
00132   *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
00133   *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
00134   *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
00135   *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
00136   *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
00137   *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
00138   *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
00139   *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
00140   * @retval HAL status
00141   */
00142 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00143 {
00144   /* Check the parameters */
00145   assert_param(IS_DAC_CHANNEL(Channel));
00146   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00147
00148   /* Process locked */
00149   __HAL_LOCK(hdac);
00150
00151   /* Change DAC state */
00152   hdac->State = HAL_DAC_STATE_BUSY;
00153
00154   /* Enable the selected wave generation for the selected DAC channel */
00155   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
00156
00157   /* Change DAC state */
00158   hdac->State = HAL_DAC_STATE_READY;
00159
00160   /* Process unlocked */
00161   __HAL_UNLOCK(hdac);
00162
00163   /* Return function status */
00164   return HAL_OK;
00165 }
00166
00167 /**
00168   * @brief  Enables or disables the selected DAC channel wave generation.
00169   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00170   *         the configuration information for the specified DAC.
00171   * @param  Channel: The selected DAC channel.
00172   *          This parameter can be one of the following values:
00173   *            DAC_CHANNEL_1 / DAC_CHANNEL_2
00174   * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation.
00175   *          This parameter can be one of the following values:
00176   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
00177   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
00178   *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
00179   *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
00180   *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
00181   *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
00182   *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
00183   *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
00184   *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
00185   *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
00186   *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
00187   *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
00188   * @retval HAL status
00189   */
00190 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
00191 {
00192   /* Check the parameters */
00193   assert_param(IS_DAC_CHANNEL(Channel));
00194   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
00195
00196   /* Process locked */
00197   __HAL_LOCK(hdac);
00198
00199   /* Change DAC state */
00200   hdac->State = HAL_DAC_STATE_BUSY;
00201
00202   /* Enable the selected wave generation for the selected DAC channel */
00203   MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
00204
00205   /* Change DAC state */
00206   hdac->State = HAL_DAC_STATE_READY;
00207
00208   /* Process unlocked */
00209   __HAL_UNLOCK(hdac);
00210
00211   /* Return function status */
00212   return HAL_OK;
00213 }
00214
00215 /**
00216   * @brief  Set the specified data holding register value for dual DAC channel.
00217   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00218   *               the configuration information for the specified DAC.
00219   * @param  Alignment: Specifies the data alignment for dual channel DAC.
00220   *          This parameter can be one of the following values:
00221   *            DAC_ALIGN_8B_R: 8bit right data alignment selected
00222   *            DAC_ALIGN_12B_L: 12bit left data alignment selected
00223   *            DAC_ALIGN_12B_R: 12bit right data alignment selected
00224   * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
00225   * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
00226   * @note   In dual mode, a unique register access is required to write in both
00227   *          DAC channels at the same time.
00228   * @retval HAL status
00229   */
00230 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
00231 {
00232   uint32_t data = 0U, tmp = 0U;
00233
00234   /* Check the parameters */
00235   assert_param(IS_DAC_ALIGN(Alignment));
00236   assert_param(IS_DAC_DATA(Data1));
00237   assert_param(IS_DAC_DATA(Data2));
00238
00239   /* Calculate and set dual DAC data holding register value */
00240   if (Alignment == DAC_ALIGN_8B_R)
00241   {
00242     data = ((uint32_t)Data2 << 8U) | Data1;
00243   }
00244   else
00245   {
00246     data = ((uint32_t)Data2 << 16U) | Data1;
00247   }
00248
00249   tmp = (uint32_t)hdac->Instance;
00250   tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
00251
00252   /* Set the dual DAC selected data holding register */
00253   *(__IO uint32_t *)tmp = data;
00254
00255   /* Return function status */
00256   return HAL_OK;
00257 }
00258
00259 /**
00260   * @brief  Conversion complete callback in non blocking mode for Channel2
00261   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00262   *         the configuration information for the specified DAC.
00263   * @retval None
00264   */
00265 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00266 {
00267   /* Prevent unused argument(s) compilation warning */
00268   UNUSED(hdac);
00269   /* NOTE : This function Should not be modified, when the callback is needed,
00270             the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
00271    */
00272 }
00273
00274 /**
00275   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2
00276   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00277   *         the configuration information for the specified DAC.
00278   * @retval None
00279   */
00280 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
00281 {
00282   /* Prevent unused argument(s) compilation warning */
00283   UNUSED(hdac);
00284   /* NOTE : This function Should not be modified, when the callback is needed,
00285             the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
00286    */
00287 }
00288
00289 /**
00290   * @brief  Error DAC callback for Channel2.
00291   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00292   *         the configuration information for the specified DAC.
00293   * @retval None
00294   */
00295 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
00296 {
00297   /* Prevent unused argument(s) compilation warning */
00298   UNUSED(hdac);
00299   /* NOTE : This function Should not be modified, when the callback is needed,
00300             the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
00301    */
00302 }
00303
00304 #if defined (STM32F100xB) || defined (STM32F100xE)
00305 /**
00306   * @brief  DMA underrun DAC callback for channel1.
00307   *         Note: For STM32F100x devices with specific feature: DMA underrun.
00308   *         On these devices, this function uses the interruption of DMA
00309   *         underrun.
00310   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00311   *         the configuration information for the specified DAC.
00312   * @retval None
00313   */
00314 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
00315 {
00316   /* Prevent unused argument(s) compilation warning */
00317   UNUSED(hdac);
00318   /* NOTE : This function Should not be modified, when the callback is needed,
00319             the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
00320    */
00321 }
00322
00323 /**
00324   * @brief  DMA underrun DAC callback for channel2.
00325   *         Note: For STM32F100x devices with specific feature: DMA underrun.
00326   *         On these devices, this function uses the interruption of DMA
00327   *         underrun.
00328   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00329   *         the configuration information for the specified DAC.
00330   * @retval None
00331   */
00332 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
00333 {
00334   /* Prevent unused argument(s) compilation warning */
00335   UNUSED(hdac);
00336   /* NOTE : This function Should not be modified, when the callback is needed,
00337             the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
00338    */
00339 }
00340 #endif /* STM32F100xB) || defined (STM32F100xE) */
00341
00342 /**
00343   * @}
00344   */
00345
00346 #if defined (STM32F100xB) || defined (STM32F100xE)
00347 /**
00348   * @brief  Enables DAC and starts conversion of channel.
00349   *         Note: For STM32F100x devices with specific feature: DMA underrun.
00350   *         On these devices, this function enables the interruption of DMA
00351   *         underrun.
00352   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00353   *         the configuration information for the specified DAC.
00354   * @param  Channel: The selected DAC channel.
00355   *          This parameter can be one of the following values:
00356   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00357   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00358   * @param  pData: The destination peripheral Buffer address.
00359   * @param  Length: The length of data to be transferred from memory to DAC peripheral
00360   * @param  Alignment: Specifies the data alignment for DAC channel.
00361   *          This parameter can be one of the following values:
00362   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
00363   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
00364   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
00365   * @retval HAL status
00366   */
00367 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
00368 {
00369   uint32_t tmpreg = 0U;
00370
00371   /* Check the parameters */
00372   assert_param(IS_DAC_CHANNEL(Channel));
00373   assert_param(IS_DAC_ALIGN(Alignment));
00374
00375   /* Process locked */
00376   __HAL_LOCK(hdac);
00377
00378   /* Change DAC state */
00379   hdac->State = HAL_DAC_STATE_BUSY;
00380
00381   if(Channel == DAC_CHANNEL_1)
00382   {
00383     /* Set the DMA transfer complete callback for channel1 */
00384     hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
00385
00386     /* Set the DMA half transfer complete callback for channel1 */
00387     hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
00388
00389     /* Set the DMA error callback for channel1 */
00390     hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
00391
00392     /* Enable the selected DAC channel1 DMA request */
00393     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00394
00395     /* Case of use of channel 1 */
00396     switch(Alignment)
00397     {
00398       case DAC_ALIGN_12B_R:
00399         /* Get DHR12R1 address */
00400         tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
00401         break;
00402       case DAC_ALIGN_12B_L:
00403         /* Get DHR12L1 address */
00404         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
00405         break;
00406       case DAC_ALIGN_8B_R:
00407         /* Get DHR8R1 address */
00408         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
00409         break;
00410       default:
00411         break;
00412     }
00413   }
00414   else
00415   {
00416     /* Set the DMA transfer complete callback for channel2 */
00417     hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
00418
00419     /* Set the DMA half transfer complete callback for channel2 */
00420     hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
00421
00422     /* Set the DMA error callback for channel2 */
00423     hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
00424
00425     /* Enable the selected DAC channel2 DMA request */
00426     SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00427
00428     /* Case of use of channel 2 */
00429     switch(Alignment)
00430     {
00431       case DAC_ALIGN_12B_R:
00432         /* Get DHR12R2 address */
00433         tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
00434         break;
00435       case DAC_ALIGN_12B_L:
00436         /* Get DHR12L2 address */
00437         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
00438         break;
00439       case DAC_ALIGN_8B_R:
00440         /* Get DHR8R2 address */
00441         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
00442         break;
00443       default:
00444         break;
00445     }
00446   }
00447
00448   /* Enable the DMA channel */
00449   if(Channel == DAC_CHANNEL_1)
00450   {
00451     /* Enable the DAC DMA underrun interrupt */
00452     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
00453
00454     /* Enable the DMA channel */
00455     HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
00456   }
00457   else
00458   {
00459     /* Enable the DAC DMA underrun interrupt */
00460     __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
00461
00462     /* Enable the DMA channel */
00463     HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
00464   }
00465
00466   /* Enable the Peripharal */
00467   __HAL_DAC_ENABLE(hdac, Channel);
00468
00469   /* Process Unlocked */
00470   __HAL_UNLOCK(hdac);
00471
00472   /* Return function status */
00473   return HAL_OK;
00474 }
00475 #endif /* STM32F100xB) || defined (STM32F100xE) */
00476
00477 #if defined (STM32F100xB) || defined (STM32F100xE)
00478 /**
00479   * @brief  Disables DAC and stop conversion of channel.
00480   *         Note: For STM32F100x devices with specific feature: DMA underrun.
00481   *         On these devices, this function disables the interruption of DMA
00482   *         underrun.
00483   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00484   *         the configuration information for the specified DAC.
00485   * @param  Channel: The selected DAC channel.
00486   *          This parameter can be one of the following values:
00487   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
00488   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
00489   * @retval HAL status
00490   */
00491 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
00492 {
00493   HAL_StatusTypeDef status = HAL_OK;
00494
00495   /* Check the parameters */
00496   assert_param(IS_DAC_CHANNEL(Channel));
00497
00498   /* Disable the selected DAC channel DMA request */
00499   hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
00500
00501   /* Disable the Peripharal */
00502   __HAL_DAC_DISABLE(hdac, Channel);
00503
00504   /* Disable the DMA Channel */
00505   /* Channel1 is used */
00506   if(Channel == DAC_CHANNEL_1)
00507   {
00508     /* Disable the DMA channel */
00509     status = HAL_DMA_Abort(hdac->DMA_Handle1);
00510
00511     /* Disable the DAC DMA underrun interrupt */
00512     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
00513   }
00514   else /* Channel2 is used for */
00515   {
00516     /* Disable the DMA channel */
00517     status = HAL_DMA_Abort(hdac->DMA_Handle2);
00518
00519     /* Disable the DAC DMA underrun interrupt */
00520     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
00521   }
00522
00523   /* Check if DMA Channel effectively disabled */
00524   if(status != HAL_OK)
00525   {
00526     /* Update ADC state machine to error */
00527     hdac->State = HAL_DAC_STATE_ERROR;
00528   }
00529   else
00530   {
00531     /* Change DAC state */
00532     hdac->State = HAL_DAC_STATE_READY;
00533   }
00534
00535   /* Return function status */
00536   return status;
00537 }
00538 #endif /* STM32F100xB) || defined (STM32F100xE) */
00539
00540 #if defined (STM32F100xB) || defined (STM32F100xE)
00541 /**
00542   * @brief  Handles DAC interrupt request
00543   *         Note: For STM32F100x devices with specific feature: DMA underrun.
00544   *         On these devices, this function uses the interruption of DMA
00545   *         underrun.
00546   * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
00547   *         the configuration information for the specified DAC.
00548   * @retval None
00549   */
00550 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
00551 {
00552
00553   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
00554   {
00555     /* Check underrun flag of DAC channel 1 */
00556     if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
00557     {
00558       /* Change DAC state to error state */
00559       hdac->State = HAL_DAC_STATE_ERROR;
00560
00561       /* Set DAC error code to chanel1 DMA underrun error */
00562       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
00563
00564       /* Clear the underrun flag */
00565       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
00566
00567       /* Disable the selected DAC channel1 DMA request */
00568       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
00569
00570       /* Error callback */
00571       HAL_DAC_DMAUnderrunCallbackCh1(hdac);
00572     }
00573   }
00574
00575   if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
00576   {
00577     /* Check underrun flag of DAC channel 2 */
00578     if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
00579     {
00580       /* Change DAC state to error state */
00581       hdac->State = HAL_DAC_STATE_ERROR;
00582
00583       /* Set DAC error code to channel2 DMA underrun error */
00584       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
00585
00586       /* Clear the underrun flag */
00587       __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
00588
00589       /* Disable the selected DAC channel1 DMA request */
00590       CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
00591
00592       /* Error callback */
00593       HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
00594     }
00595   }
00596 }
00597 #endif /* STM32F100xB || STM32F100xE */
00598
00599
00600 /**
00601   * @}
00602   */
00603
00604 /** @defgroup DACEx_Private_Functions DACEx Private Functions
00605   * @{
00606   */
00607
00608 /**
00609   * @brief  DMA conversion complete callback.
00610   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00611   *                the configuration information for the specified DMA module.
00612   * @retval None
00613   */
00614 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
00615 {
00616   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00617
00618   HAL_DACEx_ConvCpltCallbackCh2(hdac);
00619
00620   hdac->State= HAL_DAC_STATE_READY;
00621 }
00622
00623 /**
00624   * @brief  DMA half transfer complete callback.
00625   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00626   *                the configuration information for the specified DMA module.
00627   * @retval None
00628   */
00629 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
00630 {
00631     DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00632     /* Conversion complete callback */
00633     HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
00634 }
00635
00636 /**
00637   * @brief  DMA error callback
00638   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00639   *                the configuration information for the specified DMA module.
00640   * @retval None
00641   */
00642 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
00643 {
00644   DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
00645
00646   /* Set DAC error code to DMA error */
00647   hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
00648
00649   HAL_DACEx_ErrorCallbackCh2(hdac);
00650
00651   hdac->State= HAL_DAC_STATE_READY;
00652 }
00653
00654 /**
00655   * @}
00656   */
00657
00658 #endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00659 #endif /* HAL_DAC_MODULE_ENABLED */
00660
00661 /**
00662   * @}
00663   */
00664
00665 /**
00666   * @}
00667   */
00668
00669 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dac_ex.h Source File

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stm32f1xx_hal_dac_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_dac_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of DAC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_DAC_EX_H
00040 #define __STM32F1xx_HAL_DAC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f1xx_hal_def.h"
00050
00051 /** @addtogroup STM32F1xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup DACEx
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060
00061 /* Exported constants --------------------------------------------------------*/
00062
00063 /** @defgroup DACEx_Exported_Constants DACEx Exported Constants
00064   * @{
00065   */
00066
00067 /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
00068   * @{
00069   */
00070 #define DAC_LFSRUNMASK_BIT0                0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
00071 #define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
00072 #define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
00073 #define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
00074 #define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
00075 #define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
00076 #define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
00077 #define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
00078 #define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
00079 #define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
00080 #define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
00081 #define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
00082 #define DAC_TRIANGLEAMPLITUDE_1            0x00000000U /*!< Select max triangle amplitude of 1 */
00083 #define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
00084 #define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
00085 #define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
00086 #define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
00087 #define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
00088 #define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
00089 #define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
00090 #define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
00091 #define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
00092 #define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
00093 #define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
00094
00095 /**
00096   * @}
00097   */
00098
00099 /** @defgroup DACEx_trigger_selection DAC trigger selection
00100   * @{
00101   */
00102 #define DAC_TRIGGER_NONE                   0x00000000U            /*!< Conversion is automatic once the DAC1_DHRxxxx register
00103                                                                        has been loaded, and not by external trigger */
00104 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)                                                    DAC_CR_TEN1)  /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
00105 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(                 DAC_CR_TSEL1_1                  | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
00106 #define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2                                   | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
00107 #define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
00108 #define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
00109 #define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1                                     | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
00110
00111 #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
00112 /* For STM32F10x high-density and XL-density devices: TIM8 */
00113 #define DAC_TRIGGER_T8_TRGO                ((uint32_t)                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1)  /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
00114 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
00115
00116 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
00117 /* For STM32F10x connectivity line devices and STM32F100x devices: TIM3 */
00118 #define DAC_TRIGGER_T3_TRGO                ((uint32_t)                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1)  /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
00119 #endif /* STM32F100xB || STM32F100xE || STM32F105xC || STM32F107xC */
00120
00121 /* Availability of trigger from TIM5 and TIM15:                               */
00122 /*  - For STM32F10x value line devices STM32F100xB:                           */
00123 /*    trigger from TIM15 is available, TIM5 not available.                    */
00124 /*  - For STM32F10x value line devices STM32F100xE:                           */
00125 /*    trigger from TIM15 and TIM5 are both available,                         */
00126 /*    selection depends on remap (with TIM5 as default configuration).        */
00127 /*  - Other STM32F1 devices:                                                  */
00128 /*    trigger from TIM5 is available, TIM15 not  available.                   */
00129 #if defined (STM32F100xB)
00130 #define DAC_TRIGGER_T15_TRGO               ((uint32_t)(                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
00131 #else
00132
00133 #define DAC_TRIGGER_T5_TRGO                ((uint32_t)(                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
00134
00135 #if defined (STM32F100xE)
00136 /*!< DAC trigger availability depending on STM32F1 devices:
00137      For STM32F100x high-density value line devices, the TIM15 TRGO event can be selected
00138      as replacement of TIM5 TRGO if the MISC_REMAP bit in the AFIO_MAPR2 register is set.
00139      Refer to macro "__HAL_AFIO_REMAP_MISC_ENABLE()/__HAL_AFIO_REMAP_MISC_DISABLE()".
00140      Otherwise, TIM5 TRGO is used and TIM15 TRGO is not used (default case).
00141      For more details please refer to the AFIO section. */
00142 #define DAC_TRIGGER_T15_TRGO    DAC_TRIGGER_T5_TRGO
00143 #endif /* STM32F100xE */
00144
00145 #endif /* STM32F100xB */
00146 /**
00147   * @}
00148   */
00149
00150 #if defined (STM32F100xB) || defined (STM32F100xE)
00151 /** @defgroup DAC_flags_definition DAC flags definition
00152   * @{
00153   */
00154 #define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00155 #define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00156
00157 /**
00158   * @}
00159   */
00160
00161 /** @defgroup DAC_IT_definition DAC IT definition
00162   * @{
00163   */
00164 #define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
00165 #define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)
00166
00167 /**
00168   * @}
00169   */
00170 #endif /* STM32F100xB || STM32F100xE */
00171
00172 /**
00173   * @}
00174   */
00175
00176 /* Exported macro ------------------------------------------------------------*/
00177
00178 #if defined (STM32F100xB) || defined (STM32F100xE)
00179 /** @defgroup DACEx_Exported_Macros DACEx Exported Macros
00180   * @{
00181   */
00182
00183 /** @brief Enable the DAC interrupt
00184   * @param  __HANDLE__: specifies the DAC handle
00185   * @param  __INTERRUPT__: specifies the DAC interrupt.
00186   *          This parameter can be any combination of the following values:
00187   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00188   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00189   * @retval None
00190   */
00191 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
00192
00193 /** @brief Disable the DAC interrupt
00194   * @param  __HANDLE__: specifies the DAC handle
00195   * @param  __INTERRUPT__: specifies the DAC interrupt.
00196   *          This parameter can be any combination of the following values:
00197   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00198   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00199   * @retval None
00200   */
00201 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
00202
00203 /** @brief  Checks if the specified DAC interrupt source is enabled or disabled.
00204   * @param __HANDLE__: DAC handle
00205   * @param __INTERRUPT__: DAC interrupt source to check
00206   *          This parameter can be any combination of the following values:
00207   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
00208   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
00209   * @retval State of interruption (SET or RESET)
00210   */
00211 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
00212
00213 /** @brief  Get the selected DAC's flag status.
00214   * @param  __HANDLE__: specifies the DAC handle.
00215   * @param  __FLAG__: specifies the DAC flag to get.
00216   *          This parameter can be any combination of the following values:
00217   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
00218   *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
00219   * @retval None
00220   */
00221 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00222
00223 /** @brief  Clear the DAC's flag.
00224   * @param  __HANDLE__: specifies the DAC handle.
00225   * @param  __FLAG__: specifies the DAC flag to clear.
00226   *          This parameter can be any combination of the following values:
00227   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
00228   *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
00229   * @retval None
00230   */
00231 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
00232
00233
00234 /**
00235   * @}
00236   */
00237 #endif /* STM32F100xB || STM32F100xE */
00238
00239 /* Private macro -------------------------------------------------------------*/
00240
00241 /** @defgroup DACEx_Private_Macros DACEx Private Macros
00242   * @{
00243   */
00244 #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
00245 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)    || \
00246                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00247                                  ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
00248                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00249                                  ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
00250                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00251                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
00252                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00253                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00254 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
00255 #if defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
00256 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)    || \
00257                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
00258                                  ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
00259                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
00260                                  ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
00261                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
00262                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
00263                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
00264                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00265 #endif /* STM32F100xE || STM32F105xC || STM32F107xC */
00266 #if defined (STM32F100xB)
00267 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)     || \
00268                                  ((TRIGGER) == DAC_TRIGGER_T6_TRGO)  || \
00269                                  ((TRIGGER) == DAC_TRIGGER_T3_TRGO)  || \
00270                                  ((TRIGGER) == DAC_TRIGGER_T7_TRGO)  || \
00271                                  ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
00272                                  ((TRIGGER) == DAC_TRIGGER_T2_TRGO)  || \
00273                                  ((TRIGGER) == DAC_TRIGGER_T4_TRGO)  || \
00274                                  ((TRIGGER) == DAC_TRIGGER_EXT_IT9)  || \
00275                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
00276 #endif /* STM32F100xB */
00277
00278 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
00279                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
00280                                                       ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
00281                                                       ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
00282                                                       ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
00283                                                       ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
00284                                                       ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
00285                                                       ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
00286                                                       ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
00287                                                       ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
00288                                                       ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
00289                                                       ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
00290                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
00291                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
00292                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
00293                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
00294                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
00295                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
00296                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
00297                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
00298                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
00299                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
00300                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
00301                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
00302
00303 /**
00304   * @}
00305   */
00306
00307
00308 /* Exported functions --------------------------------------------------------*/
00309
00310 /** @addtogroup DACEx_Exported_Functions
00311   * @{
00312   */
00313
00314 /** @addtogroup DACEx_Exported_Functions_Group1
00315   * @{
00316   */
00317 /* Extension features functions ***********************************************/
00318
00319 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
00320 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00321 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
00322 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
00323
00324 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00325 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
00326 void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
00327
00328 #if defined (STM32F100xB) || defined (STM32F100xE)
00329 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
00330 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
00331 void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
00332 #endif /* STM32F100xB) || defined (STM32F100xE) */
00333
00334 /**
00335   * @}
00336   */
00337
00338
00339
00340
00341 /**
00342   * @}
00343   */
00344
00345 /** @addtogroup DACEx_Private_Functions
00346   * @{
00347   */
00348 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
00349 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
00350 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
00351
00352 /**
00353   * @}
00354   */
00355
00356 /**
00357   * @}
00358   */
00359
00360 /**
00361   * @}
00362   */
00363
00364 #endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00365
00366 #ifdef __cplusplus
00367 }
00368 #endif
00369
00370 #endif /*__STM32F1xx_HAL_DAC_EX_H */
00371
00372 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dma.c Source File

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stm32f1xx_hal_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_dma.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   DMA HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *         functionalities of the Direct Memory Access (DMA) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and errors functions
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018    (#) Enable and configure the peripheral to be connected to the DMA Channel
00019        (except for internal SRAM / FLASH memories: no initialization is
00020        necessary). Please refer to the Reference manual for connection between peripherals
00021        and DMA requests.
00022
00023    (#) For a given Channel, program the required configuration through the following parameters:
00024        Channel request, Transfer Direction, Source and Destination data formats,
00025        Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
00026        using HAL_DMA_Init() function.
00027
00028    (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
00029        detection.
00030
00031    (#) Use HAL_DMA_Abort() function to abort the current transfer
00032
00033      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
00034      *** Polling mode IO operation ***
00035      =================================
00036     [..]
00037           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
00038               address and destination address and the Length of data to be transferred
00039           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
00040               case a fixed Timeout can be configured by User depending from his application.
00041
00042      *** Interrupt mode IO operation ***
00043      ===================================
00044     [..]
00045           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
00046           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
00047           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
00048               Source address and destination address and the Length of data to be transferred.
00049               In this case the DMA interrupt is configured
00050           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
00051           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
00052               add his own function by customization of function pointer XferCpltCallback and
00053               XferErrorCallback (i.e. a member of DMA handle structure).
00054
00055      *** DMA HAL driver macros list ***
00056      =============================================
00057       [..]
00058        Below the list of most used macros in DMA HAL driver.
00059
00060        (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
00061        (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
00062        (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
00063        (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
00064        (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
00065        (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
00066        (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
00067
00068      [..]
00069       (@) You can refer to the DMA HAL driver header file for more useful macros
00070
00071   @endverbatim
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00076   *
00077   * Redistribution and use in source and binary forms, with or without modification,
00078   * are permitted provided that the following conditions are met:
00079   *   1. Redistributions of source code must retain the above copyright notice,
00080   *      this list of conditions and the following disclaimer.
00081   *   2. Redistributions in binary form must reproduce the above copyright notice,
00082   *      this list of conditions and the following disclaimer in the documentation
00083   *      and/or other materials provided with the distribution.
00084   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00085   *      may be used to endorse or promote products derived from this software
00086   *      without specific prior written permission.
00087   *
00088   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00089   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00090   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00091   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00092   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00093   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00094   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00095   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00096   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00097   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00098   *
00099   ******************************************************************************
00100   */
00101
00102 /* Includes ------------------------------------------------------------------*/
00103 #include "stm32f1xx_hal.h"
00104
00105 /** @addtogroup STM32F1xx_HAL_Driver
00106   * @{
00107   */
00108
00109 /** @defgroup DMA DMA
00110   * @brief DMA HAL module driver
00111   * @{
00112   */
00113
00114 #ifdef HAL_DMA_MODULE_ENABLED
00115
00116 /* Private typedef -----------------------------------------------------------*/
00117 /* Private define ------------------------------------------------------------*/
00118 /* Private macro -------------------------------------------------------------*/
00119 /* Private variables ---------------------------------------------------------*/
00120 /* Private function prototypes -----------------------------------------------*/
00121 /** @defgroup DMA_Private_Functions DMA Private Functions
00122   * @{
00123   */
00124 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00125 /**
00126   * @}
00127   */
00128
00129 /* Exported functions ---------------------------------------------------------*/
00130
00131 /** @defgroup DMA_Exported_Functions DMA Exported Functions
00132   * @{
00133   */
00134
00135 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
00136   *  @brief   Initialization and de-initialization functions
00137   *
00138 @verbatim
00139  ===============================================================================
00140              ##### Initialization and de-initialization functions  #####
00141  ===============================================================================
00142     [..]
00143     This section provides functions allowing to initialize the DMA Channel source
00144     and destination addresses, incrementation and data sizes, transfer direction,
00145     circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
00146     [..]
00147     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
00148     reference manual.
00149
00150 @endverbatim
00151   * @{
00152   */
00153
00154 /**
00155   * @brief  Initialize the DMA according to the specified
00156   *         parameters in the DMA_InitTypeDef and initialize the associated handle.
00157   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
00158   *               the configuration information for the specified DMA Channel.
00159   * @retval HAL status
00160   */
00161 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
00162 {
00163   uint32_t tmp = 0U;
00164
00165   /* Check the DMA handle allocation */
00166   if(hdma == NULL)
00167   {
00168     return HAL_ERROR;
00169   }
00170
00171   /* Check the parameters */
00172   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00173   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
00174   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
00175   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
00176   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
00177   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
00178   assert_param(IS_DMA_MODE(hdma->Init.Mode));
00179   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
00180
00181 #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
00182   /* calculation of the channel index */
00183   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00184   {
00185     /* DMA1 */
00186     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
00187     hdma->DmaBaseAddress = DMA1;
00188   }
00189   else
00190   {
00191     /* DMA2 */
00192     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
00193     hdma->DmaBaseAddress = DMA2;
00194   }
00195 #else
00196   /* DMA1 */
00197   hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
00198   hdma->DmaBaseAddress = DMA1;
00199 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
00200
00201   /* Change DMA peripheral state */
00202   hdma->State = HAL_DMA_STATE_BUSY;
00203
00204   /* Get the CR register value */
00205   tmp = hdma->Instance->CCR;
00206
00207   /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
00208   tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
00209                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
00210                       DMA_CCR_DIR));
00211
00212   /* Prepare the DMA Channel configuration */
00213   tmp |=  hdma->Init.Direction        |
00214           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
00215           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
00216           hdma->Init.Mode                | hdma->Init.Priority;
00217
00218   /* Write to DMA Channel CR register */
00219   hdma->Instance->CCR = tmp;
00220
00221
00222   /* Clean callbacks */
00223   hdma->XferCpltCallback = NULL;
00224   hdma->XferHalfCpltCallback = NULL;
00225   hdma->XferErrorCallback = NULL;
00226   hdma->XferAbortCallback = NULL;
00227
00228   /* Initialise the error code */
00229   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00230
00231   /* Initialize the DMA state*/
00232   hdma->State = HAL_DMA_STATE_READY;
00233   /* Allocate lock resource and initialize it */
00234   hdma->Lock = HAL_UNLOCKED;
00235
00236   return HAL_OK;
00237 }
00238
00239 /**
00240   * @brief  DeInitialize the DMA peripheral.
00241   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00242   *               the configuration information for the specified DMA Channel.
00243   * @retval HAL status
00244   */
00245 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
00246 {
00247   /* Check the DMA handle allocation */
00248   if(hdma == NULL)
00249   {
00250     return HAL_ERROR;
00251   }
00252
00253   /* Check the parameters */
00254   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
00255
00256   /* Disable the selected DMA Channelx */
00257   __HAL_DMA_DISABLE(hdma);
00258
00259   /* Reset DMA Channel control register */
00260   hdma->Instance->CCR  = 0U;
00261
00262   /* Reset DMA Channel Number of Data to Transfer register */
00263   hdma->Instance->CNDTR = 0U;
00264
00265   /* Reset DMA Channel peripheral address register */
00266   hdma->Instance->CPAR  = 0U;
00267
00268   /* Reset DMA Channel memory address register */
00269   hdma->Instance->CMAR = 0U;
00270
00271 #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
00272   /* calculation of the channel index */
00273   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
00274   {
00275     /* DMA1 */
00276     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
00277     hdma->DmaBaseAddress = DMA1;
00278   }
00279   else
00280   {
00281     /* DMA2 */
00282     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
00283     hdma->DmaBaseAddress = DMA2;
00284   }
00285 #else
00286   /* DMA1 */
00287   hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
00288   hdma->DmaBaseAddress = DMA1;
00289 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
00290
00291   /* Clear all flags */
00292   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
00293
00294   /* Initialize the error code */
00295   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00296
00297   /* Initialize the DMA state */
00298   hdma->State = HAL_DMA_STATE_RESET;
00299
00300   /* Release Lock */
00301   __HAL_UNLOCK(hdma);
00302
00303   return HAL_OK;
00304 }
00305
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
00311   *  @brief   Input and Output operation functions
00312   *
00313 @verbatim
00314  ===============================================================================
00315                       #####  IO operation functions  #####
00316  ===============================================================================
00317     [..]  This section provides functions allowing to:
00318       (+) Configure the source, destination address and data length and Start DMA transfer
00319       (+) Configure the source, destination address and data length and
00320           Start DMA transfer with interrupt
00321       (+) Abort DMA transfer
00322       (+) Poll for transfer complete
00323       (+) Handle DMA interrupt request
00324
00325 @endverbatim
00326   * @{
00327   */
00328
00329 /**
00330   * @brief  Start the DMA Transfer.
00331   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00332   *               the configuration information for the specified DMA Channel.
00333   * @param  SrcAddress: The source memory Buffer address
00334   * @param  DstAddress: The destination memory Buffer address
00335   * @param  DataLength: The length of data to be transferred from source to destination
00336   * @retval HAL status
00337   */
00338 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00339 {
00340   HAL_StatusTypeDef status = HAL_OK;
00341
00342   /* Check the parameters */
00343   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00344
00345   /* Process locked */
00346   __HAL_LOCK(hdma);
00347
00348   if(HAL_DMA_STATE_READY == hdma->State)
00349   {
00350     /* Change DMA peripheral state */
00351     hdma->State = HAL_DMA_STATE_BUSY;
00352     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00353
00354     /* Disable the peripheral */
00355     __HAL_DMA_DISABLE(hdma);
00356
00357     /* Configure the source, destination address and the data length & clear flags*/
00358     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00359
00360     /* Enable the Peripheral */
00361     __HAL_DMA_ENABLE(hdma);
00362   }
00363   else
00364   {
00365    /* Process Unlocked */
00366    __HAL_UNLOCK(hdma);
00367    status = HAL_BUSY;
00368   }
00369   return status;
00370 }
00371
00372 /**
00373   * @brief  Start the DMA Transfer with interrupt enabled.
00374   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00375   *               the configuration information for the specified DMA Channel.
00376   * @param  SrcAddress: The source memory Buffer address
00377   * @param  DstAddress: The destination memory Buffer address
00378   * @param  DataLength: The length of data to be transferred from source to destination
00379   * @retval HAL status
00380   */
00381 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00382 {
00383   HAL_StatusTypeDef status = HAL_OK;
00384
00385   /* Check the parameters */
00386   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
00387
00388   /* Process locked */
00389   __HAL_LOCK(hdma);
00390
00391   if(HAL_DMA_STATE_READY == hdma->State)
00392   {
00393     /* Change DMA peripheral state */
00394     hdma->State = HAL_DMA_STATE_BUSY;
00395     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
00396
00397     /* Disable the peripheral */
00398     __HAL_DMA_DISABLE(hdma);
00399
00400     /* Configure the source, destination address and the data length & clear flags*/
00401     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
00402
00403     /* Enable the transfer complete interrupt */
00404     /* Enable the transfer Error interrupt */
00405     if(NULL != hdma->XferHalfCpltCallback)
00406     {
00407       /* Enable the Half transfer complete interrupt as well */
00408       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00409     }
00410     else
00411     {
00412       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00413       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
00414     }
00415     /* Enable the Peripheral */
00416     __HAL_DMA_ENABLE(hdma);
00417   }
00418   else
00419   {
00420     /* Process Unlocked */
00421     __HAL_UNLOCK(hdma);
00422
00423     /* Remain BUSY */
00424     status = HAL_BUSY;
00425   }
00426   return status;
00427 }
00428
00429 /**
00430   * @brief  Abort the DMA Transfer.
00431   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00432   *               the configuration information for the specified DMA Channel.
00433   * @retval HAL status
00434   */
00435 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
00436 {
00437   HAL_StatusTypeDef status = HAL_OK;
00438
00439   /* Disable DMA IT */
00440   __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00441
00442   /* Disable the channel */
00443   __HAL_DMA_DISABLE(hdma);
00444
00445   /* Clear all flags */
00446   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
00447
00448   /* Change the DMA state */
00449   hdma->State = HAL_DMA_STATE_READY;
00450
00451   /* Process Unlocked */
00452   __HAL_UNLOCK(hdma);
00453
00454   return status;
00455 }
00456
00457 /**
00458   * @brief  Aborts the DMA Transfer in Interrupt mode.
00459   * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
00460   *                 the configuration information for the specified DMA Channel.
00461   * @retval HAL status
00462   */
00463 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
00464 {
00465   HAL_StatusTypeDef status = HAL_OK;
00466
00467   if(HAL_DMA_STATE_BUSY != hdma->State)
00468   {
00469     /* no transfer ongoing */
00470     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00471
00472     status = HAL_ERROR;
00473   }
00474   else
00475   {
00476     /* Disable DMA IT */
00477     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00478
00479     /* Disable the channel */
00480     __HAL_DMA_DISABLE(hdma);
00481
00482     /* Clear all flags */
00483     __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
00484
00485     /* Change the DMA state */
00486     hdma->State = HAL_DMA_STATE_READY;
00487
00488     /* Process Unlocked */
00489     __HAL_UNLOCK(hdma);
00490
00491     /* Call User Abort callback */
00492     if(hdma->XferAbortCallback != NULL)
00493     {
00494       hdma->XferAbortCallback(hdma);
00495     }
00496   }
00497   return status;
00498 }
00499
00500 /**
00501   * @brief  Polling for transfer complete.
00502   * @param  hdma:    pointer to a DMA_HandleTypeDef structure that contains
00503   *                  the configuration information for the specified DMA Channel.
00504   * @param  CompleteLevel: Specifies the DMA level complete.
00505   * @param  Timeout:       Timeout duration.
00506   * @retval HAL status
00507   */
00508 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
00509 {
00510   uint32_t temp;
00511   uint32_t tickstart = 0U;
00512
00513   if(HAL_DMA_STATE_BUSY != hdma->State)
00514   {
00515     /* no transfer ongoing */
00516     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
00517     __HAL_UNLOCK(hdma);
00518     return HAL_ERROR;
00519   }
00520
00521   /* Polling mode not supported in circular mode */
00522   if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
00523   {
00524     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
00525     return HAL_ERROR;
00526   }
00527
00528   /* Get the level transfer complete flag */
00529   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
00530   {
00531     /* Transfer Complete flag */
00532     temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
00533   }
00534   else
00535   {
00536     /* Half Transfer Complete flag */
00537     temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
00538   }
00539
00540   /* Get tick */
00541   tickstart = HAL_GetTick();
00542
00543   while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
00544   {
00545     if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
00546     {
00547       /* When a DMA transfer error occurs */
00548       /* A hardware clear of its EN bits is performed */
00549       /* Clear all flags */
00550       hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
00551
00552       /* Update error code */
00553       SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
00554
00555       /* Change the DMA state */
00556       hdma->State= HAL_DMA_STATE_READY;
00557
00558       /* Process Unlocked */
00559       __HAL_UNLOCK(hdma);
00560
00561       return HAL_ERROR;
00562     }
00563     /* Check for the Timeout */
00564     if(Timeout != HAL_MAX_DELAY)
00565     {
00566       if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
00567       {
00568         /* Update error code */
00569         SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
00570
00571         /* Change the DMA state */
00572         hdma->State = HAL_DMA_STATE_READY;
00573
00574         /* Process Unlocked */
00575         __HAL_UNLOCK(hdma);
00576
00577         return HAL_ERROR;
00578       }
00579     }
00580   }
00581
00582   if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
00583   {
00584     /* Clear the transfer complete flag */
00585     __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
00586
00587     /* The selected Channelx EN bit is cleared (DMA is disabled and
00588     all transfers are complete) */
00589     hdma->State = HAL_DMA_STATE_READY;
00590   }
00591   else
00592   {
00593     /* Clear the half transfer complete flag */
00594     __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
00595   }
00596
00597   /* Process unlocked */
00598   __HAL_UNLOCK(hdma);
00599
00600   return HAL_OK;
00601 }
00602
00603 /**
00604   * @brief  Handles DMA interrupt request.
00605   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00606   *               the configuration information for the specified DMA Channel.
00607   * @retval None
00608   */
00609 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
00610 {
00611   uint32_t flag_it = hdma->DmaBaseAddress->ISR;
00612   uint32_t source_it = hdma->Instance->CCR;
00613
00614   /* Half Transfer Complete Interrupt management ******************************/
00615   if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
00616   {
00617     /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
00618     if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
00619     {
00620       /* Disable the half transfer interrupt */
00621       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
00622     }
00623     /* Clear the half transfer complete flag */
00624     __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
00625
00626     /* DMA peripheral state is not updated in Half Transfer */
00627     /* but in Transfer Complete case */
00628
00629     if(hdma->XferHalfCpltCallback != NULL)
00630     {
00631       /* Half transfer callback */
00632       hdma->XferHalfCpltCallback(hdma);
00633     }
00634   }
00635
00636   /* Transfer Complete Interrupt management ***********************************/
00637   else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
00638   {
00639     if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
00640     {
00641       /* Disable the transfer complete and error interrupt */
00642       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
00643
00644       /* Change the DMA state */
00645       hdma->State = HAL_DMA_STATE_READY;
00646     }
00647     /* Clear the transfer complete flag */
00648       __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
00649
00650     /* Process Unlocked */
00651     __HAL_UNLOCK(hdma);
00652
00653     if(hdma->XferCpltCallback != NULL)
00654     {
00655       /* Transfer complete callback */
00656       hdma->XferCpltCallback(hdma);
00657     }
00658   }
00659
00660   /* Transfer Error Interrupt management **************************************/
00661   else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
00662   {
00663     /* When a DMA transfer error occurs */
00664     /* A hardware clear of its EN bits is performed */
00665     /* Disable ALL DMA IT */
00666     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
00667
00668     /* Clear all flags */
00669     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
00670
00671     /* Update error code */
00672     hdma->ErrorCode = HAL_DMA_ERROR_TE;
00673
00674     /* Change the DMA state */
00675     hdma->State = HAL_DMA_STATE_READY;
00676
00677     /* Process Unlocked */
00678     __HAL_UNLOCK(hdma);
00679
00680     if (hdma->XferErrorCallback != NULL)
00681     {
00682       /* Transfer error callback */
00683       hdma->XferErrorCallback(hdma);
00684     }
00685   }
00686   return;
00687 }
00688
00689 /**
00690   * @brief Register callbacks
00691   * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
00692   *              the configuration information for the specified DMA Channel.
00693   * @param CallbackID: User Callback identifer
00694   *                    a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00695   * @param pCallback: pointer to private callbacsk function which has pointer to
00696   *                   a DMA_HandleTypeDef structure as parameter.
00697   * @retval HAL status
00698   */
00699 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
00700 {
00701   HAL_StatusTypeDef status = HAL_OK;
00702
00703   /* Process locked */
00704   __HAL_LOCK(hdma);
00705
00706   if(HAL_DMA_STATE_READY == hdma->State)
00707   {
00708     switch (CallbackID)
00709     {
00710     case  HAL_DMA_XFER_CPLT_CB_ID:
00711       hdma->XferCpltCallback = pCallback;
00712       break;
00713
00714     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00715       hdma->XferHalfCpltCallback = pCallback;
00716       break;
00717
00718     case  HAL_DMA_XFER_ERROR_CB_ID:
00719       hdma->XferErrorCallback = pCallback;
00720       break;
00721
00722     case  HAL_DMA_XFER_ABORT_CB_ID:
00723       hdma->XferAbortCallback = pCallback;
00724       break;
00725
00726     default:
00727       status = HAL_ERROR;
00728       break;
00729     }
00730   }
00731   else
00732   {
00733     status = HAL_ERROR;
00734   }
00735
00736   /* Release Lock */
00737   __HAL_UNLOCK(hdma);
00738
00739   return status;
00740 }
00741
00742 /**
00743   * @brief UnRegister callbacks
00744   * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
00745   *              the configuration information for the specified DMA Channel.
00746   * @param CallbackID: User Callback identifer
00747   *                    a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
00748   * @retval HAL status
00749   */
00750 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
00751 {
00752   HAL_StatusTypeDef status = HAL_OK;
00753
00754   /* Process locked */
00755   __HAL_LOCK(hdma);
00756
00757   if(HAL_DMA_STATE_READY == hdma->State)
00758   {
00759     switch (CallbackID)
00760     {
00761     case  HAL_DMA_XFER_CPLT_CB_ID:
00762       hdma->XferCpltCallback = NULL;
00763       break;
00764
00765     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
00766       hdma->XferHalfCpltCallback = NULL;
00767       break;
00768
00769     case  HAL_DMA_XFER_ERROR_CB_ID:
00770       hdma->XferErrorCallback = NULL;
00771       break;
00772
00773     case  HAL_DMA_XFER_ABORT_CB_ID:
00774       hdma->XferAbortCallback = NULL;
00775       break;
00776
00777     case   HAL_DMA_XFER_ALL_CB_ID:
00778       hdma->XferCpltCallback = NULL;
00779       hdma->XferHalfCpltCallback = NULL;
00780       hdma->XferErrorCallback = NULL;
00781       hdma->XferAbortCallback = NULL;
00782       break;
00783
00784     default:
00785       status = HAL_ERROR;
00786       break;
00787     }
00788   }
00789   else
00790   {
00791     status = HAL_ERROR;
00792   }
00793
00794   /* Release Lock */
00795   __HAL_UNLOCK(hdma);
00796
00797   return status;
00798 }
00799
00800 /**
00801   * @}
00802   */
00803
00804 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
00805   *  @brief    Peripheral State and Errors functions
00806   *
00807 @verbatim
00808  ===============================================================================
00809             ##### Peripheral State and Errors functions #####
00810  ===============================================================================
00811     [..]
00812     This subsection provides functions allowing to
00813       (+) Check the DMA state
00814       (+) Get error code
00815
00816 @endverbatim
00817   * @{
00818   */
00819
00820 /**
00821   * @brief  Return the DMA hande state.
00822   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
00823   *               the configuration information for the specified DMA Channel.
00824   * @retval HAL state
00825   */
00826 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
00827 {
00828   /* Return DMA handle state */
00829   return hdma->State;
00830 }
00831
00832 /**
00833   * @brief  Return the DMA error code.
00834   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
00835   *              the configuration information for the specified DMA Channel.
00836   * @retval DMA Error Code
00837   */
00838 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
00839 {
00840   return hdma->ErrorCode;
00841 }
00842
00843 /**
00844   * @}
00845   */
00846
00847 /**
00848   * @}
00849   */
00850
00851 /** @addtogroup DMA_Private_Functions
00852   * @{
00853   */
00854
00855 /**
00856   * @brief  Sets the DMA Transfer parameter.
00857   * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
00858   *                     the configuration information for the specified DMA Channel.
00859   * @param  SrcAddress: The source memory Buffer address
00860   * @param  DstAddress: The destination memory Buffer address
00861   * @param  DataLength: The length of data to be transferred from source to destination
00862   * @retval HAL status
00863   */
00864 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
00865 {
00866   /* Clear all flags */
00867   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
00868
00869   /* Configure DMA Channel data length */
00870   hdma->Instance->CNDTR = DataLength;
00871
00872   /* Peripheral to Memory */
00873   if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
00874   {
00875     /* Configure DMA Channel destination address */
00876     hdma->Instance->CPAR = DstAddress;
00877
00878     /* Configure DMA Channel source address */
00879     hdma->Instance->CMAR = SrcAddress;
00880   }
00881   /* Memory to Peripheral */
00882   else
00883   {
00884     /* Configure DMA Channel source address */
00885     hdma->Instance->CPAR = SrcAddress;
00886
00887     /* Configure DMA Channel destination address */
00888     hdma->Instance->CMAR = DstAddress;
00889   }
00890 }
00891
00892 /**
00893   * @}
00894   */
00895
00896 #endif /* HAL_DMA_MODULE_ENABLED */
00897 /**
00898   * @}
00899   */
00900
00901 /**
00902   * @}
00903   */
00904
00905 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dma.h Source File

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stm32f1xx_hal_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of DMA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_DMA_H
00040 #define __STM32F1xx_HAL_DMA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup DMA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup DMA_Exported_Types DMA Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  DMA Configuration Structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
00069                                            from memory to memory or from peripheral to memory.
00070                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
00071
00072   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
00073                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
00074
00075   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
00076                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
00077
00078   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
00079                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
00080
00081   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
00082                                            This parameter can be a value of @ref DMA_Memory_data_size */
00083
00084   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
00085                                            This parameter can be a value of @ref DMA_mode
00086                                            @note The circular buffer mode cannot be used if the memory-to-memory
00087                                                  data transfer is configured on the selected Channel */
00088
00089   uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
00090                                            This parameter can be a value of @ref DMA_Priority_level */
00091 } DMA_InitTypeDef;
00092
00093 /**
00094   * @brief  HAL DMA State structures definition
00095   */
00096 typedef enum
00097 {
00098   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
00099   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
00100   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
00101   HAL_DMA_STATE_TIMEOUT           = 0x03U   /*!< DMA timeout state                      */
00102 }HAL_DMA_StateTypeDef;
00103
00104 /**
00105   * @brief  HAL DMA Error Code structure definition
00106   */
00107 typedef enum
00108 {
00109   HAL_DMA_FULL_TRANSFER           = 0x00U,    /*!< Full transfer     */
00110   HAL_DMA_HALF_TRANSFER           = 0x01U     /*!< Half Transfer     */
00111 }HAL_DMA_LevelCompleteTypeDef;
00112
00113 /**
00114   * @brief  HAL DMA Callback ID structure definition
00115   */
00116 typedef enum
00117 {
00118   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
00119   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
00120   HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
00121   HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
00122   HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */
00123
00124 }HAL_DMA_CallbackIDTypeDef;
00125
00126 /**
00127   * @brief  DMA handle Structure definition
00128   */
00129 typedef struct __DMA_HandleTypeDef
00130 {
00131   DMA_Channel_TypeDef   *Instance;                       /*!< Register base address                  */
00132
00133   DMA_InitTypeDef       Init;                            /*!< DMA communication parameters           */
00134
00135   HAL_LockTypeDef       Lock;                            /*!< DMA locking object                     */
00136
00137   HAL_DMA_StateTypeDef  State;                           /*!< DMA transfer state                     */
00138
00139   void                  *Parent;                                                      /*!< Parent object state                    */
00140
00141   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
00142
00143   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
00144
00145   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
00146
00147   void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer abort callback            */
00148
00149   __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
00150
00151   DMA_TypeDef            *DmaBaseAddress;                                             /*!< DMA Channel Base Address               */
00152
00153   uint32_t               ChannelIndex;                                                /*!< DMA Channel Index                      */
00154
00155 } DMA_HandleTypeDef;
00156 /**
00157   * @}
00158   */
00159
00160 /* Exported constants --------------------------------------------------------*/
00161
00162 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00163   * @{
00164   */
00165
00166 /** @defgroup DMA_Error_Code DMA Error Code
00167   * @{
00168   */
00169 #define HAL_DMA_ERROR_NONE                     0x00000000U    /*!< No error             */
00170 #define HAL_DMA_ERROR_TE                       0x00000001U    /*!< Transfer error       */
00171 #define HAL_DMA_ERROR_NO_XFER                  0x00000004U    /*!< no ongoing transfer  */
00172 #define HAL_DMA_ERROR_TIMEOUT                  0x00000020U    /*!< Timeout error        */
00173 #define HAL_DMA_ERROR_NOT_SUPPORTED            0x00000100U    /*!< Not supported mode                    */
00174 /**
00175   * @}
00176   */
00177
00178 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00179   * @{
00180   */
00181 #define DMA_PERIPH_TO_MEMORY         0x00000000U                 /*!< Peripheral to memory direction */
00182 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
00183 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
00184
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00190   * @{
00191   */
00192 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
00193 #define DMA_PINC_DISABLE       0x00000000U               /*!< Peripheral increment mode Disable */
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00199   * @{
00200   */
00201 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
00202 #define DMA_MINC_DISABLE        0x00000000U               /*!< Memory increment mode Disable */
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00208   * @{
00209   */
00210 #define DMA_PDATAALIGN_BYTE          0x00000000U                  /*!< Peripheral data alignment: Byte     */
00211 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
00212 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup DMA_Memory_data_size DMA Memory data size
00218   * @{
00219   */
00220 #define DMA_MDATAALIGN_BYTE          0x00000000U                  /*!< Memory data alignment: Byte     */
00221 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
00222 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment: Word     */
00223 /**
00224   * @}
00225   */
00226
00227 /** @defgroup DMA_mode DMA mode
00228   * @{
00229   */
00230 #define DMA_NORMAL         0x00000000U                  /*!< Normal mode                  */
00231 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup DMA_Priority_level DMA Priority level
00237   * @{
00238   */
00239 #define DMA_PRIORITY_LOW             0x00000000U               /*!< Priority level : Low       */
00240 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
00241 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
00242 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
00243 /**
00244   * @}
00245   */
00246
00247
00248 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00249   * @{
00250   */
00251 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
00252 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
00253 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup DMA_flag_definitions DMA flag definitions
00259   * @{
00260   */
00261 #define DMA_FLAG_GL1                      0x00000001U
00262 #define DMA_FLAG_TC1                      0x00000002U
00263 #define DMA_FLAG_HT1                      0x00000004U
00264 #define DMA_FLAG_TE1                      0x00000008U
00265 #define DMA_FLAG_GL2                      0x00000010U
00266 #define DMA_FLAG_TC2                      0x00000020U
00267 #define DMA_FLAG_HT2                      0x00000040U
00268 #define DMA_FLAG_TE2                      0x00000080U
00269 #define DMA_FLAG_GL3                      0x00000100U
00270 #define DMA_FLAG_TC3                      0x00000200U
00271 #define DMA_FLAG_HT3                      0x00000400U
00272 #define DMA_FLAG_TE3                      0x00000800U
00273 #define DMA_FLAG_GL4                      0x00001000U
00274 #define DMA_FLAG_TC4                      0x00002000U
00275 #define DMA_FLAG_HT4                      0x00004000U
00276 #define DMA_FLAG_TE4                      0x00008000U
00277 #define DMA_FLAG_GL5                      0x00010000U
00278 #define DMA_FLAG_TC5                      0x00020000U
00279 #define DMA_FLAG_HT5                      0x00040000U
00280 #define DMA_FLAG_TE5                      0x00080000U
00281 #define DMA_FLAG_GL6                      0x00100000U
00282 #define DMA_FLAG_TC6                      0x00200000U
00283 #define DMA_FLAG_HT6                      0x00400000U
00284 #define DMA_FLAG_TE6                      0x00800000U
00285 #define DMA_FLAG_GL7                      0x01000000U
00286 #define DMA_FLAG_TC7                      0x02000000U
00287 #define DMA_FLAG_HT7                      0x04000000U
00288 #define DMA_FLAG_TE7                      0x08000000U
00289 /**
00290   * @}
00291   */
00292
00293 /**
00294   * @}
00295   */
00296
00297
00298 /* Exported macros -----------------------------------------------------------*/
00299 /** @defgroup DMA_Exported_Macros DMA Exported Macros
00300   * @{
00301   */
00302
00303 /** @brief  Reset DMA handle state.
00304   * @param  __HANDLE__: DMA handle
00305   * @retval None
00306   */
00307 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00308
00309 /**
00310   * @brief  Enable the specified DMA Channel.
00311   * @param  __HANDLE__: DMA handle
00312   * @retval None
00313   */
00314 #define __HAL_DMA_ENABLE(__HANDLE__)        (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
00315
00316 /**
00317   * @brief  Disable the specified DMA Channel.
00318   * @param  __HANDLE__: DMA handle
00319   * @retval None
00320   */
00321 #define __HAL_DMA_DISABLE(__HANDLE__)       (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
00322
00323
00324 /* Interrupt & Flag management */
00325
00326 /**
00327   * @brief  Enables the specified DMA Channel interrupts.
00328   * @param  __HANDLE__: DMA handle
00329   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00330   *          This parameter can be any combination of the following values:
00331   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00332   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00333   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00334   * @retval None
00335   */
00336 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
00337
00338 /**
00339   * @brief  Disable the specified DMA Channel interrupts.
00340   * @param  __HANDLE__: DMA handle
00341   * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00342   *          This parameter can be any combination of the following values:
00343   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00344   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00345   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00346   * @retval None
00347   */
00348 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
00349
00350 /**
00351   * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
00352   * @param  __HANDLE__: DMA handle
00353   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
00354   *          This parameter can be one of the following values:
00355   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00356   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00357   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00358   * @retval The state of DMA_IT (SET or RESET).
00359   */
00360 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00361
00362 /**
00363   * @brief  Return the number of remaining data units in the current DMA Channel transfer.
00364   * @param  __HANDLE__: DMA handle
00365   * @retval The number of remaining data units in the current DMA Channel transfer.
00366   */
00367 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
00368
00369 /**
00370   * @}
00371   */
00372
00373 /* Include DMA HAL Extension module */
00374 #include "stm32f1xx_hal_dma_ex.h"
00375
00376 /* Exported functions --------------------------------------------------------*/
00377 /** @addtogroup DMA_Exported_Functions
00378   * @{
00379   */
00380
00381 /** @addtogroup DMA_Exported_Functions_Group1
00382   * @{
00383   */
00384 /* Initialization and de-initialization functions *****************************/
00385 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00386 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
00387 /**
00388   * @}
00389   */
00390
00391 /** @addtogroup DMA_Exported_Functions_Group2
00392   * @{
00393   */
00394 /* IO operation functions *****************************************************/
00395 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00396 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00397 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
00398 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
00399 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
00400 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
00401 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
00402 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
00403
00404 /**
00405   * @}
00406   */
00407
00408 /** @addtogroup DMA_Exported_Functions_Group3
00409   * @{
00410   */
00411 /* Peripheral State and Error functions ***************************************/
00412 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
00413 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
00414 /**
00415   * @}
00416   */
00417
00418 /**
00419   * @}
00420   */
00421
00422 /* Private macros ------------------------------------------------------------*/
00423 /** @defgroup DMA_Private_Macros DMA Private Macros
00424   * @{
00425   */
00426
00427 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
00428                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
00429                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
00430
00431 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
00432
00433 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
00434                                             ((STATE) == DMA_PINC_DISABLE))
00435
00436 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
00437                                         ((STATE) == DMA_MINC_DISABLE))
00438
00439 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
00440                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
00441                                            ((SIZE) == DMA_PDATAALIGN_WORD))
00442
00443 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
00444                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
00445                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
00446
00447 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
00448                            ((MODE) == DMA_CIRCULAR))
00449
00450 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
00451                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
00452                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
00453                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
00454
00455 /**
00456   * @}
00457   */
00458
00459 /* Private functions ---------------------------------------------------------*/
00460
00461 /**
00462   * @}
00463   */
00464
00465 /**
00466   * @}
00467   */
00468
00469 #ifdef __cplusplus
00470 }
00471 #endif
00472
00473 #endif /* __STM32F1xx_HAL_DMA_H */
00474
00475 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_dma_ex.h Source File

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stm32f1xx_hal_dma_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_dma_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of DMA HAL extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_DMA_EX_H
00040 #define __STM32F1xx_HAL_DMA_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup DMAEx DMAEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /* Exported constants --------------------------------------------------------*/
00059 /* Exported macro ------------------------------------------------------------*/
00060 /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
00061   * @{
00062   */
00063 /* Interrupt & Flag management */
00064 #if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
00065     defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
00066 /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
00067   * @{
00068   */
00069
00070 /**
00071   * @brief  Returns the current DMA Channel transfer complete flag.
00072   * @param  __HANDLE__: DMA handle
00073   * @retval The specified transfer complete flag index.
00074   */
00075 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00076 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00077  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00078  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00079  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00080  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00081  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00082  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
00083  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
00084  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
00085  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
00086  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
00087    DMA_FLAG_TC5)
00088
00089 /**
00090   * @brief  Returns the current DMA Channel half transfer complete flag.
00091   * @param  __HANDLE__: DMA handle
00092   * @retval The specified half transfer complete flag index.
00093   */
00094 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00095 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00096  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00097  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00098  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00099  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00100  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00101  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
00102  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
00103  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
00104  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
00105  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
00106    DMA_FLAG_HT5)
00107
00108 /**
00109   * @brief  Returns the current DMA Channel transfer error flag.
00110   * @param  __HANDLE__: DMA handle
00111   * @retval The specified transfer error flag index.
00112   */
00113 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00114 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00115  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00116  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00117  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00118  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00119  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00120  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
00121  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
00122  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
00123  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
00124  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
00125    DMA_FLAG_TE5)
00126
00127 /**
00128   * @brief  Return the current DMA Channel Global interrupt flag.
00129   * @param  __HANDLE__: DMA handle
00130   * @retval The specified transfer error flag index.
00131   */
00132 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00133 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
00134  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
00135  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
00136  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
00137  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
00138  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
00139  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
00140  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
00141  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
00142  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
00143  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
00144    DMA_FLAG_GL5)
00145
00146 /**
00147   * @brief  Get the DMA Channel pending flags.
00148   * @param  __HANDLE__: DMA handle
00149   * @param  __FLAG__: Get the specified flag.
00150   *          This parameter can be any combination of the following values:
00151   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00152   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00153   *            @arg DMA_FLAG_TEx:  Transfer error flag
00154   *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
00155   * @retval The state of FLAG (SET or RESET).
00156   */
00157 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
00158 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
00159   (DMA1->ISR & (__FLAG__)))
00160
00161 /**
00162   * @brief  Clears the DMA Channel pending flags.
00163   * @param  __HANDLE__: DMA handle
00164   * @param  __FLAG__: specifies the flag to clear.
00165   *          This parameter can be any combination of the following values:
00166   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00167   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00168   *            @arg DMA_FLAG_TEx:  Transfer error flag
00169   *         Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
00170   * @retval None
00171   */
00172 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
00173 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
00174   (DMA1->IFCR = (__FLAG__)))
00175
00176 /**
00177   * @}
00178   */
00179
00180 #else
00181 /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
00182   * @{
00183   */
00184
00185 /**
00186   * @brief  Returns the current DMA Channel transfer complete flag.
00187   * @param  __HANDLE__: DMA handle
00188   * @retval The specified transfer complete flag index.
00189   */
00190 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00191 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00192  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00193  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00194  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00195  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00196  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00197    DMA_FLAG_TC7)
00198
00199 /**
00200   * @brief  Return the current DMA Channel half transfer complete flag.
00201   * @param  __HANDLE__: DMA handle
00202   * @retval The specified half transfer complete flag index.
00203   */
00204 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00205 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00206  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00207  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00208  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00209  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00210  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00211    DMA_FLAG_HT7)
00212
00213 /**
00214   * @brief  Return the current DMA Channel transfer error flag.
00215   * @param  __HANDLE__: DMA handle
00216   * @retval The specified transfer error flag index.
00217   */
00218 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00219 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00220  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00221  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00222  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00223  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00224  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00225    DMA_FLAG_TE7)
00226
00227 /**
00228   * @brief  Return the current DMA Channel Global interrupt flag.
00229   * @param  __HANDLE__: DMA handle
00230   * @retval The specified transfer error flag index.
00231   */
00232 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00233 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
00234  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
00235  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
00236  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
00237  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
00238  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
00239    DMA_FLAG_GL7)
00240
00241 /**
00242   * @brief  Get the DMA Channel pending flags.
00243   * @param  __HANDLE__: DMA handle
00244   * @param  __FLAG__: Get the specified flag.
00245   *          This parameter can be any combination of the following values:
00246   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00247   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00248   *            @arg DMA_FLAG_TEx:  Transfer error flag
00249   *            @arg DMA_FLAG_GLx:  Global interrupt flag
00250   *         Where x can be 1_7 to select the DMA Channel flag.
00251   * @retval The state of FLAG (SET or RESET).
00252   */
00253
00254 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
00255
00256 /**
00257   * @brief  Clear the DMA Channel pending flags.
00258   * @param  __HANDLE__: DMA handle
00259   * @param  __FLAG__: specifies the flag to clear.
00260   *          This parameter can be any combination of the following values:
00261   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00262   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00263   *            @arg DMA_FLAG_TEx:  Transfer error flag
00264   *            @arg DMA_FLAG_GLx:  Global interrupt flag
00265   *         Where x can be 1_7 to select the DMA Channel flag.
00266   * @retval None
00267   */
00268 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
00269
00270 /**
00271   * @}
00272   */
00273
00274 #endif
00275
00276 /**
00277   * @}
00278   */
00279
00280 /**
00281   * @}
00282   */
00283
00284 /**
00285   * @}
00286   */
00287
00288 #ifdef __cplusplus
00289 }
00290 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
00291        /* STM32F103xG || STM32F105xC || STM32F107xC */
00292
00293 #endif /* __STM32F1xx_HAL_DMA_H */
00294
00295 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_eth.c Source File

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stm32f1xx_hal_eth.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_eth.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   ETH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Ethernet (ETH) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       (#)Declare a ETH_HandleTypeDef handle structure, for example:
00021          ETH_HandleTypeDef  heth;
00022
00023       (#)Fill parameters of Init structure in heth handle
00024
00025       (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
00026
00027       (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
00028           (##) Enable the Ethernet interface clock using
00029                (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
00030                (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
00031                (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
00032
00033           (##) Initialize the related GPIO clocks
00034           (##) Configure Ethernet pin-out
00035           (##) Configure Ethernet NVIC interrupt (IT mode)
00036
00037       (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
00038           (##) HAL_ETH_DMATxDescListInit(); for Transmission process
00039           (##) HAL_ETH_DMARxDescListInit(); for Reception process
00040
00041       (#)Enable MAC and DMA transmission and reception:
00042           (##) HAL_ETH_Start();
00043
00044       (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
00045          the frame to MAC TX FIFO:
00046          (##) HAL_ETH_TransmitFrame();
00047
00048       (#)Poll for a received frame in ETH RX DMA Descriptors and get received
00049          frame parameters
00050          (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
00051
00052       (#) Get a received frame when an ETH RX interrupt occurs:
00053          (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
00054
00055       (#) Communicate with external PHY device:
00056          (##) Read a specific register from the PHY
00057               HAL_ETH_ReadPHYRegister();
00058          (##) Write data to a specific RHY register:
00059               HAL_ETH_WritePHYRegister();
00060
00061       (#) Configure the Ethernet MAC after ETH peripheral initialization
00062           HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
00063
00064       (#) Configure the Ethernet DMA after ETH peripheral initialization
00065           HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
00066
00067       -@- The PTP protocol and the DMA descriptors ring mode are not supported
00068           in this driver
00069
00070   @endverbatim
00071   ******************************************************************************
00072   * @attention
00073   *
00074   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00075   *
00076   * Redistribution and use in source and binary forms, with or without modification,
00077   * are permitted provided that the following conditions are met:
00078   *   1. Redistributions of source code must retain the above copyright notice,
00079   *      this list of conditions and the following disclaimer.
00080   *   2. Redistributions in binary form must reproduce the above copyright notice,
00081   *      this list of conditions and the following disclaimer in the documentation
00082   *      and/or other materials provided with the distribution.
00083   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00084   *      may be used to endorse or promote products derived from this software
00085   *      without specific prior written permission.
00086   *
00087   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00088   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00089   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00090   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00091   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00092   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00093   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00094   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00095   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00096   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00097   *
00098   ******************************************************************************
00099   */
00100
00101 /* Includes ------------------------------------------------------------------*/
00102 #include "stm32f1xx_hal.h"
00103
00104 /** @addtogroup STM32F1xx_HAL_Driver
00105   * @{
00106   */
00107 #if defined (STM32F107xC)
00108
00109 /** @defgroup ETH ETH
00110   * @brief ETH HAL module driver
00111   * @{
00112   */
00113
00114 #ifdef HAL_ETH_MODULE_ENABLED
00115
00116 /* Private typedef -----------------------------------------------------------*/
00117 /* Private define ------------------------------------------------------------*/
00118 /** @defgroup ETH_Private_Constants ETH Private Constants
00119   * @{
00120   */
00121 #define ETH_TIMEOUT_SWRESET               500U
00122 #define ETH_TIMEOUT_LINKED_STATE          5000U
00123 #define ETH_TIMEOUT_AUTONEGO_COMPLETED    5000U
00124
00125 /**
00126   * @}
00127   */
00128 /* Private macro -------------------------------------------------------------*/
00129 /* Private variables ---------------------------------------------------------*/
00130 /* Private function prototypes -----------------------------------------------*/
00131 /** @defgroup ETH_Private_Functions ETH Private Functions
00132   * @{
00133   */
00134 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
00135 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
00136 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
00137 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
00138 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
00139 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
00140 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
00141 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
00142 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
00143 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
00144 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
00145 static void ETH_Delay(uint32_t mdelay);
00146
00147 /**
00148   * @}
00149   */
00150 /* Private functions ---------------------------------------------------------*/
00151
00152 /** @defgroup ETH_Exported_Functions ETH Exported Functions
00153   * @{
00154   */
00155
00156 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
00157   *  @brief   Initialization and Configuration functions
00158   *
00159   @verbatim
00160   ===============================================================================
00161             ##### Initialization and de-initialization functions #####
00162   ===============================================================================
00163   [..]  This section provides functions allowing to:
00164       (+) Initialize and configure the Ethernet peripheral
00165       (+) De-initialize the Ethernet peripheral
00166
00167   @endverbatim
00168   * @{
00169   */
00170
00171 /**
00172   * @brief  Initializes the Ethernet MAC and DMA according to default
00173   *         parameters.
00174   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00175   *         the configuration information for ETHERNET module
00176   * @retval HAL status
00177   */
00178 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
00179 {
00180   uint32_t tmpreg1 = 0U, phyreg = 0U;
00181   uint32_t hclk = 60000000U;
00182   uint32_t tickstart = 0U;
00183   uint32_t err = ETH_SUCCESS;
00184
00185   /* Check the ETH peripheral state */
00186   if(heth == NULL)
00187   {
00188     return HAL_ERROR;
00189   }
00190
00191   /* Check parameters */
00192   assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
00193   assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
00194   assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
00195   assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
00196
00197   if(heth->State == HAL_ETH_STATE_RESET)
00198   {
00199     /* Allocate lock resource and initialize it */
00200     heth->Lock = HAL_UNLOCKED;
00201     /* Init the low level hardware : GPIO, CLOCK, NVIC. */
00202     HAL_ETH_MspInit(heth);
00203   }
00204
00205   /* Select MII or RMII Mode*/
00206   AFIO->MAPR &= ~(AFIO_MAPR_MII_RMII_SEL);
00207   AFIO->MAPR |= (uint32_t)heth->Init.MediaInterface;
00208
00209   /* Ethernet Software reset */
00210   /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
00211   /* After reset all the registers holds their respective reset values */
00212   (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
00213
00214   /* Get tick */
00215   tickstart = HAL_GetTick();
00216
00217   /* Wait for software reset */
00218   while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
00219   {
00220     /* Check for the Timeout */
00221     if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
00222     {
00223       heth->State= HAL_ETH_STATE_TIMEOUT;
00224
00225       /* Process Unlocked */
00226       __HAL_UNLOCK(heth);
00227
00228       /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
00229          not available, please check your external PHY or the IO configuration */
00230       return HAL_TIMEOUT;
00231     }
00232   }
00233
00234   /*-------------------------------- MAC Initialization ----------------------*/
00235   /* Get the ETHERNET MACMIIAR value */
00236   tmpreg1 = (heth->Instance)->MACMIIAR;
00237   /* Clear CSR Clock Range CR[2:0] bits */
00238   tmpreg1 &= ETH_MACMIIAR_CR_MASK;
00239
00240   /* Get hclk frequency value */
00241   hclk = HAL_RCC_GetHCLKFreq();
00242
00243   /* Set CR bits depending on hclk value */
00244   if((hclk >= 20000000U)&&(hclk < 35000000U))
00245   {
00246     /* CSR Clock Range between 20-35 MHz */
00247     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV16;
00248   }
00249   else if((hclk >= 35000000U)&&(hclk < 60000000U))
00250   {
00251     /* CSR Clock Range between 35-60 MHz */
00252     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV26;
00253   }
00254   else
00255   {
00256     /* CSR Clock Range between 60-72 MHz */
00257     tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV42;
00258   }
00259
00260   /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
00261   (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
00262
00263   /*-------------------- PHY initialization and configuration ----------------*/
00264   /* Put the PHY in reset mode */
00265   if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
00266   {
00267     /* In case of write timeout */
00268     err = ETH_ERROR;
00269
00270     /* Config MAC and DMA */
00271     ETH_MACDMAConfig(heth, err);
00272
00273     /* Set the ETH peripheral state to READY */
00274     heth->State = HAL_ETH_STATE_READY;
00275
00276     /* Return HAL_ERROR */
00277     return HAL_ERROR;
00278   }
00279
00280   /* Delay to assure PHY reset */
00281   HAL_Delay(PHY_RESET_DELAY);
00282
00283   if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
00284   {
00285     /* Get tick */
00286     tickstart = HAL_GetTick();
00287
00288     /* We wait for linked status */
00289     do
00290     {
00291       HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
00292
00293       /* Check for the Timeout */
00294       if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
00295       {
00296         /* In case of write timeout */
00297         err = ETH_ERROR;
00298
00299         /* Config MAC and DMA */
00300         ETH_MACDMAConfig(heth, err);
00301
00302         heth->State= HAL_ETH_STATE_READY;
00303
00304         /* Process Unlocked */
00305         __HAL_UNLOCK(heth);
00306
00307         return HAL_TIMEOUT;
00308       }
00309     } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
00310
00311
00312     /* Enable Auto-Negotiation */
00313     if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
00314     {
00315       /* In case of write timeout */
00316       err = ETH_ERROR;
00317
00318       /* Config MAC and DMA */
00319       ETH_MACDMAConfig(heth, err);
00320
00321       /* Set the ETH peripheral state to READY */
00322       heth->State = HAL_ETH_STATE_READY;
00323
00324       /* Return HAL_ERROR */
00325       return HAL_ERROR;
00326     }
00327
00328     /* Get tick */
00329     tickstart = HAL_GetTick();
00330
00331     /* Wait until the auto-negotiation will be completed */
00332     do
00333     {
00334       HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
00335
00336       /* Check for the Timeout */
00337       if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
00338       {
00339         /* In case of write timeout */
00340         err = ETH_ERROR;
00341
00342         /* Config MAC and DMA */
00343         ETH_MACDMAConfig(heth, err);
00344
00345         heth->State= HAL_ETH_STATE_READY;
00346
00347         /* Process Unlocked */
00348         __HAL_UNLOCK(heth);
00349
00350         return HAL_TIMEOUT;
00351       }
00352
00353     } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
00354
00355     /* Read the result of the auto-negotiation */
00356     if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
00357     {
00358       /* In case of write timeout */
00359       err = ETH_ERROR;
00360
00361       /* Config MAC and DMA */
00362       ETH_MACDMAConfig(heth, err);
00363
00364       /* Set the ETH peripheral state to READY */
00365       heth->State = HAL_ETH_STATE_READY;
00366
00367       /* Return HAL_ERROR */
00368       return HAL_ERROR;
00369     }
00370
00371     /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
00372     if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
00373     {
00374       /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
00375       (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
00376     }
00377     else
00378     {
00379       /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
00380       (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
00381     }
00382     /* Configure the MAC with the speed fixed by the auto-negotiation process */
00383     if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
00384     {
00385       /* Set Ethernet speed to 10M following the auto-negotiation */
00386       (heth->Init).Speed = ETH_SPEED_10M;
00387     }
00388     else
00389     {
00390       /* Set Ethernet speed to 100M following the auto-negotiation */
00391       (heth->Init).Speed = ETH_SPEED_100M;
00392     }
00393   }
00394   else /* AutoNegotiation Disable */
00395   {
00396     /* Check parameters */
00397     assert_param(IS_ETH_SPEED(heth->Init.Speed));
00398     assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
00399
00400     /* Set MAC Speed and Duplex Mode */
00401     if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
00402                                                 (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
00403     {
00404       /* In case of write timeout */
00405       err = ETH_ERROR;
00406
00407       /* Config MAC and DMA */
00408       ETH_MACDMAConfig(heth, err);
00409
00410       /* Set the ETH peripheral state to READY */
00411       heth->State = HAL_ETH_STATE_READY;
00412
00413       /* Return HAL_ERROR */
00414       return HAL_ERROR;
00415     }
00416
00417     /* Delay to assure PHY configuration */
00418     HAL_Delay(PHY_CONFIG_DELAY);
00419   }
00420
00421   /* Config MAC and DMA */
00422   ETH_MACDMAConfig(heth, err);
00423
00424   /* Set ETH HAL State to Ready */
00425   heth->State= HAL_ETH_STATE_READY;
00426
00427   /* Return function status */
00428   return HAL_OK;
00429 }
00430
00431 /**
00432   * @brief  De-Initializes the ETH peripheral.
00433   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00434   *         the configuration information for ETHERNET module
00435   * @retval HAL status
00436   */
00437 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
00438 {
00439   /* Set the ETH peripheral state to BUSY */
00440   heth->State = HAL_ETH_STATE_BUSY;
00441
00442   /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
00443   HAL_ETH_MspDeInit(heth);
00444
00445   /* Set ETH HAL state to Disabled */
00446   heth->State= HAL_ETH_STATE_RESET;
00447
00448   /* Release Lock */
00449   __HAL_UNLOCK(heth);
00450
00451   /* Return function status */
00452   return HAL_OK;
00453 }
00454
00455 /**
00456   * @brief  Initializes the DMA Tx descriptors in chain mode.
00457   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00458   *         the configuration information for ETHERNET module
00459   * @param  DMATxDescTab: Pointer to the first Tx desc list
00460   * @param  TxBuff: Pointer to the first TxBuffer list
00461   * @param  TxBuffCount: Number of the used Tx desc in the list
00462   * @retval HAL status
00463   */
00464 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
00465 {
00466   uint32_t i = 0U;
00467   ETH_DMADescTypeDef *dmatxdesc;
00468
00469   /* Process Locked */
00470   __HAL_LOCK(heth);
00471
00472   /* Set the ETH peripheral state to BUSY */
00473   heth->State = HAL_ETH_STATE_BUSY;
00474
00475   /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
00476   heth->TxDesc = DMATxDescTab;
00477
00478   /* Fill each DMATxDesc descriptor with the right values */
00479   for(i=0U; i < TxBuffCount; i++)
00480   {
00481     /* Get the pointer on the ith member of the Tx Desc list */
00482     dmatxdesc = DMATxDescTab + i;
00483
00484     /* Set Second Address Chained bit */
00485     dmatxdesc->Status = ETH_DMATXDESC_TCH;
00486
00487     /* Set Buffer1 address pointer */
00488     dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
00489
00490     if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
00491     {
00492       /* Set the DMA Tx descriptors checksum insertion */
00493       dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
00494     }
00495
00496     /* Initialize the next descriptor with the Next Descriptor Polling Enable */
00497     if(i < (TxBuffCount-1U))
00498     {
00499       /* Set next descriptor address register with next descriptor base address */
00500       dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
00501     }
00502     else
00503     {
00504       /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
00505       dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
00506     }
00507   }
00508
00509   /* Set Transmit Descriptor List Address Register */
00510   (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
00511
00512   /* Set ETH HAL State to Ready */
00513   heth->State= HAL_ETH_STATE_READY;
00514
00515   /* Process Unlocked */
00516   __HAL_UNLOCK(heth);
00517
00518   /* Return function status */
00519   return HAL_OK;
00520 }
00521
00522 /**
00523   * @brief  Initializes the DMA Rx descriptors in chain mode.
00524   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00525   *         the configuration information for ETHERNET module
00526   * @param  DMARxDescTab: Pointer to the first Rx desc list
00527   * @param  RxBuff: Pointer to the first RxBuffer list
00528   * @param  RxBuffCount: Number of the used Rx desc in the list
00529   * @retval HAL status
00530   */
00531 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
00532 {
00533   uint32_t i = 0U;
00534   ETH_DMADescTypeDef *DMARxDesc;
00535
00536   /* Process Locked */
00537   __HAL_LOCK(heth);
00538
00539   /* Set the ETH peripheral state to BUSY */
00540   heth->State = HAL_ETH_STATE_BUSY;
00541
00542   /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
00543   heth->RxDesc = DMARxDescTab;
00544
00545   /* Fill each DMARxDesc descriptor with the right values */
00546   for(i=0U; i < RxBuffCount; i++)
00547   {
00548     /* Get the pointer on the ith member of the Rx Desc list */
00549     DMARxDesc = DMARxDescTab+i;
00550
00551     /* Set Own bit of the Rx descriptor Status */
00552     DMARxDesc->Status = ETH_DMARXDESC_OWN;
00553
00554     /* Set Buffer1 size and Second Address Chained bit */
00555     DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
00556
00557     /* Set Buffer1 address pointer */
00558     DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
00559
00560     if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
00561     {
00562       /* Enable Ethernet DMA Rx Descriptor interrupt */
00563       DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
00564     }
00565
00566     /* Initialize the next descriptor with the Next Descriptor Polling Enable */
00567     if(i < (RxBuffCount-1U))
00568     {
00569       /* Set next descriptor address register with next descriptor base address */
00570       DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
00571     }
00572     else
00573     {
00574       /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
00575       DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
00576     }
00577   }
00578
00579   /* Set Receive Descriptor List Address Register */
00580   (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
00581
00582   /* Set ETH HAL State to Ready */
00583   heth->State= HAL_ETH_STATE_READY;
00584
00585   /* Process Unlocked */
00586   __HAL_UNLOCK(heth);
00587
00588   /* Return function status */
00589   return HAL_OK;
00590 }
00591
00592 /**
00593   * @brief  Initializes the ETH MSP.
00594   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00595   *         the configuration information for ETHERNET module
00596   * @retval None
00597   */
00598 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
00599 {
00600   /* Prevent unused argument(s) compilation warning */
00601   UNUSED(heth);
00602   /* NOTE : This function Should not be modified, when the callback is needed,
00603   the HAL_ETH_MspInit could be implemented in the user file
00604   */
00605 }
00606
00607 /**
00608   * @brief  DeInitializes ETH MSP.
00609   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00610   *         the configuration information for ETHERNET module
00611   * @retval None
00612   */
00613 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
00614 {
00615   /* Prevent unused argument(s) compilation warning */
00616   UNUSED(heth);
00617   /* NOTE : This function Should not be modified, when the callback is needed,
00618   the HAL_ETH_MspDeInit could be implemented in the user file
00619   */
00620 }
00621
00622 /**
00623   * @}
00624   */
00625
00626 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
00627   *  @brief   Data transfers functions
00628   *
00629   @verbatim
00630   ==============================================================================
00631                           ##### IO operation functions #####
00632   ==============================================================================
00633   [..]  This section provides functions allowing to:
00634         (+) Transmit a frame
00635             HAL_ETH_TransmitFrame();
00636         (+) Receive a frame
00637             HAL_ETH_GetReceivedFrame();
00638             HAL_ETH_GetReceivedFrame_IT();
00639         (+) Read from an External PHY register
00640             HAL_ETH_ReadPHYRegister();
00641         (+) Write to an External PHY register
00642             HAL_ETH_WritePHYRegister();
00643
00644   @endverbatim
00645
00646   * @{
00647   */
00648
00649 /**
00650   * @brief  Sends an Ethernet frame.
00651   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00652   *         the configuration information for ETHERNET module
00653   * @param  FrameLength: Amount of data to be sent
00654   * @retval HAL status
00655   */
00656 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
00657 {
00658   uint32_t bufcount = 0U, size = 0U, i = 0U;
00659
00660   /* Process Locked */
00661   __HAL_LOCK(heth);
00662
00663   /* Set the ETH peripheral state to BUSY */
00664   heth->State = HAL_ETH_STATE_BUSY;
00665
00666   if (FrameLength == 0U)
00667   {
00668     /* Set ETH HAL state to READY */
00669     heth->State = HAL_ETH_STATE_READY;
00670
00671     /* Process Unlocked */
00672     __HAL_UNLOCK(heth);
00673
00674     return  HAL_ERROR;
00675   }
00676
00677   /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
00678   if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
00679   {
00680     /* OWN bit set */
00681     heth->State = HAL_ETH_STATE_BUSY_TX;
00682
00683     /* Process Unlocked */
00684     __HAL_UNLOCK(heth);
00685
00686     return HAL_ERROR;
00687   }
00688
00689   /* Get the number of needed Tx buffers for the current frame */
00690   if (FrameLength > ETH_TX_BUF_SIZE)
00691   {
00692     bufcount = FrameLength/ETH_TX_BUF_SIZE;
00693     if (FrameLength % ETH_TX_BUF_SIZE)
00694     {
00695       bufcount++;
00696     }
00697   }
00698   else
00699   {
00700     bufcount = 1U;
00701   }
00702   if (bufcount == 1U)
00703   {
00704     /* Set LAST and FIRST segment */
00705     heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
00706     /* Set frame size */
00707     heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
00708     /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
00709     heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
00710     /* Point to next descriptor */
00711     heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
00712   }
00713   else
00714   {
00715     for (i=0U; i< bufcount; i++)
00716     {
00717       /* Clear FIRST and LAST segment bits */
00718       heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
00719
00720       if (i == 0U)
00721       {
00722         /* Setting the first segment bit */
00723         heth->TxDesc->Status |= ETH_DMATXDESC_FS;
00724       }
00725
00726       /* Program size */
00727       heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
00728
00729       if (i == (bufcount-1U))
00730       {
00731         /* Setting the last segment bit */
00732         heth->TxDesc->Status |= ETH_DMATXDESC_LS;
00733         size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
00734         heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
00735       }
00736
00737       /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
00738       heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
00739       /* point to next descriptor */
00740       heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
00741     }
00742   }
00743
00744   /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
00745   if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
00746   {
00747     /* Clear TBUS ETHERNET DMA flag */
00748     (heth->Instance)->DMASR = ETH_DMASR_TBUS;
00749     /* Resume DMA transmission*/
00750     (heth->Instance)->DMATPDR = 0U;
00751   }
00752
00753   /* Set ETH HAL State to Ready */
00754   heth->State = HAL_ETH_STATE_READY;
00755
00756   /* Process Unlocked */
00757   __HAL_UNLOCK(heth);
00758
00759   /* Return function status */
00760   return HAL_OK;
00761 }
00762
00763 /**
00764   * @brief  Checks for received frames.
00765   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00766   *         the configuration information for ETHERNET module
00767   * @retval HAL status
00768   */
00769 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
00770 {
00771   uint32_t framelength = 0U;
00772
00773   /* Process Locked */
00774   __HAL_LOCK(heth);
00775
00776   /* Check the ETH state to BUSY */
00777   heth->State = HAL_ETH_STATE_BUSY;
00778
00779   /* Check if segment is not owned by DMA */
00780   /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
00781   if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
00782   {
00783     /* Check if last segment */
00784     if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
00785     {
00786       /* increment segment count */
00787       (heth->RxFrameInfos).SegCount++;
00788
00789       /* Check if last segment is first segment: one segment contains the frame */
00790       if ((heth->RxFrameInfos).SegCount == 1U)
00791       {
00792         (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
00793       }
00794
00795       heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
00796
00797       /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
00798       framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
00799       heth->RxFrameInfos.length = framelength;
00800
00801       /* Get the address of the buffer start address */
00802       heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
00803       /* point to next descriptor */
00804       heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
00805
00806       /* Set HAL State to Ready */
00807       heth->State = HAL_ETH_STATE_READY;
00808
00809       /* Process Unlocked */
00810       __HAL_UNLOCK(heth);
00811
00812       /* Return function status */
00813       return HAL_OK;
00814     }
00815     /* Check if first segment */
00816     else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
00817     {
00818       (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
00819       (heth->RxFrameInfos).LSRxDesc = NULL;
00820       (heth->RxFrameInfos).SegCount = 1U;
00821       /* Point to next descriptor */
00822       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00823     }
00824     /* Check if intermediate segment */
00825     else
00826     {
00827       (heth->RxFrameInfos).SegCount++;
00828       /* Point to next descriptor */
00829       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00830     }
00831   }
00832
00833   /* Set ETH HAL State to Ready */
00834   heth->State = HAL_ETH_STATE_READY;
00835
00836   /* Process Unlocked */
00837   __HAL_UNLOCK(heth);
00838
00839   /* Return function status */
00840   return HAL_ERROR;
00841 }
00842
00843 /**
00844   * @brief  Gets the Received frame in interrupt mode.
00845   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00846   *         the configuration information for ETHERNET module
00847   * @retval HAL status
00848   */
00849 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
00850 {
00851   uint32_t descriptorscancounter = 0U;
00852
00853   /* Process Locked */
00854   __HAL_LOCK(heth);
00855
00856   /* Set ETH HAL State to BUSY */
00857   heth->State = HAL_ETH_STATE_BUSY;
00858
00859   /* Scan descriptors owned by CPU */
00860   while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
00861   {
00862     /* Just for security */
00863     descriptorscancounter++;
00864
00865     /* Check if first segment in frame */
00866     /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
00867     if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
00868     {
00869       heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
00870       heth->RxFrameInfos.SegCount = 1U;
00871       /* Point to next descriptor */
00872       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00873     }
00874     /* Check if intermediate segment */
00875     /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
00876     else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
00877     {
00878       /* Increment segment count */
00879       (heth->RxFrameInfos.SegCount)++;
00880       /* Point to next descriptor */
00881       heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
00882     }
00883     /* Should be last segment */
00884     else
00885     {
00886       /* Last segment */
00887       heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
00888
00889       /* Increment segment count */
00890       (heth->RxFrameInfos.SegCount)++;
00891
00892       /* Check if last segment is first segment: one segment contains the frame */
00893       if ((heth->RxFrameInfos.SegCount) == 1U)
00894       {
00895         heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
00896       }
00897
00898       /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
00899       heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
00900
00901       /* Get the address of the buffer start address */
00902       heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
00903
00904       /* Point to next descriptor */
00905       heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
00906
00907       /* Set HAL State to Ready */
00908       heth->State = HAL_ETH_STATE_READY;
00909
00910       /* Process Unlocked */
00911       __HAL_UNLOCK(heth);
00912
00913       /* Return function status */
00914       return HAL_OK;
00915     }
00916   }
00917
00918   /* Set HAL State to Ready */
00919   heth->State = HAL_ETH_STATE_READY;
00920
00921   /* Process Unlocked */
00922   __HAL_UNLOCK(heth);
00923
00924   /* Return function status */
00925   return HAL_ERROR;
00926 }
00927
00928 /**
00929   * @brief  This function handles ETH interrupt request.
00930   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00931   *         the configuration information for ETHERNET module
00932   * @retval HAL status
00933   */
00934 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
00935 {
00936   /* Frame received */
00937   if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
00938   {
00939     /* Receive complete callback */
00940     HAL_ETH_RxCpltCallback(heth);
00941
00942      /* Clear the Eth DMA Rx IT pending bits */
00943     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
00944
00945     /* Set HAL State to Ready */
00946     heth->State = HAL_ETH_STATE_READY;
00947
00948     /* Process Unlocked */
00949     __HAL_UNLOCK(heth);
00950
00951   }
00952   /* Frame transmitted */
00953   else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
00954   {
00955     /* Transfer complete callback */
00956     HAL_ETH_TxCpltCallback(heth);
00957
00958     /* Clear the Eth DMA Tx IT pending bits */
00959     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
00960
00961     /* Set HAL State to Ready */
00962     heth->State = HAL_ETH_STATE_READY;
00963
00964     /* Process Unlocked */
00965     __HAL_UNLOCK(heth);
00966   }
00967
00968   /* Clear the interrupt flags */
00969   __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
00970
00971   /* ETH DMA Error */
00972   if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
00973   {
00974     /* Ethernet Error callback */
00975     HAL_ETH_ErrorCallback(heth);
00976
00977     /* Clear the interrupt flags */
00978     __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
00979
00980     /* Set HAL State to Ready */
00981     heth->State = HAL_ETH_STATE_READY;
00982
00983     /* Process Unlocked */
00984     __HAL_UNLOCK(heth);
00985   }
00986 }
00987
00988 /**
00989   * @brief  Tx Transfer completed callbacks.
00990   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
00991   *         the configuration information for ETHERNET module
00992   * @retval None
00993   */
00994 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
00995 {
00996   /* Prevent unused argument(s) compilation warning */
00997   UNUSED(heth);
00998   /* NOTE : This function Should not be modified, when the callback is needed,
00999   the HAL_ETH_TxCpltCallback could be implemented in the user file
01000   */
01001 }
01002
01003 /**
01004   * @brief  Rx Transfer completed callbacks.
01005   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01006   *         the configuration information for ETHERNET module
01007   * @retval None
01008   */
01009 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
01010 {
01011   /* Prevent unused argument(s) compilation warning */
01012   UNUSED(heth);
01013   /* NOTE : This function Should not be modified, when the callback is needed,
01014   the HAL_ETH_TxCpltCallback could be implemented in the user file
01015   */
01016 }
01017
01018 /**
01019   * @brief  Ethernet transfer error callbacks
01020   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01021   *         the configuration information for ETHERNET module
01022   * @retval None
01023   */
01024 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
01025 {
01026   /* Prevent unused argument(s) compilation warning */
01027   UNUSED(heth);
01028   /* NOTE : This function Should not be modified, when the callback is needed,
01029   the HAL_ETH_TxCpltCallback could be implemented in the user file
01030   */
01031 }
01032
01033 /**
01034   * @brief  Reads a PHY register
01035   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01036   *         the configuration information for ETHERNET module
01037   * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
01038   *                This parameter can be one of the following values:
01039   *                   PHY_BCR: Transceiver Basic Control Register,
01040   *                   PHY_BSR: Transceiver Basic Status Register.
01041   *                   More PHY register could be read depending on the used PHY
01042   * @param RegValue: PHY register value
01043   * @retval HAL status
01044   */
01045 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
01046 {
01047   uint32_t tmpreg1 = 0U;
01048   uint32_t tickstart = 0U;
01049
01050   /* Check parameters */
01051   assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
01052
01053   /* Check the ETH peripheral state */
01054   if(heth->State == HAL_ETH_STATE_BUSY_RD)
01055   {
01056     return HAL_BUSY;
01057   }
01058   /* Set ETH HAL State to BUSY_RD */
01059   heth->State = HAL_ETH_STATE_BUSY_RD;
01060
01061   /* Get the ETHERNET MACMIIAR value */
01062   tmpreg1 = heth->Instance->MACMIIAR;
01063
01064   /* Keep only the CSR Clock Range CR[2:0] bits value */
01065   tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
01066
01067   /* Prepare the MII address register value */
01068   tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address   */
01069   tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR);                   /* Set the PHY register address */
01070   tmpreg1 &= ~ETH_MACMIIAR_MW;                                            /* Set the read mode            */
01071   tmpreg1 |= ETH_MACMIIAR_MB;                                             /* Set the MII Busy bit         */
01072
01073   /* Write the result value into the MII Address register */
01074   heth->Instance->MACMIIAR = tmpreg1;
01075
01076   /* Get tick */
01077   tickstart = HAL_GetTick();
01078
01079   /* Check for the Busy flag */
01080   while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
01081   {
01082     /* Check for the Timeout */
01083     if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
01084     {
01085       heth->State= HAL_ETH_STATE_READY;
01086
01087       /* Process Unlocked */
01088       __HAL_UNLOCK(heth);
01089
01090       return HAL_TIMEOUT;
01091     }
01092
01093     tmpreg1 = heth->Instance->MACMIIAR;
01094   }
01095
01096   /* Get MACMIIDR value */
01097   *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
01098
01099   /* Set ETH HAL State to READY */
01100   heth->State = HAL_ETH_STATE_READY;
01101
01102   /* Return function status */
01103   return HAL_OK;
01104 }
01105
01106 /**
01107   * @brief  Writes to a PHY register.
01108   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01109   *         the configuration information for ETHERNET module
01110   * @param  PHYReg: PHY register address, is the index of one of the 32 PHY register.
01111   *          This parameter can be one of the following values:
01112   *             PHY_BCR: Transceiver Control Register.
01113   *             More PHY register could be written depending on the used PHY
01114   * @param  RegValue: the value to write
01115   * @retval HAL status
01116   */
01117 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
01118 {
01119   uint32_t tmpreg1 = 0U;
01120   uint32_t tickstart = 0U;
01121
01122   /* Check parameters */
01123   assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
01124
01125   /* Check the ETH peripheral state */
01126   if(heth->State == HAL_ETH_STATE_BUSY_WR)
01127   {
01128     return HAL_BUSY;
01129   }
01130   /* Set ETH HAL State to BUSY_WR */
01131   heth->State = HAL_ETH_STATE_BUSY_WR;
01132
01133   /* Get the ETHERNET MACMIIAR value */
01134   tmpreg1 = heth->Instance->MACMIIAR;
01135
01136   /* Keep only the CSR Clock Range CR[2:0] bits value */
01137   tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
01138
01139   /* Prepare the MII register address value */
01140   tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
01141   tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR);                 /* Set the PHY register address */
01142   tmpreg1 |= ETH_MACMIIAR_MW;                                           /* Set the write mode */
01143   tmpreg1 |= ETH_MACMIIAR_MB;                                           /* Set the MII Busy bit */
01144
01145   /* Give the value to the MII data register */
01146   heth->Instance->MACMIIDR = (uint16_t)RegValue;
01147
01148   /* Write the result value into the MII Address register */
01149   heth->Instance->MACMIIAR = tmpreg1;
01150
01151   /* Get tick */
01152   tickstart = HAL_GetTick();
01153
01154   /* Check for the Busy flag */
01155   while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
01156   {
01157     /* Check for the Timeout */
01158     if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
01159     {
01160       heth->State= HAL_ETH_STATE_READY;
01161
01162       /* Process Unlocked */
01163       __HAL_UNLOCK(heth);
01164
01165       return HAL_TIMEOUT;
01166     }
01167
01168     tmpreg1 = heth->Instance->MACMIIAR;
01169   }
01170
01171   /* Set ETH HAL State to READY */
01172   heth->State = HAL_ETH_STATE_READY;
01173
01174   /* Return function status */
01175   return HAL_OK;
01176 }
01177
01178 /**
01179   * @}
01180   */
01181
01182 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
01183  *  @brief    Peripheral Control functions
01184  *
01185 @verbatim
01186  ===============================================================================
01187                   ##### Peripheral Control functions #####
01188  ===============================================================================
01189     [..]  This section provides functions allowing to:
01190       (+) Enable MAC and DMA transmission and reception.
01191           HAL_ETH_Start();
01192       (+) Disable MAC and DMA transmission and reception.
01193           HAL_ETH_Stop();
01194       (+) Set the MAC configuration in runtime mode
01195           HAL_ETH_ConfigMAC();
01196       (+) Set the DMA configuration in runtime mode
01197           HAL_ETH_ConfigDMA();
01198
01199 @endverbatim
01200   * @{
01201   */
01202
01203  /**
01204   * @brief  Enables Ethernet MAC and DMA reception/transmission
01205   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01206   *         the configuration information for ETHERNET module
01207   * @retval HAL status
01208   */
01209 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
01210 {
01211   /* Process Locked */
01212   __HAL_LOCK(heth);
01213
01214   /* Set the ETH peripheral state to BUSY */
01215   heth->State = HAL_ETH_STATE_BUSY;
01216
01217   /* Enable transmit state machine of the MAC for transmission on the MII */
01218   ETH_MACTransmissionEnable(heth);
01219
01220   /* Enable receive state machine of the MAC for reception from the MII */
01221   ETH_MACReceptionEnable(heth);
01222
01223   /* Flush Transmit FIFO */
01224   ETH_FlushTransmitFIFO(heth);
01225
01226   /* Start DMA transmission */
01227   ETH_DMATransmissionEnable(heth);
01228
01229   /* Start DMA reception */
01230   ETH_DMAReceptionEnable(heth);
01231
01232   /* Set the ETH state to READY*/
01233   heth->State= HAL_ETH_STATE_READY;
01234
01235   /* Process Unlocked */
01236   __HAL_UNLOCK(heth);
01237
01238   /* Return function status */
01239   return HAL_OK;
01240 }
01241
01242 /**
01243   * @brief  Stop Ethernet MAC and DMA reception/transmission
01244   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01245   *         the configuration information for ETHERNET module
01246   * @retval HAL status
01247   */
01248 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
01249 {
01250   /* Process Locked */
01251   __HAL_LOCK(heth);
01252
01253   /* Set the ETH peripheral state to BUSY */
01254   heth->State = HAL_ETH_STATE_BUSY;
01255
01256   /* Stop DMA transmission */
01257   ETH_DMATransmissionDisable(heth);
01258
01259   /* Stop DMA reception */
01260   ETH_DMAReceptionDisable(heth);
01261
01262   /* Disable receive state machine of the MAC for reception from the MII */
01263   ETH_MACReceptionDisable(heth);
01264
01265   /* Flush Transmit FIFO */
01266   ETH_FlushTransmitFIFO(heth);
01267
01268   /* Disable transmit state machine of the MAC for transmission on the MII */
01269   ETH_MACTransmissionDisable(heth);
01270
01271   /* Set the ETH state*/
01272   heth->State = HAL_ETH_STATE_READY;
01273
01274   /* Process Unlocked */
01275   __HAL_UNLOCK(heth);
01276
01277   /* Return function status */
01278   return HAL_OK;
01279 }
01280
01281 /**
01282   * @brief  Set ETH MAC Configuration.
01283   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01284   *         the configuration information for ETHERNET module
01285   * @param  macconf: MAC Configuration structure
01286   * @retval HAL status
01287   */
01288 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
01289 {
01290   uint32_t tmpreg1 = 0U;
01291
01292   /* Process Locked */
01293   __HAL_LOCK(heth);
01294
01295   /* Set the ETH peripheral state to BUSY */
01296   heth->State= HAL_ETH_STATE_BUSY;
01297
01298   assert_param(IS_ETH_SPEED(heth->Init.Speed));
01299   assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
01300
01301   if (macconf != NULL)
01302   {
01303     /* Check the parameters */
01304     assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
01305     assert_param(IS_ETH_JABBER(macconf->Jabber));
01306     assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
01307     assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
01308     assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
01309     assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
01310     assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
01311     assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
01312     assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
01313     assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
01314     assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
01315     assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
01316     assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
01317     assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
01318     assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
01319     assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
01320     assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
01321     assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
01322     assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
01323     assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
01324     assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
01325     assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
01326     assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
01327     assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
01328     assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
01329     assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
01330     assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
01331
01332     /*------------------------ ETHERNET MACCR Configuration --------------------*/
01333     /* Get the ETHERNET MACCR value */
01334     tmpreg1 = (heth->Instance)->MACCR;
01335     /* Clear WD, PCE, PS, TE and RE bits */
01336     tmpreg1 &= ETH_MACCR_CLEAR_MASK;
01337
01338     tmpreg1 |= (uint32_t)(macconf->Watchdog |
01339                          macconf->Jabber |
01340                          macconf->InterFrameGap |
01341                          macconf->CarrierSense |
01342                          (heth->Init).Speed |
01343                          macconf->ReceiveOwn |
01344                          macconf->LoopbackMode |
01345                          (heth->Init).DuplexMode |
01346                          macconf->ChecksumOffload |
01347                          macconf->RetryTransmission |
01348                          macconf->AutomaticPadCRCStrip |
01349                          macconf->BackOffLimit |
01350                          macconf->DeferralCheck);
01351
01352     /* Write to ETHERNET MACCR */
01353     (heth->Instance)->MACCR = (uint32_t)tmpreg1;
01354
01355     /* Wait until the write operation will be taken into account :
01356     at least four TX_CLK/RX_CLK clock cycles */
01357     tmpreg1 = (heth->Instance)->MACCR;
01358     HAL_Delay(ETH_REG_WRITE_DELAY);
01359     (heth->Instance)->MACCR = tmpreg1;
01360
01361     /*----------------------- ETHERNET MACFFR Configuration --------------------*/
01362     /* Write to ETHERNET MACFFR */
01363     (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
01364                                           macconf->SourceAddrFilter |
01365                                           macconf->PassControlFrames |
01366                                           macconf->BroadcastFramesReception |
01367                                           macconf->DestinationAddrFilter |
01368                                           macconf->PromiscuousMode |
01369                                           macconf->MulticastFramesFilter |
01370                                           macconf->UnicastFramesFilter);
01371
01372      /* Wait until the write operation will be taken into account :
01373      at least four TX_CLK/RX_CLK clock cycles */
01374      tmpreg1 = (heth->Instance)->MACFFR;
01375      HAL_Delay(ETH_REG_WRITE_DELAY);
01376      (heth->Instance)->MACFFR = tmpreg1;
01377
01378      /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
01379      /* Write to ETHERNET MACHTHR */
01380      (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
01381
01382      /* Write to ETHERNET MACHTLR */
01383      (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
01384      /*----------------------- ETHERNET MACFCR Configuration --------------------*/
01385
01386      /* Get the ETHERNET MACFCR value */
01387      tmpreg1 = (heth->Instance)->MACFCR;
01388      /* Clear xx bits */
01389      tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
01390
01391      tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
01392                           macconf->ZeroQuantaPause |
01393                           macconf->PauseLowThreshold |
01394                           macconf->UnicastPauseFrameDetect |
01395                           macconf->ReceiveFlowControl |
01396                           macconf->TransmitFlowControl);
01397
01398      /* Write to ETHERNET MACFCR */
01399      (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
01400
01401      /* Wait until the write operation will be taken into account :
01402      at least four TX_CLK/RX_CLK clock cycles */
01403      tmpreg1 = (heth->Instance)->MACFCR;
01404      HAL_Delay(ETH_REG_WRITE_DELAY);
01405      (heth->Instance)->MACFCR = tmpreg1;
01406
01407      /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
01408      (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
01409                                               macconf->VLANTagIdentifier);
01410
01411       /* Wait until the write operation will be taken into account :
01412       at least four TX_CLK/RX_CLK clock cycles */
01413       tmpreg1 = (heth->Instance)->MACVLANTR;
01414       HAL_Delay(ETH_REG_WRITE_DELAY);
01415       (heth->Instance)->MACVLANTR = tmpreg1;
01416   }
01417   else /* macconf == NULL : here we just configure Speed and Duplex mode */
01418   {
01419     /*------------------------ ETHERNET MACCR Configuration --------------------*/
01420     /* Get the ETHERNET MACCR value */
01421     tmpreg1 = (heth->Instance)->MACCR;
01422
01423     /* Clear FES and DM bits */
01424     tmpreg1 &= ~(0x00004800U);
01425
01426     tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
01427
01428     /* Write to ETHERNET MACCR */
01429     (heth->Instance)->MACCR = (uint32_t)tmpreg1;
01430
01431     /* Wait until the write operation will be taken into account:
01432     at least four TX_CLK/RX_CLK clock cycles */
01433     tmpreg1 = (heth->Instance)->MACCR;
01434     HAL_Delay(ETH_REG_WRITE_DELAY);
01435     (heth->Instance)->MACCR = tmpreg1;
01436   }
01437
01438   /* Set the ETH state to Ready */
01439   heth->State= HAL_ETH_STATE_READY;
01440
01441   /* Process Unlocked */
01442   __HAL_UNLOCK(heth);
01443
01444   /* Return function status */
01445   return HAL_OK;
01446 }
01447
01448 /**
01449   * @brief  Sets ETH DMA Configuration.
01450   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01451   *         the configuration information for ETHERNET module
01452   * @param  dmaconf: DMA Configuration structure
01453   * @retval HAL status
01454   */
01455 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
01456 {
01457   uint32_t tmpreg1 = 0U;
01458
01459   /* Process Locked */
01460   __HAL_LOCK(heth);
01461
01462   /* Set the ETH peripheral state to BUSY */
01463   heth->State= HAL_ETH_STATE_BUSY;
01464
01465   /* Check parameters */
01466   assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
01467   assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
01468   assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
01469   assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
01470   assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
01471   assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
01472   assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
01473   assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
01474   assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
01475   assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
01476   assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
01477   assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
01478   assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
01479   assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
01480   assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
01481
01482   /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
01483   /* Get the ETHERNET DMAOMR value */
01484   tmpreg1 = (heth->Instance)->DMAOMR;
01485   /* Clear xx bits */
01486   tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
01487
01488   tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
01489                        dmaconf->ReceiveStoreForward |
01490                        dmaconf->FlushReceivedFrame |
01491                        dmaconf->TransmitStoreForward |
01492                        dmaconf->TransmitThresholdControl |
01493                        dmaconf->ForwardErrorFrames |
01494                        dmaconf->ForwardUndersizedGoodFrames |
01495                        dmaconf->ReceiveThresholdControl |
01496                        dmaconf->SecondFrameOperate);
01497
01498   /* Write to ETHERNET DMAOMR */
01499   (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
01500
01501   /* Wait until the write operation will be taken into account:
01502   at least four TX_CLK/RX_CLK clock cycles */
01503   tmpreg1 = (heth->Instance)->DMAOMR;
01504   HAL_Delay(ETH_REG_WRITE_DELAY);
01505   (heth->Instance)->DMAOMR = tmpreg1;
01506
01507   /*----------------------- ETHERNET DMABMR Configuration --------------------*/
01508   (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
01509                                          dmaconf->FixedBurst |
01510                                          dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
01511                                          dmaconf->TxDMABurstLength |
01512                                          (dmaconf->DescriptorSkipLength << 2U) |
01513                                          dmaconf->DMAArbitration |
01514                                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
01515
01516    /* Wait until the write operation will be taken into account:
01517       at least four TX_CLK/RX_CLK clock cycles */
01518    tmpreg1 = (heth->Instance)->DMABMR;
01519    HAL_Delay(ETH_REG_WRITE_DELAY);
01520    (heth->Instance)->DMABMR = tmpreg1;
01521
01522    /* Set the ETH state to Ready */
01523    heth->State= HAL_ETH_STATE_READY;
01524
01525    /* Process Unlocked */
01526    __HAL_UNLOCK(heth);
01527
01528    /* Return function status */
01529    return HAL_OK;
01530 }
01531
01532 /**
01533   * @}
01534   */
01535
01536 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
01537   *  @brief   Peripheral State functions
01538   *
01539   @verbatim
01540   ===============================================================================
01541                          ##### Peripheral State functions #####
01542   ===============================================================================
01543   [..]
01544   This subsection permits to get in run-time the status of the peripheral
01545   and the data flow.
01546        (+) Get the ETH handle state:
01547            HAL_ETH_GetState();
01548
01549
01550   @endverbatim
01551   * @{
01552   */
01553
01554 /**
01555   * @brief  Return the ETH HAL state
01556   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01557   *         the configuration information for ETHERNET module
01558   * @retval HAL state
01559   */
01560 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
01561 {
01562   /* Return ETH state */
01563   return heth->State;
01564 }
01565
01566 /**
01567   * @}
01568   */
01569
01570 /**
01571   * @}
01572   */
01573
01574 /** @addtogroup ETH_Private_Functions
01575   * @{
01576   */
01577
01578 /**
01579   * @brief  Configures Ethernet MAC and DMA with default parameters.
01580   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01581   *         the configuration information for ETHERNET module
01582   * @param  err: Ethernet Init error
01583   * @retval HAL status
01584   */
01585 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
01586 {
01587   ETH_MACInitTypeDef macinit;
01588   ETH_DMAInitTypeDef dmainit;
01589   uint32_t tmpreg1 = 0U;
01590
01591   if (err != ETH_SUCCESS) /* Auto-negotiation failed */
01592   {
01593     /* Set Ethernet duplex mode to Full-duplex */
01594     (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
01595
01596     /* Set Ethernet speed to 100M */
01597     (heth->Init).Speed = ETH_SPEED_100M;
01598   }
01599
01600   /* Ethernet MAC default initialization **************************************/
01601   macinit.Watchdog = ETH_WATCHDOG_ENABLE;
01602   macinit.Jabber = ETH_JABBER_ENABLE;
01603   macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
01604   macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
01605   macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
01606   macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
01607   if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
01608   {
01609     macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
01610   }
01611   else
01612   {
01613     macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
01614   }
01615   macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
01616   macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
01617   macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
01618   macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
01619   macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
01620   macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
01621   macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
01622   macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
01623   macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
01624   macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
01625   macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
01626   macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
01627   macinit.HashTableHigh = 0x0U;
01628   macinit.HashTableLow = 0x0U;
01629   macinit.PauseTime = 0x0U;
01630   macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
01631   macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
01632   macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
01633   macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
01634   macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
01635   macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
01636   macinit.VLANTagIdentifier = 0x0U;
01637
01638   /*------------------------ ETHERNET MACCR Configuration --------------------*/
01639   /* Get the ETHERNET MACCR value */
01640   tmpreg1 = (heth->Instance)->MACCR;
01641   /* Clear WD, PCE, PS, TE and RE bits */
01642   tmpreg1 &= ETH_MACCR_CLEAR_MASK;
01643   /* Set the WD bit according to ETH Watchdog value */
01644   /* Set the JD: bit according to ETH Jabber value */
01645   /* Set the IFG bit according to ETH InterFrameGap value */
01646   /* Set the DCRS bit according to ETH CarrierSense value */
01647   /* Set the FES bit according to ETH Speed value */
01648   /* Set the DO bit according to ETH ReceiveOwn value */
01649   /* Set the LM bit according to ETH LoopbackMode value */
01650   /* Set the DM bit according to ETH Mode value */
01651   /* Set the IPCO bit according to ETH ChecksumOffload value */
01652   /* Set the DR bit according to ETH RetryTransmission value */
01653   /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
01654   /* Set the BL bit according to ETH BackOffLimit value */
01655   /* Set the DC bit according to ETH DeferralCheck value */
01656   tmpreg1 |= (uint32_t)(macinit.Watchdog |
01657                        macinit.Jabber |
01658                        macinit.InterFrameGap |
01659                        macinit.CarrierSense |
01660                        (heth->Init).Speed |
01661                        macinit.ReceiveOwn |
01662                        macinit.LoopbackMode |
01663                        (heth->Init).DuplexMode |
01664                        macinit.ChecksumOffload |
01665                        macinit.RetryTransmission |
01666                        macinit.AutomaticPadCRCStrip |
01667                        macinit.BackOffLimit |
01668                        macinit.DeferralCheck);
01669
01670   /* Write to ETHERNET MACCR */
01671   (heth->Instance)->MACCR = (uint32_t)tmpreg1;
01672
01673   /* Wait until the write operation will be taken into account:
01674      at least four TX_CLK/RX_CLK clock cycles */
01675   tmpreg1 = (heth->Instance)->MACCR;
01676   HAL_Delay(ETH_REG_WRITE_DELAY);
01677   (heth->Instance)->MACCR = tmpreg1;
01678
01679   /*----------------------- ETHERNET MACFFR Configuration --------------------*/
01680   /* Set the RA bit according to ETH ReceiveAll value */
01681   /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
01682   /* Set the PCF bit according to ETH PassControlFrames value */
01683   /* Set the DBF bit according to ETH BroadcastFramesReception value */
01684   /* Set the DAIF bit according to ETH DestinationAddrFilter value */
01685   /* Set the PR bit according to ETH PromiscuousMode value */
01686   /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
01687   /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
01688   /* Write to ETHERNET MACFFR */
01689   (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
01690                                         macinit.SourceAddrFilter |
01691                                         macinit.PassControlFrames |
01692                                         macinit.BroadcastFramesReception |
01693                                         macinit.DestinationAddrFilter |
01694                                         macinit.PromiscuousMode |
01695                                         macinit.MulticastFramesFilter |
01696                                         macinit.UnicastFramesFilter);
01697
01698    /* Wait until the write operation will be taken into account:
01699       at least four TX_CLK/RX_CLK clock cycles */
01700    tmpreg1 = (heth->Instance)->MACFFR;
01701    HAL_Delay(ETH_REG_WRITE_DELAY);
01702    (heth->Instance)->MACFFR = tmpreg1;
01703
01704    /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
01705    /* Write to ETHERNET MACHTHR */
01706    (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
01707
01708    /* Write to ETHERNET MACHTLR */
01709    (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
01710    /*----------------------- ETHERNET MACFCR Configuration -------------------*/
01711
01712    /* Get the ETHERNET MACFCR value */
01713    tmpreg1 = (heth->Instance)->MACFCR;
01714    /* Clear xx bits */
01715    tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
01716
01717    /* Set the PT bit according to ETH PauseTime value */
01718    /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
01719    /* Set the PLT bit according to ETH PauseLowThreshold value */
01720    /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
01721    /* Set the RFE bit according to ETH ReceiveFlowControl value */
01722    /* Set the TFE bit according to ETH TransmitFlowControl value */
01723    tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
01724                         macinit.ZeroQuantaPause |
01725                         macinit.PauseLowThreshold |
01726                         macinit.UnicastPauseFrameDetect |
01727                         macinit.ReceiveFlowControl |
01728                         macinit.TransmitFlowControl);
01729
01730    /* Write to ETHERNET MACFCR */
01731    (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
01732
01733    /* Wait until the write operation will be taken into account:
01734    at least four TX_CLK/RX_CLK clock cycles */
01735    tmpreg1 = (heth->Instance)->MACFCR;
01736    HAL_Delay(ETH_REG_WRITE_DELAY);
01737    (heth->Instance)->MACFCR = tmpreg1;
01738
01739    /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
01740    /* Set the ETV bit according to ETH VLANTagComparison value */
01741    /* Set the VL bit according to ETH VLANTagIdentifier value */
01742    (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
01743                                             macinit.VLANTagIdentifier);
01744
01745     /* Wait until the write operation will be taken into account:
01746        at least four TX_CLK/RX_CLK clock cycles */
01747     tmpreg1 = (heth->Instance)->MACVLANTR;
01748     HAL_Delay(ETH_REG_WRITE_DELAY);
01749     (heth->Instance)->MACVLANTR = tmpreg1;
01750
01751     /* Ethernet DMA default initialization ************************************/
01752     dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
01753     dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
01754     dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
01755     dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
01756     dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
01757     dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
01758     dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
01759     dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
01760     dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
01761     dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
01762     dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
01763     dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
01764     dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
01765     dmainit.DescriptorSkipLength = 0x0U;
01766     dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
01767
01768     /* Get the ETHERNET DMAOMR value */
01769     tmpreg1 = (heth->Instance)->DMAOMR;
01770     /* Clear xx bits */
01771     tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
01772
01773     /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
01774     /* Set the RSF bit according to ETH ReceiveStoreForward value */
01775     /* Set the DFF bit according to ETH FlushReceivedFrame value */
01776     /* Set the TSF bit according to ETH TransmitStoreForward value */
01777     /* Set the TTC bit according to ETH TransmitThresholdControl value */
01778     /* Set the FEF bit according to ETH ForwardErrorFrames value */
01779     /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
01780     /* Set the RTC bit according to ETH ReceiveThresholdControl value */
01781     /* Set the OSF bit according to ETH SecondFrameOperate value */
01782     tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
01783                          dmainit.ReceiveStoreForward |
01784                          dmainit.FlushReceivedFrame |
01785                          dmainit.TransmitStoreForward |
01786                          dmainit.TransmitThresholdControl |
01787                          dmainit.ForwardErrorFrames |
01788                          dmainit.ForwardUndersizedGoodFrames |
01789                          dmainit.ReceiveThresholdControl |
01790                          dmainit.SecondFrameOperate);
01791
01792     /* Write to ETHERNET DMAOMR */
01793     (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
01794
01795     /* Wait until the write operation will be taken into account:
01796        at least four TX_CLK/RX_CLK clock cycles */
01797     tmpreg1 = (heth->Instance)->DMAOMR;
01798     HAL_Delay(ETH_REG_WRITE_DELAY);
01799     (heth->Instance)->DMAOMR = tmpreg1;
01800
01801     /*----------------------- ETHERNET DMABMR Configuration ------------------*/
01802     /* Set the AAL bit according to ETH AddressAlignedBeats value */
01803     /* Set the FB bit according to ETH FixedBurst value */
01804     /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
01805     /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
01806     /* Set the DSL bit according to ETH DesciptorSkipLength value */
01807     /* Set the PR and DA bits according to ETH DMAArbitration value */
01808     (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
01809                                           dmainit.FixedBurst |
01810                                           dmainit.RxDMABurstLength |    /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
01811                                           dmainit.TxDMABurstLength |
01812                                           (dmainit.DescriptorSkipLength << 2U) |
01813                                           dmainit.DMAArbitration |
01814                                           ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
01815
01816      /* Wait until the write operation will be taken into account:
01817         at least four TX_CLK/RX_CLK clock cycles */
01818      tmpreg1 = (heth->Instance)->DMABMR;
01819      HAL_Delay(ETH_REG_WRITE_DELAY);
01820      (heth->Instance)->DMABMR = tmpreg1;
01821
01822      if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
01823      {
01824        /* Enable the Ethernet Rx Interrupt */
01825        __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
01826      }
01827
01828      /* Initialize MAC address in ethernet MAC */
01829      ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
01830 }
01831
01832 /**
01833   * @brief  Configures the selected MAC address.
01834   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01835   *         the configuration information for ETHERNET module
01836   * @param  MacAddr: The MAC address to configure
01837   *          This parameter can be one of the following values:
01838   *             @arg ETH_MAC_Address0: MAC Address0
01839   *             @arg ETH_MAC_Address1: MAC Address1
01840   *             @arg ETH_MAC_Address2: MAC Address2
01841   *             @arg ETH_MAC_Address3: MAC Address3
01842   * @param  Addr: Pointer to MAC address buffer data (6 bytes)
01843   * @retval HAL status
01844   */
01845 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
01846 {
01847   uint32_t tmpreg1;
01848
01849   /* Prevent unused argument(s) compilation warning */
01850   UNUSED(heth);
01851
01852   /* Check the parameters */
01853   assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
01854
01855   /* Calculate the selected MAC address high register */
01856   tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
01857   /* Load the selected MAC address high register */
01858   (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
01859   /* Calculate the selected MAC address low register */
01860   tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
01861
01862   /* Load the selected MAC address low register */
01863   (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
01864 }
01865
01866 /**
01867   * @brief  Enables the MAC transmission.
01868   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01869   *         the configuration information for ETHERNET module
01870   * @retval None
01871   */
01872 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
01873 {
01874   __IO uint32_t tmpreg1 = 0U;
01875
01876   /* Enable the MAC transmission */
01877   (heth->Instance)->MACCR |= ETH_MACCR_TE;
01878
01879   /* Wait until the write operation will be taken into account:
01880      at least four TX_CLK/RX_CLK clock cycles */
01881   tmpreg1 = (heth->Instance)->MACCR;
01882   ETH_Delay(ETH_REG_WRITE_DELAY);
01883   (heth->Instance)->MACCR = tmpreg1;
01884 }
01885
01886 /**
01887   * @brief  Disables the MAC transmission.
01888   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01889   *         the configuration information for ETHERNET module
01890   * @retval None
01891   */
01892 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
01893 {
01894   __IO uint32_t tmpreg1 = 0U;
01895
01896   /* Disable the MAC transmission */
01897   (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
01898
01899   /* Wait until the write operation will be taken into account:
01900      at least four TX_CLK/RX_CLK clock cycles */
01901   tmpreg1 = (heth->Instance)->MACCR;
01902   ETH_Delay(ETH_REG_WRITE_DELAY);
01903   (heth->Instance)->MACCR = tmpreg1;
01904 }
01905
01906 /**
01907   * @brief  Enables the MAC reception.
01908   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01909   *         the configuration information for ETHERNET module
01910   * @retval None
01911   */
01912 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
01913 {
01914   __IO uint32_t tmpreg1 = 0U;
01915
01916   /* Enable the MAC reception */
01917   (heth->Instance)->MACCR |= ETH_MACCR_RE;
01918
01919   /* Wait until the write operation will be taken into account:
01920      at least four TX_CLK/RX_CLK clock cycles */
01921   tmpreg1 = (heth->Instance)->MACCR;
01922   ETH_Delay(ETH_REG_WRITE_DELAY);
01923   (heth->Instance)->MACCR = tmpreg1;
01924 }
01925
01926 /**
01927   * @brief  Disables the MAC reception.
01928   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01929   *         the configuration information for ETHERNET module
01930   * @retval None
01931   */
01932 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
01933 {
01934   __IO uint32_t tmpreg1 = 0U;
01935
01936   /* Disable the MAC reception */
01937   (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
01938
01939   /* Wait until the write operation will be taken into account:
01940      at least four TX_CLK/RX_CLK clock cycles */
01941   tmpreg1 = (heth->Instance)->MACCR;
01942   ETH_Delay(ETH_REG_WRITE_DELAY);
01943   (heth->Instance)->MACCR = tmpreg1;
01944 }
01945
01946 /**
01947   * @brief  Enables the DMA transmission.
01948   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01949   *         the configuration information for ETHERNET module
01950   * @retval None
01951   */
01952 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
01953 {
01954   /* Enable the DMA transmission */
01955   (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
01956 }
01957
01958 /**
01959   * @brief  Disables the DMA transmission.
01960   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01961   *         the configuration information for ETHERNET module
01962   * @retval None
01963   */
01964 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
01965 {
01966   /* Disable the DMA transmission */
01967   (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
01968 }
01969
01970 /**
01971   * @brief  Enables the DMA reception.
01972   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01973   *         the configuration information for ETHERNET module
01974   * @retval None
01975   */
01976 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
01977 {
01978   /* Enable the DMA reception */
01979   (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
01980 }
01981
01982 /**
01983   * @brief  Disables the DMA reception.
01984   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01985   *         the configuration information for ETHERNET module
01986   * @retval None
01987   */
01988 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
01989 {
01990   /* Disable the DMA reception */
01991   (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
01992 }
01993
01994 /**
01995   * @brief  Clears the ETHERNET transmit FIFO.
01996   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
01997   *         the configuration information for ETHERNET module
01998   * @retval None
01999   */
02000 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
02001 {
02002   __IO uint32_t tmpreg1 = 0U;
02003
02004   /* Set the Flush Transmit FIFO bit */
02005   (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
02006
02007   /* Wait until the write operation will be taken into account:
02008      at least four TX_CLK/RX_CLK clock cycles */
02009   tmpreg1 = (heth->Instance)->DMAOMR;
02010   ETH_Delay(ETH_REG_WRITE_DELAY);
02011   (heth->Instance)->DMAOMR = tmpreg1;
02012 }
02013
02014 /**
02015   * @brief  This function provides delay (in milliseconds) based on CPU cycles method.
02016   * @param  mdelay: specifies the delay time length, in milliseconds.
02017   * @retval None
02018   */
02019 static void ETH_Delay(uint32_t mdelay)
02020 {
02021   __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
02022   do
02023   {
02024     __NOP();
02025   }
02026   while (Delay --);
02027 }
02028
02029 /**
02030   * @}
02031   */
02032
02033 #endif /* HAL_ETH_MODULE_ENABLED */
02034 /**
02035   * @}
02036   */
02037
02038 #endif /* STM32F107xC */
02039 /**
02040   * @}
02041   */
02042
02043 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_eth.h Source File

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stm32f1xx_hal_eth.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_eth.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of ETH HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_ETH_H
00040 #define __STM32F1xx_HAL_ETH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052 #if defined (STM32F107xC)
00053
00054 /** @addtogroup ETH
00055   * @{
00056   */
00057
00058 /** @addtogroup ETH_Private_Macros
00059   * @{
00060   */
00061 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
00062 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
00063                                      ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
00064 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
00065                              ((SPEED) == ETH_SPEED_100M))
00066 #define IS_ETH_DUPLEX_MODE(MODE)  (((MODE) == ETH_MODE_FULLDUPLEX) || \
00067                                   ((MODE) == ETH_MODE_HALFDUPLEX))
00068 #define IS_ETH_RX_MODE(MODE)    (((MODE) == ETH_RXPOLLING_MODE) || \
00069                                  ((MODE) == ETH_RXINTERRUPT_MODE))
00070 #define IS_ETH_CHECKSUM_MODE(MODE)    (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
00071                                       ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
00072 #define IS_ETH_MEDIA_INTERFACE(MODE)         (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
00073                                               ((MODE) == ETH_MEDIA_INTERFACE_RMII))
00074 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
00075                               ((CMD) == ETH_WATCHDOG_DISABLE))
00076 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
00077                             ((CMD) == ETH_JABBER_DISABLE))
00078 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
00079                                      ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
00080                                      ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
00081                                      ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
00082                                      ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
00083                                      ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
00084                                      ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
00085                                      ((GAP) == ETH_INTERFRAMEGAP_40BIT))
00086 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
00087                                    ((CMD) == ETH_CARRIERSENCE_DISABLE))
00088 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
00089                                  ((CMD) == ETH_RECEIVEOWN_DISABLE))
00090 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
00091                                    ((CMD) == ETH_LOOPBACKMODE_DISABLE))
00092 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
00093                                       ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
00094 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
00095                                         ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
00096 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
00097                                             ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
00098 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
00099                                      ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
00100                                      ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
00101                                      ((LIMIT) == ETH_BACKOFFLIMIT_1))
00102 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
00103                                     ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
00104 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
00105                                  ((CMD) == ETH_RECEIVEAll_DISABLE))
00106 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
00107                                         ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
00108                                         ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
00109 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
00110                                      ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
00111                                      ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
00112 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
00113                                                 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
00114 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
00115                                                 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
00116 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
00117                                       ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
00118 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
00119                                                 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
00120                                                 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
00121                                                 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
00122 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
00123                                               ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
00124                                               ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
00125 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
00126 #define IS_ETH_ZEROQUANTA_PAUSE(CMD)   (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
00127                                         ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
00128 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
00129                                                ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
00130                                                ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
00131                                                ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
00132 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
00133                                                 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
00134 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
00135                                          ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
00136 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
00137                                           ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
00138 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
00139                                                 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
00140 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
00141 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
00142                                          ((ADDRESS) == ETH_MAC_ADDRESS1) || \
00143                                          ((ADDRESS) == ETH_MAC_ADDRESS2) || \
00144                                          ((ADDRESS) == ETH_MAC_ADDRESS3))
00145 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
00146                                         ((ADDRESS) == ETH_MAC_ADDRESS2) || \
00147                                         ((ADDRESS) == ETH_MAC_ADDRESS3))
00148 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
00149                                            ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
00150 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
00151                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
00152                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
00153                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
00154                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
00155                                        ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
00156 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
00157                                                ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
00158 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
00159                                            ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
00160 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
00161                                          ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
00162 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
00163                                             ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
00164 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
00165                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
00166                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
00167                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
00168                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
00169                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
00170                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
00171                                                       ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
00172 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
00173                                           ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
00174 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
00175                                                     ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
00176 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
00177                                                      ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
00178                                                      ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
00179                                                      ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
00180 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
00181                                           ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
00182 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
00183                                            ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
00184 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
00185                                  ((CMD) == ETH_FIXEDBURST_DISABLE))
00186 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
00187                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
00188                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
00189                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
00190                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
00191                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
00192                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
00193                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
00194                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
00195                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
00196                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
00197                                            ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
00198 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
00199                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
00200                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
00201                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
00202                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
00203                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
00204                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
00205                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
00206                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
00207                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
00208                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
00209                                            ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
00210 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
00211 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
00212                                                        ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
00213                                                        ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
00214                                                        ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
00215                                                        ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
00216 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
00217                                          ((FLAG) == ETH_DMATXDESC_IC) || \
00218                                          ((FLAG) == ETH_DMATXDESC_LS) || \
00219                                          ((FLAG) == ETH_DMATXDESC_FS) || \
00220                                          ((FLAG) == ETH_DMATXDESC_DC) || \
00221                                          ((FLAG) == ETH_DMATXDESC_DP) || \
00222                                          ((FLAG) == ETH_DMATXDESC_TTSE) || \
00223                                          ((FLAG) == ETH_DMATXDESC_TER) || \
00224                                          ((FLAG) == ETH_DMATXDESC_TCH) || \
00225                                          ((FLAG) == ETH_DMATXDESC_TTSS) || \
00226                                          ((FLAG) == ETH_DMATXDESC_IHE) || \
00227                                          ((FLAG) == ETH_DMATXDESC_ES) || \
00228                                          ((FLAG) == ETH_DMATXDESC_JT) || \
00229                                          ((FLAG) == ETH_DMATXDESC_FF) || \
00230                                          ((FLAG) == ETH_DMATXDESC_PCE) || \
00231                                          ((FLAG) == ETH_DMATXDESC_LCA) || \
00232                                          ((FLAG) == ETH_DMATXDESC_NC) || \
00233                                          ((FLAG) == ETH_DMATXDESC_LCO) || \
00234                                          ((FLAG) == ETH_DMATXDESC_EC) || \
00235                                          ((FLAG) == ETH_DMATXDESC_VF) || \
00236                                          ((FLAG) == ETH_DMATXDESC_CC) || \
00237                                          ((FLAG) == ETH_DMATXDESC_ED) || \
00238                                          ((FLAG) == ETH_DMATXDESC_UF) || \
00239                                          ((FLAG) == ETH_DMATXDESC_DB))
00240 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
00241                                             ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
00242 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
00243                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
00244                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
00245                                               ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
00246 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
00247 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
00248                                          ((FLAG) == ETH_DMARXDESC_AFM) || \
00249                                          ((FLAG) == ETH_DMARXDESC_ES) || \
00250                                          ((FLAG) == ETH_DMARXDESC_DE) || \
00251                                          ((FLAG) == ETH_DMARXDESC_SAF) || \
00252                                          ((FLAG) == ETH_DMARXDESC_LE) || \
00253                                          ((FLAG) == ETH_DMARXDESC_OE) || \
00254                                          ((FLAG) == ETH_DMARXDESC_VLAN) || \
00255                                          ((FLAG) == ETH_DMARXDESC_FS) || \
00256                                          ((FLAG) == ETH_DMARXDESC_LS) || \
00257                                          ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
00258                                          ((FLAG) == ETH_DMARXDESC_LC) || \
00259                                          ((FLAG) == ETH_DMARXDESC_FT) || \
00260                                          ((FLAG) == ETH_DMARXDESC_RWT) || \
00261                                          ((FLAG) == ETH_DMARXDESC_RE) || \
00262                                          ((FLAG) == ETH_DMARXDESC_DBE) || \
00263                                          ((FLAG) == ETH_DMARXDESC_CE) || \
00264                                          ((FLAG) == ETH_DMARXDESC_MAMPCE))
00265 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
00266                                           ((BUFFER) == ETH_DMARXDESC_BUFFER2))
00267 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
00268                                    ((FLAG) == ETH_PMT_FLAG_MPR))
00269 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
00270 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
00271                                    ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
00272                                    ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
00273                                    ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
00274                                    ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
00275                                    ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
00276                                    ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
00277                                    ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
00278                                    ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
00279                                    ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
00280                                    ((FLAG) == ETH_DMA_FLAG_T))
00281 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
00282 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
00283                                ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
00284                                ((IT) == ETH_MAC_IT_PMT))
00285 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
00286                                    ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
00287                                    ((FLAG) == ETH_MAC_FLAG_PMT))
00288 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
00289 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
00290                                ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
00291                                ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
00292                                ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
00293                                ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
00294                                ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
00295                                ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
00296                                ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
00297                                ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
00298 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
00299                                            ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
00300 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
00301                            ((IT) != 0x00U))
00302 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
00303                                ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
00304                                ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
00305 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
00306                                                 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
00307
00308 /**
00309   * @}
00310   */
00311
00312 /** @addtogroup ETH_Private_Defines
00313   * @{
00314   */
00315 /* Delay to wait when writing to some Ethernet registers */
00316 #define ETH_REG_WRITE_DELAY     0x00000001U
00317
00318 /* ETHERNET Errors */
00319 #define  ETH_SUCCESS            0U
00320 #define  ETH_ERROR              1U
00321
00322 /* ETHERNET DMA Tx descriptors Collision Count Shift */
00323 #define  ETH_DMATXDESC_COLLISION_COUNTSHIFT        3U
00324
00325 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
00326 #define  ETH_DMATXDESC_BUFFER2_SIZESHIFT           16U
00327
00328 /* ETHERNET DMA Rx descriptors Frame Length Shift */
00329 #define  ETH_DMARXDESC_FRAME_LENGTHSHIFT           16U
00330
00331 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
00332 #define  ETH_DMARXDESC_BUFFER2_SIZESHIFT           16U
00333
00334 /* ETHERNET DMA Rx descriptors Frame length Shift */
00335 #define  ETH_DMARXDESC_FRAMELENGTHSHIFT            16U
00336
00337 /* ETHERNET MAC address offsets */
00338 #define ETH_MAC_ADDR_HBASE    (uint32_t)(ETH_MAC_BASE + 0x40U)  /* ETHERNET MAC address high offset */
00339 #define ETH_MAC_ADDR_LBASE    (uint32_t)(ETH_MAC_BASE + 0x44U)  /* ETHERNET MAC address low offset */
00340
00341 /* ETHERNET MACMIIAR register Mask */
00342 #define ETH_MACMIIAR_CR_MASK    0xFFFFFFE3U
00343
00344 /* ETHERNET MACCR register Mask */
00345 #define ETH_MACCR_CLEAR_MASK    0xFF20810FU
00346
00347 /* ETHERNET MACFCR register Mask */
00348 #define ETH_MACFCR_CLEAR_MASK   0x0000FF41U
00349
00350 /* ETHERNET DMAOMR register Mask */
00351 #define ETH_DMAOMR_CLEAR_MASK   0xF8DE3F23U
00352
00353 /* ETHERNET Remote Wake-up frame register length */
00354 #define ETH_WAKEUP_REGISTER_LENGTH      8U
00355
00356 /* ETHERNET Missed frames counter Shift */
00357 #define  ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT     17U
00358  /**
00359   * @}
00360   */
00361
00362 /* Exported types ------------------------------------------------------------*/
00363 /** @defgroup ETH_Exported_Types ETH Exported Types
00364   * @{
00365   */
00366
00367 /**
00368   * @brief  HAL State structures definition
00369   */
00370 typedef enum
00371 {
00372   HAL_ETH_STATE_RESET             = 0x00U,    /*!< Peripheral not yet Initialized or disabled         */
00373   HAL_ETH_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00374   HAL_ETH_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                     */
00375   HAL_ETH_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing               */
00376   HAL_ETH_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing                  */
00377   HAL_ETH_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission and Reception process is ongoing */
00378   HAL_ETH_STATE_BUSY_WR           = 0x42U,    /*!< Write process is ongoing                           */
00379   HAL_ETH_STATE_BUSY_RD           = 0x82U,    /*!< Read process is ongoing                            */
00380   HAL_ETH_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                      */
00381   HAL_ETH_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                       */
00382 }HAL_ETH_StateTypeDef;
00383
00384 /**
00385   * @brief  ETH Init Structure definition
00386   */
00387
00388 typedef struct
00389 {
00390   uint32_t             AutoNegotiation;           /*!< Selects or not the AutoNegotiation mode for the external PHY
00391                                                            The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
00392                                                            and the mode (half/full-duplex).
00393                                                            This parameter can be a value of @ref ETH_AutoNegotiation */
00394
00395   uint32_t             Speed;                     /*!< Sets the Ethernet speed: 10/100 Mbps.
00396                                                            This parameter can be a value of @ref ETH_Speed */
00397
00398   uint32_t             DuplexMode;                /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
00399                                                            This parameter can be a value of @ref ETH_Duplex_Mode */
00400
00401   uint16_t             PhyAddress;                /*!< Ethernet PHY address.
00402                                                            This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
00403
00404   uint8_t             *MACAddr;                   /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
00405
00406   uint32_t             RxMode;                    /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
00407                                                            This parameter can be a value of @ref ETH_Rx_Mode */
00408
00409   uint32_t             ChecksumMode;              /*!< Selects if the checksum is check by hardware or by software.
00410                                                          This parameter can be a value of @ref ETH_Checksum_Mode */
00411
00412   uint32_t             MediaInterface;            /*!< Selects the media-independent interface or the reduced media-independent interface.
00413                                                          This parameter can be a value of @ref ETH_Media_Interface */
00414
00415 } ETH_InitTypeDef;
00416
00417
00418  /**
00419   * @brief  ETH MAC Configuration Structure definition
00420   */
00421
00422 typedef struct
00423 {
00424   uint32_t             Watchdog;                  /*!< Selects or not the Watchdog timer
00425                                                            When enabled, the MAC allows no more then 2048 bytes to be received.
00426                                                            When disabled, the MAC can receive up to 16384 bytes.
00427                                                            This parameter can be a value of @ref ETH_Watchdog */
00428
00429   uint32_t             Jabber;                    /*!< Selects or not Jabber timer
00430                                                            When enabled, the MAC allows no more then 2048 bytes to be sent.
00431                                                            When disabled, the MAC can send up to 16384 bytes.
00432                                                            This parameter can be a value of @ref ETH_Jabber */
00433
00434   uint32_t             InterFrameGap;             /*!< Selects the minimum IFG between frames during transmission.
00435                                                            This parameter can be a value of @ref ETH_Inter_Frame_Gap */
00436
00437   uint32_t             CarrierSense;              /*!< Selects or not the Carrier Sense.
00438                                                            This parameter can be a value of @ref ETH_Carrier_Sense */
00439
00440   uint32_t             ReceiveOwn;                /*!< Selects or not the ReceiveOwn,
00441                                                            ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
00442                                                            in Half-Duplex mode.
00443                                                            This parameter can be a value of @ref ETH_Receive_Own */
00444
00445   uint32_t             LoopbackMode;              /*!< Selects or not the internal MAC MII Loopback mode.
00446                                                            This parameter can be a value of @ref ETH_Loop_Back_Mode */
00447
00448   uint32_t             ChecksumOffload;           /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
00449                                                            This parameter can be a value of @ref ETH_Checksum_Offload */
00450
00451   uint32_t             RetryTransmission;         /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
00452                                                            when a collision occurs (Half-Duplex mode).
00453                                                            This parameter can be a value of @ref ETH_Retry_Transmission */
00454
00455   uint32_t             AutomaticPadCRCStrip;      /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
00456                                                            This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
00457
00458   uint32_t             BackOffLimit;              /*!< Selects the BackOff limit value.
00459                                                            This parameter can be a value of @ref ETH_Back_Off_Limit */
00460
00461   uint32_t             DeferralCheck;             /*!< Selects or not the deferral check function (Half-Duplex mode).
00462                                                            This parameter can be a value of @ref ETH_Deferral_Check */
00463
00464   uint32_t             ReceiveAll;                /*!< Selects or not all frames reception by the MAC (No filtering).
00465                                                            This parameter can be a value of @ref ETH_Receive_All */
00466
00467   uint32_t             SourceAddrFilter;          /*!< Selects the Source Address Filter mode.
00468                                                            This parameter can be a value of @ref ETH_Source_Addr_Filter */
00469
00470   uint32_t             PassControlFrames;         /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
00471                                                            This parameter can be a value of @ref ETH_Pass_Control_Frames */
00472
00473   uint32_t             BroadcastFramesReception;  /*!< Selects or not the reception of Broadcast Frames.
00474                                                            This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
00475
00476   uint32_t             DestinationAddrFilter;     /*!< Sets the destination filter mode for both unicast and multicast frames.
00477                                                            This parameter can be a value of @ref ETH_Destination_Addr_Filter */
00478
00479   uint32_t             PromiscuousMode;           /*!< Selects or not the Promiscuous Mode
00480                                                            This parameter can be a value of @ref ETH_Promiscuous_Mode */
00481
00482   uint32_t             MulticastFramesFilter;     /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
00483                                                            This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
00484
00485   uint32_t             UnicastFramesFilter;       /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
00486                                                            This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
00487
00488   uint32_t             HashTableHigh;             /*!< This field holds the higher 32 bits of Hash table.
00489                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
00490
00491   uint32_t             HashTableLow;              /*!< This field holds the lower 32 bits of Hash table.
00492                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU  */
00493
00494   uint32_t             PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
00495                                                            This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
00496
00497   uint32_t             ZeroQuantaPause;           /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
00498                                                            This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
00499
00500   uint32_t             PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for
00501                                                            automatic retransmission of PAUSE Frame.
00502                                                            This parameter can be a value of @ref ETH_Pause_Low_Threshold */
00503
00504   uint32_t             UnicastPauseFrameDetect;   /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
00505                                                            unicast address and unique multicast address).
00506                                                            This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
00507
00508   uint32_t             ReceiveFlowControl;        /*!< Enables or disables the MAC to decode the received Pause frame and
00509                                                            disable its transmitter for a specified time (Pause Time)
00510                                                            This parameter can be a value of @ref ETH_Receive_Flow_Control */
00511
00512   uint32_t             TransmitFlowControl;       /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
00513                                                            or the MAC back-pressure operation (Half-Duplex mode)
00514                                                            This parameter can be a value of @ref ETH_Transmit_Flow_Control */
00515
00516   uint32_t             VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
00517                                                            comparison and filtering.
00518                                                            This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
00519
00520   uint32_t             VLANTagIdentifier;         /*!< Holds the VLAN tag identifier for receive frames */
00521
00522 } ETH_MACInitTypeDef;
00523
00524 /**
00525   * @brief  ETH DMA Configuration Structure definition
00526   */
00527
00528 typedef struct
00529 {
00530  uint32_t              DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
00531                                                              This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
00532
00533   uint32_t             ReceiveStoreForward;         /*!< Enables or disables the Receive store and forward mode.
00534                                                              This parameter can be a value of @ref ETH_Receive_Store_Forward */
00535
00536   uint32_t             FlushReceivedFrame;          /*!< Enables or disables the flushing of received frames.
00537                                                              This parameter can be a value of @ref ETH_Flush_Received_Frame */
00538
00539   uint32_t             TransmitStoreForward;        /*!< Enables or disables Transmit store and forward mode.
00540                                                              This parameter can be a value of @ref ETH_Transmit_Store_Forward */
00541
00542   uint32_t             TransmitThresholdControl;    /*!< Selects or not the Transmit Threshold Control.
00543                                                              This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
00544
00545   uint32_t             ForwardErrorFrames;          /*!< Selects or not the forward to the DMA of erroneous frames.
00546                                                              This parameter can be a value of @ref ETH_Forward_Error_Frames */
00547
00548   uint32_t             ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
00549                                                              and length less than 64 bytes) including pad-bytes and CRC)
00550                                                              This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
00551
00552   uint32_t             ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO.
00553                                                              This parameter can be a value of @ref ETH_Receive_Threshold_Control */
00554
00555   uint32_t             SecondFrameOperate;          /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
00556                                                              frame of Transmit data even before obtaining the status for the first frame.
00557                                                              This parameter can be a value of @ref ETH_Second_Frame_Operate */
00558
00559   uint32_t             AddressAlignedBeats;         /*!< Enables or disables the Address Aligned Beats.
00560                                                              This parameter can be a value of @ref ETH_Address_Aligned_Beats */
00561
00562   uint32_t             FixedBurst;                  /*!< Enables or disables the AHB Master interface fixed burst transfers.
00563                                                              This parameter can be a value of @ref ETH_Fixed_Burst */
00564
00565   uint32_t             RxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
00566                                                              This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
00567
00568   uint32_t             TxDMABurstLength;            /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
00569                                                              This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
00570
00571   uint32_t             DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
00572                                                              This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
00573
00574   uint32_t             DMAArbitration;              /*!< Selects the DMA Tx/Rx arbitration.
00575                                                              This parameter can be a value of @ref ETH_DMA_Arbitration */
00576 } ETH_DMAInitTypeDef;
00577
00578
00579 /**
00580   * @brief  ETH DMA Descriptors data structure definition
00581   */
00582
00583 typedef struct
00584 {
00585   __IO uint32_t   Status;           /*!< Status */
00586
00587   uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */
00588
00589   uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */
00590
00591   uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */
00592
00593 } ETH_DMADescTypeDef;
00594
00595 /**
00596   * @brief  Received Frame Informations structure definition
00597   */
00598 typedef struct
00599 {
00600   ETH_DMADescTypeDef *FSRxDesc;          /*!< First Segment Rx Desc */
00601
00602   ETH_DMADescTypeDef *LSRxDesc;          /*!< Last Segment Rx Desc */
00603
00604   uint32_t  SegCount;                    /*!< Segment count */
00605
00606   uint32_t length;                       /*!< Frame length */
00607
00608   uint32_t buffer;                       /*!< Frame buffer */
00609
00610 } ETH_DMARxFrameInfos;
00611
00612 /**
00613   * @brief  ETH Handle Structure definition
00614   */
00615
00616 typedef struct
00617 {
00618   ETH_TypeDef                *Instance;     /*!< Register base address       */
00619
00620   ETH_InitTypeDef            Init;          /*!< Ethernet Init Configuration */
00621
00622   uint32_t                   LinkStatus;    /*!< Ethernet link status        */
00623
00624   ETH_DMADescTypeDef         *RxDesc;       /*!< Rx descriptor to Get        */
00625
00626   ETH_DMADescTypeDef         *TxDesc;       /*!< Tx descriptor to Set        */
00627
00628   ETH_DMARxFrameInfos        RxFrameInfos;  /*!< last Rx frame infos         */
00629
00630   __IO HAL_ETH_StateTypeDef  State;         /*!< ETH communication state     */
00631
00632   HAL_LockTypeDef            Lock;          /*!< ETH Lock                    */
00633
00634 } ETH_HandleTypeDef;
00635
00636  /**
00637   * @}
00638   */
00639
00640 /* Exported constants --------------------------------------------------------*/
00641 /** @defgroup ETH_Exported_Constants ETH Exported Constants
00642   * @{
00643   */
00644
00645 /** @defgroup ETH_Buffers_setting ETH Buffers setting
00646   * @{
00647   */
00648 #define ETH_MAX_PACKET_SIZE       1524U    /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
00649 #define ETH_HEADER                14U      /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
00650 #define ETH_CRC                   4U       /*!< Ethernet CRC */
00651 #define ETH_EXTRA                 2U       /*!< Extra bytes in some cases */
00652 #define ETH_VLAN_TAG              4U       /*!< optional 802.1q VLAN Tag */
00653 #define ETH_MIN_ETH_PAYLOAD       46U      /*!< Minimum Ethernet payload size */
00654 #define ETH_MAX_ETH_PAYLOAD       1500U    /*!< Maximum Ethernet payload size */
00655 #define ETH_JUMBO_FRAME_PAYLOAD   9000U    /*!< Jumbo frame payload size */
00656
00657  /* Ethernet driver receive buffers are organized in a chained linked-list, when
00658     an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
00659     to the driver receive buffers memory.
00660
00661     Depending on the size of the received ethernet packet and the size of
00662     each ethernet driver receive buffer, the received packet can take one or more
00663     ethernet driver receive buffer.
00664
00665     In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
00666     and the total count of the driver receive buffers ETH_RXBUFNB.
00667
00668     The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
00669     example, they can be reconfigured in the application layer to fit the application
00670     needs */
00671
00672 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
00673    packet */
00674 #ifndef ETH_RX_BUF_SIZE
00675  #define ETH_RX_BUF_SIZE         ETH_MAX_PACKET_SIZE
00676 #endif
00677
00678 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
00679 #ifndef ETH_RXBUFNB
00680  #define ETH_RXBUFNB             5U     /*  5 Rx buffers of size ETH_RX_BUF_SIZE */
00681 #endif
00682
00683
00684  /* Ethernet driver transmit buffers are organized in a chained linked-list, when
00685     an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
00686     driver transmit buffers memory to the TxFIFO.
00687
00688     Depending on the size of the Ethernet packet to be transmitted and the size of
00689     each ethernet driver transmit buffer, the packet to be transmitted can take
00690     one or more ethernet driver transmit buffer.
00691
00692     In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
00693     and the total count of the driver transmit buffers ETH_TXBUFNB.
00694
00695     The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
00696     example, they can be reconfigured in the application layer to fit the application
00697     needs */
00698
00699 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
00700    packet */
00701 #ifndef ETH_TX_BUF_SIZE
00702  #define ETH_TX_BUF_SIZE         ETH_MAX_PACKET_SIZE
00703 #endif
00704
00705 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
00706 #ifndef ETH_TXBUFNB
00707  #define ETH_TXBUFNB             5U      /* 5  Tx buffers of size ETH_TX_BUF_SIZE */
00708 #endif
00709
00710  /**
00711   * @}
00712   */
00713
00714 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
00715   * @{
00716   */
00717
00718 /*
00719    DMA Tx Descriptor
00720   -----------------------------------------------------------------------------------------------
00721   TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
00722   -----------------------------------------------------------------------------------------------
00723   TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
00724   -----------------------------------------------------------------------------------------------
00725   TDES2 |                         Buffer1 Address [31:0]                                         |
00726   -----------------------------------------------------------------------------------------------
00727   TDES3 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
00728   -----------------------------------------------------------------------------------------------
00729 */
00730
00731 /**
00732   * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register
00733   */
00734 #define ETH_DMATXDESC_OWN                     0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
00735 #define ETH_DMATXDESC_IC                      0x40000000U  /*!< Interrupt on Completion */
00736 #define ETH_DMATXDESC_LS                      0x20000000U  /*!< Last Segment */
00737 #define ETH_DMATXDESC_FS                      0x10000000U  /*!< First Segment */
00738 #define ETH_DMATXDESC_DC                      0x08000000U  /*!< Disable CRC */
00739 #define ETH_DMATXDESC_DP                      0x04000000U  /*!< Disable Padding */
00740 #define ETH_DMATXDESC_TTSE                    0x02000000U  /*!< Transmit Time Stamp Enable */
00741 #define ETH_DMATXDESC_CIC                     0x00C00000U  /*!< Checksum Insertion Control: 4 cases */
00742 #define ETH_DMATXDESC_CIC_BYPASS              0x00000000U  /*!< Do Nothing: Checksum Engine is bypassed */
00743 #define ETH_DMATXDESC_CIC_IPV4HEADER          0x00400000U  /*!< IPV4 header Checksum Insertion */
00744 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT  0x00800000U  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
00745 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL     0x00C00000U  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
00746 #define ETH_DMATXDESC_TER                     0x00200000U  /*!< Transmit End of Ring */
00747 #define ETH_DMATXDESC_TCH                     0x00100000U  /*!< Second Address Chained */
00748 #define ETH_DMATXDESC_TTSS                    0x00020000U  /*!< Tx Time Stamp Status */
00749 #define ETH_DMATXDESC_IHE                     0x00010000U  /*!< IP Header Error */
00750 #define ETH_DMATXDESC_ES                      0x00008000U  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
00751 #define ETH_DMATXDESC_JT                      0x00004000U  /*!< Jabber Timeout */
00752 #define ETH_DMATXDESC_FF                      0x00002000U  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
00753 #define ETH_DMATXDESC_PCE                     0x00001000U  /*!< Payload Checksum Error */
00754 #define ETH_DMATXDESC_LCA                     0x00000800U  /*!< Loss of Carrier: carrier lost during transmission */
00755 #define ETH_DMATXDESC_NC                      0x00000400U  /*!< No Carrier: no carrier signal from the transceiver */
00756 #define ETH_DMATXDESC_LCO                     0x00000200U  /*!< Late Collision: transmission aborted due to collision */
00757 #define ETH_DMATXDESC_EC                      0x00000100U  /*!< Excessive Collision: transmission aborted after 16 collisions */
00758 #define ETH_DMATXDESC_VF                      0x00000080U  /*!< VLAN Frame */
00759 #define ETH_DMATXDESC_CC                      0x00000078U  /*!< Collision Count */
00760 #define ETH_DMATXDESC_ED                      0x00000004U  /*!< Excessive Deferral */
00761 #define ETH_DMATXDESC_UF                      0x00000002U  /*!< Underflow Error: late data arrival from the memory */
00762 #define ETH_DMATXDESC_DB                      0x00000001U  /*!< Deferred Bit */
00763
00764 /**
00765   * @brief  Bit definition of TDES1 register
00766   */
00767 #define ETH_DMATXDESC_TBS2  0x1FFF0000U  /*!< Transmit Buffer2 Size */
00768 #define ETH_DMATXDESC_TBS1  0x00001FFFU  /*!< Transmit Buffer1 Size */
00769
00770 /**
00771   * @brief  Bit definition of TDES2 register
00772   */
00773 #define ETH_DMATXDESC_B1AP  0xFFFFFFFFU  /*!< Buffer1 Address Pointer */
00774
00775 /**
00776   * @brief  Bit definition of TDES3 register
00777   */
00778 #define ETH_DMATXDESC_B2AP  0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
00779
00780 /**
00781   * @}
00782   */
00783 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
00784   * @{
00785   */
00786
00787 /*
00788   DMA Rx Descriptor
00789   --------------------------------------------------------------------------------------------------------------------
00790   RDES0 | OWN(31) |                                             Status [30:0]                                          |
00791   ---------------------------------------------------------------------------------------------------------------------
00792   RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
00793   ---------------------------------------------------------------------------------------------------------------------
00794   RDES2 |                                       Buffer1 Address [31:0]                                                 |
00795   ---------------------------------------------------------------------------------------------------------------------
00796   RDES3 |                          Buffer2 Address [31:0] / Next Descriptor Address [31:0]                             |
00797   ---------------------------------------------------------------------------------------------------------------------
00798 */
00799
00800 /**
00801   * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register
00802   */
00803 #define ETH_DMARXDESC_OWN         0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine  */
00804 #define ETH_DMARXDESC_AFM         0x40000000U  /*!< DA Filter Fail for the rx frame  */
00805 #define ETH_DMARXDESC_FL          0x3FFF0000U  /*!< Receive descriptor frame length  */
00806 #define ETH_DMARXDESC_ES          0x00008000U  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
00807 #define ETH_DMARXDESC_DE          0x00004000U  /*!< Descriptor error: no more descriptors for receive frame  */
00808 #define ETH_DMARXDESC_SAF         0x00002000U  /*!< SA Filter Fail for the received frame */
00809 #define ETH_DMARXDESC_LE          0x00001000U  /*!< Frame size not matching with length field */
00810 #define ETH_DMARXDESC_OE          0x00000800U  /*!< Overflow Error: Frame was damaged due to buffer overflow */
00811 #define ETH_DMARXDESC_VLAN        0x00000400U  /*!< VLAN Tag: received frame is a VLAN frame */
00812 #define ETH_DMARXDESC_FS          0x00000200U  /*!< First descriptor of the frame  */
00813 #define ETH_DMARXDESC_LS          0x00000100U  /*!< Last descriptor of the frame  */
00814 #define ETH_DMARXDESC_IPV4HCE     0x00000080U  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */
00815 #define ETH_DMARXDESC_LC          0x00000040U  /*!< Late collision occurred during reception   */
00816 #define ETH_DMARXDESC_FT          0x00000020U  /*!< Frame type - Ethernet, otherwise 802.3    */
00817 #define ETH_DMARXDESC_RWT         0x00000010U  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */
00818 #define ETH_DMARXDESC_RE          0x00000008U  /*!< Receive error: error reported by MII interface  */
00819 #define ETH_DMARXDESC_DBE         0x00000004U  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */
00820 #define ETH_DMARXDESC_CE          0x00000002U  /*!< CRC error */
00821 #define ETH_DMARXDESC_MAMPCE      0x00000001U  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
00822
00823 /**
00824   * @brief  Bit definition of RDES1 register
00825   */
00826 #define ETH_DMARXDESC_DIC   0x80000000U  /*!< Disable Interrupt on Completion */
00827 #define ETH_DMARXDESC_RBS2  0x1FFF0000U  /*!< Receive Buffer2 Size */
00828 #define ETH_DMARXDESC_RER   0x00008000U  /*!< Receive End of Ring */
00829 #define ETH_DMARXDESC_RCH   0x00004000U  /*!< Second Address Chained */
00830 #define ETH_DMARXDESC_RBS1  0x00001FFFU  /*!< Receive Buffer1 Size */
00831
00832 /**
00833   * @brief  Bit definition of RDES2 register
00834   */
00835 #define ETH_DMARXDESC_B1AP  0xFFFFFFFFU  /*!< Buffer1 Address Pointer */
00836
00837 /**
00838   * @brief  Bit definition of RDES3 register
00839   */
00840 #define ETH_DMARXDESC_B2AP  0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
00841
00842 /**
00843   * @}
00844   */
00845  /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
00846   * @{
00847   */
00848 #define ETH_AUTONEGOTIATION_ENABLE     0x00000001U
00849 #define ETH_AUTONEGOTIATION_DISABLE    0x00000000U
00850
00851 /**
00852   * @}
00853   */
00854 /** @defgroup ETH_Speed ETH Speed
00855   * @{
00856   */
00857 #define ETH_SPEED_10M        0x00000000U
00858 #define ETH_SPEED_100M       0x00004000U
00859
00860 /**
00861   * @}
00862   */
00863 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
00864   * @{
00865   */
00866 #define ETH_MODE_FULLDUPLEX       0x00000800U
00867 #define ETH_MODE_HALFDUPLEX       0x00000000U
00868 /**
00869   * @}
00870   */
00871 /** @defgroup ETH_Rx_Mode ETH Rx Mode
00872   * @{
00873   */
00874 #define ETH_RXPOLLING_MODE      0x00000000U
00875 #define ETH_RXINTERRUPT_MODE    0x00000001U
00876 /**
00877   * @}
00878   */
00879
00880 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
00881   * @{
00882   */
00883 #define ETH_CHECKSUM_BY_HARDWARE      0x00000000U
00884 #define ETH_CHECKSUM_BY_SOFTWARE      0x00000001U
00885 /**
00886   * @}
00887   */
00888
00889 /** @defgroup ETH_Media_Interface ETH Media Interface
00890   * @{
00891   */
00892 #define ETH_MEDIA_INTERFACE_MII       0x00000000U
00893 #define ETH_MEDIA_INTERFACE_RMII      ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
00894
00895 /**
00896   * @}
00897   */
00898
00899 /** @defgroup ETH_Watchdog ETH Watchdog
00900   * @{
00901   */
00902 #define ETH_WATCHDOG_ENABLE       0x00000000U
00903 #define ETH_WATCHDOG_DISABLE      0x00800000U
00904 /**
00905   * @}
00906   */
00907
00908 /** @defgroup ETH_Jabber ETH Jabber
00909   * @{
00910   */
00911 #define ETH_JABBER_ENABLE    0x00000000U
00912 #define ETH_JABBER_DISABLE   0x00400000U
00913 /**
00914   * @}
00915   */
00916
00917 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
00918   * @{
00919   */
00920 #define ETH_INTERFRAMEGAP_96BIT   0x00000000U  /*!< minimum IFG between frames during transmission is 96Bit */
00921 #define ETH_INTERFRAMEGAP_88BIT   0x00020000U  /*!< minimum IFG between frames during transmission is 88Bit */
00922 #define ETH_INTERFRAMEGAP_80BIT   0x00040000U  /*!< minimum IFG between frames during transmission is 80Bit */
00923 #define ETH_INTERFRAMEGAP_72BIT   0x00060000U  /*!< minimum IFG between frames during transmission is 72Bit */
00924 #define ETH_INTERFRAMEGAP_64BIT   0x00080000U  /*!< minimum IFG between frames during transmission is 64Bit */
00925 #define ETH_INTERFRAMEGAP_56BIT   0x000A0000U  /*!< minimum IFG between frames during transmission is 56Bit */
00926 #define ETH_INTERFRAMEGAP_48BIT   0x000C0000U  /*!< minimum IFG between frames during transmission is 48Bit */
00927 #define ETH_INTERFRAMEGAP_40BIT   0x000E0000U  /*!< minimum IFG between frames during transmission is 40Bit */
00928 /**
00929   * @}
00930   */
00931
00932 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
00933   * @{
00934   */
00935 #define ETH_CARRIERSENCE_ENABLE   0x00000000U
00936 #define ETH_CARRIERSENCE_DISABLE  0x00010000U
00937 /**
00938   * @}
00939   */
00940
00941 /** @defgroup ETH_Receive_Own ETH Receive Own
00942   * @{
00943   */
00944 #define ETH_RECEIVEOWN_ENABLE     0x00000000U
00945 #define ETH_RECEIVEOWN_DISABLE    0x00002000U
00946 /**
00947   * @}
00948   */
00949
00950 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
00951   * @{
00952   */
00953 #define ETH_LOOPBACKMODE_ENABLE        0x00001000U
00954 #define ETH_LOOPBACKMODE_DISABLE       0x00000000U
00955 /**
00956   * @}
00957   */
00958
00959 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
00960   * @{
00961   */
00962 #define ETH_CHECKSUMOFFLAOD_ENABLE     0x00000400U
00963 #define ETH_CHECKSUMOFFLAOD_DISABLE    0x00000000U
00964 /**
00965   * @}
00966   */
00967
00968 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
00969   * @{
00970   */
00971 #define ETH_RETRYTRANSMISSION_ENABLE   0x00000000U
00972 #define ETH_RETRYTRANSMISSION_DISABLE  0x00000200U
00973 /**
00974   * @}
00975   */
00976
00977 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
00978   * @{
00979   */
00980 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE     0x00000080U
00981 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE    0x00000000U
00982 /**
00983   * @}
00984   */
00985
00986 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
00987   * @{
00988   */
00989 #define ETH_BACKOFFLIMIT_10  0x00000000U
00990 #define ETH_BACKOFFLIMIT_8   0x00000020U
00991 #define ETH_BACKOFFLIMIT_4   0x00000040U
00992 #define ETH_BACKOFFLIMIT_1   0x00000060U
00993 /**
00994   * @}
00995   */
00996
00997 /** @defgroup ETH_Deferral_Check ETH Deferral Check
00998   * @{
00999   */
01000 #define ETH_DEFFERRALCHECK_ENABLE       0x00000010U
01001 #define ETH_DEFFERRALCHECK_DISABLE      0x00000000U
01002 /**
01003   * @}
01004   */
01005
01006 /** @defgroup ETH_Receive_All ETH Receive All
01007   * @{
01008   */
01009 #define ETH_RECEIVEALL_ENABLE     0x80000000U
01010 #define ETH_RECEIVEAll_DISABLE    0x00000000U
01011 /**
01012   * @}
01013   */
01014
01015 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
01016   * @{
01017   */
01018 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE       0x00000200U
01019 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE      0x00000300U
01020 #define ETH_SOURCEADDRFILTER_DISABLE             0x00000000U
01021 /**
01022   * @}
01023   */
01024
01025 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
01026   * @{
01027   */
01028 #define ETH_PASSCONTROLFRAMES_BLOCKALL                0x00000040U  /*!< MAC filters all control frames from reaching the application */
01029 #define ETH_PASSCONTROLFRAMES_FORWARDALL              0x00000080U  /*!< MAC forwards all control frames to application even if they fail the Address Filter */
01030 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U  /*!< MAC forwards control frames that pass the Address Filter. */
01031 /**
01032   * @}
01033   */
01034
01035 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
01036   * @{
01037   */
01038 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE     0x00000000U
01039 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE    0x00000020U
01040 /**
01041   * @}
01042   */
01043
01044 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
01045   * @{
01046   */
01047 #define ETH_DESTINATIONADDRFILTER_NORMAL    0x00000000U
01048 #define ETH_DESTINATIONADDRFILTER_INVERSE   0x00000008U
01049 /**
01050   * @}
01051   */
01052
01053 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
01054   * @{
01055   */
01056 #define ETH_PROMISCUOUS_MODE_ENABLE     0x00000001U
01057 #define ETH_PROMISCUOUS_MODE_DISABLE    0x00000000U
01058 /**
01059   * @}
01060   */
01061
01062 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
01063   * @{
01064   */
01065 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE    0x00000404U
01066 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE           0x00000004U
01067 #define ETH_MULTICASTFRAMESFILTER_PERFECT             0x00000000U
01068 #define ETH_MULTICASTFRAMESFILTER_NONE                0x00000010U
01069 /**
01070   * @}
01071   */
01072
01073 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
01074   * @{
01075   */
01076 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
01077 #define ETH_UNICASTFRAMESFILTER_HASHTABLE        0x00000002U
01078 #define ETH_UNICASTFRAMESFILTER_PERFECT          0x00000000U
01079 /**
01080   * @}
01081   */
01082
01083 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
01084   * @{
01085   */
01086 #define ETH_ZEROQUANTAPAUSE_ENABLE     0x00000000U
01087 #define ETH_ZEROQUANTAPAUSE_DISABLE    0x00000080U
01088 /**
01089   * @}
01090   */
01091
01092 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
01093   * @{
01094   */
01095 #define ETH_PAUSELOWTHRESHOLD_MINUS4        0x00000000U  /*!< Pause time minus 4 slot times */
01096 #define ETH_PAUSELOWTHRESHOLD_MINUS28       0x00000010U  /*!< Pause time minus 28 slot times */
01097 #define ETH_PAUSELOWTHRESHOLD_MINUS144      0x00000020U  /*!< Pause time minus 144 slot times */
01098 #define ETH_PAUSELOWTHRESHOLD_MINUS256      0x00000030U  /*!< Pause time minus 256 slot times */
01099 /**
01100   * @}
01101   */
01102
01103 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
01104   * @{
01105   */
01106 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE  0x00000008U
01107 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
01108 /**
01109   * @}
01110   */
01111
01112 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
01113   * @{
01114   */
01115 #define ETH_RECEIVEFLOWCONTROL_ENABLE       0x00000004U
01116 #define ETH_RECEIVEFLOWCONTROL_DISABLE      0x00000000U
01117 /**
01118   * @}
01119   */
01120
01121 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
01122   * @{
01123   */
01124 #define ETH_TRANSMITFLOWCONTROL_ENABLE      0x00000002U
01125 #define ETH_TRANSMITFLOWCONTROL_DISABLE     0x00000000U
01126 /**
01127   * @}
01128   */
01129
01130 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
01131   * @{
01132   */
01133 #define ETH_VLANTAGCOMPARISON_12BIT    0x00010000U
01134 #define ETH_VLANTAGCOMPARISON_16BIT    0x00000000U
01135 /**
01136   * @}
01137   */
01138
01139 /** @defgroup ETH_MAC_addresses ETH MAC addresses
01140   * @{
01141   */
01142 #define ETH_MAC_ADDRESS0     0x00000000U
01143 #define ETH_MAC_ADDRESS1     0x00000008U
01144 #define ETH_MAC_ADDRESS2     0x00000010U
01145 #define ETH_MAC_ADDRESS3     0x00000018U
01146 /**
01147   * @}
01148   */
01149
01150 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
01151   * @{
01152   */
01153 #define ETH_MAC_ADDRESSFILTER_SA       0x00000000U
01154 #define ETH_MAC_ADDRESSFILTER_DA       0x00000008U
01155 /**
01156   * @}
01157   */
01158
01159 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
01160   * @{
01161   */
01162 #define ETH_MAC_ADDRESSMASK_BYTE6      0x20000000U  /*!< Mask MAC Address high reg bits [15:8] */
01163 #define ETH_MAC_ADDRESSMASK_BYTE5      0x10000000U  /*!< Mask MAC Address high reg bits [7:0] */
01164 #define ETH_MAC_ADDRESSMASK_BYTE4      0x08000000U  /*!< Mask MAC Address low reg bits [31:24] */
01165 #define ETH_MAC_ADDRESSMASK_BYTE3      0x04000000U  /*!< Mask MAC Address low reg bits [23:16] */
01166 #define ETH_MAC_ADDRESSMASK_BYTE2      0x02000000U  /*!< Mask MAC Address low reg bits [15:8] */
01167 #define ETH_MAC_ADDRESSMASK_BYTE1      0x01000000U  /*!< Mask MAC Address low reg bits [70] */
01168 /**
01169   * @}
01170   */
01171
01172 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
01173   * @{
01174   */
01175 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE   0x00000000U
01176 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE  0x04000000U
01177 /**
01178   * @}
01179   */
01180
01181 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
01182   * @{
01183   */
01184 #define ETH_RECEIVESTOREFORWARD_ENABLE      0x02000000U
01185 #define ETH_RECEIVESTOREFORWARD_DISABLE     0x00000000U
01186 /**
01187   * @}
01188   */
01189
01190 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
01191   * @{
01192   */
01193 #define ETH_FLUSHRECEIVEDFRAME_ENABLE       0x00000000U
01194 #define ETH_FLUSHRECEIVEDFRAME_DISABLE      0x01000000U
01195 /**
01196   * @}
01197   */
01198
01199 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
01200   * @{
01201   */
01202 #define ETH_TRANSMITSTOREFORWARD_ENABLE     0x00200000U
01203 #define ETH_TRANSMITSTOREFORWARD_DISABLE    0x00000000U
01204 /**
01205   * @}
01206   */
01207
01208 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
01209   * @{
01210   */
01211 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES     0x00000000U  /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
01212 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES    0x00004000U  /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
01213 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES    0x00008000U  /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
01214 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES    0x0000C000U  /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
01215 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES     0x00010000U  /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
01216 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES     0x00014000U  /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
01217 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES     0x00018000U  /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
01218 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES     0x0001C000U  /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
01219 /**
01220   * @}
01221   */
01222
01223 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
01224   * @{
01225   */
01226 #define ETH_FORWARDERRORFRAMES_ENABLE       0x00000080U
01227 #define ETH_FORWARDERRORFRAMES_DISABLE      0x00000000U
01228 /**
01229   * @}
01230   */
01231
01232 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
01233   * @{
01234   */
01235 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE   0x00000040U
01236 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE  0x00000000U
01237 /**
01238   * @}
01239   */
01240
01241 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
01242   * @{
01243   */
01244 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES      0x00000000U  /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
01245 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES      0x00000008U  /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
01246 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES      0x00000010U  /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
01247 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES     0x00000018U  /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
01248 /**
01249   * @}
01250   */
01251
01252 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
01253   * @{
01254   */
01255 #define ETH_SECONDFRAMEOPERARTE_ENABLE       0x00000004U
01256 #define ETH_SECONDFRAMEOPERARTE_DISABLE      0x00000000U
01257 /**
01258   * @}
01259   */
01260
01261 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
01262   * @{
01263   */
01264 #define ETH_ADDRESSALIGNEDBEATS_ENABLE      0x02000000U
01265 #define ETH_ADDRESSALIGNEDBEATS_DISABLE     0x00000000U
01266 /**
01267   * @}
01268   */
01269
01270 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
01271   * @{
01272   */
01273 #define ETH_FIXEDBURST_ENABLE     0x00010000U
01274 #define ETH_FIXEDBURST_DISABLE    0x00000000U
01275 /**
01276   * @}
01277   */
01278
01279 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
01280   * @{
01281   */
01282 #define ETH_RXDMABURSTLENGTH_1BEAT          0x00020000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
01283 #define ETH_RXDMABURSTLENGTH_2BEAT          0x00040000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
01284 #define ETH_RXDMABURSTLENGTH_4BEAT          0x00080000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
01285 #define ETH_RXDMABURSTLENGTH_8BEAT          0x00100000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
01286 #define ETH_RXDMABURSTLENGTH_16BEAT         0x00200000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
01287 #define ETH_RXDMABURSTLENGTH_32BEAT         0x00400000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
01288 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT    0x01020000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
01289 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT    0x01040000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
01290 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT   0x01080000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
01291 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT   0x01100000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
01292 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT   0x01200000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
01293 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT  0x01400000U  /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
01294 /**
01295   * @}
01296   */
01297
01298 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
01299   * @{
01300   */
01301 #define ETH_TXDMABURSTLENGTH_1BEAT          0x00000100U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
01302 #define ETH_TXDMABURSTLENGTH_2BEAT          0x00000200U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
01303 #define ETH_TXDMABURSTLENGTH_4BEAT          0x00000400U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
01304 #define ETH_TXDMABURSTLENGTH_8BEAT          0x00000800U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
01305 #define ETH_TXDMABURSTLENGTH_16BEAT         0x00001000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
01306 #define ETH_TXDMABURSTLENGTH_32BEAT         0x00002000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
01307 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT    0x01000100U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
01308 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT    0x01000200U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
01309 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT   0x01000400U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
01310 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT   0x01000800U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
01311 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT   0x01001000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
01312 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT  0x01002000U  /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
01313
01314 /**
01315   * @}
01316   */
01317
01318 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
01319   * @{
01320   */
01321 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1   0x00000000U
01322 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1   0x00004000U
01323 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1   0x00008000U
01324 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1   0x0000C000U
01325 #define ETH_DMAARBITRATION_RXPRIORTX             0x00000002U
01326 /**
01327   * @}
01328   */
01329
01330 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
01331   * @{
01332   */
01333 #define ETH_DMATXDESC_LASTSEGMENTS      0x40000000U  /*!< Last Segment */
01334 #define ETH_DMATXDESC_FIRSTSEGMENT      0x20000000U  /*!< First Segment */
01335 /**
01336   * @}
01337   */
01338
01339 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
01340   * @{
01341   */
01342 #define ETH_DMATXDESC_CHECKSUMBYPASS             0x00000000U   /*!< Checksum engine bypass */
01343 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER         0x00400000U   /*!< IPv4 header checksum insertion  */
01344 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT  0x00800000U   /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
01345 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL     0x00C00000U   /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
01346 /**
01347   * @}
01348   */
01349
01350 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
01351   * @{
01352   */
01353 #define ETH_DMARXDESC_BUFFER1     0x00000000U  /*!< DMA Rx Desc Buffer1 */
01354 #define ETH_DMARXDESC_BUFFER2     0x00000001U  /*!< DMA Rx Desc Buffer2 */
01355 /**
01356   * @}
01357   */
01358
01359 /** @defgroup ETH_PMT_Flags ETH PMT Flags
01360   * @{
01361   */
01362 #define ETH_PMT_FLAG_WUFFRPR      0x80000000U  /*!< Wake-Up Frame Filter Register Pointer Reset */
01363 #define ETH_PMT_FLAG_WUFR         0x00000040U  /*!< Wake-Up Frame Received */
01364 #define ETH_PMT_FLAG_MPR          0x00000020U  /*!< Magic Packet Received */
01365 /**
01366   * @}
01367   */
01368
01369 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
01370   * @{
01371   */
01372 #define ETH_MMC_IT_TGF       0x00200000U  /*!< When Tx good frame counter reaches half the maximum value */
01373 #define ETH_MMC_IT_TGFMSC    0x00008000U  /*!< When Tx good multi col counter reaches half the maximum value */
01374 #define ETH_MMC_IT_TGFSC     0x00004000U  /*!< When Tx good single col counter reaches half the maximum value */
01375 /**
01376   * @}
01377   */
01378
01379 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
01380   * @{
01381   */
01382 #define ETH_MMC_IT_RGUF      0x10020000U  /*!< When Rx good unicast frames counter reaches half the maximum value */
01383 #define ETH_MMC_IT_RFAE      0x10000040U  /*!< When Rx alignment error counter reaches half the maximum value */
01384 #define ETH_MMC_IT_RFCE      0x10000020U  /*!< When Rx crc error counter reaches half the maximum value */
01385 /**
01386   * @}
01387   */
01388
01389 /** @defgroup ETH_MAC_Flags ETH MAC Flags
01390   * @{
01391   */
01392 #define ETH_MAC_FLAG_TST     0x00000200U  /*!< Time stamp trigger flag (on MAC) */
01393 #define ETH_MAC_FLAG_MMCT    0x00000040U  /*!< MMC transmit flag  */
01394 #define ETH_MAC_FLAG_MMCR    0x00000020U  /*!< MMC receive flag */
01395 #define ETH_MAC_FLAG_MMC     0x00000010U  /*!< MMC flag (on MAC) */
01396 #define ETH_MAC_FLAG_PMT     0x00000008U  /*!< PMT flag (on MAC) */
01397 /**
01398   * @}
01399   */
01400
01401 /** @defgroup ETH_DMA_Flags ETH DMA Flags
01402   * @{
01403   */
01404 #define ETH_DMA_FLAG_TST               0x20000000U  /*!< Time-stamp trigger interrupt (on DMA) */
01405 #define ETH_DMA_FLAG_PMT               0x10000000U  /*!< PMT interrupt (on DMA) */
01406 #define ETH_DMA_FLAG_MMC               0x08000000U  /*!< MMC interrupt (on DMA) */
01407 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U  /*!< Error bits 0-Rx DMA, 1-Tx DMA */
01408 #define ETH_DMA_FLAG_READWRITEERROR    0x01000000U  /*!< Error bits 0-write transfer, 1-read transfer */
01409 #define ETH_DMA_FLAG_ACCESSERROR       0x02000000U  /*!< Error bits 0-data buffer, 1-desc. access */
01410 #define ETH_DMA_FLAG_NIS               0x00010000U  /*!< Normal interrupt summary flag */
01411 #define ETH_DMA_FLAG_AIS               0x00008000U  /*!< Abnormal interrupt summary flag */
01412 #define ETH_DMA_FLAG_ER                0x00004000U  /*!< Early receive flag */
01413 #define ETH_DMA_FLAG_FBE               0x00002000U  /*!< Fatal bus error flag */
01414 #define ETH_DMA_FLAG_ET                0x00000400U  /*!< Early transmit flag */
01415 #define ETH_DMA_FLAG_RWT               0x00000200U  /*!< Receive watchdog timeout flag */
01416 #define ETH_DMA_FLAG_RPS               0x00000100U  /*!< Receive process stopped flag */
01417 #define ETH_DMA_FLAG_RBU               0x00000080U  /*!< Receive buffer unavailable flag */
01418 #define ETH_DMA_FLAG_R                 0x00000040U  /*!< Receive flag */
01419 #define ETH_DMA_FLAG_TU                0x00000020U  /*!< Underflow flag */
01420 #define ETH_DMA_FLAG_RO                0x00000010U  /*!< Overflow flag */
01421 #define ETH_DMA_FLAG_TJT               0x00000008U  /*!< Transmit jabber timeout flag */
01422 #define ETH_DMA_FLAG_TBU               0x00000004U  /*!< Transmit buffer unavailable flag */
01423 #define ETH_DMA_FLAG_TPS               0x00000002U  /*!< Transmit process stopped flag */
01424 #define ETH_DMA_FLAG_T                 0x00000001U  /*!< Transmit flag */
01425 /**
01426   * @}
01427   */
01428
01429 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
01430   * @{
01431   */
01432 #define ETH_MAC_IT_TST       0x00000200U  /*!< Time stamp trigger interrupt (on MAC) */
01433 #define ETH_MAC_IT_MMCT      0x00000040U  /*!< MMC transmit interrupt */
01434 #define ETH_MAC_IT_MMCR      0x00000020U  /*!< MMC receive interrupt */
01435 #define ETH_MAC_IT_MMC       0x00000010U  /*!< MMC interrupt (on MAC) */
01436 #define ETH_MAC_IT_PMT       0x00000008U  /*!< PMT interrupt (on MAC) */
01437 /**
01438   * @}
01439   */
01440
01441 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
01442   * @{
01443   */
01444 #define ETH_DMA_IT_TST       0x20000000U  /*!< Time-stamp trigger interrupt (on DMA) */
01445 #define ETH_DMA_IT_PMT       0x10000000U  /*!< PMT interrupt (on DMA) */
01446 #define ETH_DMA_IT_MMC       0x08000000U  /*!< MMC interrupt (on DMA) */
01447 #define ETH_DMA_IT_NIS       0x00010000U  /*!< Normal interrupt summary */
01448 #define ETH_DMA_IT_AIS       0x00008000U  /*!< Abnormal interrupt summary */
01449 #define ETH_DMA_IT_ER        0x00004000U  /*!< Early receive interrupt */
01450 #define ETH_DMA_IT_FBE       0x00002000U  /*!< Fatal bus error interrupt */
01451 #define ETH_DMA_IT_ET        0x00000400U  /*!< Early transmit interrupt */
01452 #define ETH_DMA_IT_RWT       0x00000200U  /*!< Receive watchdog timeout interrupt */
01453 #define ETH_DMA_IT_RPS       0x00000100U  /*!< Receive process stopped interrupt */
01454 #define ETH_DMA_IT_RBU       0x00000080U  /*!< Receive buffer unavailable interrupt */
01455 #define ETH_DMA_IT_R         0x00000040U  /*!< Receive interrupt */
01456 #define ETH_DMA_IT_TU        0x00000020U  /*!< Underflow interrupt */
01457 #define ETH_DMA_IT_RO        0x00000010U  /*!< Overflow interrupt */
01458 #define ETH_DMA_IT_TJT       0x00000008U  /*!< Transmit jabber timeout interrupt */
01459 #define ETH_DMA_IT_TBU       0x00000004U  /*!< Transmit buffer unavailable interrupt */
01460 #define ETH_DMA_IT_TPS       0x00000002U  /*!< Transmit process stopped interrupt */
01461 #define ETH_DMA_IT_T         0x00000001U  /*!< Transmit interrupt */
01462 /**
01463   * @}
01464   */
01465
01466 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
01467   * @{
01468   */
01469 #define ETH_DMA_TRANSMITPROCESS_STOPPED     0x00000000U  /*!< Stopped - Reset or Stop Tx Command issued */
01470 #define ETH_DMA_TRANSMITPROCESS_FETCHING    0x00100000U  /*!< Running - fetching the Tx descriptor */
01471 #define ETH_DMA_TRANSMITPROCESS_WAITING     0x00200000U  /*!< Running - waiting for status */
01472 #define ETH_DMA_TRANSMITPROCESS_READING     0x00300000U  /*!< Running - reading the data from host memory */
01473 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED   0x00600000U  /*!< Suspended - Tx Descriptor unavailable */
01474 #define ETH_DMA_TRANSMITPROCESS_CLOSING     0x00700000U  /*!< Running - closing Rx descriptor */
01475
01476 /**
01477   * @}
01478   */
01479
01480
01481 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
01482   * @{
01483   */
01484 #define ETH_DMA_RECEIVEPROCESS_STOPPED      0x00000000U  /*!< Stopped - Reset or Stop Rx Command issued */
01485 #define ETH_DMA_RECEIVEPROCESS_FETCHING     0x00020000U  /*!< Running - fetching the Rx descriptor */
01486 #define ETH_DMA_RECEIVEPROCESS_WAITING      0x00060000U  /*!< Running - waiting for packet */
01487 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED    0x00080000U  /*!< Suspended - Rx Descriptor unavailable */
01488 #define ETH_DMA_RECEIVEPROCESS_CLOSING      0x000A0000U  /*!< Running - closing descriptor */
01489 #define ETH_DMA_RECEIVEPROCESS_QUEUING      0x000E0000U  /*!< Running - queuing the receive frame into host memory */
01490
01491 /**
01492   * @}
01493   */
01494
01495 /** @defgroup ETH_DMA_overflow ETH DMA overflow
01496   * @{
01497   */
01498 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER      0x10000000U  /*!< Overflow bit for FIFO overflow counter */
01499 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U  /*!< Overflow bit for missed frame counter */
01500 /**
01501   * @}
01502   */
01503
01504 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
01505   * @{
01506   */
01507 #define ETH_EXTI_LINE_WAKEUP              0x00080000U  /*!< External interrupt line 19 Connected to the ETH EXTI Line */
01508
01509 /**
01510   * @}
01511   */
01512
01513 /**
01514   * @}
01515   */
01516
01517 /* Exported macro ------------------------------------------------------------*/
01518 /** @defgroup ETH_Exported_Macros ETH Exported Macros
01519  *  @brief macros to handle interrupts and specific clock configurations
01520  * @{
01521  */
01522
01523 /** @brief Reset ETH handle state
01524   * @param  __HANDLE__: specifies the ETH handle.
01525   * @retval None
01526   */
01527 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
01528
01529 /**
01530   * @brief  Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
01531   * @param  __HANDLE__: ETH Handle
01532   * @param  __FLAG__: specifies the flag of TDES0 to check.
01533   * @retval the ETH_DMATxDescFlag (SET or RESET).
01534   */
01535 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
01536
01537 /**
01538   * @brief  Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
01539   * @param  __HANDLE__: ETH Handle
01540   * @param  __FLAG__: specifies the flag of RDES0 to check.
01541   * @retval the ETH_DMATxDescFlag (SET or RESET).
01542   */
01543 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
01544
01545 /**
01546   * @brief  Enables the specified DMA Rx Desc receive interrupt.
01547   * @param  __HANDLE__: ETH Handle
01548   * @retval None
01549   */
01550 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
01551
01552 /**
01553   * @brief  Disables the specified DMA Rx Desc receive interrupt.
01554   * @param  __HANDLE__: ETH Handle
01555   * @retval None
01556   */
01557 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__)                         ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
01558
01559 /**
01560   * @brief  Set the specified DMA Rx Desc Own bit.
01561   * @param  __HANDLE__: ETH Handle
01562   * @retval None
01563   */
01564 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__)                           ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
01565
01566 /**
01567   * @brief  Returns the specified ETHERNET DMA Tx Desc collision count.
01568   * @param  __HANDLE__: ETH Handle
01569   * @retval The Transmit descriptor collision counter value.
01570   */
01571 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__)                   (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
01572
01573 /**
01574   * @brief  Set the specified DMA Tx Desc Own bit.
01575   * @param  __HANDLE__: ETH Handle
01576   * @retval None
01577   */
01578 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__)                       ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
01579
01580 /**
01581   * @brief  Enables the specified DMA Tx Desc Transmit interrupt.
01582   * @param  __HANDLE__: ETH Handle
01583   * @retval None
01584   */
01585 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
01586
01587 /**
01588   * @brief  Disables the specified DMA Tx Desc Transmit interrupt.
01589   * @param  __HANDLE__: ETH Handle
01590   * @retval None
01591   */
01592 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
01593
01594 /**
01595   * @brief  Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
01596   * @param  __HANDLE__: ETH Handle
01597   * @param  __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
01598   *   This parameter can be one of the following values:
01599   *     @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
01600   *     @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
01601   *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
01602   *     @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
01603   * @retval None
01604   */
01605 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__)     ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
01606
01607 /**
01608   * @brief  Enables the DMA Tx Desc CRC.
01609   * @param  __HANDLE__: ETH Handle
01610   * @retval None
01611   */
01612 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__)                          ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
01613
01614 /**
01615   * @brief  Disables the DMA Tx Desc CRC.
01616   * @param  __HANDLE__: ETH Handle
01617   * @retval None
01618   */
01619 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__)                         ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
01620
01621 /**
01622   * @brief  Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
01623   * @param  __HANDLE__: ETH Handle
01624   * @retval None
01625   */
01626 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__)            ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
01627
01628 /**
01629   * @brief  Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
01630   * @param  __HANDLE__: ETH Handle
01631   * @retval None
01632   */
01633 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__)           ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
01634
01635 /**
01636  * @brief  Enables the specified ETHERNET MAC interrupts.
01637   * @param  __HANDLE__   : ETH Handle
01638   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
01639   *   enabled or disabled.
01640   *   This parameter can be any combination of the following values:
01641   *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
01642   *     @arg ETH_MAC_IT_PMT : PMT interrupt
01643   * @retval None
01644   */
01645 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
01646
01647 /**
01648   * @brief  Disables the specified ETHERNET MAC interrupts.
01649   * @param  __HANDLE__   : ETH Handle
01650   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
01651   *   enabled or disabled.
01652   *   This parameter can be any combination of the following values:
01653   *     @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
01654   *     @arg ETH_MAC_IT_PMT : PMT interrupt
01655   * @retval None
01656   */
01657 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
01658
01659 /**
01660   * @brief  Initiate a Pause Control Frame (Full-duplex only).
01661   * @param  __HANDLE__: ETH Handle
01662   * @retval None
01663   */
01664 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__)              ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
01665
01666 /**
01667   * @brief  Checks whether the ETHERNET flow control busy bit is set or not.
01668   * @param  __HANDLE__: ETH Handle
01669   * @retval The new state of flow control busy status bit (SET or RESET).
01670   */
01671 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__)               (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
01672
01673 /**
01674   * @brief  Enables the MAC Back Pressure operation activation (Half-duplex only).
01675   * @param  __HANDLE__: ETH Handle
01676   * @retval None
01677   */
01678 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
01679
01680 /**
01681   * @brief  Disables the MAC BackPressure operation activation (Half-duplex only).
01682   * @param  __HANDLE__: ETH Handle
01683   * @retval None
01684   */
01685 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__)         ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
01686
01687 /**
01688   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
01689   * @param  __HANDLE__: ETH Handle
01690   * @param  __FLAG__: specifies the flag to check.
01691   *   This parameter can be one of the following values:
01692   *     @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag
01693   *     @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
01694   *     @arg ETH_MAC_FLAG_MMCR : MMC receive flag
01695   *     @arg ETH_MAC_FLAG_MMC  : MMC flag
01696   *     @arg ETH_MAC_FLAG_PMT  : PMT flag
01697   * @retval The state of ETHERNET MAC flag.
01698   */
01699 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
01700
01701 /**
01702   * @brief  Enables the specified ETHERNET DMA interrupts.
01703   * @param  __HANDLE__   : ETH Handle
01704   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
01705   *   enabled @ref ETH_DMA_Interrupts
01706   * @retval None
01707   */
01708 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
01709
01710 /**
01711   * @brief  Disables the specified ETHERNET DMA interrupts.
01712   * @param  __HANDLE__   : ETH Handle
01713   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
01714   *   disabled. @ref ETH_DMA_Interrupts
01715   * @retval None
01716   */
01717 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
01718
01719 /**
01720   * @brief  Clears the ETHERNET DMA IT pending bit.
01721   * @param  __HANDLE__   : ETH Handle
01722   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
01723   * @retval None
01724   */
01725 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
01726
01727 /**
01728   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
01729 * @param  __HANDLE__: ETH Handle
01730   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
01731   * @retval The new state of ETH_DMA_FLAG (SET or RESET).
01732   */
01733 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
01734
01735 /**
01736   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
01737   * @param  __HANDLE__: ETH Handle
01738   * @param  __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
01739   * @retval The new state of ETH_DMA_FLAG (SET or RESET).
01740   */
01741 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->DMASR = (__FLAG__))
01742
01743 /**
01744   * @brief  Checks whether the specified ETHERNET DMA overflow flag is set or not.
01745   * @param  __HANDLE__: ETH Handle
01746   * @param  __OVERFLOW__: specifies the DMA overflow flag to check.
01747   *   This parameter can be one of the following values:
01748   *     @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
01749   *     @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
01750   * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
01751   */
01752 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__)       (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
01753
01754 /**
01755   * @brief  Set the DMA Receive status watchdog timer register value
01756   * @param  __HANDLE__: ETH Handle
01757   * @param  __VALUE__: DMA Receive status watchdog timer register value
01758   * @retval None
01759   */
01760 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__)       ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
01761
01762 /**
01763   * @brief  Enables any unicast packet filtered by the MAC address
01764   *   recognition to be a wake-up frame.
01765   * @param  __HANDLE__: ETH Handle.
01766   * @retval None
01767   */
01768 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
01769
01770 /**
01771   * @brief  Disables any unicast packet filtered by the MAC address
01772   *   recognition to be a wake-up frame.
01773   * @param  __HANDLE__: ETH Handle.
01774   * @retval None
01775   */
01776 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
01777
01778 /**
01779   * @brief  Enables the MAC Wake-Up Frame Detection.
01780   * @param  __HANDLE__: ETH Handle.
01781   * @retval None
01782   */
01783 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
01784
01785 /**
01786   * @brief  Disables the MAC Wake-Up Frame Detection.
01787   * @param  __HANDLE__: ETH Handle.
01788   * @retval None
01789   */
01790 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
01791
01792 /**
01793   * @brief  Enables the MAC Magic Packet Detection.
01794   * @param  __HANDLE__: ETH Handle.
01795   * @retval None
01796   */
01797 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__)              ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
01798
01799 /**
01800   * @brief  Disables the MAC Magic Packet Detection.
01801   * @param  __HANDLE__: ETH Handle.
01802   * @retval None
01803   */
01804 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__)             ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
01805
01806 /**
01807   * @brief  Enables the MAC Power Down.
01808   * @param  __HANDLE__: ETH Handle
01809   * @retval None
01810   */
01811 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__)                         ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
01812
01813 /**
01814   * @brief  Disables the MAC Power Down.
01815   * @param  __HANDLE__: ETH Handle
01816   * @retval None
01817   */
01818 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__)                        ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
01819
01820 /**
01821   * @brief  Checks whether the specified ETHERNET PMT flag is set or not.
01822   * @param  __HANDLE__: ETH Handle.
01823   * @param  __FLAG__: specifies the flag to check.
01824   *   This parameter can be one of the following values:
01825   *     @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
01826   *     @arg ETH_PMT_FLAG_WUFR    : Wake-Up Frame Received
01827   *     @arg ETH_PMT_FLAG_MPR     : Magic Packet Received
01828   * @retval The new state of ETHERNET PMT Flag (SET or RESET).
01829   */
01830 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__)               (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
01831
01832 /**
01833   * @brief  Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
01834   * @param   __HANDLE__: ETH Handle.
01835   * @retval None
01836   */
01837 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__)                     ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
01838
01839 /**
01840   * @brief  Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
01841   * @param  __HANDLE__: ETH Handle.
01842   * @retval None
01843   */
01844 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__)                     do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
01845                                                                           (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U)
01846
01847 /**
01848   * @brief  Enables the MMC Counter Freeze.
01849   * @param  __HANDLE__: ETH Handle.
01850   * @retval None
01851   */
01852 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__)                  ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
01853
01854 /**
01855   * @brief  Disables the MMC Counter Freeze.
01856   * @param  __HANDLE__: ETH Handle.
01857   * @retval None
01858   */
01859 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__)                 ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
01860
01861 /**
01862   * @brief  Enables the MMC Reset On Read.
01863   * @param  __HANDLE__: ETH Handle.
01864   * @retval None
01865   */
01866 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
01867
01868 /**
01869   * @brief  Disables the MMC Reset On Read.
01870   * @param  __HANDLE__: ETH Handle.
01871   * @retval None
01872   */
01873 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
01874
01875 /**
01876   * @brief  Enables the MMC Counter Stop Rollover.
01877   * @param  __HANDLE__: ETH Handle.
01878   * @retval None
01879   */
01880 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__)            ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
01881
01882 /**
01883   * @brief  Disables the MMC Counter Stop Rollover.
01884   * @param  __HANDLE__: ETH Handle.
01885   * @retval None
01886   */
01887 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__)           ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
01888
01889 /**
01890   * @brief  Resets the MMC Counters.
01891   * @param   __HANDLE__: ETH Handle.
01892   * @retval None
01893   */
01894 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__)                         ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
01895
01896 /**
01897   * @brief  Enables the specified ETHERNET MMC Rx interrupts.
01898   * @param   __HANDLE__: ETH Handle.
01899   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
01900   *   This parameter can be one of the following values:
01901   *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
01902   *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
01903   *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
01904   * @retval None
01905   */
01906 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__)               (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
01907 /**
01908   * @brief  Disables the specified ETHERNET MMC Rx interrupts.
01909   * @param   __HANDLE__: ETH Handle.
01910   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
01911   *   This parameter can be one of the following values:
01912   *     @arg ETH_MMC_IT_RGUF  : When Rx good unicast frames counter reaches half the maximum value
01913   *     @arg ETH_MMC_IT_RFAE  : When Rx alignment error counter reaches half the maximum value
01914   *     @arg ETH_MMC_IT_RFCE  : When Rx crc error counter reaches half the maximum value
01915   * @retval None
01916   */
01917 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__)              (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
01918 /**
01919   * @brief  Enables the specified ETHERNET MMC Tx interrupts.
01920   * @param   __HANDLE__: ETH Handle.
01921   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
01922   *   This parameter can be one of the following values:
01923   *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
01924   *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
01925   *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
01926   * @retval None
01927   */
01928 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__)            ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
01929
01930 /**
01931   * @brief  Disables the specified ETHERNET MMC Tx interrupts.
01932   * @param   __HANDLE__: ETH Handle.
01933   * @param  __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
01934   *   This parameter can be one of the following values:
01935   *     @arg ETH_MMC_IT_TGF   : When Tx good frame counter reaches half the maximum value
01936   *     @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
01937   *     @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
01938   * @retval None
01939   */
01940 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__)           ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
01941
01942 /**
01943   * @brief  Enables the ETH External interrupt line.
01944   * @retval None
01945   */
01946 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
01947
01948 /**
01949   * @brief  Disables the ETH External interrupt line.
01950   * @retval None
01951   */
01952 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
01953
01954 /**
01955   * @brief Enable event on ETH External event line.
01956   * @retval None.
01957   */
01958 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT()  EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
01959
01960 /**
01961   * @brief Disable event on ETH External event line
01962   * @retval None.
01963   */
01964 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
01965
01966 /**
01967   * @brief  Get flag of the ETH External interrupt line.
01968   * @retval None
01969   */
01970 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
01971
01972 /**
01973   * @brief  Clear flag of the ETH External interrupt line.
01974   * @retval None
01975   */
01976 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
01977
01978 /**
01979   * @brief  Enables rising edge trigger to the ETH External interrupt line.
01980   * @retval None
01981   */
01982 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
01983
01984 /**
01985   * @brief  Disables the rising edge trigger to the ETH External interrupt line.
01986   * @retval None
01987   */
01988 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER()  EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
01989
01990 /**
01991   * @brief  Enables falling edge trigger to the ETH External interrupt line.
01992   * @retval None
01993   */
01994 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
01995
01996 /**
01997   * @brief  Disables falling edge trigger to the ETH External interrupt line.
01998   * @retval None
01999   */
02000 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER()  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
02001
02002 /**
02003   * @brief  Enables rising/falling edge trigger to the ETH External interrupt line.
02004   * @retval None
02005   */
02006 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER()  do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
02007                                                                  EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
02008                                                                 }while(0U)
02009
02010 /**
02011   * @brief  Disables rising/falling edge trigger to the ETH External interrupt line.
02012   * @retval None
02013   */
02014 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
02015                                                                  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
02016                                                                 }while(0U)
02017
02018 /**
02019   * @brief Generate a Software interrupt on selected EXTI line.
02020   * @retval None.
02021   */
02022 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT()                  EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
02023
02024 /**
02025   * @}
02026   */
02027 /* Exported functions --------------------------------------------------------*/
02028
02029 /** @addtogroup ETH_Exported_Functions
02030   * @{
02031   */
02032
02033 /* Initialization and de-initialization functions  ****************************/
02034
02035 /** @addtogroup ETH_Exported_Functions_Group1
02036   * @{
02037   */
02038 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
02039 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
02040 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
02041 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
02042 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
02043 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
02044
02045 /**
02046   * @}
02047   */
02048 /* IO operation functions  ****************************************************/
02049
02050 /** @addtogroup ETH_Exported_Functions_Group2
02051   * @{
02052   */
02053 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
02054 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
02055 /* Communication with PHY functions*/
02056 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
02057 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
02058 /* Non-Blocking mode: Interrupt */
02059 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
02060 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
02061 /* Callback in non blocking modes (Interrupt) */
02062 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
02063 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
02064 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
02065 /**
02066   * @}
02067   */
02068
02069 /* Peripheral Control functions  **********************************************/
02070
02071 /** @addtogroup ETH_Exported_Functions_Group3
02072   * @{
02073   */
02074
02075 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
02076 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
02077 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
02078 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
02079 /**
02080   * @}
02081   */
02082
02083 /* Peripheral State functions  ************************************************/
02084
02085 /** @addtogroup ETH_Exported_Functions_Group4
02086   * @{
02087   */
02088 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
02089 /**
02090   * @}
02091   */
02092
02093 /**
02094   * @}
02095   */
02096
02097 /**
02098   * @}
02099   */
02100
02101 #endif /* STM32F107xC */
02102 /**
02103   * @}
02104   */
02105
02106 #ifdef __cplusplus
02107 }
02108 #endif
02109
02110 #endif /* __STM32F1xx_HAL_ETH_H */
02111
02112
02113 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_flash.c Source File

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stm32f1xx_hal_flash.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_flash.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   FLASH HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the internal FLASH memory:
00010   *           + Program operations functions
00011   *           + Memory Control functions
00012   *           + Peripheral State functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### FLASH peripheral features #####
00017   ==============================================================================
00018   [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
00019        to the Flash memory. It implements the erase and program Flash memory operations
00020        and the read and write protection mechanisms.
00021
00022   [..] The Flash memory interface accelerates code execution with a system of instruction
00023       prefetch.
00024
00025   [..] The FLASH main features are:
00026       (+) Flash memory read operations
00027       (+) Flash memory program/erase operations
00028       (+) Read / write protections
00029       (+) Prefetch on I-Code
00030       (+) Option Bytes programming
00031
00032
00033                      ##### How to use this driver #####
00034   ==============================================================================
00035   [..]
00036       This driver provides functions and macros to configure and program the FLASH
00037       memory of all STM32F1xx devices.
00038
00039       (#) FLASH Memory I/O Programming functions: this group includes all needed
00040           functions to erase and program the main memory:
00041         (++) Lock and Unlock the FLASH interface
00042         (++) Erase function: Erase page, erase all pages
00043         (++) Program functions: half word, word and doubleword
00044       (#) FLASH Option Bytes Programming functions: this group includes all needed
00045           functions to manage the Option Bytes:
00046         (++) Lock and Unlock the Option Bytes
00047         (++) Set/Reset the write protection
00048         (++) Set the Read protection Level
00049         (++) Program the user Option Bytes
00050         (++) Launch the Option Bytes loader
00051         (++) Erase Option Bytes
00052         (++) Program the data Option Bytes
00053         (++) Get the Write protection.
00054         (++) Get the user option bytes.
00055
00056       (#) Interrupts and flags management functions : this group
00057           includes all needed functions to:
00058         (++) Handle FLASH interrupts
00059         (++) Wait for last FLASH operation according to its status
00060         (++) Get error flag status
00061
00062   [..] In addition to these function, this driver includes a set of macros allowing
00063        to handle the following operations:
00064
00065       (+) Set/Get the latency
00066       (+) Enable/Disable the prefetch buffer
00067       (+) Enable/Disable the half cycle access
00068       (+) Enable/Disable the FLASH interrupts
00069       (+) Monitor the FLASH flags status
00070
00071   @endverbatim
00072   ******************************************************************************
00073   * @attention
00074   *
00075   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00076   *
00077   * Redistribution and use in source and binary forms, with or without modification,
00078   * are permitted provided that the following conditions are met:
00079   *   1. Redistributions of source code must retain the above copyright notice,
00080   *      this list of conditions and the following disclaimer.
00081   *   2. Redistributions in binary form must reproduce the above copyright notice,
00082   *      this list of conditions and the following disclaimer in the documentation
00083   *      and/or other materials provided with the distribution.
00084   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00085   *      may be used to endorse or promote products derived from this software
00086   *      without specific prior written permission.
00087   *
00088   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00089   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00090   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00091   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00092   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00093   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00094   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00095   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00096   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00097   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00098   *
00099   ******************************************************************************
00100   */
00101
00102 /* Includes ------------------------------------------------------------------*/
00103 #include "stm32f1xx_hal.h"
00104
00105 /** @addtogroup STM32F1xx_HAL_Driver
00106   * @{
00107   */
00108
00109 #ifdef HAL_FLASH_MODULE_ENABLED
00110
00111 /** @defgroup FLASH FLASH
00112   * @brief FLASH HAL module driver
00113   * @{
00114   */
00115
00116 /* Private typedef -----------------------------------------------------------*/
00117 /* Private define ------------------------------------------------------------*/
00118 /** @defgroup FLASH_Private_Constants FLASH Private Constants
00119   * @{
00120   */
00121 /**
00122   * @}
00123   */
00124
00125 /* Private macro ---------------------------- ---------------------------------*/
00126 /** @defgroup FLASH_Private_Macros FLASH Private Macros
00127   * @{
00128   */
00129
00130 /**
00131   * @}
00132   */
00133
00134 /* Private variables ---------------------------------------------------------*/
00135 /** @defgroup FLASH_Private_Variables FLASH Private Variables
00136   * @{
00137   */
00138 /* Variables used for Erase pages under interruption*/
00139 FLASH_ProcessTypeDef pFlash;
00140 /**
00141   * @}
00142   */
00143
00144 /* Private function prototypes -----------------------------------------------*/
00145 /** @defgroup FLASH_Private_Functions FLASH Private Functions
00146   * @{
00147   */
00148 static  void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
00149 static  void   FLASH_SetErrorCode(void);
00150 extern void    FLASH_PageErase(uint32_t PageAddress);
00151 /**
00152   * @}
00153   */
00154
00155 /* Exported functions ---------------------------------------------------------*/
00156 /** @defgroup FLASH_Exported_Functions FLASH Exported Functions
00157   * @{
00158   */
00159
00160 /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
00161   *  @brief   Programming operation functions
00162   *
00163 @verbatim
00164 @endverbatim
00165   * @{
00166   */
00167
00168 /**
00169   * @brief  Program halfword, word or double word at a specified address
00170   * @note   The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
00171   *         The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
00172   *
00173   * @note   If an erase and a program operations are requested simultaneously,
00174   *         the erase operation is performed before the program one.
00175   *
00176   * @note   FLASH should be previously erased before new programmation (only exception to this
00177   *         is when 0x0000 is programmed)
00178   *
00179   * @param  TypeProgram:  Indicate the way to program at a specified address.
00180   *                       This parameter can be a value of @ref FLASH_Type_Program
00181   * @param  Address:      Specifies the address to be programmed.
00182   * @param  Data:         Specifies the data to be programmed
00183   *
00184   * @retval HAL_StatusTypeDef HAL Status
00185   */
00186 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00187 {
00188   HAL_StatusTypeDef status = HAL_ERROR;
00189   uint8_t index = 0;
00190   uint8_t nbiterations = 0;
00191
00192   /* Process Locked */
00193   __HAL_LOCK(&pFlash);
00194
00195   /* Check the parameters */
00196   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00197   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00198
00199 #if defined(FLASH_BANK2_END)
00200   if(Address <= FLASH_BANK1_END)
00201   {
00202 #endif /* FLASH_BANK2_END */
00203     /* Wait for last operation to be completed */
00204     status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00205 #if defined(FLASH_BANK2_END)
00206   }
00207   else
00208   {
00209     /* Wait for last operation to be completed */
00210     status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
00211   }
00212 #endif /* FLASH_BANK2_END */
00213
00214   if(status == HAL_OK)
00215   {
00216     if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
00217     {
00218       /* Program halfword (16-bit) at a specified address. */
00219       nbiterations = 1U;
00220     }
00221     else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
00222     {
00223       /* Program word (32-bit = 2*16-bit) at a specified address. */
00224       nbiterations = 2U;
00225     }
00226     else
00227     {
00228       /* Program double word (64-bit = 4*16-bit) at a specified address. */
00229       nbiterations = 4U;
00230     }
00231
00232     for (index = 0U; index < nbiterations; index++)
00233     {
00234       FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
00235
00236 #if defined(FLASH_BANK2_END)
00237       if(Address <= FLASH_BANK1_END)
00238       {
00239 #endif /* FLASH_BANK2_END */
00240         /* Wait for last operation to be completed */
00241         status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
00242
00243         /* If the program operation is completed, disable the PG Bit */
00244         CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
00245 #if defined(FLASH_BANK2_END)
00246       }
00247       else
00248       {
00249         /* Wait for last operation to be completed */
00250         status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
00251
00252         /* If the program operation is completed, disable the PG Bit */
00253         CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
00254       }
00255 #endif /* FLASH_BANK2_END */
00256       /* In case of error, stop programation procedure */
00257       if (status != HAL_OK)
00258       {
00259         break;
00260       }
00261     }
00262   }
00263
00264   /* Process Unlocked */
00265   __HAL_UNLOCK(&pFlash);
00266
00267   return status;
00268 }
00269
00270 /**
00271   * @brief  Program halfword, word or double word at a specified address  with interrupt enabled.
00272   * @note   The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
00273   *         The function HAL_FLASH_Lock() should be called after to lock the FLASH interface
00274   *
00275   * @note   If an erase and a program operations are requested simultaneously,
00276   *         the erase operation is performed before the program one.
00277   *
00278   * @param  TypeProgram: Indicate the way to program at a specified address.
00279   *                      This parameter can be a value of @ref FLASH_Type_Program
00280   * @param  Address:     Specifies the address to be programmed.
00281   * @param  Data:        Specifies the data to be programmed
00282   *
00283   * @retval HAL_StatusTypeDef HAL Status
00284   */
00285 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
00286 {
00287   HAL_StatusTypeDef status = HAL_OK;
00288
00289   /* Process Locked */
00290   __HAL_LOCK(&pFlash);
00291
00292   /* Check the parameters */
00293   assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
00294   assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
00295
00296 #if defined(FLASH_BANK2_END)
00297   /* If procedure already ongoing, reject the next one */
00298   if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
00299   {
00300     return HAL_ERROR;
00301   }
00302
00303   if(Address <= FLASH_BANK1_END)
00304   {
00305     /* Enable End of FLASH Operation and Error source interrupts */
00306     __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1);
00307
00308   }else
00309   {
00310     /* Enable End of FLASH Operation and Error source interrupts */
00311     __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
00312   }
00313 #else
00314   /* Enable End of FLASH Operation and Error source interrupts */
00315   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
00316 #endif /* FLASH_BANK2_END */
00317
00318   pFlash.Address = Address;
00319   pFlash.Data = Data;
00320
00321   if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
00322   {
00323     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
00324     /* Program halfword (16-bit) at a specified address. */
00325     pFlash.DataRemaining = 1U;
00326   }
00327   else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
00328   {
00329     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
00330     /* Program word (32-bit : 2*16-bit) at a specified address. */
00331     pFlash.DataRemaining = 2U;
00332   }
00333   else
00334   {
00335     pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
00336     /* Program double word (64-bit : 4*16-bit) at a specified address. */
00337     pFlash.DataRemaining = 4U;
00338   }
00339
00340   /* Program halfword (16-bit) at a specified address. */
00341   FLASH_Program_HalfWord(Address, (uint16_t)Data);
00342
00343   return status;
00344 }
00345
00346 /**
00347   * @brief This function handles FLASH interrupt request.
00348   * @retval None
00349   */
00350 void HAL_FLASH_IRQHandler(void)
00351 {
00352   uint32_t addresstmp = 0U;
00353
00354   /* Check FLASH operation error flags */
00355 #if defined(FLASH_BANK2_END)
00356   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK1) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK1) || \
00357     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)))
00358 #else
00359   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
00360 #endif /* FLASH_BANK2_END */
00361   {
00362     /* Return the faulty address */
00363     addresstmp = pFlash.Address;
00364     /* Reset address */
00365     pFlash.Address = 0xFFFFFFFFU;
00366
00367     /* Save the Error code */
00368     FLASH_SetErrorCode();
00369
00370     /* FLASH error interrupt user callback */
00371     HAL_FLASH_OperationErrorCallback(addresstmp);
00372
00373     /* Stop the procedure ongoing */
00374     pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00375   }
00376
00377   /* Check FLASH End of Operation flag  */
00378 #if defined(FLASH_BANK2_END)
00379   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK1))
00380   {
00381     /* Clear FLASH End of Operation pending bit */
00382     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK1);
00383 #else
00384   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
00385   {
00386     /* Clear FLASH End of Operation pending bit */
00387     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00388 #endif /* FLASH_BANK2_END */
00389
00390     /* Process can continue only if no error detected */
00391     if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
00392     {
00393       if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
00394       {
00395         /* Nb of pages to erased can be decreased */
00396         pFlash.DataRemaining--;
00397
00398         /* Check if there are still pages to erase */
00399         if(pFlash.DataRemaining != 0U)
00400         {
00401           addresstmp = pFlash.Address;
00402           /*Indicate user which sector has been erased */
00403           HAL_FLASH_EndOfOperationCallback(addresstmp);
00404
00405           /*Increment sector number*/
00406           addresstmp = pFlash.Address + FLASH_PAGE_SIZE;
00407           pFlash.Address = addresstmp;
00408
00409           /* If the erase operation is completed, disable the PER Bit */
00410           CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
00411
00412           FLASH_PageErase(addresstmp);
00413         }
00414         else
00415         {
00416           /* No more pages to Erase, user callback can be called. */
00417           /* Reset Sector and stop Erase pages procedure */
00418           pFlash.Address = addresstmp = 0xFFFFFFFFU;
00419           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00420           /* FLASH EOP interrupt user callback */
00421           HAL_FLASH_EndOfOperationCallback(addresstmp);
00422         }
00423       }
00424       else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
00425       {
00426         /* Operation is completed, disable the MER Bit */
00427         CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
00428
00429 #if defined(FLASH_BANK2_END)
00430         /* Stop Mass Erase procedure if no pending mass erase on other bank */
00431         if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER))
00432         {
00433 #endif /* FLASH_BANK2_END */
00434           /* MassErase ended. Return the selected bank */
00435           /* FLASH EOP interrupt user callback */
00436           HAL_FLASH_EndOfOperationCallback(0U);
00437
00438           /* Stop Mass Erase procedure*/
00439           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00440         }
00441 #if defined(FLASH_BANK2_END)
00442       }
00443 #endif /* FLASH_BANK2_END */
00444       else
00445       {
00446         /* Nb of 16-bit data to program can be decreased */
00447         pFlash.DataRemaining--;
00448
00449         /* Check if there are still 16-bit data to program */
00450         if(pFlash.DataRemaining != 0U)
00451         {
00452           /* Increment address to 16-bit */
00453           pFlash.Address += 2U;
00454           addresstmp = pFlash.Address;
00455
00456           /* Shift to have next 16-bit data */
00457           pFlash.Data = (pFlash.Data >> 16U);
00458
00459           /* Operation is completed, disable the PG Bit */
00460           CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
00461
00462           /*Program halfword (16-bit) at a specified address.*/
00463           FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
00464         }
00465         else
00466         {
00467           /* Program ended. Return the selected address */
00468           /* FLASH EOP interrupt user callback */
00469           if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
00470           {
00471             HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00472           }
00473           else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
00474           {
00475             HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
00476           }
00477           else
00478           {
00479             HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
00480           }
00481
00482           /* Reset Address and stop Program procedure */
00483           pFlash.Address = 0xFFFFFFFFU;
00484           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00485         }
00486       }
00487     }
00488   }
00489
00490 #if defined(FLASH_BANK2_END)
00491   /* Check FLASH End of Operation flag  */
00492   if(__HAL_FLASH_GET_FLAG( FLASH_FLAG_EOP_BANK2))
00493   {
00494     /* Clear FLASH End of Operation pending bit */
00495     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
00496
00497     /* Process can continue only if no error detected */
00498     if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
00499     {
00500       if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
00501       {
00502         /* Nb of pages to erased can be decreased */
00503         pFlash.DataRemaining--;
00504
00505         /* Check if there are still pages to erase*/
00506         if(pFlash.DataRemaining != 0U)
00507         {
00508           /* Indicate user which page address has been erased*/
00509           HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00510
00511           /* Increment page address to next page */
00512           pFlash.Address += FLASH_PAGE_SIZE;
00513           addresstmp = pFlash.Address;
00514
00515           /* Operation is completed, disable the PER Bit */
00516           CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
00517
00518           FLASH_PageErase(addresstmp);
00519         }
00520         else
00521         {
00522           /*No more pages to Erase*/
00523
00524           /*Reset Address and stop Erase pages procedure*/
00525           pFlash.Address = 0xFFFFFFFFU;
00526           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00527
00528           /* FLASH EOP interrupt user callback */
00529           HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00530         }
00531       }
00532       else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
00533       {
00534         /* Operation is completed, disable the MER Bit */
00535         CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
00536
00537         if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_MER))
00538         {
00539           /* MassErase ended. Return the selected bank*/
00540           /* FLASH EOP interrupt user callback */
00541           HAL_FLASH_EndOfOperationCallback(0U);
00542
00543           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00544         }
00545       }
00546       else
00547       {
00548         /* Nb of 16-bit data to program can be decreased */
00549         pFlash.DataRemaining--;
00550
00551         /* Check if there are still 16-bit data to program */
00552         if(pFlash.DataRemaining != 0U)
00553         {
00554           /* Increment address to 16-bit */
00555           pFlash.Address += 2U;
00556           addresstmp = pFlash.Address;
00557
00558           /* Shift to have next 16-bit data */
00559           pFlash.Data = (pFlash.Data >> 16U);
00560
00561           /* Operation is completed, disable the PG Bit */
00562           CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
00563
00564           /*Program halfword (16-bit) at a specified address.*/
00565           FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data);
00566         }
00567         else
00568         {
00569           /*Program ended. Return the selected address*/
00570           /* FLASH EOP interrupt user callback */
00571           if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
00572           {
00573             HAL_FLASH_EndOfOperationCallback(pFlash.Address);
00574           }
00575           else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
00576           {
00577             HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U);
00578           }
00579           else
00580           {
00581             HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U);
00582           }
00583
00584           /* Reset Address and stop Program procedure*/
00585           pFlash.Address = 0xFFFFFFFFU;
00586           pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
00587         }
00588       }
00589     }
00590   }
00591 #endif
00592
00593   if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
00594   {
00595 #if defined(FLASH_BANK2_END)
00596     /* Operation is completed, disable the PG, PER and MER Bits for both bank */
00597     CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
00598     CLEAR_BIT(FLASH->CR2, (FLASH_CR2_PG | FLASH_CR2_PER | FLASH_CR2_MER));
00599
00600     /* Disable End of FLASH Operation and Error source interrupts for both banks */
00601     __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP_BANK1 | FLASH_IT_ERR_BANK1 | FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
00602 #else
00603     /* Operation is completed, disable the PG, PER and MER Bits */
00604     CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER));
00605
00606     /* Disable End of FLASH Operation and Error source interrupts */
00607     __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
00608 #endif /* FLASH_BANK2_END */
00609
00610     /* Process Unlocked */
00611     __HAL_UNLOCK(&pFlash);
00612   }
00613 }
00614
00615 /**
00616   * @brief  FLASH end of operation interrupt callback
00617   * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
00618   *                 - Mass Erase: No return value expected
00619   *                 - Pages Erase: Address of the page which has been erased
00620   *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
00621   *                 - Program: Address which was selected for data program
00622   * @retval none
00623   */
00624 __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
00625 {
00626   /* Prevent unused argument(s) compilation warning */
00627   UNUSED(ReturnValue);
00628
00629   /* NOTE : This function Should not be modified, when the callback is needed,
00630             the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
00631    */
00632 }
00633
00634 /**
00635   * @brief  FLASH operation error interrupt callback
00636   * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
00637   *                 - Mass Erase: No return value expected
00638   *                 - Pages Erase: Address of the page which returned an error
00639   *                 - Program: Address which was selected for data program
00640   * @retval none
00641   */
00642 __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
00643 {
00644   /* Prevent unused argument(s) compilation warning */
00645   UNUSED(ReturnValue);
00646
00647   /* NOTE : This function Should not be modified, when the callback is needed,
00648             the HAL_FLASH_OperationErrorCallback could be implemented in the user file
00649    */
00650 }
00651
00652 /**
00653   * @}
00654   */
00655
00656 /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
00657  *  @brief   management functions
00658  *
00659 @verbatim
00660  ===============================================================================
00661                       ##### Peripheral Control functions #####
00662  ===============================================================================
00663     [..]
00664     This subsection provides a set of functions allowing to control the FLASH
00665     memory operations.
00666
00667 @endverbatim
00668   * @{
00669   */
00670
00671 /**
00672   * @brief  Unlock the FLASH control register access
00673   * @retval HAL Status
00674   */
00675 HAL_StatusTypeDef HAL_FLASH_Unlock(void)
00676 {
00677   if (HAL_IS_BIT_SET(FLASH->CR, FLASH_CR_LOCK))
00678   {
00679     /* Authorize the FLASH Registers access */
00680     WRITE_REG(FLASH->KEYR, FLASH_KEY1);
00681     WRITE_REG(FLASH->KEYR, FLASH_KEY2);
00682   }
00683   else
00684   {
00685     return HAL_ERROR;
00686   }
00687
00688 #if defined(FLASH_BANK2_END)
00689   if (HAL_IS_BIT_SET(FLASH->CR2, FLASH_CR2_LOCK))
00690   {
00691     /* Authorize the FLASH BANK2 Registers access */
00692     WRITE_REG(FLASH->KEYR2, FLASH_KEY1);
00693     WRITE_REG(FLASH->KEYR2, FLASH_KEY2);
00694   }
00695   else
00696   {
00697     return HAL_ERROR;
00698   }
00699
00700 #endif /* FLASH_BANK2_END */
00701   return HAL_OK;
00702 }
00703
00704 /**
00705   * @brief  Locks the FLASH control register access
00706   * @retval HAL Status
00707   */
00708 HAL_StatusTypeDef HAL_FLASH_Lock(void)
00709 {
00710   /* Set the LOCK Bit to lock the FLASH Registers access */
00711   SET_BIT(FLASH->CR, FLASH_CR_LOCK);
00712
00713 #if defined(FLASH_BANK2_END)
00714   /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
00715   SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
00716
00717 #endif /* FLASH_BANK2_END */
00718   return HAL_OK;
00719 }
00720
00721 /**
00722   * @brief  Unlock the FLASH Option Control Registers access.
00723   * @retval HAL Status
00724   */
00725 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
00726 {
00727   if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE))
00728   {
00729     /* Authorizes the Option Byte register programming */
00730     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
00731     WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
00732   }
00733   else
00734   {
00735     return HAL_ERROR;
00736   }
00737
00738   return HAL_OK;
00739 }
00740
00741 /**
00742   * @brief  Lock the FLASH Option Control Registers access.
00743   * @retval HAL Status
00744   */
00745 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
00746 {
00747   /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */
00748   CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE);
00749
00750   return HAL_OK;
00751 }
00752
00753 /**
00754   * @brief  Launch the option byte loading.
00755   * @note   This function will reset automatically the MCU.
00756   * @retval HAL Status
00757   */
00758 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
00759 {
00760   /* Initiates a system reset request to launch the option byte loading */
00761   HAL_NVIC_SystemReset();
00762
00763   return HAL_OK;
00764 }
00765
00766 /**
00767   * @}
00768   */
00769
00770 /** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
00771  *  @brief    Peripheral errors functions
00772  *
00773 @verbatim
00774  ===============================================================================
00775                       ##### Peripheral Errors functions #####
00776  ===============================================================================
00777     [..]
00778     This subsection permit to get in run-time errors of  the FLASH peripheral.
00779
00780 @endverbatim
00781   * @{
00782   */
00783
00784 /**
00785   * @brief  Get the specific FLASH error flag.
00786   * @retval FLASH_ErrorCode The returned value can be:
00787   *            @ref FLASH_Error_Codes
00788   */
00789 uint32_t HAL_FLASH_GetError(void)
00790 {
00791    return pFlash.ErrorCode;
00792 }
00793
00794 /**
00795   * @}
00796   */
00797
00798 /**
00799   * @}
00800   */
00801
00802 /** @addtogroup FLASH_Private_Functions
00803  * @{
00804  */
00805
00806 /**
00807   * @brief  Program a half-word (16-bit) at a specified address.
00808   * @param  Address specify the address to be programmed.
00809   * @param  Data    specify the data to be programmed.
00810   * @retval None
00811   */
00812 static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
00813 {
00814   /* Clean the error context */
00815   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00816
00817 #if defined(FLASH_BANK2_END)
00818   if(Address <= FLASH_BANK1_END)
00819   {
00820 #endif /* FLASH_BANK2_END */
00821     /* Proceed to program the new data */
00822     SET_BIT(FLASH->CR, FLASH_CR_PG);
00823 #if defined(FLASH_BANK2_END)
00824   }
00825   else
00826   {
00827     /* Proceed to program the new data */
00828     SET_BIT(FLASH->CR2, FLASH_CR2_PG);
00829   }
00830 #endif /* FLASH_BANK2_END */
00831
00832   /* Write data in the address */
00833   *(__IO uint16_t*)Address = Data;
00834 }
00835
00836 /**
00837   * @brief  Wait for a FLASH operation to complete.
00838   * @param  Timeout  maximum flash operation timeout
00839   * @retval HAL Status
00840   */
00841 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
00842 {
00843   /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
00844      Even if the FLASH operation fails, the BUSY flag will be reset and an error
00845      flag will be set */
00846
00847   uint32_t tickstart = HAL_GetTick();
00848
00849   while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
00850   {
00851     if (Timeout != HAL_MAX_DELAY)
00852     {
00853       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00854       {
00855         return HAL_TIMEOUT;
00856       }
00857     }
00858   }
00859
00860   /* Check FLASH End of Operation flag  */
00861   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
00862   {
00863     /* Clear FLASH End of Operation pending bit */
00864     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
00865   }
00866
00867   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)  ||
00868      __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
00869      __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
00870   {
00871     /*Save the error code*/
00872     FLASH_SetErrorCode();
00873     return HAL_ERROR;
00874   }
00875
00876   /* There is no error flag set */
00877   return HAL_OK;
00878 }
00879
00880 #if defined(FLASH_BANK2_END)
00881 /**
00882   * @brief  Wait for a FLASH BANK2 operation to complete.
00883   * @param  Timeout maximum flash operation timeout
00884   * @retval HAL_StatusTypeDef HAL Status
00885   */
00886 HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)
00887 {
00888   /* Wait for the FLASH BANK2 operation to complete by polling on BUSY flag to be reset.
00889      Even if the FLASH BANK2 operation fails, the BUSY flag will be reset and an error
00890      flag will be set */
00891
00892   uint32_t tickstart = HAL_GetTick();
00893
00894   while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY_BANK2))
00895   {
00896     if (Timeout != HAL_MAX_DELAY)
00897     {
00898       if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
00899       {
00900         return HAL_TIMEOUT;
00901       }
00902     }
00903   }
00904
00905   /* Check FLASH End of Operation flag  */
00906   if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP_BANK2))
00907   {
00908     /* Clear FLASH End of Operation pending bit */
00909     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP_BANK2);
00910   }
00911
00912   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
00913   {
00914     /*Save the error code*/
00915     FLASH_SetErrorCode();
00916     return HAL_ERROR;
00917   }
00918
00919   /* If there is an error flag set */
00920   return HAL_OK;
00921
00922 }
00923 #endif /* FLASH_BANK2_END */
00924
00925 /**
00926   * @brief  Set the specific FLASH error flag.
00927   * @retval None
00928   */
00929 static void FLASH_SetErrorCode(void)
00930 {
00931   uint32_t flags = 0U;
00932
00933 #if defined(FLASH_BANK2_END)
00934   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
00935 #else
00936   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
00937 #endif /* FLASH_BANK2_END */
00938   {
00939     pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
00940 #if defined(FLASH_BANK2_END)
00941     flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
00942 #else
00943     flags |= FLASH_FLAG_WRPERR;
00944 #endif /* FLASH_BANK2_END */
00945   }
00946 #if defined(FLASH_BANK2_END)
00947   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
00948 #else
00949   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
00950 #endif /* FLASH_BANK2_END */
00951   {
00952     pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
00953 #if defined(FLASH_BANK2_END)
00954     flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
00955 #else
00956     flags |= FLASH_FLAG_PGERR;
00957 #endif /* FLASH_BANK2_END */
00958   }
00959   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
00960   {
00961     pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
00962   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
00963   }
00964
00965   /* Clear FLASH error pending bits */
00966   __HAL_FLASH_CLEAR_FLAG(flags);
00967 }
00968 /**
00969   * @}
00970   */
00971
00972 /**
00973   * @}
00974   */
00975
00976 #endif /* HAL_FLASH_MODULE_ENABLED */
00977
00978 /**
00979   * @}
00980   */
00981
00982 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_flash.h Source File

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stm32f1xx_hal_flash.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_flash.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of Flash HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_FLASH_H
00040 #define __STM32F1xx_HAL_FLASH_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASH
00054   * @{
00055   */
00056
00057 /** @addtogroup FLASH_Private_Constants
00058   * @{
00059   */
00060 #define FLASH_TIMEOUT_VALUE              50000U /* 50 s */
00061 /**
00062   * @}
00063   */
00064
00065 /** @addtogroup FLASH_Private_Macros
00066   * @{
00067   */
00068
00069 #define IS_FLASH_TYPEPROGRAM(VALUE)  (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
00070                                       ((VALUE) == FLASH_TYPEPROGRAM_WORD)     || \
00071                                       ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
00072
00073 #if   defined(FLASH_ACR_LATENCY)
00074 #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
00075                                        ((__LATENCY__) == FLASH_LATENCY_1) || \
00076                                        ((__LATENCY__) == FLASH_LATENCY_2))
00077
00078 #else
00079 #define IS_FLASH_LATENCY(__LATENCY__)   ((__LATENCY__) == FLASH_LATENCY_0)
00080 #endif /* FLASH_ACR_LATENCY */
00081 /**
00082   * @}
00083   */
00084
00085 /* Exported types ------------------------------------------------------------*/
00086 /** @defgroup FLASH_Exported_Types FLASH Exported Types
00087   * @{
00088   */
00089
00090 /**
00091   * @brief  FLASH Procedure structure definition
00092   */
00093 typedef enum
00094 {
00095   FLASH_PROC_NONE              = 0U,
00096   FLASH_PROC_PAGEERASE         = 1U,
00097   FLASH_PROC_MASSERASE         = 2U,
00098   FLASH_PROC_PROGRAMHALFWORD   = 3U,
00099   FLASH_PROC_PROGRAMWORD       = 4U,
00100   FLASH_PROC_PROGRAMDOUBLEWORD = 5U
00101 } FLASH_ProcedureTypeDef;
00102
00103 /**
00104   * @brief  FLASH handle Structure definition
00105   */
00106 typedef struct
00107 {
00108   __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
00109
00110   __IO uint32_t               DataRemaining;    /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
00111
00112   __IO uint32_t               Address;          /*!< Internal variable to save address selected for program or erase */
00113
00114   __IO uint64_t               Data;             /*!< Internal variable to save data to be programmed */
00115
00116   HAL_LockTypeDef             Lock;             /*!< FLASH locking object                */
00117
00118   __IO uint32_t               ErrorCode;        /*!< FLASH error code
00119                                                      This parameter can be a value of @ref FLASH_Error_Codes  */
00120 } FLASH_ProcessTypeDef;
00121
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported constants --------------------------------------------------------*/
00127 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
00128   * @{
00129   */
00130
00131 /** @defgroup FLASH_Error_Codes FLASH Error Codes
00132   * @{
00133   */
00134
00135 #define HAL_FLASH_ERROR_NONE      0x00U  /*!< No error */
00136 #define HAL_FLASH_ERROR_PROG      0x01U  /*!< Programming error */
00137 #define HAL_FLASH_ERROR_WRP       0x02U  /*!< Write protection error */
00138 #define HAL_FLASH_ERROR_OPTV      0x04U  /*!< Option validity error */
00139
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup FLASH_Type_Program FLASH Type Program
00145   * @{
00146   */
00147 #define FLASH_TYPEPROGRAM_HALFWORD             0x01U  /*!<Program a half-word (16-bit) at a specified address.*/
00148 #define FLASH_TYPEPROGRAM_WORD                 0x02U  /*!<Program a word (32-bit) at a specified address.*/
00149 #define FLASH_TYPEPROGRAM_DOUBLEWORD           0x03U  /*!<Program a double word (64-bit) at a specified address*/
00150
00151 /**
00152   * @}
00153   */
00154
00155 #if   defined(FLASH_ACR_LATENCY)
00156 /** @defgroup FLASH_Latency FLASH Latency
00157   * @{
00158   */
00159 #define FLASH_LATENCY_0            0x00000000U               /*!< FLASH Zero Latency cycle */
00160 #define FLASH_LATENCY_1            FLASH_ACR_LATENCY_0       /*!< FLASH One Latency cycle */
00161 #define FLASH_LATENCY_2            FLASH_ACR_LATENCY_1       /*!< FLASH Two Latency cycles */
00162
00163 /**
00164   * @}
00165   */
00166
00167 #else
00168 /** @defgroup FLASH_Latency FLASH Latency
00169   * @{
00170   */
00171 #define FLASH_LATENCY_0            0x00000000U    /*!< FLASH Zero Latency cycle */
00172
00173 /**
00174   * @}
00175   */
00176
00177 #endif /* FLASH_ACR_LATENCY */
00178 /**
00179   * @}
00180   */
00181
00182 /* Exported macro ------------------------------------------------------------*/
00183
00184 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
00185  *  @brief macros to control FLASH features
00186  *  @{
00187  */
00188
00189 /** @defgroup FLASH_Half_Cycle FLASH Half Cycle
00190  *  @brief macros to handle FLASH half cycle
00191  * @{
00192  */
00193
00194 /**
00195   * @brief  Enable the FLASH half cycle access.
00196   * @note   half cycle access can only be used with a low-frequency clock of less than
00197             8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
00198   * @retval None
00199   */
00200 #define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE()  (FLASH->ACR |= FLASH_ACR_HLFCYA)
00201
00202 /**
00203   * @brief  Disable the FLASH half cycle access.
00204   * @note   half cycle access can only be used with a low-frequency clock of less than
00205             8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
00206   * @retval None
00207   */
00208 #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
00209
00210 /**
00211   * @}
00212   */
00213
00214 #if defined(FLASH_ACR_LATENCY)
00215 /** @defgroup FLASH_EM_Latency FLASH Latency
00216  *  @brief macros to handle FLASH Latency
00217  * @{
00218  */
00219
00220 /**
00221   * @brief  Set the FLASH Latency.
00222   * @param  __LATENCY__ FLASH Latency
00223   *         The value of this parameter depend on device used within the same series
00224   * @retval None
00225   */
00226 #define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
00227
00228
00229 /**
00230   * @brief  Get the FLASH Latency.
00231   * @retval FLASH Latency
00232   *         The value of this parameter depend on device used within the same series
00233   */
00234 #define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
00235
00236 /**
00237   * @}
00238   */
00239
00240 #endif /* FLASH_ACR_LATENCY */
00241 /** @defgroup FLASH_Prefetch FLASH Prefetch
00242  *  @brief macros to handle FLASH Prefetch buffer
00243  * @{
00244  */
00245 /**
00246   * @brief  Enable the FLASH prefetch buffer.
00247   * @retval None
00248   */
00249 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    (FLASH->ACR |= FLASH_ACR_PRFTBE)
00250
00251 /**
00252   * @brief  Disable the FLASH prefetch buffer.
00253   * @retval None
00254   */
00255 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
00256
00257 /**
00258   * @}
00259   */
00260
00261 /**
00262   * @}
00263   */
00264
00265 /* Include FLASH HAL Extended module */
00266 #include "stm32f1xx_hal_flash_ex.h"
00267
00268 /* Exported functions --------------------------------------------------------*/
00269 /** @addtogroup FLASH_Exported_Functions
00270   * @{
00271   */
00272
00273 /** @addtogroup FLASH_Exported_Functions_Group1
00274   * @{
00275   */
00276 /* IO operation functions *****************************************************/
00277 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00278 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
00279
00280 /* FLASH IRQ handler function */
00281 void       HAL_FLASH_IRQHandler(void);
00282 /* Callbacks in non blocking modes */
00283 void       HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
00284 void       HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
00285
00286 /**
00287   * @}
00288   */
00289
00290 /** @addtogroup FLASH_Exported_Functions_Group2
00291   * @{
00292   */
00293 /* Peripheral Control functions ***********************************************/
00294 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
00295 HAL_StatusTypeDef HAL_FLASH_Lock(void);
00296 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
00297 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
00298 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @addtogroup FLASH_Exported_Functions_Group3
00305   * @{
00306   */
00307 /* Peripheral State and Error functions ***************************************/
00308 uint32_t HAL_FLASH_GetError(void);
00309
00310 /**
00311   * @}
00312   */
00313
00314 /**
00315   * @}
00316   */
00317
00318 /* Private function -------------------------------------------------*/
00319 /** @addtogroup FLASH_Private_Functions
00320  * @{
00321  */
00322 HAL_StatusTypeDef       FLASH_WaitForLastOperation(uint32_t Timeout);
00323 #if defined(FLASH_BANK2_END)
00324 HAL_StatusTypeDef       FLASH_WaitForLastOperationBank2(uint32_t Timeout);
00325 #endif /* FLASH_BANK2_END */
00326
00327 /**
00328   * @}
00329   */
00330
00331 /**
00332   * @}
00333   */
00334
00335 /**
00336   * @}
00337   */
00338
00339 #ifdef __cplusplus
00340 }
00341 #endif
00342
00343 #endif /* __STM32F1xx_HAL_FLASH_H */
00344
00345 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00346
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_flash_ex.c Source File

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stm32f1xx_hal_flash_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_flash_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Extended FLASH HAL module driver.
00008   *
00009   *          This file provides firmware functions to manage the following
00010   *          functionalities of the FLASH peripheral:
00011   *           + Extended Initialization/de-initialization functions
00012   *           + Extended I/O operation functions
00013   *           + Extended Peripheral Control functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                ##### Flash peripheral extended features  #####
00018   ==============================================================================
00019
00020                       ##### How to use this driver #####
00021   ==============================================================================
00022   [..] This driver provides functions to configure and program the FLASH memory
00023        of all STM32F1xxx devices. It includes
00024
00025         (++) Set/Reset the write protection
00026         (++) Program the user Option Bytes
00027         (++) Get the Read protection Level
00028
00029   @endverbatim
00030   ******************************************************************************
00031   * @attention
00032   *
00033   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00034   *
00035   * Redistribution and use in source and binary forms, with or without modification,
00036   * are permitted provided that the following conditions are met:
00037   *   1. Redistributions of source code must retain the above copyright notice,
00038   *      this list of conditions and the following disclaimer.
00039   *   2. Redistributions in binary form must reproduce the above copyright notice,
00040   *      this list of conditions and the following disclaimer in the documentation
00041   *      and/or other materials provided with the distribution.
00042   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00043   *      may be used to endorse or promote products derived from this software
00044   *      without specific prior written permission.
00045   *
00046   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00047   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00048   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00049   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00050   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00051   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00052   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00053   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00054   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00055   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00056   *
00057   ******************************************************************************
00058   */
00059
00060 /* Includes ------------------------------------------------------------------*/
00061 #include "stm32f1xx_hal.h"
00062
00063 /** @addtogroup STM32F1xx_HAL_Driver
00064   * @{
00065   */
00066 #ifdef HAL_FLASH_MODULE_ENABLED
00067
00068 /** @addtogroup FLASH
00069   * @{
00070   */
00071 /** @addtogroup FLASH_Private_Variables
00072  * @{
00073  */
00074 /* Variables used for Erase pages under interruption*/
00075 extern FLASH_ProcessTypeDef pFlash;
00076 /**
00077   * @}
00078   */
00079
00080 /**
00081   * @}
00082   */
00083
00084 /** @defgroup FLASHEx FLASHEx
00085   * @brief FLASH HAL Extension module driver
00086   * @{
00087   */
00088
00089 /* Private typedef -----------------------------------------------------------*/
00090 /* Private define ------------------------------------------------------------*/
00091 /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
00092  * @{
00093  */
00094 #define FLASH_POSITION_IWDGSW_BIT        FLASH_OBR_IWDG_SW_Pos
00095 #define FLASH_POSITION_OB_USERDATA0_BIT  FLASH_OBR_DATA0_Pos
00096 #define FLASH_POSITION_OB_USERDATA1_BIT  FLASH_OBR_DATA1_Pos
00097 /**
00098   * @}
00099   */
00100
00101 /* Private macro -------------------------------------------------------------*/
00102 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
00103   * @{
00104   */
00105 /**
00106   * @}
00107   */
00108
00109 /* Private variables ---------------------------------------------------------*/
00110 /* Private function prototypes -----------------------------------------------*/
00111 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
00112  * @{
00113  */
00114 /* Erase operations */
00115 static void              FLASH_MassErase(uint32_t Banks);
00116 void    FLASH_PageErase(uint32_t PageAddress);
00117
00118 /* Option bytes control */
00119 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
00120 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage);
00121 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel);
00122 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig);
00123 static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
00124 static uint32_t          FLASH_OB_GetWRP(void);
00125 static uint32_t          FLASH_OB_GetRDP(void);
00126 static uint8_t           FLASH_OB_GetUser(void);
00127
00128 /**
00129   * @}
00130   */
00131
00132 /* Exported functions ---------------------------------------------------------*/
00133 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
00134   * @{
00135   */
00136
00137 /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions
00138  *  @brief   FLASH Memory Erasing functions
00139   *
00140 @verbatim
00141   ==============================================================================
00142                 ##### FLASH Erasing Programming functions #####
00143   ==============================================================================
00144
00145     [..] The FLASH Memory Erasing functions, includes the following functions:
00146     (+) @ref HAL_FLASHEx_Erase: return only when erase has been done
00147     (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback
00148         is called with parameter 0xFFFFFFFF
00149
00150     [..] Any operation of erase should follow these steps:
00151     (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and
00152         program memory access.
00153     (#) Call the desired function to erase page.
00154     (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access
00155        (recommended to protect the FLASH memory against possible unwanted operation).
00156
00157 @endverbatim
00158   * @{
00159   */
00160
00161
00162 /**
00163   * @brief  Perform a mass erase or erase the specified FLASH memory pages
00164   * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
00165   *         must be called before.
00166   *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
00167   *         (recommended to protect the FLASH memory against possible unwanted operation)
00168   * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
00169   *         contains the configuration information for the erasing.
00170   *
00171   * @param[out]  PageError pointer to variable  that
00172   *         contains the configuration information on faulty page in case of error
00173   *         (0xFFFFFFFF means that all the pages have been correctly erased)
00174   *
00175   * @retval HAL_StatusTypeDef HAL Status
00176   */
00177 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
00178 {
00179   HAL_StatusTypeDef status = HAL_ERROR;
00180   uint32_t address = 0U;
00181
00182   /* Process Locked */
00183   __HAL_LOCK(&pFlash);
00184
00185   /* Check the parameters */
00186   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00187
00188   if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00189   {
00190 #if defined(FLASH_BANK2_END)
00191     if (pEraseInit->Banks == FLASH_BANK_BOTH)
00192     {
00193       /* Mass Erase requested for Bank1 and Bank2 */
00194       /* Wait for last operation to be completed */
00195       if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
00196           (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
00197       {
00198         /*Mass erase to be done*/
00199         FLASH_MassErase(FLASH_BANK_BOTH);
00200
00201         /* Wait for last operation to be completed */
00202         if ((FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) && \
00203             (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK))
00204         {
00205           status = HAL_OK;
00206         }
00207
00208         /* If the erase operation is completed, disable the MER Bit */
00209         CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
00210         CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
00211       }
00212     }
00213     else if (pEraseInit->Banks == FLASH_BANK_2)
00214     {
00215       /* Mass Erase requested for Bank2 */
00216       /* Wait for last operation to be completed */
00217       if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
00218       {
00219         /*Mass erase to be done*/
00220         FLASH_MassErase(FLASH_BANK_2);
00221
00222         /* Wait for last operation to be completed */
00223         status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
00224
00225         /* If the erase operation is completed, disable the MER Bit */
00226         CLEAR_BIT(FLASH->CR2, FLASH_CR2_MER);
00227       }
00228     }
00229     else
00230 #endif /* FLASH_BANK2_END */
00231     {
00232       /* Mass Erase requested for Bank1 */
00233       /* Wait for last operation to be completed */
00234       if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
00235       {
00236         /*Mass erase to be done*/
00237         FLASH_MassErase(FLASH_BANK_1);
00238
00239         /* Wait for last operation to be completed */
00240         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00241
00242         /* If the erase operation is completed, disable the MER Bit */
00243         CLEAR_BIT(FLASH->CR, FLASH_CR_MER);
00244       }
00245     }
00246   }
00247   else
00248   {
00249     /* Page Erase is requested */
00250     /* Check the parameters */
00251     assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
00252     assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
00253
00254 #if defined(FLASH_BANK2_END)
00255     /* Page Erase requested on address located on bank2 */
00256     if(pEraseInit->PageAddress > FLASH_BANK1_END)
00257     {
00258       /* Wait for last operation to be completed */
00259       if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
00260       {
00261         /*Initialization of PageError variable*/
00262         *PageError = 0xFFFFFFFFU;
00263
00264         /* Erase by page by page to be done*/
00265         for(address = pEraseInit->PageAddress;
00266             address < (pEraseInit->PageAddress + (pEraseInit->NbPages)*FLASH_PAGE_SIZE);
00267             address += FLASH_PAGE_SIZE)
00268         {
00269           FLASH_PageErase(address);
00270
00271           /* Wait for last operation to be completed */
00272           status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
00273
00274           /* If the erase operation is completed, disable the PER Bit */
00275           CLEAR_BIT(FLASH->CR2, FLASH_CR2_PER);
00276
00277           if (status != HAL_OK)
00278           {
00279             /* In case of error, stop erase procedure and return the faulty address */
00280             *PageError = address;
00281             break;
00282           }
00283         }
00284       }
00285     }
00286     else
00287 #endif /* FLASH_BANK2_END */
00288    {
00289       /* Page Erase requested on address located on bank1 */
00290       /* Wait for last operation to be completed */
00291       if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
00292       {
00293         /*Initialization of PageError variable*/
00294         *PageError = 0xFFFFFFFFU;
00295
00296         /* Erase page by page to be done*/
00297         for(address = pEraseInit->PageAddress;
00298             address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress);
00299             address += FLASH_PAGE_SIZE)
00300         {
00301           FLASH_PageErase(address);
00302
00303           /* Wait for last operation to be completed */
00304           status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00305
00306           /* If the erase operation is completed, disable the PER Bit */
00307           CLEAR_BIT(FLASH->CR, FLASH_CR_PER);
00308
00309           if (status != HAL_OK)
00310           {
00311             /* In case of error, stop erase procedure and return the faulty address */
00312             *PageError = address;
00313             break;
00314           }
00315         }
00316       }
00317     }
00318   }
00319
00320   /* Process Unlocked */
00321   __HAL_UNLOCK(&pFlash);
00322
00323   return status;
00324 }
00325
00326 /**
00327   * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled
00328   * @note   To correctly run this function, the @ref HAL_FLASH_Unlock() function
00329   *         must be called before.
00330   *         Call the @ref HAL_FLASH_Lock() to disable the flash memory access
00331   *         (recommended to protect the FLASH memory against possible unwanted operation)
00332   * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
00333   *         contains the configuration information for the erasing.
00334   *
00335   * @retval HAL_StatusTypeDef HAL Status
00336   */
00337 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
00338 {
00339   HAL_StatusTypeDef status = HAL_OK;
00340
00341   /* Process Locked */
00342   __HAL_LOCK(&pFlash);
00343
00344   /* If procedure already ongoing, reject the next one */
00345   if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
00346   {
00347     return HAL_ERROR;
00348   }
00349
00350   /* Check the parameters */
00351   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
00352
00353   /* Enable End of FLASH Operation and Error source interrupts */
00354   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
00355
00356 #if defined(FLASH_BANK2_END)
00357   /* Enable End of FLASH Operation and Error source interrupts */
00358   __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP_BANK2 | FLASH_IT_ERR_BANK2);
00359
00360 #endif
00361   if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
00362   {
00363     /*Mass erase to be done*/
00364     pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
00365         FLASH_MassErase(pEraseInit->Banks);
00366   }
00367   else
00368   {
00369     /* Erase by page to be done*/
00370
00371     /* Check the parameters */
00372     assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
00373     assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages));
00374
00375     pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
00376     pFlash.DataRemaining = pEraseInit->NbPages;
00377     pFlash.Address = pEraseInit->PageAddress;
00378
00379     /*Erase 1st page and wait for IT*/
00380     FLASH_PageErase(pEraseInit->PageAddress);
00381   }
00382
00383   return status;
00384 }
00385
00386 /**
00387   * @}
00388   */
00389
00390 /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
00391  *  @brief   Option Bytes Programming functions
00392   *
00393 @verbatim
00394   ==============================================================================
00395                 ##### Option Bytes Programming functions #####
00396   ==============================================================================
00397     [..]
00398     This subsection provides a set of functions allowing to control the FLASH
00399     option bytes operations.
00400
00401 @endverbatim
00402   * @{
00403   */
00404
00405 /**
00406   * @brief  Erases the FLASH option bytes.
00407   * @note   This functions erases all option bytes except the Read protection (RDP).
00408   *         The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
00409   *         The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
00410   *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
00411   *         (system reset will occur)
00412   * @retval HAL status
00413   */
00414
00415 HAL_StatusTypeDef HAL_FLASHEx_OBErase(void)
00416 {
00417   uint8_t rdptmp = OB_RDP_LEVEL_0;
00418   HAL_StatusTypeDef status = HAL_ERROR;
00419
00420   /* Get the actual read protection Option Byte value */
00421   rdptmp = FLASH_OB_GetRDP();
00422
00423   /* Wait for last operation to be completed */
00424   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00425
00426   if(status == HAL_OK)
00427   {
00428     /* Clean the error context */
00429     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00430
00431     /* If the previous operation is completed, proceed to erase the option bytes */
00432     SET_BIT(FLASH->CR, FLASH_CR_OPTER);
00433     SET_BIT(FLASH->CR, FLASH_CR_STRT);
00434
00435     /* Wait for last operation to be completed */
00436     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00437
00438     /* If the erase operation is completed, disable the OPTER Bit */
00439     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
00440
00441     if(status == HAL_OK)
00442     {
00443       /* Restore the last read protection Option Byte value */
00444       status = FLASH_OB_RDP_LevelConfig(rdptmp);
00445     }
00446   }
00447
00448   /* Return the erase status */
00449   return status;
00450 }
00451
00452 /**
00453   * @brief  Program option bytes
00454   * @note   The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
00455   *         The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
00456   *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
00457   *         (system reset will occur)
00458   *
00459   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
00460   *         contains the configuration information for the programming.
00461   *
00462   * @retval HAL_StatusTypeDef HAL Status
00463   */
00464 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
00465 {
00466   HAL_StatusTypeDef status = HAL_ERROR;
00467
00468   /* Process Locked */
00469   __HAL_LOCK(&pFlash);
00470
00471   /* Check the parameters */
00472   assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
00473
00474   /* Write protection configuration */
00475   if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
00476   {
00477     assert_param(IS_WRPSTATE(pOBInit->WRPState));
00478     if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
00479     {
00480       /* Enable of Write protection on the selected page */
00481       status = FLASH_OB_EnableWRP(pOBInit->WRPPage);
00482     }
00483     else
00484     {
00485       /* Disable of Write protection on the selected page */
00486       status = FLASH_OB_DisableWRP(pOBInit->WRPPage);
00487     }
00488     if (status != HAL_OK)
00489     {
00490       /* Process Unlocked */
00491       __HAL_UNLOCK(&pFlash);
00492       return status;
00493     }
00494   }
00495
00496   /* Read protection configuration */
00497   if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
00498   {
00499     status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
00500     if (status != HAL_OK)
00501     {
00502       /* Process Unlocked */
00503       __HAL_UNLOCK(&pFlash);
00504       return status;
00505     }
00506   }
00507
00508   /* USER configuration */
00509   if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
00510   {
00511     status = FLASH_OB_UserConfig(pOBInit->USERConfig);
00512     if (status != HAL_OK)
00513     {
00514       /* Process Unlocked */
00515       __HAL_UNLOCK(&pFlash);
00516       return status;
00517     }
00518   }
00519
00520   /* DATA configuration*/
00521   if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA)
00522   {
00523     status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData);
00524     if (status != HAL_OK)
00525     {
00526       /* Process Unlocked */
00527       __HAL_UNLOCK(&pFlash);
00528       return status;
00529     }
00530   }
00531
00532   /* Process Unlocked */
00533   __HAL_UNLOCK(&pFlash);
00534
00535   return status;
00536 }
00537
00538 /**
00539   * @brief  Get the Option byte configuration
00540   * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
00541   *         contains the configuration information for the programming.
00542   *
00543   * @retval None
00544   */
00545 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
00546 {
00547   pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER;
00548
00549   /*Get WRP*/
00550   pOBInit->WRPPage = FLASH_OB_GetWRP();
00551
00552   /*Get RDP Level*/
00553   pOBInit->RDPLevel = FLASH_OB_GetRDP();
00554
00555   /*Get USER*/
00556   pOBInit->USERConfig = FLASH_OB_GetUser();
00557 }
00558
00559 /**
00560   * @brief  Get the Option byte user data
00561   * @param  DATAAdress Address of the option byte DATA
00562   *          This parameter can be one of the following values:
00563   *            @arg @ref OB_DATA_ADDRESS_DATA0
00564   *            @arg @ref OB_DATA_ADDRESS_DATA1
00565   * @retval Value programmed in USER data
00566   */
00567 uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress)
00568 {
00569   uint32_t value = 0;
00570
00571   if (DATAAdress == OB_DATA_ADDRESS_DATA0)
00572   {
00573     /* Get value programmed in OB USER Data0 */
00574     value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT;
00575   }
00576   else
00577   {
00578     /* Get value programmed in OB USER Data1 */
00579     value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT;
00580   }
00581
00582   return value;
00583 }
00584
00585 /**
00586   * @}
00587   */
00588
00589 /**
00590   * @}
00591   */
00592
00593 /** @addtogroup FLASHEx_Private_Functions
00594  * @{
00595  */
00596
00597 /**
00598   * @brief  Full erase of FLASH memory Bank
00599   * @param  Banks Banks to be erased
00600   *          This parameter can be one of the following values:
00601   *            @arg @ref FLASH_BANK_1 Bank1 to be erased
00602   @if STM32F101xG
00603   *            @arg @ref FLASH_BANK_2 Bank2 to be erased
00604   *            @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
00605   @endif
00606   @if STM32F103xG
00607   *            @arg @ref FLASH_BANK_2 Bank2 to be erased
00608   *            @arg @ref FLASH_BANK_BOTH Bank1 and Bank2 to be erased
00609   @endif
00610   *
00611   * @retval None
00612   */
00613 static void FLASH_MassErase(uint32_t Banks)
00614 {
00615   /* Check the parameters */
00616   assert_param(IS_FLASH_BANK(Banks));
00617
00618   /* Clean the error context */
00619   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00620
00621 #if defined(FLASH_BANK2_END)
00622   if(Banks == FLASH_BANK_BOTH)
00623   {
00624     /* bank1 & bank2 will be erased*/
00625     SET_BIT(FLASH->CR, FLASH_CR_MER);
00626     SET_BIT(FLASH->CR2, FLASH_CR2_MER);
00627     SET_BIT(FLASH->CR, FLASH_CR_STRT);
00628     SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
00629   }
00630   else if(Banks == FLASH_BANK_2)
00631   {
00632     /*Only bank2 will be erased*/
00633     SET_BIT(FLASH->CR2, FLASH_CR2_MER);
00634     SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
00635   }
00636   else
00637   {
00638 #endif /* FLASH_BANK2_END */
00639     /* Only bank1 will be erased*/
00640     SET_BIT(FLASH->CR, FLASH_CR_MER);
00641     SET_BIT(FLASH->CR, FLASH_CR_STRT);
00642 #if defined(FLASH_BANK2_END)
00643   }
00644 #endif /* FLASH_BANK2_END */
00645 }
00646
00647 /**
00648   * @brief  Enable the write protection of the desired pages
00649   * @note   An option byte erase is done automatically in this function.
00650   * @note   When the memory read protection level is selected (RDP level = 1),
00651   *         it is not possible to program or erase the flash page i if
00652   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
00653   *
00654   * @param  WriteProtectPage specifies the page(s) to be write protected.
00655   *         The value of this parameter depend on device used within the same series
00656   * @retval HAL status
00657   */
00658 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage)
00659 {
00660   HAL_StatusTypeDef status = HAL_OK;
00661   uint16_t WRP0_Data = 0xFFFF;
00662 #if defined(FLASH_WRP1_WRP1)
00663   uint16_t WRP1_Data = 0xFFFF;
00664 #endif /* FLASH_WRP1_WRP1 */
00665 #if defined(FLASH_WRP2_WRP2)
00666   uint16_t WRP2_Data = 0xFFFF;
00667 #endif /* FLASH_WRP2_WRP2 */
00668 #if defined(FLASH_WRP3_WRP3)
00669   uint16_t WRP3_Data = 0xFFFF;
00670 #endif /* FLASH_WRP3_WRP3 */
00671
00672   /* Check the parameters */
00673   assert_param(IS_OB_WRP(WriteProtectPage));
00674
00675   /* Get current write protected pages and the new pages to be protected ******/
00676   WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage));
00677
00678 #if defined(OB_WRP_PAGES0TO15MASK)
00679   WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
00680 #elif defined(OB_WRP_PAGES0TO31MASK)
00681   WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
00682 #endif /* OB_WRP_PAGES0TO31MASK */
00683
00684 #if defined(OB_WRP_PAGES16TO31MASK)
00685   WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
00686 #elif defined(OB_WRP_PAGES32TO63MASK)
00687   WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
00688 #endif /* OB_WRP_PAGES32TO63MASK */
00689
00690 #if defined(OB_WRP_PAGES64TO95MASK)
00691   WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);
00692 #endif /* OB_WRP_PAGES64TO95MASK */
00693 #if defined(OB_WRP_PAGES32TO47MASK)
00694   WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
00695 #endif /* OB_WRP_PAGES32TO47MASK */
00696
00697 #if defined(OB_WRP_PAGES96TO127MASK)
00698   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U);
00699 #elif defined(OB_WRP_PAGES48TO255MASK)
00700   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
00701 #elif defined(OB_WRP_PAGES48TO511MASK)
00702   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U);
00703 #elif defined(OB_WRP_PAGES48TO127MASK)
00704   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
00705 #endif /* OB_WRP_PAGES96TO127MASK */
00706
00707   /* Wait for last operation to be completed */
00708   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00709
00710   if(status == HAL_OK)
00711   {
00712     /* Clean the error context */
00713     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00714
00715     /* To be able to write again option byte, need to perform a option byte erase */
00716     status = HAL_FLASHEx_OBErase();
00717     if (status == HAL_OK)
00718     {
00719       /* Enable write protection */
00720       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
00721
00722 #if defined(FLASH_WRP0_WRP0)
00723       if(WRP0_Data != 0xFFU)
00724       {
00725         OB->WRP0 &= WRP0_Data;
00726
00727         /* Wait for last operation to be completed */
00728         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00729       }
00730 #endif /* FLASH_WRP0_WRP0 */
00731
00732 #if defined(FLASH_WRP1_WRP1)
00733       if((status == HAL_OK) && (WRP1_Data != 0xFFU))
00734       {
00735         OB->WRP1 &= WRP1_Data;
00736
00737         /* Wait for last operation to be completed */
00738         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00739       }
00740 #endif /* FLASH_WRP1_WRP1 */
00741
00742 #if defined(FLASH_WRP2_WRP2)
00743       if((status == HAL_OK) && (WRP2_Data != 0xFFU))
00744       {
00745         OB->WRP2 &= WRP2_Data;
00746
00747         /* Wait for last operation to be completed */
00748         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00749       }
00750 #endif /* FLASH_WRP2_WRP2 */
00751
00752 #if defined(FLASH_WRP3_WRP3)
00753       if((status == HAL_OK) && (WRP3_Data != 0xFFU))
00754       {
00755         OB->WRP3 &= WRP3_Data;
00756
00757         /* Wait for last operation to be completed */
00758         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00759       }
00760 #endif /* FLASH_WRP3_WRP3 */
00761
00762       /* if the program operation is completed, disable the OPTPG Bit */
00763       CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
00764     }
00765   }
00766
00767   return status;
00768 }
00769
00770 /**
00771   * @brief  Disable the write protection of the desired pages
00772   * @note   An option byte erase is done automatically in this function.
00773   * @note   When the memory read protection level is selected (RDP level = 1),
00774   *         it is not possible to program or erase the flash page i if
00775   *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
00776   *
00777   * @param  WriteProtectPage specifies the page(s) to be write unprotected.
00778   *         The value of this parameter depend on device used within the same series
00779   * @retval HAL status
00780   */
00781 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage)
00782 {
00783   HAL_StatusTypeDef status = HAL_OK;
00784   uint16_t WRP0_Data = 0xFFFF;
00785 #if defined(FLASH_WRP1_WRP1)
00786   uint16_t WRP1_Data = 0xFFFF;
00787 #endif /* FLASH_WRP1_WRP1 */
00788 #if defined(FLASH_WRP2_WRP2)
00789   uint16_t WRP2_Data = 0xFFFF;
00790 #endif /* FLASH_WRP2_WRP2 */
00791 #if defined(FLASH_WRP3_WRP3)
00792   uint16_t WRP3_Data = 0xFFFF;
00793 #endif /* FLASH_WRP3_WRP3 */
00794
00795   /* Check the parameters */
00796   assert_param(IS_OB_WRP(WriteProtectPage));
00797
00798   /* Get current write protected pages and the new pages to be unprotected ******/
00799   WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage);
00800
00801 #if defined(OB_WRP_PAGES0TO15MASK)
00802   WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK);
00803 #elif defined(OB_WRP_PAGES0TO31MASK)
00804   WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO31MASK);
00805 #endif /* OB_WRP_PAGES0TO31MASK */
00806
00807 #if defined(OB_WRP_PAGES16TO31MASK)
00808   WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
00809 #elif defined(OB_WRP_PAGES32TO63MASK)
00810   WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
00811 #endif /* OB_WRP_PAGES32TO63MASK */
00812
00813 #if defined(OB_WRP_PAGES64TO95MASK)
00814   WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);
00815 #endif /* OB_WRP_PAGES64TO95MASK */
00816 #if defined(OB_WRP_PAGES32TO47MASK)
00817   WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
00818 #endif /* OB_WRP_PAGES32TO47MASK */
00819
00820 #if defined(OB_WRP_PAGES96TO127MASK)
00821   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U);
00822 #elif defined(OB_WRP_PAGES48TO255MASK)
00823   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
00824 #elif defined(OB_WRP_PAGES48TO511MASK)
00825   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U);
00826 #elif defined(OB_WRP_PAGES48TO127MASK)
00827   WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
00828 #endif /* OB_WRP_PAGES96TO127MASK */
00829
00830
00831   /* Wait for last operation to be completed */
00832   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00833
00834   if(status == HAL_OK)
00835   {
00836     /* Clean the error context */
00837     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00838
00839     /* To be able to write again option byte, need to perform a option byte erase */
00840     status = HAL_FLASHEx_OBErase();
00841     if (status == HAL_OK)
00842     {
00843       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
00844
00845 #if defined(FLASH_WRP0_WRP0)
00846       if(WRP0_Data != 0xFFU)
00847       {
00848         OB->WRP0 |= WRP0_Data;
00849
00850         /* Wait for last operation to be completed */
00851         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00852       }
00853 #endif /* FLASH_WRP0_WRP0 */
00854
00855 #if defined(FLASH_WRP1_WRP1)
00856       if((status == HAL_OK) && (WRP1_Data != 0xFFU))
00857       {
00858         OB->WRP1 |= WRP1_Data;
00859
00860         /* Wait for last operation to be completed */
00861         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00862       }
00863 #endif /* FLASH_WRP1_WRP1 */
00864
00865 #if defined(FLASH_WRP2_WRP2)
00866       if((status == HAL_OK) && (WRP2_Data != 0xFFU))
00867       {
00868         OB->WRP2 |= WRP2_Data;
00869
00870         /* Wait for last operation to be completed */
00871         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00872       }
00873 #endif /* FLASH_WRP2_WRP2 */
00874
00875 #if defined(FLASH_WRP3_WRP3)
00876       if((status == HAL_OK) && (WRP3_Data != 0xFFU))
00877       {
00878         OB->WRP3 |= WRP3_Data;
00879
00880         /* Wait for last operation to be completed */
00881         status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00882       }
00883 #endif /* FLASH_WRP3_WRP3 */
00884
00885       /* if the program operation is completed, disable the OPTPG Bit */
00886       CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
00887     }
00888   }
00889   return status;
00890 }
00891
00892 /**
00893   * @brief  Set the read protection level.
00894   * @param  ReadProtectLevel specifies the read protection level.
00895   *         This parameter can be one of the following values:
00896   *            @arg @ref OB_RDP_LEVEL_0 No protection
00897   *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
00898   * @retval HAL status
00899   */
00900 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel)
00901 {
00902   HAL_StatusTypeDef status = HAL_OK;
00903
00904   /* Check the parameters */
00905   assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel));
00906
00907   /* Wait for last operation to be completed */
00908   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00909
00910   if(status == HAL_OK)
00911   {
00912     /* Clean the error context */
00913     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00914
00915     /* If the previous operation is completed, proceed to erase the option bytes */
00916     SET_BIT(FLASH->CR, FLASH_CR_OPTER);
00917     SET_BIT(FLASH->CR, FLASH_CR_STRT);
00918
00919     /* Wait for last operation to be completed */
00920     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00921
00922     /* If the erase operation is completed, disable the OPTER Bit */
00923     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER);
00924
00925     if(status == HAL_OK)
00926     {
00927       /* Enable the Option Bytes Programming operation */
00928       SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
00929
00930       WRITE_REG(OB->RDP, ReadProtectLevel);
00931
00932       /* Wait for last operation to be completed */
00933       status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00934
00935       /* if the program operation is completed, disable the OPTPG Bit */
00936       CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
00937     }
00938   }
00939
00940   return status;
00941 }
00942
00943 /**
00944   * @brief  Program the FLASH User Option Byte.
00945   * @note   Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
00946   * @param  UserConfig The FLASH User Option Bytes values FLASH_OBR_IWDG_SW(Bit2),
00947   *         FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
00948   *         And BFBF2(Bit5) for STM32F101xG and STM32F103xG .
00949   * @retval HAL status
00950   */
00951 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig)
00952 {
00953   HAL_StatusTypeDef status = HAL_OK;
00954
00955   /* Check the parameters */
00956   assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW)));
00957   assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST)));
00958   assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST)));
00959 #if defined(FLASH_BANK2_END)
00960   assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET)));
00961 #endif /* FLASH_BANK2_END */
00962
00963   /* Wait for last operation to be completed */
00964   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00965
00966   if(status == HAL_OK)
00967   {
00968     /* Clean the error context */
00969     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
00970
00971     /* Enable the Option Bytes Programming operation */
00972     SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
00973
00974 #if defined(FLASH_BANK2_END)
00975     OB->USER = (UserConfig | 0xF0U);
00976 #else
00977     OB->USER = (UserConfig | 0x88U);
00978 #endif /* FLASH_BANK2_END */
00979
00980     /* Wait for last operation to be completed */
00981     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
00982
00983     /* if the program operation is completed, disable the OPTPG Bit */
00984     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
00985   }
00986
00987   return status;
00988 }
00989
00990 /**
00991   * @brief  Programs a half word at a specified Option Byte Data address.
00992   * @note   The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interface
00993   *         The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options bytes
00994   *         The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of the options bytes
00995   *         (system reset will occur)
00996   *         Programming of the OB should be performed only after an erase (otherwise PGERR occurs)
00997   * @param  Address specifies the address to be programmed.
00998   *         This parameter can be 0x1FFFF804 or 0x1FFFF806.
00999   * @param  Data specifies the data to be programmed.
01000   * @retval HAL status
01001   */
01002 static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
01003 {
01004   HAL_StatusTypeDef status = HAL_ERROR;
01005
01006   /* Check the parameters */
01007   assert_param(IS_OB_DATA_ADDRESS(Address));
01008
01009   /* Wait for last operation to be completed */
01010   status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01011
01012   if(status == HAL_OK)
01013   {
01014     /* Clean the error context */
01015     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
01016
01017     /* Enables the Option Bytes Programming operation */
01018     SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
01019     *(__IO uint16_t*)Address = Data;
01020
01021     /* Wait for last operation to be completed */
01022     status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
01023
01024     /* If the program operation is completed, disable the OPTPG Bit */
01025     CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG);
01026   }
01027   /* Return the Option Byte Data Program Status */
01028   return status;
01029 }
01030
01031 /**
01032   * @brief  Return the FLASH Write Protection Option Bytes value.
01033   * @retval The FLASH Write Protection Option Bytes value
01034   */
01035 static uint32_t FLASH_OB_GetWRP(void)
01036 {
01037   /* Return the FLASH write protection Register value */
01038   return (uint32_t)(READ_REG(FLASH->WRPR));
01039 }
01040
01041 /**
01042   * @brief  Returns the FLASH Read Protection level.
01043   * @retval FLASH RDP level
01044   *         This parameter can be one of the following values:
01045   *            @arg @ref OB_RDP_LEVEL_0 No protection
01046   *            @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
01047   */
01048 static uint32_t FLASH_OB_GetRDP(void)
01049 {
01050   uint32_t readstatus = OB_RDP_LEVEL_0;
01051   uint32_t tmp_reg = 0U;
01052
01053   /* Read RDP level bits */
01054   tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
01055
01056   if (tmp_reg == FLASH_OBR_RDPRT)
01057   {
01058     readstatus = OB_RDP_LEVEL_1;
01059   }
01060   else
01061   {
01062     readstatus = OB_RDP_LEVEL_0;
01063   }
01064
01065   return readstatus;
01066 }
01067
01068 /**
01069   * @brief  Return the FLASH User Option Byte value.
01070   * @retval The FLASH User Option Bytes values: FLASH_OBR_IWDG_SW(Bit2),
01071   *         FLASH_OBR_nRST_STOP(Bit3),FLASH_OBR_nRST_STDBY(Bit4).
01072   *         And FLASH_OBR_BFB2(Bit5) for STM32F101xG and STM32F103xG .
01073   */
01074 static uint8_t FLASH_OB_GetUser(void)
01075 {
01076   /* Return the User Option Byte */
01077   return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT);
01078 }
01079
01080 /**
01081   * @}
01082   */
01083
01084 /**
01085   * @}
01086   */
01087
01088 /** @addtogroup FLASH
01089   * @{
01090   */
01091
01092 /** @addtogroup FLASH_Private_Functions
01093  * @{
01094  */
01095
01096 /**
01097   * @brief  Erase the specified FLASH memory page
01098   * @param  PageAddress FLASH page to erase
01099   *         The value of this parameter depend on device used within the same series
01100   *
01101   * @retval None
01102   */
01103 void FLASH_PageErase(uint32_t PageAddress)
01104 {
01105   /* Clean the error context */
01106   pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
01107
01108 #if defined(FLASH_BANK2_END)
01109   if(PageAddress > FLASH_BANK1_END)
01110   {
01111     /* Proceed to erase the page */
01112     SET_BIT(FLASH->CR2, FLASH_CR2_PER);
01113     WRITE_REG(FLASH->AR2, PageAddress);
01114     SET_BIT(FLASH->CR2, FLASH_CR2_STRT);
01115   }
01116   else
01117   {
01118 #endif /* FLASH_BANK2_END */
01119     /* Proceed to erase the page */
01120     SET_BIT(FLASH->CR, FLASH_CR_PER);
01121     WRITE_REG(FLASH->AR, PageAddress);
01122     SET_BIT(FLASH->CR, FLASH_CR_STRT);
01123 #if defined(FLASH_BANK2_END)
01124   }
01125 #endif /* FLASH_BANK2_END */
01126 }
01127
01128 /**
01129   * @}
01130   */
01131
01132 /**
01133   * @}
01134   */
01135
01136 #endif /* HAL_FLASH_MODULE_ENABLED */
01137 /**
01138   * @}
01139   */
01140
01141 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_flash_ex.h Source File

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stm32f1xx_hal_flash_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_flash_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of Flash HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_FLASH_EX_H
00040 #define __STM32F1xx_HAL_FLASH_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup FLASHEx
00054   * @{
00055   */
00056
00057 /** @addtogroup FLASHEx_Private_Constants
00058   * @{
00059   */
00060
00061 #define FLASH_SIZE_DATA_REGISTER     0x1FFFF7E0U
00062 #define OBR_REG_INDEX                1U
00063 #define SR_FLAG_MASK                 ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
00064
00065 /**
00066   * @}
00067   */
00068
00069 /** @addtogroup FLASHEx_Private_Macros
00070   * @{
00071   */
00072
00073 #define IS_FLASH_TYPEERASE(VALUE)   (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
00074
00075 #define IS_OPTIONBYTE(VALUE)        (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
00076
00077 #define IS_WRPSTATE(VALUE)          (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
00078
00079 #define IS_OB_RDP_LEVEL(LEVEL)      (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
00080
00081 #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
00082
00083 #define IS_OB_IWDG_SOURCE(SOURCE)   (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
00084
00085 #define IS_OB_STOP_SOURCE(SOURCE)   (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
00086
00087 #define IS_OB_STDBY_SOURCE(SOURCE)  (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
00088
00089 #if defined(FLASH_BANK2_END)
00090 #define IS_OB_BOOT1(BOOT1)         (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
00091 #endif /* FLASH_BANK2_END */
00092
00093 /* Low Density */
00094 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
00095 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \
00096                                            ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU))
00097 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
00098
00099 /* Medium Density */
00100 #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
00101 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
00102                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
00103                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
00104                                            ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))
00105 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
00106
00107 /* High Density */
00108 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
00109 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \
00110                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
00111                                            ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))
00112 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
00113
00114 /* XL Density */
00115 #if defined(FLASH_BANK2_END)
00116 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \
00117                                            ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU))
00118 #endif /* FLASH_BANK2_END */
00119
00120 /* Connectivity Line */
00121 #if (defined(STM32F105xC) || defined(STM32F107xC))
00122 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \
00123                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) ==  0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
00124                                            ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU)))
00125 #endif /* STM32F105xC || STM32F107xC */
00126
00127 #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
00128
00129 #if defined(FLASH_BANK2_END)
00130 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
00131                              ((BANK) == FLASH_BANK_2)  || \
00132                              ((BANK) == FLASH_BANK_BOTH))
00133 #else
00134 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
00135 #endif /* FLASH_BANK2_END */
00136
00137 /* Low Density */
00138 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
00139 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
00140                                             ((ADDRESS) <= FLASH_BANK1_END) :  ((ADDRESS) <= 0x08003FFFU)))
00141
00142 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
00143
00144 /* Medium Density */
00145 #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
00146 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
00147                                            ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
00148                                            ((ADDRESS) <= 0x0800FFFF) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
00149                                            ((ADDRESS) <= 0x08007FFF) :  ((ADDRESS) <= 0x08003FFFU)))))
00150
00151 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
00152
00153 /* High Density */
00154 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
00155 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \
00156                                            ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
00157                                            ((ADDRESS) <= 0x0805FFFFU) :  ((ADDRESS) <= 0x0803FFFFU))))
00158
00159 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
00160
00161 /* XL Density */
00162 #if defined(FLASH_BANK2_END)
00163 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \
00164                                            ((ADDRESS) <= FLASH_BANK2_END) :  ((ADDRESS) <= 0x080BFFFFU)))
00165
00166 #endif /* FLASH_BANK2_END */
00167
00168 /* Connectivity Line */
00169 #if (defined(STM32F105xC) || defined(STM32F107xC))
00170 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
00171                                            ((ADDRESS) <= FLASH_BANK1_END) :  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
00172                                            ((ADDRESS) <= 0x0801FFFFU) :  ((ADDRESS) <= 0x0800FFFFU))))
00173
00174 #endif /* STM32F105xC || STM32F107xC */
00175
00176 /**
00177   * @}
00178   */
00179
00180 /* Exported types ------------------------------------------------------------*/
00181 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
00182   * @{
00183   */
00184
00185 /**
00186   * @brief  FLASH Erase structure definition
00187   */
00188 typedef struct
00189 {
00190   uint32_t TypeErase;   /*!< TypeErase: Mass erase or page erase.
00191                              This parameter can be a value of @ref FLASHEx_Type_Erase */
00192
00193   uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
00194                              This parameter must be a value of @ref FLASHEx_Banks */
00195
00196   uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
00197                              This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
00198                              (x = 1 or 2 depending on devices)*/
00199
00200   uint32_t NbPages;     /*!< NbPages: Number of pagess to be erased.
00201                              This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
00202
00203 } FLASH_EraseInitTypeDef;
00204
00205 /**
00206   * @brief  FLASH Options bytes program structure definition
00207   */
00208 typedef struct
00209 {
00210   uint32_t OptionType;  /*!< OptionType: Option byte to be configured.
00211                              This parameter can be a value of @ref FLASHEx_OB_Type */
00212
00213   uint32_t WRPState;    /*!< WRPState: Write protection activation or deactivation.
00214                              This parameter can be a value of @ref FLASHEx_OB_WRP_State */
00215
00216   uint32_t WRPPage;     /*!< WRPPage: specifies the page(s) to be write protected
00217                              This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
00218
00219   uint32_t Banks;        /*!< Select banks for WRP activation/deactivation of all sectors.
00220                               This parameter must be a value of @ref FLASHEx_Banks */
00221
00222   uint8_t RDPLevel;     /*!< RDPLevel: Set the read protection level..
00223                              This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
00224
00225 #if defined(FLASH_BANK2_END)
00226   uint8_t USERConfig;   /*!< USERConfig: Program the FLASH User Option Byte:
00227                              IWDG / STOP / STDBY / BOOT1
00228                              This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
00229                              @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
00230 #else
00231   uint8_t USERConfig;   /*!< USERConfig: Program the FLASH User Option Byte:
00232                              IWDG / STOP / STDBY
00233                              This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
00234                              @ref FLASHEx_OB_nRST_STDBY */
00235 #endif /* FLASH_BANK2_END */
00236
00237   uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
00238                              This parameter can be a value of @ref FLASHEx_OB_Data_Address */
00239
00240   uint8_t DATAData;     /*!< DATAData: Data to be stored in the option byte DATA
00241                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00242 } FLASH_OBProgramInitTypeDef;
00243
00244 /**
00245   * @}
00246   */
00247
00248 /* Exported constants --------------------------------------------------------*/
00249 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
00250   * @{
00251   */
00252
00253 /** @defgroup FLASHEx_Constants FLASH Constants
00254   * @{
00255   */
00256
00257 /** @defgroup FLASHEx_Page_Size Page Size
00258   * @{
00259   */
00260 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
00261 #define FLASH_PAGE_SIZE          0x400U
00262 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
00263        /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
00264
00265 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
00266 #define FLASH_PAGE_SIZE          0x800U
00267 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
00268        /* STM32F101xG || STM32F103xG */
00269        /* STM32F105xC || STM32F107xC */
00270
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup FLASHEx_Type_Erase Type Erase
00276   * @{
00277   */
00278 #define FLASH_TYPEERASE_PAGES     0x00U  /*!<Pages erase only*/
00279 #define FLASH_TYPEERASE_MASSERASE 0x02U  /*!<Flash mass erase activation*/
00280
00281 /**
00282   * @}
00283   */
00284
00285 /** @defgroup FLASHEx_Banks Banks
00286   * @{
00287   */
00288 #if defined(FLASH_BANK2_END)
00289 #define FLASH_BANK_1     1U /*!< Bank 1   */
00290 #define FLASH_BANK_2     2U /*!< Bank 2   */
00291 #define FLASH_BANK_BOTH  ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
00292
00293 #else
00294 #define FLASH_BANK_1     1U /*!< Bank 1   */
00295 #endif
00296 /**
00297   * @}
00298   */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
00305   * @{
00306   */
00307
00308 /** @defgroup FLASHEx_OB_Type Option Bytes Type
00309   * @{
00310   */
00311 #define OPTIONBYTE_WRP            0x01U  /*!<WRP option byte configuration*/
00312 #define OPTIONBYTE_RDP            0x02U  /*!<RDP option byte configuration*/
00313 #define OPTIONBYTE_USER           0x04U  /*!<USER option byte configuration*/
00314 #define OPTIONBYTE_DATA           0x08U  /*!<DATA option byte configuration*/
00315
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
00321   * @{
00322   */
00323 #define OB_WRPSTATE_DISABLE       0x00U  /*!<Disable the write protection of the desired pages*/
00324 #define OB_WRPSTATE_ENABLE        0x01U  /*!<Enable the write protection of the desired pagess*/
00325
00326 /**
00327   * @}
00328   */
00329
00330 /** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
00331   * @{
00332   */
00333 /* STM32 Low and Medium density devices */
00334 #if  defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
00335   || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
00336   || defined(STM32F103xB)
00337 #define OB_WRP_PAGES0TO3               0x00000001U /*!< Write protection of page 0 to 3 */
00338 #define OB_WRP_PAGES4TO7               0x00000002U /*!< Write protection of page 4 to 7 */
00339 #define OB_WRP_PAGES8TO11              0x00000004U /*!< Write protection of page 8 to 11 */
00340 #define OB_WRP_PAGES12TO15             0x00000008U /*!< Write protection of page 12 to 15 */
00341 #define OB_WRP_PAGES16TO19             0x00000010U /*!< Write protection of page 16 to 19 */
00342 #define OB_WRP_PAGES20TO23             0x00000020U /*!< Write protection of page 20 to 23 */
00343 #define OB_WRP_PAGES24TO27             0x00000040U /*!< Write protection of page 24 to 27 */
00344 #define OB_WRP_PAGES28TO31             0x00000080U /*!< Write protection of page 28 to 31 */
00345 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
00346        /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
00347
00348 /* STM32 Medium-density devices */
00349 #if  defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
00350 #define OB_WRP_PAGES32TO35             0x00000100U   /*!< Write protection of page 32 to 35 */
00351 #define OB_WRP_PAGES36TO39             0x00000200U   /*!< Write protection of page 36 to 39 */
00352 #define OB_WRP_PAGES40TO43             0x00000400U   /*!< Write protection of page 40 to 43 */
00353 #define OB_WRP_PAGES44TO47             0x00000800U   /*!< Write protection of page 44 to 47 */
00354 #define OB_WRP_PAGES48TO51             0x00001000U   /*!< Write protection of page 48 to 51 */
00355 #define OB_WRP_PAGES52TO55             0x00002000U   /*!< Write protection of page 52 to 55 */
00356 #define OB_WRP_PAGES56TO59             0x00004000U   /*!< Write protection of page 56 to 59 */
00357 #define OB_WRP_PAGES60TO63             0x00008000U   /*!< Write protection of page 60 to 63 */
00358 #define OB_WRP_PAGES64TO67             0x00010000U   /*!< Write protection of page 64 to 67 */
00359 #define OB_WRP_PAGES68TO71             0x00020000U   /*!< Write protection of page 68 to 71 */
00360 #define OB_WRP_PAGES72TO75             0x00040000U   /*!< Write protection of page 72 to 75 */
00361 #define OB_WRP_PAGES76TO79             0x00080000U   /*!< Write protection of page 76 to 79 */
00362 #define OB_WRP_PAGES80TO83             0x00100000U   /*!< Write protection of page 80 to 83 */
00363 #define OB_WRP_PAGES84TO87             0x00200000U   /*!< Write protection of page 84 to 87 */
00364 #define OB_WRP_PAGES88TO91             0x00400000U   /*!< Write protection of page 88 to 91 */
00365 #define OB_WRP_PAGES92TO95             0x00800000U   /*!< Write protection of page 92 to 95 */
00366 #define OB_WRP_PAGES96TO99             0x01000000U   /*!< Write protection of page 96 to 99 */
00367 #define OB_WRP_PAGES100TO103           0x02000000U   /*!< Write protection of page 100 to 103 */
00368 #define OB_WRP_PAGES104TO107           0x04000000U   /*!< Write protection of page 104 to 107 */
00369 #define OB_WRP_PAGES108TO111           0x08000000U   /*!< Write protection of page 108 to 111 */
00370 #define OB_WRP_PAGES112TO115           0x10000000U   /*!< Write protection of page 112 to 115 */
00371 #define OB_WRP_PAGES116TO119           0x20000000U   /*!< Write protection of page 115 to 119 */
00372 #define OB_WRP_PAGES120TO123           0x40000000U   /*!< Write protection of page 120 to 123 */
00373 #define OB_WRP_PAGES124TO127           0x80000000U    /*!< Write protection of page 124 to 127 */
00374 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
00375
00376
00377 /* STM32 High-density, XL-density and Connectivity line devices */
00378 #if  defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
00379   || defined(STM32F101xG) || defined(STM32F103xG) \
00380   || defined(STM32F105xC) || defined(STM32F107xC)
00381 #define OB_WRP_PAGES0TO1               0x00000001U  /*!< Write protection of page 0 TO 1 */
00382 #define OB_WRP_PAGES2TO3               0x00000002U  /*!< Write protection of page 2 TO 3 */
00383 #define OB_WRP_PAGES4TO5               0x00000004U  /*!< Write protection of page 4 TO 5 */
00384 #define OB_WRP_PAGES6TO7               0x00000008U  /*!< Write protection of page 6 TO 7 */
00385 #define OB_WRP_PAGES8TO9               0x00000010U  /*!< Write protection of page 8 TO 9 */
00386 #define OB_WRP_PAGES10TO11             0x00000020U  /*!< Write protection of page 10 TO 11 */
00387 #define OB_WRP_PAGES12TO13             0x00000040U  /*!< Write protection of page 12 TO 13 */
00388 #define OB_WRP_PAGES14TO15             0x00000080U  /*!< Write protection of page 14 TO 15 */
00389 #define OB_WRP_PAGES16TO17             0x00000100U  /*!< Write protection of page 16 TO 17 */
00390 #define OB_WRP_PAGES18TO19             0x00000200U  /*!< Write protection of page 18 TO 19 */
00391 #define OB_WRP_PAGES20TO21             0x00000400U  /*!< Write protection of page 20 TO 21 */
00392 #define OB_WRP_PAGES22TO23             0x00000800U  /*!< Write protection of page 22 TO 23 */
00393 #define OB_WRP_PAGES24TO25             0x00001000U  /*!< Write protection of page 24 TO 25 */
00394 #define OB_WRP_PAGES26TO27             0x00002000U  /*!< Write protection of page 26 TO 27 */
00395 #define OB_WRP_PAGES28TO29             0x00004000U  /*!< Write protection of page 28 TO 29 */
00396 #define OB_WRP_PAGES30TO31             0x00008000U  /*!< Write protection of page 30 TO 31 */
00397 #define OB_WRP_PAGES32TO33             0x00010000U  /*!< Write protection of page 32 TO 33 */
00398 #define OB_WRP_PAGES34TO35             0x00020000U  /*!< Write protection of page 34 TO 35 */
00399 #define OB_WRP_PAGES36TO37             0x00040000U  /*!< Write protection of page 36 TO 37 */
00400 #define OB_WRP_PAGES38TO39             0x00080000U  /*!< Write protection of page 38 TO 39 */
00401 #define OB_WRP_PAGES40TO41             0x00100000U  /*!< Write protection of page 40 TO 41 */
00402 #define OB_WRP_PAGES42TO43             0x00200000U  /*!< Write protection of page 42 TO 43 */
00403 #define OB_WRP_PAGES44TO45             0x00400000U  /*!< Write protection of page 44 TO 45 */
00404 #define OB_WRP_PAGES46TO47             0x00800000U  /*!< Write protection of page 46 TO 47 */
00405 #define OB_WRP_PAGES48TO49             0x01000000U  /*!< Write protection of page 48 TO 49 */
00406 #define OB_WRP_PAGES50TO51             0x02000000U  /*!< Write protection of page 50 TO 51 */
00407 #define OB_WRP_PAGES52TO53             0x04000000U  /*!< Write protection of page 52 TO 53 */
00408 #define OB_WRP_PAGES54TO55             0x08000000U  /*!< Write protection of page 54 TO 55 */
00409 #define OB_WRP_PAGES56TO57             0x10000000U  /*!< Write protection of page 56 TO 57 */
00410 #define OB_WRP_PAGES58TO59             0x20000000U  /*!< Write protection of page 58 TO 59 */
00411 #define OB_WRP_PAGES60TO61             0x40000000U  /*!< Write protection of page 60 TO 61 */
00412 #define OB_WRP_PAGES62TO127            0x80000000U   /*!< Write protection of page 62 TO 127 */
00413 #define OB_WRP_PAGES62TO255            0x80000000U   /*!< Write protection of page 62 TO 255 */
00414 #define OB_WRP_PAGES62TO511            0x80000000U   /*!< Write protection of page 62 TO 511 */
00415 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
00416        /* STM32F101xG || STM32F103xG */
00417        /* STM32F105xC || STM32F107xC */
00418
00419 #define OB_WRP_ALLPAGES                0xFFFFFFFFU  /*!< Write protection of all Pages */
00420
00421 /* Low Density */
00422 #if  defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
00423 #define OB_WRP_PAGES0TO31MASK          0x000000FFU
00424 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
00425
00426 /* Medium Density */
00427 #if  defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
00428 #define OB_WRP_PAGES0TO31MASK          0x000000FFU
00429 #define OB_WRP_PAGES32TO63MASK         0x0000FF00U
00430 #define OB_WRP_PAGES64TO95MASK         0x00FF0000U
00431 #define OB_WRP_PAGES96TO127MASK        0xFF000000U
00432 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
00433
00434 /* High Density */
00435 #if  defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
00436 #define OB_WRP_PAGES0TO15MASK          0x000000FFU
00437 #define OB_WRP_PAGES16TO31MASK         0x0000FF00U
00438 #define OB_WRP_PAGES32TO47MASK         0x00FF0000U
00439 #define OB_WRP_PAGES48TO255MASK        0xFF000000U
00440 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
00441
00442 /* XL Density */
00443 #if  defined(STM32F101xG) || defined(STM32F103xG)
00444 #define OB_WRP_PAGES0TO15MASK          0x000000FFU
00445 #define OB_WRP_PAGES16TO31MASK         0x0000FF00U
00446 #define OB_WRP_PAGES32TO47MASK         0x00FF0000U
00447 #define OB_WRP_PAGES48TO511MASK        0xFF000000U
00448 #endif /* STM32F101xG || STM32F103xG */
00449
00450 /* Connectivity line devices */
00451 #if defined(STM32F105xC) || defined(STM32F107xC)
00452 #define OB_WRP_PAGES0TO15MASK          0x000000FFU
00453 #define OB_WRP_PAGES16TO31MASK         0x0000FF00U
00454 #define OB_WRP_PAGES32TO47MASK         0x00FF0000U
00455 #define OB_WRP_PAGES48TO127MASK        0xFF000000U
00456 #endif /* STM32F105xC || STM32F107xC */
00457
00458 /**
00459   * @}
00460   */
00461
00462 /** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
00463   * @{
00464   */
00465 #define OB_RDP_LEVEL_0            ((uint8_t)0xA5)
00466 #define OB_RDP_LEVEL_1            ((uint8_t)0x00)
00467 /**
00468   * @}
00469   */
00470
00471 /** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
00472   * @{
00473   */
00474 #define OB_IWDG_SW                ((uint16_t)0x0001)  /*!< Software IWDG selected */
00475 #define OB_IWDG_HW                ((uint16_t)0x0000)  /*!< Hardware IWDG selected */
00476 /**
00477   * @}
00478   */
00479
00480 /** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
00481   * @{
00482   */
00483 #define OB_STOP_NO_RST            ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
00484 #define OB_STOP_RST               ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
00485 /**
00486   * @}
00487   */
00488
00489 /** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
00490   * @{
00491   */
00492 #define OB_STDBY_NO_RST           ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
00493 #define OB_STDBY_RST              ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
00494 /**
00495   * @}
00496   */
00497
00498 #if defined(FLASH_BANK2_END)
00499 /** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
00500   * @{
00501   */
00502 #define OB_BOOT1_RESET            ((uint16_t)0x0000) /*!< BOOT1 Reset */
00503 #define OB_BOOT1_SET              ((uint16_t)0x0008) /*!< BOOT1 Set */
00504 /**
00505   * @}
00506   */
00507 #endif /* FLASH_BANK2_END */
00508
00509 /** @defgroup FLASHEx_OB_Data_Address  Option Byte Data Address
00510   * @{
00511   */
00512 #define OB_DATA_ADDRESS_DATA0     0x1FFFF804U
00513 #define OB_DATA_ADDRESS_DATA1     0x1FFFF806U
00514 /**
00515   * @}
00516   */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /** @addtogroup FLASHEx_Constants
00523   * @{
00524   */
00525
00526 /** @defgroup FLASH_Flag_definition Flag definition
00527   * @brief Flag definition
00528   * @{
00529   */
00530 #if defined(FLASH_BANK2_END)
00531  #define FLASH_FLAG_BSY             FLASH_FLAG_BSY_BANK1       /*!< FLASH Bank1 Busy flag                   */
00532  #define FLASH_FLAG_PGERR           FLASH_FLAG_PGERR_BANK1     /*!< FLASH Bank1 Programming error flag      */
00533  #define FLASH_FLAG_WRPERR          FLASH_FLAG_WRPERR_BANK1    /*!< FLASH Bank1 Write protected error flag  */
00534  #define FLASH_FLAG_EOP             FLASH_FLAG_EOP_BANK1       /*!< FLASH Bank1 End of Operation flag       */
00535
00536  #define FLASH_FLAG_BSY_BANK1       FLASH_SR_BSY               /*!< FLASH Bank1 Busy flag                   */
00537  #define FLASH_FLAG_PGERR_BANK1     FLASH_SR_PGERR             /*!< FLASH Bank1 Programming error flag      */
00538  #define FLASH_FLAG_WRPERR_BANK1    FLASH_SR_WRPRTERR          /*!< FLASH Bank1 Write protected error flag  */
00539  #define FLASH_FLAG_EOP_BANK1       FLASH_SR_EOP               /*!< FLASH Bank1 End of Operation flag       */
00540
00541  #define FLASH_FLAG_BSY_BANK2       (FLASH_SR2_BSY << 16U)      /*!< FLASH Bank2 Busy flag                   */
00542  #define FLASH_FLAG_PGERR_BANK2     (FLASH_SR2_PGERR << 16U)    /*!< FLASH Bank2 Programming error flag      */
00543  #define FLASH_FLAG_WRPERR_BANK2    (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag  */
00544  #define FLASH_FLAG_EOP_BANK2       (FLASH_SR2_EOP << 16U)      /*!< FLASH Bank2 End of Operation flag       */
00545
00546 #else
00547
00548  #define FLASH_FLAG_BSY             FLASH_SR_BSY              /*!< FLASH Busy flag                          */
00549  #define FLASH_FLAG_PGERR           FLASH_SR_PGERR            /*!< FLASH Programming error flag             */
00550  #define FLASH_FLAG_WRPERR          FLASH_SR_WRPRTERR         /*!< FLASH Write protected error flag         */
00551  #define FLASH_FLAG_EOP             FLASH_SR_EOP              /*!< FLASH End of Operation flag              */
00552
00553 #endif
00554  #define FLASH_FLAG_OPTVERR         ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error        */
00555 /**
00556   * @}
00557   */
00558
00559 /** @defgroup FLASH_Interrupt_definition Interrupt definition
00560   * @brief FLASH Interrupt definition
00561   * @{
00562   */
00563 #if defined(FLASH_BANK2_END)
00564  #define FLASH_IT_EOP               FLASH_IT_EOP_BANK1        /*!< End of FLASH Operation Interrupt source Bank1 */
00565  #define FLASH_IT_ERR               FLASH_IT_ERR_BANK1        /*!< Error Interrupt source Bank1                  */
00566
00567  #define FLASH_IT_EOP_BANK1         FLASH_CR_EOPIE            /*!< End of FLASH Operation Interrupt source Bank1 */
00568  #define FLASH_IT_ERR_BANK1         FLASH_CR_ERRIE            /*!< Error Interrupt source Bank1                  */
00569
00570  #define FLASH_IT_EOP_BANK2         (FLASH_CR2_EOPIE << 16U)   /*!< End of FLASH Operation Interrupt source Bank2 */
00571  #define FLASH_IT_ERR_BANK2         (FLASH_CR2_ERRIE << 16U)   /*!< Error Interrupt source Bank2                  */
00572
00573 #else
00574
00575  #define FLASH_IT_EOP               FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
00576  #define FLASH_IT_ERR               FLASH_CR_ERRIE          /*!< Error Interrupt source                  */
00577
00578 #endif
00579 /**
00580   * @}
00581   */
00582
00583 /**
00584   * @}
00585   */
00586
00587
00588 /**
00589   * @}
00590   */
00591
00592 /* Exported macro ------------------------------------------------------------*/
00593 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
00594   * @{
00595   */
00596
00597 /** @defgroup FLASH_Interrupt Interrupt
00598  *  @brief macros to handle FLASH interrupts
00599  * @{
00600  */
00601
00602 #if defined(FLASH_BANK2_END)
00603 /**
00604   * @brief  Enable the specified FLASH interrupt.
00605   * @param  __INTERRUPT__  FLASH interrupt
00606   *     This parameter can be any combination of the following values:
00607   *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
00608   *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
00609   *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
00610   *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
00611   * @retval none
00612   */
00613 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  do { \
00614                           /* Enable Bank1 IT */ \
00615                           SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
00616                           /* Enable Bank2 IT */ \
00617                           SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
00618                     } while(0U)
00619
00620 /**
00621   * @brief  Disable the specified FLASH interrupt.
00622   * @param  __INTERRUPT__  FLASH interrupt
00623   *     This parameter can be any combination of the following values:
00624   *     @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
00625   *     @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
00626   *     @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
00627   *     @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
00628   * @retval none
00629   */
00630 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  do { \
00631                           /* Disable Bank1 IT */ \
00632                           CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
00633                           /* Disable Bank2 IT */ \
00634                           CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
00635                     } while(0U)
00636
00637 /**
00638   * @brief  Get the specified FLASH flag status.
00639   * @param  __FLAG__ specifies the FLASH flag to check.
00640   *          This parameter can be one of the following values:
00641   *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
00642   *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
00643   *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
00644   *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
00645   *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
00646   *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
00647   *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
00648   *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
00649   *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
00650   * @retval The new state of __FLAG__ (SET or RESET).
00651   */
00652 #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
00653                                             (FLASH->OBR & FLASH_OBR_OPTERR) : \
00654                                         ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
00655                                             (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
00656                                             (FLASH->SR2 & ((__FLAG__) >> 16U))))
00657
00658 /**
00659   * @brief  Clear the specified FLASH flag.
00660   * @param  __FLAG__ specifies the FLASH flags to clear.
00661   *          This parameter can be any combination of the following values:
00662   *            @arg @ref FLASH_FLAG_EOP_BANK1    FLASH End of Operation flag on bank1
00663   *            @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
00664   *            @arg @ref FLASH_FLAG_PGERR_BANK1  FLASH Programming error flag on bank1
00665   *            @arg @ref FLASH_FLAG_BSY_BANK1    FLASH Busy flag on bank1
00666   *            @arg @ref FLASH_FLAG_EOP_BANK2    FLASH End of Operation flag on bank2
00667   *            @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
00668   *            @arg @ref FLASH_FLAG_PGERR_BANK2  FLASH Programming error flag on bank2
00669   *            @arg @ref FLASH_FLAG_BSY_BANK2    FLASH Busy flag on bank2
00670   *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
00671   * @retval none
00672   */
00673 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)  do { \
00674                           /* Clear FLASH_FLAG_OPTVERR flag */ \
00675                           if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
00676                           { \
00677                             CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
00678                           } \
00679                           else { \
00680                           /* Clear Flag in Bank1 */ \
00681                           if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
00682                           { \
00683                             FLASH->SR  = ((__FLAG__) & SR_FLAG_MASK); \
00684                           } \
00685                           /* Clear Flag in Bank2 */ \
00686                           if (((__FLAG__) >> 16U) != RESET) \
00687                           { \
00688                             FLASH->SR2 = ((__FLAG__) >> 16U); \
00689                           } \
00690                           } \
00691                     } while(0U)
00692 #else
00693 /**
00694   * @brief  Enable the specified FLASH interrupt.
00695   * @param  __INTERRUPT__  FLASH interrupt
00696   *         This parameter can be any combination of the following values:
00697   *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
00698   *     @arg @ref FLASH_IT_ERR Error Interrupt
00699   * @retval none
00700   */
00701 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
00702
00703 /**
00704   * @brief  Disable the specified FLASH interrupt.
00705   * @param  __INTERRUPT__  FLASH interrupt
00706   *         This parameter can be any combination of the following values:
00707   *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
00708   *     @arg @ref FLASH_IT_ERR Error Interrupt
00709   * @retval none
00710   */
00711 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   (FLASH->CR &= ~(__INTERRUPT__))
00712
00713 /**
00714   * @brief  Get the specified FLASH flag status.
00715   * @param  __FLAG__ specifies the FLASH flag to check.
00716   *          This parameter can be one of the following values:
00717   *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag
00718   *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
00719   *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag
00720   *            @arg @ref FLASH_FLAG_BSY    FLASH Busy flag
00721   *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
00722   * @retval The new state of __FLAG__ (SET or RESET).
00723   */
00724 #define __HAL_FLASH_GET_FLAG(__FLAG__)  (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
00725                                             (FLASH->OBR & FLASH_OBR_OPTERR) : \
00726                                             (FLASH->SR & (__FLAG__)))
00727 /**
00728   * @brief  Clear the specified FLASH flag.
00729   * @param  __FLAG__ specifies the FLASH flags to clear.
00730   *          This parameter can be any combination of the following values:
00731   *            @arg @ref FLASH_FLAG_EOP    FLASH End of Operation flag
00732   *            @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
00733   *            @arg @ref FLASH_FLAG_PGERR  FLASH Programming error flag
00734   *            @arg @ref FLASH_FLAG_OPTVERR  Loaded OB and its complement do not match
00735   * @retval none
00736   */
00737 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   do { \
00738                           /* Clear FLASH_FLAG_OPTVERR flag */ \
00739                           if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
00740                           { \
00741                             CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
00742                           } \
00743                           else { \
00744                             /* Clear Flag in Bank1 */ \
00745                             FLASH->SR  = (__FLAG__); \
00746                           } \
00747                     } while(0U)
00748
00749 #endif
00750
00751 /**
00752   * @}
00753   */
00754
00755 /**
00756   * @}
00757   */
00758
00759 /* Exported functions --------------------------------------------------------*/
00760 /** @addtogroup FLASHEx_Exported_Functions
00761   * @{
00762   */
00763
00764 /** @addtogroup FLASHEx_Exported_Functions_Group1
00765   * @{
00766   */
00767 /* IO operation functions *****************************************************/
00768 HAL_StatusTypeDef  HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
00769 HAL_StatusTypeDef  HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
00770
00771 /**
00772   * @}
00773   */
00774
00775 /** @addtogroup FLASHEx_Exported_Functions_Group2
00776   * @{
00777   */
00778 /* Peripheral Control functions ***********************************************/
00779 HAL_StatusTypeDef  HAL_FLASHEx_OBErase(void);
00780 HAL_StatusTypeDef  HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
00781 void               HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
00782 uint32_t           HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
00783 /**
00784   * @}
00785   */
00786
00787 /**
00788   * @}
00789   */
00790
00791 /**
00792   * @}
00793   */
00794
00795 /**
00796   * @}
00797   */
00798 #ifdef __cplusplus
00799 }
00800 #endif
00801
00802 #endif /* __STM32F1xx_HAL_FLASH_EX_H */
00803
00804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_gpio.c Source File

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stm32f1xx_hal_gpio.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_gpio.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   GPIO HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### GPIO Peripheral features #####
00016   ==============================================================================
00017   [..]
00018   Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
00019   port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
00020   in several modes:
00021   (+) Input mode
00022   (+) Analog mode
00023   (+) Output mode
00024   (+) Alternate function mode
00025   (+) External interrupt/event lines
00026
00027   [..]
00028   During and just after reset, the alternate functions and external interrupt
00029   lines are not active and the I/O ports are configured in input floating mode.
00030
00031   [..]
00032   All GPIO pins have weak internal pull-up and pull-down resistors, which can be
00033   activated or not.
00034
00035   [..]
00036   In Output or Alternate mode, each IO can be configured on open-drain or push-pull
00037   type and the IO speed can be selected depending on the VDD value.
00038
00039   [..]
00040   All ports have external interrupt/event capability. To use external interrupt
00041   lines, the port must be configured in input mode. All available GPIO pins are
00042   connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
00043
00044   [..]
00045   The external interrupt/event controller consists of up to 20 edge detectors in connectivity
00046   line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
00047   Each input line can be independently configured to select the type (event or interrupt) and
00048   the corresponding trigger event (rising or falling or both). Each line can also masked
00049   independently. A pending register maintains the status line of the interrupt requests
00050
00051                      ##### How to use this driver #####
00052   ==============================================================================
00053  [..]
00054    (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
00055
00056    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
00057        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
00058        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
00059             structure.
00060        (++) In case of Output or alternate function mode selection: the speed is
00061             configured through "Speed" member from GPIO_InitTypeDef structure
00062        (++) Analog mode is required when a pin is to be used as ADC channel
00063             or DAC output.
00064        (++) In case of external interrupt/event selection the "Mode" member from
00065             GPIO_InitTypeDef structure select the type (interrupt or event) and
00066             the corresponding trigger event (rising or falling or both).
00067
00068    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
00069        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
00070        HAL_NVIC_EnableIRQ().
00071
00072    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
00073
00074    (#) To set/reset the level of a pin configured in output mode use
00075        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
00076
00077    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
00078
00079    (#) During and just after reset, the alternate functions are not
00080        active and the GPIO pins are configured in input floating mode (except JTAG
00081        pins).
00082
00083    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
00084        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
00085        priority over the GPIO function.
00086
00087    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
00088        general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
00089        The HSE has priority over the GPIO function.
00090
00091   @endverbatim
00092   ******************************************************************************
00093   * @attention
00094   *
00095   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00096   *
00097   * Redistribution and use in source and binary forms, with or without modification,
00098   * are permitted provided that the following conditions are met:
00099   *   1. Redistributions of source code must retain the above copyright notice,
00100   *      this list of conditions and the following disclaimer.
00101   *   2. Redistributions in binary form must reproduce the above copyright notice,
00102   *      this list of conditions and the following disclaimer in the documentation
00103   *      and/or other materials provided with the distribution.
00104   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00105   *      may be used to endorse or promote products derived from this software
00106   *      without specific prior written permission.
00107   *
00108   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00109   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00110   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00111   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00112   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00113   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00114   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00115   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00116   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00117   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00118   *
00119   ******************************************************************************
00120   */
00121
00122 /* Includes ------------------------------------------------------------------*/
00123 #include "stm32f1xx_hal.h"
00124
00125 /** @addtogroup STM32F1xx_HAL_Driver
00126   * @{
00127   */
00128
00129 /** @defgroup GPIO GPIO
00130   * @brief GPIO HAL module driver
00131   * @{
00132   */
00133
00134 #ifdef HAL_GPIO_MODULE_ENABLED
00135
00136 /* Private typedef -----------------------------------------------------------*/
00137 /* Private define ------------------------------------------------------------*/
00138 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
00139   * @{
00140   */
00141 #define GPIO_MODE             0x00000003U
00142 #define EXTI_MODE             0x10000000U
00143 #define GPIO_MODE_IT          0x00010000U
00144 #define GPIO_MODE_EVT         0x00020000U
00145 #define RISING_EDGE           0x00100000U
00146 #define FALLING_EDGE          0x00200000U
00147 #define GPIO_OUTPUT_TYPE      0x00000010U
00148
00149 #define GPIO_NUMBER           16U
00150
00151 /* Definitions for bit manipulation of CRL and CRH register */
00152 #define  GPIO_CR_MODE_INPUT         0x00000000U /*!< 00: Input mode (reset state)  */
00153 #define  GPIO_CR_CNF_ANALOG         0x00000000U /*!< 00: Analog mode  */
00154 #define  GPIO_CR_CNF_INPUT_FLOATING 0x00000004U /*!< 01: Floating input (reset state)  */
00155 #define  GPIO_CR_CNF_INPUT_PU_PD    0x00000008U /*!< 10: Input with pull-up / pull-down  */
00156 #define  GPIO_CR_CNF_GP_OUTPUT_PP   0x00000000U /*!< 00: General purpose output push-pull  */
00157 #define  GPIO_CR_CNF_GP_OUTPUT_OD   0x00000004U /*!< 01: General purpose output Open-drain  */
00158 #define  GPIO_CR_CNF_AF_OUTPUT_PP   0x00000008U /*!< 10: Alternate function output Push-pull  */
00159 #define  GPIO_CR_CNF_AF_OUTPUT_OD   0x0000000CU /*!< 11: Alternate function output Open-drain  */
00160
00161 /**
00162   * @}
00163   */
00164 /* Private macro -------------------------------------------------------------*/
00165 /* Private variables ---------------------------------------------------------*/
00166 /* Private function prototypes -----------------------------------------------*/
00167 /* Private functions ---------------------------------------------------------*/
00168 /* Exported functions --------------------------------------------------------*/
00169 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
00170   * @{
00171   */
00172
00173 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
00174  *  @brief    Initialization and Configuration functions
00175  *
00176 @verbatim
00177  ===============================================================================
00178               ##### Initialization and de-initialization functions #####
00179  ===============================================================================
00180   [..]
00181     This section provides functions allowing to initialize and de-initialize the GPIOs
00182     to be ready for use.
00183
00184 @endverbatim
00185   * @{
00186   */
00187
00188
00189 /**
00190   * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
00191   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00192   * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
00193   *         the configuration information for the specified GPIO peripheral.
00194   * @retval None
00195   */
00196 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
00197 {
00198   uint32_t position;
00199   uint32_t ioposition = 0x00U;
00200   uint32_t iocurrent = 0x00U;
00201   uint32_t temp = 0x00U;
00202   uint32_t config = 0x00U;
00203   __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
00204   uint32_t registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
00205
00206   /* Check the parameters */
00207   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00208   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
00209   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
00210
00211   /* Configure the port pins */
00212   for (position = 0U; position < GPIO_NUMBER; position++)
00213   {
00214     /* Get the IO position */
00215     ioposition = (0x01U << position);
00216
00217     /* Get the current IO position */
00218     iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
00219
00220     if (iocurrent == ioposition)
00221     {
00222       /* Check the Alternate function parameters */
00223       assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
00224
00225       /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
00226       switch (GPIO_Init->Mode)
00227       {
00228         /* If we are configuring the pin in OUTPUT push-pull mode */
00229         case GPIO_MODE_OUTPUT_PP:
00230           /* Check the GPIO speed parameter */
00231           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00232           config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
00233           break;
00234
00235         /* If we are configuring the pin in OUTPUT open-drain mode */
00236         case GPIO_MODE_OUTPUT_OD:
00237           /* Check the GPIO speed parameter */
00238           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00239           config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
00240           break;
00241
00242         /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
00243         case GPIO_MODE_AF_PP:
00244           /* Check the GPIO speed parameter */
00245           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00246           config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
00247           break;
00248
00249         /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
00250         case GPIO_MODE_AF_OD:
00251           /* Check the GPIO speed parameter */
00252           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
00253           config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
00254           break;
00255
00256         /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
00257         case GPIO_MODE_INPUT:
00258         case GPIO_MODE_IT_RISING:
00259         case GPIO_MODE_IT_FALLING:
00260         case GPIO_MODE_IT_RISING_FALLING:
00261         case GPIO_MODE_EVT_RISING:
00262         case GPIO_MODE_EVT_FALLING:
00263         case GPIO_MODE_EVT_RISING_FALLING:
00264           /* Check the GPIO pull parameter */
00265           assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
00266           if(GPIO_Init->Pull == GPIO_NOPULL)
00267           {
00268             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
00269           }
00270           else if(GPIO_Init->Pull == GPIO_PULLUP)
00271           {
00272             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
00273
00274             /* Set the corresponding ODR bit */
00275             GPIOx->BSRR = ioposition;
00276           }
00277           else /* GPIO_PULLDOWN */
00278           {
00279             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
00280
00281             /* Reset the corresponding ODR bit */
00282             GPIOx->BRR = ioposition;
00283           }
00284           break;
00285
00286         /* If we are configuring the pin in INPUT analog mode */
00287         case GPIO_MODE_ANALOG:
00288             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
00289           break;
00290
00291         /* Parameters are checked with assert_param */
00292         default:
00293           break;
00294       }
00295
00296       /* Check if the current bit belongs to first half or last half of the pin count number
00297        in order to address CRH or CRL register*/
00298       configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
00299       registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
00300
00301       /* Apply the new configuration of the pin to the register */
00302       MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset));
00303
00304       /*--------------------- EXTI Mode Configuration ------------------------*/
00305       /* Configure the External Interrupt or event for the current IO */
00306       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
00307       {
00308         /* Enable AFIO Clock */
00309         __HAL_RCC_AFIO_CLK_ENABLE();
00310         temp = AFIO->EXTICR[position >> 2U];
00311         CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
00312         SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
00313         AFIO->EXTICR[position >> 2U] = temp;
00314
00315
00316         /* Configure the interrupt mask */
00317         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
00318         {
00319           SET_BIT(EXTI->IMR, iocurrent);
00320         }
00321         else
00322         {
00323           CLEAR_BIT(EXTI->IMR, iocurrent);
00324         }
00325
00326         /* Configure the event mask */
00327         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
00328         {
00329           SET_BIT(EXTI->EMR, iocurrent);
00330         }
00331         else
00332         {
00333           CLEAR_BIT(EXTI->EMR, iocurrent);
00334         }
00335
00336         /* Enable or disable the rising trigger */
00337         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
00338         {
00339           SET_BIT(EXTI->RTSR, iocurrent);
00340         }
00341         else
00342         {
00343           CLEAR_BIT(EXTI->RTSR, iocurrent);
00344         }
00345
00346         /* Enable or disable the falling trigger */
00347         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
00348         {
00349           SET_BIT(EXTI->FTSR, iocurrent);
00350         }
00351         else
00352         {
00353           CLEAR_BIT(EXTI->FTSR, iocurrent);
00354         }
00355       }
00356     }
00357   }
00358 }
00359
00360 /**
00361   * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
00362   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00363   * @param  GPIO_Pin: specifies the port bit to be written.
00364   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
00365   * @retval None
00366   */
00367 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
00368 {
00369   uint32_t position = 0x00U;
00370   uint32_t iocurrent = 0x00U;
00371   uint32_t tmp = 0x00U;
00372   __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
00373   uint32_t registeroffset = 0U;
00374
00375   /* Check the parameters */
00376   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00377   assert_param(IS_GPIO_PIN(GPIO_Pin));
00378
00379   /* Configure the port pins */
00380   while ((GPIO_Pin >> position) != 0U)
00381   {
00382     /* Get current io position */
00383     iocurrent = (GPIO_Pin) & (1U << position);
00384
00385     if (iocurrent)
00386     {
00387       /*------------------------- GPIO Mode Configuration --------------------*/
00388       /* Check if the current bit belongs to first half or last half of the pin count number
00389        in order to address CRH or CRL register */
00390       configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
00391       registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
00392
00393       /* CRL/CRH default value is floating input(0x04) shifted to correct position */
00394       MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset);
00395
00396       /* ODR default value is 0 */
00397       CLEAR_BIT(GPIOx->ODR, iocurrent);
00398
00399       /*------------------------- EXTI Mode Configuration --------------------*/
00400       /* Clear the External Interrupt or Event for the current IO */
00401
00402       tmp = AFIO->EXTICR[position >> 2U];
00403       tmp &= 0x0FU << (4U * (position & 0x03U));
00404       if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
00405       {
00406         tmp = 0x0FU << (4U * (position & 0x03U));
00407         CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp);
00408
00409         /* Clear EXTI line configuration */
00410         CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
00411         CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
00412
00413         /* Clear Rising Falling edge configuration */
00414         CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
00415         CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
00416       }
00417     }
00418
00419     position++;
00420   }
00421 }
00422
00423 /**
00424   * @}
00425   */
00426
00427 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
00428  *  @brief   GPIO Read and Write
00429  *
00430 @verbatim
00431  ===============================================================================
00432                        ##### IO operation functions #####
00433  ===============================================================================
00434   [..]
00435     This subsection provides a set of functions allowing to manage the GPIOs.
00436
00437 @endverbatim
00438   * @{
00439   */
00440
00441 /**
00442   * @brief  Reads the specified input port pin.
00443   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00444   * @param  GPIO_Pin: specifies the port bit to read.
00445   *         This parameter can be GPIO_PIN_x where x can be (0..15).
00446   * @retval The input port pin value.
00447   */
00448 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00449 {
00450   GPIO_PinState bitstatus;
00451
00452   /* Check the parameters */
00453   assert_param(IS_GPIO_PIN(GPIO_Pin));
00454
00455   if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
00456   {
00457     bitstatus = GPIO_PIN_SET;
00458   }
00459   else
00460   {
00461     bitstatus = GPIO_PIN_RESET;
00462   }
00463   return bitstatus;
00464 }
00465
00466 /**
00467   * @brief  Sets or clears the selected data port bit.
00468   *
00469   * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
00470   *         accesses. In this way, there is no risk of an IRQ occurring between
00471   *         the read and the modify access.
00472   *
00473   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00474   * @param  GPIO_Pin: specifies the port bit to be written.
00475   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
00476   * @param  PinState: specifies the value to be written to the selected bit.
00477   *          This parameter can be one of the GPIO_PinState enum values:
00478   *            @arg GPIO_BIT_RESET: to clear the port pin
00479   *            @arg GPIO_BIT_SET: to set the port pin
00480   * @retval None
00481   */
00482 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
00483 {
00484   /* Check the parameters */
00485   assert_param(IS_GPIO_PIN(GPIO_Pin));
00486   assert_param(IS_GPIO_PIN_ACTION(PinState));
00487
00488   if(PinState != GPIO_PIN_RESET)
00489   {
00490     GPIOx->BSRR = GPIO_Pin;
00491   }
00492   else
00493   {
00494     GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
00495   }
00496 }
00497
00498 /**
00499   * @brief  Toggles the specified GPIO pin
00500   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00501   * @param  GPIO_Pin: Specifies the pins to be toggled.
00502   * @retval None
00503   */
00504 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00505 {
00506   /* Check the parameters */
00507   assert_param(IS_GPIO_PIN(GPIO_Pin));
00508
00509   GPIOx->ODR ^= GPIO_Pin;
00510 }
00511
00512 /**
00513 * @brief  Locks GPIO Pins configuration registers.
00514 * @note   The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
00515 *         has been applied on a port bit, it is no longer possible to modify the value of the port bit until
00516 *         the next reset.
00517 * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
00518 * @param  GPIO_Pin: specifies the port bit to be locked.
00519 *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
00520 * @retval None
00521 */
00522 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
00523 {
00524   __IO uint32_t tmp = GPIO_LCKR_LCKK;
00525
00526   /* Check the parameters */
00527   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
00528   assert_param(IS_GPIO_PIN(GPIO_Pin));
00529
00530   /* Apply lock key write sequence */
00531   SET_BIT(tmp, GPIO_Pin);
00532   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00533   GPIOx->LCKR = tmp;
00534   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
00535   GPIOx->LCKR = GPIO_Pin;
00536   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
00537   GPIOx->LCKR = tmp;
00538   /* Read LCKK bit*/
00539   tmp = GPIOx->LCKR;
00540
00541   if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
00542   {
00543     return HAL_OK;
00544   }
00545   else
00546   {
00547     return HAL_ERROR;
00548   }
00549 }
00550
00551 /**
00552   * @brief  This function handles EXTI interrupt request.
00553   * @param  GPIO_Pin: Specifies the pins connected EXTI line
00554   * @retval None
00555   */
00556 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
00557 {
00558   /* EXTI line interrupt detected */
00559   if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
00560   {
00561     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
00562     HAL_GPIO_EXTI_Callback(GPIO_Pin);
00563   }
00564 }
00565
00566 /**
00567   * @brief  EXTI line detection callbacks.
00568   * @param  GPIO_Pin: Specifies the pins connected EXTI line
00569   * @retval None
00570   */
00571 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
00572 {
00573   /* Prevent unused argument(s) compilation warning */
00574   UNUSED(GPIO_Pin);
00575   /* NOTE: This function Should not be modified, when the callback is needed,
00576            the HAL_GPIO_EXTI_Callback could be implemented in the user file
00577    */
00578 }
00579
00580 /**
00581   * @}
00582   */
00583
00584 /**
00585   * @}
00586   */
00587
00588 #endif /* HAL_GPIO_MODULE_ENABLED */
00589 /**
00590   * @}
00591   */
00592
00593 /**
00594   * @}
00595   */
00596
00597 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_gpio.h Source File

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stm32f1xx_hal_gpio.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_gpio.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of GPIO HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_GPIO_H
00040 #define __STM32F1xx_HAL_GPIO_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup GPIO
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup GPIO_Exported_Types GPIO Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief GPIO Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
00068                            This parameter can be any value of @ref GPIO_pins_define */
00069
00070   uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
00071                            This parameter can be a value of @ref GPIO_mode_define */
00072
00073   uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
00074                            This parameter can be a value of @ref GPIO_pull_define */
00075
00076   uint32_t Speed;     /*!< Specifies the speed for the selected pins.
00077                            This parameter can be a value of @ref GPIO_speed_define */
00078 }GPIO_InitTypeDef;
00079
00080 /**
00081   * @brief  GPIO Bit SET and Bit RESET enumeration
00082   */
00083 typedef enum
00084 {
00085   GPIO_PIN_RESET = 0U,
00086   GPIO_PIN_SET
00087 }GPIO_PinState;
00088 /**
00089   * @}
00090   */
00091
00092 /* Exported constants --------------------------------------------------------*/
00093
00094 /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
00095   * @{
00096   */
00097
00098 /** @defgroup GPIO_pins_define GPIO pins define
00099   * @{
00100   */
00101 #define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
00102 #define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
00103 #define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
00104 #define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
00105 #define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
00106 #define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
00107 #define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
00108 #define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
00109 #define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
00110 #define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
00111 #define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
00112 #define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
00113 #define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
00114 #define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
00115 #define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
00116 #define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
00117 #define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
00118
00119 #define GPIO_PIN_MASK              0x0000FFFFU /* PIN mask for assert test */
00120 /**
00121   * @}
00122   */
00123
00124 /** @defgroup GPIO_mode_define GPIO mode define
00125   * @brief GPIO Configuration Mode
00126   *        Elements values convention: 0xX0yz00YZ
00127   *           - X  : GPIO mode or EXTI Mode
00128   *           - y  : External IT or Event trigger detection
00129   *           - z  : IO configuration on External IT or Event
00130   *           - Y  : Output type (Push Pull or Open Drain)
00131   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
00132   * @{
00133   */
00134 #define  GPIO_MODE_INPUT                        0x00000000U   /*!< Input Floating Mode                   */
00135 #define  GPIO_MODE_OUTPUT_PP                    0x00000001U   /*!< Output Push Pull Mode                 */
00136 #define  GPIO_MODE_OUTPUT_OD                    0x00000011U   /*!< Output Open Drain Mode                */
00137 #define  GPIO_MODE_AF_PP                        0x00000002U   /*!< Alternate Function Push Pull Mode     */
00138 #define  GPIO_MODE_AF_OD                        0x00000012U   /*!< Alternate Function Open Drain Mode    */
00139 #define  GPIO_MODE_AF_INPUT                     GPIO_MODE_INPUT          /*!< Alternate Function Input Mode         */
00140
00141 #define  GPIO_MODE_ANALOG                       0x00000003U   /*!< Analog Mode  */
00142
00143 #define  GPIO_MODE_IT_RISING                    0x10110000U   /*!< External Interrupt Mode with Rising edge trigger detection          */
00144 #define  GPIO_MODE_IT_FALLING                   0x10210000U   /*!< External Interrupt Mode with Falling edge trigger detection         */
00145 #define  GPIO_MODE_IT_RISING_FALLING            0x10310000U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
00146
00147 #define  GPIO_MODE_EVT_RISING                   0x10120000U   /*!< External Event Mode with Rising edge trigger detection               */
00148 #define  GPIO_MODE_EVT_FALLING                  0x10220000U   /*!< External Event Mode with Falling edge trigger detection              */
00149 #define  GPIO_MODE_EVT_RISING_FALLING           0x10320000U   /*!< External Event Mode with Rising/Falling edge trigger detection       */
00150
00151 /**
00152   * @}
00153   */
00154
00155 /** @defgroup GPIO_speed_define  GPIO speed define
00156   * @brief GPIO Output Maximum frequency
00157   * @{
00158   */
00159 #define  GPIO_SPEED_FREQ_LOW              (GPIO_CRL_MODE0_1) /*!< Low speed */
00160 #define  GPIO_SPEED_FREQ_MEDIUM           (GPIO_CRL_MODE0_0) /*!< Medium speed */
00161 #define  GPIO_SPEED_FREQ_HIGH             (GPIO_CRL_MODE0)   /*!< High speed */
00162
00163 /**
00164   * @}
00165   */
00166
00167  /** @defgroup GPIO_pull_define GPIO pull define
00168    * @brief GPIO Pull-Up or Pull-Down Activation
00169    * @{
00170    */
00171 #define  GPIO_NOPULL        0x00000000U   /*!< No Pull-up or Pull-down activation  */
00172 #define  GPIO_PULLUP        0x00000001U   /*!< Pull-up activation                  */
00173 #define  GPIO_PULLDOWN      0x00000002U   /*!< Pull-down activation                */
00174 /**
00175   * @}
00176   */
00177
00178 /**
00179   * @}
00180   */
00181
00182 /* Exported macro ------------------------------------------------------------*/
00183 /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
00184   * @{
00185   */
00186
00187 /**
00188   * @brief  Checks whether the specified EXTI line flag is set or not.
00189   * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
00190   *         This parameter can be GPIO_PIN_x where x can be(0..15)
00191   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00192   */
00193 #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
00194
00195 /**
00196   * @brief  Clears the EXTI's line pending flags.
00197   * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
00198   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00199   * @retval None
00200   */
00201 #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
00202
00203 /**
00204   * @brief  Checks whether the specified EXTI line is asserted or not.
00205   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00206   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00207   * @retval The new state of __EXTI_LINE__ (SET or RESET).
00208   */
00209 #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
00210
00211 /**
00212   * @brief  Clears the EXTI's line pending bits.
00213   * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
00214   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
00215   * @retval None
00216   */
00217 #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
00218
00219 /**
00220   * @brief  Generates a Software interrupt on selected EXTI line.
00221   * @param  __EXTI_LINE__: specifies the EXTI line to check.
00222   *          This parameter can be GPIO_PIN_x where x can be(0..15)
00223   * @retval None
00224   */
00225 #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
00226 /**
00227   * @}
00228   */
00229
00230 /* Include GPIO HAL Extension module */
00231 #include "stm32f1xx_hal_gpio_ex.h"
00232
00233 /* Exported functions --------------------------------------------------------*/
00234 /** @addtogroup GPIO_Exported_Functions
00235   * @{
00236   */
00237
00238 /** @addtogroup GPIO_Exported_Functions_Group1
00239   * @{
00240   */
00241 /* Initialization and de-initialization functions *****************************/
00242 void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
00243 void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
00244 /**
00245   * @}
00246   */
00247
00248 /** @addtogroup GPIO_Exported_Functions_Group2
00249   * @{
00250   */
00251 /* IO operation functions *****************************************************/
00252 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00253 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
00254 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00255 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
00256 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
00257 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
00258
00259 /**
00260   * @}
00261   */
00262
00263 /**
00264   * @}
00265   */
00266 /* Private types -------------------------------------------------------------*/
00267 /* Private variables ---------------------------------------------------------*/
00268 /* Private constants ---------------------------------------------------------*/
00269 /** @defgroup GPIO_Private_Constants GPIO Private Constants
00270   * @{
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277 /* Private macros ------------------------------------------------------------*/
00278 /** @defgroup GPIO_Private_Macros GPIO Private Macros
00279   * @{
00280   */
00281 #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
00282 #define IS_GPIO_PIN(PIN)           ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
00283 #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
00284                             ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
00285                             ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
00286                             ((MODE) == GPIO_MODE_AF_PP)              ||\
00287                             ((MODE) == GPIO_MODE_AF_OD)              ||\
00288                             ((MODE) == GPIO_MODE_IT_RISING)          ||\
00289                             ((MODE) == GPIO_MODE_IT_FALLING)         ||\
00290                             ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
00291                             ((MODE) == GPIO_MODE_EVT_RISING)         ||\
00292                             ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
00293                             ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
00294                             ((MODE) == GPIO_MODE_ANALOG))
00295 #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
00296                               ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
00297 #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
00298                             ((PULL) == GPIO_PULLDOWN))
00299 /**
00300   * @}
00301   */
00302
00303 /* Private functions ---------------------------------------------------------*/
00304 /** @defgroup GPIO_Private_Functions GPIO Private Functions
00305   * @{
00306   */
00307
00308 /**
00309   * @}
00310   */
00311
00312 /**
00313   * @}
00314   */
00315
00316 /**
00317   * @}
00318   */
00319
00320 #ifdef __cplusplus
00321 }
00322 #endif
00323
00324 #endif /* __STM32F1xx_HAL_GPIO_H */
00325
00326 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_gpio_ex.c Source File

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stm32f1xx_hal_gpio_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_gpio_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   GPIO Extension HAL module driver.
00008   *         This file provides firmware functions to manage the following
00009   *          functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
00010   *           + Extended features functions
00011   *
00012   @verbatim
00013   ==============================================================================
00014                     ##### GPIO Peripheral extension features #####
00015   ==============================================================================
00016   [..] GPIO module on STM32F1 family, manage also the AFIO register:
00017        (+) Possibility to use the EVENTOUT Cortex feature
00018
00019                      ##### How to use this driver #####
00020   ==============================================================================
00021   [..] This driver provides functions to use EVENTOUT Cortex feature
00022     (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
00023     (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
00024     (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
00025
00026   @endverbatim
00027   ******************************************************************************
00028   * @attention
00029   *
00030   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00031   *
00032   * Redistribution and use in source and binary forms, with or without modification,
00033   * are permitted provided that the following conditions are met:
00034   *   1. Redistributions of source code must retain the above copyright notice,
00035   *      this list of conditions and the following disclaimer.
00036   *   2. Redistributions in binary form must reproduce the above copyright notice,
00037   *      this list of conditions and the following disclaimer in the documentation
00038   *      and/or other materials provided with the distribution.
00039   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00040   *      may be used to endorse or promote products derived from this software
00041   *      without specific prior written permission.
00042   *
00043   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00044   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00045   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00046   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00047   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00048   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00049   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00050   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00051   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00052   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00053   *
00054   ******************************************************************************
00055   */
00056
00057 /* Includes ------------------------------------------------------------------*/
00058 #include "stm32f1xx_hal.h"
00059
00060 /** @addtogroup STM32F1xx_HAL_Driver
00061   * @{
00062   */
00063
00064 /** @defgroup GPIOEx GPIOEx
00065   * @brief GPIO HAL module driver
00066   * @{
00067   */
00068
00069 #ifdef HAL_GPIO_MODULE_ENABLED
00070
00071 /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
00072   * @{
00073   */
00074
00075 /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
00076  *  @brief    Extended features functions
00077  *
00078 @verbatim
00079   ==============================================================================
00080                  ##### Extended features functions #####
00081   ==============================================================================
00082     [..]  This section provides functions allowing to:
00083     (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
00084     (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
00085     (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
00086
00087 @endverbatim
00088   * @{
00089   */
00090
00091 /**
00092   * @brief  Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
00093   * @param  GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
00094   *   This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
00095   * @param  GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
00096   *   This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
00097   * @retval None
00098   */
00099 void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
00100 {
00101   /* Verify the parameters */
00102   assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
00103   assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
00104
00105   /* Apply the new configuration */
00106   MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT)|(AFIO_EVCR_PIN), (GPIO_PortSource)|(GPIO_PinSource));
00107 }
00108
00109 /**
00110   * @brief  Enables the Event Output.
00111   * @retval None
00112   */
00113 void HAL_GPIOEx_EnableEventout(void)
00114 {
00115   SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
00116 }
00117
00118 /**
00119   * @brief  Disables the Event Output.
00120   * @retval None
00121   */
00122 void HAL_GPIOEx_DisableEventout(void)
00123 {
00124   CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
00125 }
00126
00127 /**
00128   * @}
00129   */
00130
00131 /**
00132   * @}
00133   */
00134
00135 #endif /* HAL_GPIO_MODULE_ENABLED */
00136
00137 /**
00138   * @}
00139   */
00140
00141 /**
00142   * @}
00143   */
00144
00145 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_gpio_ex.h Source File

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stm32f1xx_hal_gpio_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_gpio_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of GPIO HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_GPIO_EX_H
00040 #define __STM32F1xx_HAL_GPIO_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup GPIOEx GPIOEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /* Exported constants --------------------------------------------------------*/
00060
00061 /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
00062   * @{
00063   */
00064
00065 /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
00066   * @brief This section propose definition to use the Cortex EVENTOUT signal.
00067   * @{
00068   */
00069
00070 /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
00071   * @{
00072   */
00073
00074 #define AFIO_EVENTOUT_PIN_0  AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
00075 #define AFIO_EVENTOUT_PIN_1  AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
00076 #define AFIO_EVENTOUT_PIN_2  AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
00077 #define AFIO_EVENTOUT_PIN_3  AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
00078 #define AFIO_EVENTOUT_PIN_4  AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
00079 #define AFIO_EVENTOUT_PIN_5  AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
00080 #define AFIO_EVENTOUT_PIN_6  AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
00081 #define AFIO_EVENTOUT_PIN_7  AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
00082 #define AFIO_EVENTOUT_PIN_8  AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
00083 #define AFIO_EVENTOUT_PIN_9  AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
00084 #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
00085 #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
00086 #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
00087 #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
00088 #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
00089 #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
00090
00091 #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
00092                                        ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
00093                                        ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
00094                                        ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
00095                                        ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
00096                                        ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
00097                                        ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
00098                                        ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
00099                                        ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
00100                                        ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
00101                                        ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
00102                                        ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
00103                                        ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
00104                                        ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
00105                                        ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
00106                                        ((__PIN__) == AFIO_EVENTOUT_PIN_15))
00107 /**
00108   * @}
00109   */
00110
00111 /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
00112   * @{
00113   */
00114
00115 #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
00116 #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
00117 #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
00118 #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
00119 #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
00120
00121 #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
00122                                          ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
00123                                          ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
00124                                          ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
00125                                          ((__PORT__) == AFIO_EVENTOUT_PORT_E))
00126 /**
00127   * @}
00128   */
00129
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
00135   * @brief This section propose definition to remap the alternate function to some other port/pins.
00136   * @{
00137   */
00138
00139 /**
00140   * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
00141   * @note  ENABLE: Remap     (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
00142   * @retval None
00143   */
00144 #define __HAL_AFIO_REMAP_SPI1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
00145
00146 /**
00147   * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
00148   * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
00149   * @retval None
00150   */
00151 #define __HAL_AFIO_REMAP_SPI1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP)
00152
00153 /**
00154   * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
00155   * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
00156   * @retval None
00157   */
00158 #define __HAL_AFIO_REMAP_I2C1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
00159
00160 /**
00161   * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
00162   * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
00163   * @retval None
00164   */
00165 #define __HAL_AFIO_REMAP_I2C1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP)
00166
00167 /**
00168   * @brief Enable the remapping of USART1 alternate function TX and RX.
00169   * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
00170   * @retval None
00171   */
00172 #define __HAL_AFIO_REMAP_USART1_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
00173
00174 /**
00175   * @brief Disable the remapping of USART1 alternate function TX and RX.
00176   * @note  DISABLE: No remap (TX/PA9, RX/PA10)
00177   * @retval None
00178   */
00179 #define __HAL_AFIO_REMAP_USART1_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP)
00180
00181 /**
00182   * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
00183   * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
00184   * @retval None
00185   */
00186 #define __HAL_AFIO_REMAP_USART2_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
00187
00188 /**
00189   * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
00190   * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
00191   * @retval None
00192   */
00193 #define __HAL_AFIO_REMAP_USART2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP)
00194
00195 /**
00196   * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
00197   * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
00198   * @retval None
00199   */
00200 #define __HAL_AFIO_REMAP_USART3_ENABLE()  do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);            \
00201                                               SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);    \
00202                                             }while(0U)
00203 /**
00204   * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
00205   * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
00206   * @retval None
00207   */
00208 #define __HAL_AFIO_REMAP_USART3_PARTIAL() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);            \
00209                                               SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP); \
00210                                             }while(0U)
00211
00212 /**
00213   * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
00214   * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
00215   * @retval None
00216   */
00217 #define __HAL_AFIO_REMAP_USART3_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);       \
00218                                               SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP); \
00219                                             }while(0U)
00220
00221 /**
00222   * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
00223   * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
00224   * @retval None
00225   */
00226 #define __HAL_AFIO_REMAP_TIM1_ENABLE()  do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);         \
00227                                             SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP); \
00228                                           }while(0U)
00229
00230 /**
00231   * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
00232   * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
00233   * @retval None
00234   */
00235 #define __HAL_AFIO_REMAP_TIM1_PARTIAL()  do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);            \
00236                                              SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP); \
00237                                            }while(0U)
00238
00239 /**
00240   * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
00241   * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
00242   * @retval None
00243   */
00244 #define __HAL_AFIO_REMAP_TIM1_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);       \
00245                                             SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP); \
00246                                           }while(0U)
00247
00248 /**
00249   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
00250   * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
00251   * @retval None
00252   */
00253 #define __HAL_AFIO_REMAP_TIM2_ENABLE()  do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);         \
00254                                             SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP); \
00255                                           }while(0U)
00256
00257 /**
00258   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
00259   * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
00260   * @retval None
00261   */
00262 #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2()  do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);             \
00263                                                SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2); \
00264                                              }while(0U)
00265
00266 /**
00267   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
00268   * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
00269   * @retval None
00270   */
00271 #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1()  do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);             \
00272                                                SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1); \
00273                                              }while(0U)
00274
00275 /**
00276   * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
00277   * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
00278   * @retval None
00279   */
00280 #define __HAL_AFIO_REMAP_TIM2_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);         \
00281                                             SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);   \
00282                                           }while(0U)
00283
00284 /**
00285   * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
00286   * @note  ENABLE: Full remap     (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
00287   * @note  TIM3_ETR on PE0 is not re-mapped.
00288   * @retval None
00289   */
00290 #define __HAL_AFIO_REMAP_TIM3_ENABLE()  do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);         \
00291                                             SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP); \
00292                                           }while(0U)
00293
00294 /**
00295   * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
00296   * @note  PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
00297   * @note  TIM3_ETR on PE0 is not re-mapped.
00298   * @retval None
00299   */
00300 #define __HAL_AFIO_REMAP_TIM3_PARTIAL()    do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);            \
00301                                                SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP); \
00302                                              }while(0U)
00303
00304 /**
00305   * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
00306   * @note  DISABLE: No remap      (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
00307   * @note  TIM3_ETR on PE0 is not re-mapped.
00308   * @retval None
00309   */
00310 #define __HAL_AFIO_REMAP_TIM3_DISABLE()   do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);           \
00311                                               SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);     \
00312                                             }while(0U)
00313
00314 /**
00315   * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
00316   * @note  ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
00317   * @note  TIM4_ETR on PE0 is not re-mapped.
00318   * @retval None
00319   */
00320 #define __HAL_AFIO_REMAP_TIM4_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
00321
00322 /**
00323   * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
00324   * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
00325   * @note  TIM4_ETR on PE0 is not re-mapped.
00326   * @retval None
00327   */
00328 #define __HAL_AFIO_REMAP_TIM4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP)
00329
00330 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
00331
00332 /**
00333   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
00334   * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
00335   * @retval None
00336   */
00337 #define __HAL_AFIO_REMAP_CAN1_1()   do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);         \
00338                                         SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);    \
00339                                       }while(0U)
00340
00341 /**
00342   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
00343   * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
00344   * @retval None
00345   */
00346 #define __HAL_AFIO_REMAP_CAN1_2()   do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);         \
00347                                         SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);    \
00348                                       }while(0U)
00349
00350 /**
00351   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
00352   * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
00353   * @retval None
00354   */
00355 #define __HAL_AFIO_REMAP_CAN1_3()  do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);                 \
00356                                        SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);       \
00357                                      }while(0U)
00358 #endif
00359
00360 /**
00361   * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
00362   *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
00363   *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
00364   *        on 100-pin and 144-pin packages, no need for remapping).
00365   * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
00366   * @retval None
00367   */
00368 #define __HAL_AFIO_REMAP_PD01_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
00369
00370 /**
00371   * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
00372   *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
00373   *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
00374   *        on 100-pin and 144-pin packages, no need for remapping).
00375   * @note  DISABLE: No remapping of PD0 and PD1
00376   * @retval None
00377   */
00378 #define __HAL_AFIO_REMAP_PD01_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP)
00379
00380 #if defined(AFIO_MAPR_TIM5CH4_IREMAP)
00381 /**
00382   * @brief Enable the remapping of TIM5CH4.
00383   * @note  ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
00384   * @note  This function is available only in high density value line devices.
00385   * @retval None
00386   */
00387 #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
00388
00389 /**
00390   * @brief Disable the remapping of TIM5CH4.
00391   * @note  DISABLE: TIM5_CH4 is connected to PA3
00392   * @note  This function is available only in high density value line devices.
00393   * @retval None
00394   */
00395 #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP)
00396 #endif
00397
00398 #if defined(AFIO_MAPR_ETH_REMAP)
00399 /**
00400   * @brief Enable the remapping of Ethernet MAC connections with the PHY.
00401   * @note  ENABLE: Remap     (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
00402   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00403   * @retval None
00404   */
00405 #define __HAL_AFIO_REMAP_ETH_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
00406
00407 /**
00408   * @brief Disable the remapping of Ethernet MAC connections with the PHY.
00409   * @note  DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5,  RXD2/PB0,  RXD3/PB1)
00410   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00411   * @retval None
00412   */
00413 #define __HAL_AFIO_REMAP_ETH_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP)
00414 #endif
00415
00416 #if defined(AFIO_MAPR_CAN2_REMAP)
00417
00418 /**
00419   * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
00420   * @note  ENABLE: Remap     (CAN2_RX/PB5,  CAN2_TX/PB6)
00421   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00422   * @retval None
00423   */
00424 #define __HAL_AFIO_REMAP_CAN2_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
00425
00426 /**
00427   * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
00428   * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
00429   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00430   * @retval None
00431   */
00432 #define __HAL_AFIO_REMAP_CAN2_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP)
00433 #endif
00434
00435 #if defined(AFIO_MAPR_MII_RMII_SEL)
00436 /**
00437   * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
00438   * @note  ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
00439   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00440   * @retval None
00441   */
00442 #define __HAL_AFIO_ETH_RMII() SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
00443
00444 /**
00445   * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
00446   * @note  ETH_MII: Configure Ethernet MAC for connection with an MII PHY
00447   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00448   * @retval None
00449   */
00450 #define __HAL_AFIO_ETH_MII()  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL)
00451 #endif
00452
00453 /**
00454   * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
00455   * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
00456   * @retval None
00457   */
00458 #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
00459
00460 /**
00461   * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
00462   * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
00463   * @retval None
00464   */
00465 #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP)
00466
00467 /**
00468   * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
00469   * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
00470   * @retval None
00471   */
00472 #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
00473
00474 /**
00475   * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
00476   * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
00477   * @retval None
00478   */
00479 #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP)
00480
00481 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
00482
00483 /**
00484   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
00485   * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
00486   * @retval None
00487   */
00488 #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
00489
00490 /**
00491   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
00492   * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
00493   * @retval None
00494   */
00495 #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP)
00496 #endif
00497
00498 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
00499
00500 /**
00501   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
00502   * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
00503   * @retval None
00504   */
00505 #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
00506
00507 /**
00508   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
00509   * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
00510   * @retval None
00511   */
00512 #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP)
00513 #endif
00514
00515 /**
00516   * @brief Enable the Serial wire JTAG configuration
00517   * @note  ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
00518   * @retval None
00519   */
00520 #define __HAL_AFIO_REMAP_SWJ_ENABLE()  do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG);         \
00521                                            SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);     \
00522                                          }while(0U)
00523
00524 /**
00525   * @brief Enable the Serial wire JTAG configuration
00526   * @note  NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
00527   * @retval None
00528   */
00529 #define __HAL_AFIO_REMAP_SWJ_NONJTRST()   do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG);         \
00530                                               SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);  \
00531                                             }while(0U)
00532
00533 /**
00534   * @brief Enable the Serial wire JTAG configuration
00535   * @note  NOJTAG: JTAG-DP Disabled and SW-DP Enabled
00536   * @retval None
00537   */
00538 #define __HAL_AFIO_REMAP_SWJ_NOJTAG()   do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG);           \
00539                                             SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); \
00540                                           }while(0U)
00541
00542 /**
00543   * @brief Disable the Serial wire JTAG configuration
00544   * @note  DISABLE: JTAG-DP Disabled and SW-DP Disabled
00545   * @retval None
00546   */
00547 #define __HAL_AFIO_REMAP_SWJ_DISABLE()  do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG);         \
00548                                             SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);   \
00549                                           }while(0U)
00550
00551 #if defined(AFIO_MAPR_SPI3_REMAP)
00552
00553 /**
00554   * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
00555   * @note  ENABLE: Remap     (SPI3_NSS-I2S3_WS/PA4,  SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
00556   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00557   * @retval None
00558   */
00559 #define __HAL_AFIO_REMAP_SPI3_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
00560
00561 /**
00562   * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
00563   * @note  DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3,  SPI3_MISO/PB4,  SPI3_MOSI-I2S3_SD/PB5).
00564   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00565   * @retval None
00566   */
00567 #define __HAL_AFIO_REMAP_SPI3_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP)
00568 #endif
00569
00570 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
00571
00572 /**
00573   * @brief Control of TIM2_ITR1 internal mapping.
00574   * @note  TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
00575   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00576   * @retval None
00577   */
00578 #define __HAL_AFIO_TIM2ITR1_TO_USB() SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
00579
00580 /**
00581   * @brief Control of TIM2_ITR1 internal mapping.
00582   * @note  TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
00583   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00584   * @retval None
00585   */
00586 #define __HAL_AFIO_TIM2ITR1_TO_ETH() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP)
00587 #endif
00588
00589 #if defined(AFIO_MAPR_PTP_PPS_REMAP)
00590
00591 /**
00592   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
00593   * @note  ENABLE: PTP_PPS is output on PB5 pin.
00594   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00595   * @retval None
00596   */
00597 #define __HAL_AFIO_ETH_PTP_PPS_ENABLE()  SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
00598
00599 /**
00600   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
00601   * @note  DISABLE: PTP_PPS not output on PB5 pin.
00602   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
00603   * @retval None
00604   */
00605 #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP)
00606 #endif
00607
00608 #if defined(AFIO_MAPR2_TIM9_REMAP)
00609
00610 /**
00611   * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
00612   * @note  ENABLE: Remap     (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
00613   * @retval None
00614   */
00615 #define __HAL_AFIO_REMAP_TIM9_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
00616
00617 /**
00618   * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
00619   * @note  DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
00620   * @retval None
00621   */
00622 #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
00623 #endif
00624
00625 #if defined(AFIO_MAPR2_TIM10_REMAP)
00626
00627 /**
00628   * @brief Enable the remapping of TIM10_CH1.
00629   * @note  ENABLE: Remap     (TIM10_CH1 on PF6).
00630   * @retval None
00631   */
00632 #define __HAL_AFIO_REMAP_TIM10_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
00633
00634 /**
00635   * @brief Disable the remapping of TIM10_CH1.
00636   * @note  DISABLE: No remap (TIM10_CH1 on PB8).
00637   * @retval None
00638   */
00639 #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
00640 #endif
00641
00642 #if defined(AFIO_MAPR2_TIM11_REMAP)
00643 /**
00644   * @brief Enable the remapping of TIM11_CH1.
00645   * @note  ENABLE: Remap     (TIM11_CH1 on PF7).
00646   * @retval None
00647   */
00648 #define __HAL_AFIO_REMAP_TIM11_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
00649
00650 /**
00651   * @brief Disable the remapping of TIM11_CH1.
00652   * @note  DISABLE: No remap (TIM11_CH1 on PB9).
00653   * @retval None
00654   */
00655 #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
00656 #endif
00657
00658 #if defined(AFIO_MAPR2_TIM13_REMAP)
00659
00660 /**
00661   * @brief Enable the remapping of TIM13_CH1.
00662   * @note  ENABLE: Remap     STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
00663   * @retval None
00664   */
00665 #define __HAL_AFIO_REMAP_TIM13_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
00666
00667 /**
00668   * @brief Disable the remapping of TIM13_CH1.
00669   * @note  DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
00670   * @retval None
00671   */
00672 #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
00673 #endif
00674
00675 #if defined(AFIO_MAPR2_TIM14_REMAP)
00676
00677 /**
00678   * @brief Enable the remapping of TIM14_CH1.
00679   * @note  ENABLE: Remap     STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
00680   * @retval None
00681   */
00682 #define __HAL_AFIO_REMAP_TIM14_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
00683
00684 /**
00685   * @brief Disable the remapping of TIM14_CH1.
00686   * @note  DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
00687   * @retval None
00688   */
00689 #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
00690 #endif
00691
00692 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
00693
00694 /**
00695   * @brief Controls the use of the optional FSMC_NADV signal.
00696   * @note  DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
00697   * @retval None
00698   */
00699 #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
00700
00701 /**
00702   * @brief Controls the use of the optional FSMC_NADV signal.
00703   * @note  CONNECTED: The NADV signal is connected to the output (default).
00704   * @retval None
00705   */
00706 #define __HAL_AFIO_FSMCNADV_CONNECTED()    CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
00707 #endif
00708
00709 #if defined(AFIO_MAPR2_TIM15_REMAP)
00710
00711 /**
00712   * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
00713   * @note  ENABLE: Remap     (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
00714   * @retval None
00715   */
00716 #define __HAL_AFIO_REMAP_TIM15_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
00717
00718 /**
00719   * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
00720   * @note  DISABLE: No remap (TIM15_CH1 on PA2  and TIM15_CH2 on PA3).
00721   * @retval None
00722   */
00723 #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
00724 #endif
00725
00726 #if defined(AFIO_MAPR2_TIM16_REMAP)
00727
00728 /**
00729   * @brief Enable the remapping of TIM16_CH1.
00730   * @note  ENABLE: Remap     (TIM16_CH1 on PA6).
00731   * @retval None
00732   */
00733 #define __HAL_AFIO_REMAP_TIM16_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
00734
00735 /**
00736   * @brief Disable the remapping of TIM16_CH1.
00737   * @note  DISABLE: No remap (TIM16_CH1 on PB8).
00738   * @retval None
00739   */
00740 #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
00741 #endif
00742
00743 #if defined(AFIO_MAPR2_TIM17_REMAP)
00744
00745 /**
00746   * @brief Enable the remapping of TIM17_CH1.
00747   * @note  ENABLE: Remap     (TIM17_CH1 on PA7).
00748   * @retval None
00749   */
00750 #define __HAL_AFIO_REMAP_TIM17_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
00751
00752 /**
00753   * @brief Disable the remapping of TIM17_CH1.
00754   * @note  DISABLE: No remap (TIM17_CH1 on PB9).
00755   * @retval None
00756   */
00757 #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
00758 #endif
00759
00760 #if defined(AFIO_MAPR2_CEC_REMAP)
00761
00762 /**
00763   * @brief Enable the remapping of CEC.
00764   * @note  ENABLE: Remap     (CEC on PB10).
00765   * @retval None
00766   */
00767 #define __HAL_AFIO_REMAP_CEC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
00768
00769 /**
00770   * @brief Disable the remapping of CEC.
00771   * @note  DISABLE: No remap (CEC on PB8).
00772   * @retval None
00773   */
00774 #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
00775 #endif
00776
00777 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
00778
00779 /**
00780   * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
00781   * @note  ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
00782   * @retval None
00783   */
00784 #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
00785
00786 /**
00787   * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
00788   * @note  DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
00789   * @retval None
00790   */
00791 #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
00792 #endif
00793
00794 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
00795
00796 /**
00797   * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
00798   * @note  ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
00799   * @retval None
00800   */
00801 #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
00802
00803 /**
00804   * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
00805   * @note  DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
00806   * @retval None
00807   */
00808 #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
00809 #endif
00810
00811 #if defined(AFIO_MAPR2_TIM12_REMAP)
00812
00813 /**
00814   * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
00815   * @note  ENABLE: Remap     (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
00816   * @note  This bit is available only in high density value line devices.
00817   * @retval None
00818   */
00819 #define __HAL_AFIO_REMAP_TIM12_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
00820
00821 /**
00822   * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
00823   * @note  DISABLE: No remap (TIM12_CH1 on PC4  and TIM12_CH2 on PC5).
00824   * @note  This bit is available only in high density value line devices.
00825   * @retval None
00826   */
00827 #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
00828 #endif
00829
00830 #if defined(AFIO_MAPR2_MISC_REMAP)
00831
00832 /**
00833   * @brief Miscellaneous features remapping.
00834   *        This bit is set and cleared by software. It controls miscellaneous features.
00835   *        The DMA2 channel 5 interrupt position in the vector table.
00836   *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
00837   * @note  ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
00838   *        selected as DAC Trigger 3, TIM15 triggers TIM1/3.
00839   * @note  This bit is available only in high density value line devices.
00840   * @retval None
00841   */
00842 #define __HAL_AFIO_REMAP_MISC_ENABLE()  SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
00843
00844 /**
00845   * @brief Miscellaneous features remapping.
00846   *        This bit is set and cleared by software. It controls miscellaneous features.
00847   *        The DMA2 channel 5 interrupt position in the vector table.
00848   *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
00849   * @note  DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
00850   *        event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
00851   * @note  This bit is available only in high density value line devices.
00852   * @retval None
00853   */
00854 #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
00855 #endif
00856
00857 /**
00858   * @}
00859   */
00860
00861 /**
00862   * @}
00863   */
00864
00865 /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
00866   * @{
00867   */
00868 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
00869 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
00870                                    ((__GPIOx__) == (GPIOB))? 1U :\
00871                                    ((__GPIOx__) == (GPIOC))? 2U :3U)
00872 #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
00873 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
00874                                    ((__GPIOx__) == (GPIOB))? 1U :\
00875                                    ((__GPIOx__) == (GPIOC))? 2U :\
00876                                    ((__GPIOx__) == (GPIOD))? 3U :4U)
00877 #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
00878 #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
00879                                    ((__GPIOx__) == (GPIOB))? 1U :\
00880                                    ((__GPIOx__) == (GPIOC))? 2U :\
00881                                    ((__GPIOx__) == (GPIOD))? 3U :\
00882                                    ((__GPIOx__) == (GPIOE))? 4U :\
00883                                    ((__GPIOx__) == (GPIOF))? 5U :6U)
00884 #endif
00885
00886 /**
00887   * @}
00888   */
00889
00890 /* Exported macro ------------------------------------------------------------*/
00891 /* Exported functions --------------------------------------------------------*/
00892
00893 /** @addtogroup GPIOEx_Exported_Functions
00894   * @{
00895   */
00896
00897 /** @addtogroup GPIOEx_Exported_Functions_Group1
00898   * @{
00899   */
00900 void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
00901 void HAL_GPIOEx_EnableEventout(void);
00902 void HAL_GPIOEx_DisableEventout(void);
00903
00904 /**
00905   * @}
00906   */
00907
00908 /**
00909   * @}
00910   */
00911
00912 /**
00913   * @}
00914   */
00915
00916 /**
00917   * @}
00918   */
00919
00920 #ifdef __cplusplus
00921 }
00922 #endif
00923
00924 #endif /* __STM32F1xx_HAL_GPIO_EX_H */
00925
00926 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_hcd.c Source File

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stm32f1xx_hal_hcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_hcd.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   HCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     (#)Declare a HCD_HandleTypeDef handle structure, for example:
00021        HCD_HandleTypeDef  hhcd;
00022
00023     (#)Fill parameters of Init structure in HCD handle
00024
00025     (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
00026
00027     (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
00028         (##) Enable the HCD/USB Low Level interface clock using the following macro
00029              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE()
00030
00031         (##) Initialize the related GPIO clocks
00032         (##) Configure HCD pin-out
00033         (##) Configure HCD NVIC interrupt
00034
00035     (#)Associate the Upper USB Host stack to the HAL HCD Driver:
00036         (##) hhcd.pData = phost;
00037
00038     (#)Enable HCD transmission and reception:
00039         (##) HAL_HCD_Start();
00040
00041   @endverbatim
00042   ******************************************************************************
00043   * @attention
00044   *
00045   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00046   *
00047   * Redistribution and use in source and binary forms, with or without modification,
00048   * are permitted provided that the following conditions are met:
00049   *   1. Redistributions of source code must retain the above copyright notice,
00050   *      this list of conditions and the following disclaimer.
00051   *   2. Redistributions in binary form must reproduce the above copyright notice,
00052   *      this list of conditions and the following disclaimer in the documentation
00053   *      and/or other materials provided with the distribution.
00054   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00055   *      may be used to endorse or promote products derived from this software
00056   *      without specific prior written permission.
00057   *
00058   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00059   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00060   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00061   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00062   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00063   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00064   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00065   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00066   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00067   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00068   *
00069   ******************************************************************************
00070   */
00071
00072 /* Includes ------------------------------------------------------------------*/
00073 #include "stm32f1xx_hal.h"
00074 /** @addtogroup STM32F1xx_HAL_Driver
00075   * @{
00076   */
00077
00078
00079 #ifdef HAL_HCD_MODULE_ENABLED
00080
00081 #if defined(STM32F105xC) || defined(STM32F107xC)
00082
00083 /** @defgroup HCD HCD
00084   * @brief HCD HAL module driver
00085   * @{
00086   */
00087
00088 /* Private types -------------------------------------------------------------*/
00089 /* Private variables ---------------------------------------------------------*/
00090 /* Private constants ---------------------------------------------------------*/
00091 /* Private macros ------------------------------------------------------------*/
00092 /* Private function ----------------------------------------------------------*/
00093 /** @defgroup HCD_Private_Functions HCD Private Functions
00094   * @{
00095   */
00096 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00097 static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00098 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
00099 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported functions --------------------------------------------------------*/
00105 /** @defgroup HCD_Exported_Functions HCD Exported Functions
00106   * @{
00107   */
00108
00109 /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00110  *  @brief    Initialization and Configuration functions
00111  *
00112 @verbatim
00113  ===============================================================================
00114           ##### Initialization and de-initialization functions #####
00115  ===============================================================================
00116     [..]  This section provides functions allowing to:
00117
00118 @endverbatim
00119   * @{
00120   */
00121
00122 /**
00123   * @brief  Initialize the host driver
00124   * @param  hhcd: HCD handle
00125   * @retval HAL status
00126   */
00127 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
00128 {
00129   /* Check the HCD handle allocation */
00130   if(hhcd == NULL)
00131   {
00132     return HAL_ERROR;
00133   }
00134
00135   /* Check the parameters */
00136   assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
00137
00138   if(hhcd->State == HAL_HCD_STATE_RESET)
00139   {
00140     /* Allocate lock resource and initialize it */
00141     hhcd->Lock = HAL_UNLOCKED;
00142
00143     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00144     HAL_HCD_MspInit(hhcd);
00145   }
00146
00147   hhcd->State = HAL_HCD_STATE_BUSY;
00148
00149   /* Disable the Interrupts */
00150   __HAL_HCD_DISABLE(hhcd);
00151
00152   /* Init the Core (common init.) */
00153   USB_CoreInit(hhcd->Instance, hhcd->Init);
00154
00155   /* Force Host Mode*/
00156   USB_SetCurrentMode(hhcd->Instance , USB_HOST_MODE);
00157
00158   /* Init Host */
00159   USB_HostInit(hhcd->Instance, hhcd->Init);
00160
00161   hhcd->State= HAL_HCD_STATE_READY;
00162
00163   return HAL_OK;
00164 }
00165
00166 /**
00167   * @brief  Initialize a host channel
00168   * @param  hhcd: HCD handle
00169   * @param  ch_num: Channel number.
00170   *         This parameter can be a value from 1 to 15
00171   * @param  epnum: Endpoint number.
00172   *          This parameter can be a value from 1 to 15
00173   * @param  dev_address : Current device address
00174   *          This parameter can be a value from 0 to 255
00175   * @param  speed: Current device speed.
00176   *          This parameter can be one of these values:
00177   *            HCD_SPEED_FULL: Full speed mode,
00178   *            HCD_SPEED_LOW: Low speed mode
00179   * @param  ep_type: Endpoint Type.
00180   *          This parameter can be one of these values:
00181   *            EP_TYPE_CTRL: Control type,
00182   *            EP_TYPE_ISOC: Isochronous type,
00183   *            EP_TYPE_BULK: Bulk type,
00184   *            EP_TYPE_INTR: Interrupt type
00185   * @param  mps: Max Packet Size.
00186   *          This parameter can be a value from 0 to32K
00187   * @retval HAL status
00188   */
00189 HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00190                                   uint8_t ch_num,
00191                                   uint8_t epnum,
00192                                   uint8_t dev_address,
00193                                   uint8_t speed,
00194                                   uint8_t ep_type,
00195                                   uint16_t mps)
00196 {
00197   HAL_StatusTypeDef status = HAL_OK;
00198
00199   __HAL_LOCK(hhcd);
00200
00201   hhcd->hc[ch_num].dev_addr = dev_address;
00202   hhcd->hc[ch_num].max_packet = mps;
00203   hhcd->hc[ch_num].ch_num = ch_num;
00204   hhcd->hc[ch_num].ep_type = ep_type;
00205   hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
00206   hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80U) == 0x80U);
00207   hhcd->hc[ch_num].speed = speed;
00208
00209   status =  USB_HC_Init(hhcd->Instance,
00210                         ch_num,
00211                         epnum,
00212                         dev_address,
00213                         speed,
00214                         ep_type,
00215                         mps);
00216   __HAL_UNLOCK(hhcd);
00217
00218   return status;
00219 }
00220
00221 /**
00222   * @brief  Halt a host channel
00223   * @param  hhcd: HCD handle
00224   * @param  ch_num: Channel number.
00225   *         This parameter can be a value from 1 to 15
00226   * @retval HAL status
00227   */
00228 HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
00229                                   uint8_t ch_num)
00230 {
00231   __HAL_LOCK(hhcd);
00232   USB_HC_Halt(hhcd->Instance, ch_num);
00233   __HAL_UNLOCK(hhcd);
00234
00235   return HAL_OK;
00236 }
00237
00238 /**
00239   * @brief  DeInitialize the host driver
00240   * @param  hhcd: HCD handle
00241   * @retval HAL status
00242   */
00243 HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
00244 {
00245   /* Check the HCD handle allocation */
00246   if(hhcd == NULL)
00247   {
00248     return HAL_ERROR;
00249   }
00250
00251   hhcd->State = HAL_HCD_STATE_BUSY;
00252
00253   /* DeInit the low level hardware */
00254   HAL_HCD_MspDeInit(hhcd);
00255
00256   __HAL_HCD_DISABLE(hhcd);
00257
00258   hhcd->State = HAL_HCD_STATE_RESET;
00259
00260   return HAL_OK;
00261 }
00262
00263 /**
00264   * @brief  Initializes the HCD MSP.
00265   * @param  hhcd: HCD handle
00266   * @retval None
00267   */
00268 __weak void  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
00269 {
00270   /* Prevent unused argument(s) compilation warning */
00271   UNUSED(hhcd);
00272   /* NOTE : This function Should not be modified, when the callback is needed,
00273             the HAL_HCD_MspInit could be implemented in the user file
00274    */
00275 }
00276
00277 /**
00278   * @brief  DeInitializes HCD MSP.
00279   * @param  hhcd: HCD handle
00280   * @retval None
00281   */
00282 __weak void  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
00283 {
00284   /* Prevent unused argument(s) compilation warning */
00285   UNUSED(hhcd);
00286   /* NOTE : This function Should not be modified, when the callback is needed,
00287             the HAL_HCD_MspDeInit could be implemented in the user file
00288    */
00289 }
00290
00291 /**
00292   * @}
00293   */
00294
00295 /** @defgroup HCD_Exported_Functions_Group2 IO operation functions
00296   *  @brief   HCD IO operation functions
00297   *
00298 @verbatim
00299  ===============================================================================
00300                       ##### IO operation functions #####
00301  ===============================================================================
00302     This subsection provides a set of functions allowing to manage the USB Host Data
00303     Transfer
00304
00305 @endverbatim
00306   * @{
00307   */
00308
00309 /**
00310   * @brief  Submit a new URB for processing
00311   * @param  hhcd: HCD handle
00312   * @param  ch_num: Channel number.
00313   *         This parameter can be a value from 1 to 15
00314   * @param  direction: Channel number.
00315   *          This parameter can be one of these values:
00316   *           0 : Output / 1 : Input
00317   * @param  ep_type: Endpoint Type.
00318   *          This parameter can be one of these values:
00319   *            EP_TYPE_CTRL: Control type/
00320   *            EP_TYPE_ISOC: Isochronous type/
00321   *            EP_TYPE_BULK: Bulk type/
00322   *            EP_TYPE_INTR: Interrupt type/
00323   * @param  token: Endpoint Type.
00324   *          This parameter can be one of these values:
00325   *            0: HC_PID_SETUP / 1: HC_PID_DATA1
00326   * @param  pbuff: pointer to URB data
00327   * @param  length: Length of URB data
00328   * @param  do_ping: activate do ping protocol (for high speed only).
00329   *          This parameter can be one of these values:
00330   *           0 : do ping inactive / 1 : do ping active
00331   * @retval HAL status
00332   */
00333 HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00334                                            uint8_t ch_num,
00335                                            uint8_t direction,
00336                                            uint8_t ep_type,
00337                                            uint8_t token,
00338                                            uint8_t* pbuff,
00339                                            uint16_t length,
00340                                            uint8_t do_ping)
00341 {
00342   hhcd->hc[ch_num].ep_is_in = direction;
00343   hhcd->hc[ch_num].ep_type  = ep_type;
00344
00345   if(token == 0U)
00346   {
00347     hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
00348   }
00349   else
00350   {
00351     hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00352   }
00353
00354   /* Manage Data Toggle */
00355   switch(ep_type)
00356   {
00357   case EP_TYPE_CTRL:
00358     if((token == 1U) && (direction == 0U)) /*send data */
00359     {
00360       if (length == 0U)
00361       { /* For Status OUT stage, Length==0, Status Out PID = 1 */
00362         hhcd->hc[ch_num].toggle_out = 1U;
00363       }
00364
00365       /* Set the Data Toggle bit as per the Flag */
00366       if ( hhcd->hc[ch_num].toggle_out == 0U)
00367       { /* Put the PID 0 */
00368         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00369       }
00370       else
00371       { /* Put the PID 1 */
00372         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00373       }
00374       if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
00375       {
00376         hhcd->hc[ch_num].do_ping = do_ping;
00377       }
00378     }
00379     break;
00380
00381   case EP_TYPE_BULK:
00382     if(direction == 0U)
00383     {
00384       /* Set the Data Toggle bit as per the Flag */
00385       if ( hhcd->hc[ch_num].toggle_out == 0U)
00386       { /* Put the PID 0 */
00387         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00388       }
00389       else
00390       { /* Put the PID 1 */
00391         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00392       }
00393       if(hhcd->hc[ch_num].urb_state  != URB_NOTREADY)
00394       {
00395         hhcd->hc[ch_num].do_ping = do_ping;
00396       }
00397     }
00398     else
00399     {
00400       if( hhcd->hc[ch_num].toggle_in == 0U)
00401       {
00402         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00403       }
00404       else
00405       {
00406         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00407       }
00408     }
00409     break;
00410
00411   case EP_TYPE_INTR:
00412     if(direction == 0U)
00413     {
00414       /* Set the Data Toggle bit as per the Flag */
00415       if ( hhcd->hc[ch_num].toggle_out == 0U)
00416       { /* Put the PID 0 */
00417         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00418       }
00419       else
00420       { /* Put the PID 1 */
00421         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00422       }
00423     }
00424     else
00425     {
00426       if( hhcd->hc[ch_num].toggle_in == 0U)
00427       {
00428         hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00429       }
00430       else
00431       {
00432         hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
00433       }
00434     }
00435     break;
00436
00437   case EP_TYPE_ISOC:
00438     hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
00439     break;
00440   }
00441
00442   hhcd->hc[ch_num].xfer_buff = pbuff;
00443   hhcd->hc[ch_num].xfer_len  = length;
00444   hhcd->hc[ch_num].urb_state = URB_IDLE;
00445   hhcd->hc[ch_num].xfer_count = 0U;
00446   hhcd->hc[ch_num].ch_num = ch_num;
00447   hhcd->hc[ch_num].state = HC_IDLE;
00448
00449   return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]));
00450 }
00451
00452 /**
00453   * @brief  handle HCD interrupt request.
00454   * @param  hhcd: HCD handle
00455   * @retval None
00456   */
00457 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
00458 {
00459   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00460
00461   uint32_t index = 0U, interrupt = 0U;
00462
00463   /* ensure that we are in device mode */
00464   if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
00465   {
00466     /* Avoid spurious interrupt */
00467     if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
00468     {
00469       return;
00470     }
00471
00472     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00473     {
00474      /* Incorrect mode, acknowledge the interrupt */
00475       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00476     }
00477
00478     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
00479     {
00480      /* Incorrect mode, acknowledge the interrupt */
00481       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
00482     }
00483
00484     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
00485     {
00486      /* Incorrect mode, acknowledge the interrupt */
00487       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
00488     }
00489
00490     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
00491     {
00492      /* Incorrect mode, acknowledge the interrupt */
00493       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
00494     }
00495
00496     /* Handle Host Disconnect Interrupts */
00497     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
00498     {
00499
00500       /* Cleanup HPRT */
00501       USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
00502         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
00503
00504       /* Handle Host Port Interrupts */
00505       HAL_HCD_Disconnect_Callback(hhcd);
00506       USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ);
00507       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
00508     }
00509
00510     /* Handle Host Port Interrupts */
00511     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
00512     {
00513       HCD_Port_IRQHandler (hhcd);
00514     }
00515
00516     /* Handle Host SOF Interrupts */
00517     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
00518     {
00519       HAL_HCD_SOF_Callback(hhcd);
00520       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
00521     }
00522
00523     /* Handle Host channel Interrupts */
00524     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
00525     {
00526       interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
00527       for (index = 0U; index < hhcd->Init.Host_channels ; index++)
00528       {
00529         if (interrupt & (1 << index))
00530         {
00531           if ((USBx_HC(index)->HCCHAR) &  USB_OTG_HCCHAR_EPDIR)
00532           {
00533             HCD_HC_IN_IRQHandler (hhcd, index);
00534           }
00535           else
00536           {
00537             HCD_HC_OUT_IRQHandler (hhcd, index);
00538           }
00539         }
00540       }
00541       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
00542     }
00543
00544     /* Handle Rx Queue Level Interrupts */
00545     if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
00546     {
00547       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00548
00549       HCD_RXQLVL_IRQHandler (hhcd);
00550
00551       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00552     }
00553   }
00554 }
00555
00556 /**
00557   * @brief  SOF callback.
00558   * @param  hhcd: HCD handle
00559   * @retval None
00560   */
00561 __weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
00562 {
00563   /* Prevent unused argument(s) compilation warning */
00564   UNUSED(hhcd);
00565   /* NOTE : This function Should not be modified, when the callback is needed,
00566             the HAL_HCD_SOF_Callback could be implemented in the user file
00567    */
00568 }
00569
00570 /**
00571   * @brief Connexion Event callback.
00572   * @param  hhcd: HCD handle
00573   * @retval None
00574   */
00575 __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
00576 {
00577   /* Prevent unused argument(s) compilation warning */
00578   UNUSED(hhcd);
00579   /* NOTE : This function Should not be modified, when the callback is needed,
00580             the HAL_HCD_Connect_Callback could be implemented in the user file
00581    */
00582 }
00583
00584 /**
00585   * @brief  Disonnection Event callback.
00586   * @param  hhcd: HCD handle
00587   * @retval None
00588   */
00589 __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
00590 {
00591   /* Prevent unused argument(s) compilation warning */
00592   UNUSED(hhcd);
00593   /* NOTE : This function Should not be modified, when the callback is needed,
00594             the HAL_HCD_Disconnect_Callback could be implemented in the user file
00595    */
00596 }
00597
00598 /**
00599   * @brief  Notify URB state change callback.
00600   * @param  hhcd: HCD handle
00601   * @param  chnum: Channel number.
00602   *         This parameter can be a value from 1 to 15
00603   * @param  urb_state:
00604   *          This parameter can be one of these values:
00605   *            URB_IDLE/
00606   *            URB_DONE/
00607   *            URB_NOTREADY/
00608   *            URB_NYET/
00609   *            URB_ERROR/
00610   *            URB_STALL/
00611   * @retval None
00612   */
00613 __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
00614 {
00615   /* Prevent unused argument(s) compilation warning */
00616   UNUSED(hhcd);
00617   UNUSED(chnum);
00618   UNUSED(urb_state);
00619   /* NOTE : This function Should not be modified, when the callback is needed,
00620             the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
00621    */
00622 }
00623
00624 /**
00625   * @}
00626   */
00627
00628 /** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
00629  *  @brief   management functions
00630  *
00631 @verbatim
00632  ===============================================================================
00633                       ##### Peripheral Control functions #####
00634  ===============================================================================
00635     [..]
00636     This subsection provides a set of functions allowing to control the HCD data
00637     transfers.
00638
00639 @endverbatim
00640   * @{
00641   */
00642
00643 /**
00644   * @brief  Start the host driver
00645   * @param  hhcd: HCD handle
00646   * @retval HAL status
00647   */
00648 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
00649 {
00650   __HAL_LOCK(hhcd);
00651   __HAL_HCD_ENABLE(hhcd);
00652   USB_DriveVbus(hhcd->Instance, 1U);
00653   __HAL_UNLOCK(hhcd);
00654   return HAL_OK;
00655 }
00656
00657 /**
00658   * @brief  Stop the host driver
00659   * @param  hhcd: HCD handle
00660   * @retval HAL status
00661   */
00662
00663 HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
00664 {
00665   __HAL_LOCK(hhcd);
00666   USB_StopHost(hhcd->Instance);
00667   __HAL_UNLOCK(hhcd);
00668   return HAL_OK;
00669 }
00670
00671 /**
00672   * @brief  Reset the host port
00673   * @param  hhcd: HCD handle
00674   * @retval HAL status
00675   */
00676 HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
00677 {
00678   return (USB_ResetPort(hhcd->Instance));
00679 }
00680
00681 /**
00682   * @}
00683   */
00684
00685 /** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
00686  *  @brief   Peripheral State functions
00687  *
00688 @verbatim
00689  ===============================================================================
00690                       ##### Peripheral State functions #####
00691  ===============================================================================
00692     [..]
00693     This subsection permits to get in run-time the status of the peripheral
00694     and the data flow.
00695
00696 @endverbatim
00697   * @{
00698   */
00699
00700 /**
00701   * @brief  Return the HCD handle state
00702   * @param  hhcd: HCD handle
00703   * @retval HAL state
00704   */
00705 HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
00706 {
00707   return hhcd->State;
00708 }
00709
00710 /**
00711   * @brief  Return  URB state for a channel
00712   * @param  hhcd: HCD handle
00713   * @param  chnum: Channel number.
00714   *         This parameter can be a value from 1 to 15
00715   * @retval URB state.
00716   *          This parameter can be one of these values:
00717   *            URB_IDLE/
00718   *            URB_DONE/
00719   *            URB_NOTREADY/
00720   *            URB_NYET/
00721   *            URB_ERROR/
00722   *            URB_STALL/
00723   */
00724 HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00725 {
00726   return hhcd->hc[chnum].urb_state;
00727 }
00728
00729
00730 /**
00731   * @brief  Return the last host transfer size
00732   * @param  hhcd: HCD handle
00733   * @param  chnum: Channel number.
00734   *         This parameter can be a value from 1 to 15
00735   * @retval last transfer size in byte
00736   */
00737 uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00738 {
00739   return hhcd->hc[chnum].xfer_count;
00740 }
00741
00742 /**
00743   * @brief  Return the Host Channel state
00744   * @param  hhcd: HCD handle
00745   * @param  chnum: Channel number.
00746   *         This parameter can be a value from 1 to 15
00747   * @retval Host channel state
00748   *          This parameter can be one of the these values:
00749   *            HC_IDLE/
00750   *            HC_XFRC/
00751   *            HC_HALTED/
00752   *            HC_NYET/
00753   *            HC_NAK/
00754   *            HC_STALL/
00755   *            HC_XACTERR/
00756   *            HC_BBLERR/
00757   *            HC_DATATGLERR/
00758   */
00759 HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
00760 {
00761   return hhcd->hc[chnum].state;
00762 }
00763
00764 /**
00765   * @brief  Return the current Host frame number
00766   * @param  hhcd: HCD handle
00767   * @retval Current Host frame number
00768   */
00769 uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
00770 {
00771   return (USB_GetCurrentFrame(hhcd->Instance));
00772 }
00773
00774 /**
00775   * @brief  Return the Host enumeration speed
00776   * @param  hhcd: HCD handle
00777   * @retval Enumeration speed
00778   */
00779 uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
00780 {
00781   return (USB_GetHostSpeed(hhcd->Instance));
00782 }
00783
00784 /**
00785   * @}
00786   */
00787 /**
00788   * @}
00789   */
00790
00791 /** @addtogroup HCD_Private_Functions
00792   * @{
00793   */
00794 /**
00795   * @brief  This function handles Host Channel IN interrupt requests.
00796   * @param  hhcd: HCD handle
00797   * @param  chnum: Channel number.
00798   *         This parameter can be a value from 1 to 15
00799   * @retval none
00800   */
00801 static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
00802 {
00803   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00804   uint32_t tmpreg = 0U;
00805
00806   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
00807   {
00808     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
00809     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00810   }
00811   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
00812   {
00813     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
00814   }
00815
00816   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)
00817   {
00818     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00819     hhcd->hc[chnum].state = HC_STALL;
00820     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00821     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
00822     USB_HC_Halt(hhcd->Instance, chnum);
00823   }
00824   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
00825   {
00826     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00827     USB_HC_Halt(hhcd->Instance, chnum);
00828     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00829     hhcd->hc[chnum].state = HC_DATATGLERR;
00830     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
00831   }
00832
00833   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
00834   {
00835     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00836     USB_HC_Halt(hhcd->Instance, chnum);
00837     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
00838   }
00839
00840   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
00841   {
00842     hhcd->hc[chnum].state = HC_XFRC;
00843     hhcd->hc[chnum].ErrCnt = 0U;
00844     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
00845
00846     if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
00847         (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
00848     {
00849       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00850       USB_HC_Halt(hhcd->Instance, chnum);
00851       __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00852
00853     }
00854     else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
00855     {
00856       USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
00857       hhcd->hc[chnum].urb_state = URB_DONE;
00858       HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
00859     }
00860     hhcd->hc[chnum].toggle_in ^= 1U;
00861
00862   }
00863   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
00864   {
00865     __HAL_HCD_MASK_HALT_HC_INT(chnum);
00866
00867     if(hhcd->hc[chnum].state == HC_XFRC)
00868     {
00869       hhcd->hc[chnum].urb_state  = URB_DONE;
00870     }
00871     else if (hhcd->hc[chnum].state == HC_STALL)
00872     {
00873       hhcd->hc[chnum].urb_state  = URB_STALL;
00874     }
00875     else if((hhcd->hc[chnum].state == HC_XACTERR) ||
00876             (hhcd->hc[chnum].state == HC_DATATGLERR))
00877     {
00878       if(hhcd->hc[chnum].ErrCnt++ > 3U)
00879       {
00880         hhcd->hc[chnum].ErrCnt = 0U;
00881         hhcd->hc[chnum].urb_state = URB_ERROR;
00882       }
00883       else
00884       {
00885         hhcd->hc[chnum].urb_state = URB_NOTREADY;
00886       }
00887
00888       /* re-activate the channel  */
00889       tmpreg = USBx_HC(chnum)->HCCHAR;
00890       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
00891       tmpreg |= USB_OTG_HCCHAR_CHENA;
00892       USBx_HC(chnum)->HCCHAR = tmpreg;
00893     }
00894     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
00895     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
00896   }
00897
00898   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
00899   {
00900     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00901      hhcd->hc[chnum].ErrCnt++;
00902      hhcd->hc[chnum].state = HC_XACTERR;
00903      USB_HC_Halt(hhcd->Instance, chnum);
00904      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
00905   }
00906   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
00907   {
00908     if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
00909     {
00910       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00911       USB_HC_Halt(hhcd->Instance, chnum);
00912     }
00913     else if  ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
00914               (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
00915     {
00916       /* re-activate the channel  */
00917       tmpreg = USBx_HC(chnum)->HCCHAR;
00918       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
00919       tmpreg |= USB_OTG_HCCHAR_CHENA;
00920       USBx_HC(chnum)->HCCHAR = tmpreg;
00921     }
00922     hhcd->hc[chnum].state = HC_NAK;
00923      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00924   }
00925 }
00926
00927 /**
00928   * @brief  This function handles Host Channel OUT interrupt requests.
00929   * @param  hhcd: HCD handle
00930   * @param  chnum: Channel number.
00931   *         This parameter can be a value from 1 to 15
00932   * @retval none
00933   */
00934 static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
00935 {
00936   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
00937   uint32_t tmpreg = 0U;
00938
00939   if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_AHBERR)
00940   {
00941     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
00942     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00943   }
00944   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_ACK)
00945   {
00946     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
00947
00948     if( hhcd->hc[chnum].do_ping == 1U)
00949     {
00950       hhcd->hc[chnum].state = HC_NYET;
00951       __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00952       USB_HC_Halt(hhcd->Instance, chnum);
00953       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
00954     }
00955   }
00956
00957   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NYET)
00958   {
00959     hhcd->hc[chnum].state = HC_NYET;
00960     hhcd->hc[chnum].ErrCnt= 0U;
00961     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00962     USB_HC_Halt(hhcd->Instance, chnum);
00963     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
00964
00965   }
00966
00967   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_FRMOR)
00968   {
00969     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00970     USB_HC_Halt(hhcd->Instance, chnum);
00971     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
00972   }
00973
00974   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_XFRC)
00975   {
00976     hhcd->hc[chnum].ErrCnt = 0U;
00977     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00978     USB_HC_Halt(hhcd->Instance, chnum);
00979     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
00980     hhcd->hc[chnum].state = HC_XFRC;
00981   }
00982   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_STALL)
00983   {
00984     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
00985     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00986     USB_HC_Halt(hhcd->Instance, chnum);
00987     hhcd->hc[chnum].state = HC_STALL;
00988   }
00989   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_NAK)
00990   {
00991     hhcd->hc[chnum].ErrCnt = 0U;
00992     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
00993     USB_HC_Halt(hhcd->Instance, chnum);
00994     hhcd->hc[chnum].state = HC_NAK;
00995     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
00996   }
00997   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_TXERR)
00998   {
00999     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01000     USB_HC_Halt(hhcd->Instance, chnum);
01001     hhcd->hc[chnum].state = HC_XACTERR;
01002      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
01003   }
01004   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_DTERR)
01005   {
01006     __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
01007     USB_HC_Halt(hhcd->Instance, chnum);
01008     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
01009     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
01010     hhcd->hc[chnum].state = HC_DATATGLERR;
01011   }
01012   else if ((USBx_HC(chnum)->HCINT) &  USB_OTG_HCINT_CHH)
01013   {
01014     __HAL_HCD_MASK_HALT_HC_INT(chnum);
01015
01016     if(hhcd->hc[chnum].state == HC_XFRC)
01017     {
01018       hhcd->hc[chnum].urb_state  = URB_DONE;
01019       if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
01020       {
01021         hhcd->hc[chnum].toggle_out ^= 1U;
01022       }
01023     }
01024     else if (hhcd->hc[chnum].state == HC_NAK)
01025     {
01026       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
01027     }
01028     else if (hhcd->hc[chnum].state == HC_NYET)
01029     {
01030       hhcd->hc[chnum].urb_state  = URB_NOTREADY;
01031       hhcd->hc[chnum].do_ping = 0U;
01032     }
01033     else if (hhcd->hc[chnum].state == HC_STALL)
01034     {
01035       hhcd->hc[chnum].urb_state  = URB_STALL;
01036     }
01037     else if((hhcd->hc[chnum].state == HC_XACTERR) ||
01038             (hhcd->hc[chnum].state == HC_DATATGLERR))
01039     {
01040       if(hhcd->hc[chnum].ErrCnt++ > 3U)
01041       {
01042         hhcd->hc[chnum].ErrCnt = 0U;
01043         hhcd->hc[chnum].urb_state = URB_ERROR;
01044       }
01045       else
01046       {
01047         hhcd->hc[chnum].urb_state = URB_NOTREADY;
01048       }
01049
01050       /* re-activate the channel  */
01051       tmpreg = USBx_HC(chnum)->HCCHAR;
01052       tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01053       tmpreg |= USB_OTG_HCCHAR_CHENA;
01054       USBx_HC(chnum)->HCCHAR = tmpreg;
01055     }
01056
01057     __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
01058     HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
01059   }
01060 }
01061
01062 /**
01063   * @brief  This function handles Rx Queue Level interrupt requests.
01064   * @param  hhcd: HCD handle
01065   * @retval none
01066   */
01067 static void HCD_RXQLVL_IRQHandler  (HCD_HandleTypeDef *hhcd)
01068 {
01069   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01070   uint8_t                       channelnum =0U;
01071   uint32_t                      pktsts;
01072   uint32_t                      pktcnt;
01073   uint32_t                      temp = 0U;
01074   uint32_t tmpreg = 0U;
01075
01076   temp = hhcd->Instance->GRXSTSP;
01077   channelnum = temp &  USB_OTG_GRXSTSP_EPNUM;
01078   pktsts = (temp &  USB_OTG_GRXSTSP_PKTSTS) >> 17U;
01079   pktcnt = (temp &  USB_OTG_GRXSTSP_BCNT) >> 4U;
01080
01081   switch (pktsts)
01082   {
01083   case GRXSTS_PKTSTS_IN:
01084     /* Read the data into the host buffer. */
01085     if ((pktcnt > 0U) && (hhcd->hc[channelnum].xfer_buff != (void  *)0U))
01086     {
01087       USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
01088
01089       /*manage multiple Xfer */
01090       hhcd->hc[channelnum].xfer_buff += pktcnt;
01091       hhcd->hc[channelnum].xfer_count  += pktcnt;
01092
01093       if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
01094       {
01095         /* re-activate the channel when more packets are expected */
01096         tmpreg = USBx_HC(channelnum)->HCCHAR;
01097         tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
01098         tmpreg |= USB_OTG_HCCHAR_CHENA;
01099         USBx_HC(channelnum)->HCCHAR = tmpreg;
01100         hhcd->hc[channelnum].toggle_in ^= 1U;
01101       }
01102     }
01103     break;
01104
01105   case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
01106     break;
01107
01108   case GRXSTS_PKTSTS_IN_XFER_COMP:
01109   case GRXSTS_PKTSTS_CH_HALTED:
01110   default:
01111     break;
01112   }
01113 }
01114
01115 /**
01116   * @brief  This function handles Host Port interrupt requests.
01117   * @param  hhcd: HCD handle
01118   * @retval None
01119   */
01120 static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
01121 {
01122   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
01123   __IO uint32_t hprt0 = 0, hprt0_dup = 0U;
01124
01125   /* Handle Host Port Interrupts */
01126   hprt0 = USBx_HPRT0;
01127   hprt0_dup = USBx_HPRT0;
01128
01129   hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
01130                  USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
01131
01132   /* Check whether Port Connect Detected */
01133   if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
01134   {
01135     if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
01136     {
01137       USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01138       HAL_HCD_Connect_Callback(hhcd);
01139     }
01140     hprt0_dup  |= USB_OTG_HPRT_PCDET;
01141   }
01142
01143   /* Check whether Port Enable Changed */
01144   if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
01145   {
01146     hprt0_dup |= USB_OTG_HPRT_PENCHNG;
01147
01148     if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
01149     {
01150       if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17U))
01151       {
01152         USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
01153       }
01154       else
01155       {
01156         USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
01157       }
01158       HAL_HCD_Connect_Callback(hhcd);
01159     }
01160     else
01161     {
01162       /* Cleanup HPRT */
01163       USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
01164         USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
01165
01166       USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
01167     }
01168   }
01169
01170   /* Check For an over current */
01171   if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
01172   {
01173     hprt0_dup |= USB_OTG_HPRT_POCCHNG;
01174   }
01175
01176   /* Clear Port Interrupts */
01177   USBx_HPRT0 = hprt0_dup;
01178 }
01179
01180 /**
01181   * @}
01182   */
01183
01184 /**
01185   * @}
01186   */
01187
01188 #endif /* STM32F105xC || STM32F107xC */
01189
01190 #endif /* HAL_HCD_MODULE_ENABLED */
01191
01192 /**
01193   * @}
01194   */
01195
01196 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_hcd.h Source File

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stm32f1xx_hal_hcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_hcd.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of HCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_HCD_H
00040 #define __STM32F1xx_HAL_HCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F105xC) || defined(STM32F107xC)
00047
00048
00049 /* Includes ------------------------------------------------------------------*/
00050 #include "stm32f1xx_ll_usb.h"
00051
00052 /** @addtogroup STM32F1xx_HAL_Driver
00053   * @{
00054   */
00055
00056 /** @addtogroup HCD
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup HCD_Exported_Types HCD Exported Types
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  HCD Status structure definition
00067   */
00068 typedef enum
00069 {
00070   HAL_HCD_STATE_RESET    = 0x00U,
00071   HAL_HCD_STATE_READY    = 0x01U,
00072   HAL_HCD_STATE_ERROR    = 0x02U,
00073   HAL_HCD_STATE_BUSY     = 0x03U,
00074   HAL_HCD_STATE_TIMEOUT  = 0x04U
00075 } HCD_StateTypeDef;
00076
00077 typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;
00078 typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;
00079 typedef USB_OTG_HCTypeDef       HCD_HCTypeDef;
00080 typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
00081 typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef;
00082
00083 /**
00084   * @brief  HCD Handle Structure definition
00085   */
00086 typedef struct
00087 {
00088   HCD_TypeDef               *Instance;  /*!< Register base address    */
00089   HCD_InitTypeDef           Init;       /*!< HCD required parameters  */
00090   HCD_HCTypeDef             hc[15U];     /*!< Host channels parameters */
00091   HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */
00092   __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */
00093   void                      *pData;     /*!< Pointer Stack Handler    */
00094 } HCD_HandleTypeDef;
00095
00096 /**
00097   * @}
00098   */
00099
00100 /* Exported constants --------------------------------------------------------*/
00101 /** @defgroup HCD_Exported_Constants HCD Exported Constants
00102   * @{
00103   */
00104 /** @defgroup HCD_Speed HCD Speed
00105   * @{
00106   */
00107 #define HCD_SPEED_LOW                2U
00108 #define HCD_SPEED_FULL               3U
00109
00110 /**
00111   * @}
00112   */
00113
00114 /**
00115   * @}
00116   */
00117
00118 /* Exported macro ------------------------------------------------------------*/
00119 /** @defgroup HCD_Exported_Macros HCD Exported Macros
00120  *  @brief macros to handle interrupts and specific clock configurations
00121  * @{
00122  */
00123 #define __HAL_HCD_ENABLE(__HANDLE__)                       USB_EnableGlobalInt ((__HANDLE__)->Instance)
00124 #define __HAL_HCD_DISABLE(__HANDLE__)                      USB_DisableGlobalInt ((__HANDLE__)->Instance)
00125
00126
00127 #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00128 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
00129 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
00130
00131
00132 #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)       (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
00133 #define __HAL_HCD_MASK_HALT_HC_INT(chnum)                  (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
00134 #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)                (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
00135 #define __HAL_HCD_MASK_ACK_HC_INT(chnum)                   (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
00136 #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)                 (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
00137
00138 /**
00139   * @}
00140   */
00141
00142 /* Exported functions --------------------------------------------------------*/
00143 /** @addtogroup HCD_Exported_Functions HCD Exported Functions
00144   * @{
00145   */
00146
00147 /* Initialization/de-initialization functions  ********************************/
00148 /** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
00149   * @{
00150   */
00151 HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
00152 HAL_StatusTypeDef      HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
00153 HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
00154                                        uint8_t ch_num,
00155                                        uint8_t epnum,
00156                                        uint8_t dev_address,
00157                                        uint8_t speed,
00158                                        uint8_t ep_type,
00159                                        uint16_t mps);
00160
00161 HAL_StatusTypeDef      HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
00162                                        uint8_t ch_num);
00163
00164 void                   HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
00165 void                   HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
00166 /**
00167   * @}
00168   */
00169
00170 /* I/O operation functions  ***************************************************/
00171 /** @addtogroup HCD_Exported_Functions_Group2 IO operation functions
00172   * @{
00173   */
00174 HAL_StatusTypeDef      HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
00175                                                 uint8_t pipe,
00176                                                 uint8_t direction,
00177                                                 uint8_t ep_type,
00178                                                 uint8_t token,
00179                                                 uint8_t* pbuff,
00180                                                 uint16_t length,
00181                                                 uint8_t do_ping);
00182
00183  /* Non-Blocking mode: Interrupt */
00184 void                   HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
00185 void                   HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
00186 void                   HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
00187 void                   HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
00188 void                   HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
00189                                                            uint8_t chnum,
00190                                                            HCD_URBStateTypeDef urb_state);
00191 /**
00192   * @}
00193   */
00194 /* Peripheral Control functions  **********************************************/
00195 /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
00196   * @{
00197   */
00198 HAL_StatusTypeDef      HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
00199 HAL_StatusTypeDef      HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
00200 HAL_StatusTypeDef      HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
00201 /**
00202   * @}
00203   */
00204 /* Peripheral State functions  ************************************************/
00205 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
00206   * @{
00207   */
00208 HCD_StateTypeDef       HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
00209 HCD_URBStateTypeDef    HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00210 uint32_t               HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00211 HCD_HCStateTypeDef     HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
00212 uint32_t               HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
00213 uint32_t               HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
00214 /**
00215   * @}
00216   */
00217
00218 /**
00219   * @}
00220   */
00221
00222 /* Private macros ------------------------------------------------------------*/
00223 /** @defgroup HCD_Private_Macros HCD Private Macros
00224  * @{
00225  */
00226 /** @defgroup HCD_Instance_definition HCD Instance definition
00227   * @{
00228   */
00229  #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
00230 /**
00231   * @}
00232   */
00233 /**
00234   * @}
00235   */
00236
00237 /**
00238   * @}
00239   */
00240
00241 /**
00242   * @}
00243   */
00244
00245 #endif /* STM32F105xC || STM32F107xC */
00246
00247
00248 #ifdef __cplusplus
00249 }
00250 #endif
00251
00252 #endif /* __STM32F1xx_HAL_HCD_H */
00253
00254 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_i2c.c Source File

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stm32f1xx_hal_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   I2C HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State, Mode and Error functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     The I2C HAL driver can be used as follows:
00020
00021     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00022         I2C_HandleTypeDef  hi2c;
00023
00024     (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
00025         (##) Enable the I2Cx interface clock
00026         (##) I2C pins configuration
00027             (+++) Enable the clock for the I2C GPIOs
00028             (+++) Configure I2C pins as alternate function open-drain
00029         (##) NVIC configuration if you need to use interrupt process
00030             (+++) Configure the I2Cx interrupt priority
00031             (+++) Enable the NVIC I2C IRQ Channel
00032         (##) DMA Configuration if you need to use DMA process
00033             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
00034             (+++) Enable the DMAx interface clock using
00035             (+++) Configure the DMA handle parameters
00036             (+++) Configure the DMA Tx or Rx channel
00037             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00039                   the DMA Tx or Rx channel
00040
00041     (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
00042         Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
00043
00044     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
00045         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
00046
00047     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
00048
00049     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00050
00051     *** Polling mode IO operation ***
00052     =================================
00053     [..]
00054       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
00055       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
00056       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
00057       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
00058
00059     *** Polling mode IO MEM operation ***
00060     =====================================
00061     [..]
00062       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
00063       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
00064
00065
00066     *** Interrupt mode IO operation ***
00067     ===================================
00068     [..]
00069       (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
00070       (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
00071            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
00072       (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
00073       (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
00074            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
00075       (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
00076       (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
00077            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
00078       (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
00079       (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
00080            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
00081       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00082            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00083       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00084       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00085            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00086
00087     *** Interrupt mode IO sequential operation ***
00088     ==============================================
00089     [..]
00090       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
00091           when a direction change during transfer
00092     [..]
00093       (+) A specific option field manage the different steps of a sequential transfer
00094       (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
00095       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
00096       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
00097                             and data to transfer without a final stop condition
00098       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
00099                             and with new data to transfer if the direction change or manage only the new data to transfer
00100                             if no direction change and without a final stop condition in both cases
00101       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
00102                             and with new data to transfer if the direction change or manage only the new data to transfer
00103                             if no direction change and with a final stop condition in both cases
00104
00105       (+) Differents sequential I2C interfaces are listed below:
00106       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
00107       (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00108            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00109       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
00110       (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00111            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00112       (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00113       (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00114            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00115       (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
00116       (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
00117            add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
00118       (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
00119            add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
00120       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
00121       (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00122            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00123       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
00124       (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00125            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00126       (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00127            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00128
00129     *** Interrupt mode IO MEM operation ***
00130     =======================================
00131     [..]
00132       (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
00133           HAL_I2C_Mem_Write_IT()
00134       (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
00135            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
00136       (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
00137           HAL_I2C_Mem_Read_IT()
00138       (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
00139            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
00140       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00141            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00142
00143     *** DMA mode IO operation ***
00144     ==============================
00145     [..]
00146       (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
00147           HAL_I2C_Master_Transmit_DMA()
00148       (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
00149            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
00150       (+) Receive in master mode an amount of data in non blocking mode (DMA) using
00151           HAL_I2C_Master_Receive_DMA()
00152       (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
00153            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
00154       (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
00155           HAL_I2C_Slave_Transmit_DMA()
00156       (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
00157            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
00158       (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
00159           HAL_I2C_Slave_Receive_DMA()
00160       (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
00161            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
00162       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00163            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00164       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00165       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00166            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00167
00168     *** DMA mode IO MEM operation ***
00169     =================================
00170     [..]
00171       (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
00172           HAL_I2C_Mem_Write_DMA()
00173       (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
00174            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
00175       (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
00176           HAL_I2C_Mem_Read_DMA()
00177       (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
00178            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
00179       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00180            add his own code by customization of function pointer HAL_I2C_ErrorCallback
00181
00182
00183      *** I2C HAL driver macros list ***
00184      ==================================
00185      [..]
00186        Below the list of most used macros in I2C HAL driver.
00187
00188       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
00189       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
00190       (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
00191       (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
00192       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00193       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00194
00195      [..]
00196        (@) You can refer to the I2C HAL driver header file for more useful macros
00197
00198      *** I2C Workarounds linked to Silicon Limitation ***
00199      ====================================================
00200      [..]
00201        Below the list of all silicon limitations implemented for HAL on STM32F1xx product.
00202        (@) See ErrataSheet to know full silicon limitation list of your product.
00203
00204        (#) Workarounds Implemented inside I2C HAL Driver
00205           (##) Wrong data read into data register (Polling and Interrupt mode)
00206           (##) Start cannot be generated after a misplaced Stop
00207           (##) Some software events must be managed before the current byte is being transferred:
00208                Workaround: Use DMA in general, except when the Master is receiving a single byte.
00209                For Interupt mode, I2C should have the highest priority in the application.
00210           (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter:
00211                Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if
00212                supported by the slave.
00213           (##) Data valid time (tVD;DAT) violated without the OVR flag being set:
00214                Workaround: If the slave device allows it, use the clock stretching mechanism
00215                by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in HAL_I2C_Init.
00216
00217   @endverbatim
00218   ******************************************************************************
00219   * @attention
00220   *
00221   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00222   *
00223   * Redistribution and use in source and binary forms, with or without modification,
00224   * are permitted provided that the following conditions are met:
00225   *   1. Redistributions of source code must retain the above copyright notice,
00226   *      this list of conditions and the following disclaimer.
00227   *   2. Redistributions in binary form must reproduce the above copyright notice,
00228   *      this list of conditions and the following disclaimer in the documentation
00229   *      and/or other materials provided with the distribution.
00230   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00231   *      may be used to endorse or promote products derived from this software
00232   *      without specific prior written permission.
00233   *
00234   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00235   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00236   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00237   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00238   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00239   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00240   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00241   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00242   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00243   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00244   *
00245   ******************************************************************************
00246   */
00247
00248 /* Includes ------------------------------------------------------------------*/
00249 #include "stm32f1xx_hal.h"
00250
00251 /** @addtogroup STM32F1xx_HAL_Driver
00252   * @{
00253   */
00254
00255 /** @defgroup I2C I2C
00256   * @brief I2C HAL module driver
00257   * @{
00258   */
00259
00260 #ifdef HAL_I2C_MODULE_ENABLED
00261
00262 /* Private typedef -----------------------------------------------------------*/
00263 /* Private define ------------------------------------------------------------*/
00264 /** @addtogroup I2C_Private_Define
00265   * @{
00266   */
00267 #define I2C_TIMEOUT_FLAG          35U         /*!< Timeout 35 ms             */
00268 #define I2C_TIMEOUT_BUSY_FLAG     25U         /*!< Timeout 25 ms             */
00269 #define I2C_NO_OPTION_FRAME       0xFFFF0000U /*!< XferOptions default value */
00270
00271 /* Private define for @ref PreviousState usage */
00272 #define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits            */
00273 #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
00274 #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00275 #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00276 #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
00277 #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00278
00279 /**
00280   * @}
00281   */
00282
00283 /* Private macro -------------------------------------------------------------*/
00284 /* Private variables ---------------------------------------------------------*/
00285 /* Private function prototypes -----------------------------------------------*/
00286 /** @addtogroup I2C_Private_Functions
00287   * @{
00288   */
00289 /* Private functions to handle DMA transfer */
00290 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
00291 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00292 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
00293
00294 static void I2C_ITError(I2C_HandleTypeDef *hi2c);
00295
00296 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
00297 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
00298 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00299 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00300 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
00301 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
00302 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00303 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00304 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00305 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00306 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
00307
00308 /* Private functions for I2C transfer IRQ handler */
00309 static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
00310 static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
00311 static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
00312 static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
00313 static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
00314 static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
00315 static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
00316
00317 static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
00318 static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
00319 static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
00320 static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
00321 static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
00322 static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
00323 static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
00324 /**
00325   * @}
00326   */
00327
00328 /* Exported functions --------------------------------------------------------*/
00329 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00330   * @{
00331   */
00332
00333 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00334  *  @brief    Initialization and Configuration functions
00335  *
00336 @verbatim
00337  ===============================================================================
00338               ##### Initialization and de-initialization functions #####
00339  ===============================================================================
00340     [..]  This subsection provides a set of functions allowing to initialize and
00341           de-initialize the I2Cx peripheral:
00342
00343       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00344           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
00345
00346       (+) Call the function HAL_I2C_Init() to configure the selected device with
00347           the selected configuration:
00348         (++) Communication Speed
00349         (++) Duty cycle
00350         (++) Addressing mode
00351         (++) Own Address 1
00352         (++) Dual Addressing mode
00353         (++) Own Address 2
00354         (++) General call mode
00355         (++) Nostretch mode
00356
00357       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00358           of the selected I2Cx peripheral.
00359
00360 @endverbatim
00361   * @{
00362   */
00363
00364 /**
00365   * @brief  Initializes the I2C according to the specified parameters
00366   *         in the I2C_InitTypeDef and create the associated handle.
00367   * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
00368   *         the configuration information for I2C module
00369   * @retval HAL status
00370   */
00371 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00372 {
00373   uint32_t freqrange = 0U;
00374   uint32_t pclk1 = 0U;
00375
00376   /* Check the I2C handle allocation */
00377   if(hi2c == NULL)
00378   {
00379     return HAL_ERROR;
00380   }
00381
00382   /* Check the parameters */
00383   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00384   assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
00385   assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
00386   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00387   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00388   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00389   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00390   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00391   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00392
00393   if(hi2c->State == HAL_I2C_STATE_RESET)
00394   {
00395     /* Allocate lock resource and initialize it */
00396     hi2c->Lock = HAL_UNLOCKED;
00397     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00398     HAL_I2C_MspInit(hi2c);
00399   }
00400
00401   hi2c->State = HAL_I2C_STATE_BUSY;
00402
00403   /* Disable the selected I2C peripheral */
00404   __HAL_I2C_DISABLE(hi2c);
00405
00406   /* Get PCLK1 frequency */
00407   pclk1 = HAL_RCC_GetPCLK1Freq();
00408
00409   /* Calculate frequency range */
00410   freqrange = I2C_FREQRANGE(pclk1);
00411
00412   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00413   /* Configure I2Cx: Frequency range */
00414   hi2c->Instance->CR2 = freqrange;
00415
00416   /*---------------------------- I2Cx TRISE Configuration --------------------*/
00417   /* Configure I2Cx: Rise Time */
00418   hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
00419
00420   /*---------------------------- I2Cx CCR Configuration ----------------------*/
00421   /* Configure I2Cx: Speed */
00422   hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
00423
00424   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00425   /* Configure I2Cx: Generalcall and NoStretch mode */
00426   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00427
00428   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00429   /* Configure I2Cx: Own Address1 and addressing mode */
00430   hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1);
00431
00432   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00433   /* Configure I2Cx: Dual mode and Own Address2 */
00434   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2);
00435
00436   /* Enable the selected I2C peripheral */
00437   __HAL_I2C_ENABLE(hi2c);
00438
00439   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00440   hi2c->State = HAL_I2C_STATE_READY;
00441   hi2c->PreviousState = I2C_STATE_NONE;
00442   hi2c->Mode = HAL_I2C_MODE_NONE;
00443
00444   return HAL_OK;
00445 }
00446
00447 /**
00448   * @brief  DeInitializes the I2C peripheral.
00449   * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
00450   *         the configuration information for I2C module
00451   * @retval HAL status
00452   */
00453 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00454 {
00455   /* Check the I2C handle allocation */
00456   if(hi2c == NULL)
00457   {
00458     return HAL_ERROR;
00459   }
00460
00461   /* Check the parameters */
00462   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00463
00464   hi2c->State = HAL_I2C_STATE_BUSY;
00465
00466   /* Disable the I2C Peripheral Clock */
00467   __HAL_I2C_DISABLE(hi2c);
00468
00469   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00470   HAL_I2C_MspDeInit(hi2c);
00471
00472   hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;
00473   hi2c->State         = HAL_I2C_STATE_RESET;
00474   hi2c->PreviousState = I2C_STATE_NONE;
00475   hi2c->Mode          = HAL_I2C_MODE_NONE;
00476
00477   /* Release Lock */
00478   __HAL_UNLOCK(hi2c);
00479
00480   return HAL_OK;
00481 }
00482
00483 /**
00484   * @brief I2C MSP Init.
00485   * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
00486   *         the configuration information for I2C module
00487   * @retval None
00488   */
00489  __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00490 {
00491   /* Prevent unused argument(s) compilation warning */
00492   UNUSED(hi2c);
00493   /* NOTE : This function Should not be modified, when the callback is needed,
00494             the HAL_I2C_MspInit could be implemented in the user file
00495    */
00496 }
00497
00498 /**
00499   * @brief I2C MSP DeInit
00500   * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
00501   *         the configuration information for I2C module
00502   * @retval None
00503   */
00504  __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00505 {
00506   /* Prevent unused argument(s) compilation warning */
00507   UNUSED(hi2c);
00508   /* NOTE : This function Should not be modified, when the callback is needed,
00509             the HAL_I2C_MspDeInit could be implemented in the user file
00510    */
00511 }
00512
00513 /**
00514   * @}
00515   */
00516
00517 /** @defgroup I2C_Exported_Functions_Group2 IO operation functions
00518  *  @brief   Data transfers functions
00519  *
00520 @verbatim
00521  ===============================================================================
00522                       ##### IO operation functions #####
00523  ===============================================================================
00524     [..]
00525     This subsection provides a set of functions allowing to manage the I2C data
00526     transfers.
00527
00528     (#) There are two modes of transfer:
00529        (++) Blocking mode : The communication is performed in the polling mode.
00530             The status of all data processing is returned by the same function
00531             after finishing transfer.
00532        (++) No-Blocking mode : The communication is performed using Interrupts
00533             or DMA. These functions return the status of the transfer startup.
00534             The end of the data processing will be indicated through the
00535             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
00536             using DMA mode.
00537
00538     (#) Blocking mode functions are :
00539         (++) HAL_I2C_Master_Transmit()
00540         (++) HAL_I2C_Master_Receive()
00541         (++) HAL_I2C_Slave_Transmit()
00542         (++) HAL_I2C_Slave_Receive()
00543         (++) HAL_I2C_Mem_Write()
00544         (++) HAL_I2C_Mem_Read()
00545         (++) HAL_I2C_IsDeviceReady()
00546
00547     (#) No-Blocking mode functions with Interrupt are :
00548         (++) HAL_I2C_Master_Transmit_IT()
00549         (++) HAL_I2C_Master_Receive_IT()
00550         (++) HAL_I2C_Slave_Transmit_IT()
00551         (++) HAL_I2C_Slave_Receive_IT()
00552         (++) HAL_I2C_Master_Sequential_Transmit_IT()
00553         (++) HAL_I2C_Master_Sequential_Receive_IT()
00554         (++) HAL_I2C_Slave_Sequential_Transmit_IT()
00555         (++) HAL_I2C_Slave_Sequential_Receive_IT()
00556         (++) HAL_I2C_Mem_Write_IT()
00557         (++) HAL_I2C_Mem_Read_IT()
00558
00559     (#) No-Blocking mode functions with DMA are :
00560         (++) HAL_I2C_Master_Transmit_DMA()
00561         (++) HAL_I2C_Master_Receive_DMA()
00562         (++) HAL_I2C_Slave_Transmit_DMA()
00563         (++) HAL_I2C_Slave_Receive_DMA()
00564         (++) HAL_I2C_Mem_Write_DMA()
00565         (++) HAL_I2C_Mem_Read_DMA()
00566
00567     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00568         (++) HAL_I2C_MemTxCpltCallback()
00569         (++) HAL_I2C_MemRxCpltCallback()
00570         (++) HAL_I2C_MasterTxCpltCallback()
00571         (++) HAL_I2C_MasterRxCpltCallback()
00572         (++) HAL_I2C_SlaveTxCpltCallback()
00573         (++) HAL_I2C_SlaveRxCpltCallback()
00574         (++) HAL_I2C_ErrorCallback()
00575         (++) HAL_I2C_AbortCpltCallback()
00576
00577 @endverbatim
00578   * @{
00579   */
00580
00581 /**
00582   * @brief  Transmits in master mode an amount of data in blocking mode.
00583   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00584   *                the configuration information for the specified I2C.
00585   * @param  DevAddress Target device address: The device 7 bits address value
00586   *         in datasheet must be shift at right before call interface
00587   * @param  pData Pointer to data buffer
00588   * @param  Size Amount of data to be sent
00589   * @param  Timeout Timeout duration
00590   * @retval HAL status
00591   */
00592 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00593 {
00594   uint32_t tickstart = 0x00U;
00595
00596   /* Init tickstart for timeout management*/
00597   tickstart = HAL_GetTick();
00598
00599   if(hi2c->State == HAL_I2C_STATE_READY)
00600   {
00601     /* Wait until BUSY flag is reset */
00602     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
00603     {
00604       return HAL_BUSY;
00605     }
00606
00607     /* Process Locked */
00608     __HAL_LOCK(hi2c);
00609
00610     /* Check if the I2C is already enabled */
00611     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
00612     {
00613       /* Enable I2C peripheral */
00614       __HAL_I2C_ENABLE(hi2c);
00615     }
00616
00617     /* Disable Pos */
00618     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
00619
00620     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
00621     hi2c->Mode      = HAL_I2C_MODE_MASTER;
00622     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00623
00624     /* Prepare transfer parameters */
00625     hi2c->pBuffPtr    = pData;
00626     hi2c->XferCount   = Size;
00627     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
00628     hi2c->XferSize    = hi2c->XferCount;
00629
00630     /* Send Slave Address */
00631     if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
00632     {
00633       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00634       {
00635         /* Process Unlocked */
00636         __HAL_UNLOCK(hi2c);
00637         return HAL_ERROR;
00638       }
00639       else
00640       {
00641         /* Process Unlocked */
00642         __HAL_UNLOCK(hi2c);
00643         return HAL_TIMEOUT;
00644       }
00645     }
00646
00647     /* Clear ADDR flag */
00648     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00649
00650     while(hi2c->XferSize > 0U)
00651     {
00652       /* Wait until TXE flag is set */
00653       if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00654       {
00655         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00656         {
00657           /* Generate Stop */
00658           hi2c->Instance->CR1 |= I2C_CR1_STOP;
00659           return HAL_ERROR;
00660         }
00661         else
00662         {
00663           return HAL_TIMEOUT;
00664         }
00665       }
00666
00667       /* Write data to DR */
00668       hi2c->Instance->DR = (*hi2c->pBuffPtr++);
00669       hi2c->XferCount--;
00670       hi2c->XferSize--;
00671
00672       if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
00673       {
00674         /* Write data to DR */
00675         hi2c->Instance->DR = (*hi2c->pBuffPtr++);
00676         hi2c->XferCount--;
00677         hi2c->XferSize--;
00678       }
00679
00680       /* Wait until BTF flag is set */
00681       if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00682       {
00683         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00684         {
00685           /* Generate Stop */
00686           hi2c->Instance->CR1 |= I2C_CR1_STOP;
00687           return HAL_ERROR;
00688         }
00689         else
00690         {
00691           return HAL_TIMEOUT;
00692         }
00693       }
00694     }
00695
00696     /* Generate Stop */
00697     hi2c->Instance->CR1 |= I2C_CR1_STOP;
00698
00699     hi2c->State = HAL_I2C_STATE_READY;
00700     hi2c->Mode = HAL_I2C_MODE_NONE;
00701
00702     /* Process Unlocked */
00703     __HAL_UNLOCK(hi2c);
00704
00705     return HAL_OK;
00706   }
00707   else
00708   {
00709     return HAL_BUSY;
00710   }
00711 }
00712
00713 /**
00714   * @brief  Receives in master mode an amount of data in blocking mode.
00715   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00716   *                the configuration information for the specified I2C.
00717   * @param  DevAddress Target device address: The device 7 bits address value
00718   *         in datasheet must be shift at right before call interface
00719   * @param  pData Pointer to data buffer
00720   * @param  Size Amount of data to be sent
00721   * @param  Timeout Timeout duration
00722   * @retval HAL status
00723   */
00724 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00725 {
00726   uint32_t tickstart = 0x00U;
00727
00728   /* Init tickstart for timeout management*/
00729   tickstart = HAL_GetTick();
00730
00731   if(hi2c->State == HAL_I2C_STATE_READY)
00732   {
00733     /* Wait until BUSY flag is reset */
00734     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
00735     {
00736       return HAL_BUSY;
00737     }
00738
00739     /* Process Locked */
00740     __HAL_LOCK(hi2c);
00741
00742     /* Check if the I2C is already enabled */
00743     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
00744     {
00745       /* Enable I2C peripheral */
00746       __HAL_I2C_ENABLE(hi2c);
00747     }
00748
00749     /* Disable Pos */
00750     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
00751
00752     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
00753     hi2c->Mode        = HAL_I2C_MODE_MASTER;
00754     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
00755
00756     /* Prepare transfer parameters */
00757     hi2c->pBuffPtr    = pData;
00758     hi2c->XferCount   = Size;
00759     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
00760     hi2c->XferSize    = hi2c->XferCount;
00761
00762     /* Send Slave Address */
00763     if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
00764     {
00765       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00766       {
00767         /* Process Unlocked */
00768         __HAL_UNLOCK(hi2c);
00769         return HAL_ERROR;
00770       }
00771       else
00772       {
00773         /* Process Unlocked */
00774         __HAL_UNLOCK(hi2c);
00775         return HAL_TIMEOUT;
00776       }
00777     }
00778
00779     if(hi2c->XferSize == 0U)
00780     {
00781       /* Clear ADDR flag */
00782       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00783
00784       /* Generate Stop */
00785       hi2c->Instance->CR1 |= I2C_CR1_STOP;
00786     }
00787     else if(hi2c->XferSize == 1U)
00788     {
00789       /* Disable Acknowledge */
00790       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
00791
00792       /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
00793       software sequence must complete before the current byte end of transfer */
00794       __disable_irq();
00795
00796       /* Clear ADDR flag */
00797       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00798
00799       /* Generate Stop */
00800       hi2c->Instance->CR1 |= I2C_CR1_STOP;
00801
00802       /* Re-enable IRQs */
00803       __enable_irq();
00804     }
00805     else if(hi2c->XferSize == 2U)
00806     {
00807       /* Enable Pos */
00808       hi2c->Instance->CR1 |= I2C_CR1_POS;
00809
00810       /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
00811       software sequence must complete before the current byte end of transfer */
00812       __disable_irq();
00813
00814       /* Clear ADDR flag */
00815       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00816
00817       /* Disable Acknowledge */
00818       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
00819
00820       /* Re-enable IRQs */
00821       __enable_irq();
00822     }
00823     else
00824     {
00825       /* Enable Acknowledge */
00826       hi2c->Instance->CR1 |= I2C_CR1_ACK;
00827
00828       /* Clear ADDR flag */
00829       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
00830     }
00831
00832     while(hi2c->XferSize > 0U)
00833     {
00834       if(hi2c->XferSize <= 3U)
00835       {
00836         /* One byte */
00837         if(hi2c->XferSize == 1U)
00838         {
00839           /* Wait until RXNE flag is set */
00840           if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00841           {
00842             if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
00843             {
00844               return HAL_TIMEOUT;
00845             }
00846             else
00847             {
00848               return HAL_ERROR;
00849             }
00850           }
00851
00852           /* Read data from DR */
00853           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
00854           hi2c->XferSize--;
00855           hi2c->XferCount--;
00856         }
00857         /* Two bytes */
00858         else if(hi2c->XferSize == 2U)
00859         {
00860           /* Wait until BTF flag is set */
00861           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
00862           {
00863             return HAL_TIMEOUT;
00864           }
00865
00866           /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
00867              software sequence must complete before the current byte end of transfer */
00868            __disable_irq();
00869
00870           /* Generate Stop */
00871           hi2c->Instance->CR1 |= I2C_CR1_STOP;
00872
00873           /* Read data from DR */
00874           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
00875           hi2c->XferSize--;
00876           hi2c->XferCount--;
00877
00878           /* Re-enable IRQs */
00879           __enable_irq();
00880
00881           /* Read data from DR */
00882           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
00883           hi2c->XferSize--;
00884           hi2c->XferCount--;
00885         }
00886         /* 3 Last bytes */
00887         else
00888         {
00889           /* Wait until BTF flag is set */
00890           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
00891           {
00892             return HAL_TIMEOUT;
00893           }
00894
00895           /* Disable Acknowledge */
00896           hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
00897
00898           /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
00899              software sequence must complete before the current byte end of transfer */
00900           __disable_irq();
00901
00902           /* Read data from DR */
00903           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
00904           hi2c->XferSize--;
00905           hi2c->XferCount--;
00906
00907           /* Wait until BTF flag is set */
00908           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
00909           {
00910             return HAL_TIMEOUT;
00911           }
00912
00913           /* Generate Stop */
00914           hi2c->Instance->CR1 |= I2C_CR1_STOP;
00915
00916           /* Read data from DR */
00917           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
00918           hi2c->XferSize--;
00919           hi2c->XferCount--;
00920
00921           /* Re-enable IRQs */
00922           __enable_irq();
00923
00924           /* Read data from DR */
00925           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
00926           hi2c->XferSize--;
00927           hi2c->XferCount--;
00928         }
00929       }
00930       else
00931       {
00932         /* Wait until RXNE flag is set */
00933         if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00934         {
00935           if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
00936           {
00937             return HAL_TIMEOUT;
00938           }
00939           else
00940           {
00941             return HAL_ERROR;
00942           }
00943         }
00944
00945         /* Read data from DR */
00946         (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
00947         hi2c->XferSize--;
00948         hi2c->XferCount--;
00949
00950         if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
00951         {
00952           /* Read data from DR */
00953           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
00954           hi2c->XferSize--;
00955           hi2c->XferCount--;
00956         }
00957       }
00958     }
00959
00960     hi2c->State = HAL_I2C_STATE_READY;
00961     hi2c->Mode = HAL_I2C_MODE_NONE;
00962
00963     /* Process Unlocked */
00964     __HAL_UNLOCK(hi2c);
00965
00966     return HAL_OK;
00967   }
00968   else
00969   {
00970     return HAL_BUSY;
00971   }
00972 }
00973
00974 /**
00975   * @brief  Transmits in slave mode an amount of data in blocking mode.
00976   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00977   *                the configuration information for the specified I2C.
00978   * @param  pData Pointer to data buffer
00979   * @param  Size Amount of data to be sent
00980   * @param  Timeout Timeout duration
00981   * @retval HAL status
00982   */
00983 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00984 {
00985   uint32_t tickstart = 0x00U;
00986
00987   /* Init tickstart for timeout management*/
00988   tickstart = HAL_GetTick();
00989
00990   if(hi2c->State == HAL_I2C_STATE_READY)
00991   {
00992     if((pData == NULL) || (Size == 0U))
00993     {
00994       return  HAL_ERROR;
00995     }
00996
00997     /* Process Locked */
00998     __HAL_LOCK(hi2c);
00999
01000     /* Check if the I2C is already enabled */
01001     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01002     {
01003       /* Enable I2C peripheral */
01004       __HAL_I2C_ENABLE(hi2c);
01005     }
01006
01007     /* Disable Pos */
01008     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01009
01010     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01011     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01012     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01013
01014     /* Prepare transfer parameters */
01015     hi2c->pBuffPtr    = pData;
01016     hi2c->XferCount   = Size;
01017     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01018     hi2c->XferSize    = hi2c->XferCount;
01019
01020     /* Enable Address Acknowledge */
01021     hi2c->Instance->CR1 |= I2C_CR1_ACK;
01022
01023     /* Wait until ADDR flag is set */
01024     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01025     {
01026       return HAL_TIMEOUT;
01027     }
01028
01029     /* Clear ADDR flag */
01030     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01031
01032     /* If 10bit addressing mode is selected */
01033     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
01034     {
01035       /* Wait until ADDR flag is set */
01036       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01037       {
01038         return HAL_TIMEOUT;
01039       }
01040
01041       /* Clear ADDR flag */
01042       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01043     }
01044
01045     while(hi2c->XferSize > 0U)
01046     {
01047       /* Wait until TXE flag is set */
01048       if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01049       {
01050         /* Disable Address Acknowledge */
01051         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01052
01053         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01054         {
01055           return HAL_ERROR;
01056         }
01057         else
01058         {
01059           return HAL_TIMEOUT;
01060         }
01061       }
01062
01063       /* Write data to DR */
01064       hi2c->Instance->DR = (*hi2c->pBuffPtr++);
01065       hi2c->XferCount--;
01066       hi2c->XferSize--;
01067
01068       if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
01069       {
01070         /* Write data to DR */
01071         hi2c->Instance->DR = (*hi2c->pBuffPtr++);
01072         hi2c->XferCount--;
01073         hi2c->XferSize--;
01074       }
01075     }
01076
01077     /* Wait until AF flag is set */
01078     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
01079     {
01080       return HAL_TIMEOUT;
01081     }
01082
01083     /* Clear AF flag */
01084     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
01085
01086     /* Disable Address Acknowledge */
01087     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01088
01089     hi2c->State = HAL_I2C_STATE_READY;
01090     hi2c->Mode = HAL_I2C_MODE_NONE;
01091
01092     /* Process Unlocked */
01093     __HAL_UNLOCK(hi2c);
01094
01095     return HAL_OK;
01096   }
01097   else
01098   {
01099     return HAL_BUSY;
01100   }
01101 }
01102
01103 /**
01104   * @brief  Receive in slave mode an amount of data in blocking mode
01105   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01106   *         the configuration information for the specified I2C.
01107   * @param  pData Pointer to data buffer
01108   * @param  Size Amount of data to be sent
01109   * @param  Timeout Timeout duration
01110   * @retval HAL status
01111   */
01112 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01113 {
01114   uint32_t tickstart = 0x00U;
01115
01116   /* Init tickstart for timeout management*/
01117   tickstart = HAL_GetTick();
01118
01119   if(hi2c->State == HAL_I2C_STATE_READY)
01120   {
01121     if((pData == NULL) || (Size == 0U))
01122     {
01123       return  HAL_ERROR;
01124     }
01125
01126     /* Process Locked */
01127     __HAL_LOCK(hi2c);
01128
01129     /* Check if the I2C is already enabled */
01130     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01131     {
01132       /* Enable I2C peripheral */
01133       __HAL_I2C_ENABLE(hi2c);
01134     }
01135
01136     /* Disable Pos */
01137     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01138
01139     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01140     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01141     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01142
01143     /* Prepare transfer parameters */
01144     hi2c->pBuffPtr    = pData;
01145     hi2c->XferCount   = Size;
01146     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01147     hi2c->XferSize    = hi2c->XferCount;
01148
01149     /* Enable Address Acknowledge */
01150     hi2c->Instance->CR1 |= I2C_CR1_ACK;
01151
01152     /* Wait until ADDR flag is set */
01153     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01154     {
01155       return HAL_TIMEOUT;
01156     }
01157
01158     /* Clear ADDR flag */
01159     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01160
01161     while(hi2c->XferSize > 0U)
01162     {
01163       /* Wait until RXNE flag is set */
01164       if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01165       {
01166         /* Disable Address Acknowledge */
01167         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01168
01169         if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
01170         {
01171           return HAL_TIMEOUT;
01172         }
01173         else
01174         {
01175           return HAL_ERROR;
01176         }
01177       }
01178
01179       /* Read data from DR */
01180       (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
01181       hi2c->XferSize--;
01182       hi2c->XferCount--;
01183
01184       if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
01185       {
01186         /* Read data from DR */
01187       (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
01188       hi2c->XferSize--;
01189       hi2c->XferCount--;
01190       }
01191     }
01192
01193     /* Wait until STOP flag is set */
01194     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01195     {
01196       /* Disable Address Acknowledge */
01197       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01198
01199       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01200       {
01201         return HAL_ERROR;
01202       }
01203       else
01204       {
01205         return HAL_TIMEOUT;
01206       }
01207     }
01208
01209     /* Clear STOP flag */
01210     __HAL_I2C_CLEAR_STOPFLAG(hi2c);
01211
01212     /* Disable Address Acknowledge */
01213     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01214
01215     hi2c->State = HAL_I2C_STATE_READY;
01216     hi2c->Mode = HAL_I2C_MODE_NONE;
01217
01218     /* Process Unlocked */
01219     __HAL_UNLOCK(hi2c);
01220
01221     return HAL_OK;
01222   }
01223   else
01224   {
01225     return HAL_BUSY;
01226   }
01227 }
01228
01229 /**
01230   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
01231   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01232   *                the configuration information for the specified I2C.
01233   * @param  DevAddress Target device address: The device 7 bits address value
01234   *         in datasheet must be shift at right before call interface
01235   * @param  pData Pointer to data buffer
01236   * @param  Size Amount of data to be sent
01237   * @retval HAL status
01238   */
01239 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01240 {
01241   __IO uint32_t count = 0U;
01242
01243   if(hi2c->State == HAL_I2C_STATE_READY)
01244   {
01245     /* Wait until BUSY flag is reset */
01246     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
01247     do
01248     {
01249       if(count-- == 0U)
01250       {
01251         hi2c->PreviousState = I2C_STATE_NONE;
01252         hi2c->State= HAL_I2C_STATE_READY;
01253
01254         /* Process Unlocked */
01255         __HAL_UNLOCK(hi2c);
01256
01257         return HAL_TIMEOUT;
01258       }
01259     }
01260     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
01261
01262     /* Process Locked */
01263     __HAL_LOCK(hi2c);
01264
01265     /* Check if the I2C is already enabled */
01266     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01267     {
01268       /* Enable I2C peripheral */
01269       __HAL_I2C_ENABLE(hi2c);
01270     }
01271
01272     /* Disable Pos */
01273     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01274
01275     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01276     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01277     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01278
01279     /* Prepare transfer parameters */
01280     hi2c->pBuffPtr    = pData;
01281     hi2c->XferCount   = Size;
01282     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01283     hi2c->XferSize    = hi2c->XferCount;
01284     hi2c->Devaddress  = DevAddress;
01285
01286     /* Generate Start */
01287     hi2c->Instance->CR1 |= I2C_CR1_START;
01288
01289     /* Process Unlocked */
01290     __HAL_UNLOCK(hi2c);
01291
01292     /* Note : The I2C interrupts must be enabled after unlocking current process
01293               to avoid the risk of I2C interrupt handle execution before current
01294               process unlock */
01295     /* Enable EVT, BUF and ERR interrupt */
01296     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01297
01298     return HAL_OK;
01299   }
01300   else
01301   {
01302     return HAL_BUSY;
01303   }
01304 }
01305
01306 /**
01307   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
01308   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01309   *                the configuration information for the specified I2C.
01310   * @param  DevAddress Target device address: The device 7 bits address value
01311   *         in datasheet must be shift at right before call interface
01312   * @param  pData Pointer to data buffer
01313   * @param  Size Amount of data to be sent
01314   * @retval HAL status
01315   */
01316 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01317 {
01318   __IO uint32_t count = 0U;
01319
01320   if(hi2c->State == HAL_I2C_STATE_READY)
01321   {
01322     /* Wait until BUSY flag is reset */
01323     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
01324     do
01325     {
01326       if(count-- == 0U)
01327       {
01328         hi2c->PreviousState = I2C_STATE_NONE;
01329         hi2c->State= HAL_I2C_STATE_READY;
01330
01331         /* Process Unlocked */
01332         __HAL_UNLOCK(hi2c);
01333
01334         return HAL_TIMEOUT;
01335       }
01336     }
01337     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
01338
01339     /* Process Locked */
01340     __HAL_LOCK(hi2c);
01341
01342     /* Check if the I2C is already enabled */
01343     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01344     {
01345       /* Enable I2C peripheral */
01346       __HAL_I2C_ENABLE(hi2c);
01347     }
01348
01349     /* Disable Pos */
01350     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01351
01352     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01353     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01354     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01355
01356     /* Prepare transfer parameters */
01357     hi2c->pBuffPtr    = pData;
01358     hi2c->XferCount   = Size;
01359     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01360     hi2c->XferSize    = hi2c->XferCount;
01361     hi2c->Devaddress  = DevAddress;
01362
01363     /* Enable Acknowledge */
01364     hi2c->Instance->CR1 |= I2C_CR1_ACK;
01365
01366     /* Generate Start */
01367     hi2c->Instance->CR1 |= I2C_CR1_START;
01368
01369     /* Process Unlocked */
01370     __HAL_UNLOCK(hi2c);
01371
01372     /* Note : The I2C interrupts must be enabled after unlocking current process
01373     to avoid the risk of I2C interrupt handle execution before current
01374     process unlock */
01375
01376     /* Enable EVT, BUF and ERR interrupt */
01377     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01378
01379     return HAL_OK;
01380   }
01381   else
01382   {
01383     return HAL_BUSY;
01384   }
01385 }
01386
01387 /**
01388   * @brief  Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
01389   * @note   This interface allow to manage repeated start condition when a direction change during transfer
01390   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01391   *         the configuration information for the specified I2C.
01392   * @param  DevAddress Target device address: The device 7 bits address value
01393   *         in datasheet must be shift at right before call interface
01394   * @param  pData Pointer to data buffer
01395   * @param  Size Amount of data to be sent
01396   * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
01397   * @retval HAL status
01398   */
01399 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01400 {
01401   __IO uint32_t Prev_State = 0x00U;
01402   __IO uint32_t count      = 0x00U;
01403
01404   /* Check the parameters */
01405   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
01406
01407   if(hi2c->State == HAL_I2C_STATE_READY)
01408   {
01409     /* Check Busy Flag only if FIRST call of Master interface */
01410     if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
01411     {
01412       /* Wait until BUSY flag is reset */
01413       count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
01414       do
01415       {
01416         if(count-- == 0U)
01417         {
01418           hi2c->PreviousState = I2C_STATE_NONE;
01419           hi2c->State= HAL_I2C_STATE_READY;
01420
01421           /* Process Unlocked */
01422           __HAL_UNLOCK(hi2c);
01423
01424           return HAL_TIMEOUT;
01425         }
01426       }
01427       while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
01428     }
01429
01430     /* Process Locked */
01431     __HAL_LOCK(hi2c);
01432
01433     /* Check if the I2C is already enabled */
01434     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01435     {
01436       /* Enable I2C peripheral */
01437       __HAL_I2C_ENABLE(hi2c);
01438     }
01439
01440     /* Disable Pos */
01441     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01442
01443     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01444     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01445     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01446
01447     /* Prepare transfer parameters */
01448     hi2c->pBuffPtr    = pData;
01449     hi2c->XferCount   = Size;
01450     hi2c->XferOptions = XferOptions;
01451     hi2c->XferSize    = hi2c->XferCount;
01452     hi2c->Devaddress  = DevAddress;
01453
01454     Prev_State = hi2c->PreviousState;
01455
01456     /* Generate Start */
01457     if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE))
01458     {
01459       /* Generate Start condition if first transfer */
01460       if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
01461       {
01462         /* Generate Start */
01463         hi2c->Instance->CR1 |= I2C_CR1_START;
01464       }
01465       else if(Prev_State == I2C_STATE_MASTER_BUSY_RX)
01466       {
01467         /* Generate ReStart */
01468         hi2c->Instance->CR1 |= I2C_CR1_START;
01469       }
01470     }
01471
01472     /* Process Unlocked */
01473     __HAL_UNLOCK(hi2c);
01474
01475     /* Note : The I2C interrupts must be enabled after unlocking current process
01476     to avoid the risk of I2C interrupt handle execution before current
01477     process unlock */
01478
01479     /* Enable EVT, BUF and ERR interrupt */
01480     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01481
01482     return HAL_OK;
01483   }
01484   else
01485   {
01486     return HAL_BUSY;
01487   }
01488 }
01489
01490 /**
01491   * @brief  Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
01492   * @note   This interface allow to manage repeated start condition when a direction change during transfer
01493   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01494   *         the configuration information for the specified I2C.
01495   * @param  DevAddress Target device address: The device 7 bits address value
01496   *         in datasheet must be shift at right before call interface
01497   * @param  pData Pointer to data buffer
01498   * @param  Size Amount of data to be sent
01499   * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
01500   * @retval HAL status
01501   */
01502 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01503 {
01504   __IO uint32_t count = 0U;
01505
01506   /* Check the parameters */
01507   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
01508
01509   if(hi2c->State == HAL_I2C_STATE_READY)
01510   {
01511     /* Check Busy Flag only if FIRST call of Master interface */
01512     if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
01513     {
01514       /* Wait until BUSY flag is reset */
01515       count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
01516       do
01517       {
01518         if(count-- == 0U)
01519         {
01520           hi2c->PreviousState = I2C_STATE_NONE;
01521           hi2c->State= HAL_I2C_STATE_READY;
01522
01523           /* Process Unlocked */
01524           __HAL_UNLOCK(hi2c);
01525
01526           return HAL_TIMEOUT;
01527         }
01528       }
01529       while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
01530     }
01531
01532     /* Process Locked */
01533     __HAL_LOCK(hi2c);
01534
01535     /* Check if the I2C is already enabled */
01536     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01537     {
01538       /* Enable I2C peripheral */
01539       __HAL_I2C_ENABLE(hi2c);
01540     }
01541
01542     /* Disable Pos */
01543     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01544
01545     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01546     hi2c->Mode      = HAL_I2C_MODE_MASTER;
01547     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01548
01549     /* Prepare transfer parameters */
01550     hi2c->pBuffPtr = pData;
01551     hi2c->XferCount = Size;
01552     hi2c->XferOptions = XferOptions;
01553     hi2c->XferSize    = hi2c->XferCount;
01554     hi2c->Devaddress = DevAddress;
01555
01556     if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
01557     {
01558       /* Generate Start condition if first transfer */
01559       if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)  || (XferOptions == I2C_NO_OPTION_FRAME))
01560       {
01561         /* Enable Acknowledge */
01562         hi2c->Instance->CR1 |= I2C_CR1_ACK;
01563
01564         /* Generate Start */
01565         hi2c->Instance->CR1 |= I2C_CR1_START;
01566       }
01567       else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
01568       {
01569         /* Enable Acknowledge */
01570         hi2c->Instance->CR1 |= I2C_CR1_ACK;
01571
01572         /* Generate ReStart */
01573         hi2c->Instance->CR1 |= I2C_CR1_START;
01574       }
01575     }
01576
01577     /* Process Unlocked */
01578     __HAL_UNLOCK(hi2c);
01579
01580     /* Note : The I2C interrupts must be enabled after unlocking current process
01581     to avoid the risk of I2C interrupt handle execution before current
01582     process unlock */
01583
01584     /* Enable EVT, BUF and ERR interrupt */
01585     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01586
01587     return HAL_OK;
01588   }
01589   else
01590   {
01591     return HAL_BUSY;
01592   }
01593 }
01594
01595 /**
01596   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
01597   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01598   *         the configuration information for the specified I2C.
01599   * @param  pData Pointer to data buffer
01600   * @param  Size Amount of data to be sent
01601   * @retval HAL status
01602   */
01603 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01604 {
01605   __IO uint32_t count = 0U;
01606
01607   if(hi2c->State == HAL_I2C_STATE_READY)
01608   {
01609     if((pData == NULL) || (Size == 0U))
01610     {
01611       return  HAL_ERROR;
01612     }
01613
01614     /* Wait until BUSY flag is reset */
01615     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
01616     do
01617     {
01618       if(count-- == 0U)
01619       {
01620         hi2c->PreviousState = I2C_STATE_NONE;
01621         hi2c->State= HAL_I2C_STATE_READY;
01622
01623         /* Process Unlocked */
01624         __HAL_UNLOCK(hi2c);
01625
01626         return HAL_TIMEOUT;
01627       }
01628     }
01629     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
01630
01631     /* Process Locked */
01632     __HAL_LOCK(hi2c);
01633
01634     /* Check if the I2C is already enabled */
01635     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01636     {
01637       /* Enable I2C peripheral */
01638       __HAL_I2C_ENABLE(hi2c);
01639     }
01640
01641     /* Disable Pos */
01642     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01643
01644     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01645     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01646     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01647
01648     /* Prepare transfer parameters */
01649     hi2c->pBuffPtr    = pData;
01650     hi2c->XferCount   = Size;
01651     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01652     hi2c->XferSize    = hi2c->XferCount;
01653
01654     /* Enable Address Acknowledge */
01655     hi2c->Instance->CR1 |= I2C_CR1_ACK;
01656
01657     /* Process Unlocked */
01658     __HAL_UNLOCK(hi2c);
01659
01660     /* Note : The I2C interrupts must be enabled after unlocking current process
01661               to avoid the risk of I2C interrupt handle execution before current
01662               process unlock */
01663
01664     /* Enable EVT, BUF and ERR interrupt */
01665     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01666
01667     return HAL_OK;
01668   }
01669   else
01670   {
01671     return HAL_BUSY;
01672   }
01673 }
01674
01675 /**
01676   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt
01677   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01678   *                the configuration information for the specified I2C.
01679   * @param  pData Pointer to data buffer
01680   * @param  Size Amount of data to be sent
01681   * @retval HAL status
01682   */
01683 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01684 {
01685   __IO uint32_t count = 0U;
01686
01687   if(hi2c->State == HAL_I2C_STATE_READY)
01688   {
01689     if((pData == NULL) || (Size == 0U))
01690     {
01691       return  HAL_ERROR;
01692     }
01693
01694     /* Wait until BUSY flag is reset */
01695     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
01696     do
01697     {
01698       if(count-- == 0U)
01699       {
01700         hi2c->PreviousState = I2C_STATE_NONE;
01701         hi2c->State= HAL_I2C_STATE_READY;
01702
01703         /* Process Unlocked */
01704         __HAL_UNLOCK(hi2c);
01705
01706         return HAL_TIMEOUT;
01707       }
01708     }
01709     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
01710
01711     /* Process Locked */
01712     __HAL_LOCK(hi2c);
01713
01714     /* Check if the I2C is already enabled */
01715     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01716     {
01717       /* Enable I2C peripheral */
01718       __HAL_I2C_ENABLE(hi2c);
01719     }
01720
01721     /* Disable Pos */
01722     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01723
01724     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01725     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01726     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01727
01728     /* Prepare transfer parameters */
01729     hi2c->pBuffPtr = pData;
01730     hi2c->XferSize = Size;
01731     hi2c->XferCount = Size;
01732     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01733
01734     /* Enable Address Acknowledge */
01735     hi2c->Instance->CR1 |= I2C_CR1_ACK;
01736
01737     /* Process Unlocked */
01738     __HAL_UNLOCK(hi2c);
01739
01740     /* Note : The I2C interrupts must be enabled after unlocking current process
01741               to avoid the risk of I2C interrupt handle execution before current
01742               process unlock */
01743
01744     /* Enable EVT, BUF and ERR interrupt */
01745     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01746
01747     return HAL_OK;
01748   }
01749   else
01750   {
01751     return HAL_BUSY;
01752   }
01753 }
01754
01755 /**
01756   * @brief  Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
01757   * @note   This interface allow to manage repeated start condition when a direction change during transfer
01758   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01759   *         the configuration information for I2C module
01760   * @param  pData Pointer to data buffer
01761   * @param  Size Amount of data to be sent
01762   * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
01763   * @retval HAL status
01764   */
01765 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01766 {
01767   /* Check the parameters */
01768   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
01769
01770   if(hi2c->State == HAL_I2C_STATE_LISTEN)
01771   {
01772     if((pData == NULL) || (Size == 0U))
01773     {
01774       return  HAL_ERROR;
01775     }
01776
01777     /* Process Locked */
01778     __HAL_LOCK(hi2c);
01779
01780     /* Check if the I2C is already enabled */
01781     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01782     {
01783       /* Enable I2C peripheral */
01784       __HAL_I2C_ENABLE(hi2c);
01785     }
01786
01787     /* Disable Pos */
01788     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01789
01790     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
01791     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01792     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01793
01794     /* Prepare transfer parameters */
01795     hi2c->pBuffPtr    = pData;
01796     hi2c->XferCount   = Size;
01797     hi2c->XferOptions = XferOptions;
01798     hi2c->XferSize    = hi2c->XferCount;
01799
01800     /* Clear ADDR flag */
01801     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01802
01803     /* Process Unlocked */
01804     __HAL_UNLOCK(hi2c);
01805
01806     /* Note : The I2C interrupts must be enabled after unlocking current process
01807               to avoid the risk of I2C interrupt handle execution before current
01808               process unlock */
01809
01810     /* Enable EVT, BUF and ERR interrupt */
01811     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01812
01813     return HAL_OK;
01814   }
01815   else
01816   {
01817     return HAL_BUSY;
01818   }
01819 }
01820
01821 /**
01822   * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
01823   * @note   This interface allow to manage repeated start condition when a direction change during transfer
01824   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01825   *         the configuration information for the specified I2C.
01826   * @param  pData Pointer to data buffer
01827   * @param  Size Amount of data to be sent
01828   * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
01829   * @retval HAL status
01830   */
01831 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
01832 {
01833   /* Check the parameters */
01834   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
01835
01836   if(hi2c->State == HAL_I2C_STATE_LISTEN)
01837   {
01838     if((pData == NULL) || (Size == 0U))
01839     {
01840       return  HAL_ERROR;
01841     }
01842
01843     /* Process Locked */
01844     __HAL_LOCK(hi2c);
01845
01846     /* Check if the I2C is already enabled */
01847     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01848     {
01849       /* Enable I2C peripheral */
01850       __HAL_I2C_ENABLE(hi2c);
01851     }
01852
01853     /* Disable Pos */
01854     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01855
01856     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
01857     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01858     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01859
01860     /* Prepare transfer parameters */
01861     hi2c->pBuffPtr   = pData;
01862     hi2c->XferCount   = Size;
01863     hi2c->XferOptions = XferOptions;
01864     hi2c->XferSize    = hi2c->XferCount;
01865
01866     /* Clear ADDR flag */
01867     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
01868
01869     /* Process Unlocked */
01870     __HAL_UNLOCK(hi2c);
01871
01872     /* Note : The I2C interrupts must be enabled after unlocking current process
01873               to avoid the risk of I2C interrupt handle execution before current
01874               process unlock */
01875
01876     /* Enable EVT, BUF and ERR interrupt */
01877     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
01878
01879     return HAL_OK;
01880   }
01881   else
01882   {
01883     return HAL_BUSY;
01884   }
01885 }
01886
01887 /**
01888   * @brief  Enable the Address listen mode with Interrupt.
01889   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01890   *                the configuration information for the specified I2C.
01891   * @retval HAL status
01892   */
01893 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
01894 {
01895   if(hi2c->State == HAL_I2C_STATE_READY)
01896   {
01897     hi2c->State = HAL_I2C_STATE_LISTEN;
01898
01899     /* Check if the I2C is already enabled */
01900     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01901     {
01902       /* Enable I2C peripheral */
01903       __HAL_I2C_ENABLE(hi2c);
01904     }
01905
01906     /* Enable Address Acknowledge */
01907     hi2c->Instance->CR1 |= I2C_CR1_ACK;
01908
01909     /* Enable EVT and ERR interrupt */
01910     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
01911
01912     return HAL_OK;
01913   }
01914   else
01915   {
01916     return HAL_BUSY;
01917   }
01918 }
01919
01920 /**
01921   * @brief  Disable the Address listen mode with Interrupt.
01922   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01923   *                the configuration information for the specified I2C.
01924   * @retval HAL status
01925   */
01926 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
01927 {
01928   /* Declaration of tmp to prevent undefined behavior of volatile usage */
01929   uint32_t tmp;
01930
01931   /* Disable Address listen mode only if a transfer is not ongoing */
01932   if(hi2c->State == HAL_I2C_STATE_LISTEN)
01933   {
01934     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
01935     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
01936     hi2c->State = HAL_I2C_STATE_READY;
01937     hi2c->Mode = HAL_I2C_MODE_NONE;
01938
01939     /* Disable Address Acknowledge */
01940     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
01941
01942     /* Disable EVT and ERR interrupt */
01943     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
01944
01945     return HAL_OK;
01946   }
01947   else
01948   {
01949     return HAL_BUSY;
01950   }
01951 }
01952
01953 /**
01954   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
01955   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01956   *                the configuration information for the specified I2C.
01957   * @param  DevAddress Target device address: The device 7 bits address value
01958   *         in datasheet must be shift at right before call interface
01959   * @param  pData Pointer to data buffer
01960   * @param  Size Amount of data to be sent
01961   * @retval HAL status
01962   */
01963 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01964 {
01965   __IO uint32_t count = 0U;
01966
01967   if(hi2c->State == HAL_I2C_STATE_READY)
01968   {
01969     /* Wait until BUSY flag is reset */
01970     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
01971     do
01972     {
01973       if(count-- == 0U)
01974       {
01975         hi2c->PreviousState = I2C_STATE_NONE;
01976         hi2c->State= HAL_I2C_STATE_READY;
01977
01978         /* Process Unlocked */
01979         __HAL_UNLOCK(hi2c);
01980
01981         return HAL_TIMEOUT;
01982       }
01983     }
01984     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
01985
01986     /* Process Locked */
01987     __HAL_LOCK(hi2c);
01988
01989     /* Check if the I2C is already enabled */
01990     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
01991     {
01992       /* Enable I2C peripheral */
01993       __HAL_I2C_ENABLE(hi2c);
01994     }
01995
01996     /* Disable Pos */
01997     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
01998
01999     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02000     hi2c->Mode      = HAL_I2C_MODE_MASTER;
02001     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02002
02003     /* Prepare transfer parameters */
02004     hi2c->pBuffPtr    = pData;
02005     hi2c->XferCount   = Size;
02006     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02007     hi2c->XferSize    = hi2c->XferCount;
02008     hi2c->Devaddress  = DevAddress;
02009
02010     if(hi2c->XferSize > 0U)
02011     {
02012       /* Set the I2C DMA transfer complete callback */
02013       hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
02014
02015       /* Set the DMA error callback */
02016       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02017
02018       /* Set the unused DMA callbacks to NULL */
02019       hi2c->hdmatx->XferHalfCpltCallback = NULL;
02020       hi2c->hdmatx->XferAbortCallback = NULL;
02021
02022       /* Enable the DMA channel */
02023       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
02024
02025       /* Enable Acknowledge */
02026       hi2c->Instance->CR1 |= I2C_CR1_ACK;
02027
02028       /* Generate Start */
02029       hi2c->Instance->CR1 |= I2C_CR1_START;
02030
02031       /* Process Unlocked */
02032       __HAL_UNLOCK(hi2c);
02033
02034       /* Note : The I2C interrupts must be enabled after unlocking current process
02035       to avoid the risk of I2C interrupt handle execution before current
02036       process unlock */
02037
02038       /* Enable EVT and ERR interrupt */
02039       __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
02040
02041       /* Enable DMA Request */
02042       hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
02043     }
02044     else
02045     {
02046       /* Enable Acknowledge */
02047       hi2c->Instance->CR1 |= I2C_CR1_ACK;
02048
02049       /* Generate Start */
02050       hi2c->Instance->CR1 |= I2C_CR1_START;
02051
02052       /* Process Unlocked */
02053       __HAL_UNLOCK(hi2c);
02054
02055       /* Note : The I2C interrupts must be enabled after unlocking current process
02056       to avoid the risk of I2C interrupt handle execution before current
02057       process unlock */
02058
02059      /* Enable EVT, BUF and ERR interrupt */
02060     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
02061     }
02062
02063     return HAL_OK;
02064   }
02065   else
02066   {
02067     return HAL_BUSY;
02068   }
02069 }
02070
02071 /**
02072   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
02073   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02074   *                the configuration information for the specified I2C.
02075   * @param  DevAddress Target device address: The device 7 bits address value
02076   *         in datasheet must be shift at right before call interface
02077   * @param  pData Pointer to data buffer
02078   * @param  Size Amount of data to be sent
02079   * @retval HAL status
02080   */
02081 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
02082 {
02083   __IO uint32_t count = 0U;
02084
02085   if(hi2c->State == HAL_I2C_STATE_READY)
02086   {
02087     /* Wait until BUSY flag is reset */
02088     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
02089     do
02090     {
02091       if(count-- == 0U)
02092       {
02093         hi2c->PreviousState = I2C_STATE_NONE;
02094         hi2c->State= HAL_I2C_STATE_READY;
02095
02096         /* Process Unlocked */
02097         __HAL_UNLOCK(hi2c);
02098
02099         return HAL_TIMEOUT;
02100       }
02101     }
02102     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
02103
02104     /* Process Locked */
02105     __HAL_LOCK(hi2c);
02106
02107     /* Check if the I2C is already enabled */
02108     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
02109     {
02110       /* Enable I2C peripheral */
02111       __HAL_I2C_ENABLE(hi2c);
02112     }
02113
02114     /* Disable Pos */
02115     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02116
02117     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02118     hi2c->Mode      = HAL_I2C_MODE_MASTER;
02119     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02120
02121     /* Prepare transfer parameters */
02122     hi2c->pBuffPtr    = pData;
02123     hi2c->XferCount   = Size;
02124     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02125     hi2c->XferSize    = hi2c->XferCount;
02126     hi2c->Devaddress  = DevAddress;
02127
02128     if(hi2c->XferSize > 0U)
02129     {
02130       /* Set the I2C DMA transfer complete callback */
02131       hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
02132
02133       /* Set the DMA error callback */
02134       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02135
02136       /* Set the unused DMA callbacks to NULL */
02137       hi2c->hdmarx->XferHalfCpltCallback = NULL;
02138       hi2c->hdmarx->XferAbortCallback = NULL;
02139
02140       /* Enable the DMA channel */
02141       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
02142
02143       /* Enable Acknowledge */
02144       hi2c->Instance->CR1 |= I2C_CR1_ACK;
02145
02146       /* Generate Start */
02147       hi2c->Instance->CR1 |= I2C_CR1_START;
02148
02149       /* Process Unlocked */
02150       __HAL_UNLOCK(hi2c);
02151
02152       /* Note : The I2C interrupts must be enabled after unlocking current process
02153                 to avoid the risk of I2C interrupt handle execution before current
02154                 process unlock */
02155
02156       /* Enable EVT and ERR interrupt */
02157       __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
02158
02159       /* Enable DMA Request */
02160       hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
02161     }
02162     else
02163     {
02164       /* Enable Acknowledge */
02165       hi2c->Instance->CR1 |= I2C_CR1_ACK;
02166
02167       /* Generate Start */
02168       hi2c->Instance->CR1 |= I2C_CR1_START;
02169
02170       /* Process Unlocked */
02171       __HAL_UNLOCK(hi2c);
02172
02173       /* Note : The I2C interrupts must be enabled after unlocking current process
02174       to avoid the risk of I2C interrupt handle execution before current
02175       process unlock */
02176
02177       /* Enable EVT, BUF and ERR interrupt */
02178       __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
02179     }
02180
02181     return HAL_OK;
02182   }
02183   else
02184   {
02185     return HAL_BUSY;
02186   }
02187 }
02188
02189 /**
02190   * @brief  Abort a master I2C process communication with Interrupt.
02191   * @note   This abort can be called only if state is ready
02192   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02193   *         the configuration information for the specified I2C.
02194   * @param  DevAddress Target device address: The device 7 bits address value
02195   *         in datasheet must be shift at right before call interface
02196   * @retval HAL status
02197   */
02198 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
02199 {
02200   /* Abort Master transfer during Receive or Transmit process    */
02201   if(hi2c->Mode == HAL_I2C_MODE_MASTER)
02202   {
02203     /* Process Locked */
02204     __HAL_LOCK(hi2c);
02205
02206     hi2c->PreviousState = I2C_STATE_NONE;
02207     hi2c->State = HAL_I2C_STATE_ABORT;
02208
02209     /* Disable Acknowledge */
02210     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02211
02212     /* Generate Stop */
02213     hi2c->Instance->CR1 |= I2C_CR1_STOP;
02214
02215     hi2c->XferCount = 0U;
02216
02217     /* Disable EVT, BUF and ERR interrupt */
02218     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
02219
02220     /* Process Unlocked */
02221     __HAL_UNLOCK(hi2c);
02222
02223     /* Call the corresponding callback to inform upper layer of End of Transfer */
02224     I2C_ITError(hi2c);
02225
02226     return HAL_OK;
02227   }
02228   else
02229   {
02230     /* Wrong usage of abort function */
02231     /* This function should be used only in case of abort monitored by master device */
02232     return HAL_ERROR;
02233   }
02234 }
02235
02236 /**
02237   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
02238   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02239   *                the configuration information for the specified I2C.
02240   * @param  pData Pointer to data buffer
02241   * @param  Size Amount of data to be sent
02242   * @retval HAL status
02243   */
02244 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02245 {
02246   __IO uint32_t count = 0U;
02247
02248   if(hi2c->State == HAL_I2C_STATE_READY)
02249   {
02250     if((pData == NULL) || (Size == 0U))
02251     {
02252       return  HAL_ERROR;
02253     }
02254
02255     /* Wait until BUSY flag is reset */
02256     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
02257     do
02258     {
02259       if(count-- == 0U)
02260       {
02261         hi2c->PreviousState = I2C_STATE_NONE;
02262         hi2c->State= HAL_I2C_STATE_READY;
02263
02264         /* Process Unlocked */
02265         __HAL_UNLOCK(hi2c);
02266
02267         return HAL_TIMEOUT;
02268       }
02269     }
02270     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
02271
02272     /* Process Locked */
02273     __HAL_LOCK(hi2c);
02274
02275     /* Check if the I2C is already enabled */
02276     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
02277     {
02278       /* Enable I2C peripheral */
02279       __HAL_I2C_ENABLE(hi2c);
02280     }
02281
02282     /* Disable Pos */
02283     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02284
02285     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02286     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
02287     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02288
02289     /* Prepare transfer parameters */
02290     hi2c->pBuffPtr    = pData;
02291     hi2c->XferCount   = Size;
02292     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02293     hi2c->XferSize    = hi2c->XferCount;
02294
02295     /* Set the I2C DMA transfer complete callback */
02296     hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
02297
02298     /* Set the DMA error callback */
02299     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02300
02301     /* Set the unused DMA callbacks to NULL */
02302     hi2c->hdmatx->XferHalfCpltCallback = NULL;
02303     hi2c->hdmatx->XferAbortCallback = NULL;
02304
02305     /* Enable the DMA channel */
02306     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
02307
02308     /* Enable Address Acknowledge */
02309     hi2c->Instance->CR1 |= I2C_CR1_ACK;
02310
02311     /* Process Unlocked */
02312     __HAL_UNLOCK(hi2c);
02313
02314       /* Note : The I2C interrupts must be enabled after unlocking current process
02315                 to avoid the risk of I2C interrupt handle execution before current
02316                 process unlock */
02317     /* Enable EVT and ERR interrupt */
02318     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
02319
02320     /* Enable DMA Request */
02321     hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
02322
02323     return HAL_OK;
02324   }
02325   else
02326   {
02327     return HAL_BUSY;
02328   }
02329 }
02330
02331 /**
02332   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
02333   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02334   *                the configuration information for the specified I2C.
02335   * @param  pData Pointer to data buffer
02336   * @param  Size Amount of data to be sent
02337   * @retval HAL status
02338   */
02339 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
02340 {
02341   __IO uint32_t count = 0U;
02342
02343   if(hi2c->State == HAL_I2C_STATE_READY)
02344   {
02345     if((pData == NULL) || (Size == 0U))
02346     {
02347       return  HAL_ERROR;
02348     }
02349
02350     /* Wait until BUSY flag is reset */
02351     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
02352     do
02353     {
02354       if(count-- == 0U)
02355       {
02356         hi2c->PreviousState = I2C_STATE_NONE;
02357         hi2c->State= HAL_I2C_STATE_READY;
02358
02359         /* Process Unlocked */
02360         __HAL_UNLOCK(hi2c);
02361
02362         return HAL_TIMEOUT;
02363       }
02364     }
02365     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
02366
02367     /* Process Locked */
02368     __HAL_LOCK(hi2c);
02369
02370     /* Check if the I2C is already enabled */
02371     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
02372     {
02373       /* Enable I2C peripheral */
02374       __HAL_I2C_ENABLE(hi2c);
02375     }
02376
02377     /* Disable Pos */
02378     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02379
02380     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02381     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
02382     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02383
02384     /* Prepare transfer parameters */
02385     hi2c->pBuffPtr    = pData;
02386     hi2c->XferCount   = Size;
02387     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02388     hi2c->XferSize    = hi2c->XferCount;
02389
02390     /* Set the I2C DMA transfer complete callback */
02391     hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
02392
02393     /* Set the DMA error callback */
02394     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02395
02396     /* Set the unused DMA callbacks to NULL */
02397     hi2c->hdmarx->XferHalfCpltCallback = NULL;
02398     hi2c->hdmarx->XferAbortCallback = NULL;
02399
02400     /* Enable the DMA channel */
02401     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
02402
02403     /* Enable Address Acknowledge */
02404     hi2c->Instance->CR1 |= I2C_CR1_ACK;
02405
02406     /* Process Unlocked */
02407     __HAL_UNLOCK(hi2c);
02408
02409     /* Note : The I2C interrupts must be enabled after unlocking current process
02410               to avoid the risk of I2C interrupt handle execution before current
02411               process unlock */
02412     /* Enable EVT and ERR interrupt */
02413     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
02414
02415     /* Enable DMA Request */
02416     hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
02417
02418     return HAL_OK;
02419   }
02420   else
02421   {
02422     return HAL_BUSY;
02423   }
02424 }
02425 /**
02426   * @brief  Write an amount of data in blocking mode to a specific memory address
02427   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02428   *                the configuration information for the specified I2C.
02429   * @param  DevAddress Target device address
02430   * @param  MemAddress Internal memory address
02431   * @param  MemAddSize Size of internal memory address
02432   * @param  pData Pointer to data buffer
02433   * @param  Size Amount of data to be sent
02434   * @param  Timeout Timeout duration
02435   * @retval HAL status
02436   */
02437 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02438 {
02439   uint32_t tickstart = 0x00U;
02440
02441   /* Init tickstart for timeout management*/
02442   tickstart = HAL_GetTick();
02443
02444   /* Check the parameters */
02445   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02446
02447   if(hi2c->State == HAL_I2C_STATE_READY)
02448   {
02449     /* Wait until BUSY flag is reset */
02450     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
02451     {
02452       return HAL_BUSY;
02453     }
02454
02455     /* Process Locked */
02456     __HAL_LOCK(hi2c);
02457
02458     /* Check if the I2C is already enabled */
02459     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
02460     {
02461       /* Enable I2C peripheral */
02462       __HAL_I2C_ENABLE(hi2c);
02463     }
02464
02465     /* Disable Pos */
02466     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02467
02468     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02469     hi2c->Mode      = HAL_I2C_MODE_MEM;
02470     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02471
02472     /* Prepare transfer parameters */
02473     hi2c->pBuffPtr    = pData;
02474     hi2c->XferCount   = Size;
02475     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02476     hi2c->XferSize    = hi2c->XferCount;
02477
02478     /* Send Slave Address and Memory Address */
02479     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
02480     {
02481       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02482       {
02483         /* Process Unlocked */
02484         __HAL_UNLOCK(hi2c);
02485         return HAL_ERROR;
02486       }
02487       else
02488       {
02489         /* Process Unlocked */
02490         __HAL_UNLOCK(hi2c);
02491         return HAL_TIMEOUT;
02492       }
02493     }
02494
02495     while(hi2c->XferSize > 0U)
02496     {
02497       /* Wait until TXE flag is set */
02498       if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02499       {
02500         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02501         {
02502           /* Generate Stop */
02503           hi2c->Instance->CR1 |= I2C_CR1_STOP;
02504           return HAL_ERROR;
02505         }
02506         else
02507         {
02508           return HAL_TIMEOUT;
02509         }
02510       }
02511
02512       /* Write data to DR */
02513       hi2c->Instance->DR = (*hi2c->pBuffPtr++);
02514       hi2c->XferSize--;
02515       hi2c->XferCount--;
02516
02517       if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
02518       {
02519         /* Write data to DR */
02520         hi2c->Instance->DR = (*hi2c->pBuffPtr++);
02521         hi2c->XferSize--;
02522         hi2c->XferCount--;
02523       }
02524     }
02525
02526     /* Wait until BTF flag is set */
02527     if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02528     {
02529       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02530       {
02531         /* Generate Stop */
02532         hi2c->Instance->CR1 |= I2C_CR1_STOP;
02533         return HAL_ERROR;
02534       }
02535       else
02536       {
02537         return HAL_TIMEOUT;
02538       }
02539     }
02540
02541     /* Generate Stop */
02542     hi2c->Instance->CR1 |= I2C_CR1_STOP;
02543
02544     hi2c->State = HAL_I2C_STATE_READY;
02545     hi2c->Mode = HAL_I2C_MODE_NONE;
02546
02547     /* Process Unlocked */
02548     __HAL_UNLOCK(hi2c);
02549
02550     return HAL_OK;
02551   }
02552   else
02553   {
02554     return HAL_BUSY;
02555   }
02556 }
02557
02558 /**
02559   * @brief  Read an amount of data in blocking mode from a specific memory address
02560   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02561   *                the configuration information for the specified I2C.
02562   * @param  DevAddress Target device address
02563   * @param  MemAddress Internal memory address
02564   * @param  MemAddSize Size of internal memory address
02565   * @param  pData Pointer to data buffer
02566   * @param  Size Amount of data to be sent
02567   * @param  Timeout Timeout duration
02568   * @retval HAL status
02569   */
02570 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
02571 {
02572   uint32_t tickstart = 0x00U;
02573
02574   /* Init tickstart for timeout management*/
02575   tickstart = HAL_GetTick();
02576
02577   /* Check the parameters */
02578   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02579
02580   if(hi2c->State == HAL_I2C_STATE_READY)
02581   {
02582     /* Wait until BUSY flag is reset */
02583     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
02584     {
02585       return HAL_BUSY;
02586     }
02587
02588     /* Process Locked */
02589     __HAL_LOCK(hi2c);
02590
02591     /* Check if the I2C is already enabled */
02592     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
02593     {
02594       /* Enable I2C peripheral */
02595       __HAL_I2C_ENABLE(hi2c);
02596     }
02597
02598     /* Disable Pos */
02599     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02600
02601     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02602     hi2c->Mode      = HAL_I2C_MODE_MEM;
02603     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02604
02605     /* Prepare transfer parameters */
02606     hi2c->pBuffPtr    = pData;
02607     hi2c->XferCount   = Size;
02608     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02609     hi2c->XferSize    = hi2c->XferCount;
02610
02611     /* Send Slave Address and Memory Address */
02612     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
02613     {
02614       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02615       {
02616         /* Process Unlocked */
02617         __HAL_UNLOCK(hi2c);
02618         return HAL_ERROR;
02619       }
02620       else
02621       {
02622         /* Process Unlocked */
02623         __HAL_UNLOCK(hi2c);
02624         return HAL_TIMEOUT;
02625       }
02626     }
02627
02628     if(hi2c->XferSize == 0U)
02629     {
02630       /* Clear ADDR flag */
02631       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02632
02633       /* Generate Stop */
02634       hi2c->Instance->CR1 |= I2C_CR1_STOP;
02635     }
02636     else if(hi2c->XferSize == 1U)
02637     {
02638       /* Disable Acknowledge */
02639       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02640
02641       /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
02642          software sequence must complete before the current byte end of transfer */
02643       __disable_irq();
02644
02645       /* Clear ADDR flag */
02646       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02647
02648       /* Generate Stop */
02649       hi2c->Instance->CR1 |= I2C_CR1_STOP;
02650
02651       /* Re-enable IRQs */
02652       __enable_irq();
02653     }
02654     else if(hi2c->XferSize == 2U)
02655     {
02656       /* Enable Pos */
02657       hi2c->Instance->CR1 |= I2C_CR1_POS;
02658
02659       /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
02660          software sequence must complete before the current byte end of transfer */
02661       __disable_irq();
02662
02663       /* Clear ADDR flag */
02664       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02665
02666       /* Disable Acknowledge */
02667       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02668
02669        /* Re-enable IRQs */
02670        __enable_irq();
02671     }
02672     else
02673     {
02674       /* Enable Acknowledge */
02675       SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
02676
02677       /* Clear ADDR flag */
02678       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
02679     }
02680
02681     while(hi2c->XferSize > 0U)
02682     {
02683       if(hi2c->XferSize <= 3U)
02684       {
02685         /* One byte */
02686         if(hi2c->XferSize== 1U)
02687         {
02688           /* Wait until RXNE flag is set */
02689           if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02690           {
02691             if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
02692             {
02693               return HAL_TIMEOUT;
02694             }
02695             else
02696             {
02697               return HAL_ERROR;
02698             }
02699           }
02700
02701           /* Read data from DR */
02702           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
02703           hi2c->XferSize--;
02704           hi2c->XferCount--;
02705         }
02706         /* Two bytes */
02707         else if(hi2c->XferSize == 2U)
02708         {
02709           /* Wait until BTF flag is set */
02710           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
02711           {
02712             return HAL_TIMEOUT;
02713           }
02714
02715           /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
02716              software sequence must complete before the current byte end of transfer */
02717            __disable_irq();
02718
02719           /* Generate Stop */
02720           hi2c->Instance->CR1 |= I2C_CR1_STOP;
02721
02722           /* Read data from DR */
02723           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
02724           hi2c->XferSize--;
02725           hi2c->XferCount--;
02726
02727           /* Re-enable IRQs */
02728           __enable_irq();
02729
02730           /* Read data from DR */
02731           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
02732           hi2c->XferSize--;
02733           hi2c->XferCount--;
02734         }
02735         /* 3 Last bytes */
02736         else
02737         {
02738           /* Wait until BTF flag is set */
02739           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
02740           {
02741             return HAL_TIMEOUT;
02742           }
02743
02744           /* Disable Acknowledge */
02745           hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
02746
02747           /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
02748              software sequence must complete before the current byte end of transfer */
02749           __disable_irq();
02750
02751           /* Read data from DR */
02752           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
02753           hi2c->XferSize--;
02754           hi2c->XferCount--;
02755
02756           /* Wait until BTF flag is set */
02757           if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
02758           {
02759             return HAL_TIMEOUT;
02760           }
02761
02762           /* Generate Stop */
02763           hi2c->Instance->CR1 |= I2C_CR1_STOP;
02764
02765           /* Read data from DR */
02766           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
02767           hi2c->XferSize--;
02768           hi2c->XferCount--;
02769
02770           /* Re-enable IRQs */
02771           __enable_irq();
02772
02773           /* Read data from DR */
02774           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
02775           hi2c->XferSize--;
02776           hi2c->XferCount--;
02777         }
02778       }
02779       else
02780       {
02781         /* Wait until RXNE flag is set */
02782         if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
02783         {
02784           if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
02785           {
02786             return HAL_TIMEOUT;
02787           }
02788           else
02789           {
02790             return HAL_ERROR;
02791           }
02792         }
02793
02794         /* Read data from DR */
02795         (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
02796         hi2c->XferSize--;
02797         hi2c->XferCount--;
02798
02799         if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
02800         {
02801           /* Read data from DR */
02802           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
02803           hi2c->XferSize--;
02804           hi2c->XferCount--;
02805         }
02806       }
02807     }
02808
02809     hi2c->State = HAL_I2C_STATE_READY;
02810     hi2c->Mode = HAL_I2C_MODE_NONE;
02811
02812     /* Process Unlocked */
02813     __HAL_UNLOCK(hi2c);
02814
02815     return HAL_OK;
02816   }
02817   else
02818   {
02819     return HAL_BUSY;
02820   }
02821 }
02822
02823 /**
02824   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
02825   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02826   *                the configuration information for the specified I2C.
02827   * @param  DevAddress Target device address
02828   * @param  MemAddress Internal memory address
02829   * @param  MemAddSize Size of internal memory address
02830   * @param  pData Pointer to data buffer
02831   * @param  Size Amount of data to be sent
02832   * @retval HAL status
02833   */
02834 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02835 {
02836   __IO uint32_t count = 0U;
02837
02838   /* Check the parameters */
02839   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02840
02841   if(hi2c->State == HAL_I2C_STATE_READY)
02842   {
02843     /* Wait until BUSY flag is reset */
02844     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
02845     do
02846     {
02847       if(count-- == 0U)
02848       {
02849         hi2c->PreviousState = I2C_STATE_NONE;
02850         hi2c->State= HAL_I2C_STATE_READY;
02851
02852         /* Process Unlocked */
02853         __HAL_UNLOCK(hi2c);
02854
02855         return HAL_TIMEOUT;
02856       }
02857     }
02858     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
02859
02860     /* Process Locked */
02861     __HAL_LOCK(hi2c);
02862
02863     /* Check if the I2C is already enabled */
02864     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
02865     {
02866       /* Enable I2C peripheral */
02867       __HAL_I2C_ENABLE(hi2c);
02868     }
02869
02870     /* Disable Pos */
02871     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02872
02873     hi2c->State = HAL_I2C_STATE_BUSY_TX;
02874     hi2c->Mode = HAL_I2C_MODE_MEM;
02875     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02876
02877     /* Prepare transfer parameters */
02878     hi2c->pBuffPtr = pData;
02879     hi2c->XferSize = Size;
02880     hi2c->XferCount = Size;
02881     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02882     hi2c->Devaddress = DevAddress;
02883     hi2c->Memaddress = MemAddress;
02884     hi2c->MemaddSize = MemAddSize;
02885     hi2c->EventCount = 0U;
02886
02887     /* Generate Start */
02888     hi2c->Instance->CR1 |= I2C_CR1_START;
02889
02890     /* Process Unlocked */
02891     __HAL_UNLOCK(hi2c);
02892
02893     /* Note : The I2C interrupts must be enabled after unlocking current process
02894     to avoid the risk of I2C interrupt handle execution before current
02895     process unlock */
02896
02897     /* Enable EVT, BUF and ERR interrupt */
02898     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
02899
02900     return HAL_OK;
02901   }
02902   else
02903   {
02904     return HAL_BUSY;
02905   }
02906 }
02907
02908 /**
02909   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
02910   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02911   *                the configuration information for the specified I2C.
02912   * @param  DevAddress Target device address
02913   * @param  MemAddress Internal memory address
02914   * @param  MemAddSize Size of internal memory address
02915   * @param  pData Pointer to data buffer
02916   * @param  Size Amount of data to be sent
02917   * @retval HAL status
02918   */
02919 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02920 {
02921   __IO uint32_t count = 0U;
02922
02923   /* Check the parameters */
02924   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02925
02926   if(hi2c->State == HAL_I2C_STATE_READY)
02927   {
02928     /* Wait until BUSY flag is reset */
02929     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
02930     do
02931     {
02932       if(count-- == 0U)
02933       {
02934         hi2c->PreviousState = I2C_STATE_NONE;
02935         hi2c->State= HAL_I2C_STATE_READY;
02936
02937         /* Process Unlocked */
02938         __HAL_UNLOCK(hi2c);
02939
02940         return HAL_TIMEOUT;
02941       }
02942     }
02943     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
02944
02945     /* Process Locked */
02946     __HAL_LOCK(hi2c);
02947
02948     /* Check if the I2C is already enabled */
02949     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
02950     {
02951       /* Enable I2C peripheral */
02952       __HAL_I2C_ENABLE(hi2c);
02953     }
02954
02955     /* Disable Pos */
02956     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
02957
02958     hi2c->State = HAL_I2C_STATE_BUSY_RX;
02959     hi2c->Mode = HAL_I2C_MODE_MEM;
02960     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02961
02962     /* Prepare transfer parameters */
02963     hi2c->pBuffPtr = pData;
02964     hi2c->XferSize = Size;
02965     hi2c->XferCount = Size;
02966     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02967     hi2c->Devaddress = DevAddress;
02968     hi2c->Memaddress = MemAddress;
02969     hi2c->MemaddSize = MemAddSize;
02970     hi2c->EventCount = 0U;
02971
02972     /* Enable Acknowledge */
02973     hi2c->Instance->CR1 |= I2C_CR1_ACK;
02974
02975     /* Generate Start */
02976     hi2c->Instance->CR1 |= I2C_CR1_START;
02977
02978     /* Process Unlocked */
02979     __HAL_UNLOCK(hi2c);
02980
02981     if(hi2c->XferSize > 0U)
02982     {
02983       /* Note : The I2C interrupts must be enabled after unlocking current process
02984       to avoid the risk of I2C interrupt handle execution before current
02985       process unlock */
02986
02987       /* Enable EVT, BUF and ERR interrupt */
02988       __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
02989     }
02990     return HAL_OK;
02991   }
02992   else
02993   {
02994     return HAL_BUSY;
02995   }
02996 }
02997
02998 /**
02999   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
03000   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03001   *                the configuration information for the specified I2C.
03002   * @param  DevAddress Target device address
03003   * @param  MemAddress Internal memory address
03004   * @param  MemAddSize Size of internal memory address
03005   * @param  pData Pointer to data buffer
03006   * @param  Size Amount of data to be sent
03007   * @retval HAL status
03008   */
03009 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
03010 {
03011   __IO uint32_t count = 0U;
03012
03013   uint32_t tickstart = 0x00U;
03014
03015   /* Init tickstart for timeout management*/
03016   tickstart = HAL_GetTick();
03017
03018   /* Check the parameters */
03019   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
03020
03021   if(hi2c->State == HAL_I2C_STATE_READY)
03022   {
03023     /* Wait until BUSY flag is reset */
03024     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
03025     do
03026     {
03027       if(count-- == 0U)
03028       {
03029         hi2c->PreviousState = I2C_STATE_NONE;
03030         hi2c->State= HAL_I2C_STATE_READY;
03031
03032         /* Process Unlocked */
03033         __HAL_UNLOCK(hi2c);
03034
03035         return HAL_TIMEOUT;
03036       }
03037     }
03038     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
03039
03040     /* Process Locked */
03041     __HAL_LOCK(hi2c);
03042
03043     /* Check if the I2C is already enabled */
03044     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
03045     {
03046       /* Enable I2C peripheral */
03047       __HAL_I2C_ENABLE(hi2c);
03048     }
03049
03050     /* Disable Pos */
03051     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
03052
03053     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
03054     hi2c->Mode      = HAL_I2C_MODE_MEM;
03055     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03056
03057     /* Prepare transfer parameters */
03058     hi2c->pBuffPtr = pData;
03059     hi2c->XferSize = Size;
03060     hi2c->XferCount = Size;
03061     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
03062
03063     if(hi2c->XferSize > 0U)
03064     {
03065       /* Set the I2C DMA transfer complete callback */
03066       hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
03067
03068       /* Set the DMA error callback */
03069       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
03070
03071       /* Set the unused DMA callbacks to NULL */
03072       hi2c->hdmatx->XferHalfCpltCallback = NULL;
03073       hi2c->hdmatx->XferAbortCallback = NULL;
03074
03075       /* Enable the DMA channel */
03076       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
03077
03078       /* Send Slave Address and Memory Address */
03079       if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
03080       {
03081         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03082         {
03083           /* Process Unlocked */
03084           __HAL_UNLOCK(hi2c);
03085           return HAL_ERROR;
03086         }
03087         else
03088         {
03089           /* Process Unlocked */
03090           __HAL_UNLOCK(hi2c);
03091           return HAL_TIMEOUT;
03092         }
03093       }
03094
03095       /* Clear ADDR flag */
03096       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
03097
03098       /* Process Unlocked */
03099       __HAL_UNLOCK(hi2c);
03100
03101       /* Note : The I2C interrupts must be enabled after unlocking current process
03102       to avoid the risk of I2C interrupt handle execution before current
03103       process unlock */
03104       /* Enable ERR interrupt */
03105       __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
03106
03107       /* Enable DMA Request */
03108       hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
03109     }
03110     return HAL_OK;
03111   }
03112   else
03113   {
03114     return HAL_BUSY;
03115   }
03116 }
03117
03118 /**
03119   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
03120   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03121   *                the configuration information for the specified I2C.
03122   * @param  DevAddress Target device address
03123   * @param  MemAddress Internal memory address
03124   * @param  MemAddSize Size of internal memory address
03125   * @param  pData Pointer to data buffer
03126   * @param  Size Amount of data to be read
03127   * @retval HAL status
03128   */
03129 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
03130 {
03131   uint32_t tickstart = 0x00U;
03132
03133   /* Init tickstart for timeout management*/
03134   tickstart = HAL_GetTick();
03135
03136   __IO uint32_t count = 0U;
03137
03138   /* Check the parameters */
03139   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
03140
03141   if(hi2c->State == HAL_I2C_STATE_READY)
03142   {
03143     /* Wait until BUSY flag is reset */
03144     count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
03145     do
03146     {
03147       if(count-- == 0U)
03148       {
03149         hi2c->PreviousState = I2C_STATE_NONE;
03150         hi2c->State= HAL_I2C_STATE_READY;
03151
03152         /* Process Unlocked */
03153         __HAL_UNLOCK(hi2c);
03154
03155         return HAL_TIMEOUT;
03156       }
03157     }
03158     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
03159
03160     /* Process Locked */
03161     __HAL_LOCK(hi2c);
03162
03163     /* Check if the I2C is already enabled */
03164     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
03165     {
03166       /* Enable I2C peripheral */
03167       __HAL_I2C_ENABLE(hi2c);
03168     }
03169
03170     /* Disable Pos */
03171     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
03172
03173     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
03174     hi2c->Mode      = HAL_I2C_MODE_MEM;
03175     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03176
03177     /* Prepare transfer parameters */
03178     hi2c->pBuffPtr = pData;
03179     hi2c->XferCount = Size;
03180     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
03181     hi2c->XferSize    = hi2c->XferCount;
03182
03183     if(hi2c->XferSize > 0U)
03184     {
03185       /* Set the I2C DMA transfer complete callback */
03186       hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
03187
03188       /* Set the DMA error callback */
03189       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
03190
03191       /* Set the unused DMA callbacks to NULL */
03192       hi2c->hdmarx->XferAbortCallback = NULL;
03193
03194       /* Enable the DMA channel */
03195       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
03196
03197       /* Send Slave Address and Memory Address */
03198       if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
03199       {
03200         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03201         {
03202           /* Process Unlocked */
03203           __HAL_UNLOCK(hi2c);
03204           return HAL_ERROR;
03205         }
03206         else
03207         {
03208           /* Process Unlocked */
03209           __HAL_UNLOCK(hi2c);
03210           return HAL_TIMEOUT;
03211         }
03212       }
03213
03214       if(Size == 1U)
03215       {
03216         /* Disable Acknowledge */
03217         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
03218       }
03219       else
03220       {
03221         /* Enable Last DMA bit */
03222         hi2c->Instance->CR2 |= I2C_CR2_LAST;
03223       }
03224
03225       /* Clear ADDR flag */
03226       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
03227
03228       /* Process Unlocked */
03229       __HAL_UNLOCK(hi2c);
03230
03231       /* Note : The I2C interrupts must be enabled after unlocking current process
03232                 to avoid the risk of I2C interrupt handle execution before current
03233                 process unlock */
03234       /* Enable ERR interrupt */
03235       __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
03236
03237      /* Enable DMA Request */
03238       hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
03239     }
03240     else
03241     {
03242       /* Send Slave Address and Memory Address */
03243       if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
03244       {
03245         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03246         {
03247           /* Process Unlocked */
03248           __HAL_UNLOCK(hi2c);
03249           return HAL_ERROR;
03250         }
03251         else
03252         {
03253           /* Process Unlocked */
03254           __HAL_UNLOCK(hi2c);
03255           return HAL_TIMEOUT;
03256         }
03257       }
03258
03259       /* Clear ADDR flag */
03260       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
03261
03262       /* Generate Stop */
03263       hi2c->Instance->CR1 |= I2C_CR1_STOP;
03264
03265       hi2c->State = HAL_I2C_STATE_READY;
03266
03267       /* Process Unlocked */
03268       __HAL_UNLOCK(hi2c);
03269     }
03270
03271     return HAL_OK;
03272   }
03273   else
03274   {
03275     return HAL_BUSY;
03276   }
03277 }
03278
03279 /**
03280   * @brief  Checks if target device is ready for communication.
03281   * @note   This function is used with Memory devices
03282   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03283   *                the configuration information for the specified I2C.
03284   * @param  DevAddress Target device address
03285   * @param  Trials Number of trials
03286   * @param  Timeout Timeout duration
03287   * @retval HAL status
03288   */
03289 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
03290 {
03291   uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
03292
03293   /* Get tick */
03294   tickstart = HAL_GetTick();
03295
03296   if(hi2c->State == HAL_I2C_STATE_READY)
03297   {
03298     /* Wait until BUSY flag is reset */
03299     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
03300     {
03301       return HAL_BUSY;
03302     }
03303
03304     /* Process Locked */
03305     __HAL_LOCK(hi2c);
03306
03307     /* Check if the I2C is already enabled */
03308     if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
03309     {
03310       /* Enable I2C peripheral */
03311       __HAL_I2C_ENABLE(hi2c);
03312     }
03313
03314     /* Disable Pos */
03315     hi2c->Instance->CR1 &= ~I2C_CR1_POS;
03316
03317     hi2c->State = HAL_I2C_STATE_BUSY;
03318     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
03319     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
03320
03321     do
03322     {
03323       /* Generate Start */
03324       hi2c->Instance->CR1 |= I2C_CR1_START;
03325
03326       /* Wait until SB flag is set */
03327       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
03328       {
03329         return HAL_TIMEOUT;
03330       }
03331
03332       /* Send slave address */
03333       hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
03334
03335       /* Wait until ADDR or AF flag are set */
03336       /* Get tick */
03337       tickstart = HAL_GetTick();
03338
03339       tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
03340       tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03341       tmp3 = hi2c->State;
03342       while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
03343       {
03344         if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
03345         {
03346           hi2c->State = HAL_I2C_STATE_TIMEOUT;
03347         }
03348         tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
03349         tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
03350         tmp3 = hi2c->State;
03351       }
03352
03353       hi2c->State = HAL_I2C_STATE_READY;
03354
03355       /* Check if the ADDR flag has been set */
03356       if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
03357       {
03358         /* Generate Stop */
03359         hi2c->Instance->CR1 |= I2C_CR1_STOP;
03360
03361         /* Clear ADDR Flag */
03362         __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
03363
03364         /* Wait until BUSY flag is reset */
03365         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
03366         {
03367           return HAL_TIMEOUT;
03368         }
03369
03370         hi2c->State = HAL_I2C_STATE_READY;
03371
03372         /* Process Unlocked */
03373         __HAL_UNLOCK(hi2c);
03374
03375         return HAL_OK;
03376       }
03377       else
03378       {
03379         /* Generate Stop */
03380         hi2c->Instance->CR1 |= I2C_CR1_STOP;
03381
03382         /* Clear AF Flag */
03383         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03384
03385         /* Wait until BUSY flag is reset */
03386         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
03387         {
03388           return HAL_TIMEOUT;
03389         }
03390       }
03391     }while(I2C_Trials++ < Trials);
03392
03393     hi2c->State = HAL_I2C_STATE_READY;
03394
03395     /* Process Unlocked */
03396     __HAL_UNLOCK(hi2c);
03397
03398     return HAL_ERROR;
03399   }
03400   else
03401   {
03402     return HAL_BUSY;
03403   }
03404 }
03405
03406 /**
03407   * @brief  This function handles I2C event interrupt request.
03408   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03409   *                the configuration information for the specified I2C.
03410   * @retval None
03411   */
03412 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
03413 {
03414   uint32_t sr2itflags   = READ_REG(hi2c->Instance->SR2);
03415   uint32_t sr1itflags   = READ_REG(hi2c->Instance->SR1);
03416   uint32_t itsources    = READ_REG(hi2c->Instance->CR2);
03417
03418   uint32_t CurrentMode  = hi2c->Mode;
03419
03420   /* Master or Memory mode selected */
03421   if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
03422   {
03423     /* SB Set ----------------------------------------------------------------*/
03424     if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
03425     {
03426       I2C_Master_SB(hi2c);
03427     }
03428     /* ADD10 Set -------------------------------------------------------------*/
03429     else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
03430     {
03431       I2C_Master_ADD10(hi2c);
03432     }
03433     /* ADDR Set --------------------------------------------------------------*/
03434     else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
03435     {
03436       I2C_Master_ADDR(hi2c);
03437     }
03438
03439     /* I2C in mode Transmitter -----------------------------------------------*/
03440     if((sr2itflags & I2C_FLAG_TRA) != RESET)
03441     {
03442       /* TXE set and BTF reset -----------------------------------------------*/
03443       if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
03444       {
03445         I2C_MasterTransmit_TXE(hi2c);
03446       }
03447       /* BTF set -------------------------------------------------------------*/
03448       else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
03449       {
03450         I2C_MasterTransmit_BTF(hi2c);
03451       }
03452     }
03453     /* I2C in mode Receiver --------------------------------------------------*/
03454     else
03455     {
03456       /* RXNE set and BTF reset -----------------------------------------------*/
03457       if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
03458       {
03459         I2C_MasterReceive_RXNE(hi2c);
03460       }
03461       /* BTF set -------------------------------------------------------------*/
03462       else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
03463       {
03464         I2C_MasterReceive_BTF(hi2c);
03465       }
03466     }
03467   }
03468   /* Slave mode selected */
03469   else
03470   {
03471     /* ADDR set --------------------------------------------------------------*/
03472     if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
03473     {
03474       I2C_Slave_ADDR(hi2c);
03475     }
03476     /* STOPF set --------------------------------------------------------------*/
03477     else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
03478     {
03479       I2C_Slave_STOPF(hi2c);
03480     }
03481     /* I2C in mode Transmitter -----------------------------------------------*/
03482     else if((sr2itflags & I2C_FLAG_TRA) != RESET)
03483     {
03484       /* TXE set and BTF reset -----------------------------------------------*/
03485       if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
03486       {
03487         I2C_SlaveTransmit_TXE(hi2c);
03488       }
03489       /* BTF set -------------------------------------------------------------*/
03490       else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
03491       {
03492         I2C_SlaveTransmit_BTF(hi2c);
03493       }
03494     }
03495     /* I2C in mode Receiver --------------------------------------------------*/
03496     else
03497     {
03498       /* RXNE set and BTF reset ----------------------------------------------*/
03499       if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
03500       {
03501         I2C_SlaveReceive_RXNE(hi2c);
03502       }
03503       /* BTF set -------------------------------------------------------------*/
03504       else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
03505       {
03506         I2C_SlaveReceive_BTF(hi2c);
03507       }
03508     }
03509   }
03510 }
03511
03512 /**
03513   * @brief  This function handles I2C error interrupt request.
03514   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03515   *                the configuration information for the specified I2C.
03516   * @retval None
03517   */
03518 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
03519 {
03520   uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
03521   uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
03522   uint32_t itsources  = READ_REG(hi2c->Instance->CR2);
03523
03524   /* I2C Bus error interrupt occurred ----------------------------------------*/
03525   if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
03526   {
03527     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
03528
03529     /* Clear BERR flag */
03530     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
03531
03532     /* Workaround: Start cannot be generated after a misplaced Stop */
03533     SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST);
03534   }
03535
03536   /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
03537   if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
03538   {
03539     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
03540
03541     /* Clear ARLO flag */
03542     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
03543   }
03544
03545   /* I2C Acknowledge failure error interrupt occurred ------------------------*/
03546   if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
03547   {
03548     tmp1 = hi2c->Mode;
03549     tmp2 = hi2c->XferCount;
03550     tmp3 = hi2c->State;
03551     tmp4 = hi2c->PreviousState;
03552     if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
03553       ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
03554       ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
03555     {
03556       I2C_Slave_AF(hi2c);
03557     }
03558     else
03559     {
03560       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03561
03562       /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
03563       if(hi2c->Mode == HAL_I2C_MODE_MASTER)
03564       {
03565         /* Generate Stop */
03566         SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
03567       }
03568
03569       /* Clear AF flag */
03570       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03571     }
03572   }
03573
03574   /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
03575   if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
03576   {
03577     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
03578     /* Clear OVR flag */
03579     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
03580   }
03581
03582   /* Call the Error Callback in case of Error detected -----------------------*/
03583   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
03584   {
03585     I2C_ITError(hi2c);
03586   }
03587 }
03588
03589 /**
03590   * @brief  Master Tx Transfer completed callback.
03591   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03592   *                the configuration information for the specified I2C.
03593   * @retval None
03594   */
03595 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
03596 {
03597   /* Prevent unused argument(s) compilation warning */
03598   UNUSED(hi2c);
03599
03600   /* NOTE : This function should not be modified, when the callback is needed,
03601             the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
03602    */
03603 }
03604
03605 /**
03606   * @brief  Master Rx Transfer completed callback.
03607   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03608   *                the configuration information for the specified I2C.
03609   * @retval None
03610   */
03611 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
03612 {
03613   /* Prevent unused argument(s) compilation warning */
03614   UNUSED(hi2c);
03615
03616   /* NOTE : This function should not be modified, when the callback is needed,
03617             the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
03618    */
03619 }
03620
03621 /** @brief  Slave Tx Transfer completed callback.
03622   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03623   *                the configuration information for the specified I2C.
03624   * @retval None
03625   */
03626 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
03627 {
03628   /* Prevent unused argument(s) compilation warning */
03629   UNUSED(hi2c);
03630
03631   /* NOTE : This function should not be modified, when the callback is needed,
03632             the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
03633    */
03634 }
03635
03636 /**
03637   * @brief  Slave Rx Transfer completed callback.
03638   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03639   *                the configuration information for the specified I2C.
03640   * @retval None
03641   */
03642 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
03643 {
03644   /* Prevent unused argument(s) compilation warning */
03645   UNUSED(hi2c);
03646
03647   /* NOTE : This function should not be modified, when the callback is needed,
03648             the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
03649    */
03650 }
03651
03652 /**
03653   * @brief  Slave Address Match callback.
03654   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03655   *                the configuration information for the specified I2C.
03656   * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
03657   * @param  AddrMatchCode Address Match Code
03658   * @retval None
03659   */
03660 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
03661 {
03662   /* Prevent unused argument(s) compilation warning */
03663   UNUSED(hi2c);
03664   UNUSED(TransferDirection);
03665   UNUSED(AddrMatchCode);
03666
03667   /* NOTE : This function should not be modified, when the callback is needed,
03668             the HAL_I2C_AddrCallback can be implemented in the user file
03669    */
03670 }
03671
03672 /**
03673   * @brief  Listen Complete callback.
03674   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03675   *                the configuration information for the specified I2C.
03676   * @retval None
03677   */
03678 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
03679 {
03680   /* Prevent unused argument(s) compilation warning */
03681   UNUSED(hi2c);
03682
03683     /* NOTE : This function should not be modified, when the callback is needed,
03684             the HAL_I2C_ListenCpltCallback can be implemented in the user file
03685    */
03686 }
03687
03688 /**
03689   * @brief  Memory Tx Transfer completed callback.
03690   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03691   *                the configuration information for the specified I2C.
03692   * @retval None
03693   */
03694 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
03695 {
03696   /* Prevent unused argument(s) compilation warning */
03697   UNUSED(hi2c);
03698
03699   /* NOTE : This function should not be modified, when the callback is needed,
03700             the HAL_I2C_MemTxCpltCallback can be implemented in the user file
03701    */
03702 }
03703
03704 /**
03705   * @brief  Memory Rx Transfer completed callback.
03706   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03707   *                the configuration information for the specified I2C.
03708   * @retval None
03709   */
03710 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
03711 {
03712   /* Prevent unused argument(s) compilation warning */
03713   UNUSED(hi2c);
03714
03715   /* NOTE : This function should not be modified, when the callback is needed,
03716             the HAL_I2C_MemRxCpltCallback can be implemented in the user file
03717    */
03718 }
03719
03720 /**
03721   * @brief  I2C error callback.
03722   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03723   *                the configuration information for the specified I2C.
03724   * @retval None
03725   */
03726 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
03727 {
03728   /* Prevent unused argument(s) compilation warning */
03729   UNUSED(hi2c);
03730
03731   /* NOTE : This function should not be modified, when the callback is needed,
03732             the HAL_I2C_ErrorCallback can be implemented in the user file
03733    */
03734 }
03735
03736 /**
03737   * @brief  I2C abort callback.
03738   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03739   *                the configuration information for the specified I2C.
03740   * @retval None
03741   */
03742 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
03743 {
03744   /* Prevent unused argument(s) compilation warning */
03745   UNUSED(hi2c);
03746
03747   /* NOTE : This function should not be modified, when the callback is needed,
03748             the HAL_I2C_AbortCpltCallback could be implemented in the user file
03749    */
03750 }
03751
03752 /**
03753   * @}
03754   */
03755
03756 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
03757   *  @brief   Peripheral State and Errors functions
03758   *
03759 @verbatim
03760  ===============================================================================
03761             ##### Peripheral State, Mode and Error functions #####
03762  ===============================================================================
03763     [..]
03764     This subsection permits to get in run-time the status of the peripheral
03765     and the data flow.
03766
03767 @endverbatim
03768   * @{
03769   */
03770
03771 /**
03772   * @brief  Return the I2C handle state.
03773   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03774   *                the configuration information for the specified I2C.
03775   * @retval HAL state
03776   */
03777 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
03778 {
03779   /* Return I2C handle state */
03780   return hi2c->State;
03781 }
03782
03783 /**
03784   * @brief  Return the I2C Master, Slave, Memory or no mode.
03785   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03786   *         the configuration information for I2C module
03787   * @retval HAL mode
03788   */
03789 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
03790 {
03791   return hi2c->Mode;
03792 }
03793
03794 /**
03795   * @brief  Return the I2C error code
03796   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03797   *              the configuration information for the specified I2C.
03798   * @retval I2C Error Code
03799   */
03800 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
03801 {
03802   return hi2c->ErrorCode;
03803 }
03804
03805 /**
03806   * @}
03807   */
03808
03809 /**
03810   * @brief  Handle TXE flag for Master
03811   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03812   *         the configuration information for I2C module
03813   * @retval HAL status
03814   */
03815 static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
03816 {
03817   /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
03818   uint32_t CurrentState       = hi2c->State;
03819   uint32_t CurrentMode        = hi2c->Mode;
03820   uint32_t CurrentXferOptions = hi2c->XferOptions;
03821
03822   if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
03823   {
03824     /* Call TxCpltCallback() directly if no stop mode is set */
03825     if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
03826     {
03827       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
03828
03829       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
03830       hi2c->Mode = HAL_I2C_MODE_NONE;
03831       hi2c->State = HAL_I2C_STATE_READY;
03832
03833       HAL_I2C_MasterTxCpltCallback(hi2c);
03834     }
03835     else /* Generate Stop condition then Call TxCpltCallback() */
03836     {
03837       /* Disable EVT, BUF and ERR interrupt */
03838       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
03839
03840       /* Generate Stop */
03841       hi2c->Instance->CR1 |= I2C_CR1_STOP;
03842
03843       hi2c->PreviousState = I2C_STATE_NONE;
03844       hi2c->State = HAL_I2C_STATE_READY;
03845
03846       if(hi2c->Mode == HAL_I2C_MODE_MEM)
03847       {
03848         hi2c->Mode = HAL_I2C_MODE_NONE;
03849         HAL_I2C_MemTxCpltCallback(hi2c);
03850       }
03851       else
03852       {
03853         hi2c->Mode = HAL_I2C_MODE_NONE;
03854         HAL_I2C_MasterTxCpltCallback(hi2c);
03855       }
03856     }
03857   }
03858   else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
03859     ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
03860   {
03861     if(hi2c->XferCount == 0U)
03862     {
03863       /* Disable BUF interrupt */
03864       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
03865     }
03866     else
03867     {
03868       if(hi2c->Mode == HAL_I2C_MODE_MEM)
03869       {
03870         if(hi2c->EventCount == 0)
03871         {
03872           /* If Memory address size is 8Bit */
03873           if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
03874           {
03875             /* Send Memory Address */
03876             hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
03877
03878             hi2c->EventCount += 2;
03879           }
03880           /* If Memory address size is 16Bit */
03881           else
03882           {
03883             /* Send MSB of Memory Address */
03884             hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
03885
03886             hi2c->EventCount++;
03887           }
03888         }
03889         else if(hi2c->EventCount == 1)
03890         {
03891           /* Send LSB of Memory Address */
03892           hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
03893
03894           hi2c->EventCount++;
03895         }
03896         else if(hi2c->EventCount == 2)
03897         {
03898           if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
03899           {
03900             /* Generate Restart */
03901             hi2c->Instance->CR1 |= I2C_CR1_START;
03902           }
03903           else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
03904           {
03905             /* Write data to DR */
03906             hi2c->Instance->DR = (*hi2c->pBuffPtr++);
03907             hi2c->XferCount--;
03908           }
03909         }
03910       }
03911       else
03912       {
03913         /* Write data to DR */
03914         hi2c->Instance->DR = (*hi2c->pBuffPtr++);
03915         hi2c->XferCount--;
03916       }
03917     }
03918   }
03919   return HAL_OK;
03920 }
03921
03922 /**
03923   * @brief  Handle BTF flag for Master transmitter
03924   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03925   *         the configuration information for I2C module
03926   * @retval HAL status
03927   */
03928 static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
03929 {
03930   /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
03931   uint32_t CurrentXferOptions = hi2c->XferOptions;
03932
03933   if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
03934   {
03935     if(hi2c->XferCount != 0U)
03936     {
03937       /* Write data to DR */
03938       hi2c->Instance->DR = (*hi2c->pBuffPtr++);
03939       hi2c->XferCount--;
03940     }
03941     else
03942     {
03943       /* Call TxCpltCallback() directly if no stop mode is set */
03944       if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
03945       {
03946         __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
03947
03948         hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
03949         hi2c->Mode = HAL_I2C_MODE_NONE;
03950         hi2c->State = HAL_I2C_STATE_READY;
03951
03952         HAL_I2C_MasterTxCpltCallback(hi2c);
03953       }
03954       else /* Generate Stop condition then Call TxCpltCallback() */
03955       {
03956         /* Disable EVT, BUF and ERR interrupt */
03957         __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
03958
03959         /* Generate Stop */
03960         hi2c->Instance->CR1 |= I2C_CR1_STOP;
03961
03962         hi2c->PreviousState = I2C_STATE_NONE;
03963         hi2c->State = HAL_I2C_STATE_READY;
03964
03965         if(hi2c->Mode == HAL_I2C_MODE_MEM)
03966         {
03967           hi2c->Mode = HAL_I2C_MODE_NONE;
03968
03969           HAL_I2C_MemTxCpltCallback(hi2c);
03970         }
03971         else
03972         {
03973           hi2c->Mode = HAL_I2C_MODE_NONE;
03974
03975           HAL_I2C_MasterTxCpltCallback(hi2c);
03976         }
03977       }
03978     }
03979   }
03980   return HAL_OK;
03981 }
03982
03983 /**
03984   * @brief  Handle RXNE flag for Master
03985   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03986   *         the configuration information for I2C module
03987   * @retval HAL status
03988   */
03989 static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
03990 {
03991   if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
03992   {
03993     uint32_t tmp = 0U;
03994
03995     tmp = hi2c->XferCount;
03996     if(tmp > 3U)
03997     {
03998       /* Read data from DR */
03999       (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04000       hi2c->XferCount--;
04001     }
04002     else if((tmp == 2U) || (tmp == 3U))
04003     {
04004       if(hi2c->XferOptions != I2C_NEXT_FRAME)
04005       {
04006         /* Disable Acknowledge */
04007         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04008
04009         /* Enable Pos */
04010         hi2c->Instance->CR1 |= I2C_CR1_POS;
04011       }
04012       else
04013       {
04014         /* Enable Acknowledge */
04015         hi2c->Instance->CR1 |= I2C_CR1_ACK;
04016       }
04017
04018       /* Disable BUF interrupt */
04019       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
04020     }
04021     else
04022     {
04023       if(hi2c->XferOptions != I2C_NEXT_FRAME)
04024       {
04025         /* Disable Acknowledge */
04026         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04027       }
04028       else
04029       {
04030         /* Enable Acknowledge */
04031         hi2c->Instance->CR1 |= I2C_CR1_ACK;
04032       }
04033
04034       /* Disable EVT, BUF and ERR interrupt */
04035       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
04036
04037       /* Read data from DR */
04038       (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04039       hi2c->XferCount--;
04040
04041       hi2c->State = HAL_I2C_STATE_READY;
04042
04043       if(hi2c->Mode == HAL_I2C_MODE_MEM)
04044       {
04045         hi2c->PreviousState = I2C_STATE_NONE;
04046         hi2c->Mode = HAL_I2C_MODE_NONE;
04047         HAL_I2C_MemRxCpltCallback(hi2c);
04048       }
04049       else
04050       {
04051         hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
04052         hi2c->Mode = HAL_I2C_MODE_NONE;
04053         HAL_I2C_MasterRxCpltCallback(hi2c);
04054       }
04055     }
04056   }
04057   return HAL_OK;
04058 }
04059
04060 /**
04061   * @brief  Handle BTF flag for Master receiver
04062   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04063   *         the configuration information for I2C module
04064   * @retval HAL status
04065   */
04066 static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
04067 {
04068   /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
04069   uint32_t CurrentXferOptions = hi2c->XferOptions;
04070
04071   if(hi2c->XferCount == 3U)
04072   {
04073     if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
04074     {
04075       /* Disable Acknowledge */
04076       hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04077     }
04078
04079     /* Read data from DR */
04080     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04081     hi2c->XferCount--;
04082   }
04083   else if(hi2c->XferCount == 2U)
04084   {
04085     /* Prepare next transfer or stop current transfer */
04086     if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
04087     {
04088       if(CurrentXferOptions != I2C_NEXT_FRAME)
04089       {
04090         /* Disable Acknowledge */
04091         hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04092       }
04093       else
04094       {
04095         /* Enable Acknowledge */
04096         hi2c->Instance->CR1 |= I2C_CR1_ACK;
04097       }
04098
04099       /* Disable EVT and ERR interrupt */
04100       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
04101     }
04102     else
04103     {
04104       /* Disable EVT and ERR interrupt */
04105       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
04106
04107       /* Generate Stop */
04108       hi2c->Instance->CR1 |= I2C_CR1_STOP;
04109     }
04110
04111     /* Read data from DR */
04112     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04113     hi2c->XferCount--;
04114
04115     /* Read data from DR */
04116     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04117     hi2c->XferCount--;
04118
04119     hi2c->State = HAL_I2C_STATE_READY;
04120
04121     if(hi2c->Mode == HAL_I2C_MODE_MEM)
04122     {
04123       hi2c->PreviousState = I2C_STATE_NONE;
04124       hi2c->Mode = HAL_I2C_MODE_NONE;
04125
04126       HAL_I2C_MemRxCpltCallback(hi2c);
04127     }
04128     else
04129     {
04130       hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
04131       hi2c->Mode = HAL_I2C_MODE_NONE;
04132
04133       HAL_I2C_MasterRxCpltCallback(hi2c);
04134     }
04135   }
04136   else
04137   {
04138     /* Read data from DR */
04139     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04140     hi2c->XferCount--;
04141   }
04142   return HAL_OK;
04143 }
04144
04145 /**
04146   * @brief  Handle SB flag for Master
04147   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04148   *         the configuration information for I2C module
04149   * @retval HAL status
04150   */
04151 static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
04152 {
04153   if(hi2c->Mode == HAL_I2C_MODE_MEM)
04154   {
04155     if(hi2c->EventCount == 0U)
04156     {
04157       /* Send slave address */
04158       hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
04159     }
04160     else
04161     {
04162       hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
04163     }
04164   }
04165   else
04166   {
04167     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
04168     {
04169       /* Send slave 7 Bits address */
04170       if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
04171       {
04172         hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
04173       }
04174       else
04175       {
04176         hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
04177       }
04178     }
04179     else
04180     {
04181       if(hi2c->EventCount == 0U)
04182       {
04183         /* Send header of slave address */
04184         hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
04185       }
04186       else if(hi2c->EventCount == 1U)
04187       {
04188         /* Send header of slave address */
04189         hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
04190       }
04191     }
04192   }
04193
04194   return HAL_OK;
04195 }
04196
04197 /**
04198   * @brief  Handle ADD10 flag for Master
04199   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04200   *         the configuration information for I2C module
04201   * @retval HAL status
04202   */
04203 static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
04204 {
04205   /* Send slave address */
04206   hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
04207
04208   return HAL_OK;
04209 }
04210
04211 /**
04212   * @brief  Handle ADDR flag for Master
04213   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04214   *         the configuration information for I2C module
04215   * @retval HAL status
04216   */
04217 static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
04218 {
04219   /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
04220   uint32_t CurrentMode        = hi2c->Mode;
04221   uint32_t CurrentXferOptions = hi2c->XferOptions;
04222   uint32_t Prev_State         = hi2c->PreviousState;
04223
04224   if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
04225   {
04226     if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
04227     {
04228       /* Clear ADDR flag */
04229       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04230     }
04231     else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
04232     {
04233       /* Clear ADDR flag */
04234       __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04235
04236       /* Generate Restart */
04237       hi2c->Instance->CR1 |= I2C_CR1_START;
04238
04239       hi2c->EventCount++;
04240     }
04241     else
04242     {
04243       if(hi2c->XferCount == 0U)
04244       {
04245         /* Clear ADDR flag */
04246         __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04247
04248         /* Generate Stop */
04249         hi2c->Instance->CR1 |= I2C_CR1_STOP;
04250       }
04251       else if(hi2c->XferCount == 1U)
04252       {
04253         if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
04254         {
04255           /* Disable Acknowledge */
04256             hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04257
04258           if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
04259           {
04260             /* Disable Acknowledge */
04261             hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04262
04263             /* Clear ADDR flag */
04264             __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04265           }
04266           else
04267           {
04268             /* Clear ADDR flag */
04269             __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04270
04271             /* Generate Stop */
04272             hi2c->Instance->CR1 |= I2C_CR1_STOP;
04273           }
04274         }
04275         /* Prepare next transfer or stop current transfer */
04276         else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
04277           && (Prev_State != I2C_STATE_MASTER_BUSY_RX))
04278         {
04279           if(hi2c->XferOptions != I2C_NEXT_FRAME)
04280           {
04281             /* Disable Acknowledge */
04282             hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04283           }
04284           else
04285           {
04286             /* Enable Acknowledge */
04287             hi2c->Instance->CR1 |= I2C_CR1_ACK;
04288           }
04289
04290           /* Clear ADDR flag */
04291           __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04292         }
04293         else
04294         {
04295           /* Disable Acknowledge */
04296           hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04297
04298           /* Clear ADDR flag */
04299           __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04300
04301           /* Generate Stop */
04302           hi2c->Instance->CR1 |= I2C_CR1_STOP;
04303         }
04304       }
04305       else if(hi2c->XferCount == 2U)
04306       {
04307         if(hi2c->XferOptions != I2C_NEXT_FRAME)
04308         {
04309           /* Enable Pos */
04310           hi2c->Instance->CR1 |= I2C_CR1_POS;
04311
04312           /* Clear ADDR flag */
04313           __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04314
04315           /* Disable Acknowledge */
04316           hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04317         }
04318         else
04319         {
04320           /* Enable Acknowledge */
04321           hi2c->Instance->CR1 |= I2C_CR1_ACK;
04322
04323           /* Clear ADDR flag */
04324           __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04325         }
04326
04327         if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
04328         {
04329           /* Enable Last DMA bit */
04330           hi2c->Instance->CR2 |= I2C_CR2_LAST;
04331         }
04332       }
04333       else
04334       {
04335         /* Enable Acknowledge */
04336         hi2c->Instance->CR1 |= I2C_CR1_ACK;
04337
04338         if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
04339         {
04340           /* Enable Last DMA bit */
04341           hi2c->Instance->CR2 |= I2C_CR2_LAST;
04342         }
04343
04344         /* Clear ADDR flag */
04345         __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04346       }
04347
04348       /* Reset Event counter  */
04349       hi2c->EventCount = 0U;
04350     }
04351   }
04352   else
04353   {
04354     /* Clear ADDR flag */
04355     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04356   }
04357
04358   return HAL_OK;
04359 }
04360
04361 /**
04362   * @brief  Handle TXE flag for Slave
04363   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04364   *         the configuration information for I2C module
04365   * @retval HAL status
04366   */
04367 static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
04368 {
04369   /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
04370   uint32_t CurrentState = hi2c->State;
04371
04372   if(hi2c->XferCount != 0U)
04373   {
04374     /* Write data to DR */
04375     hi2c->Instance->DR = (*hi2c->pBuffPtr++);
04376     hi2c->XferCount--;
04377
04378     if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
04379     {
04380       /* Last Byte is received, disable Interrupt */
04381       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
04382
04383       /* Set state at HAL_I2C_STATE_LISTEN */
04384       hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
04385       hi2c->State = HAL_I2C_STATE_LISTEN;
04386
04387       /* Call the Tx complete callback to inform upper layer of the end of receive process */
04388       HAL_I2C_SlaveTxCpltCallback(hi2c);
04389     }
04390   }
04391   return HAL_OK;
04392 }
04393
04394 /**
04395   * @brief  Handle BTF flag for Slave transmitter
04396   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04397   *         the configuration information for I2C module
04398   * @retval HAL status
04399   */
04400 static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
04401 {
04402   if(hi2c->XferCount != 0U)
04403   {
04404     /* Write data to DR */
04405     hi2c->Instance->DR = (*hi2c->pBuffPtr++);
04406     hi2c->XferCount--;
04407   }
04408   return HAL_OK;
04409 }
04410
04411 /**
04412   * @brief  Handle RXNE flag for Slave
04413   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04414   *         the configuration information for I2C module
04415   * @retval HAL status
04416   */
04417 static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
04418 {
04419   /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
04420   uint32_t CurrentState = hi2c->State;
04421
04422   if(hi2c->XferCount != 0U)
04423   {
04424     /* Read data from DR */
04425     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04426     hi2c->XferCount--;
04427
04428     if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
04429     {
04430       /* Last Byte is received, disable Interrupt */
04431       __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
04432
04433       /* Set state at HAL_I2C_STATE_LISTEN */
04434       hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
04435       hi2c->State = HAL_I2C_STATE_LISTEN;
04436
04437       /* Call the Rx complete callback to inform upper layer of the end of receive process */
04438       HAL_I2C_SlaveRxCpltCallback(hi2c);
04439     }
04440   }
04441   return HAL_OK;
04442 }
04443
04444 /**
04445   * @brief  Handle BTF flag for Slave receiver
04446   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04447   *         the configuration information for I2C module
04448   * @retval HAL status
04449   */
04450 static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
04451 {
04452   if(hi2c->XferCount != 0U)
04453   {
04454     /* Read data from DR */
04455     (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04456     hi2c->XferCount--;
04457   }
04458   return HAL_OK;
04459 }
04460
04461 /**
04462   * @brief  Handle ADD flag for Slave
04463   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04464   *         the configuration information for I2C module
04465   * @retval HAL status
04466   */
04467 static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
04468 {
04469   uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
04470   uint16_t SlaveAddrCode = 0U;
04471
04472   /* Transfer Direction requested by Master */
04473   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
04474   {
04475     TransferDirection = I2C_DIRECTION_TRANSMIT;
04476   }
04477
04478   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
04479   {
04480     SlaveAddrCode = hi2c->Init.OwnAddress1;
04481   }
04482   else
04483   {
04484     SlaveAddrCode = hi2c->Init.OwnAddress2;
04485   }
04486
04487   /* Call Slave Addr callback */
04488   HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
04489
04490   return HAL_OK;
04491 }
04492
04493 /**
04494   * @brief  Handle STOPF flag for Slave
04495   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04496   *         the configuration information for I2C module
04497   * @retval HAL status
04498   */
04499 static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
04500 {
04501   /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
04502   uint32_t CurrentState = hi2c->State;
04503
04504   /* Disable EVT, BUF and ERR interrupt */
04505   __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
04506
04507   /* Clear STOPF flag */
04508   __HAL_I2C_CLEAR_STOPFLAG(hi2c);
04509
04510   /* Disable Acknowledge */
04511   hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04512
04513   /* If a DMA is ongoing, Update handle size context */
04514   if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
04515   {
04516     if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
04517     {
04518       hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
04519     }
04520     else
04521     {
04522       hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
04523     }
04524   }
04525
04526   /* All data are not transferred, so set error code accordingly */
04527   if(hi2c->XferCount != 0U)
04528   {
04529     /* Store Last receive data if any */
04530     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
04531     {
04532       /* Read data from DR */
04533       (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04534       hi2c->XferCount--;
04535     }
04536
04537     /* Store Last receive data if any */
04538     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
04539     {
04540       /* Read data from DR */
04541       (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04542       hi2c->XferCount--;
04543     }
04544
04545     /* Set ErrorCode corresponding to a Non-Acknowledge */
04546     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04547   }
04548
04549   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04550   {
04551     /* Call the corresponding callback to inform upper layer of End of Transfer */
04552     I2C_ITError(hi2c);
04553   }
04554   else
04555   {
04556     if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
04557        (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
04558     {
04559       hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04560       hi2c->PreviousState = I2C_STATE_NONE;
04561       hi2c->State = HAL_I2C_STATE_READY;
04562       hi2c->Mode = HAL_I2C_MODE_NONE;
04563
04564       /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04565       HAL_I2C_ListenCpltCallback(hi2c);
04566     }
04567     else
04568     {
04569       if((hi2c->PreviousState  == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
04570       {
04571         hi2c->PreviousState = I2C_STATE_NONE;
04572         hi2c->State = HAL_I2C_STATE_READY;
04573         hi2c->Mode = HAL_I2C_MODE_NONE;
04574
04575         HAL_I2C_SlaveRxCpltCallback(hi2c);
04576       }
04577     }
04578   }
04579   return HAL_OK;
04580 }
04581
04582 /**
04583   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04584   *         the configuration information for I2C module
04585   * @retval HAL status
04586   */
04587 static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
04588 {
04589   /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
04590   uint32_t CurrentState       = hi2c->State;
04591   uint32_t CurrentXferOptions = hi2c->XferOptions;
04592
04593   if(((CurrentXferOptions ==  I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
04594           (CurrentState == HAL_I2C_STATE_LISTEN))
04595   {
04596     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04597
04598     /* Disable EVT, BUF and ERR interrupt */
04599     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
04600
04601     /* Clear AF flag */
04602     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04603
04604     /* Disable Acknowledge */
04605     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04606
04607     hi2c->PreviousState = I2C_STATE_NONE;
04608     hi2c->State = HAL_I2C_STATE_READY;
04609     hi2c->Mode = HAL_I2C_MODE_NONE;
04610
04611     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04612     HAL_I2C_ListenCpltCallback(hi2c);
04613   }
04614   else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
04615   {
04616     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04617     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
04618     hi2c->State = HAL_I2C_STATE_READY;
04619     hi2c->Mode = HAL_I2C_MODE_NONE;
04620
04621     /* Disable EVT, BUF and ERR interrupt */
04622     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
04623
04624     /* Clear AF flag */
04625     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04626
04627     /* Disable Acknowledge */
04628     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
04629
04630     HAL_I2C_SlaveTxCpltCallback(hi2c);
04631   }
04632   else
04633   {
04634     /* Clear AF flag only */
04635     /* State Listen, but XferOptions == FIRST or NEXT */
04636     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04637   }
04638
04639   return HAL_OK;
04640 }
04641
04642 /**
04643   * @brief  I2C interrupts error process
04644   * @param  hi2c I2C handle.
04645   * @retval None
04646   */
04647 static void I2C_ITError(I2C_HandleTypeDef *hi2c)
04648 {
04649   /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
04650   uint32_t CurrentState = hi2c->State;
04651
04652   if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
04653   {
04654     /* keep HAL_I2C_STATE_LISTEN */
04655     hi2c->PreviousState = I2C_STATE_NONE;
04656     hi2c->State = HAL_I2C_STATE_LISTEN;
04657   }
04658   else
04659   {
04660     /* If state is an abort treatment on going, don't change state */
04661     /* This change will be do later */
04662     if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
04663     {
04664       hi2c->State = HAL_I2C_STATE_READY;
04665     }
04666     hi2c->PreviousState = I2C_STATE_NONE;
04667     hi2c->Mode = HAL_I2C_MODE_NONE;
04668   }
04669
04670   /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
04671   hi2c->Instance->CR1 &= ~I2C_CR1_POS;
04672
04673   /* Abort DMA transfer */
04674   if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
04675   {
04676     hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
04677
04678     if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
04679     {
04680       /* Set the DMA Abort callback :
04681       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04682       hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04683
04684       if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04685       {
04686         /* Disable I2C peripheral to prevent dummy data in buffer */
04687         __HAL_I2C_DISABLE(hi2c);
04688
04689         hi2c->State = HAL_I2C_STATE_READY;
04690
04691         /* Call Directly XferAbortCallback function in case of error */
04692         hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04693       }
04694     }
04695     else
04696     {
04697       /* Set the DMA Abort callback :
04698       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04699       hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
04700
04701       if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
04702       {
04703         /* Store Last receive data if any */
04704         if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
04705         {
04706           /* Read data from DR */
04707           (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04708         }
04709
04710         /* Disable I2C peripheral to prevent dummy data in buffer */
04711         __HAL_I2C_DISABLE(hi2c);
04712
04713         hi2c->State = HAL_I2C_STATE_READY;
04714
04715         /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
04716         hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
04717       }
04718     }
04719   }
04720   else if(hi2c->State == HAL_I2C_STATE_ABORT)
04721   {
04722     hi2c->State = HAL_I2C_STATE_READY;
04723     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04724
04725     /* Store Last receive data if any */
04726     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
04727     {
04728       /* Read data from DR */
04729       (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04730     }
04731
04732     /* Disable I2C peripheral to prevent dummy data in buffer */
04733     __HAL_I2C_DISABLE(hi2c);
04734
04735     /* Call the corresponding callback to inform upper layer of End of Transfer */
04736     HAL_I2C_AbortCpltCallback(hi2c);
04737   }
04738   else
04739   {
04740     /* Store Last receive data if any */
04741     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
04742     {
04743       /* Read data from DR */
04744       (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
04745     }
04746
04747     /* Call user error callback */
04748     HAL_I2C_ErrorCallback(hi2c);
04749   }
04750   /* STOP Flag is not set after a NACK reception */
04751   /* So may inform upper layer that listen phase is stopped */
04752   /* during NACK error treatment */
04753   if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
04754   {
04755     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04756     hi2c->PreviousState = I2C_STATE_NONE;
04757     hi2c->State = HAL_I2C_STATE_READY;
04758     hi2c->Mode = HAL_I2C_MODE_NONE;
04759
04760     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04761     HAL_I2C_ListenCpltCallback(hi2c);
04762   }
04763 }
04764
04765 /**
04766   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04767   *         the configuration information for I2C module
04768   * @param  DevAddress Target device address: The device 7 bits address value
04769   *         in datasheet must be shift at right before call interface
04770   * @param  Timeout Timeout duration
04771   * @param  Tickstart Tick start value
04772   * @retval HAL status
04773   */
04774 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
04775 {
04776   /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
04777   uint32_t CurrentXferOptions = hi2c->XferOptions;
04778
04779   /* Generate Start condition if first transfer */
04780   if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
04781   {
04782     /* Generate Start */
04783     hi2c->Instance->CR1 |= I2C_CR1_START;
04784   }
04785   else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
04786   {
04787     /* Generate ReStart */
04788     hi2c->Instance->CR1 |= I2C_CR1_START;
04789   }
04790
04791   /* Wait until SB flag is set */
04792   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
04793   {
04794     return HAL_TIMEOUT;
04795   }
04796
04797   if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
04798   {
04799     /* Send slave address */
04800     hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
04801   }
04802   else
04803   {
04804     /* Send header of slave address */
04805     hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
04806
04807     /* Wait until ADD10 flag is set */
04808     if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
04809     {
04810       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04811       {
04812         return HAL_ERROR;
04813       }
04814       else
04815       {
04816         return HAL_TIMEOUT;
04817       }
04818     }
04819
04820     /* Send slave address */
04821     hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
04822   }
04823
04824   /* Wait until ADDR flag is set */
04825   if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
04826   {
04827     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04828     {
04829       return HAL_ERROR;
04830     }
04831     else
04832     {
04833       return HAL_TIMEOUT;
04834     }
04835   }
04836
04837   return HAL_OK;
04838 }
04839
04840 /**
04841   * @brief  Master sends target device address for read request.
04842   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04843   *         the configuration information for I2C module
04844   * @param  DevAddress Target device address: The device 7 bits address value
04845   *         in datasheet must be shift at right before call interface
04846   * @param  Timeout Timeout duration
04847   * @param  Tickstart Tick start value
04848   * @retval HAL status
04849   */
04850 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
04851 {
04852   /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
04853   uint32_t CurrentXferOptions = hi2c->XferOptions;
04854
04855   /* Enable Acknowledge */
04856   hi2c->Instance->CR1 |= I2C_CR1_ACK;
04857
04858   /* Generate Start condition if first transfer */
04859   if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)  || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
04860   {
04861     /* Generate Start */
04862     hi2c->Instance->CR1 |= I2C_CR1_START;
04863   }
04864   else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
04865   {
04866     /* Generate ReStart */
04867     hi2c->Instance->CR1 |= I2C_CR1_START;
04868   }
04869
04870   /* Wait until SB flag is set */
04871   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
04872   {
04873     return HAL_TIMEOUT;
04874   }
04875
04876   if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
04877   {
04878     /* Send slave address */
04879     hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
04880   }
04881   else
04882   {
04883     /* Send header of slave address */
04884     hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
04885
04886     /* Wait until ADD10 flag is set */
04887     if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
04888     {
04889       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04890       {
04891         return HAL_ERROR;
04892       }
04893       else
04894       {
04895         return HAL_TIMEOUT;
04896       }
04897     }
04898
04899     /* Send slave address */
04900     hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
04901
04902     /* Wait until ADDR flag is set */
04903     if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
04904     {
04905       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04906       {
04907         return HAL_ERROR;
04908       }
04909       else
04910       {
04911         return HAL_TIMEOUT;
04912       }
04913     }
04914
04915     /* Clear ADDR flag */
04916     __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04917
04918     /* Generate Restart */
04919     hi2c->Instance->CR1 |= I2C_CR1_START;
04920
04921     /* Wait until SB flag is set */
04922     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
04923     {
04924       return HAL_TIMEOUT;
04925     }
04926
04927     /* Send header of slave address */
04928     hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
04929   }
04930
04931   /* Wait until ADDR flag is set */
04932   if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
04933   {
04934     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04935     {
04936       return HAL_ERROR;
04937     }
04938     else
04939     {
04940       return HAL_TIMEOUT;
04941     }
04942   }
04943
04944   return HAL_OK;
04945 }
04946
04947 /**
04948   * @brief  Master sends target device address followed by internal memory address for write request.
04949   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04950   *         the configuration information for I2C module
04951   * @param  DevAddress Target device address
04952   * @param  MemAddress Internal memory address
04953   * @param  MemAddSize Size of internal memory address
04954   * @param  Timeout Timeout duration
04955   * @param  Tickstart Tick start value
04956   * @retval HAL status
04957   */
04958 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
04959 {
04960   /* Generate Start */
04961   hi2c->Instance->CR1 |= I2C_CR1_START;
04962
04963   /* Wait until SB flag is set */
04964   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
04965   {
04966     return HAL_TIMEOUT;
04967   }
04968
04969   /* Send slave address */
04970   hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
04971
04972   /* Wait until ADDR flag is set */
04973   if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
04974   {
04975     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04976     {
04977       return HAL_ERROR;
04978     }
04979     else
04980     {
04981       return HAL_TIMEOUT;
04982     }
04983   }
04984
04985   /* Clear ADDR flag */
04986   __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
04987
04988   /* Wait until TXE flag is set */
04989   if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
04990   {
04991     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
04992     {
04993       /* Generate Stop */
04994       hi2c->Instance->CR1 |= I2C_CR1_STOP;
04995       return HAL_ERROR;
04996     }
04997     else
04998     {
04999       return HAL_TIMEOUT;
05000     }
05001   }
05002
05003   /* If Memory address size is 8Bit */
05004   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
05005   {
05006     /* Send Memory Address */
05007     hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
05008   }
05009   /* If Memory address size is 16Bit */
05010   else
05011   {
05012     /* Send MSB of Memory Address */
05013     hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
05014
05015     /* Wait until TXE flag is set */
05016     if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05017     {
05018       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
05019       {
05020         /* Generate Stop */
05021         hi2c->Instance->CR1 |= I2C_CR1_STOP;
05022         return HAL_ERROR;
05023       }
05024       else
05025       {
05026         return HAL_TIMEOUT;
05027       }
05028     }
05029
05030     /* Send LSB of Memory Address */
05031     hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
05032   }
05033
05034   return HAL_OK;
05035 }
05036
05037 /**
05038   * @brief  Master sends target device address followed by internal memory address for read request.
05039   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05040   *         the configuration information for I2C module
05041   * @param  DevAddress Target device address
05042   * @param  MemAddress Internal memory address
05043   * @param  MemAddSize Size of internal memory address
05044   * @param  Timeout Timeout duration
05045   * @param  Tickstart Tick start value
05046   * @retval HAL status
05047   */
05048 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
05049 {
05050   /* Enable Acknowledge */
05051   hi2c->Instance->CR1 |= I2C_CR1_ACK;
05052
05053   /* Generate Start */
05054   hi2c->Instance->CR1 |= I2C_CR1_START;
05055
05056   /* Wait until SB flag is set */
05057   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
05058   {
05059     return HAL_TIMEOUT;
05060   }
05061
05062   /* Send slave address */
05063   hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
05064
05065   /* Wait until ADDR flag is set */
05066   if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
05067   {
05068     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
05069     {
05070       return HAL_ERROR;
05071     }
05072     else
05073     {
05074       return HAL_TIMEOUT;
05075     }
05076   }
05077
05078   /* Clear ADDR flag */
05079   __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
05080
05081   /* Wait until TXE flag is set */
05082   if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05083   {
05084     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
05085     {
05086       /* Generate Stop */
05087       hi2c->Instance->CR1 |= I2C_CR1_STOP;
05088       return HAL_ERROR;
05089     }
05090     else
05091     {
05092       return HAL_TIMEOUT;
05093     }
05094   }
05095
05096   /* If Memory address size is 8Bit */
05097   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
05098   {
05099     /* Send Memory Address */
05100     hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
05101   }
05102   /* If Memory address size is 16Bit */
05103   else
05104   {
05105     /* Send MSB of Memory Address */
05106     hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
05107
05108     /* Wait until TXE flag is set */
05109     if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05110     {
05111       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
05112       {
05113         /* Generate Stop */
05114         hi2c->Instance->CR1 |= I2C_CR1_STOP;
05115         return HAL_ERROR;
05116       }
05117       else
05118       {
05119         return HAL_TIMEOUT;
05120       }
05121     }
05122
05123     /* Send LSB of Memory Address */
05124     hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
05125   }
05126
05127   /* Wait until TXE flag is set */
05128   if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
05129   {
05130     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
05131     {
05132       /* Generate Stop */
05133       hi2c->Instance->CR1 |= I2C_CR1_STOP;
05134       return HAL_ERROR;
05135     }
05136     else
05137     {
05138       return HAL_TIMEOUT;
05139     }
05140   }
05141
05142   /* Generate Restart */
05143   hi2c->Instance->CR1 |= I2C_CR1_START;
05144
05145   /* Wait until SB flag is set */
05146   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
05147   {
05148     return HAL_TIMEOUT;
05149   }
05150
05151   /* Send slave address */
05152   hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
05153
05154   /* Wait until ADDR flag is set */
05155   if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
05156   {
05157     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
05158     {
05159       return HAL_ERROR;
05160     }
05161     else
05162     {
05163       return HAL_TIMEOUT;
05164     }
05165   }
05166
05167   return HAL_OK;
05168 }
05169
05170 /**
05171   * @brief  DMA I2C process complete callback.
05172   * @param  hdma DMA handle
05173   * @retval None
05174   */
05175 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
05176 {
05177   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
05178
05179   /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
05180   uint32_t CurrentState = hi2c->State;
05181   uint32_t CurrentMode  = hi2c->Mode;
05182
05183   if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
05184   {
05185     /* Disable DMA Request */
05186     hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
05187
05188     hi2c->XferCount = 0U;
05189
05190     /* Enable EVT and ERR interrupt */
05191     __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
05192   }
05193   else
05194   {
05195     /* Disable Acknowledge */
05196     hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
05197
05198     /* Generate Stop */
05199     hi2c->Instance->CR1 |= I2C_CR1_STOP;
05200
05201     /* Disable Last DMA */
05202     hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
05203
05204     /* Disable DMA Request */
05205     hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
05206
05207     hi2c->XferCount = 0U;
05208
05209     /* Check if Errors has been detected during transfer */
05210     if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
05211     {
05212       HAL_I2C_ErrorCallback(hi2c);
05213     }
05214     else
05215     {
05216       hi2c->State = HAL_I2C_STATE_READY;
05217
05218       if(hi2c->Mode == HAL_I2C_MODE_MEM)
05219       {
05220         hi2c->Mode = HAL_I2C_MODE_NONE;
05221
05222         HAL_I2C_MemRxCpltCallback(hi2c);
05223       }
05224       else
05225       {
05226         hi2c->Mode = HAL_I2C_MODE_NONE;
05227
05228         HAL_I2C_MasterRxCpltCallback(hi2c);
05229       }
05230     }
05231   }
05232 }
05233
05234 /**
05235   * @brief  DMA I2C communication error callback.
05236   * @param  hdma DMA handle
05237   * @retval None
05238   */
05239 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
05240 {
05241   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
05242
05243   /* Disable Acknowledge */
05244   hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
05245
05246   hi2c->XferCount = 0U;
05247
05248   hi2c->State = HAL_I2C_STATE_READY;
05249   hi2c->Mode = HAL_I2C_MODE_NONE;
05250
05251   hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
05252
05253     HAL_I2C_ErrorCallback(hi2c);
05254 }
05255
05256 /**
05257   * @brief DMA I2C communication abort callback
05258   *        (To be called at end of DMA Abort procedure).
05259   * @param hdma: DMA handle.
05260   * @retval None
05261   */
05262 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
05263 {
05264   I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
05265
05266   /* Disable Acknowledge */
05267   hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
05268
05269   hi2c->XferCount = 0U;
05270
05271   /* Reset XferAbortCallback */
05272   hi2c->hdmatx->XferAbortCallback = NULL;
05273   hi2c->hdmarx->XferAbortCallback = NULL;
05274
05275   /* Check if come from abort from user */
05276   if(hi2c->State == HAL_I2C_STATE_ABORT)
05277   {
05278     hi2c->State = HAL_I2C_STATE_READY;
05279     hi2c->Mode = HAL_I2C_MODE_NONE;
05280     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
05281
05282     /* Disable I2C peripheral to prevent dummy data in buffer */
05283     __HAL_I2C_DISABLE(hi2c);
05284
05285     /* Call the corresponding callback to inform upper layer of End of Transfer */
05286     HAL_I2C_AbortCpltCallback(hi2c);
05287   }
05288   else
05289   {
05290     hi2c->State = HAL_I2C_STATE_READY;
05291     hi2c->Mode = HAL_I2C_MODE_NONE;
05292
05293     /* Disable I2C peripheral to prevent dummy data in buffer */
05294     __HAL_I2C_DISABLE(hi2c);
05295
05296     /* Call the corresponding callback to inform upper layer of End of Transfer */
05297     HAL_I2C_ErrorCallback(hi2c);
05298   }
05299 }
05300
05301 /**
05302   * @brief  This function handles I2C Communication Timeout.
05303   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05304   *         the configuration information for I2C module
05305   * @param  Flag specifies the I2C flag to check.
05306   * @param  Status The new Flag status (SET or RESET).
05307   * @param  Timeout Timeout duration
05308   * @param  Tickstart Tick start value
05309   * @retval HAL status
05310   */
05311 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
05312 {
05313   /* Wait until flag is set */
05314   while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
05315   {
05316     /* Check for the Timeout */
05317     if(Timeout != HAL_MAX_DELAY)
05318     {
05319       if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
05320       {
05321         hi2c->PreviousState = I2C_STATE_NONE;
05322         hi2c->State= HAL_I2C_STATE_READY;
05323         hi2c->Mode = HAL_I2C_MODE_NONE;
05324
05325         /* Process Unlocked */
05326         __HAL_UNLOCK(hi2c);
05327
05328         return HAL_TIMEOUT;
05329       }
05330     }
05331   }
05332
05333   return HAL_OK;
05334 }
05335
05336 /**
05337   * @brief  This function handles I2C Communication Timeout for Master addressing phase.
05338   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05339   *         the configuration information for I2C module
05340   * @param  Flag specifies the I2C flag to check.
05341   * @param  Timeout Timeout duration
05342   * @param  Tickstart Tick start value
05343   * @retval HAL status
05344   */
05345 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
05346 {
05347   while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
05348   {
05349     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
05350     {
05351       /* Generate Stop */
05352       hi2c->Instance->CR1 |= I2C_CR1_STOP;
05353
05354       /* Clear AF Flag */
05355       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05356
05357       hi2c->ErrorCode = HAL_I2C_ERROR_AF;
05358       hi2c->PreviousState = I2C_STATE_NONE;
05359       hi2c->State= HAL_I2C_STATE_READY;
05360
05361       /* Process Unlocked */
05362       __HAL_UNLOCK(hi2c);
05363
05364       return HAL_ERROR;
05365     }
05366
05367     /* Check for the Timeout */
05368     if(Timeout != HAL_MAX_DELAY)
05369     {
05370       if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
05371       {
05372         hi2c->PreviousState = I2C_STATE_NONE;
05373         hi2c->State= HAL_I2C_STATE_READY;
05374
05375         /* Process Unlocked */
05376         __HAL_UNLOCK(hi2c);
05377
05378         return HAL_TIMEOUT;
05379       }
05380     }
05381   }
05382   return HAL_OK;
05383 }
05384
05385 /**
05386   * @brief  This function handles I2C Communication Timeout for specific usage of TXE flag.
05387   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05388   *                the configuration information for the specified I2C.
05389   * @param  Timeout Timeout duration
05390   * @param  Tickstart Tick start value
05391   * @retval HAL status
05392   */
05393 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
05394 {
05395   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
05396   {
05397     /* Check if a NACK is detected */
05398     if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
05399     {
05400       return HAL_ERROR;
05401     }
05402
05403     /* Check for the Timeout */
05404     if(Timeout != HAL_MAX_DELAY)
05405     {
05406       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
05407       {
05408         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
05409         hi2c->PreviousState = I2C_STATE_NONE;
05410         hi2c->State= HAL_I2C_STATE_READY;
05411
05412         /* Process Unlocked */
05413         __HAL_UNLOCK(hi2c);
05414
05415         return HAL_TIMEOUT;
05416       }
05417     }
05418   }
05419   return HAL_OK;
05420 }
05421
05422 /**
05423   * @brief  This function handles I2C Communication Timeout for specific usage of BTF flag.
05424   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05425   *                the configuration information for the specified I2C.
05426   * @param  Timeout Timeout duration
05427   * @param  Tickstart Tick start value
05428   * @retval HAL status
05429   */
05430 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
05431 {
05432   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
05433   {
05434     /* Check if a NACK is detected */
05435     if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
05436     {
05437       return HAL_ERROR;
05438     }
05439
05440     /* Check for the Timeout */
05441     if(Timeout != HAL_MAX_DELAY)
05442     {
05443       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
05444       {
05445         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
05446         hi2c->PreviousState = I2C_STATE_NONE;
05447         hi2c->State= HAL_I2C_STATE_READY;
05448
05449         /* Process Unlocked */
05450         __HAL_UNLOCK(hi2c);
05451
05452         return HAL_TIMEOUT;
05453       }
05454     }
05455   }
05456   return HAL_OK;
05457 }
05458
05459 /**
05460   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
05461   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05462   *                the configuration information for the specified I2C.
05463   * @param  Timeout Timeout duration
05464   * @param  Tickstart Tick start value
05465   * @retval HAL status
05466   */
05467 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
05468 {
05469   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
05470   {
05471     /* Check if a NACK is detected */
05472     if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
05473     {
05474       return HAL_ERROR;
05475     }
05476
05477     /* Check for the Timeout */
05478     if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
05479     {
05480       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
05481       hi2c->PreviousState = I2C_STATE_NONE;
05482       hi2c->State= HAL_I2C_STATE_READY;
05483
05484       /* Process Unlocked */
05485       __HAL_UNLOCK(hi2c);
05486
05487       return HAL_TIMEOUT;
05488     }
05489   }
05490   return HAL_OK;
05491 }
05492
05493 /**
05494   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
05495   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05496   *                the configuration information for the specified I2C.
05497   * @param  Timeout Timeout duration
05498   * @param  Tickstart Tick start value
05499   * @retval HAL status
05500   */
05501 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
05502 {
05503
05504   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
05505   {
05506     /* Check if a STOPF is detected */
05507     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
05508     {
05509       /* Clear STOP Flag */
05510       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
05511
05512       hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
05513       hi2c->PreviousState = I2C_STATE_NONE;
05514       hi2c->State= HAL_I2C_STATE_READY;
05515
05516       /* Process Unlocked */
05517       __HAL_UNLOCK(hi2c);
05518
05519       return HAL_ERROR;
05520     }
05521
05522     /* Check for the Timeout */
05523     if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
05524     {
05525       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
05526       hi2c->State= HAL_I2C_STATE_READY;
05527
05528       /* Process Unlocked */
05529       __HAL_UNLOCK(hi2c);
05530
05531       return HAL_TIMEOUT;
05532     }
05533   }
05534   return HAL_OK;
05535 }
05536
05537 /**
05538   * @brief  This function handles Acknowledge failed detection during an I2C Communication.
05539   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
05540   *                the configuration information for the specified I2C.
05541   * @retval HAL status
05542   */
05543 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
05544 {
05545   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
05546   {
05547     /* Clear NACKF Flag */
05548     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
05549
05550     hi2c->ErrorCode = HAL_I2C_ERROR_AF;
05551     hi2c->PreviousState = I2C_STATE_NONE;
05552     hi2c->State= HAL_I2C_STATE_READY;
05553
05554     /* Process Unlocked */
05555     __HAL_UNLOCK(hi2c);
05556
05557     return HAL_ERROR;
05558   }
05559   return HAL_OK;
05560 }
05561 /**
05562   * @}
05563   */
05564
05565 #endif /* HAL_I2C_MODULE_ENABLED */
05566
05567 /**
05568   * @}
05569   */
05570
05571 /**
05572   * @}
05573   */
05574
05575 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_i2c.h Source File

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stm32f1xx_hal_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_i2c.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of I2C HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_I2C_H
00040 #define __STM32F1xx_HAL_I2C_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup I2C
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup I2C_Exported_Types I2C Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  I2C Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t ClockSpeed;       /*!< Specifies the clock frequency.
00068                                   This parameter must be set to a value lower than 400kHz */
00069
00070   uint32_t DutyCycle;        /*!< Specifies the I2C fast mode duty cycle.
00071                                   This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
00072
00073   uint32_t OwnAddress1;      /*!< Specifies the first device own address.
00074                                   This parameter can be a 7-bit or 10-bit address. */
00075
00076   uint32_t AddressingMode;   /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
00077                                   This parameter can be a value of @ref I2C_addressing_mode */
00078
00079   uint32_t DualAddressMode;  /*!< Specifies if dual addressing mode is selected.
00080                                   This parameter can be a value of @ref I2C_dual_addressing_mode */
00081
00082   uint32_t OwnAddress2;      /*!< Specifies the second device own address if dual addressing mode is selected
00083                                   This parameter can be a 7-bit address. */
00084
00085   uint32_t GeneralCallMode;  /*!< Specifies if general call mode is selected.
00086                                   This parameter can be a value of @ref I2C_general_call_addressing_mode */
00087
00088   uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
00089                                   This parameter can be a value of @ref I2C_nostretch_mode */
00090
00091 }I2C_InitTypeDef;
00092
00093 /**
00094   * @brief  HAL State structure definition
00095   * @note  HAL I2C State value coding follow below described bitmap :
00096   *          b7-b6  Error information
00097   *             00 : No Error
00098   *             01 : Abort (Abort user request on going)
00099   *             10 : Timeout
00100   *             11 : Error
00101   *          b5     IP initilisation status
00102   *             0  : Reset (IP not initialized)
00103   *             1  : Init done (IP initialized and ready to use. HAL I2C Init function called)
00104   *          b4     (not used)
00105   *             x  : Should be set to 0
00106   *          b3
00107   *             0  : Ready or Busy (No Listen mode ongoing)
00108   *             1  : Listen (IP in Address Listen Mode)
00109   *          b2     Intrinsic process state
00110   *             0  : Ready
00111   *             1  : Busy (IP busy with some configuration or internal operations)
00112   *          b1     Rx state
00113   *             0  : Ready (no Rx operation ongoing)
00114   *             1  : Busy (Rx operation ongoing)
00115   *          b0     Tx state
00116   *             0  : Ready (no Tx operation ongoing)
00117   *             1  : Busy (Tx operation ongoing)
00118   */
00119 typedef enum
00120 {
00121   HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
00122   HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
00123   HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
00124   HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
00125   HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
00126   HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
00127   HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
00128                                                  process is ongoing                         */
00129   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
00130                                                  process is ongoing                         */
00131   HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
00132   HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
00133   HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
00134
00135 }HAL_I2C_StateTypeDef;
00136
00137 /**
00138   * @brief  HAL Mode structure definition
00139   * @note  HAL I2C Mode value coding follow below described bitmap :
00140   *          b7     (not used)
00141   *             x  : Should be set to 0
00142   *          b6
00143   *             0  : None
00144   *             1  : Memory (HAL I2C communication is in Memory Mode)
00145   *          b5
00146   *             0  : None
00147   *             1  : Slave (HAL I2C communication is in Slave Mode)
00148   *          b4
00149   *             0  : None
00150   *             1  : Master (HAL I2C communication is in Master Mode)
00151   *          b3-b2-b1-b0  (not used)
00152   *             xxxx : Should be set to 0000
00153   */
00154 typedef enum
00155 {
00156   HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
00157   HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
00158   HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
00159   HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
00160
00161 }HAL_I2C_ModeTypeDef;
00162
00163 /**
00164   * @brief  I2C handle Structure definition
00165   */
00166 typedef struct
00167 {
00168   I2C_TypeDef                *Instance;      /*!< I2C registers base address               */
00169
00170   I2C_InitTypeDef            Init;           /*!< I2C communication parameters             */
00171
00172   uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer           */
00173
00174   uint16_t                   XferSize;       /*!< I2C transfer size                        */
00175
00176   __IO uint16_t              XferCount;      /*!< I2C transfer counter                     */
00177
00178   __IO uint32_t              XferOptions;    /*!< I2C transfer options                     */
00179
00180   __IO uint32_t              PreviousState;  /*!< I2C communication Previous state and mode
00181                                                   context for internal usage               */
00182
00183   DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters             */
00184
00185   DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters             */
00186
00187   HAL_LockTypeDef            Lock;           /*!< I2C locking object                       */
00188
00189   __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                  */
00190
00191   __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                   */
00192
00193   __IO uint32_t              ErrorCode;      /*!< I2C Error code                           */
00194
00195   __IO uint32_t              Devaddress;     /*!< I2C Target device address                */
00196
00197   __IO uint32_t              Memaddress;     /*!< I2C Target memory address                */
00198
00199   __IO uint32_t              MemaddSize;     /*!< I2C Target memory address  size          */
00200
00201   __IO uint32_t              EventCount;     /*!< I2C Event counter                        */
00202
00203 }I2C_HandleTypeDef;
00204
00205 /**
00206   * @}
00207   */
00208
00209 /* Exported constants --------------------------------------------------------*/
00210 /** @defgroup I2C_Exported_Constants I2C Exported Constants
00211   * @{
00212   */
00213
00214 /** @defgroup I2C_Error_Code I2C Error Code
00215   * @brief    I2C Error Code
00216   * @{
00217   */
00218 #define HAL_I2C_ERROR_NONE       0x00000000U    /*!< No error           */
00219 #define HAL_I2C_ERROR_BERR       0x00000001U    /*!< BERR error         */
00220 #define HAL_I2C_ERROR_ARLO       0x00000002U    /*!< ARLO error         */
00221 #define HAL_I2C_ERROR_AF         0x00000004U    /*!< AF error           */
00222 #define HAL_I2C_ERROR_OVR        0x00000008U    /*!< OVR error          */
00223 #define HAL_I2C_ERROR_DMA        0x00000010U    /*!< DMA transfer error */
00224 #define HAL_I2C_ERROR_TIMEOUT    0x00000020U    /*!< Timeout Error      */
00225 /**
00226   * @}
00227   */
00228
00229 /** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
00230   * @{
00231   */
00232 #define I2C_DUTYCYCLE_2                 0x00000000U
00233 #define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
00234 /**
00235   * @}
00236   */
00237
00238 /** @defgroup I2C_addressing_mode I2C addressing mode
00239   * @{
00240   */
00241 #define I2C_ADDRESSINGMODE_7BIT         0x00004000U
00242 #define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | 0x00004000U)
00243 /**
00244   * @}
00245   */
00246
00247 /** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
00248   * @{
00249   */
00250 #define I2C_DUALADDRESS_DISABLE        0x00000000U
00251 #define I2C_DUALADDRESS_ENABLE         I2C_OAR2_ENDUAL
00252 /**
00253   * @}
00254   */
00255
00256 /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
00257   * @{
00258   */
00259 #define I2C_GENERALCALL_DISABLE        0x00000000U
00260 #define I2C_GENERALCALL_ENABLE         I2C_CR1_ENGC
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup I2C_nostretch_mode I2C nostretch mode
00266   * @{
00267   */
00268 #define I2C_NOSTRETCH_DISABLE          0x00000000U
00269 #define I2C_NOSTRETCH_ENABLE           I2C_CR1_NOSTRETCH
00270 /**
00271   * @}
00272   */
00273
00274 /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
00275   * @{
00276   */
00277 #define I2C_MEMADD_SIZE_8BIT            0x00000001U
00278 #define I2C_MEMADD_SIZE_16BIT           0x00000010U
00279 /**
00280   * @}
00281   */
00282
00283 /** @defgroup I2C_XferDirection_definition I2C XferDirection definition
00284   * @{
00285   */
00286 #define I2C_DIRECTION_RECEIVE           0x00000000U
00287 #define I2C_DIRECTION_TRANSMIT          0x00000001U
00288 /**
00289   * @}
00290   */
00291
00292 /** @defgroup I2C_XferOptions_definition I2C XferOptions definition
00293   * @{
00294   */
00295 #define  I2C_FIRST_FRAME                0x00000001U
00296 #define  I2C_NEXT_FRAME                 0x00000002U
00297 #define  I2C_FIRST_AND_LAST_FRAME       0x00000004U
00298 #define  I2C_LAST_FRAME                 0x00000008U
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
00304   * @{
00305   */
00306 #define I2C_IT_BUF                      I2C_CR2_ITBUFEN
00307 #define I2C_IT_EVT                      I2C_CR2_ITEVTEN
00308 #define I2C_IT_ERR                      I2C_CR2_ITERREN
00309 /**
00310   * @}
00311   */
00312
00313 /** @defgroup I2C_Flag_definition I2C Flag definition
00314   * @{
00315   */
00316 #define I2C_FLAG_SMBALERT               0x00018000U
00317 #define I2C_FLAG_TIMEOUT                0x00014000U
00318 #define I2C_FLAG_PECERR                 0x00011000U
00319 #define I2C_FLAG_OVR                    0x00010800U
00320 #define I2C_FLAG_AF                     0x00010400U
00321 #define I2C_FLAG_ARLO                   0x00010200U
00322 #define I2C_FLAG_BERR                   0x00010100U
00323 #define I2C_FLAG_TXE                    0x00010080U
00324 #define I2C_FLAG_RXNE                   0x00010040U
00325 #define I2C_FLAG_STOPF                  0x00010010U
00326 #define I2C_FLAG_ADD10                  0x00010008U
00327 #define I2C_FLAG_BTF                    0x00010004U
00328 #define I2C_FLAG_ADDR                   0x00010002U
00329 #define I2C_FLAG_SB                     0x00010001U
00330 #define I2C_FLAG_DUALF                  0x00100080U
00331 #define I2C_FLAG_SMBHOST                0x00100040U
00332 #define I2C_FLAG_SMBDEFAULT             0x00100020U
00333 #define I2C_FLAG_GENCALL                0x00100010U
00334 #define I2C_FLAG_TRA                    0x00100004U
00335 #define I2C_FLAG_BUSY                   0x00100002U
00336 #define I2C_FLAG_MSL                    0x00100001U
00337 /**
00338   * @}
00339   */
00340
00341 /**
00342   * @}
00343   */
00344
00345 /* Exported macro ------------------------------------------------------------*/
00346 /** @defgroup I2C_Exported_Macros I2C Exported Macros
00347   * @{
00348   */
00349
00350 /** @brief Reset I2C handle state
00351   * @param  __HANDLE__: specifies the I2C Handle.
00352   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00353   * @retval None
00354   */
00355 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
00356
00357 /** @brief  Enable or disable the specified I2C interrupts.
00358   * @param  __HANDLE__: specifies the I2C Handle.
00359   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00360   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00361   *         This parameter can be one of the following values:
00362   *            @arg I2C_IT_BUF: Buffer interrupt enable
00363   *            @arg I2C_IT_EVT: Event interrupt enable
00364   *            @arg I2C_IT_ERR: Error interrupt enable
00365   * @retval None
00366   */
00367 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
00368 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
00369
00370 /** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
00371   * @param  __HANDLE__: specifies the I2C Handle.
00372   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00373   * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
00374   *          This parameter can be one of the following values:
00375   *            @arg I2C_IT_BUF: Buffer interrupt enable
00376   *            @arg I2C_IT_EVT: Event interrupt enable
00377   *            @arg I2C_IT_ERR: Error interrupt enable
00378   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00379   */
00380 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00381
00382 /** @brief  Checks whether the specified I2C flag is set or not.
00383   * @param  __HANDLE__: specifies the I2C Handle.
00384   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00385   * @param  __FLAG__: specifies the flag to check.
00386   *         This parameter can be one of the following values:
00387   *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
00388   *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
00389   *            @arg I2C_FLAG_PECERR: PEC error in reception flag
00390   *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
00391   *            @arg I2C_FLAG_AF: Acknowledge failure flag
00392   *            @arg I2C_FLAG_ARLO: Arbitration lost flag
00393   *            @arg I2C_FLAG_BERR: Bus error flag
00394   *            @arg I2C_FLAG_TXE: Data register empty flag
00395   *            @arg I2C_FLAG_RXNE: Data register not empty flag
00396   *            @arg I2C_FLAG_STOPF: Stop detection flag
00397   *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
00398   *            @arg I2C_FLAG_BTF: Byte transfer finished flag
00399   *            @arg I2C_FLAG_ADDR: Address sent flag
00400   *                                Address matched flag
00401   *            @arg I2C_FLAG_SB: Start bit flag
00402   *            @arg I2C_FLAG_DUALF: Dual flag
00403   *            @arg I2C_FLAG_SMBHOST: SMBus host header
00404   *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header
00405   *            @arg I2C_FLAG_GENCALL: General call header flag
00406   *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
00407   *            @arg I2C_FLAG_BUSY: Bus busy flag
00408   *            @arg I2C_FLAG_MSL: Master/Slave flag
00409   * @retval The new state of __FLAG__ (TRUE or FALSE).
00410   */
00411 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
00412                                                  ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
00413
00414 /** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
00415   * @param  __HANDLE__: specifies the I2C Handle.
00416   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00417   * @param  __FLAG__: specifies the flag to clear.
00418   *         This parameter can be any combination of the following values:
00419   *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
00420   *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
00421   *            @arg I2C_FLAG_PECERR: PEC error in reception flag
00422   *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
00423   *            @arg I2C_FLAG_AF: Acknowledge failure flag
00424   *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
00425   *            @arg I2C_FLAG_BERR: Bus error flag
00426   * @retval None
00427   */
00428 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
00429
00430 /** @brief  Clears the I2C ADDR pending flag.
00431   * @param  __HANDLE__: specifies the I2C Handle.
00432   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00433   * @retval None
00434   */
00435 #define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)    \
00436   do{                                           \
00437     __IO uint32_t tmpreg = 0x00U;               \
00438     tmpreg = (__HANDLE__)->Instance->SR1;       \
00439     tmpreg = (__HANDLE__)->Instance->SR2;       \
00440     UNUSED(tmpreg);                             \
00441   } while(0U)
00442
00443 /** @brief  Clears the I2C STOPF pending flag.
00444   * @param  __HANDLE__: specifies the I2C Handle.
00445   *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
00446   * @retval None
00447   */
00448 #define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)    \
00449   do{                                           \
00450     __IO uint32_t tmpreg = 0x00U;               \
00451     tmpreg = (__HANDLE__)->Instance->SR1;       \
00452     (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;  \
00453     UNUSED(tmpreg);                             \
00454   } while(0U)
00455
00456 /** @brief  Enable the I2C peripheral.
00457   * @param  __HANDLE__: specifies the I2C Handle.
00458   *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
00459   * @retval None
00460   */
00461 #define __HAL_I2C_ENABLE(__HANDLE__)                             ((__HANDLE__)->Instance->CR1 |=  I2C_CR1_PE)
00462
00463 /** @brief  Disable the I2C peripheral.
00464   * @param  __HANDLE__: specifies the I2C Handle.
00465   *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
00466   * @retval None
00467   */
00468 #define __HAL_I2C_DISABLE(__HANDLE__)                            ((__HANDLE__)->Instance->CR1 &=  ~I2C_CR1_PE)
00469
00470 /**
00471   * @}
00472   */
00473
00474 /* Exported functions --------------------------------------------------------*/
00475 /** @addtogroup I2C_Exported_Functions
00476   * @{
00477   */
00478
00479 /** @addtogroup I2C_Exported_Functions_Group1
00480   * @{
00481   */
00482 /* Initialization/de-initialization functions  **********************************/
00483 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
00484 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
00485 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
00486 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
00487 /**
00488   * @}
00489   */
00490
00491 /** @addtogroup I2C_Exported_Functions_Group2
00492   * @{
00493   */
00494 /* I/O operation functions  *****************************************************/
00495 /******* Blocking mode: Polling */
00496 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00497 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00498 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00499 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00500 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00501 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00502 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
00503
00504 /******* Non-Blocking mode: Interrupt */
00505 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00506 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00507 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00508 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00509 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00510 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00511
00512 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00513 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00514 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00515 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
00516 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
00517 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
00518 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
00519
00520 /******* Non-Blocking mode: DMA */
00521 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00522 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
00523 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00524 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
00525 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00526 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
00527
00528 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
00529 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
00530 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
00531 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
00532 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
00533 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
00534 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
00535 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
00536 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
00537 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
00538 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
00539 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
00540 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
00541 /**
00542   * @}
00543   */
00544
00545 /** @addtogroup I2C_Exported_Functions_Group3
00546   * @{
00547   */
00548 /* Peripheral State, Mode and Errors functions  *********************************/
00549 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
00550 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
00551 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
00552
00553 /**
00554   * @}
00555   */
00556
00557 /**
00558   * @}
00559   */
00560 /* Private types -------------------------------------------------------------*/
00561 /* Private variables ---------------------------------------------------------*/
00562 /* Private constants ---------------------------------------------------------*/
00563 /** @defgroup I2C_Private_Constants I2C Private Constants
00564   * @{
00565   */
00566 #define I2C_FLAG_MASK  0x0000FFFFU
00567 /**
00568   * @}
00569   */
00570
00571 /* Private macros ------------------------------------------------------------*/
00572 /** @defgroup I2C_Private_Macros I2C Private Macros
00573   * @{
00574   */
00575
00576 #define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000U)
00577 #define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
00578 #define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
00579 #define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
00580 #define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
00581                                                                   ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
00582                                                                   ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
00583
00584 #define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
00585 #define I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
00586
00587 #define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00588 #define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
00589 #define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
00590
00591 #define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
00592 #define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
00593
00594 /** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
00595   * @{
00596   */
00597 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
00598                                   ((CYCLE) == I2C_DUTYCYCLE_16_9))
00599 #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
00600                                          ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
00601 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
00602                                       ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
00603 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
00604                                    ((CALL) == I2C_GENERALCALL_ENABLE))
00605 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
00606                                     ((STRETCH) == I2C_NOSTRETCH_ENABLE))
00607 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
00608                                   ((SIZE) == I2C_MEMADD_SIZE_16BIT))
00609 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
00610 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
00611 #define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
00612 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == I2C_FIRST_FRAME)              || \
00613                                                        ((REQUEST) == I2C_NEXT_FRAME)               || \
00614                                                        ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \
00615                                                        ((REQUEST) == I2C_LAST_FRAME))
00616 /**
00617   * @}
00618   */
00619
00620 /**
00621   * @}
00622   */
00623
00624 /* Private functions ---------------------------------------------------------*/
00625 /** @defgroup I2C_Private_Functions I2C Private Functions
00626   * @{
00627   */
00628
00629 /**
00630   * @}
00631   */
00632
00633 /**
00634   * @}
00635   */
00636
00637 /**
00638   * @}
00639   */
00640
00641 #ifdef __cplusplus
00642 }
00643 #endif
00644
00645
00646 #endif /* __STM32F1xx_HAL_I2C_H */
00647
00648 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_i2s.c Source File

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stm32f1xx_hal_i2s.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_i2s.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   I2S HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and Errors functions
00013   @verbatim
00014  ===============================================================================
00015                   ##### How to use this driver #####
00016  ===============================================================================
00017  [..]
00018     The I2S HAL driver can be used as follow:
00019
00020     (#) Declare a I2S_HandleTypeDef handle structure.
00021     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
00022         (##) Enable the SPIx interface clock.
00023         (##) I2S pins configuration:
00024             (+++) Enable the clock for the I2S GPIOs.
00025             (+++) Configure these I2S pins as alternate function.
00026         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
00027              and HAL_I2S_Receive_IT() APIs).
00028             (+++) Configure the I2Sx interrupt priority.
00029             (+++) Enable the NVIC I2S IRQ handle.
00030         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
00031              and HAL_I2S_Receive_DMA() APIs:
00032             (+++) Declare a DMA handle structure for the Tx/Rx Channel.
00033             (+++) Enable the DMAx interface clock.
00034             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00035             (+++) Configure the DMA Tx/Rx Channel.
00036             (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
00037             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
00038                   DMA Tx/Rx Channel.
00039
00040    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
00041        using HAL_I2S_Init() function.
00042
00043    -@- The specific I2S interrupts (Transmission complete interrupt,
00044        RXNE interrupt and Error Interrupts) will be managed using the macros
00045        __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
00046    -@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock).
00047        For connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO (2 x PLL3CLK) clock
00048        in order to achieve the maximum accuracy.
00049    -@- Make sure that either:
00050        (+@) External clock source is configured after setting correctly
00051             the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file.
00052
00053    (#) Three operation modes are available within this driver :
00054
00055    *** Polling mode IO operation ***
00056    =================================
00057    [..]
00058      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
00059      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
00060
00061    *** Interrupt mode IO operation ***
00062    ===================================
00063    [..]
00064      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
00065      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00066          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00067      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00068          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00069      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
00070      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00071          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00072      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00073          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00074      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00075          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00076
00077    *** DMA mode IO operation ***
00078    ==============================
00079    [..]
00080      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
00081      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
00082          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
00083      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
00084          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
00085      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
00086      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
00087          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
00088      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
00089          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
00090      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
00091          add his own code by customization of function pointer HAL_I2S_ErrorCallback
00092      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
00093      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
00094      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
00095
00096    *** I2S HAL driver macros list ***
00097    =============================================
00098    [..]
00099      Below the list of most used macros in I2S HAL driver.
00100
00101       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
00102       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
00103       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
00104       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
00105       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
00106
00107     [..]
00108       (@) You can refer to the I2S HAL driver header file for more useful macros
00109
00110
00111      *** I2C Workarounds linked to Silicon Limitation ***
00112      ====================================================
00113      [..]
00114        (@) Only the 16-bit mode with no data extension can be used when the I2S
00115            is in Master and used the PCM long synchronization mode.
00116
00117
00118   @endverbatim
00119   ******************************************************************************
00120   * @attention
00121   *
00122   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00123   *
00124   * Redistribution and use in source and binary forms, with or without modification,
00125   * are permitted provided that the following conditions are met:
00126   *   1. Redistributions of source code must retain the above copyright notice,
00127   *      this list of conditions and the following disclaimer.
00128   *   2. Redistributions in binary form must reproduce the above copyright notice,
00129   *      this list of conditions and the following disclaimer in the documentation
00130   *      and/or other materials provided with the distribution.
00131   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00132   *      may be used to endorse or promote products derived from this software
00133   *      without specific prior written permission.
00134   *
00135   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00136   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00137   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00138   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00139   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00140   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00141   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00142   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00143   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00144   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00145   *
00146   ******************************************************************************
00147   */
00148
00149 /* Includes ------------------------------------------------------------------*/
00150 #include "stm32f1xx_hal.h"
00151
00152 /** @addtogroup STM32F1xx_HAL_Driver
00153   * @{
00154   */
00155
00156 #ifdef HAL_I2S_MODULE_ENABLED
00157 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
00158
00159 /** @defgroup I2S I2S
00160   * @brief I2S HAL module driver
00161   * @{
00162   */
00163
00164 /* Private typedef -----------------------------------------------------------*/
00165 /* Private define ------------------------------------------------------------*/
00166 /* Private macro -------------------------------------------------------------*/
00167 /* Private variables ---------------------------------------------------------*/
00168 /* Private function prototypes -----------------------------------------------*/
00169 /** @addtogroup I2S_Private_Functions I2S Private Functions
00170   * @{
00171   */
00172 static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
00173 static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00174 static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
00175 static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00176 static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
00177 static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
00178 static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
00179 static void               I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
00180 static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
00181                                                         uint32_t Timeout);
00182 /**
00183   * @}
00184   */
00185
00186 /* Exported functions ---------------------------------------------------------*/
00187 /** @defgroup I2S_Exported_Functions I2S Exported Functions
00188   * @{
00189   */
00190
00191 /** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
00192   *  @brief    Initialization and Configuration functions
00193   *
00194 @verbatim
00195  ===============================================================================
00196               ##### Initialization and de-initialization functions #####
00197  ===============================================================================
00198     [..]  This subsection provides a set of functions allowing to initialize and
00199           de-initialize the I2Sx peripheral in simplex mode:
00200
00201       (+) User must Implement HAL_I2S_MspInit() function in which he configures
00202           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00203
00204       (+) Call the function HAL_I2S_Init() to configure the selected device with
00205           the selected configuration:
00206         (++) Mode
00207         (++) Standard
00208         (++) Data Format
00209         (++) MCLK Output
00210         (++) Audio frequency
00211         (++) Polarity
00212
00213       (+) Call the function HAL_I2S_DeInit() to restore the default configuration
00214           of the selected I2Sx peripheral.
00215 @endverbatim
00216   * @{
00217   */
00218
00219 /**
00220   * @brief Initializes the I2S according to the specified parameters
00221   *         in the I2S_InitTypeDef and create the associated handle.
00222   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00223   *         the configuration information for I2S module
00224   * @retval HAL status
00225   */
00226 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
00227 {
00228   uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 16U;
00229   uint32_t tmp = 0U, i2sclk = 0U;
00230
00231   /* Check the I2S handle allocation */
00232   if(hi2s == NULL)
00233   {
00234     return HAL_ERROR;
00235   }
00236
00237   /* Check the I2S parameters */
00238   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
00239   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
00240   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
00241   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
00242   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
00243   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
00244   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
00245
00246   hi2s->State = HAL_I2S_STATE_BUSY;
00247
00248   /* Initialize Default I2S IrqHandler ISR */
00249   hi2s->IrqHandlerISR = I2S_IRQHandler;
00250
00251   /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00252   HAL_I2S_MspInit(hi2s);
00253
00254   /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
00255   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
00256   CLEAR_BIT(hi2s->Instance->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
00257                                      SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
00258                                      SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
00259   hi2s->Instance->I2SPR = 0x0002U;
00260
00261   /* Get the I2SCFGR register value */
00262   tmpreg = hi2s->Instance->I2SCFGR;
00263
00264   /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
00265   /* If the requested audio frequency is not the default, compute the prescaler */
00266   if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
00267   {
00268     /* Check the frame length (For the Prescaler computing) *******************/
00269     /* Set I2S Packet Length value*/
00270     if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
00271     {
00272       /* Packet length is 32 bits */
00273       packetlength = 32U;
00274     }
00275     else
00276     {
00277       /* Packet length is 16 bits */
00278       packetlength = 16U;
00279     }
00280
00281     /* I2S standard */
00282     if(hi2s->Init.Standard <= I2S_STANDARD_LSB)
00283     {
00284       /* In I2S standard packet lenght is multiplied by 2 */
00285       packetlength = packetlength * 2U;
00286     }
00287
00288     if(hi2s->Instance == SPI2)
00289     {
00290       /* Get the source clock value: based on SPI2 Instance */
00291       i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S2);
00292     }
00293     else if(hi2s->Instance == SPI3)
00294     {
00295       /* Get the source clock value: based on SPI3 Instance */
00296       i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S3);
00297     }
00298     else
00299     {
00300       /* Get the source clock value: based on System Clock value */
00301       i2sclk = HAL_RCC_GetSysClockFreq();
00302     }
00303
00304     /* Compute the Real divider depending on the MCLK output state, with a floating point */
00305     if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
00306     {
00307       /* MCLK output is enabled */
00308       if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
00309       {
00310         tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5);
00311       }
00312       else
00313       {
00314         tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5);
00315       }
00316     }
00317     else
00318     {
00319       /* MCLK output is disabled */
00320       tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5);
00321     }
00322
00323     /* Remove the flatting point */
00324     tmp = tmp / 10U;
00325
00326     /* Check the parity of the divider */
00327     i2sodd = (uint16_t)(tmp & (uint16_t)1U);
00328
00329     /* Compute the i2sdiv prescaler */
00330     i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
00331
00332     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00333     i2sodd = (uint32_t) (i2sodd << 8U);
00334   }
00335
00336   /* Test if the divider is 1 or 0 or greater than 0xFF */
00337   if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00338   {
00339     /* Set the default values */
00340     i2sdiv = 2U;
00341     i2sodd = 0U;
00342
00343     /* Set the error code and execute error callback*/
00344     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
00345     HAL_I2S_ErrorCallback(hi2s);
00346     return  HAL_ERROR;
00347   }
00348
00349   /* Write to SPIx I2SPR register the computed value */
00350   hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
00351
00352   /* Configure the I2S with the I2S_InitStruct values */
00353   tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
00354                        (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
00355                        (uint16_t)hi2s->Init.CPOL))));
00356   /* Write to SPIx I2SCFGR */
00357     WRITE_REG(hi2s->Instance->I2SCFGR,tmpreg);
00358   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00359   hi2s->State     = HAL_I2S_STATE_READY;
00360
00361   return HAL_OK;
00362 }
00363
00364 /**
00365   * @brief DeInitializes the I2S peripheral
00366   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00367   *         the configuration information for I2S module
00368   * @retval HAL status
00369   */
00370 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
00371 {
00372   /* Check the I2S handle allocation */
00373   if(hi2s == NULL)
00374   {
00375     return HAL_ERROR;
00376   }
00377
00378   hi2s->State = HAL_I2S_STATE_BUSY;
00379
00380   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00381   HAL_I2S_MspDeInit(hi2s);
00382
00383   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00384   hi2s->State     = HAL_I2S_STATE_RESET;
00385
00386   /* Release Lock */
00387   __HAL_UNLOCK(hi2s);
00388
00389   return HAL_OK;
00390 }
00391
00392 /**
00393   * @brief I2S MSP Init
00394   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00395   *         the configuration information for I2S module
00396   * @retval None
00397   */
00398  __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
00399 {
00400   /* Prevent unused argument(s) compilation warning */
00401   UNUSED(hi2s);
00402   /* NOTE : This function Should not be modified, when the callback is needed,
00403             the HAL_I2S_MspInit could be implemented in the user file
00404    */
00405 }
00406
00407 /**
00408   * @brief I2S MSP DeInit
00409   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00410   *         the configuration information for I2S module
00411   * @retval None
00412   */
00413  __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
00414 {
00415   /* Prevent unused argument(s) compilation warning */
00416   UNUSED(hi2s);
00417   /* NOTE : This function Should not be modified, when the callback is needed,
00418             the HAL_I2S_MspDeInit could be implemented in the user file
00419    */
00420 }
00421 /**
00422   * @}
00423   */
00424
00425 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
00426   *  @brief Data transfers functions
00427   *
00428 @verbatim
00429  ===============================================================================
00430                       ##### IO operation functions #####
00431  ===============================================================================
00432     [..]
00433     This subsection provides a set of functions allowing to manage the I2S data
00434     transfers.
00435
00436     (#) There are two modes of transfer:
00437        (++) Blocking mode : The communication is performed in the polling mode.
00438             The status of all data processing is returned by the same function
00439             after finishing transfer.
00440        (++) No-Blocking mode : The communication is performed using Interrupts
00441             or DMA. These functions return the status of the transfer startup.
00442             The end of the data processing will be indicated through the
00443             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
00444             using DMA mode.
00445
00446     (#) Blocking mode functions are :
00447         (++) HAL_I2S_Transmit()
00448         (++) HAL_I2S_Receive()
00449
00450     (#) No-Blocking mode functions with Interrupt are :
00451         (++) HAL_I2S_Transmit_IT()
00452         (++) HAL_I2S_Receive_IT()
00453
00454     (#) No-Blocking mode functions with DMA are :
00455         (++) HAL_I2S_Transmit_DMA()
00456         (++) HAL_I2S_Receive_DMA()
00457
00458     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00459         (++) HAL_I2S_TxCpltCallback()
00460         (++) HAL_I2S_RxCpltCallback()
00461         (++) HAL_I2S_ErrorCallback()
00462
00463 @endverbatim
00464   * @{
00465   */
00466
00467 /**
00468   * @brief Transmit an amount of data in blocking mode
00469   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00470   *         the configuration information for I2S module
00471   * @param pData: a 16-bit pointer to data buffer.
00472   * @param Size: number of data sample to be sent:
00473   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00474   *       configuration phase, the Size parameter means the number of 16-bit data length
00475   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00476   *       the Size parameter means the number of 16-bit data length.
00477   * @param  Timeout: Timeout duration
00478   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00479   *       between Master and Slave(example: audio streaming).
00480   * @retval HAL status
00481   */
00482 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00483 {
00484   uint32_t tmp1 = 0U;
00485
00486   if((pData == NULL ) || (Size == 0U))
00487   {
00488     return  HAL_ERROR;
00489   }
00490
00491   if(hi2s->State == HAL_I2S_STATE_READY)
00492   {
00493     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00494
00495     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00496     {
00497       hi2s->TxXferSize  = (Size << 1U);
00498       hi2s->TxXferCount = (Size << 1U);
00499     }
00500     else
00501     {
00502       hi2s->TxXferSize  = Size;
00503       hi2s->TxXferCount = Size;
00504     }
00505
00506     /* Process Locked */
00507     __HAL_LOCK(hi2s);
00508
00509     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00510     hi2s->State     = HAL_I2S_STATE_BUSY_TX;
00511
00512     /* Check if the I2S is already enabled */
00513     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00514     {
00515       /* Enable I2S peripheral */
00516       __HAL_I2S_ENABLE(hi2s);
00517     }
00518
00519     while(hi2s->TxXferCount > 0U)
00520     {
00521       hi2s->Instance->DR = (*pData++);
00522       hi2s->TxXferCount--;
00523
00524       /* Wait until TXE flag is set */
00525       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
00526       {
00527         /* Set the error code and execute error callback*/
00528         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
00529         HAL_I2S_ErrorCallback(hi2s);
00530         return HAL_TIMEOUT;
00531       }
00532
00533       /* Check if an underrun occurs */
00534       if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
00535       {
00536         /* Clear underrun flag */
00537         __HAL_I2S_CLEAR_UDRFLAG(hi2s);
00538         /* Set the I2S State ready */
00539         hi2s->State = HAL_I2S_STATE_READY;
00540
00541         /* Process Unlocked */
00542         __HAL_UNLOCK(hi2s);
00543
00544         /* Set the error code and execute error callback*/
00545         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
00546         HAL_I2S_ErrorCallback(hi2s);
00547
00548         return HAL_ERROR;
00549       }
00550     }
00551     hi2s->State = HAL_I2S_STATE_READY;
00552
00553     /* Process Unlocked */
00554     __HAL_UNLOCK(hi2s);
00555
00556     return HAL_OK;
00557   }
00558   else
00559   {
00560     return HAL_BUSY;
00561   }
00562 }
00563
00564 /**
00565   * @brief Receive an amount of data in blocking mode
00566   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00567   *         the configuration information for I2S module
00568   * @param pData: a 16-bit pointer to data buffer
00569   * @param Size: number of data sample to be sent:
00570   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00571   *       configuration phase, the Size parameter means the number of 16-bit data length
00572   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00573   *       the Size parameter means the number of 16-bit data length.
00574   * @param Timeout: Timeout duration
00575   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00576   *       between Master and Slave(example: audio streaming)
00577   * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
00578   *       in continuous way and as the I2S is not disabled at the end of the I2S transaction
00579   * @retval HAL status
00580   */
00581 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
00582 {
00583   uint32_t tmp1 = 0U;
00584
00585   if((pData == NULL ) || (Size == 0U))
00586   {
00587     return  HAL_ERROR;
00588   }
00589
00590   if(hi2s->State == HAL_I2S_STATE_READY)
00591   {
00592     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00593     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00594     {
00595       hi2s->RxXferSize  = (Size << 1U);
00596       hi2s->RxXferCount = (Size << 1U);
00597     }
00598     else
00599     {
00600       hi2s->RxXferSize  = Size;
00601       hi2s->RxXferCount = Size;
00602     }
00603     /* Process Locked */
00604     __HAL_LOCK(hi2s);
00605
00606     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00607     hi2s->State     = HAL_I2S_STATE_BUSY_RX;
00608
00609     /* Check if the I2S is already enabled */
00610     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00611     {
00612       /* Enable I2S peripheral */
00613       __HAL_I2S_ENABLE(hi2s);
00614     }
00615
00616     /* Check if Master Receiver mode is selected */
00617     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00618     {
00619       /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
00620       access to the SPI_SR register. */
00621       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00622     }
00623
00624     /* Receive data */
00625     while(hi2s->RxXferCount > 0U)
00626     {
00627       /* Wait until RXNE flag is set */
00628       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
00629       {
00630         /* Set the error code and execute error callback*/
00631         SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
00632         HAL_I2S_ErrorCallback(hi2s);
00633         return HAL_TIMEOUT;
00634       }
00635
00636       /* Check if an overrun occurs */
00637       if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
00638       {
00639         /* Clear overrun flag */
00640         __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00641
00642         /* Set the I2S State ready */
00643         hi2s->State = HAL_I2S_STATE_READY;
00644
00645         /* Process Unlocked */
00646         __HAL_UNLOCK(hi2s);
00647
00648         /* Set the error code and execute error callback*/
00649         SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
00650         HAL_I2S_ErrorCallback(hi2s);
00651
00652         return HAL_ERROR;
00653       }
00654
00655       (*pData++) = hi2s->Instance->DR;
00656       hi2s->RxXferCount--;
00657     }
00658
00659     hi2s->State = HAL_I2S_STATE_READY;
00660
00661     /* Process Unlocked */
00662     __HAL_UNLOCK(hi2s);
00663
00664     return HAL_OK;
00665   }
00666   else
00667   {
00668     return HAL_BUSY;
00669   }
00670 }
00671
00672 /**
00673   * @brief Transmit an amount of data in non-blocking mode with Interrupt
00674   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00675   *         the configuration information for I2S module
00676   * @param pData: a 16-bit pointer to data buffer.
00677   * @param Size: number of data sample to be sent:
00678   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00679   *       configuration phase, the Size parameter means the number of 16-bit data length
00680   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00681   *       the Size parameter means the number of 16-bit data length.
00682   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00683   *       between Master and Slave(example: audio streaming).
00684   * @retval HAL status
00685   */
00686 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00687 {
00688   uint32_t tmp1 = 0U;
00689
00690   if(hi2s->State == HAL_I2S_STATE_READY)
00691   {
00692     if((pData == NULL) || (Size == 0U))
00693     {
00694       return  HAL_ERROR;
00695     }
00696
00697     hi2s->pTxBuffPtr = pData;
00698     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00699     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00700     {
00701       hi2s->TxXferSize  = (Size << 1U);
00702       hi2s->TxXferCount = (Size << 1U);
00703     }
00704     else
00705     {
00706       hi2s->TxXferSize  = Size;
00707       hi2s->TxXferCount = Size;
00708     }
00709
00710     /* Process Locked */
00711     __HAL_LOCK(hi2s);
00712
00713     hi2s->State     = HAL_I2S_STATE_BUSY_TX;
00714     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00715
00716     /* Enable TXE and ERR interrupt */
00717     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
00718
00719     /* Check if the I2S is already enabled */
00720     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00721     {
00722       /* Enable I2S peripheral */
00723       __HAL_I2S_ENABLE(hi2s);
00724     }
00725
00726     /* Process Unlocked */
00727     __HAL_UNLOCK(hi2s);
00728
00729     return HAL_OK;
00730   }
00731   else
00732   {
00733     return HAL_BUSY;
00734   }
00735 }
00736
00737 /**
00738   * @brief Receive an amount of data in non-blocking mode with Interrupt
00739   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00740   *         the configuration information for I2S module
00741   * @param pData: a 16-bit pointer to the Receive data buffer.
00742   * @param Size: number of data sample to be sent:
00743   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00744   *       configuration phase, the Size parameter means the number of 16-bit data length
00745   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00746   *       the Size parameter means the number of 16-bit data length.
00747   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00748   *       between Master and Slave(example: audio streaming).
00749   * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
00750   * between Master and Slave otherwise the I2S interrupt should be optimized.
00751   * @retval HAL status
00752   */
00753 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00754 {
00755   uint32_t tmp1 = 0U;
00756
00757   if(hi2s->State == HAL_I2S_STATE_READY)
00758   {
00759     if((pData == NULL) || (Size == 0U))
00760     {
00761       return  HAL_ERROR;
00762     }
00763
00764     hi2s->pRxBuffPtr = pData;
00765     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00766     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00767     {
00768       hi2s->RxXferSize  = (Size << 1U);
00769       hi2s->RxXferCount = (Size << 1U);
00770     }
00771     else
00772     {
00773       hi2s->RxXferSize  = Size;
00774       hi2s->RxXferCount = Size;
00775     }
00776     /* Process Locked */
00777     __HAL_LOCK(hi2s);
00778
00779     hi2s->State     = HAL_I2S_STATE_BUSY_RX;
00780     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00781
00782     /* Enable TXE and ERR interrupt */
00783     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
00784
00785     /* Check if the I2S is already enabled */
00786     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00787     {
00788       /* Enable I2S peripheral */
00789       __HAL_I2S_ENABLE(hi2s);
00790     }
00791
00792     /* Process Unlocked */
00793     __HAL_UNLOCK(hi2s);
00794
00795     return HAL_OK;
00796   }
00797
00798   else
00799   {
00800     return HAL_BUSY;
00801   }
00802 }
00803
00804 /**
00805   * @brief Transmit an amount of data in non-blocking mode with DMA
00806   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00807   *         the configuration information for I2S module
00808   * @param pData: a 16-bit pointer to the Transmit data buffer.
00809   * @param Size: number of data sample to be sent:
00810   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00811   *       configuration phase, the Size parameter means the number of 16-bit data length
00812   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00813   *       the Size parameter means the number of 16-bit data length.
00814   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00815   *       between Master and Slave(example: audio streaming).
00816   * @retval HAL status
00817   */
00818 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00819 {
00820   uint32_t *tmp = NULL;
00821   uint32_t tmp1 = 0U;
00822
00823   if((pData == NULL) || (Size == 0U))
00824   {
00825     return  HAL_ERROR;
00826   }
00827
00828   if(hi2s->State == HAL_I2S_STATE_READY)
00829   {
00830     hi2s->pTxBuffPtr = pData;
00831     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00832     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00833     {
00834       hi2s->TxXferSize  = (Size << 1U);
00835       hi2s->TxXferCount = (Size << 1U);
00836     }
00837     else
00838     {
00839       hi2s->TxXferSize  = Size;
00840       hi2s->TxXferCount = Size;
00841     }
00842
00843     /* Process Locked */
00844     __HAL_LOCK(hi2s);
00845
00846     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00847     hi2s->State     = HAL_I2S_STATE_BUSY_TX;
00848
00849     /* Set the I2S Tx DMA Half transfer complete callback */
00850     hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
00851
00852     /* Set the I2S Tx DMA transfer complete callback */
00853     hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
00854
00855     /* Set the DMA error callback */
00856     hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
00857
00858     /* Enable the Tx DMA Stream */
00859     tmp = (uint32_t*)&pData;
00860     HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
00861
00862     /* Check if the I2S is already enabled */
00863     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00864     {
00865       /* Enable I2S peripheral */
00866       __HAL_I2S_ENABLE(hi2s);
00867     }
00868
00869      /* Check if the I2S Tx request is already enabled */
00870     if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
00871     {
00872       /* Enable Tx DMA Request */
00873       SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
00874     }
00875
00876     /* Process Unlocked */
00877     __HAL_UNLOCK(hi2s);
00878
00879     return HAL_OK;
00880   }
00881   else
00882   {
00883     return HAL_BUSY;
00884   }
00885 }
00886
00887 /**
00888   * @brief Receive an amount of data in non-blocking mode with DMA
00889   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00890   *         the configuration information for I2S module
00891   * @param pData: a 16-bit pointer to the Receive data buffer.
00892   * @param Size: number of data sample to be sent:
00893   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
00894   *       configuration phase, the Size parameter means the number of 16-bit data length
00895   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
00896   *       the Size parameter means the number of 16-bit data length.
00897   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
00898   *       between Master and Slave(example: audio streaming).
00899   * @retval HAL status
00900   */
00901 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
00902 {
00903   uint32_t *tmp = NULL;
00904   uint32_t tmp1 = 0U;
00905
00906   if((pData == NULL) || (Size == 0U))
00907   {
00908     return  HAL_ERROR;
00909   }
00910
00911   if(hi2s->State == HAL_I2S_STATE_READY)
00912   {
00913     hi2s->pRxBuffPtr = pData;
00914     tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
00915     if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
00916     {
00917       hi2s->RxXferSize  = (Size << 1U);
00918       hi2s->RxXferCount = (Size << 1U);
00919     }
00920     else
00921     {
00922       hi2s->RxXferSize  = Size;
00923       hi2s->RxXferCount = Size;
00924     }
00925     /* Process Locked */
00926     __HAL_LOCK(hi2s);
00927
00928     hi2s->State     = HAL_I2S_STATE_BUSY_RX;
00929     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
00930
00931     /* Set the I2S Rx DMA Half transfer complete callback */
00932     hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
00933
00934     /* Set the I2S Rx DMA transfer complete callback */
00935     hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
00936
00937     /* Set the DMA error callback */
00938     hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
00939
00940     /* Check if Master Receiver mode is selected */
00941     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
00942     {
00943       /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
00944       access to the SPI_SR register. */
00945       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
00946     }
00947
00948     /* Enable the Rx DMA Stream */
00949     tmp = (uint32_t*)&pData;
00950     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
00951
00952     /* Check if the I2S is already enabled */
00953     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
00954     {
00955       /* Enable I2S peripheral */
00956       __HAL_I2S_ENABLE(hi2s);
00957     }
00958
00959      /* Check if the I2S Rx request is already enabled */
00960     if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
00961     {
00962       /* Enable Rx DMA Request */
00963       SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
00964     }
00965
00966     /* Process Unlocked */
00967     __HAL_UNLOCK(hi2s);
00968
00969     return HAL_OK;
00970   }
00971   else
00972   {
00973     return HAL_BUSY;
00974   }
00975 }
00976
00977 /**
00978   * @brief Pauses the audio channel playing from the Media.
00979   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
00980   *         the configuration information for I2S module
00981   * @retval HAL status
00982   */
00983 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
00984 {
00985   /* Process Locked */
00986   __HAL_LOCK(hi2s);
00987
00988   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
00989   {
00990     /* Disable the I2S DMA Tx request */
00991     CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
00992   }
00993   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
00994   {
00995     /* Disable the I2S DMA Rx request */
00996     CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
00997   }
00998
00999   /* Process Unlocked */
01000   __HAL_UNLOCK(hi2s);
01001
01002   return HAL_OK;
01003 }
01004
01005 /**
01006   * @brief Resumes the audio channel playing from the Media.
01007   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01008   *         the configuration information for I2S module
01009   * @retval HAL status
01010   */
01011 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
01012 {
01013   /* Process Locked */
01014   __HAL_LOCK(hi2s);
01015
01016   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
01017   {
01018     /* Enable the I2S DMA Tx request */
01019     SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
01020   }
01021   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
01022   {
01023     /* Enable the I2S DMA Rx request */
01024     SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
01025   }
01026
01027   /* If the I2S peripheral is still not enabled, enable it */
01028   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
01029   {
01030     /* Enable I2S peripheral */
01031     __HAL_I2S_ENABLE(hi2s);
01032   }
01033
01034   /* Process Unlocked */
01035   __HAL_UNLOCK(hi2s);
01036
01037   return HAL_OK;
01038 }
01039
01040 /**
01041   * @brief Resumes the audio channel playing from the Media.
01042   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01043   *         the configuration information for I2S module
01044   * @retval HAL status
01045   */
01046 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
01047 {
01048   /* Process Locked */
01049   __HAL_LOCK(hi2s);
01050
01051   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
01052   {
01053     /* Disable the I2S DMA requests */
01054     CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
01055
01056     /* Disable the I2S DMA Channel */
01057     HAL_DMA_Abort(hi2s->hdmatx);
01058   }
01059   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
01060   {
01061     /* Disable the I2S DMA requests */
01062     CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
01063
01064     /* Disable the I2S DMA Channel */
01065     HAL_DMA_Abort(hi2s->hdmarx);
01066   }
01067   /* Disable I2S peripheral */
01068   __HAL_I2S_DISABLE(hi2s);
01069
01070   hi2s->State = HAL_I2S_STATE_READY;
01071
01072   /* Process Unlocked */
01073   __HAL_UNLOCK(hi2s);
01074
01075   return HAL_OK;
01076 }
01077
01078 /**
01079   * @brief  This function handles I2S interrupt request.
01080   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01081   *         the configuration information for I2S module
01082   * @retval None
01083   */
01084 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
01085 {
01086   /* Call the IrqHandler ISR set during HAL_I2S_INIT */
01087   hi2s->IrqHandlerISR(hi2s);
01088 }
01089
01090 /**
01091   * @brief Tx Transfer Half completed callbacks
01092   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01093   *         the configuration information for I2S module
01094   * @retval None
01095   */
01096  __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01097 {
01098   /* Prevent unused argument(s) compilation warning */
01099   UNUSED(hi2s);
01100   /* NOTE : This function Should not be modified, when the callback is needed,
01101             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
01102    */
01103 }
01104
01105 /**
01106   * @brief Tx Transfer completed callbacks
01107   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01108   *         the configuration information for I2S module
01109   * @retval None
01110   */
01111  __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
01112 {
01113   /* Prevent unused argument(s) compilation warning */
01114   UNUSED(hi2s);
01115   /* NOTE : This function Should not be modified, when the callback is needed,
01116             the HAL_I2S_TxCpltCallback could be implemented in the user file
01117    */
01118 }
01119
01120 /**
01121   * @brief Rx Transfer half completed callbacks
01122   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01123   *         the configuration information for I2S module
01124   * @retval None
01125   */
01126 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
01127 {
01128   /* Prevent unused argument(s) compilation warning */
01129   UNUSED(hi2s);
01130   /* NOTE : This function Should not be modified, when the callback is needed,
01131             the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
01132    */
01133 }
01134
01135 /**
01136   * @brief Rx Transfer completed callbacks
01137   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01138   *         the configuration information for I2S module
01139   * @retval None
01140   */
01141 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
01142 {
01143   /* Prevent unused argument(s) compilation warning */
01144   UNUSED(hi2s);
01145   /* NOTE : This function Should not be modified, when the callback is needed,
01146             the HAL_I2S_RxCpltCallback could be implemented in the user file
01147    */
01148 }
01149
01150 /**
01151   * @brief I2S error callbacks
01152   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01153   *         the configuration information for I2S module
01154   * @retval None
01155   */
01156  __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
01157 {
01158   /* Prevent unused argument(s) compilation warning */
01159   UNUSED(hi2s);
01160   /* NOTE : This function Should not be modified, when the callback is needed,
01161             the HAL_I2S_ErrorCallback could be implemented in the user file
01162    */
01163 }
01164
01165 /**
01166   * @}
01167   */
01168
01169 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
01170   *  @brief   Peripheral State functions
01171   *
01172 @verbatim
01173  ===============================================================================
01174                       ##### Peripheral State and Errors functions #####
01175  ===============================================================================
01176     [..]
01177     This subsection permits to get in run-time the status of the peripheral
01178     and the data flow.
01179
01180 @endverbatim
01181   * @{
01182   */
01183
01184 /**
01185   * @brief  Return the I2S state
01186   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01187   *         the configuration information for I2S module
01188   * @retval HAL state
01189   */
01190 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
01191 {
01192   return hi2s->State;
01193 }
01194
01195 /**
01196   * @brief  Return the I2S error code
01197   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01198   *         the configuration information for I2S module
01199   * @retval I2S Error Code
01200   */
01201 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
01202 {
01203   return hi2s->ErrorCode;
01204 }
01205 /**
01206   * @}
01207   */
01208
01209 /**
01210   * @}
01211   */
01212
01213 /* Private functions ---------------------------------------------------------*/
01214 /** @addtogroup I2S_Private_Functions I2S Private Functions
01215   * @{
01216   */
01217 /**
01218   * @brief DMA I2S transmit process complete callback
01219   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01220   *                the configuration information for the specified DMA module.
01221   * @retval None
01222   */
01223 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
01224 {
01225   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01226
01227   if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
01228   {
01229     /* Disable Tx DMA Request */
01230     CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
01231
01232     hi2s->TxXferCount = 0U;
01233     hi2s->State       = HAL_I2S_STATE_READY;
01234   }
01235   HAL_I2S_TxCpltCallback(hi2s);
01236 }
01237 /**
01238   * @brief DMA I2S transmit process half complete callback
01239   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01240   *                the configuration information for the specified DMA module.
01241   * @retval None
01242   */
01243 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01244 {
01245   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01246
01247   HAL_I2S_TxHalfCpltCallback(hi2s);
01248 }
01249
01250 /**
01251   * @brief DMA I2S receive process complete callback
01252   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01253   *                the configuration information for the specified DMA module.
01254   * @retval None
01255   */
01256 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
01257 {
01258   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01259
01260   if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
01261   {
01262     /* Disable Rx DMA Request */
01263     CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
01264     hi2s->RxXferCount = 0U;
01265     hi2s->State       = HAL_I2S_STATE_READY;
01266   }
01267   HAL_I2S_RxCpltCallback(hi2s);
01268 }
01269
01270 /**
01271   * @brief DMA I2S receive process half complete callback
01272   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01273   *                the configuration information for the specified DMA module.
01274   * @retval None
01275   */
01276 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01277 {
01278   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01279
01280   HAL_I2S_RxHalfCpltCallback(hi2s);
01281 }
01282
01283 /**
01284   * @brief DMA I2S communication error callback
01285   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01286   *                the configuration information for the specified DMA module.
01287   * @retval None
01288   */
01289 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
01290 {
01291   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01292
01293   /* Disable Rx and Tx DMA Request */
01294   CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
01295   hi2s->TxXferCount = 0U;
01296   hi2s->RxXferCount = 0U;
01297
01298   hi2s->State= HAL_I2S_STATE_READY;
01299
01300   SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA);
01301   HAL_I2S_ErrorCallback(hi2s);
01302 }
01303
01304 /**
01305   * @brief Transmit an amount of data in non-blocking mode with Interrupt
01306   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01307   *         the configuration information for I2S module
01308   * @retval HAL status
01309   */
01310 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
01311 {
01312   /* Transmit data */
01313   hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
01314   hi2s->TxXferCount--;
01315
01316   if(hi2s->TxXferCount == 0U)
01317   {
01318     /* Disable TXE and ERR interrupt */
01319     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01320
01321     hi2s->State = HAL_I2S_STATE_READY;
01322     HAL_I2S_TxCpltCallback(hi2s);
01323   }
01324 }
01325
01326 /**
01327   * @brief Receive an amount of data in non-blocking mode with Interrupt
01328   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01329   *         the configuration information for I2S module
01330   * @retval HAL status
01331   */
01332 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
01333 {
01334   /* Receive data */
01335   (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
01336   hi2s->RxXferCount--;
01337
01338   if(hi2s->RxXferCount == 0U)
01339   {
01340     /* Disable RXNE and ERR interrupt */
01341     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01342
01343     hi2s->State = HAL_I2S_STATE_READY;
01344     HAL_I2S_RxCpltCallback(hi2s);
01345   }
01346 }
01347
01348 /**
01349   * @brief  This function handles I2S interrupt request.
01350   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01351   *         the configuration information for I2S module
01352   * @retval None
01353   */
01354 static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
01355 {
01356   __IO uint32_t i2ssr = hi2s->Instance->SR;
01357
01358   if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
01359   {
01360     /* I2S in mode Receiver ------------------------------------------------*/
01361     if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
01362     {
01363       I2S_Receive_IT(hi2s);
01364     }
01365
01366     /* I2S Overrun error interrupt occured -------------------------------------*/
01367     if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
01368     {
01369       /* Disable RXNE and ERR interrupt */
01370       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
01371
01372       /* Clear Overrun flag */
01373       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
01374
01375       /* Set the I2S State ready */
01376       hi2s->State = HAL_I2S_STATE_READY;
01377
01378
01379       /* Set the error code and execute error callback*/
01380       SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
01381       HAL_I2S_ErrorCallback(hi2s);
01382       }
01383     }
01384
01385     if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
01386     {
01387       /* I2S in mode Transmitter -----------------------------------------------*/
01388     if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
01389       {
01390         I2S_Transmit_IT(hi2s);
01391       }
01392
01393       /* I2S Underrun error interrupt occurred --------------------------------*/
01394     if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
01395       {
01396       /* Disable TXE and ERR interrupt */
01397       __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
01398
01399       /* Clear Underrun flag */
01400       __HAL_I2S_CLEAR_UDRFLAG(hi2s);
01401
01402       /* Set the I2S State ready */
01403       hi2s->State = HAL_I2S_STATE_READY;
01404
01405       /* Set the error code and execute error callback*/
01406       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
01407       HAL_I2S_ErrorCallback(hi2s);
01408     }
01409   }
01410 }
01411
01412 /**
01413   * @brief This function handles I2S Communication Timeout.
01414   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
01415   *         the configuration information for I2S module
01416   * @param Flag: Flag checked
01417   * @param State: Value of the flag expected
01418   * @param Timeout: Duration of the timeout
01419   * @retval HAL status
01420   */
01421 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
01422                                                        uint32_t Timeout)
01423 {
01424   uint32_t tickstart = HAL_GetTick();
01425
01426    /* Wait until flag is set to status*/
01427   while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
01428   {
01429     if(Timeout != HAL_MAX_DELAY)
01430     {
01431       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01432       {
01433         /* Set the I2S State ready */
01434         hi2s->State = HAL_I2S_STATE_READY;
01435
01436         /* Process Unlocked */
01437         __HAL_UNLOCK(hi2s);
01438
01439         return HAL_TIMEOUT;
01440       }
01441     }
01442   }
01443   return HAL_OK;
01444 }
01445
01446 /**
01447   * @}
01448   */
01449
01450 /**
01451   * @}
01452   */
01453
01454 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
01455 #endif /* HAL_I2S_MODULE_ENABLED */
01456 /**
01457   * @}
01458   */
01459
01460 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_i2s.h Source File

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stm32f1xx_hal_i2s.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_i2s.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of I2S HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_I2S_H
00040 #define __STM32F1xx_HAL_I2S_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f1xx_hal_def.h"
00050
00051 /** @addtogroup STM32F1xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @addtogroup I2S
00056   * @{
00057   */
00058
00059 /* Exported types ------------------------------------------------------------*/
00060 /** @defgroup I2S_Exported_Types I2S Exported Types
00061   * @{
00062   */
00063
00064 /**
00065   * @brief I2S Init structure definition
00066   */
00067 typedef struct
00068 {
00069   uint32_t Mode;            /*!< Specifies the I2S operating mode.
00070                                  This parameter can be a value of @ref I2S_Mode */
00071
00072   uint32_t Standard;        /*!< Specifies the standard used for the I2S communication.
00073                                  This parameter can be a value of @ref I2S_Standard */
00074
00075   uint32_t DataFormat;      /*!< Specifies the data format for the I2S communication.
00076                                  This parameter can be a value of @ref I2S_Data_Format */
00077
00078   uint32_t MCLKOutput;      /*!< Specifies whether the I2S MCLK output is enabled or not.
00079                                  This parameter can be a value of @ref I2S_MCLK_Output */
00080
00081   uint32_t AudioFreq;       /*!< Specifies the frequency selected for the I2S communication.
00082                                  This parameter can be a value of @ref I2S_Audio_Frequency */
00083
00084   uint32_t CPOL;            /*!< Specifies the idle state of the I2S clock.
00085                                  This parameter can be a value of @ref I2S_Clock_Polarity */
00086 }I2S_InitTypeDef;
00087
00088 /**
00089   * @brief  HAL State structures definition
00090   */
00091 typedef enum
00092 {
00093   HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
00094   HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
00095   HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
00096   HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */
00097   HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */
00098   HAL_I2S_STATE_BUSY_TX_RX = 0x05U,  /*!< Data Transmission and Reception process is ongoing */
00099   HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */
00100   HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */
00101
00102 }HAL_I2S_StateTypeDef;
00103
00104 /**
00105   * @brief I2S handle Structure definition
00106   */
00107 typedef struct __I2S_HandleTypeDef
00108 {
00109   SPI_TypeDef                *Instance;    /*!< I2S registers base address        */
00110
00111   I2S_InitTypeDef            Init;         /*!< I2S communication parameters      */
00112
00113   uint16_t                   *pTxBuffPtr;  /*!< Pointer to I2S Tx transfer buffer */
00114
00115   __IO uint16_t              TxXferSize;   /*!< I2S Tx transfer size              */
00116
00117   __IO uint16_t              TxXferCount;  /*!< I2S Tx transfer Counter           */
00118
00119   uint16_t                   *pRxBuffPtr;  /*!< Pointer to I2S Rx transfer buffer */
00120
00121   __IO uint16_t              RxXferSize;   /*!< I2S Rx transfer size              */
00122
00123   __IO uint16_t              RxXferCount;  /*!< I2S Rx transfer counter
00124                                               (This field is initialized at the
00125                                                same value as transfer size at the
00126                                                beginning of the transfer and
00127                                                decremented when a sample is received
00128                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
00129
00130   void (*IrqHandlerISR)      (struct __I2S_HandleTypeDef *hi2s);   /*!< I2S function pointer on IrqHandler   */
00131
00132   DMA_HandleTypeDef          *hdmatx;      /*!< I2S Tx DMA handle parameters      */
00133
00134   DMA_HandleTypeDef          *hdmarx;      /*!< I2S Rx DMA handle parameters      */
00135
00136   __IO HAL_LockTypeDef       Lock;         /*!< I2S locking object                */
00137
00138   __IO HAL_I2S_StateTypeDef  State;        /*!< I2S communication state           */
00139
00140   __IO uint32_t              ErrorCode;    /*!< I2S Error code
00141                                               This parameter can be a value of @ref I2S_ErrorCode */
00142
00143 }I2S_HandleTypeDef;
00144 /**
00145   * @}
00146   */
00147
00148 /* Exported constants --------------------------------------------------------*/
00149 /** @defgroup I2S_Exported_Constants I2S Exported Constants
00150   * @{
00151   */
00152 /**
00153   * @defgroup  I2S_ErrorCode I2S Error Code
00154   * @{
00155   */
00156 #define HAL_I2S_ERROR_NONE               0x00000000U  /*!< No error                    */
00157 #define HAL_I2S_ERROR_TIMEOUT            0x00000001U  /*!< Timeout error               */
00158 #define HAL_I2S_ERROR_OVR                0x00000002U  /*!< OVR error                   */
00159 #define HAL_I2S_ERROR_UDR                0x00000004U  /*!< UDR error                   */
00160 #define HAL_I2S_ERROR_DMA                0x00000008U  /*!< DMA transfer error          */
00161 #define HAL_I2S_ERROR_PRESCALER          0x00000010U  /*!< Prescaler Calculation error */
00162 /**
00163   * @}
00164   */
00165
00166 /** @defgroup I2S_Mode I2S Mode
00167   * @{
00168   */
00169 #define I2S_MODE_SLAVE_TX                0x00000000U
00170 #define I2S_MODE_SLAVE_RX                ((uint32_t)SPI_I2SCFGR_I2SCFG_0)
00171 #define I2S_MODE_MASTER_TX               ((uint32_t)SPI_I2SCFGR_I2SCFG_1)
00172 #define I2S_MODE_MASTER_RX               ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup I2S_Standard I2S Standard
00178   * @{
00179   */
00180 #define I2S_STANDARD_PHILIPS             0x00000000U
00181 #define I2S_STANDARD_MSB                 ((uint32_t)SPI_I2SCFGR_I2SSTD_0)
00182 #define I2S_STANDARD_LSB                 ((uint32_t)SPI_I2SCFGR_I2SSTD_1)
00183 #define I2S_STANDARD_PCM_SHORT           ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
00184 #define I2S_STANDARD_PCM_LONG            ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
00185 /**
00186   * @}
00187   */
00188
00189 /** @defgroup I2S_Data_Format I2S Data Format
00190   * @{
00191   */
00192 #define I2S_DATAFORMAT_16B               0x00000000U
00193 #define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t)SPI_I2SCFGR_CHLEN)
00194 #define I2S_DATAFORMAT_24B               ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
00195 #define I2S_DATAFORMAT_32B               ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup I2S_MCLK_Output I2S Mclk Output
00201   * @{
00202   */
00203 #define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
00204 #define I2S_MCLKOUTPUT_DISABLE          0x00000000U
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
00210   * @{
00211   */
00212 #define I2S_AUDIOFREQ_192K               192000U
00213 #define I2S_AUDIOFREQ_96K                96000U
00214 #define I2S_AUDIOFREQ_48K                48000U
00215 #define I2S_AUDIOFREQ_44K                44100U
00216 #define I2S_AUDIOFREQ_32K                32000U
00217 #define I2S_AUDIOFREQ_22K                22050U
00218 #define I2S_AUDIOFREQ_16K                16000U
00219 #define I2S_AUDIOFREQ_11K                11025U
00220 #define I2S_AUDIOFREQ_8K                 8000U
00221 #define I2S_AUDIOFREQ_DEFAULT            2U
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup I2S_Clock_Polarity  I2S Clock Polarity
00227   * @{
00228   */
00229 #define I2S_CPOL_LOW                    0x00000000U
00230 #define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
00236   * @{
00237   */
00238 #define I2S_IT_TXE                      SPI_CR2_TXEIE
00239 #define I2S_IT_RXNE                     SPI_CR2_RXNEIE
00240 #define I2S_IT_ERR                      SPI_CR2_ERRIE
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup I2S_Flags_Definition I2S Flags Definition
00246   * @{
00247   */
00248 #define I2S_FLAG_TXE                    SPI_SR_TXE
00249 #define I2S_FLAG_RXNE                   SPI_SR_RXNE
00250
00251 #define I2S_FLAG_UDR                    SPI_SR_UDR
00252 #define I2S_FLAG_OVR                    SPI_SR_OVR
00253 #define I2S_FLAG_FRE                    SPI_SR_FRE
00254
00255 #define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
00256 #define I2S_FLAG_BSY                    SPI_SR_BSY
00257 /**
00258   * @}
00259   */
00260
00261 /**
00262   * @}
00263   */
00264
00265 /* Exported macro ------------------------------------------------------------*/
00266 /** @defgroup I2S_Exported_Macros I2S Exported Macros
00267   * @{
00268   */
00269
00270 /** @brief Reset I2S handle state
00271   * @param  __HANDLE__: specifies the I2S Handle.
00272   * @retval None
00273   */
00274 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
00275
00276 /** @brief  Enable the specified SPI peripheral (in I2S mode).
00277   * @param  __HANDLE__: specifies the I2S Handle.
00278   * @retval None
00279   */
00280 #define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
00281
00282 /** @brief  Disable the specified SPI peripheral (in I2S mode).
00283   * @param  __HANDLE__: specifies the I2S Handle.
00284   * @retval None
00285   */
00286 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
00287
00288 /** @brief  Enable the specified I2S interrupts.
00289   * @param  __HANDLE__: specifies the I2S Handle.
00290   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00291   *         This parameter can be one of the following values:
00292   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00293   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00294   *            @arg I2S_IT_ERR: Error interrupt enable
00295   * @retval None
00296   */
00297 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
00298
00299 /** @brief  Disable the specified I2S interrupts.
00300   * @param  __HANDLE__: specifies the I2S Handle.
00301   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
00302   *         This parameter can be one of the following values:
00303   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00304   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00305   *            @arg I2S_IT_ERR: Error interrupt enable
00306   * @retval None
00307   */
00308 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
00309
00310 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
00311   * @param  __HANDLE__: specifies the I2S Handle.
00312   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
00313   * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
00314   *          This parameter can be one of the following values:
00315   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
00316   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
00317   *            @arg I2S_IT_ERR: Error interrupt enable
00318   * @retval The new state of __IT__ (TRUE or FALSE).
00319   */
00320 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00321
00322 /** @brief  Checks whether the specified I2S flag is set or not.
00323   * @param  __HANDLE__: specifies the I2S Handle.
00324   * @param  __FLAG__: specifies the flag to check.
00325   *         This parameter can be one of the following values:
00326   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
00327   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
00328   *            @arg I2S_FLAG_UDR: Underrun flag
00329   *            @arg I2S_FLAG_OVR: Overrun flag
00330   *            @arg I2S_FLAG_FRE: Frame error flag
00331   *            @arg I2S_FLAG_CHSIDE: Channel Side flag
00332   *            @arg I2S_FLAG_BSY: Busy flag
00333   * @retval The new state of __FLAG__ (TRUE or FALSE).
00334   */
00335 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00336
00337 /** @brief Clears the I2S OVR pending flag.
00338   * @param  __HANDLE__: specifies the I2S Handle.
00339   * @retval None
00340   */
00341 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__)     \
00342   do{                                           \
00343     __IO uint32_t tmpreg = 0x00U;               \
00344     tmpreg = (__HANDLE__)->Instance->DR;        \
00345     tmpreg = (__HANDLE__)->Instance->SR;        \
00346     UNUSED(tmpreg);                             \
00347   } while(0U)
00348
00349 /** @brief Clears the I2S UDR pending flag.
00350   * @param  __HANDLE__: specifies the I2S Handle.
00351   * @retval None
00352   */
00353 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)     \
00354   do{                                           \
00355   __IO uint32_t tmpreg = 0x00U;                 \
00356   tmpreg = (__HANDLE__)->Instance->SR;          \
00357   UNUSED(tmpreg);                               \
00358   } while(0U)
00359 /**
00360   * @}
00361   */
00362
00363 /* Exported functions --------------------------------------------------------*/
00364 /** @addtogroup I2S_Exported_Functions
00365   * @{
00366   */
00367
00368 /** @addtogroup I2S_Exported_Functions_Group1
00369   * @{
00370   */
00371 /* Initialization/de-initialization functions  ********************************/
00372 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
00373 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
00374 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
00375 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
00376 /**
00377   * @}
00378   */
00379
00380 /** @addtogroup I2S_Exported_Functions_Group2
00381   * @{
00382   */
00383 /* I/O operation functions  ***************************************************/
00384 /* Blocking mode: Polling */
00385 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00386 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
00387
00388  /* Non-Blocking mode: Interrupt */
00389 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00390 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00391 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
00392
00393 /* Non-Blocking mode: DMA */
00394 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00395 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
00396
00397 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
00398 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
00399 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
00400
00401 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
00402 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00403 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
00404 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
00405 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
00406 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
00407 /**
00408   * @}
00409   */
00410
00411 /** @addtogroup I2S_Exported_Functions_Group3
00412   * @{
00413   */
00414 /* Peripheral Control and State functions  ************************************/
00415 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
00416 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
00417 /**
00418   * @}
00419   */
00420
00421 /**
00422   * @}
00423   */
00424
00425 /* Private types -------------------------------------------------------------*/
00426 /* Private variables ---------------------------------------------------------*/
00427 /* Private constants ---------------------------------------------------------*/
00428 /** @defgroup I2S_Private_Constants I2S Private Constants
00429   * @{
00430   */
00431
00432 /**
00433   * @}
00434   */
00435
00436 /* Private macros ------------------------------------------------------------*/
00437 /** @defgroup I2S_Private_Macros I2S Private Macros
00438   * @{
00439   */
00440 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX)  || \
00441                            ((MODE) == I2S_MODE_SLAVE_RX)  || \
00442                            ((MODE) == I2S_MODE_MASTER_TX) || \
00443                            ((MODE) == I2S_MODE_MASTER_RX))
00444
00445 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
00446                                    ((STANDARD) == I2S_STANDARD_MSB)       || \
00447                                    ((STANDARD) == I2S_STANDARD_LSB)       || \
00448                                    ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
00449                                    ((STANDARD) == I2S_STANDARD_PCM_LONG))
00450
00451 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
00452                                     ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
00453                                     ((FORMAT) == I2S_DATAFORMAT_24B)          || \
00454                                     ((FORMAT) == I2S_DATAFORMAT_32B))
00455
00456 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
00457                                     ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
00458
00459 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K)    && \
00460                                   ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
00461                                   ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
00462
00463 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
00464                            ((CPOL) == I2S_CPOL_HIGH))
00465 /**
00466   * @}
00467   */
00468
00469 /* Private Fonctions ---------------------------------------------------------*/
00470 /** @defgroup I2S_Private_Functions I2S Private Functions
00471   * @{
00472   */
00473 /* Private functions are defined in stm32f1xx_hal_i2s.c file */
00474 /**
00475   * @}
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /**
00483   * @}
00484   */
00485 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00486
00487 #ifdef __cplusplus
00488 }
00489 #endif
00490
00491 #endif /* __STM32F1xx_HAL_I2S_H */
00492
00493 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_irda.c Source File

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stm32f1xx_hal_irda.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_irda.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   IRDA HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the IrDA SIR ENDEC block (IrDA):
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     The IRDA HAL driver can be used as follows:
00020
00021     (#) Declare a IRDA_HandleTypeDef handle structure.
00022     (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
00023         (##) Enable the USARTx interface clock.
00024         (##) IRDA pins configuration:
00025             (+++) Enable the clock for the IRDA GPIOs.
00026             (+++) Configure the IRDA pins as alternate function pull-up.
00027         (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
00028              and HAL_IRDA_Receive_IT() APIs):
00029             (+++) Configure the USARTx interrupt priority.
00030             (+++) Enable the NVIC USART IRQ handle.
00031         (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
00032              and HAL_IRDA_Receive_DMA() APIs):
00033             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00034             (+++) Enable the DMAx interface clock.
00035             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00036             (+++) Configure the DMA Tx/Rx channel.
00037             (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00039             (+++) Configure the IRDAx interrupt priority and enable the NVIC USART IRQ handle
00040                   (used for last byte sending completion detection in DMA non circular mode)
00041
00042     (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
00043         and Mode(Receiver/Transmitter) in the hirda Init structure.
00044
00045     (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
00046         (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00047              by calling the customized HAL_IRDA_MspInit() API.
00048      [..]
00049         (@) The specific IRDA interrupts (Transmission complete interrupt,
00050              RXNE interrupt and Error Interrupts) will be managed using the macros
00051              __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
00052      [..]
00053         Three operation modes are available within this driver :
00054
00055      *** Polling mode IO operation ***
00056      =================================
00057      [..]
00058        (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
00059        (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
00060
00061      *** Interrupt mode IO operation ***
00062      ===================================
00063      [..]
00064        (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
00065        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
00066             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
00067        (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT()
00068        (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
00069             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
00070        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00071             add his own code by customization of function pointer HAL_IRDA_ErrorCallback
00072
00073      *** DMA mode IO operation ***
00074      ==============================
00075      [..]
00076        (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
00077        (+) At transmission end of half transfer HAL_IRDA_TxHalfCpltCallback is executed and user can
00078             add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback
00079        (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
00080             add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
00081        (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
00082        (+) At reception end of half transfer HAL_IRDA_RxHalfCpltCallback is executed and user can
00083             add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback
00084        (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
00085             add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
00086        (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
00087             add his own code by customization of function pointer HAL_IRDA_ErrorCallback
00088        (+) Pause the DMA Transfer using HAL_IRDA_DMAPause()
00089        (+) Resume the DMA Transfer using HAL_IRDA_DMAResume()
00090        (+) Stop the DMA Transfer using HAL_IRDA_DMAStop()
00091
00092      *** IRDA HAL driver macros list ***
00093      ====================================
00094      [..]
00095        Below the list of most used macros in IRDA HAL driver.
00096
00097        (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
00098        (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
00099        (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
00100        (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
00101        (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
00102        (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
00103        (+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not
00104
00105      [..]
00106        (@) You can refer to the IRDA HAL driver header file for more useful macros
00107   @endverbatim
00108      [..]
00109        (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
00110            in the data register is transmitted but is changed by the parity bit.
00111            Depending on the frame length defined by the M bit (8-bits or 9-bits),
00112            the possible IRDA frame formats are as listed in the following table:
00113     +-------------------------------------------------------------+
00114     |   M bit |  PCE bit  |            IRDA frame                 |
00115     |---------------------|---------------------------------------|
00116     |    0    |    0      |    | SB | 8 bit data | 1 STB |          |
00117     |---------|-----------|---------------------------------------|
00118     |    0    |    1      |    | SB | 7 bit data | PB | 1 STB |     |
00119     |---------|-----------|---------------------------------------|
00120     |    1    |    0      |    | SB | 9 bit data | 1 STB |          |
00121     |---------|-----------|---------------------------------------|
00122     |    1    |    1      |    | SB | 8 bit data | PB | 1 STB |     |
00123     +-------------------------------------------------------------+
00124   ******************************************************************************
00125   * @attention
00126   *
00127   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00128   *
00129   * Redistribution and use in source and binary forms, with or without modification,
00130   * are permitted provided that the following conditions are met:
00131   *   1. Redistributions of source code must retain the above copyright notice,
00132   *      this list of conditions and the following disclaimer.
00133   *   2. Redistributions in binary form must reproduce the above copyright notice,
00134   *      this list of conditions and the following disclaimer in the documentation
00135   *      and/or other materials provided with the distribution.
00136   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00137   *      may be used to endorse or promote products derived from this software
00138   *      without specific prior written permission.
00139   *
00140   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00141   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00142   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00143   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00144   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00145   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00146   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00147   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00148   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00149   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00150   *
00151   ******************************************************************************
00152   */
00153
00154 /* Includes ------------------------------------------------------------------*/
00155 #include "stm32f1xx_hal.h"
00156
00157 /** @addtogroup STM32F1xx_HAL_Driver
00158   * @{
00159   */
00160
00161 /** @defgroup IRDA IRDA
00162   * @brief HAL IRDA module driver
00163   * @{
00164   */
00165 #ifdef HAL_IRDA_MODULE_ENABLED
00166
00167 /* Private typedef -----------------------------------------------------------*/
00168 /* Private define ------------------------------------------------------------*/
00169 /** @addtogroup IRDA_Private_Constants
00170   * @{
00171   */
00172 /**
00173   * @}
00174   */
00175 /* Private macro -------------------------------------------------------------*/
00176 /* Private variables ---------------------------------------------------------*/
00177 /* Private function prototypes -----------------------------------------------*/
00178 /** @addtogroup IRDA_Private_Functions
00179   * @{
00180   */
00181 static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
00182 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
00183 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
00184 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
00185 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00186 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
00187 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00188 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
00189 static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
00190 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00191 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00192 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00193 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00194 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00195 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart,uint32_t Timeout);
00196 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
00197 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
00198 /**
00199   * @}
00200   */
00201 /* Exported functions ---------------------------------------------------------*/
00202 /** @defgroup IRDA_Exported_Functions IrDA Exported Functions
00203   * @{
00204   */
00205
00206 /** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
00207   *  @brief    Initialization and Configuration functions
00208   *
00209 @verbatim
00210   ==============================================================================
00211             ##### Initialization and Configuration functions #####
00212   ==============================================================================
00213     [..]
00214     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00215     in IrDA mode.
00216       (+) For the asynchronous mode only these parameters can be configured:
00217         (++) BaudRate
00218         (++) WordLength
00219         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00220              in the data register is transmitted but is changed by the parity bit.
00221              Depending on the frame length defined by the M bit (8-bits or 9-bits),
00222              please refer to Reference manual for possible IRDA frame formats.
00223         (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
00224              not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
00225              specification specifies a minimum of 10 ms delay between transmission and
00226              reception (IrDA is a half duplex protocol).
00227         (++) Mode: Receiver/transmitter modes
00228         (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
00229     [..]
00230     The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
00231     are available in reference manual).
00232
00233 @endverbatim
00234   * @{
00235   */
00236
00237 /**
00238   * @brief  Initializes the IRDA mode according to the specified
00239   *         parameters in the IRDA_InitTypeDef and create the associated handle.
00240   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00241   *                the configuration information for the specified IRDA module.
00242   * @retval HAL status
00243   */
00244 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
00245 {
00246   /* Check the IRDA handle allocation */
00247   if(hirda == NULL)
00248   {
00249     return HAL_ERROR;
00250   }
00251
00252   /* Check the parameters */
00253   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00254
00255   if(hirda->gState == HAL_IRDA_STATE_RESET)
00256   {
00257     /* Allocate lock resource and initialize it */
00258     hirda->Lock = HAL_UNLOCKED;
00259     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00260     HAL_IRDA_MspInit(hirda);
00261   }
00262
00263   hirda->gState = HAL_IRDA_STATE_BUSY;
00264
00265   /* Disable the IRDA peripheral */
00266   __HAL_IRDA_DISABLE(hirda);
00267
00268   /* Set the IRDA communication parameters */
00269   IRDA_SetConfig(hirda);
00270
00271   /* In IrDA mode, the following bits must be kept cleared:
00272   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
00273   - SCEN and HDSEL bits in the USART_CR3 register.*/
00274   CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN));
00275   CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
00276
00277   /* Enable the IRDA peripheral */
00278   __HAL_IRDA_ENABLE(hirda);
00279
00280   /* Set the prescaler */
00281   MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
00282
00283   /* Configure the IrDA mode */
00284   MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
00285
00286   /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
00287   SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
00288
00289   /* Initialize the IRDA state*/
00290   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00291   hirda->gState= HAL_IRDA_STATE_READY;
00292   hirda->RxState= HAL_IRDA_STATE_READY;
00293
00294   return HAL_OK;
00295 }
00296
00297 /**
00298   * @brief  DeInitializes the IRDA peripheral
00299   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00300   *                the configuration information for the specified IRDA module.
00301   * @retval HAL status
00302   */
00303 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
00304 {
00305   /* Check the IRDA handle allocation */
00306   if(hirda == NULL)
00307   {
00308     return HAL_ERROR;
00309   }
00310
00311   /* Check the parameters */
00312   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
00313
00314   hirda->gState = HAL_IRDA_STATE_BUSY;
00315
00316   /* Disable the Peripheral */
00317   __HAL_IRDA_DISABLE(hirda);
00318
00319   /* DeInit the low level hardware */
00320   HAL_IRDA_MspDeInit(hirda);
00321
00322   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00323   hirda->gState = HAL_IRDA_STATE_RESET;
00324   hirda->RxState = HAL_IRDA_STATE_RESET;
00325
00326   /* Release Lock */
00327   __HAL_UNLOCK(hirda);
00328
00329   return HAL_OK;
00330 }
00331
00332 /**
00333   * @brief  IRDA MSP Init.
00334   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00335   *                the configuration information for the specified IRDA module.
00336   * @retval None
00337   */
00338 __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
00339 {
00340   /* Prevent unused argument(s) compilation warning */
00341   UNUSED(hirda);
00342   /* NOTE: This function should not be modified, when the callback is needed,
00343            the HAL_IRDA_MspInit can be implemented in the user file
00344   */
00345 }
00346
00347 /**
00348   * @brief  IRDA MSP DeInit.
00349   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00350   *                the configuration information for the specified IRDA module.
00351   * @retval None
00352   */
00353 __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
00354 {
00355   /* Prevent unused argument(s) compilation warning */
00356   UNUSED(hirda);
00357   /* NOTE: This function should not be modified, when the callback is needed,
00358            the HAL_IRDA_MspDeInit can be implemented in the user file
00359   */
00360 }
00361
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup IRDA_Exported_Functions_Group2 IO operation functions
00367   *  @brief   IRDA Transmit and Receive functions
00368   *
00369 @verbatim
00370   ==============================================================================
00371                          ##### IO operation functions #####
00372   ==============================================================================
00373   [..]
00374     This subsection provides a set of functions allowing to manage the IRDA data transfers.
00375     IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
00376     on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
00377     is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
00378     While receiving data, transmission should be avoided as the data to be transmitted
00379     could be corrupted.
00380
00381     (#) There are two modes of transfer:
00382         (++) Blocking mode: The communication is performed in polling mode.
00383              The HAL status of all data processing is returned by the same function
00384              after finishing transfer.
00385         (++) No-Blocking mode: The communication is performed using Interrupts
00386              or DMA, these APIs return the HAL status.
00387              The end of the data processing will be indicated through the
00388              dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
00389              using DMA mode.
00390              The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks
00391              will be executed respectively at the end of the transmit or Receive process
00392              The HAL_IRDA_ErrorCallback() user callback will be executed when a communication
00393              error is detected
00394
00395     (#) Blocking mode APIs are:
00396         (++) HAL_IRDA_Transmit()
00397         (++) HAL_IRDA_Receive()
00398
00399     (#) Non Blocking mode APIs with Interrupt are:
00400         (++) HAL_IRDA_Transmit_IT()
00401         (++) HAL_IRDA_Receive_IT()
00402         (++) HAL_IRDA_IRQHandler()
00403
00404     (#) Non Blocking mode functions with DMA are:
00405         (++) HAL_IRDA_Transmit_DMA()
00406         (++) HAL_IRDA_Receive_DMA()
00407         (++) HAL_IRDA_DMAPause()
00408         (++) HAL_IRDA_DMAResume()
00409         (++) HAL_IRDA_DMAStop()
00410
00411     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00412         (++) HAL_IRDA_TxHalfCpltCallback()
00413         (++) HAL_IRDA_TxCpltCallback()
00414         (++) HAL_IRDA_RxHalfCpltCallback()
00415         (++) HAL_IRDA_RxCpltCallback()
00416         (++) HAL_IRDA_ErrorCallback()
00417
00418 @endverbatim
00419   * @{
00420   */
00421
00422 /**
00423   * @brief  Sends an amount of data in blocking mode.
00424   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00425   *                the configuration information for the specified IRDA module.
00426   * @param  pData: Pointer to data buffer
00427   * @param  Size: Amount of data to be sent
00428   * @param  Timeout: Specify timeout value
00429   * @retval HAL status
00430   */
00431 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00432 {
00433   uint16_t* tmp;
00434   uint32_t tickstart = 0U;
00435
00436   /* Check that a Tx process is not already ongoing */
00437   if(hirda->gState == HAL_IRDA_STATE_READY)
00438   {
00439     if((pData == NULL) || (Size == 0U))
00440     {
00441       return  HAL_ERROR;
00442     }
00443
00444     /* Process Locked */
00445     __HAL_LOCK(hirda);
00446
00447     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00448     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00449
00450     /* Init tickstart for timeout managment */
00451     tickstart = HAL_GetTick();
00452
00453     hirda->TxXferSize = Size;
00454     hirda->TxXferCount = Size;
00455     while(hirda->TxXferCount > 0U)
00456     {
00457       hirda->TxXferCount--;
00458       if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
00459       {
00460         if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00461         {
00462           return HAL_TIMEOUT;
00463         }
00464         tmp = (uint16_t*) pData;
00465         hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
00466         if(hirda->Init.Parity == IRDA_PARITY_NONE)
00467         {
00468           pData +=2U;
00469         }
00470         else
00471         {
00472           pData +=1U;
00473         }
00474       }
00475       else
00476       {
00477         if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00478         {
00479           return HAL_TIMEOUT;
00480         }
00481         hirda->Instance->DR = (*pData++ & (uint8_t)0xFF);
00482       }
00483     }
00484
00485     if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00486     {
00487       return HAL_TIMEOUT;
00488     }
00489
00490     /* At end of Tx process, restore hirda->gState to Ready */
00491     hirda->gState = HAL_IRDA_STATE_READY;
00492
00493     /* Process Unlocked */
00494     __HAL_UNLOCK(hirda);
00495
00496     return HAL_OK;
00497   }
00498   else
00499   {
00500     return HAL_BUSY;
00501   }
00502 }
00503
00504 /**
00505   * @brief  Receive an amount of data in blocking mode.
00506   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00507   *                the configuration information for the specified IRDA module.
00508   * @param  pData: Pointer to data buffer
00509   * @param  Size: Amount of data to be received
00510   * @param  Timeout: Specify timeout value
00511   * @retval HAL status
00512   */
00513 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00514 {
00515   uint16_t* tmp;
00516   uint32_t tickstart = 0U;
00517
00518   /* Check that a Rx process is not already ongoing */
00519   if(hirda->RxState == HAL_IRDA_STATE_READY)
00520   {
00521     if((pData == NULL) || (Size == 0U))
00522     {
00523       return  HAL_ERROR;
00524     }
00525
00526     /* Process Locked */
00527     __HAL_LOCK(hirda);
00528
00529     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00530     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00531
00532     /* Init tickstart for timeout managment */
00533     tickstart = HAL_GetTick();
00534
00535     hirda->RxXferSize = Size;
00536     hirda->RxXferCount = Size;
00537
00538     /* Check the remain data to be received */
00539     while(hirda->RxXferCount > 0U)
00540     {
00541       hirda->RxXferCount--;
00542       if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
00543       {
00544         if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00545         {
00546           return HAL_TIMEOUT;
00547         }
00548         tmp = (uint16_t*)pData;
00549         if(hirda->Init.Parity == IRDA_PARITY_NONE)
00550         {
00551           *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
00552           pData +=2U;
00553         }
00554         else
00555         {
00556           *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
00557           pData +=1U;
00558         }
00559       }
00560       else
00561       {
00562         if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00563         {
00564           return HAL_TIMEOUT;
00565         }
00566         if(hirda->Init.Parity == IRDA_PARITY_NONE)
00567         {
00568           *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
00569         }
00570         else
00571         {
00572           *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
00573         }
00574       }
00575     }
00576
00577     /* At end of Rx process, restore hirda->RxState to Ready */
00578     hirda->RxState = HAL_IRDA_STATE_READY;
00579
00580     /* Process Unlocked */
00581     __HAL_UNLOCK(hirda);
00582
00583     return HAL_OK;
00584   }
00585   else
00586   {
00587     return HAL_BUSY;
00588   }
00589 }
00590
00591 /**
00592   * @brief  Sends an amount of data in non blocking mode.
00593   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00594   *                the configuration information for the specified IRDA module.
00595   * @param  pData: Pointer to data buffer
00596   * @param  Size: Amount of data to be sent
00597   * @retval HAL status
00598   */
00599 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00600 {
00601   /* Check that a Tx process is not already ongoing */
00602   if(hirda->gState == HAL_IRDA_STATE_READY)
00603   {
00604     if((pData == NULL) || (Size == 0U))
00605     {
00606       return HAL_ERROR;
00607     }
00608     /* Process Locked */
00609     __HAL_LOCK(hirda);
00610
00611     hirda->pTxBuffPtr = pData;
00612     hirda->TxXferSize = Size;
00613     hirda->TxXferCount = Size;
00614
00615     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00616     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00617
00618     /* Process Unlocked */
00619     __HAL_UNLOCK(hirda);
00620
00621     /* Enable the IRDA Transmit data register empty Interrupt */
00622     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
00623
00624     return HAL_OK;
00625   }
00626   else
00627   {
00628     return HAL_BUSY;
00629   }
00630 }
00631
00632 /**
00633   * @brief  Receives an amount of data in non blocking mode.
00634   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00635   *                the configuration information for the specified IRDA module.
00636   * @param  pData: Pointer to data buffer
00637   * @param  Size: Amount of data to be received
00638   * @retval HAL status
00639   */
00640 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00641 {
00642   /* Check that a Rx process is not already ongoing */
00643   if(hirda->RxState == HAL_IRDA_STATE_READY)
00644   {
00645     if((pData == NULL) || (Size == 0U))
00646     {
00647       return HAL_ERROR;
00648     }
00649
00650     /* Process Locked */
00651     __HAL_LOCK(hirda);
00652
00653     hirda->pRxBuffPtr = pData;
00654     hirda->RxXferSize = Size;
00655     hirda->RxXferCount = Size;
00656
00657     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00658     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00659
00660     /* Process Unlocked */
00661     __HAL_UNLOCK(hirda);
00662
00663     /* Enable the IRDA Parity Error Interrupt */
00664     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
00665
00666     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00667     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
00668
00669     /* Enable the IRDA Data Register not empty Interrupt */
00670     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
00671
00672     return HAL_OK;
00673   }
00674   else
00675   {
00676     return HAL_BUSY;
00677   }
00678 }
00679
00680 /**
00681   * @brief  Sends an amount of data in non blocking mode.
00682   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00683   *                the configuration information for the specified IRDA module.
00684   * @param  pData: Pointer to data buffer
00685   * @param  Size: Amount of data to be sent
00686   * @retval HAL status
00687   */
00688 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00689 {
00690   uint32_t *tmp;
00691
00692   /* Check that a Tx process is not already ongoing */
00693   if(hirda->gState == HAL_IRDA_STATE_READY)
00694   {
00695     if((pData == NULL) || (Size == 0U))
00696     {
00697       return HAL_ERROR;
00698     }
00699
00700     /* Process Locked */
00701     __HAL_LOCK(hirda);
00702
00703     hirda->pTxBuffPtr = pData;
00704     hirda->TxXferSize = Size;
00705     hirda->TxXferCount = Size;
00706
00707     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00708     hirda->gState = HAL_IRDA_STATE_BUSY_TX;
00709
00710     /* Set the IRDA DMA transfer complete callback */
00711     hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
00712
00713     /* Set the IRDA DMA half transfer complete callback */
00714     hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
00715
00716     /* Set the DMA error callback */
00717     hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
00718
00719     /* Set the DMA abort callback */
00720     hirda->hdmatx->XferAbortCallback = NULL;
00721
00722     /* Enable the IRDA transmit DMA Channel */
00723     tmp = (uint32_t*)&pData;
00724     HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
00725
00726     /* Clear the TC flag in the SR register by writing 0 to it */
00727     __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
00728
00729     /* Process Unlocked */
00730     __HAL_UNLOCK(hirda);
00731
00732     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00733        in the USART CR3 register */
00734     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00735
00736     return HAL_OK;
00737   }
00738   else
00739   {
00740     return HAL_BUSY;
00741   }
00742 }
00743
00744 /**
00745   * @brief  Receives an amount of data in non blocking mode.
00746   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00747   *                the configuration information for the specified IRDA module.
00748   * @param  pData: Pointer to data buffer
00749   * @param  Size: Amount of data to be received
00750   * @note   When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
00751   * @retval HAL status
00752   */
00753 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
00754 {
00755   uint32_t *tmp;
00756
00757   /* Check that a Rx process is not already ongoing */
00758   if(hirda->RxState == HAL_IRDA_STATE_READY)
00759   {
00760     if((pData == NULL) || (Size == 0U))
00761     {
00762       return HAL_ERROR;
00763     }
00764
00765     /* Process Locked */
00766     __HAL_LOCK(hirda);
00767
00768     hirda->pRxBuffPtr = pData;
00769     hirda->RxXferSize = Size;
00770
00771     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00772     hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
00773
00774     /* Set the IRDA DMA transfer complete callback */
00775     hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
00776
00777     /* Set the IRDA DMA half transfer complete callback */
00778     hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
00779
00780     /* Set the DMA error callback */
00781     hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
00782
00783     /* Set the DMA abort callback */
00784     hirda->hdmarx->XferAbortCallback = NULL;
00785
00786     /* Enable the DMA channel */
00787     tmp = (uint32_t*)&pData;
00788     HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
00789
00790     /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
00791     __HAL_IRDA_CLEAR_OREFLAG(hirda);
00792
00793     /* Process Unlocked */
00794     __HAL_UNLOCK(hirda);
00795
00796     /* Enable the IRDA Parity Error Interrupt */
00797     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
00798
00799     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
00800     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00801
00802     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00803     in the USART CR3 register */
00804     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00805
00806     return HAL_OK;
00807   }
00808   else
00809   {
00810     return HAL_BUSY;
00811   }
00812 }
00813
00814 /**
00815   * @brief Pauses the DMA Transfer.
00816   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00817   *                the configuration information for the specified IRDA module.
00818   * @retval HAL status
00819   */
00820 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
00821 {
00822   uint32_t dmarequest = 0x00U;
00823
00824   /* Process Locked */
00825   __HAL_LOCK(hirda);
00826
00827   dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
00828   if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
00829   {
00830     /* Disable the IRDA DMA Tx request */
00831     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00832   }
00833
00834   dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
00835   if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
00836   {
00837     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
00838     CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
00839     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00840
00841     /* Disable the IRDA DMA Rx request */
00842     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00843   }
00844
00845   /* Process Unlocked */
00846   __HAL_UNLOCK(hirda);
00847
00848   return HAL_OK;
00849 }
00850
00851 /**
00852   * @brief Resumes the DMA Transfer.
00853   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00854   *                the configuration information for the specified IRDA module.
00855   * @retval HAL status
00856   */
00857 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
00858 {
00859   /* Process Locked */
00860   __HAL_LOCK(hirda);
00861
00862   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
00863   {
00864     /* Enable the IRDA DMA Tx request */
00865     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00866   }
00867
00868   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
00869   {
00870     /* Clear the Overrun flag before resuming the Rx transfer */
00871     __HAL_IRDA_CLEAR_OREFLAG(hirda);
00872
00873     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
00874     SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
00875     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00876
00877     /* Enable the IRDA DMA Rx request */
00878     SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00879   }
00880
00881   /* Process Unlocked */
00882   __HAL_UNLOCK(hirda);
00883
00884   return HAL_OK;
00885 }
00886
00887 /**
00888   * @brief Stops the DMA Transfer.
00889   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
00890   *                the configuration information for the specified IRDA module.
00891   * @retval HAL status
00892   */
00893 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
00894 {
00895   uint32_t dmarequest = 0x00U;
00896   /* The Lock is not implemented on this API to allow the user application
00897   to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
00898   when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
00899   and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
00900   */
00901
00902   /* Stop IRDA DMA Tx request if ongoing */
00903   dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
00904   if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
00905   {
00906     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00907
00908     /* Abort the IRDA DMA Tx channel */
00909     if(hirda->hdmatx != NULL)
00910     {
00911       HAL_DMA_Abort(hirda->hdmatx);
00912     }
00913     IRDA_EndTxTransfer(hirda);
00914   }
00915
00916   /* Stop IRDA DMA Rx request if ongoing */
00917   dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
00918   if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
00919   {
00920     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00921
00922     /* Abort the IRDA DMA Rx channel */
00923     if(hirda->hdmarx != NULL)
00924     {
00925       HAL_DMA_Abort(hirda->hdmarx);
00926     }
00927     IRDA_EndRxTransfer(hirda);
00928   }
00929
00930   return HAL_OK;
00931 }
00932
00933 /**
00934   * @brief  Abort ongoing transfers (blocking mode).
00935   * @param  hirda IRDA handle.
00936   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
00937   *         This procedure performs following operations :
00938   *           - Disable PPP Interrupts
00939   *           - Disable the DMA transfer in the peripheral register (if enabled)
00940   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00941   *           - Set handle State to READY
00942   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00943   * @retval HAL status
00944 */
00945 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
00946 {
00947   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
00948   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
00949   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
00950
00951   /* Disable the IRDA DMA Tx request if enabled */
00952   if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
00953   {
00954     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
00955
00956     /* Abort the IRDA DMA Tx channel: use blocking DMA Abort API (no callback) */
00957     if(hirda->hdmatx != NULL)
00958     {
00959       /* Set the IRDA DMA Abort callback to Null.
00960          No call back execution at end of DMA abort procedure */
00961       hirda->hdmatx->XferAbortCallback = NULL;
00962
00963       HAL_DMA_Abort(hirda->hdmatx);
00964     }
00965   }
00966
00967   /* Disable the IRDA DMA Rx request if enabled */
00968   if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
00969   {
00970     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
00971
00972     /* Abort the IRDA DMA Rx channel: use blocking DMA Abort API (no callback) */
00973     if(hirda->hdmarx != NULL)
00974     {
00975       /* Set the IRDA DMA Abort callback to Null.
00976          No call back execution at end of DMA abort procedure */
00977       hirda->hdmarx->XferAbortCallback = NULL;
00978
00979       HAL_DMA_Abort(hirda->hdmarx);
00980     }
00981   }
00982
00983   /* Reset Tx and Rx transfer counters */
00984   hirda->TxXferCount = 0x00U;
00985   hirda->RxXferCount = 0x00U;
00986
00987   /* Reset ErrorCode */
00988   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
00989
00990   /* Restore hirda->RxState and hirda->gState to Ready */
00991   hirda->RxState = HAL_IRDA_STATE_READY;
00992   hirda->gState = HAL_IRDA_STATE_READY;
00993
00994   return HAL_OK;
00995 }
00996
00997 /**
00998   * @brief  Abort ongoing Transmit transfer (blocking mode).
00999   * @param  hirda IRDA handle.
01000   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01001   *         This procedure performs following operations :
01002   *           - Disable PPP Interrupts
01003   *           - Disable the DMA transfer in the peripheral register (if enabled)
01004   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01005   *           - Set handle State to READY
01006   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01007   * @retval HAL status
01008 */
01009 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
01010 {
01011   /* Disable TXEIE and TCIE interrupts */
01012   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01013
01014   /* Disable the IRDA DMA Tx request if enabled */
01015   if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01016   {
01017     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01018
01019     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01020     if(hirda->hdmatx != NULL)
01021     {
01022       /* Set the IRDA DMA Abort callback to Null.
01023          No call back execution at end of DMA abort procedure */
01024       hirda->hdmatx->XferAbortCallback = NULL;
01025
01026       HAL_DMA_Abort(hirda->hdmatx);
01027     }
01028   }
01029
01030   /* Reset Tx transfer counter */
01031   hirda->TxXferCount = 0x00U;
01032
01033   /* Restore hirda->gState to Ready */
01034   hirda->gState = HAL_IRDA_STATE_READY;
01035
01036   return HAL_OK;
01037 }
01038
01039 /**
01040   * @brief  Abort ongoing Receive transfer (blocking mode).
01041   * @param  hirda IRDA handle.
01042   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01043   *         This procedure performs following operations :
01044   *           - Disable PPP Interrupts
01045   *           - Disable the DMA transfer in the peripheral register (if enabled)
01046   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01047   *           - Set handle State to READY
01048   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01049   * @retval HAL status
01050 */
01051 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
01052 {
01053   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01054   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01055   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01056
01057   /* Disable the IRDA DMA Rx request if enabled */
01058   if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01059   {
01060     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01061
01062     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01063     if(hirda->hdmarx != NULL)
01064     {
01065       /* Set the IRDA DMA Abort callback to Null.
01066          No call back execution at end of DMA abort procedure */
01067       hirda->hdmarx->XferAbortCallback = NULL;
01068
01069       HAL_DMA_Abort(hirda->hdmarx);
01070     }
01071   }
01072
01073   /* Reset Rx transfer counter */
01074   hirda->RxXferCount = 0x00U;
01075
01076   /* Restore hirda->RxState to Ready */
01077   hirda->RxState = HAL_IRDA_STATE_READY;
01078
01079   return HAL_OK;
01080 }
01081
01082 /**
01083   * @brief  Abort ongoing transfers (Interrupt mode).
01084   * @param  hirda IRDA handle.
01085   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01086   *         This procedure performs following operations :
01087   *           - Disable PPP Interrupts
01088   *           - Disable the DMA transfer in the peripheral register (if enabled)
01089   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01090   *           - Set handle State to READY
01091   *           - At abort completion, call user abort complete callback
01092   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01093   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01094   * @retval HAL status
01095 */
01096 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
01097 {
01098   uint32_t AbortCplt = 0x01U;
01099
01100   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01101   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01102   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01103
01104   /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
01105      before any call to DMA Abort functions */
01106   /* DMA Tx Handle is valid */
01107   if(hirda->hdmatx != NULL)
01108   {
01109     /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
01110        Otherwise, set it to NULL */
01111     if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01112     {
01113       hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
01114     }
01115     else
01116     {
01117       hirda->hdmatx->XferAbortCallback = NULL;
01118     }
01119   }
01120   /* DMA Rx Handle is valid */
01121   if(hirda->hdmarx != NULL)
01122   {
01123     /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
01124        Otherwise, set it to NULL */
01125     if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01126     {
01127       hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
01128     }
01129     else
01130     {
01131       hirda->hdmarx->XferAbortCallback = NULL;
01132     }
01133   }
01134
01135   /* Disable the IRDA DMA Tx request if enabled */
01136   if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01137   {
01138     /* Disable DMA Tx at IRDA level */
01139     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01140
01141     /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
01142     if(hirda->hdmatx != NULL)
01143     {
01144       /* IRDA Tx DMA Abort callback has already been initialised :
01145          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01146
01147       /* Abort DMA TX */
01148       if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01149       {
01150         hirda->hdmatx->XferAbortCallback = NULL;
01151       }
01152       else
01153       {
01154         AbortCplt = 0x00U;
01155       }
01156     }
01157   }
01158
01159   /* Disable the IRDA DMA Rx request if enabled */
01160   if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01161   {
01162     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01163
01164     /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
01165     if(hirda->hdmarx != NULL)
01166     {
01167       /* IRDA Rx DMA Abort callback has already been initialised :
01168          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01169
01170       /* Abort DMA RX */
01171       if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01172       {
01173         hirda->hdmarx->XferAbortCallback = NULL;
01174         AbortCplt = 0x01U;
01175       }
01176       else
01177       {
01178         AbortCplt = 0x00U;
01179       }
01180     }
01181   }
01182
01183   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01184   if(AbortCplt == 0x01U)
01185   {
01186     /* Reset Tx and Rx transfer counters */
01187     hirda->TxXferCount = 0x00U;
01188     hirda->RxXferCount = 0x00U;
01189
01190     /* Reset ErrorCode */
01191     hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01192
01193     /* Restore hirda->gState and hirda->RxState to Ready */
01194     hirda->gState  = HAL_IRDA_STATE_READY;
01195     hirda->RxState = HAL_IRDA_STATE_READY;
01196
01197     /* As no DMA to be aborted, call directly user Abort complete callback */
01198     HAL_IRDA_AbortCpltCallback(hirda);
01199   }
01200
01201   return HAL_OK;
01202 }
01203
01204 /**
01205   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01206   * @param  hirda IRDA handle.
01207   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01208   *         This procedure performs following operations :
01209   *           - Disable PPP Interrupts
01210   *           - Disable the DMA transfer in the peripheral register (if enabled)
01211   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01212   *           - Set handle State to READY
01213   *           - At abort completion, call user abort complete callback
01214   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01215   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01216   * @retval HAL status
01217 */
01218 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
01219 {
01220   /* Disable TXEIE and TCIE interrupts */
01221   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01222
01223   /* Disable the IRDA DMA Tx request if enabled */
01224   if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
01225   {
01226     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01227
01228     /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
01229     if(hirda->hdmatx != NULL)
01230     {
01231       /* Set the IRDA DMA Abort callback :
01232          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01233       hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
01234
01235       /* Abort DMA TX */
01236       if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
01237       {
01238         /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
01239         hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
01240       }
01241     }
01242     else
01243     {
01244       /* Reset Tx transfer counter */
01245       hirda->TxXferCount = 0x00U;
01246
01247       /* Restore hirda->gState to Ready */
01248       hirda->gState = HAL_IRDA_STATE_READY;
01249
01250       /* As no DMA to be aborted, call directly user Abort complete callback */
01251       HAL_IRDA_AbortTransmitCpltCallback(hirda);
01252     }
01253   }
01254   else
01255   {
01256     /* Reset Tx transfer counter */
01257     hirda->TxXferCount = 0x00U;
01258
01259     /* Restore hirda->gState to Ready */
01260     hirda->gState = HAL_IRDA_STATE_READY;
01261
01262     /* As no DMA to be aborted, call directly user Abort complete callback */
01263     HAL_IRDA_AbortTransmitCpltCallback(hirda);
01264   }
01265
01266   return HAL_OK;
01267 }
01268
01269 /**
01270   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01271   * @param  hirda IRDA handle.
01272   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01273   *         This procedure performs following operations :
01274   *           - Disable PPP Interrupts
01275   *           - Disable the DMA transfer in the peripheral register (if enabled)
01276   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01277   *           - Set handle State to READY
01278   *           - At abort completion, call user abort complete callback
01279   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01280   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01281   * @retval HAL status
01282 */
01283 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
01284 {
01285   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01286   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01287   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01288
01289   /* Disable the IRDA DMA Rx request if enabled */
01290   if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01291   {
01292     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01293
01294     /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
01295     if(hirda->hdmarx != NULL)
01296     {
01297       /* Set the IRDA DMA Abort callback :
01298          will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
01299       hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
01300
01301       /* Abort DMA RX */
01302       if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01303       {
01304         /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
01305         hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01306       }
01307     }
01308     else
01309     {
01310       /* Reset Rx transfer counter */
01311       hirda->RxXferCount = 0x00U;
01312
01313       /* Restore hirda->RxState to Ready */
01314       hirda->RxState = HAL_IRDA_STATE_READY;
01315
01316       /* As no DMA to be aborted, call directly user Abort complete callback */
01317       HAL_IRDA_AbortReceiveCpltCallback(hirda);
01318     }
01319   }
01320   else
01321   {
01322     /* Reset Rx transfer counter */
01323     hirda->RxXferCount = 0x00U;
01324
01325     /* Restore hirda->RxState to Ready */
01326     hirda->RxState = HAL_IRDA_STATE_READY;
01327
01328     /* As no DMA to be aborted, call directly user Abort complete callback */
01329     HAL_IRDA_AbortReceiveCpltCallback(hirda);
01330   }
01331
01332   return HAL_OK;
01333 }
01334
01335 /**
01336   * @brief  This function handles IRDA interrupt request.
01337   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01338   *                the configuration information for the specified IRDA module.
01339   * @retval None
01340   */
01341 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
01342 {
01343    uint32_t isrflags   = READ_REG(hirda->Instance->SR);
01344    uint32_t cr1its     = READ_REG(hirda->Instance->CR1);
01345    uint32_t cr3its     = READ_REG(hirda->Instance->CR3);
01346    uint32_t errorflags = 0x00U;
01347    uint32_t dmarequest = 0x00U;
01348
01349   /* If no error occurs */
01350   errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
01351   if(errorflags == RESET)
01352   {
01353     /* IRDA in mode Receiver -----------------------------------------------*/
01354     if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01355     {
01356       IRDA_Receive_IT(hirda);
01357       return;
01358     }
01359   }
01360
01361   /* If some errors occur */
01362   if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
01363   {
01364     /* IRDA parity error interrupt occurred -------------------------------*/
01365     if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01366     {
01367       hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
01368     }
01369
01370     /* IRDA noise error interrupt occurred --------------------------------*/
01371     if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01372     {
01373       hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
01374     }
01375
01376     /* IRDA frame error interrupt occurred --------------------------------*/
01377     if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01378     {
01379       hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
01380     }
01381
01382     /* IRDA Over-Run interrupt occurred -----------------------------------*/
01383     if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01384     {
01385       hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
01386     }
01387     /* Call IRDA Error Call back function if need be -----------------------*/
01388     if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
01389     {
01390       /* IRDA in mode Receiver ---------------------------------------------*/
01391       if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01392       {
01393         IRDA_Receive_IT(hirda);
01394       }
01395
01396       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01397          consider error as blocking */
01398       dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
01399       if(((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
01400       {
01401         /* Blocking error : transfer is aborted
01402            Set the IRDA state ready to be able to start again the process,
01403            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01404         IRDA_EndRxTransfer(hirda);
01405
01406         /* Disable the IRDA DMA Rx request if enabled */
01407         if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
01408         {
01409           CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01410
01411           /* Abort the IRDA DMA Rx channel */
01412           if(hirda->hdmarx != NULL)
01413           {
01414             /* Set the IRDA DMA Abort callback :
01415             will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
01416             hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
01417
01418             if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
01419             {
01420               /* Call Directly XferAbortCallback function in case of error */
01421               hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
01422             }
01423           }
01424           else
01425           {
01426             /* Call user error callback */
01427             HAL_IRDA_ErrorCallback(hirda);
01428           }
01429         }
01430         else
01431         {
01432           /* Call user error callback */
01433           HAL_IRDA_ErrorCallback(hirda);
01434         }
01435       }
01436       else
01437       {
01438         /* Non Blocking error : transfer could go on.
01439            Error is notified to user through user error callback */
01440         HAL_IRDA_ErrorCallback(hirda);
01441         hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01442       }
01443     }
01444     return;
01445   } /* End if some error occurs */
01446
01447   /* IRDA in mode Transmitter ------------------------------------------------*/
01448   if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01449   {
01450     IRDA_Transmit_IT(hirda);
01451     return;
01452   }
01453
01454   /* IRDA in mode Transmitter end --------------------------------------------*/
01455   if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01456   {
01457     IRDA_EndTransmit_IT(hirda);
01458     return;
01459   }
01460 }
01461
01462 /**
01463   * @brief  Tx Transfer complete callbacks.
01464   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01465   *                the configuration information for the specified IRDA module.
01466   * @retval None
01467   */
01468 __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
01469 {
01470   /* Prevent unused argument(s) compilation warning */
01471   UNUSED(hirda);
01472   /* NOTE: This function should not be modified, when the callback is needed,
01473            the HAL_IRDA_TxCpltCallback can be implemented in the user file
01474   */
01475 }
01476
01477 /**
01478   * @brief  Tx Half Transfer completed callbacks.
01479   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01480   *                the configuration information for the specified USART module.
01481   * @retval None
01482   */
01483 __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
01484 {
01485   /* Prevent unused argument(s) compilation warning */
01486   UNUSED(hirda);
01487   /* NOTE: This function should not be modified, when the callback is needed,
01488            the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
01489   */
01490 }
01491
01492 /**
01493   * @brief  Rx Transfer complete callbacks.
01494   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01495   *                the configuration information for the specified IRDA module.
01496   * @retval None
01497   */
01498 __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
01499 {
01500   /* Prevent unused argument(s) compilation warning */
01501   UNUSED(hirda);
01502   /* NOTE: This function should not be modified, when the callback is needed,
01503            the HAL_IRDA_RxCpltCallback can be implemented in the user file
01504   */
01505 }
01506
01507 /**
01508   * @brief  Rx Half Transfer complete callbacks.
01509   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01510   *                the configuration information for the specified IRDA module.
01511   * @retval None
01512   */
01513 __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
01514 {
01515   /* Prevent unused argument(s) compilation warning */
01516   UNUSED(hirda);
01517   /* NOTE : This function should not be modified, when the callback is needed,
01518             the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
01519   */
01520 }
01521
01522 /**
01523   * @brief IRDA error callbacks.
01524   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01525   *                the configuration information for the specified IRDA module.
01526   * @retval None
01527   */
01528 __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
01529 {
01530   /* Prevent unused argument(s) compilation warning */
01531   UNUSED(hirda);
01532   /* NOTE : This function Should not be modified, when the callback is needed,
01533   the HAL_IRDA_ErrorCallback could be implemented in the user file
01534   */
01535 }
01536
01537 /**
01538   * @brief  IRDA Abort Complete callback.
01539   * @param  hirda IRDA handle.
01540   * @retval None
01541   */
01542 __weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
01543 {
01544   /* Prevent unused argument(s) compilation warning */
01545   UNUSED(hirda);
01546
01547   /* NOTE : This function should not be modified, when the callback is needed,
01548             the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
01549    */
01550 }
01551
01552 /**
01553   * @brief  IRDA Abort Transmit Complete callback.
01554   * @param  hirda IRDA handle.
01555   * @retval None
01556   */
01557 __weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
01558 {
01559   /* Prevent unused argument(s) compilation warning */
01560   UNUSED(hirda);
01561
01562   /* NOTE : This function should not be modified, when the callback is needed,
01563             the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
01564    */
01565 }
01566
01567 /**
01568   * @brief  IRDA Abort ReceiveComplete callback.
01569   * @param  hirda IRDA handle.
01570   * @retval None
01571   */
01572 __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
01573 {
01574   /* Prevent unused argument(s) compilation warning */
01575   UNUSED(hirda);
01576
01577   /* NOTE : This function should not be modified, when the callback is needed,
01578             the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
01579    */
01580 }
01581
01582 /**
01583   * @}
01584   */
01585
01586 /** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
01587   *  @brief   IRDA State and Errors functions
01588   *
01589 @verbatim
01590   ==============================================================================
01591                   ##### Peripheral State and Errors functions #####
01592   ==============================================================================
01593   [..]
01594     This subsection provides a set of functions allowing to return the State of IrDA
01595     communication process and also return Peripheral Errors occurred during communication process
01596      (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
01597      (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
01598
01599 @endverbatim
01600   * @{
01601   */
01602
01603 /**
01604   * @brief  Returns the IRDA state.
01605   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01606   *                the configuration information for the specified IRDA module.
01607   * @retval HAL state
01608   */
01609 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
01610 {
01611   uint32_t temp1 = 0x00U, temp2 = 0x00U;
01612   temp1 = hirda->gState;
01613   temp2 = hirda->RxState;
01614
01615   return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
01616 }
01617
01618 /**
01619   * @brief  Return the IRDA error code
01620   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01621   *                the configuration information for the specified IRDA module.
01622   * @retval IRDA Error Code
01623   */
01624 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
01625 {
01626   return hirda->ErrorCode;
01627 }
01628
01629 /**
01630   * @}
01631   */
01632
01633 /**
01634   * @brief  DMA IRDA transmit process complete callback.
01635   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01636   *               the configuration information for the specified DMA module.
01637   * @retval None
01638   */
01639 static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01640 {
01641   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01642   /* DMA Normal mode */
01643   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
01644   {
01645     hirda->TxXferCount = 0U;
01646
01647     /* Disable the DMA transfer for transmit request by setting the DMAT bit
01648     in the IRDA CR3 register */
01649     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
01650
01651     /* Enable the IRDA Transmit Complete Interrupt */
01652     __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
01653   }
01654   /* DMA Circular mode */
01655   else
01656   {
01657     HAL_IRDA_TxCpltCallback(hirda);
01658   }
01659 }
01660
01661 /**
01662   * @brief DMA IRDA receive process half complete callback
01663   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01664   *                the configuration information for the specified DMA module.
01665   * @retval None
01666   */
01667 static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
01668 {
01669   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01670
01671   HAL_IRDA_TxHalfCpltCallback(hirda);
01672 }
01673
01674 /**
01675   * @brief  DMA IRDA receive process complete callback.
01676   * @param  hdma: DMA handle
01677   * @retval None
01678   */
01679 static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01680 {
01681   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01682   /* DMA Normal mode */
01683   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
01684   {
01685     hirda->RxXferCount = 0U;
01686
01687     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
01688     CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
01689     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01690
01691     /* Disable the DMA transfer for the receiver request by setting the DMAR bit
01692     in the IRDA CR3 register */
01693     CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
01694
01695     /* At end of Rx process, restore hirda->RxState to Ready */
01696     hirda->RxState = HAL_IRDA_STATE_READY;
01697   }
01698   HAL_IRDA_RxCpltCallback(hirda);
01699 }
01700
01701 /**
01702   * @brief DMA IRDA receive process half complete callback
01703   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01704   *                the configuration information for the specified DMA module.
01705   * @retval None
01706   */
01707 static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
01708 {
01709   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01710   HAL_IRDA_RxHalfCpltCallback(hirda);
01711 }
01712
01713 /**
01714   * @brief  DMA IRDA communication error callback.
01715   * @param  hdma: DMA handle
01716   * @retval None
01717   */
01718 static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
01719 {
01720   uint32_t dmarequest = 0x00U;
01721   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01722
01723   /* Stop IRDA DMA Tx request if ongoing */
01724   dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
01725   if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
01726   {
01727     hirda->TxXferCount = 0U;
01728     IRDA_EndTxTransfer(hirda);
01729   }
01730
01731   /* Stop IRDA DMA Rx request if ongoing */
01732   dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
01733   if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
01734   {
01735     hirda->RxXferCount = 0U;
01736     IRDA_EndRxTransfer(hirda);
01737   }
01738
01739   hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
01740
01741   HAL_IRDA_ErrorCallback(hirda);
01742 }
01743
01744 /**
01745   * @brief  This function handles IRDA Communication Timeout.
01746   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
01747   *                the configuration information for the specified IRDA module.
01748   * @param  Flag: specifies the IRDA flag to check.
01749   * @param  Status: The new Flag status (SET or RESET).
01750   * @param  Tickstart: Tick start value
01751   * @param  Timeout: Timeout duration
01752   * @retval HAL status
01753   */
01754 static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01755 {
01756   /* Wait until flag is set */
01757   while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
01758   {
01759     /* Check for the Timeout */
01760     if(Timeout != HAL_MAX_DELAY)
01761     {
01762       if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
01763       {
01764         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01765         CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
01766         CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01767
01768         hirda->gState  = HAL_IRDA_STATE_READY;
01769         hirda->RxState = HAL_IRDA_STATE_READY;
01770
01771         /* Process Unlocked */
01772         __HAL_UNLOCK(hirda);
01773
01774         return HAL_TIMEOUT;
01775       }
01776     }
01777   }
01778   return HAL_OK;
01779 }
01780
01781 /**
01782   * @brief  End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
01783   * @param  hirda: IRDA handle.
01784   * @retval None
01785   */
01786 static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
01787 {
01788   /* Disable TXEIE and TCIE interrupts */
01789   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01790
01791   /* At end of Tx process, restore hirda->gState to Ready */
01792   hirda->gState = HAL_IRDA_STATE_READY;
01793 }
01794
01795 /**
01796   * @brief  End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
01797   * @param  hirda: IRDA handle.
01798   * @retval None
01799   */
01800 static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
01801 {
01802   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01803   CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01804   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
01805
01806   /* At end of Rx process, restore hirda->RxState to Ready */
01807   hirda->RxState = HAL_IRDA_STATE_READY;
01808 }
01809
01810 /**
01811   * @brief  DMA IRDA communication abort callback, when initiated by HAL services on Error
01812   *         (To be called at end of DMA Abort procedure following error occurrence).
01813   * @param  hdma DMA handle.
01814   * @retval None
01815   */
01816 static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
01817 {
01818   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01819   hirda->RxXferCount = 0x00U;
01820   hirda->TxXferCount = 0x00U;
01821
01822   HAL_IRDA_ErrorCallback(hirda);
01823 }
01824
01825 /**
01826   * @brief  DMA IRDA Tx communication abort callback, when initiated by user
01827   *         (To be called at end of DMA Tx Abort procedure following user abort request).
01828   * @note   When this callback is executed, User Abort complete call back is called only if no
01829   *         Abort still ongoing for Rx DMA Handle.
01830   * @param  hdma DMA handle.
01831   * @retval None
01832   */
01833 static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
01834 {
01835   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01836
01837   hirda->hdmatx->XferAbortCallback = NULL;
01838
01839   /* Check if an Abort process is still ongoing */
01840   if(hirda->hdmarx != NULL)
01841   {
01842     if(hirda->hdmarx->XferAbortCallback != NULL)
01843     {
01844       return;
01845     }
01846   }
01847
01848   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
01849   hirda->TxXferCount = 0x00U;
01850   hirda->RxXferCount = 0x00U;
01851
01852   /* Reset ErrorCode */
01853   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01854
01855   /* Restore hirda->gState and hirda->RxState to Ready */
01856   hirda->gState  = HAL_IRDA_STATE_READY;
01857   hirda->RxState = HAL_IRDA_STATE_READY;
01858
01859   /* Call user Abort complete callback */
01860   HAL_IRDA_AbortCpltCallback(hirda);
01861 }
01862
01863 /**
01864   * @brief  DMA IRDA Rx communication abort callback, when initiated by user
01865   *         (To be called at end of DMA Rx Abort procedure following user abort request).
01866   * @note   When this callback is executed, User Abort complete call back is called only if no
01867   *         Abort still ongoing for Tx DMA Handle.
01868   * @param  hdma DMA handle.
01869   * @retval None
01870   */
01871 static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
01872 {
01873   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01874
01875   hirda->hdmarx->XferAbortCallback = NULL;
01876
01877   /* Check if an Abort process is still ongoing */
01878   if(hirda->hdmatx != NULL)
01879   {
01880     if(hirda->hdmatx->XferAbortCallback != NULL)
01881     {
01882       return;
01883     }
01884   }
01885
01886   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
01887   hirda->TxXferCount = 0x00U;
01888   hirda->RxXferCount = 0x00U;
01889
01890   /* Reset ErrorCode */
01891   hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
01892
01893   /* Restore hirda->gState and hirda->RxState to Ready */
01894   hirda->gState  = HAL_IRDA_STATE_READY;
01895   hirda->RxState = HAL_IRDA_STATE_READY;
01896
01897   /* Call user Abort complete callback */
01898   HAL_IRDA_AbortCpltCallback(hirda);
01899 }
01900
01901 /**
01902   * @brief  DMA IRDA Tx communication abort callback, when initiated by user by a call to
01903   *         HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
01904   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
01905   *         and leads to user Tx Abort Complete callback execution).
01906   * @param  hdma DMA handle.
01907   * @retval None
01908   */
01909 static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
01910 {
01911   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01912
01913   hirda->TxXferCount = 0x00U;
01914
01915   /* Restore hirda->gState to Ready */
01916   hirda->gState = HAL_IRDA_STATE_READY;
01917
01918   /* Call user Abort complete callback */
01919   HAL_IRDA_AbortTransmitCpltCallback(hirda);
01920 }
01921
01922 /**
01923   * @brief  DMA IRDA Rx communication abort callback, when initiated by user by a call to
01924   *         HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
01925   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
01926   *         and leads to user Rx Abort Complete callback execution).
01927   * @param  hdma DMA handle.
01928   * @retval None
01929   */
01930 static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
01931 {
01932   IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01933
01934   hirda->RxXferCount = 0x00U;
01935
01936   /* Restore hirda->RxState to Ready */
01937   hirda->RxState = HAL_IRDA_STATE_READY;
01938
01939   /* Call user Abort complete callback */
01940   HAL_IRDA_AbortReceiveCpltCallback(hirda);
01941 }
01942
01943 /**
01944   * @brief  Send an amount of data in non blocking mode.
01945   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01946   *                the configuration information for the specified IRDA module.
01947   * @retval HAL status
01948   */
01949 static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
01950 {
01951   uint16_t* tmp;
01952
01953   /* Check that a Tx process is ongoing */
01954   if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
01955   {
01956     if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
01957     {
01958       tmp = (uint16_t*) hirda->pTxBuffPtr;
01959       hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
01960       if(hirda->Init.Parity == IRDA_PARITY_NONE)
01961       {
01962         hirda->pTxBuffPtr += 2U;
01963       }
01964       else
01965       {
01966         hirda->pTxBuffPtr += 1U;
01967       }
01968     }
01969     else
01970     {
01971       hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
01972     }
01973
01974     if(--hirda->TxXferCount == 0U)
01975     {
01976       /* Disable the IRDA Transmit Data Register Empty Interrupt */
01977       CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
01978
01979       /* Enable the IRDA Transmit Complete Interrupt */
01980       SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
01981     }
01982     return HAL_OK;
01983   }
01984   else
01985   {
01986     return HAL_BUSY;
01987   }
01988 }
01989
01990 /**
01991   * @brief  Wraps up transmission in non blocking mode.
01992   * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
01993   *                the configuration information for the specified IRDA module.
01994   * @retval HAL status
01995   */
01996 static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
01997 {
01998   /* Disable the IRDA Transmit Complete Interrupt */
01999   CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
02000
02001   /* Tx process is ended, restore hirda->gState to Ready */
02002   hirda->gState = HAL_IRDA_STATE_READY;
02003   HAL_IRDA_TxCpltCallback(hirda);
02004
02005   return HAL_OK;
02006 }
02007
02008 /**
02009   * @brief  Receives an amount of data in non blocking mode.
02010   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
02011   *                the configuration information for the specified IRDA module.
02012   * @retval HAL status
02013   */
02014 static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
02015 {
02016   uint16_t* tmp;
02017   uint16_t  uhdata;
02018
02019   /* Check that a Rx process is ongoing */
02020   if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
02021   {
02022     uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
02023     if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
02024     {
02025       tmp = (uint16_t*) hirda->pRxBuffPtr;
02026       if(hirda->Init.Parity == IRDA_PARITY_NONE)
02027       {
02028         *tmp = (uint16_t)(uhdata & (uint16_t)0x01FF);
02029         hirda->pRxBuffPtr += 2U;
02030       }
02031       else
02032       {
02033         *tmp = (uint16_t)(uhdata & (uint16_t)0x00FF);
02034         hirda->pRxBuffPtr += 1U;
02035       }
02036     }
02037     else
02038     {
02039       if(hirda->Init.Parity == IRDA_PARITY_NONE)
02040       {
02041         *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF);
02042       }
02043       else
02044       {
02045         *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007F);
02046       }
02047     }
02048
02049     if(--hirda->RxXferCount == 0U)
02050     {
02051       /* Disable the IRDA Data Register not empty Interrupt */
02052       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
02053
02054       /* Disable the IRDA Parity Error Interrupt */
02055       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
02056
02057       /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
02058       __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
02059
02060       /* Rx process is completed, restore hirda->RxState to Ready */
02061       hirda->RxState = HAL_IRDA_STATE_READY;
02062       HAL_IRDA_RxCpltCallback(hirda);
02063
02064       return HAL_OK;
02065     }
02066     return HAL_OK;
02067   }
02068   else
02069   {
02070     return HAL_BUSY;
02071   }
02072 }
02073
02074 /**
02075   * @brief  Configures the IRDA peripheral.
02076   * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
02077   *                the configuration information for the specified IRDA module.
02078   * @retval None
02079   */
02080 static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
02081 {
02082   /* Check the parameters */
02083   assert_param(IS_IRDA_INSTANCE(hirda->Instance));
02084   assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
02085   assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
02086   assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
02087   assert_param(IS_IRDA_MODE(hirda->Init.Mode));
02088   assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
02089
02090   /*-------------------------- USART CR2 Configuration ------------------------*/
02091   /* Clear STOP[13:12] bits */
02092   CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
02093
02094   /*-------------------------- USART CR1 Configuration -----------------------*/
02095   /* Clear M, PCE, PS, TE and RE bits */
02096   CLEAR_BIT(hirda->Instance->CR1, USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE);
02097
02098   /* Configure the USART Word Length, Parity and mode:
02099   Set the M bits according to hirda->Init.WordLength value
02100   Set PCE and PS bits according to hirda->Init.Parity value
02101   Set TE and RE bits according to hirda->Init.Mode value */
02102   /* Write to USART CR1 */
02103   SET_BIT(hirda->Instance->CR1, (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
02104
02105   /*-------------------------- USART CR3 Configuration -----------------------*/
02106   /* Clear CTSE and RTSE bits */
02107   CLEAR_BIT(hirda->Instance->CR3, USART_CR3_RTSE | USART_CR3_CTSE);
02108
02109   /*-------------------------- USART BRR Configuration -----------------------*/
02110   if(hirda->Instance == USART1)
02111   {
02112     SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
02113   }
02114   else
02115   {
02116     SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
02117   }
02118 }
02119
02120 /**
02121   * @}
02122   */
02123
02124 #endif /* HAL_IRDA_MODULE_ENABLED */
02125 /**
02126   * @}
02127   */
02128
02129 /**
02130   * @}
02131   */
02132
02133 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_irda.h Source File

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stm32f1xx_hal_irda.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_irda.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of IRDA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_IRDA_H
00040 #define __STM32F1xx_HAL_IRDA_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IRDA
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup IRDA_Exported_Types IRDA Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief IRDA Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
00068                                            The baud rate is computed using the following formula:
00069                                            - IntegerDivider = ((PCLKx) / (16 * (hirda->Init.BaudRate)))
00070                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
00071
00072   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00073                                            This parameter can be a value of @ref IRDA_Word_Length */
00074
00075
00076   uint32_t Parity;                    /*!< Specifies the parity mode.
00077                                            This parameter can be a value of @ref IRDA_Parity
00078                                            @note When parity is enabled, the computed parity is inserted
00079                                                  at the MSB position of the transmitted data (9th bit when
00080                                                  the word length is set to 9 data bits; 8th bit when the
00081                                                  word length is set to 8 data bits). */
00082
00083   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00084                                            This parameter can be a value of @ref IRDA_Transfer_Mode */
00085
00086   uint8_t  Prescaler;                 /*!< Specifies the Prescaler value prescaler value to be programmed
00087                                            in the IrDA low-power Baud Register, for defining pulse width on which
00088                                            burst acceptance/rejection will be decided. This value is used as divisor
00089                                            of system clock to achieve required pulse width. */
00090
00091   uint32_t IrDAMode;                  /*!< Specifies the IrDA mode
00092                                            This parameter can be a value of @ref IRDA_Low_Power */
00093 }IRDA_InitTypeDef;
00094
00095 /**
00096   * @brief HAL IRDA State structures definition
00097   * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState.
00098   *        - gState contains IRDA state information related to global Handle management
00099   *          and also information related to Tx operations.
00100   *          gState value coding follow below described bitmap :
00101   *          b7-b6  Error information
00102   *             00 : No Error
00103   *             01 : (Not Used)
00104   *             10 : Timeout
00105   *             11 : Error
00106   *          b5     IP initilisation status
00107   *             0  : Reset (IP not initialized)
00108   *             1  : Init done (IP not initialized. HAL IRDA Init function already called)
00109   *          b4-b3  (not used)
00110   *             xx : Should be set to 00
00111   *          b2     Intrinsic process state
00112   *             0  : Ready
00113   *             1  : Busy (IP busy with some configuration or internal operations)
00114   *          b1     (not used)
00115   *             x  : Should be set to 0
00116   *          b0     Tx state
00117   *             0  : Ready (no Tx operation ongoing)
00118   *             1  : Busy (Tx operation ongoing)
00119   *        - RxState contains information related to Rx operations.
00120   *          RxState value coding follow below described bitmap :
00121   *          b7-b6  (not used)
00122   *             xx : Should be set to 00
00123   *          b5     IP initilisation status
00124   *             0  : Reset (IP not initialized)
00125   *             1  : Init done (IP not initialized)
00126   *          b4-b2  (not used)
00127   *            xxx : Should be set to 000
00128   *          b1     Rx state
00129   *             0  : Ready (no Rx operation ongoing)
00130   *             1  : Busy (Rx operation ongoing)
00131   *          b0     (not used)
00132   *             x  : Should be set to 0.
00133   */
00134 typedef enum
00135 {
00136   HAL_IRDA_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
00137                                                    Value is allowed for gState and RxState */
00138   HAL_IRDA_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
00139                                                    Value is allowed for gState and RxState */
00140   HAL_IRDA_STATE_BUSY              = 0x24U,    /*!< An internal process is ongoing
00141                                                    Value is allowed for gState only */
00142   HAL_IRDA_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
00143                                                    Value is allowed for gState only */
00144   HAL_IRDA_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
00145                                                    Value is allowed for RxState only */
00146   HAL_IRDA_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
00147                                                    Not to be used for neither gState nor RxState.
00148                                                    Value is result of combination (Or) between gState and RxState values */
00149   HAL_IRDA_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
00150                                                    Value is allowed for gState only */
00151   HAL_IRDA_STATE_ERROR             = 0xE0U     /*!< Error
00152                                                    Value is allowed for gState only */
00153 }HAL_IRDA_StateTypeDef;
00154
00155 /**
00156   * @brief IRDA handle Structure definition
00157   */
00158 typedef struct
00159 {
00160   USART_TypeDef               *Instance;        /*!< USART registers base address       */
00161
00162   IRDA_InitTypeDef            Init;             /*!< IRDA communication parameters      */
00163
00164   uint8_t                     *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
00165
00166   uint16_t                    TxXferSize;       /*!< IRDA Tx Transfer size              */
00167
00168   __IO uint16_t               TxXferCount;      /*!< IRDA Tx Transfer Counter           */
00169
00170   uint8_t                     *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
00171
00172   uint16_t                    RxXferSize;       /*!< IRDA Rx Transfer size              */
00173
00174   __IO uint16_t               RxXferCount;      /*!< IRDA Rx Transfer Counter           */
00175
00176   DMA_HandleTypeDef           *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
00177
00178   DMA_HandleTypeDef           *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
00179
00180   HAL_LockTypeDef             Lock;             /*!< Locking object                     */
00181
00182   __IO HAL_IRDA_StateTypeDef  gState;           /*!< IRDA state information related to global Handle management
00183                                                    and also related to Tx operations.
00184                                                    This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00185
00186   __IO HAL_IRDA_StateTypeDef  RxState;          /*!< IRDA state information related to Rx operations.
00187                                                    This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
00188
00189   __IO uint32_t               ErrorCode;        /*!< IRDA Error code                    */
00190 }IRDA_HandleTypeDef;
00191
00192 /**
00193   * @}
00194   */
00195
00196 /* Exported constants --------------------------------------------------------*/
00197 /** @defgroup IRDA_Exported_Constants IRDA Exported constants
00198   * @{
00199   */
00200 /** @defgroup IRDA_Error_Code IRDA Error Code
00201   * @{
00202   */
00203 #define HAL_IRDA_ERROR_NONE         0x00000000U   /*!< No error            */
00204 #define HAL_IRDA_ERROR_PE           0x00000001U   /*!< Parity error        */
00205 #define HAL_IRDA_ERROR_NE           0x00000002U   /*!< Noise error         */
00206 #define HAL_IRDA_ERROR_FE           0x00000004U   /*!< Frame error         */
00207 #define HAL_IRDA_ERROR_ORE          0x00000008U   /*!< Overrun error       */
00208 #define HAL_IRDA_ERROR_DMA          0x00000010U   /*!< DMA transfer error  */
00209 /**
00210   * @}
00211   */
00212
00213 /** @defgroup IRDA_Word_Length IRDA Word Length
00214   * @{
00215   */
00216 #define IRDA_WORDLENGTH_8B                  0x00000000U
00217 #define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
00218 /**
00219   * @}
00220   */
00221
00222 /** @defgroup IRDA_Parity IRDA Parity
00223   * @{
00224   */
00225 #define IRDA_PARITY_NONE                    0x00000000U
00226 #define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00227 #define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00228 /**
00229   * @}
00230   */
00231
00232 /** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
00233   * @{
00234   */
00235 #define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)
00236 #define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)
00237 #define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00238 /**
00239   * @}
00240   */
00241
00242 /** @defgroup IRDA_Low_Power IRDA Low Power
00243   * @{
00244   */
00245 #define IRDA_POWERMODE_LOWPOWER                  ((uint32_t)USART_CR3_IRLP)
00246 #define IRDA_POWERMODE_NORMAL                    0x00000000U
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup IRDA_Flags IRDA Flags
00252   *        Elements values convention: 0xXXXX
00253   *           - 0xXXXX  : Flag mask in the SR register
00254   * @{
00255   */
00256 #define IRDA_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
00257 #define IRDA_FLAG_TC                        ((uint32_t)USART_SR_TC)
00258 #define IRDA_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
00259 #define IRDA_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
00260 #define IRDA_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
00261 #define IRDA_FLAG_NE                        ((uint32_t)USART_SR_NE)
00262 #define IRDA_FLAG_FE                        ((uint32_t)USART_SR_FE)
00263 #define IRDA_FLAG_PE                        ((uint32_t)USART_SR_PE)
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
00269   *        Elements values convention: 0xY000XXXX
00270   *           - XXXX  : Interrupt mask in the XX register
00271   *           - Y  : Interrupt source register (2bits)
00272   *                 - 01: CR1 register
00273   *                 - 10: CR2 register
00274   *                 - 11: CR3 register
00275   * @{
00276   */
00277 #define IRDA_IT_PE                          ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
00278 #define IRDA_IT_TXE                         ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
00279 #define IRDA_IT_TC                          ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
00280 #define IRDA_IT_RXNE                        ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
00281 #define IRDA_IT_IDLE                        ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
00282
00283 #define IRDA_IT_LBD                         ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
00284
00285 #define IRDA_IT_CTS                         ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
00286 #define IRDA_IT_ERR                         ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
00287 /**
00288   * @}
00289   */
00290
00291 /**
00292   * @}
00293   */
00294
00295 /* Exported macro ------------------------------------------------------------*/
00296 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
00297   * @{
00298   */
00299
00300 /** @brief Reset IRDA handle gstate & RxState
00301   * @param  __HANDLE__: specifies the IRDA Handle.
00302   *         IRDA Handle selects the USARTx or UARTy peripheral
00303   *         (USART,UART availability and x,y values depending on device).
00304   */
00305 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00306                                                        (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
00307                                                        (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
00308                                                      } while(0U)
00309
00310 /** @brief  Flush the IRDA DR register
00311   * @param  __HANDLE__: specifies the USART Handle.
00312   *         IRDA Handle selects the USARTx or UARTy peripheral
00313   *         (USART,UART availability and x,y values depending on device).
00314   */
00315 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
00316
00317 /** @brief  Check whether the specified IRDA flag is set or not.
00318   * @param  __HANDLE__: specifies the IRDA Handle.
00319   *         IRDA Handle selects the USARTx or UARTy peripheral
00320   *         (USART,UART availability and x,y values depending on device).
00321   * @param  __FLAG__: specifies the flag to check.
00322   *        This parameter can be one of the following values:
00323   *            @arg IRDA_FLAG_TXE:  Transmit data register empty flag
00324   *            @arg IRDA_FLAG_TC:   Transmission Complete flag
00325   *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag
00326   *            @arg IRDA_FLAG_IDLE: Idle Line detection flag
00327   *            @arg IRDA_FLAG_ORE:  OverRun Error flag
00328   *            @arg IRDA_FLAG_NE:   Noise Error flag
00329   *            @arg IRDA_FLAG_FE:   Framing Error flag
00330   *            @arg IRDA_FLAG_PE:   Parity Error flag
00331   * @retval The new state of __FLAG__ (TRUE or FALSE).
00332   */
00333 #define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00334
00335 /** @brief  Clear the specified IRDA pending flag.
00336   * @param  __HANDLE__: specifies the IRDA Handle.
00337   *         IRDA Handle selects the USARTx or UARTy peripheral
00338   *         (USART,UART availability and x,y values depending on device).
00339   * @param  __FLAG__: specifies the flag to check.
00340   *          This parameter can be any combination of the following values:
00341   *            @arg IRDA_FLAG_TC:   Transmission Complete flag.
00342   *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
00343   *
00344   * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
00345   *          error) and IDLE (Idle line detected) flags are cleared by software
00346   *          sequence: a read operation to USART_SR register followed by a read
00347   *          operation to USART_DR register.
00348   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
00349   * @note   TC flag can be also cleared by software sequence: a read operation to
00350   *          USART_SR register followed by a write operation to USART_DR register.
00351   * @note   TXE flag is cleared only by a write to the USART_DR register.
00352   *
00353   */
00354 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00355
00356 /** @brief  Clear the IRDA PE pending flag.
00357   * @param  __HANDLE__: specifies the IRDA Handle.
00358   *         IRDA Handle selects the USARTx or UARTy peripheral
00359   *         (USART,UART availability and x,y values depending on device).
00360   */
00361 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)     \
00362 do{                                             \
00363     __IO uint32_t tmpreg = 0x00U;               \
00364     tmpreg = (__HANDLE__)->Instance->SR;        \
00365     tmpreg = (__HANDLE__)->Instance->DR;        \
00366     UNUSED(tmpreg);                             \
00367   } while(0U)
00368
00369 /** @brief  Clear the IRDA FE pending flag.
00370   * @param  __HANDLE__: specifies the IRDA Handle.
00371   *         IRDA Handle selects the USARTx or UARTy peripheral
00372   *         (USART,UART availability and x,y values depending on device).
00373   */
00374 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
00375
00376 /** @brief  Clear the IRDA NE pending flag.
00377   * @param  __HANDLE__: specifies the IRDA Handle.
00378   *         IRDA Handle selects the USARTx or UARTy peripheral
00379   *         (USART,UART availability and x,y values depending on device).
00380   */
00381 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
00382
00383 /** @brief  Clear the IRDA ORE pending flag.
00384   * @param  __HANDLE__: specifies the IRDA Handle.
00385   *         IRDA Handle selects the USARTx or UARTy peripheral
00386   *         (USART,UART availability and x,y values depending on device).
00387   */
00388 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
00389
00390 /** @brief  Clear the IRDA IDLE pending flag.
00391   * @param  __HANDLE__: specifies the IRDA Handle.
00392   *         IRDA Handle selects the USARTx or UARTy peripheral
00393   *         (USART,UART availability and x,y values depending on device).
00394   */
00395 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
00396
00397 /** @brief  Enable the specified IRDA interrupt.
00398   * @param  __HANDLE__: specifies the IRDA Handle.
00399   *         IRDA Handle selects the USARTx or UARTy peripheral
00400   *         (USART,UART availability and x,y values depending on device).
00401   * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
00402   *          This parameter can be one of the following values:
00403   *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
00404   *            @arg IRDA_IT_TC:   Transmission complete interrupt
00405   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
00406   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
00407   *            @arg IRDA_IT_PE:   Parity Error interrupt
00408   *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00409   */
00410 #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
00411                                                            (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
00412                                                            ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
00413 /** @brief  Disable the specified IRDA interrupt.
00414   * @param  __HANDLE__: specifies the IRDA Handle.
00415   *         IRDA Handle selects the USARTx or UARTy peripheral
00416   *         (USART,UART availability and x,y values depending on device).
00417   * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
00418   *          This parameter can be one of the following values:
00419   *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
00420   *            @arg IRDA_IT_TC:   Transmission complete interrupt
00421   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
00422   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
00423   *            @arg IRDA_IT_PE:   Parity Error interrupt
00424   *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00425   */
00426 #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
00427                                                            (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
00428                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
00429
00430 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
00431   * @param  __HANDLE__: specifies the IRDA Handle.
00432   *         IRDA Handle selects the USARTx or UARTy peripheral
00433   *         (USART,UART availability and x,y values depending on device).
00434   * @param  __IT__: specifies the IRDA interrupt source to check.
00435   *          This parameter can be one of the following values:
00436   *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
00437   *            @arg IRDA_IT_TC:  Transmission complete interrupt
00438   *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
00439   *            @arg IRDA_IT_IDLE: Idle line detection interrupt
00440   *            @arg IRDA_IT_ERR: Error interrupt
00441   *            @arg IRDA_IT_PE: Parity Error interrupt
00442   * @retval The new state of __IT__ (TRUE or FALSE).
00443   */
00444 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
00445                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
00446
00447 /** @brief  Enable UART/USART associated to IRDA Handle
00448   * @param  __HANDLE__: specifies the IRDA Handle.
00449   *         IRDA Handle selects the USARTx or UARTy peripheral
00450   *         (USART,UART availability and x,y values depending on device).
00451   */
00452 #define __HAL_IRDA_ENABLE(__HANDLE__)                   (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
00453
00454 /** @brief  Disable UART/USART associated to IRDA Handle
00455   * @param  __HANDLE__: specifies the IRDA Handle.
00456   *         IRDA Handle selects the USARTx or UARTy peripheral
00457   *         (USART,UART availability and x,y values depending on device).
00458   */
00459 #define __HAL_IRDA_DISABLE(__HANDLE__)                  (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
00460
00461 /**
00462   * @}
00463   */
00464
00465 /* Exported functions --------------------------------------------------------*/
00466 /** @addtogroup IRDA_Exported_Functions
00467   * @{
00468   */
00469
00470 /** @addtogroup IRDA_Exported_Functions_Group1
00471   * @{
00472   */
00473 /* Initialization/de-initialization functions  **********************************/
00474 HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
00475 HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
00476 void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
00477 void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
00478 /**
00479   * @}
00480   */
00481
00482 /** @addtogroup IRDA_Exported_Functions_Group2
00483   * @{
00484   */
00485 /* IO operation functions *******************************************************/
00486 HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00487 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00488 HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00489 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00490 HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00491 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
00492 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
00493 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
00494 HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
00495 /* Transfer Abort functions */
00496 HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
00497 HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
00498 HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
00499 HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
00500 HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
00501 HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
00502
00503 void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
00504 void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
00505 void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
00506 void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00507 void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
00508 void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
00509 void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
00510 void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
00511 void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
00512 /**
00513   * @}
00514   */
00515
00516 /** @addtogroup IRDA_Exported_Functions_Group3
00517   * @{
00518   */
00519 /* Peripheral State functions  **************************************************/
00520 HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
00521 uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
00522 /**
00523   * @}
00524   */
00525
00526 /**
00527   * @}
00528   */
00529
00530 /* Private types -------------------------------------------------------------*/
00531 /* Private variables ---------------------------------------------------------*/
00532 /* Private constants ---------------------------------------------------------*/
00533 /** @defgroup IRDA_Private_Constants IRDA Private Constants
00534   * @{
00535   */
00536
00537 /** @brief IRDA interruptions flag mask
00538   *
00539   */
00540 #define IRDA_IT_MASK                        0x0000FFFFU
00541
00542 #define IRDA_CR1_REG_INDEX                  1U
00543 #define IRDA_CR2_REG_INDEX                  2U
00544 #define IRDA_CR3_REG_INDEX                  3U
00545 /**
00546   * @}
00547   */
00548
00549 /* Private macros --------------------------------------------------------*/
00550 /** @defgroup IRDA_Private_Macros   IRDA Private Macros
00551   * @{
00552   */
00553 #define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
00554                                      ((LENGTH) == IRDA_WORDLENGTH_9B))
00555 #define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
00556                                 ((PARITY) == IRDA_PARITY_EVEN) || \
00557                                 ((PARITY) == IRDA_PARITY_ODD))
00558 #define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
00559 #define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
00560                                  ((MODE) == IRDA_POWERMODE_NORMAL))
00561 #define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
00562
00563 #define IRDA_DIV(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
00564 #define IRDA_DIVMANT(_PCLK_, _BAUD_)        (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
00565 #define IRDA_DIVFRAQ(_PCLK_, _BAUD_)        (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
00566 /* UART BRR = mantissa + overflow + fraction
00567             = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
00568 #define IRDA_BRR(_PCLK_, _BAUD_)            (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
00569                                              (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
00570                                              (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
00571
00572 /**
00573   * @}
00574   */
00575
00576 /* Private functions ---------------------------------------------------------*/
00577 /** @defgroup IRDA_Private_Functions IRDA Private Functions
00578   * @{
00579   */
00580
00581 /**
00582   * @}
00583   */
00584
00585 /**
00586   * @}
00587   */
00588
00589 /**
00590   * @}
00591   */
00592
00593 #ifdef __cplusplus
00594 }
00595 #endif
00596
00597 #endif /* __STM32F1xx_HAL_IRDA_H */
00598
00599 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_iwdg.c Source File

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stm32f1xx_hal_iwdg.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_iwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.5.0
00006   * @date    06-May-2016
00007   * @brief   IWDG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Independent Watchdog (IWDG) peripheral:
00010   *           + Initialization and Start functions
00011   *           + IO operation functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                     ##### IWDG Generic features #####
00016   ==============================================================================
00017   [..]
00018     (+) The IWDG can be started by either software or hardware (configurable
00019         through option byte).
00020
00021     (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
00022         if the main clock fails.
00023
00024     (+) Once the IWDG is started, the LSI is forced ON and both can not be
00025         disabled. The counter starts counting down from the reset value (0xFFF).
00026         When it reaches the end of count value (0x000) a reset signal is
00027         generated (IWDG reset).
00028
00029     (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
00030         the IWDG_RLR value is reloaded in the counter and the watchdog reset is
00031         prevented.
00032
00033     (+) The IWDG is implemented in the VDD voltage domain that is still functional
00034         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
00035         IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
00036         reset occurs.
00037
00038     (+) Debug mode : When the microcontroller enters debug mode (core halted),
00039         the IWDG counter either continues to work normally or stops, depending
00040         on DBG_IWDG_STOP configuration bit in DBG module, accessible through
00041         __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
00042
00043     [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
00044          The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
00045          devices provide the capability to measure the LSI frequency (LSI clock
00046          connected internally to TIM5 CH4 input capture). The measured value
00047          can be used to have an IWDG timeout with an acceptable accuracy.
00048
00049                      ##### How to use this driver #####
00050   ==============================================================================
00051   [..]
00052     (#) Use IWDG using HAL_IWDG_Init() function to :
00053       (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
00054            clock is forced ON and IWDG counter starts downcounting.
00055       (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
00056       (++) Configure the IWDG prescaler and counter reload value. This reload
00057            value will be loaded in the IWDG counter each time the watchdog is
00058            reloaded, then the IWDG will start counting down from this value.
00059       (++) wait for status flags to be reset"
00060
00061     (#) Then the application program must refresh the IWDG counter at regular
00062         intervals during normal operation to prevent an MCU reset, using
00063         HAL_IWDG_Refresh() function.
00064
00065      *** IWDG HAL driver macros list ***
00066      ====================================
00067      [..]
00068        Below the list of most used macros in IWDG HAL driver:
00069       (+) __HAL_IWDG_START: Enable the IWDG peripheral
00070       (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
00071           the reload register
00072
00073   @endverbatim
00074   ******************************************************************************
00075   * @attention
00076   *
00077   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00078   *
00079   * Redistribution and use in source and binary forms, with or without modification,
00080   * are permitted provided that the following conditions are met:
00081   *   1. Redistributions of source code must retain the above copyright notice,
00082   *      this list of conditions and the following disclaimer.
00083   *   2. Redistributions in binary form must reproduce the above copyright notice,
00084   *      this list of conditions and the following disclaimer in the documentation
00085   *      and/or other materials provided with the distribution
00086   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00087   *      may be used to endorse or promote products derived from this software
00088   *      without specific prior written permission.
00089   *
00090   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00091   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00092   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00093   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00094   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00095   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00096   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00097   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00098   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00099   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00100   *
00101   ******************************************************************************
00102   */
00103
00104 /* Includes ------------------------------------------------------------------*/
00105 #include "stm32f1xx_hal.h"
00106
00107 /** @addtogroup STM32F1xx_HAL_Driver
00108   * @{
00109   */
00110
00111 #ifdef HAL_IWDG_MODULE_ENABLED
00112 /** @defgroup IWDG IWDG
00113   * @brief IWDG HAL module driver.
00114   * @{
00115   */
00116
00117 /* Private typedef -----------------------------------------------------------*/
00118 /* Private define ------------------------------------------------------------*/
00119 /** @defgroup IWDG_Private_Defines IWDG Private Defines
00120   * @{
00121   */
00122 /* Status register need 5 RC LSI divided by prescaler clock to be updated. With
00123    higher prescaler (256), and according to HSI variation, we need to wait at
00124    least 6 cycles so 48 ms. */
00125 #define HAL_IWDG_DEFAULT_TIMEOUT            48U
00126 /**
00127   * @}
00128   */
00129
00130 /* Private macro -------------------------------------------------------------*/
00131 /* Private variables ---------------------------------------------------------*/
00132 /* Private function prototypes -----------------------------------------------*/
00133 /* Exported functions --------------------------------------------------------*/
00134
00135 /** @addtogroup IWDG_Exported_Functions
00136   * @{
00137   */
00138
00139 /** @addtogroup IWDG_Exported_Functions_Group1
00140   *  @brief    Initialization and Start functions.
00141   *
00142 @verbatim
00143  ===============================================================================
00144           ##### Initialization and Start functions #####
00145  ===============================================================================
00146  [..]  This section provides functions allowing to:
00147       (+) Initialize the IWDG according to the specified parameters in the
00148           IWDG_InitTypeDef of associated handle.
00149       (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
00150           is reloaded in order to exit function with correct time base.
00151
00152 @endverbatim
00153   * @{
00154   */
00155
00156 /**
00157   * @brief  Initialize the IWDG according to the specified parameters in the
00158   *         IWDG_InitTypeDef and start watchdog. Before exiting function,
00159   *         watchdog is refreshed in order to have correct time base.
00160   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00161   *                the configuration information for the specified IWDG module.
00162   * @retval HAL status
00163   */
00164 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
00165 {
00166   uint32_t tickstart;
00167
00168   /* Check the IWDG handle allocation */
00169   if(hiwdg == NULL)
00170   {
00171     return HAL_ERROR;
00172   }
00173
00174   /* Check the parameters */
00175   assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
00176   assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
00177   assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
00178
00179   /* Enable IWDG. LSI is turned on automaticaly */
00180   __HAL_IWDG_START(hiwdg);
00181
00182   /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
00183   IWDG_ENABLE_WRITE_ACCESS(hiwdg);
00184
00185   /* Write to IWDG registers the Prescaler & Reload values to work with */
00186   hiwdg->Instance->PR = hiwdg->Init.Prescaler;
00187   hiwdg->Instance->RLR = hiwdg->Init.Reload;
00188
00189   /* Check pending flag, if previous update not done, return timeout */
00190   tickstart = HAL_GetTick();
00191
00192   /* Wait for register to be updated */
00193   while(hiwdg->Instance->SR != RESET)
00194   {
00195     if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
00196     {
00197       return HAL_TIMEOUT;
00198     }
00199   }
00200
00201   /* Reload IWDG counter with value defined in the reload register */
00202   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00203
00204   /* Return function status */
00205   return HAL_OK;
00206 }
00207
00208 /**
00209   * @}
00210   */
00211
00212 /** @addtogroup IWDG_Exported_Functions_Group2
00213   *  @brief   IO operation functions
00214   *
00215 @verbatim
00216  ===============================================================================
00217                       ##### IO operation functions #####
00218  ===============================================================================
00219  [..]  This section provides functions allowing to:
00220       (+) Refresh the IWDG.
00221
00222 @endverbatim
00223   * @{
00224   */
00225
00226 /**
00227   * @brief  Refresh the IWDG.
00228   * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
00229   *                the configuration information for the specified IWDG module.
00230   * @retval HAL status
00231   */
00232 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
00233 {
00234   /* Reload IWDG counter with value defined in the reload register */
00235   __HAL_IWDG_RELOAD_COUNTER(hiwdg);
00236
00237   /* Return function status */
00238   return HAL_OK;
00239 }
00240
00241 /**
00242   * @}
00243   */
00244
00245 /**
00246   * @}
00247   */
00248
00249 #endif /* HAL_IWDG_MODULE_ENABLED */
00250 /**
00251   * @}
00252   */
00253
00254 /**
00255   * @}
00256   */
00257
00258 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_iwdg.h Source File

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stm32f1xx_hal_iwdg.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_iwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.5.0
00006   * @date    06-May-2016
00007   * @brief   Header file of IWDG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_IWDG_H
00040 #define __STM32F1xx_HAL_IWDG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup IWDG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup IWDG_Exported_Types IWDG Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  IWDG Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
00068                             This parameter can be a value of @ref IWDG_Prescaler */
00069
00070   uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
00071                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
00072
00073 } IWDG_InitTypeDef;
00074
00075 /**
00076   * @brief  IWDG Handle Structure definition
00077   */
00078 typedef struct
00079 {
00080   IWDG_TypeDef                 *Instance;  /*!< Register base address    */
00081
00082   IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
00083
00084 }IWDG_HandleTypeDef;
00085
00086 /**
00087   * @}
00088   */
00089
00090 /* Exported constants --------------------------------------------------------*/
00091 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
00092   * @{
00093   */
00094
00095 /** @defgroup IWDG_Prescaler IWDG Prescaler
00096   * @{
00097   */
00098 #define IWDG_PRESCALER_4                0x00000000U                   /*!< IWDG prescaler set to 4   */
00099 #define IWDG_PRESCALER_8                IWDG_PR_PR_0                  /*!< IWDG prescaler set to 8   */
00100 #define IWDG_PRESCALER_16               IWDG_PR_PR_1                  /*!< IWDG prescaler set to 16  */
00101 #define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32  */
00102 #define IWDG_PRESCALER_64               IWDG_PR_PR_2                  /*!< IWDG prescaler set to 64  */
00103 #define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
00104 #define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
00105 /**
00106   * @}
00107   */
00108
00109 /**
00110   * @}
00111   */
00112
00113
00114 /* Exported macros -----------------------------------------------------------*/
00115 /** @defgroup IWDG_Exported_Macros IWDG Exported Macros
00116   * @{
00117   */
00118
00119 /**
00120   * @brief  Enable the IWDG peripheral.
00121   * @param  __HANDLE__  IWDG handle
00122   * @retval None
00123   */
00124 #define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
00125
00126 /**
00127   * @brief  Reload IWDG counter with value defined in the reload register
00128   *         (write access to IWDG_PR & IWDG_RLR registers disabled).
00129   * @param  __HANDLE__  IWDG handle
00130   * @retval None
00131   */
00132 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
00133
00134 /**
00135   * @}
00136   */
00137
00138 /* Exported functions --------------------------------------------------------*/
00139 /** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
00140   * @{
00141   */
00142
00143 /** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
00144   * @{
00145   */
00146 /* Initialization/Start functions  ********************************************/
00147 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
00153   * @{
00154   */
00155 /* I/O operation functions ****************************************************/
00156 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
00157 /**
00158   * @}
00159   */
00160
00161 /**
00162   * @}
00163   */
00164
00165 /* Private constants ---------------------------------------------------------*/
00166 /** @defgroup IWDG_Private_Constants IWDG Private Constants
00167   * @{
00168   */
00169
00170 /**
00171   * @brief  IWDG Key Register BitMask
00172   */
00173 #define IWDG_KEY_RELOAD                 0x0000AAAAU  /*!< IWDG Reload Counter Enable   */
00174 #define IWDG_KEY_ENABLE                 0x0000CCCCU  /*!< IWDG Peripheral Enable       */
00175 #define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555U  /*!< IWDG KR Write Access Enable  */
00176 #define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000U  /*!< IWDG KR Write Access Disable */
00177
00178 /**
00179   * @}
00180   */
00181
00182 /* Private macros ------------------------------------------------------------*/
00183 /** @defgroup IWDG_Private_Macros IWDG Private Macros
00184   * @{
00185   */
00186
00187 /**
00188   * @brief  Enable write access to IWDG_PR and IWDG_RLR registers.
00189   * @param  __HANDLE__  IWDG handle
00190   * @retval None
00191   */
00192 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
00193
00194 /**
00195   * @brief  Disable write access to IWDG_PR and IWDG_RLR registers.
00196   * @param  __HANDLE__  IWDG handle
00197   * @retval None
00198   */
00199 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
00200
00201 /**
00202   * @brief  Check IWDG prescaler value.
00203   * @param  __PRESCALER__  IWDG prescaler value
00204   * @retval None
00205   */
00206 #define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
00207                                                ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
00208                                                ((__PRESCALER__) == IWDG_PRESCALER_16) || \
00209                                                ((__PRESCALER__) == IWDG_PRESCALER_32) || \
00210                                                ((__PRESCALER__) == IWDG_PRESCALER_64) || \
00211                                                ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
00212                                                ((__PRESCALER__) == IWDG_PRESCALER_256))
00213
00214 /**
00215   * @brief  Check IWDG reload value.
00216   * @param  __RELOAD__  IWDG reload value
00217   * @retval None
00218   */
00219 #define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
00220
00221 /**
00222   * @}
00223   */
00224
00225 /**
00226   * @}
00227   */
00228
00229 /**
00230   * @}
00231   */
00232
00233
00234 #ifdef __cplusplus
00235 }
00236 #endif
00237
00238 #endif /* __STM32F1xx_HAL_IWDG_H */
00239
00240 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_nand.c Source File

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stm32f1xx_hal_nand.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_nand.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   NAND HAL module driver.
00008   *          This file provides a generic firmware to drive NAND memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                          ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016       This driver is a generic layered driver which contains a set of APIs used to
00017       control NAND flash memories. It uses the FSMC layer functions to interface
00018       with NAND devices. This driver is used as follows:
00019
00020       (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
00021           with control and timing parameters for both common and attribute spaces.
00022
00023       (+) Read NAND flash memory maker and device IDs using the function
00024           HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
00025           structure declared by the function caller.
00026
00027       (+) Access NAND flash memory by read/write operations using the functions
00028           HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
00029           HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
00030           HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
00031           HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
00032           to read/write page(s)/spare area(s). These functions use specific device
00033           information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
00034           structure. The read/write address information is contained by the Nand_Address_Typedef
00035           structure passed as parameter.
00036
00037       (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
00038
00039       (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
00040           The erase block address information is contained in the Nand_Address_Typedef
00041           structure passed as parameter.
00042
00043       (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
00044
00045       (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
00046           HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
00047           feature or the function HAL_NAND_GetECC() to get the ECC correction code.
00048
00049       (+) You can monitor the NAND device HAL state by calling the function
00050           HAL_NAND_GetState()
00051
00052     [..]
00053       (@) This driver is a set of generic APIs which handle standard NAND flash operations.
00054           If a NAND flash device contains different operations and/or implementations,
00055           it should be implemented separately.
00056
00057   @endverbatim
00058   ******************************************************************************
00059   * @attention
00060   *
00061   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00062   *
00063   * Redistribution and use in source and binary forms, with or without modification,
00064   * are permitted provided that the following conditions are met:
00065   *   1. Redistributions of source code must retain the above copyright notice,
00066   *      this list of conditions and the following disclaimer.
00067   *   2. Redistributions in binary form must reproduce the above copyright notice,
00068   *      this list of conditions and the following disclaimer in the documentation
00069   *      and/or other materials provided with the distribution.
00070   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00071   *      may be used to endorse or promote products derived from this software
00072   *      without specific prior written permission.
00073   *
00074   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00075   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00076   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00077   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00078   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00079   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00080   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00081   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00082   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00083   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00084   *
00085   ******************************************************************************
00086   */
00087
00088 /* Includes ------------------------------------------------------------------*/
00089 #include "stm32f1xx_hal.h"
00090
00091 /** @addtogroup STM32F1xx_HAL_Driver
00092   * @{
00093   */
00094
00095 #ifdef HAL_NAND_MODULE_ENABLED
00096
00097 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
00098
00099 /** @defgroup NAND NAND
00100   * @brief NAND HAL module driver
00101   * @{
00102   */
00103
00104 /* Private typedef -----------------------------------------------------------*/
00105 /* Private define ------------------------------------------------------------*/
00106 /** @defgroup NAND_Private_Constants NAND Private Constants
00107   * @{
00108   */
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Private macro -------------------------------------------------------------*/
00115 /** @defgroup NAND_Private_Macros NAND Private Macros
00116   * @{
00117   */
00118
00119 /**
00120   * @}
00121   */
00122
00123 /* Private variables ---------------------------------------------------------*/
00124 /* Private function prototypes -----------------------------------------------*/
00125 /* Exported functions --------------------------------------------------------*/
00126 /** @defgroup NAND_Exported_Functions NAND Exported Functions
00127   * @{
00128   */
00129
00130 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00131   * @brief    Initialization and Configuration functions
00132   *
00133   @verbatim
00134   ==============================================================================
00135             ##### NAND Initialization and de-initialization functions #####
00136   ==============================================================================
00137   [..]
00138     This section provides functions allowing to initialize/de-initialize
00139     the NAND memory
00140
00141 @endverbatim
00142   * @{
00143   */
00144
00145 /**
00146   * @brief  Perform NAND memory Initialization sequence
00147   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00148   *                the configuration information for NAND module.
00149   * @param  ComSpace_Timing: pointer to Common space timing structure
00150   * @param  AttSpace_Timing: pointer to Attribute space timing structure
00151   * @retval HAL status
00152   */
00153 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
00154 {
00155   /* Check the NAND handle state */
00156   if(hnand == NULL)
00157   {
00158      return HAL_ERROR;
00159   }
00160
00161   if(hnand->State == HAL_NAND_STATE_RESET)
00162   {
00163     /* Allocate lock resource and initialize it */
00164     hnand->Lock = HAL_UNLOCKED;
00165     /* Initialize the low level hardware (MSP) */
00166     HAL_NAND_MspInit(hnand);
00167   }
00168
00169   /* Initialize NAND control Interface */
00170   FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
00171
00172   /* Initialize NAND common space timing Interface */
00173   FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
00174
00175   /* Initialize NAND attribute space timing Interface */
00176   FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
00177
00178   /* Enable the NAND device */
00179   __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
00180
00181   /* Update the NAND controller state */
00182   hnand->State = HAL_NAND_STATE_READY;
00183
00184   return HAL_OK;
00185 }
00186
00187 /**
00188   * @brief  Perform NAND memory De-Initialization sequence
00189   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00190   *                the configuration information for NAND module.
00191   * @retval HAL status
00192   */
00193 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
00194 {
00195   /* Initialize the low level hardware (MSP) */
00196   HAL_NAND_MspDeInit(hnand);
00197
00198   /* Configure the NAND registers with their reset values */
00199   FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
00200
00201   /* Reset the NAND controller state */
00202   hnand->State = HAL_NAND_STATE_RESET;
00203
00204   /* Release Lock */
00205   __HAL_UNLOCK(hnand);
00206
00207   return HAL_OK;
00208 }
00209
00210 /**
00211   * @brief  NAND MSP Init
00212   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00213   *                the configuration information for NAND module.
00214   * @retval None
00215   */
00216 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
00217 {
00218   /* Prevent unused argument(s) compilation warning */
00219   UNUSED(hnand);
00220   /* NOTE : This function Should not be modified, when the callback is needed,
00221             the HAL_NAND_MspInit could be implemented in the user file
00222    */
00223 }
00224
00225 /**
00226   * @brief  NAND MSP DeInit
00227   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00228   *                the configuration information for NAND module.
00229   * @retval None
00230   */
00231 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
00232 {
00233   /* Prevent unused argument(s) compilation warning */
00234   UNUSED(hnand);
00235   /* NOTE : This function Should not be modified, when the callback is needed,
00236             the HAL_NAND_MspDeInit could be implemented in the user file
00237    */
00238 }
00239
00240
00241 /**
00242   * @brief  This function handles NAND device interrupt request.
00243   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00244   *                the configuration information for NAND module.
00245   * @retval HAL status
00246 */
00247 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
00248 {
00249   /* Check NAND interrupt Rising edge flag */
00250   if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
00251   {
00252     /* NAND interrupt callback*/
00253     HAL_NAND_ITCallback(hnand);
00254
00255     /* Clear NAND interrupt Rising edge pending bit */
00256     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
00257   }
00258
00259   /* Check NAND interrupt Level flag */
00260   if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
00261   {
00262     /* NAND interrupt callback*/
00263     HAL_NAND_ITCallback(hnand);
00264
00265     /* Clear NAND interrupt Level pending bit */
00266     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
00267   }
00268
00269   /* Check NAND interrupt Falling edge flag */
00270   if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
00271   {
00272     /* NAND interrupt callback*/
00273     HAL_NAND_ITCallback(hnand);
00274
00275     /* Clear NAND interrupt Falling edge pending bit */
00276     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
00277   }
00278
00279   /* Check NAND interrupt FIFO empty flag */
00280   if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
00281   {
00282     /* NAND interrupt callback*/
00283     HAL_NAND_ITCallback(hnand);
00284
00285     /* Clear NAND interrupt FIFO empty pending bit */
00286     __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
00287   }
00288 }
00289
00290 /**
00291   * @brief  NAND interrupt feature callback
00292   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00293   *                the configuration information for NAND module.
00294   * @retval None
00295   */
00296 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
00297 {
00298   /* Prevent unused argument(s) compilation warning */
00299   UNUSED(hnand);
00300   /* NOTE : This function Should not be modified, when the callback is needed,
00301             the HAL_NAND_ITCallback could be implemented in the user file
00302    */
00303 }
00304
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
00310   * @brief    Input Output and memory control functions
00311   *
00312   @verbatim
00313   ==============================================================================
00314                     ##### NAND Input and Output functions #####
00315   ==============================================================================
00316   [..]
00317     This section provides functions allowing to use and control the NAND
00318     memory
00319
00320 @endverbatim
00321   * @{
00322   */
00323
00324 /**
00325   * @brief  Read the NAND memory electronic signature
00326   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00327   *                the configuration information for NAND module.
00328   * @param  pNAND_ID: NAND ID structure
00329   * @retval HAL status
00330   */
00331 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
00332 {
00333   __IO uint32_t data = 0U;
00334   __IO uint32_t data1 = 0U;
00335   uint32_t deviceaddress = 0U;
00336
00337   /* Process Locked */
00338   __HAL_LOCK(hnand);
00339
00340   /* Check the NAND controller state */
00341   if(hnand->State == HAL_NAND_STATE_BUSY)
00342   {
00343      return HAL_BUSY;
00344   }
00345
00346   /* Identify the device address */
00347   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
00348   {
00349     deviceaddress = NAND_DEVICE1;
00350   }
00351   else
00352   {
00353     deviceaddress = NAND_DEVICE2;
00354   }
00355
00356   /* Update the NAND controller state */
00357   hnand->State = HAL_NAND_STATE_BUSY;
00358
00359   /* Send Read ID command sequence */
00360   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_READID;
00361   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00362
00363   /* Read the electronic signature from NAND flash */
00364   if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
00365   {
00366     data = *(__IO uint32_t *)deviceaddress;
00367
00368     /* Return the data read */
00369     pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00370     pNAND_ID->Device_Id  = ADDR_2ND_CYCLE(data);
00371     pNAND_ID->Third_Id   = ADDR_3RD_CYCLE(data);
00372     pNAND_ID->Fourth_Id  = ADDR_4TH_CYCLE(data);
00373   }
00374   else
00375   {
00376     data = *(__IO uint32_t *)deviceaddress;
00377     data1 = *((__IO uint32_t *)deviceaddress + 4U);
00378
00379     /* Return the data read */
00380     pNAND_ID->Maker_Id   = ADDR_1ST_CYCLE(data);
00381     pNAND_ID->Device_Id  = ADDR_3RD_CYCLE(data);
00382     pNAND_ID->Third_Id   = ADDR_1ST_CYCLE(data1);
00383     pNAND_ID->Fourth_Id  = ADDR_3RD_CYCLE(data1);
00384   }
00385
00386   /* Update the NAND controller state */
00387   hnand->State = HAL_NAND_STATE_READY;
00388
00389   /* Process unlocked */
00390   __HAL_UNLOCK(hnand);
00391
00392   return HAL_OK;
00393 }
00394
00395 /**
00396   * @brief  NAND memory reset
00397   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00398   *                the configuration information for NAND module.
00399   * @retval HAL status
00400   */
00401 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
00402 {
00403   uint32_t deviceaddress = 0U;
00404
00405   /* Process Locked */
00406   __HAL_LOCK(hnand);
00407
00408   /* Check the NAND controller state */
00409   if(hnand->State == HAL_NAND_STATE_BUSY)
00410   {
00411      return HAL_BUSY;
00412   }
00413
00414   /* Identify the device address */
00415   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
00416   {
00417     deviceaddress = NAND_DEVICE1;
00418   }
00419   else
00420   {
00421     deviceaddress = NAND_DEVICE2;
00422   }
00423
00424   /* Update the NAND controller state */
00425   hnand->State = HAL_NAND_STATE_BUSY;
00426
00427   /* Send NAND reset command */
00428   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
00429
00430
00431   /* Update the NAND controller state */
00432   hnand->State = HAL_NAND_STATE_READY;
00433
00434   /* Process unlocked */
00435   __HAL_UNLOCK(hnand);
00436
00437   return HAL_OK;
00438
00439 }
00440
00441 /**
00442   * @brief  Configure the device: Enter the physical parameters of the device
00443   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00444   *                the configuration information for NAND module.
00445   * @param  pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
00446   * @retval HAL status
00447   */
00448 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
00449 {
00450   hnand->Config.PageSize           = pDeviceConfig->PageSize;
00451   hnand->Config.SpareAreaSize      = pDeviceConfig->SpareAreaSize;
00452   hnand->Config.BlockSize          = pDeviceConfig->BlockSize;
00453   hnand->Config.BlockNbr           = pDeviceConfig->BlockNbr;
00454   hnand->Config.PlaneSize          = pDeviceConfig->PlaneSize;
00455   hnand->Config.PlaneNbr           = pDeviceConfig->PlaneNbr;
00456   hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
00457
00458   return HAL_OK;
00459 }
00460
00461 /**
00462   * @brief  Read Page(s) from NAND memory block (8-bits addressing)
00463   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00464   *                the configuration information for NAND module.
00465   * @param  pAddress : pointer to NAND address structure
00466   * @param  pBuffer : pointer to destination read buffer
00467   * @param  NumPageToRead : number of pages to read from block
00468   * @retval HAL status
00469   */
00470 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
00471 {
00472   __IO uint32_t index  = 0U;
00473   uint32_t tickstart = 0U;
00474   uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
00475
00476   /* Process Locked */
00477   __HAL_LOCK(hnand);
00478
00479   /* Check the NAND controller state */
00480   if(hnand->State == HAL_NAND_STATE_BUSY)
00481   {
00482      return HAL_BUSY;
00483   }
00484
00485   /* Identify the device address */
00486   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
00487   {
00488     deviceaddress = NAND_DEVICE1;
00489   }
00490   else
00491   {
00492     deviceaddress = NAND_DEVICE2;
00493   }
00494
00495   /* Update the NAND controller state */
00496   hnand->State = HAL_NAND_STATE_BUSY;
00497
00498   /* NAND raw address calculation */
00499   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00500
00501   /* Page(s) read loop */
00502   while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00503   {
00504     /* update the buffer size */
00505     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
00506
00507     /* Send read page command sequence */
00508     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00509
00510     /* Cards with page size <= 512 bytes */
00511     if((hnand->Config.PageSize) <= 512U)
00512     {
00513       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00514       {
00515         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00516         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00517         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00518       }
00519       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00520       {
00521         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00522         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00523         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00524         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00525       }
00526     }
00527     else /* (hnand->Config.PageSize) > 512 */
00528     {
00529       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00530       {
00531         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00532         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00533         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00534         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00535       }
00536       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00537       {
00538         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00539         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00540         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00541         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00542         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00543       }
00544     }
00545
00546     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00547
00548     /* Check if an extra command is needed for reading pages  */
00549     if(hnand->Config.ExtraCommandEnable == ENABLE)
00550     {
00551       /* Get tick */
00552       tickstart = HAL_GetTick();
00553
00554       /* Read status until NAND is ready */
00555       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00556       {
00557         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00558         {
00559           return HAL_TIMEOUT;
00560         }
00561       }
00562
00563       /* Go back to read mode */
00564       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
00565     }
00566
00567     /* Get Data into Buffer */
00568     for(; index < size; index++)
00569     {
00570       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
00571     }
00572
00573     /* Increment read pages number */
00574     numPagesRead++;
00575
00576     /* Decrement pages to read */
00577     NumPageToRead--;
00578
00579     /* Increment the NAND address */
00580     nandaddress = (uint32_t)(nandaddress + 1U);
00581   }
00582
00583   /* Update the NAND controller state */
00584   hnand->State = HAL_NAND_STATE_READY;
00585
00586   /* Process unlocked */
00587   __HAL_UNLOCK(hnand);
00588
00589   return HAL_OK;
00590 }
00591
00592 /**
00593   * @brief  Read Page(s) from NAND memory block (16-bits addressing)
00594   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00595   *                the configuration information for NAND module.
00596   * @param  pAddress : pointer to NAND address structure
00597   * @param  pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
00598   * @param  NumPageToRead : number of pages to read from block
00599   * @retval HAL status
00600   */
00601 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
00602 {
00603   __IO uint32_t index  = 0U;
00604   uint32_t tickstart = 0U;
00605   uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
00606
00607   /* Process Locked */
00608   __HAL_LOCK(hnand);
00609
00610   /* Check the NAND controller state */
00611   if(hnand->State == HAL_NAND_STATE_BUSY)
00612   {
00613      return HAL_BUSY;
00614   }
00615
00616   /* Identify the device address */
00617   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
00618   {
00619     deviceaddress = NAND_DEVICE1;
00620   }
00621   else
00622   {
00623     deviceaddress = NAND_DEVICE2;
00624   }
00625
00626   /* Update the NAND controller state */
00627   hnand->State = HAL_NAND_STATE_BUSY;
00628
00629   /* NAND raw address calculation */
00630   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00631
00632   /* Page(s) read loop */
00633   while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00634   {
00635     /* update the buffer size */
00636     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
00637
00638     /* Send read page command sequence */
00639     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00640
00641     /* Cards with page size <= 512 bytes */
00642     if((hnand->Config.PageSize) <= 512U)
00643     {
00644       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00645       {
00646         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00647         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00648         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00649       }
00650       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00651       {
00652         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00653         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00654         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00655         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00656       }
00657     }
00658     else /* (hnand->Config.PageSize) > 512 */
00659     {
00660       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00661       {
00662         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00663         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00664         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00665         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00666       }
00667       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00668       {
00669         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00670         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00671         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00672         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00673         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00674       }
00675     }
00676
00677     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA))  = NAND_CMD_AREA_TRUE1;
00678
00679     if(hnand->Config.ExtraCommandEnable == ENABLE)
00680     {
00681       /* Get tick */
00682       tickstart = HAL_GetTick();
00683
00684       /* Read status until NAND is ready */
00685       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00686       {
00687         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00688         {
00689           return HAL_TIMEOUT;
00690         }
00691       }
00692
00693       /* Go back to read mode */
00694       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
00695     }
00696
00697     /* Get Data into Buffer */
00698     for(; index < size; index++)
00699     {
00700       *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
00701     }
00702
00703     /* Increment read pages number */
00704     numPagesRead++;
00705
00706     /* Decrement pages to read */
00707     NumPageToRead--;
00708
00709     /* Increment the NAND address */
00710     nandaddress = (uint32_t)(nandaddress + 1U);
00711   }
00712
00713   /* Update the NAND controller state */
00714   hnand->State = HAL_NAND_STATE_READY;
00715
00716   /* Process unlocked */
00717   __HAL_UNLOCK(hnand);
00718
00719   return HAL_OK;
00720 }
00721
00722 /**
00723   * @brief  Write Page(s) to NAND memory block (8-bits addressing)
00724   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00725   *                the configuration information for NAND module.
00726   * @param  pAddress : pointer to NAND address structure
00727   * @param  pBuffer : pointer to source buffer to write
00728   * @param  NumPageToWrite  : number of pages to write to block
00729   * @retval HAL status
00730   */
00731 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
00732 {
00733   __IO uint32_t index = 0U;
00734   uint32_t tickstart = 0U;
00735   uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
00736
00737   /* Process Locked */
00738   __HAL_LOCK(hnand);
00739
00740   /* Check the NAND controller state */
00741   if(hnand->State == HAL_NAND_STATE_BUSY)
00742   {
00743      return HAL_BUSY;
00744   }
00745
00746   /* Identify the device address */
00747   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
00748   {
00749     deviceaddress = NAND_DEVICE1;
00750   }
00751   else
00752   {
00753     deviceaddress = NAND_DEVICE2;
00754   }
00755
00756   /* Update the NAND controller state */
00757   hnand->State = HAL_NAND_STATE_BUSY;
00758
00759   /* NAND raw address calculation */
00760   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00761
00762   /* Page(s) write loop */
00763   while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00764   {
00765     /* update the buffer size */
00766     size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
00767
00768     /* Send write page command sequence */
00769     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00770     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
00771
00772     /* Cards with page size <= 512 bytes */
00773     if((hnand->Config.PageSize) <= 512U)
00774     {
00775       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00776       {
00777         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00778         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00779         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00780       }
00781       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00782       {
00783         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00784         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00785         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00786         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00787       }
00788     }
00789     else /* (hnand->Config.PageSize) > 512 */
00790     {
00791       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00792       {
00793         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00794         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00795         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00796         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00797       }
00798       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00799       {
00800         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00801         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00802         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00803         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00804         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00805       }
00806     }
00807
00808
00809     /* Write data to memory */
00810     for(; index < size; index++)
00811     {
00812       *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
00813     }
00814
00815     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00816
00817     /* Read status until NAND is ready */
00818     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00819     {
00820       /* Get tick */
00821       tickstart = HAL_GetTick();
00822
00823       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00824       {
00825         return HAL_TIMEOUT;
00826       }
00827     }
00828
00829     /* Increment written pages number */
00830     numPagesWritten++;
00831
00832     /* Decrement pages to write */
00833     NumPageToWrite--;
00834
00835     /* Increment the NAND address */
00836     nandaddress = (uint32_t)(nandaddress + 1U);
00837   }
00838
00839   /* Update the NAND controller state */
00840   hnand->State = HAL_NAND_STATE_READY;
00841
00842   /* Process unlocked */
00843   __HAL_UNLOCK(hnand);
00844
00845   return HAL_OK;
00846 }
00847
00848 /**
00849   * @brief  Write Page(s) to NAND memory block (16-bits addressing)
00850   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00851   *                the configuration information for NAND module.
00852   * @param  pAddress : pointer to NAND address structure
00853   * @param  pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
00854   * @param  NumPageToWrite  : number of pages to write to block
00855   * @retval HAL status
00856   */
00857 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
00858 {
00859   __IO uint32_t index = 0U;
00860   uint32_t tickstart = 0U;
00861   uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
00862
00863   /* Process Locked */
00864   __HAL_LOCK(hnand);
00865
00866   /* Check the NAND controller state */
00867   if(hnand->State == HAL_NAND_STATE_BUSY)
00868   {
00869      return HAL_BUSY;
00870   }
00871
00872   /* Identify the device address */
00873   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
00874   {
00875     deviceaddress = NAND_DEVICE1;
00876   }
00877   else
00878   {
00879     deviceaddress = NAND_DEVICE2;
00880   }
00881
00882   /* Update the NAND controller state */
00883   hnand->State = HAL_NAND_STATE_BUSY;
00884
00885   /* NAND raw address calculation */
00886   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
00887
00888   /* Page(s) write loop */
00889   while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
00890   {
00891     /* update the buffer size */
00892     size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
00893
00894     /* Send write page command sequence */
00895     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
00896     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
00897
00898     /* Cards with page size <= 512 bytes */
00899     if((hnand->Config.PageSize) <= 512U)
00900     {
00901       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00902       {
00903         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00904         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00905         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00906       }
00907       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00908       {
00909         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00910         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00911         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00912         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00913       }
00914     }
00915     else /* (hnand->Config.PageSize) > 512 */
00916     {
00917       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
00918       {
00919         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00920         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00921         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00922         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00923       }
00924       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
00925       {
00926         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00927         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
00928         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
00929         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
00930         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
00931       }
00932     }
00933
00934     /* Write data to memory */
00935     for(; index < size; index++)
00936     {
00937       *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
00938     }
00939
00940     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
00941
00942     /* Read status until NAND is ready */
00943     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
00944     {
00945       /* Get tick */
00946       tickstart = HAL_GetTick();
00947
00948       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
00949       {
00950         return HAL_TIMEOUT;
00951       }
00952     }
00953
00954     /* Increment written pages number */
00955     numPagesWritten++;
00956
00957     /* Decrement pages to write */
00958     NumPageToWrite--;
00959
00960     /* Increment the NAND address */
00961     nandaddress = (uint32_t)(nandaddress + 1U);
00962   }
00963
00964   /* Update the NAND controller state */
00965   hnand->State = HAL_NAND_STATE_READY;
00966
00967   /* Process unlocked */
00968   __HAL_UNLOCK(hnand);
00969
00970   return HAL_OK;
00971 }
00972
00973 /**
00974   * @brief  Read Spare area(s) from NAND memory (8-bits addressing)
00975   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
00976   *                the configuration information for NAND module.
00977   * @param  pAddress : pointer to NAND address structure
00978   * @param  pBuffer: pointer to source buffer to write
00979   * @param  NumSpareAreaToRead: Number of spare area to read
00980   * @retval HAL status
00981 */
00982 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
00983 {
00984   __IO uint32_t index = 0U;
00985   uint32_t tickstart = 0U;
00986   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
00987
00988   /* Process Locked */
00989   __HAL_LOCK(hnand);
00990
00991   /* Check the NAND controller state */
00992   if(hnand->State == HAL_NAND_STATE_BUSY)
00993   {
00994      return HAL_BUSY;
00995   }
00996
00997   /* Identify the device address */
00998   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
00999   {
01000     deviceaddress = NAND_DEVICE1;
01001   }
01002   else
01003   {
01004     deviceaddress = NAND_DEVICE2;
01005   }
01006
01007   /* Update the NAND controller state */
01008   hnand->State = HAL_NAND_STATE_BUSY;
01009
01010   /* NAND raw address calculation */
01011   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01012
01013   /* Column in page address */
01014   columnaddress = COLUMN_ADDRESS(hnand);
01015
01016   /* Spare area(s) read loop */
01017   while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01018   {
01019     /* update the buffer size */
01020     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
01021
01022     /* Cards with page size <= 512 bytes */
01023     if((hnand->Config.PageSize) <= 512U)
01024     {
01025       /* Send read spare area command sequence */
01026       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01027
01028       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01029       {
01030         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01031         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01032         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01033       }
01034       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01035       {
01036         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01037         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01038         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01039         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01040       }
01041     }
01042     else /* (hnand->Config.PageSize) > 512 */
01043     {
01044       /* Send read spare area command sequence */
01045       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01046
01047       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01048       {
01049         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01050         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01051         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01052         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01053       }
01054       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01055       {
01056         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01057         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01058         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01059         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01060         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01061       }
01062     }
01063
01064     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
01065
01066     if(hnand->Config.ExtraCommandEnable == ENABLE)
01067     {
01068       /* Get tick */
01069       tickstart = HAL_GetTick();
01070
01071       /* Read status until NAND is ready */
01072       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01073       {
01074         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01075         {
01076           return HAL_TIMEOUT;
01077         }
01078       }
01079
01080       /* Go back to read mode */
01081       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
01082     }
01083
01084     /* Get Data into Buffer */
01085     for(; index < size; index++)
01086     {
01087       *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
01088     }
01089
01090     /* Increment read spare areas number */
01091     numSpareAreaRead++;
01092
01093     /* Decrement spare areas to read */
01094     NumSpareAreaToRead--;
01095
01096     /* Increment the NAND address */
01097     nandaddress = (uint32_t)(nandaddress + 1U);
01098   }
01099
01100   /* Update the NAND controller state */
01101   hnand->State = HAL_NAND_STATE_READY;
01102
01103   /* Process unlocked */
01104   __HAL_UNLOCK(hnand);
01105
01106   return HAL_OK;
01107 }
01108
01109 /**
01110   * @brief  Read Spare area(s) from NAND memory (16-bits addressing)
01111   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01112   *                the configuration information for NAND module.
01113   * @param  pAddress : pointer to NAND address structure
01114   * @param  pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
01115   * @param  NumSpareAreaToRead: Number of spare area to read
01116   * @retval HAL status
01117 */
01118 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
01119 {
01120   __IO uint32_t index = 0U;
01121   uint32_t tickstart = 0U;
01122   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
01123
01124   /* Process Locked */
01125   __HAL_LOCK(hnand);
01126
01127   /* Check the NAND controller state */
01128   if(hnand->State == HAL_NAND_STATE_BUSY)
01129   {
01130      return HAL_BUSY;
01131   }
01132
01133   /* Identify the device address */
01134   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
01135   {
01136     deviceaddress = NAND_DEVICE1;
01137   }
01138   else
01139   {
01140     deviceaddress = NAND_DEVICE2;
01141   }
01142
01143   /* Update the NAND controller state */
01144   hnand->State = HAL_NAND_STATE_BUSY;
01145
01146   /* NAND raw address calculation */
01147   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01148
01149   /* Column in page address */
01150   columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
01151
01152   /* Spare area(s) read loop */
01153   while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01154   {
01155     /* update the buffer size */
01156     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
01157
01158     /* Cards with page size <= 512 bytes */
01159     if((hnand->Config.PageSize) <= 512U)
01160     {
01161       /* Send read spare area command sequence */
01162       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01163
01164       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01165       {
01166         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01167         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01168         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01169       }
01170       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01171       {
01172         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01173         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01174         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01175         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01176       }
01177     }
01178     else /* (hnand->Config.PageSize) > 512 */
01179     {
01180       /* Send read spare area command sequence */
01181       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01182
01183       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01184       {
01185         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01186         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01187         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01188         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01189       }
01190       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01191       {
01192         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01193         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01194         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01195         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01196         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01197       }
01198     }
01199
01200     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
01201
01202     if(hnand->Config.ExtraCommandEnable == ENABLE)
01203     {
01204       /* Get tick */
01205       tickstart = HAL_GetTick();
01206
01207       /* Read status until NAND is ready */
01208       while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01209       {
01210         if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01211         {
01212           return HAL_TIMEOUT;
01213         }
01214       }
01215
01216       /* Go back to read mode */
01217       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
01218     }
01219
01220     /* Get Data into Buffer */
01221     for(; index < size; index++)
01222     {
01223       *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
01224     }
01225
01226     /* Increment read spare areas number */
01227     numSpareAreaRead++;
01228
01229     /* Decrement spare areas to read */
01230     NumSpareAreaToRead--;
01231
01232     /* Increment the NAND address */
01233     nandaddress = (uint32_t)(nandaddress + 1U);
01234   }
01235
01236   /* Update the NAND controller state */
01237   hnand->State = HAL_NAND_STATE_READY;
01238
01239   /* Process unlocked */
01240   __HAL_UNLOCK(hnand);
01241
01242   return HAL_OK;
01243 }
01244
01245 /**
01246   * @brief  Write Spare area(s) to NAND memory (8-bits addressing)
01247   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01248   *                the configuration information for NAND module.
01249   * @param  pAddress : pointer to NAND address structure
01250   * @param  pBuffer : pointer to source buffer to write
01251   * @param  NumSpareAreaTowrite  : number of spare areas to write to block
01252   * @retval HAL status
01253   */
01254 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
01255 {
01256   __IO uint32_t index = 0U;
01257   uint32_t tickstart = 0U;
01258   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
01259
01260   /* Process Locked */
01261   __HAL_LOCK(hnand);
01262
01263   /* Check the NAND controller state */
01264   if(hnand->State == HAL_NAND_STATE_BUSY)
01265   {
01266      return HAL_BUSY;
01267   }
01268
01269   /* Identify the device address */
01270   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
01271   {
01272     deviceaddress = NAND_DEVICE1;
01273   }
01274   else
01275   {
01276     deviceaddress = NAND_DEVICE2;
01277   }
01278
01279   /* Update the FSMC_NAND controller state */
01280   hnand->State = HAL_NAND_STATE_BUSY;
01281
01282   /* Page address calculation */
01283   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01284
01285   /* Column in page address */
01286   columnaddress = COLUMN_ADDRESS(hnand);
01287
01288   /* Spare area(s) write loop */
01289   while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01290   {
01291     /* update the buffer size */
01292     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
01293
01294     /* Cards with page size <= 512 bytes */
01295     if((hnand->Config.PageSize) <= 512U)
01296     {
01297       /* Send write Spare area command sequence */
01298       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01299       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01300
01301       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01302       {
01303         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01304         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01305         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01306       }
01307       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01308       {
01309         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01310         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01311         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01312         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01313       }
01314     }
01315     else /* (hnand->Config.PageSize) > 512 */
01316     {
01317       /* Send write Spare area command sequence */
01318       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01319       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01320
01321       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01322       {
01323         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01324         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01325         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01326         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01327       }
01328       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01329       {
01330         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01331         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01332         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01333         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01334         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01335       }
01336     }
01337
01338     /* Write data to memory */
01339     for(; index < size; index++)
01340     {
01341       *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
01342     }
01343
01344     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01345
01346     /* Get tick */
01347     tickstart = HAL_GetTick();
01348
01349     /* Read status until NAND is ready */
01350     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01351     {
01352       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01353       {
01354         return HAL_TIMEOUT;
01355       }
01356     }
01357
01358     /* Increment written spare areas number */
01359     numSpareAreaWritten++;
01360
01361     /* Decrement spare areas to write */
01362     NumSpareAreaTowrite--;
01363
01364     /* Increment the NAND address */
01365     nandaddress = (uint32_t)(nandaddress + 1U);
01366   }
01367
01368   /* Update the NAND controller state */
01369   hnand->State = HAL_NAND_STATE_READY;
01370
01371   /* Process unlocked */
01372   __HAL_UNLOCK(hnand);
01373
01374   return HAL_OK;
01375 }
01376
01377 /**
01378   * @brief  Write Spare area(s) to NAND memory (16-bits addressing)
01379   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01380   *                the configuration information for NAND module.
01381   * @param  pAddress : pointer to NAND address structure
01382   * @param  pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
01383   * @param  NumSpareAreaTowrite  : number of spare areas to write to block
01384   * @retval HAL status
01385   */
01386 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
01387 {
01388   __IO uint32_t index = 0U;
01389   uint32_t tickstart = 0U;
01390   uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
01391
01392   /* Process Locked */
01393   __HAL_LOCK(hnand);
01394
01395   /* Check the NAND controller state */
01396   if(hnand->State == HAL_NAND_STATE_BUSY)
01397   {
01398      return HAL_BUSY;
01399   }
01400
01401   /* Identify the device address */
01402   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
01403   {
01404     deviceaddress = NAND_DEVICE1;
01405   }
01406   else
01407   {
01408     deviceaddress = NAND_DEVICE2;
01409   }
01410
01411   /* Update the FSMC_NAND controller state */
01412   hnand->State = HAL_NAND_STATE_BUSY;
01413
01414   /* NAND raw address calculation */
01415   nandaddress = ARRAY_ADDRESS(pAddress, hnand);
01416
01417   /* Column in page address */
01418   columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
01419
01420   /* Spare area(s) write loop */
01421   while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
01422   {
01423     /* update the buffer size */
01424     size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
01425
01426     /* Cards with page size <= 512 bytes */
01427     if((hnand->Config.PageSize) <= 512U)
01428     {
01429       /* Send write Spare area command sequence */
01430       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
01431       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01432
01433       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01434       {
01435         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01436         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01437         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01438       }
01439       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01440       {
01441         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
01442         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01443         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01444         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01445       }
01446     }
01447     else /* (hnand->Config.PageSize) > 512 */
01448     {
01449       /* Send write Spare area command sequence */
01450       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
01451       *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
01452
01453       if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
01454       {
01455         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01456         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01457         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01458         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01459       }
01460       else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
01461       {
01462         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
01463         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
01464         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
01465         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
01466         *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
01467       }
01468     }
01469
01470     /* Write data to memory */
01471     for(; index < size; index++)
01472     {
01473       *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
01474     }
01475
01476     *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
01477
01478     /* Read status until NAND is ready */
01479     while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01480     {
01481       /* Get tick */
01482       tickstart = HAL_GetTick();
01483
01484       if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01485       {
01486         return HAL_TIMEOUT;
01487       }
01488     }
01489
01490     /* Increment written spare areas number */
01491     numSpareAreaWritten++;
01492
01493     /* Decrement spare areas to write */
01494     NumSpareAreaTowrite--;
01495
01496     /* Increment the NAND address */
01497     nandaddress = (uint32_t)(nandaddress + 1U);
01498   }
01499
01500   /* Update the NAND controller state */
01501   hnand->State = HAL_NAND_STATE_READY;
01502
01503   /* Process unlocked */
01504   __HAL_UNLOCK(hnand);
01505
01506   return HAL_OK;
01507 }
01508
01509 /**
01510   * @brief  NAND memory Block erase
01511   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01512   *                the configuration information for NAND module.
01513   * @param  pAddress : pointer to NAND address structure
01514   * @retval HAL status
01515   */
01516 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
01517 {
01518   uint32_t deviceaddress = 0U;
01519   uint32_t tickstart = 0U;
01520
01521   /* Process Locked */
01522   __HAL_LOCK(hnand);
01523
01524   /* Check the NAND controller state */
01525   if(hnand->State == HAL_NAND_STATE_BUSY)
01526   {
01527      return HAL_BUSY;
01528   }
01529
01530   /* Identify the device address */
01531   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
01532   {
01533     deviceaddress = NAND_DEVICE1;
01534   }
01535   else
01536   {
01537     deviceaddress = NAND_DEVICE2;
01538   }
01539
01540   /* Update the NAND controller state */
01541   hnand->State = HAL_NAND_STATE_BUSY;
01542
01543   /* Send Erase block command sequence */
01544   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
01545
01546   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01547   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01548   *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
01549
01550   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
01551
01552   /* Update the NAND controller state */
01553   hnand->State = HAL_NAND_STATE_READY;
01554
01555   /* Get tick */
01556   tickstart = HAL_GetTick();
01557
01558   /* Read status until NAND is ready */
01559   while(HAL_NAND_Read_Status(hnand) != NAND_READY)
01560   {
01561     if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
01562     {
01563       /* Process unlocked */
01564       __HAL_UNLOCK(hnand);
01565
01566       return HAL_TIMEOUT;
01567     }
01568   }
01569
01570   /* Process unlocked */
01571   __HAL_UNLOCK(hnand);
01572
01573   return HAL_OK;
01574 }
01575
01576 /**
01577   * @brief  NAND memory read status
01578   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01579   *                the configuration information for NAND module.
01580   * @retval NAND status
01581   */
01582 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
01583 {
01584   uint32_t data = 0U;
01585   uint32_t deviceaddress = 0U;
01586
01587   /* Identify the device address */
01588   if(hnand->Init.NandBank == FSMC_NAND_BANK2)
01589   {
01590     deviceaddress = NAND_DEVICE1;
01591   }
01592   else
01593   {
01594     deviceaddress = NAND_DEVICE2;
01595   }
01596
01597   /* Send Read status operation command */
01598   *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
01599
01600   /* Read status register data */
01601   data = *(__IO uint8_t *)deviceaddress;
01602
01603   /* Return the status */
01604   if((data & NAND_ERROR) == NAND_ERROR)
01605   {
01606     return NAND_ERROR;
01607   }
01608   else if((data & NAND_READY) == NAND_READY)
01609   {
01610     return NAND_READY;
01611   }
01612
01613   return NAND_BUSY;
01614 }
01615
01616 /**
01617   * @brief  Increment the NAND memory address
01618   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01619   *                the configuration information for NAND module.
01620   * @param pAddress: pointer to NAND address structure
01621   * @retval The new status of the increment address operation. It can be:
01622   *           - NAND_VALID_ADDRESS: When the new address is valid address
01623   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
01624   */
01625 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
01626 {
01627   uint32_t status = NAND_VALID_ADDRESS;
01628
01629   /* Increment page address */
01630   pAddress->Page++;
01631
01632   /* Check NAND address is valid */
01633   if(pAddress->Page == hnand->Config.BlockSize)
01634   {
01635     pAddress->Page = 0U;
01636     pAddress->Block++;
01637
01638     if(pAddress->Block == hnand->Config.PlaneSize)
01639     {
01640       pAddress->Block = 0U;
01641       pAddress->Plane++;
01642
01643       if(pAddress->Plane == (hnand->Config.PlaneNbr))
01644       {
01645         status = NAND_INVALID_ADDRESS;
01646       }
01647     }
01648   }
01649
01650   return (status);
01651 }
01652 /**
01653   * @}
01654   */
01655
01656 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
01657  *  @brief   management functions
01658  *
01659 @verbatim
01660   ==============================================================================
01661                          ##### NAND Control functions #####
01662   ==============================================================================
01663   [..]
01664     This subsection provides a set of functions allowing to control dynamically
01665     the NAND interface.
01666
01667 @endverbatim
01668   * @{
01669   */
01670
01671
01672 /**
01673   * @brief  Enables dynamically NAND ECC feature.
01674   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01675   *                the configuration information for NAND module.
01676   * @retval HAL status
01677   */
01678 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
01679 {
01680   /* Check the NAND controller state */
01681   if(hnand->State == HAL_NAND_STATE_BUSY)
01682   {
01683      return HAL_BUSY;
01684   }
01685
01686   /* Update the NAND state */
01687   hnand->State = HAL_NAND_STATE_BUSY;
01688
01689   /* Enable ECC feature */
01690   FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
01691
01692   /* Update the NAND state */
01693   hnand->State = HAL_NAND_STATE_READY;
01694
01695   return HAL_OK;
01696 }
01697
01698 /**
01699   * @brief  Disables dynamically FSMC_NAND ECC feature.
01700   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01701   *                the configuration information for NAND module.
01702   * @retval HAL status
01703   */
01704 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
01705 {
01706   /* Check the NAND controller state */
01707   if(hnand->State == HAL_NAND_STATE_BUSY)
01708   {
01709      return HAL_BUSY;
01710   }
01711
01712   /* Update the NAND state */
01713   hnand->State = HAL_NAND_STATE_BUSY;
01714
01715   /* Disable ECC feature */
01716   FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
01717
01718   /* Update the NAND state */
01719   hnand->State = HAL_NAND_STATE_READY;
01720
01721   return HAL_OK;
01722 }
01723
01724 /**
01725   * @brief  Disables dynamically NAND ECC feature.
01726   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01727   *                the configuration information for NAND module.
01728   * @param  ECCval: pointer to ECC value
01729   * @param  Timeout: maximum timeout to wait
01730   * @retval HAL status
01731   */
01732 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
01733 {
01734   HAL_StatusTypeDef status = HAL_OK;
01735
01736   /* Check the NAND controller state */
01737   if(hnand->State == HAL_NAND_STATE_BUSY)
01738   {
01739      return HAL_BUSY;
01740   }
01741
01742   /* Update the NAND state */
01743   hnand->State = HAL_NAND_STATE_BUSY;
01744
01745   /* Get NAND ECC value */
01746   status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
01747
01748   /* Update the NAND state */
01749   hnand->State = HAL_NAND_STATE_READY;
01750
01751   return status;
01752 }
01753
01754 /**
01755   * @}
01756   */
01757
01758
01759 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
01760  *  @brief   Peripheral State functions
01761  *
01762 @verbatim
01763   ==============================================================================
01764                          ##### NAND State functions #####
01765   ==============================================================================
01766   [..]
01767     This subsection permits to get in run-time the status of the NAND controller
01768     and the data flow.
01769
01770 @endverbatim
01771   * @{
01772   */
01773
01774 /**
01775   * @brief  return the NAND state
01776   * @param  hnand: pointer to a NAND_HandleTypeDef structure that contains
01777   *                the configuration information for NAND module.
01778   * @retval HAL state
01779   */
01780 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
01781 {
01782   return hnand->State;
01783 }
01784
01785 /**
01786   * @}
01787   */
01788
01789 /**
01790   * @}
01791   */
01792
01793 /**
01794   * @}
01795   */
01796
01797 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
01798 #endif /* HAL_NAND_MODULE_ENABLED  */
01799
01800 /**
01801   * @}
01802   */
01803
01804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_nand.h Source File

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stm32f1xx_hal_nand.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_nand.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of NAND HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_NAND_H
00040 #define __STM32F1xx_HAL_NAND_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_ll_fsmc.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
00054 /** @addtogroup NAND
00055   * @{
00056   */
00057
00058
00059 /* Exported typedef ----------------------------------------------------------*/
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup NAND_Exported_Types NAND Exported Types
00062   * @{
00063   */
00064
00065 /**
00066   * @brief  HAL NAND State structures definition
00067   */
00068 typedef enum
00069 {
00070   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
00071   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
00072   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
00073   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
00074 }HAL_NAND_StateTypeDef;
00075
00076 /**
00077   * @brief  NAND Memory electronic signature Structure definition
00078   */
00079 typedef struct
00080 {
00081   /*<! NAND memory electronic signature maker and device IDs */
00082
00083   uint8_t Maker_Id;
00084
00085   uint8_t Device_Id;
00086
00087   uint8_t Third_Id;
00088
00089   uint8_t Fourth_Id;
00090 }NAND_IDTypeDef;
00091
00092 /**
00093   * @brief  NAND Memory address Structure definition
00094   */
00095 typedef struct
00096 {
00097   uint16_t Page;   /*!< NAND memory Page address    */
00098
00099   uint16_t Plane;   /*!< NAND memory Plane address  */
00100
00101   uint16_t Block;  /*!< NAND memory Block address   */
00102
00103 }NAND_AddressTypeDef;
00104
00105 /**
00106   * @brief  NAND Memory info Structure definition
00107   */
00108 typedef struct
00109 {
00110   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
00111                                               for 8 bits adressing or words for 16 bits addressing             */
00112
00113   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
00114                                               for 8 bits adressing or words for 16 bits addressing             */
00115
00116   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
00117
00118   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
00119
00120   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
00121
00122   uint32_t        PlaneSize;             /*!< NAND memory plane size measured in number of blocks              */
00123
00124   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
00125                                               parameter is mandatory for some NAND parts after the read
00126                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
00127                                               Example: Toshiba THTH58BYG3S0HBAI6.
00128                                               This parameter could be ENABLE or DISABLE
00129                                               Please check the Read Mode sequnece in the NAND device datasheet */
00130 }NAND_DeviceConfigTypeDef;
00131
00132 /**
00133   * @brief  NAND handle Structure definition
00134   */
00135 typedef struct
00136 {
00137   FSMC_NAND_TypeDef              *Instance;  /*!< Register base address                                 */
00138
00139   FSMC_NAND_InitTypeDef          Init;       /*!< NAND device control configuration parameters          */
00140
00141   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
00142
00143   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
00144
00145   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
00146
00147 }NAND_HandleTypeDef;
00148
00149 /**
00150   * @}
00151   */
00152
00153 /* Exported constants --------------------------------------------------------*/
00154 /* Exported macros -----------------------------------------------------------*/
00155 /** @defgroup NAND_Exported_Macros NAND Exported Macros
00156   * @{
00157   */
00158
00159 /** @brief Reset NAND handle state
00160   * @param  __HANDLE__: specifies the NAND handle.
00161   * @retval None
00162   */
00163 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
00164
00165 /**
00166   * @}
00167   */
00168
00169 /* Exported functions --------------------------------------------------------*/
00170 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
00171   * @{
00172   */
00173
00174 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
00175   * @{
00176   */
00177
00178 /* Initialization/de-initialization functions  ********************************/
00179 HAL_StatusTypeDef   HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
00180 HAL_StatusTypeDef   HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
00181
00182 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
00183
00184 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
00185
00186 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
00187 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
00188 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
00189 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
00190
00191 /**
00192   * @}
00193   */
00194
00195 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
00196   * @{
00197   */
00198
00199 /* IO operation functions  ****************************************************/
00200
00201 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
00202
00203 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
00204 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
00205 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
00206 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
00207
00208 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
00209 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
00210 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
00211 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
00212
00213 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00214 uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00215 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
00216
00217 /**
00218   * @}
00219   */
00220
00221 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
00222   * @{
00223   */
00224
00225 /* NAND Control functions  ****************************************************/
00226 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
00227 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
00228 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
00229
00230 /**
00231   * @}
00232   */
00233
00234 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
00235   * @{
00236   */
00237
00238 /* NAND State functions *******************************************************/
00239 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
00240 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
00241
00242 /**
00243   * @}
00244   */
00245
00246 /**
00247   * @}
00248   */
00249 /* Private types -------------------------------------------------------------*/
00250 /* Private variables ---------------------------------------------------------*/
00251 /* Private constants ---------------------------------------------------------*/
00252 /** @addtogroup NAND_Private_Constants
00253   * @{
00254   */
00255
00256 #define NAND_DEVICE1               FSMC_BANK2
00257 #define NAND_DEVICE2               FSMC_BANK3
00258 #define NAND_WRITE_TIMEOUT         1000U
00259
00260 #define CMD_AREA                   (1U<<16U)  /* A16 = CLE high */
00261 #define ADDR_AREA                  (1U<<17U)  /* A17 = ALE high */
00262
00263 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
00264 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
00265 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
00266 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
00267
00268 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
00269 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
00270 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
00271 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
00272 #define NAND_CMD_READID            ((uint8_t)0x90)
00273 #define NAND_CMD_STATUS            ((uint8_t)0x70)
00274 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
00275 #define NAND_CMD_RESET             ((uint8_t)0xFF)
00276
00277 /* NAND memory status */
00278 #define NAND_VALID_ADDRESS         0x00000100U
00279 #define NAND_INVALID_ADDRESS       0x00000200U
00280 #define NAND_TIMEOUT_ERROR         0x00000400U
00281 #define NAND_BUSY                  0x00000000U
00282 #define NAND_ERROR                 0x00000001U
00283 #define NAND_READY                 0x00000040U
00284
00285 /**
00286   * @}
00287   */
00288
00289 /* Private macros ------------------------------------------------------------*/
00290 /** @addtogroup NAND_Private_Macros
00291   * @{
00292   */
00293
00294 /**
00295   * @brief  NAND memory address computation.
00296   * @param  __ADDRESS__: NAND memory address.
00297   * @param  __HANDLE__ : NAND handle.
00298   * @retval NAND Raw address value
00299   */
00300 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
00301                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
00302
00303 /**
00304   * @brief  NAND memory Column address computation.
00305   * @param  __HANDLE__: NAND handle.
00306   * @retval NAND Raw address value
00307   */
00308 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
00309
00310 /**
00311   * @brief  NAND memory address cycling.
00312   * @param  __ADDRESS__: NAND memory address.
00313   * @retval NAND address cycling value.
00314   */
00315 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)               /* 1st addressing cycle */
00316 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8U)       /* 2nd addressing cycle */
00317 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16U)      /* 3rd addressing cycle */
00318 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24U)      /* 4th addressing cycle */
00319
00320 /**
00321   * @brief  NAND memory Columns cycling.
00322   * @param  __ADDRESS__: NAND memory address.
00323   * @retval NAND Column address cycling value.
00324   */
00325 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
00326 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8U)      /* 2nd Column addressing cycle */
00327
00328 /**
00329   * @}
00330   */
00331
00332 /**
00333   * @}
00334   */
00335 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
00336
00337 /**
00338   * @}
00339   */
00340
00341 #ifdef __cplusplus
00342 }
00343 #endif
00344
00345 #endif /* __STM32F1xx_HAL_NAND_H */
00346
00347 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_nor.c Source File

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stm32f1xx_hal_nor.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_nor.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   NOR HAL module driver.
00008   *          This file provides a generic firmware to drive NOR memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                      ##### How to use this driver #####
00014   ==============================================================================
00015     [..]
00016       This driver is a generic layered driver which contains a set of APIs used to
00017       control NOR flash memories. It uses the FSMC layer functions to interface
00018       with NOR devices. This driver is used as follows:
00019
00020       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
00021           with control and timing parameters for both normal and extended mode.
00022
00023       (+) Read NOR flash memory manufacturer code and device IDs using the function
00024           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
00025           structure declared by the function caller.
00026
00027       (+) Access NOR flash memory by read/write data unit operations using the functions
00028           HAL_NOR_Read(), HAL_NOR_Program().
00029
00030       (+) Perform NOR flash erase block/chip operations using the functions
00031           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
00032
00033       (+) Read the NOR flash CFI (common flash interface) IDs using the function
00034           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
00035           structure declared by the function caller.
00036
00037       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
00038           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
00039
00040       (+) You can monitor the NOR device HAL state by calling the function
00041           HAL_NOR_GetState()
00042     [..]
00043      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
00044          If a NOR flash device contains different operations and/or implementations,
00045          it should be implemented separately.
00046
00047      *** NOR HAL driver macros list ***
00048      =============================================
00049      [..]
00050        Below the list of most used macros in NOR HAL driver.
00051
00052       (+) NOR_WRITE : NOR memory write data to specified address
00053
00054   @endverbatim
00055   ******************************************************************************
00056   * @attention
00057   *
00058   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00059   *
00060   * Redistribution and use in source and binary forms, with or without modification,
00061   * are permitted provided that the following conditions are met:
00062   *   1. Redistributions of source code must retain the above copyright notice,
00063   *      this list of conditions and the following disclaimer.
00064   *   2. Redistributions in binary form must reproduce the above copyright notice,
00065   *      this list of conditions and the following disclaimer in the documentation
00066   *      and/or other materials provided with the distribution.
00067   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00068   *      may be used to endorse or promote products derived from this software
00069   *      without specific prior written permission.
00070   *
00071   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00072   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00073   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00074   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00075   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00076   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00077   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00078   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00079   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00080   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00081   *
00082   ******************************************************************************
00083   */
00084
00085 /* Includes ------------------------------------------------------------------*/
00086 #include "stm32f1xx_hal.h"
00087
00088 /** @addtogroup STM32F1xx_HAL_Driver
00089   * @{
00090   */
00091
00092 #ifdef HAL_NOR_MODULE_ENABLED
00093 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
00094
00095 /** @defgroup NOR NOR
00096   * @brief NOR driver modules
00097   * @{
00098   */
00099 /* Private typedef -----------------------------------------------------------*/
00100 /* Private define ------------------------------------------------------------*/
00101 /** @defgroup NOR_Private_Constants NOR Private Constants
00102   * @{
00103   */
00104
00105 /* Constants to define address to set to write a command */
00106 #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
00107 #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
00108 #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
00109 #define NOR_CMD_ADDRESS_THIRD                 (uint16_t)0x0555
00110 #define NOR_CMD_ADDRESS_FOURTH                (uint16_t)0x0555
00111 #define NOR_CMD_ADDRESS_FIFTH                 (uint16_t)0x02AA
00112 #define NOR_CMD_ADDRESS_SIXTH                 (uint16_t)0x0555
00113
00114 /* Constants to define data to program a command */
00115 #define NOR_CMD_DATA_READ_RESET               (uint16_t)0x00F0
00116 #define NOR_CMD_DATA_FIRST                    (uint16_t)0x00AA
00117 #define NOR_CMD_DATA_SECOND                   (uint16_t)0x0055
00118 #define NOR_CMD_DATA_AUTO_SELECT              (uint16_t)0x0090
00119 #define NOR_CMD_DATA_PROGRAM                  (uint16_t)0x00A0
00120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD   (uint16_t)0x0080
00121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH  (uint16_t)0x00AA
00122 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH   (uint16_t)0x0055
00123 #define NOR_CMD_DATA_CHIP_ERASE               (uint16_t)0x0010
00124 #define NOR_CMD_DATA_CFI                      (uint16_t)0x0098
00125
00126 #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
00127 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
00128 #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
00129
00130 /* Mask on NOR STATUS REGISTER */
00131 #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
00132 #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
00133
00134 /**
00135   * @}
00136   */
00137
00138 /* Private macro -------------------------------------------------------------*/
00139 /** @defgroup NOR_Private_Macros NOR Private Macros
00140   * @{
00141   */
00142
00143 /**
00144   * @}
00145   */
00146
00147 /* Private variables ---------------------------------------------------------*/
00148
00149 /** @defgroup NOR_Private_Variables NOR Private Variables
00150   * @{
00151   */
00152
00153 static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
00154
00155 /**
00156   * @}
00157   */
00158
00159 /* Private function prototypes -----------------------------------------------*/
00160 /* Private functions ---------------------------------------------------------*/
00161
00162 /** @defgroup NOR_Exported_Functions NOR Exported Functions
00163   * @{
00164   */
00165
00166 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
00167   * @brief    Initialization and Configuration functions
00168   *
00169   @verbatim
00170   ==============================================================================
00171            ##### NOR Initialization and de_initialization functions #####
00172   ==============================================================================
00173   [..]
00174     This section provides functions allowing to initialize/de-initialize
00175     the NOR memory
00176
00177 @endverbatim
00178   * @{
00179   */
00180
00181 /**
00182   * @brief  Perform the NOR memory Initialization sequence
00183   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00184   *                the configuration information for NOR module.
00185   * @param  Timing: pointer to NOR control timing structure
00186   * @param  ExtTiming: pointer to NOR extended mode timing structure
00187   * @retval HAL status
00188   */
00189 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
00190 {
00191   /* Check the NOR handle parameter */
00192   if(hnor == NULL)
00193   {
00194      return HAL_ERROR;
00195   }
00196
00197   if(hnor->State == HAL_NOR_STATE_RESET)
00198   {
00199     /* Allocate lock resource and initialize it */
00200     hnor->Lock = HAL_UNLOCKED;
00201
00202     /* Initialize the low level hardware (MSP) */
00203     HAL_NOR_MspInit(hnor);
00204   }
00205
00206   /* Initialize NOR control Interface */
00207   FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
00208
00209   /* Initialize NOR timing Interface */
00210   FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
00211
00212   /* Initialize NOR extended mode timing Interface */
00213   FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
00214
00215   /* Enable the NORSRAM device */
00216   __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
00217
00218   /* Initialize NOR Memory Data Width*/
00219   if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
00220   {
00221     uwNORMemoryDataWidth = NOR_MEMORY_8B;
00222   }
00223   else
00224   {
00225     uwNORMemoryDataWidth = NOR_MEMORY_16B;
00226   }
00227
00228   /* Check the NOR controller state */
00229   hnor->State = HAL_NOR_STATE_READY;
00230
00231   return HAL_OK;
00232 }
00233
00234 /**
00235   * @brief  Perform NOR memory De-Initialization sequence
00236   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00237   *                the configuration information for NOR module.
00238   * @retval HAL status
00239   */
00240 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
00241 {
00242   /* De-Initialize the low level hardware (MSP) */
00243   HAL_NOR_MspDeInit(hnor);
00244
00245   /* Configure the NOR registers with their reset values */
00246   FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
00247
00248   /* Update the NOR controller state */
00249   hnor->State = HAL_NOR_STATE_RESET;
00250
00251   /* Release Lock */
00252   __HAL_UNLOCK(hnor);
00253
00254   return HAL_OK;
00255 }
00256
00257 /**
00258   * @brief  NOR MSP Init
00259   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00260   *                the configuration information for NOR module.
00261   * @retval None
00262   */
00263 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
00264 {
00265   /* Prevent unused argument(s) compilation warning */
00266   UNUSED(hnor);
00267   /* NOTE : This function Should not be modified, when the callback is needed,
00268             the HAL_NOR_MspInit could be implemented in the user file
00269    */
00270 }
00271
00272 /**
00273   * @brief  NOR MSP DeInit
00274   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00275   *                the configuration information for NOR module.
00276   * @retval None
00277   */
00278 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
00279 {
00280   /* Prevent unused argument(s) compilation warning */
00281   UNUSED(hnor);
00282   /* NOTE : This function Should not be modified, when the callback is needed,
00283             the HAL_NOR_MspDeInit could be implemented in the user file
00284    */
00285 }
00286
00287 /**
00288   * @brief  NOR MSP Wait fro Ready/Busy signal
00289   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00290   *                the configuration information for NOR module.
00291   * @param  Timeout: Maximum timeout value
00292   * @retval None
00293   */
00294 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
00295 {
00296   /* Prevent unused argument(s) compilation warning */
00297   UNUSED(hnor);
00298   /* NOTE : This function Should not be modified, when the callback is needed,
00299             the HAL_NOR_MspWait could be implemented in the user file
00300    */
00301 }
00302
00303 /**
00304   * @}
00305   */
00306
00307 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
00308   * @brief    Input Output and memory control functions
00309   *
00310   @verbatim
00311   ==============================================================================
00312                 ##### NOR Input and Output functions #####
00313   ==============================================================================
00314   [..]
00315     This section provides functions allowing to use and control the NOR memory
00316
00317 @endverbatim
00318   * @{
00319   */
00320
00321 /**
00322   * @brief  Read NOR flash IDs
00323   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00324   *                the configuration information for NOR module.
00325   * @param  pNOR_ID : pointer to NOR ID structure
00326   * @retval HAL status
00327   */
00328 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
00329 {
00330   uint32_t deviceaddress = 0U;
00331
00332   /* Process Locked */
00333   __HAL_LOCK(hnor);
00334
00335   /* Check the NOR controller state */
00336   if(hnor->State == HAL_NOR_STATE_BUSY)
00337   {
00338      return HAL_BUSY;
00339   }
00340
00341   /* Select the NOR device address */
00342   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
00343   {
00344     deviceaddress = NOR_MEMORY_ADRESS1;
00345   }
00346   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
00347   {
00348     deviceaddress = NOR_MEMORY_ADRESS2;
00349   }
00350   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
00351   {
00352     deviceaddress = NOR_MEMORY_ADRESS3;
00353   }
00354   else /* FSMC_NORSRAM_BANK4 */
00355   {
00356     deviceaddress = NOR_MEMORY_ADRESS4;
00357   }
00358
00359   /* Update the NOR controller state */
00360   hnor->State = HAL_NOR_STATE_BUSY;
00361
00362   /* Send read ID command */
00363   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00364   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00365   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
00366
00367   /* Read the NOR IDs */
00368   pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
00369   pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
00370   pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
00371   pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
00372
00373   /* Check the NOR controller state */
00374   hnor->State = HAL_NOR_STATE_READY;
00375
00376   /* Process unlocked */
00377   __HAL_UNLOCK(hnor);
00378
00379   return HAL_OK;
00380 }
00381
00382 /**
00383   * @brief  Returns the NOR memory to Read mode.
00384   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00385   *                the configuration information for NOR module.
00386   * @retval HAL status
00387   */
00388 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
00389 {
00390   uint32_t deviceaddress = 0U;
00391
00392   /* Process Locked */
00393   __HAL_LOCK(hnor);
00394
00395   /* Check the NOR controller state */
00396   if(hnor->State == HAL_NOR_STATE_BUSY)
00397   {
00398      return HAL_BUSY;
00399   }
00400
00401   /* Select the NOR device address */
00402   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
00403   {
00404     deviceaddress = NOR_MEMORY_ADRESS1;
00405   }
00406   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
00407   {
00408     deviceaddress = NOR_MEMORY_ADRESS2;
00409   }
00410   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
00411   {
00412     deviceaddress = NOR_MEMORY_ADRESS3;
00413   }
00414   else /* FSMC_NORSRAM_BANK4 */
00415   {
00416     deviceaddress = NOR_MEMORY_ADRESS4;
00417   }
00418
00419   NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
00420
00421   /* Check the NOR controller state */
00422   hnor->State = HAL_NOR_STATE_READY;
00423
00424   /* Process unlocked */
00425   __HAL_UNLOCK(hnor);
00426
00427   return HAL_OK;
00428 }
00429
00430 /**
00431   * @brief  Read data from NOR memory
00432   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00433   *                the configuration information for NOR module.
00434   * @param  pAddress: pointer to Device address
00435   * @param  pData : pointer to read data
00436   * @retval HAL status
00437   */
00438 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00439 {
00440   uint32_t deviceaddress = 0U;
00441
00442   /* Process Locked */
00443   __HAL_LOCK(hnor);
00444
00445   /* Check the NOR controller state */
00446   if(hnor->State == HAL_NOR_STATE_BUSY)
00447   {
00448      return HAL_BUSY;
00449   }
00450
00451   /* Select the NOR device address */
00452   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
00453   {
00454     deviceaddress = NOR_MEMORY_ADRESS1;
00455   }
00456   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
00457   {
00458     deviceaddress = NOR_MEMORY_ADRESS2;
00459   }
00460   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
00461   {
00462     deviceaddress = NOR_MEMORY_ADRESS3;
00463   }
00464   else /* FSMC_NORSRAM_BANK4 */
00465   {
00466     deviceaddress = NOR_MEMORY_ADRESS4;
00467   }
00468
00469   /* Update the NOR controller state */
00470   hnor->State = HAL_NOR_STATE_BUSY;
00471
00472   /* Send read data command */
00473   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00474   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00475   NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
00476
00477   /* Read the data */
00478   *pData = *(__IO uint32_t *)(uint32_t)pAddress;
00479
00480   /* Check the NOR controller state */
00481   hnor->State = HAL_NOR_STATE_READY;
00482
00483   /* Process unlocked */
00484   __HAL_UNLOCK(hnor);
00485
00486   return HAL_OK;
00487 }
00488
00489 /**
00490   * @brief  Program data to NOR memory
00491   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00492   *                the configuration information for NOR module.
00493   * @param  pAddress: Device address
00494   * @param  pData : pointer to the data to write
00495   * @retval HAL status
00496   */
00497 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
00498 {
00499   uint32_t deviceaddress = 0U;
00500
00501   /* Process Locked */
00502   __HAL_LOCK(hnor);
00503
00504   /* Check the NOR controller state */
00505   if(hnor->State == HAL_NOR_STATE_BUSY)
00506   {
00507      return HAL_BUSY;
00508   }
00509
00510   /* Select the NOR device address */
00511   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
00512   {
00513     deviceaddress = NOR_MEMORY_ADRESS1;
00514   }
00515   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
00516   {
00517     deviceaddress = NOR_MEMORY_ADRESS2;
00518   }
00519   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
00520   {
00521     deviceaddress = NOR_MEMORY_ADRESS3;
00522   }
00523   else /* FSMC_NORSRAM_BANK4 */
00524   {
00525     deviceaddress = NOR_MEMORY_ADRESS4;
00526   }
00527
00528   /* Update the NOR controller state */
00529   hnor->State = HAL_NOR_STATE_BUSY;
00530
00531   /* Send program data command */
00532   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00533   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00534   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
00535
00536   /* Write the data */
00537   NOR_WRITE(pAddress, *pData);
00538
00539   /* Check the NOR controller state */
00540   hnor->State = HAL_NOR_STATE_READY;
00541
00542   /* Process unlocked */
00543   __HAL_UNLOCK(hnor);
00544
00545   return HAL_OK;
00546 }
00547
00548 /**
00549   * @brief  Reads a block of data from the FSMC NOR memory.
00550   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00551   *                the configuration information for NOR module.
00552   * @param  uwAddress: NOR memory internal address to read from.
00553   * @param  pData: pointer to the buffer that receives the data read from the
00554   *         NOR memory.
00555   * @param  uwBufferSize : number of Half word to read.
00556   * @retval HAL status
00557   */
00558 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00559 {
00560   uint32_t deviceaddress = 0U;
00561
00562   /* Process Locked */
00563   __HAL_LOCK(hnor);
00564
00565   /* Check the NOR controller state */
00566   if(hnor->State == HAL_NOR_STATE_BUSY)
00567   {
00568      return HAL_BUSY;
00569   }
00570
00571   /* Select the NOR device address */
00572   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
00573   {
00574     deviceaddress = NOR_MEMORY_ADRESS1;
00575   }
00576   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
00577   {
00578     deviceaddress = NOR_MEMORY_ADRESS2;
00579   }
00580   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
00581   {
00582     deviceaddress = NOR_MEMORY_ADRESS3;
00583   }
00584   else /* FSMC_NORSRAM_BANK4 */
00585   {
00586     deviceaddress = NOR_MEMORY_ADRESS4;
00587   }
00588
00589   /* Update the NOR controller state */
00590   hnor->State = HAL_NOR_STATE_BUSY;
00591
00592   /* Send read data command */
00593   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00594   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00595   NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
00596
00597   /* Read buffer */
00598   while( uwBufferSize > 0U)
00599   {
00600     *pData++ = *(__IO uint16_t *)uwAddress;
00601     uwAddress += 2U;
00602     uwBufferSize--;
00603   }
00604
00605   /* Check the NOR controller state */
00606   hnor->State = HAL_NOR_STATE_READY;
00607
00608   /* Process unlocked */
00609   __HAL_UNLOCK(hnor);
00610
00611   return HAL_OK;
00612 }
00613
00614 /**
00615   * @brief  Writes a half-word buffer to the FSMC NOR memory. This function
00616   *         must be used only with S29GL128P NOR memory.
00617   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00618   *                the configuration information for NOR module.
00619   * @param  uwAddress: NOR memory internal address from which the data
00620   * @note   Some NOR memory need Address aligned to xx bytes (can be aligned to
00621   *          64 bytes boundary for example).
00622   * @param  pData: pointer to source data buffer.
00623   * @param  uwBufferSize: number of Half words to write.
00624   * @note   The maximum buffer size allowed is NOR memory dependent
00625   *         (can be 64 Bytes max for example).
00626   * @retval HAL status
00627   */
00628 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
00629 {
00630   uint16_t * p_currentaddress = (uint16_t *)NULL;
00631   uint16_t * p_endaddress = (uint16_t *)NULL;
00632   uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
00633
00634   /* Process Locked */
00635   __HAL_LOCK(hnor);
00636
00637   /* Check the NOR controller state */
00638   if(hnor->State == HAL_NOR_STATE_BUSY)
00639   {
00640      return HAL_BUSY;
00641   }
00642
00643   /* Select the NOR device address */
00644   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
00645   {
00646     deviceaddress = NOR_MEMORY_ADRESS1;
00647   }
00648   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
00649   {
00650     deviceaddress = NOR_MEMORY_ADRESS2;
00651   }
00652   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
00653   {
00654     deviceaddress = NOR_MEMORY_ADRESS3;
00655   }
00656   else /* FSMC_NORSRAM_BANK4 */
00657   {
00658     deviceaddress = NOR_MEMORY_ADRESS4;
00659   }
00660
00661   /* Update the NOR controller state */
00662   hnor->State = HAL_NOR_STATE_BUSY;
00663
00664   /* Initialize variables */
00665   p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
00666   p_endaddress      = p_currentaddress + (uwBufferSize-1U);
00667   lastloadedaddress = (uint32_t)(uwAddress);
00668
00669   /* Issue unlock command sequence */
00670   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00671   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00672
00673   /* Write Buffer Load Command */
00674   NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
00675   NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1U));
00676
00677   /* Load Data into NOR Buffer */
00678   while(p_currentaddress <= p_endaddress)
00679   {
00680     /* Store last loaded address & data value (for polling) */
00681     lastloadedaddress = (uint32_t)p_currentaddress;
00682
00683     NOR_WRITE(p_currentaddress, *pData++);
00684
00685     p_currentaddress++;
00686   }
00687
00688   NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
00689
00690   /* Check the NOR controller state */
00691   hnor->State = HAL_NOR_STATE_READY;
00692
00693   /* Process unlocked */
00694   __HAL_UNLOCK(hnor);
00695
00696   return HAL_OK;
00697
00698 }
00699
00700 /**
00701   * @brief  Erase the specified block of the NOR memory
00702   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00703   *                the configuration information for NOR module.
00704   * @param  BlockAddress : Block to erase address
00705   * @param  Address: Device address
00706   * @retval HAL status
00707   */
00708 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
00709 {
00710   uint32_t deviceaddress = 0U;
00711
00712   /* Process Locked */
00713   __HAL_LOCK(hnor);
00714
00715   /* Check the NOR controller state */
00716   if(hnor->State == HAL_NOR_STATE_BUSY)
00717   {
00718      return HAL_BUSY;
00719   }
00720
00721   /* Select the NOR device address */
00722   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
00723   {
00724     deviceaddress = NOR_MEMORY_ADRESS1;
00725   }
00726   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
00727   {
00728     deviceaddress = NOR_MEMORY_ADRESS2;
00729   }
00730   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
00731   {
00732     deviceaddress = NOR_MEMORY_ADRESS3;
00733   }
00734   else /* FSMC_NORSRAM_BANK4 */
00735   {
00736     deviceaddress = NOR_MEMORY_ADRESS4;
00737   }
00738
00739   /* Update the NOR controller state */
00740   hnor->State = HAL_NOR_STATE_BUSY;
00741
00742   /* Send block erase command sequence */
00743   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00744   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00745   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00746   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00747   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00748   NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
00749
00750   /* Check the NOR memory status and update the controller state */
00751   hnor->State = HAL_NOR_STATE_READY;
00752
00753   /* Process unlocked */
00754   __HAL_UNLOCK(hnor);
00755
00756   return HAL_OK;
00757
00758 }
00759
00760 /**
00761   * @brief  Erase the entire NOR chip.
00762   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00763   *                the configuration information for NOR module.
00764   * @param  Address : Device address
00765   * @retval HAL status
00766   */
00767 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
00768 {
00769   uint32_t deviceaddress = 0U;
00770
00771   /* Process Locked */
00772   __HAL_LOCK(hnor);
00773
00774   /* Check the NOR controller state */
00775   if(hnor->State == HAL_NOR_STATE_BUSY)
00776   {
00777      return HAL_BUSY;
00778   }
00779
00780   /* Select the NOR device address */
00781   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
00782   {
00783     deviceaddress = NOR_MEMORY_ADRESS1;
00784   }
00785   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
00786   {
00787     deviceaddress = NOR_MEMORY_ADRESS2;
00788   }
00789   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
00790   {
00791     deviceaddress = NOR_MEMORY_ADRESS3;
00792   }
00793   else /* FSMC_NORSRAM_BANK4 */
00794   {
00795     deviceaddress = NOR_MEMORY_ADRESS4;
00796   }
00797
00798   /* Update the NOR controller state */
00799   hnor->State = HAL_NOR_STATE_BUSY;
00800
00801   /* Send NOR chip erase command sequence */
00802   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
00803   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
00804   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
00805   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
00806   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
00807   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
00808
00809   /* Check the NOR memory status and update the controller state */
00810   hnor->State = HAL_NOR_STATE_READY;
00811
00812   /* Process unlocked */
00813   __HAL_UNLOCK(hnor);
00814
00815   return HAL_OK;
00816 }
00817
00818 /**
00819   * @brief  Read NOR flash CFI IDs
00820   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00821   *                the configuration information for NOR module.
00822   * @param  pNOR_CFI : pointer to NOR CFI IDs structure
00823   * @retval HAL status
00824   */
00825 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
00826 {
00827   uint32_t deviceaddress = 0U;
00828
00829   /* Process Locked */
00830   __HAL_LOCK(hnor);
00831
00832   /* Check the NOR controller state */
00833   if(hnor->State == HAL_NOR_STATE_BUSY)
00834   {
00835      return HAL_BUSY;
00836   }
00837
00838   /* Select the NOR device address */
00839   if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
00840   {
00841     deviceaddress = NOR_MEMORY_ADRESS1;
00842   }
00843   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
00844   {
00845     deviceaddress = NOR_MEMORY_ADRESS2;
00846   }
00847   else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
00848   {
00849     deviceaddress = NOR_MEMORY_ADRESS3;
00850   }
00851   else /* FSMC_NORSRAM_BANK4 */
00852   {
00853     deviceaddress = NOR_MEMORY_ADRESS4;
00854   }
00855
00856   /* Update the NOR controller state */
00857   hnor->State = HAL_NOR_STATE_BUSY;
00858
00859   /* Send read CFI query command */
00860   NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
00861
00862   /* read the NOR CFI information */
00863   pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
00864   pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
00865   pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
00866   pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
00867
00868   /* Check the NOR controller state */
00869   hnor->State = HAL_NOR_STATE_READY;
00870
00871   /* Process unlocked */
00872   __HAL_UNLOCK(hnor);
00873
00874   return HAL_OK;
00875 }
00876
00877 /**
00878   * @}
00879   */
00880
00881 /** @defgroup NOR_Exported_Functions_Group3 Control functions
00882  *  @brief   management functions
00883  *
00884 @verbatim
00885   ==============================================================================
00886                         ##### NOR Control functions #####
00887   ==============================================================================
00888   [..]
00889     This subsection provides a set of functions allowing to control dynamically
00890     the NOR interface.
00891
00892 @endverbatim
00893   * @{
00894   */
00895
00896 /**
00897   * @brief  Enables dynamically NOR write operation.
00898   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00899   *                the configuration information for NOR module.
00900   * @retval HAL status
00901   */
00902 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
00903 {
00904   /* Process Locked */
00905   __HAL_LOCK(hnor);
00906
00907   /* Enable write operation */
00908   FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
00909
00910   /* Update the NOR controller state */
00911   hnor->State = HAL_NOR_STATE_READY;
00912
00913   /* Process unlocked */
00914   __HAL_UNLOCK(hnor);
00915
00916   return HAL_OK;
00917 }
00918
00919 /**
00920   * @brief  Disables dynamically NOR write operation.
00921   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00922   *                the configuration information for NOR module.
00923   * @retval HAL status
00924   */
00925 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
00926 {
00927   /* Process Locked */
00928   __HAL_LOCK(hnor);
00929
00930   /* Update the SRAM controller state */
00931   hnor->State = HAL_NOR_STATE_BUSY;
00932
00933   /* Disable write operation */
00934   FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
00935
00936   /* Update the NOR controller state */
00937   hnor->State = HAL_NOR_STATE_PROTECTED;
00938
00939   /* Process unlocked */
00940   __HAL_UNLOCK(hnor);
00941
00942   return HAL_OK;
00943 }
00944
00945 /**
00946   * @}
00947   */
00948
00949 /** @defgroup NOR_Exported_Functions_Group4 State functions
00950  *  @brief   Peripheral State functions
00951  *
00952 @verbatim
00953   ==============================================================================
00954                       ##### NOR State functions #####
00955   ==============================================================================
00956   [..]
00957     This subsection permits to get in run-time the status of the NOR controller
00958     and the data flow.
00959
00960 @endverbatim
00961   * @{
00962   */
00963
00964 /**
00965   * @brief  return the NOR controller state
00966   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00967   *                the configuration information for NOR module.
00968   * @retval NOR controller state
00969   */
00970 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
00971 {
00972   return hnor->State;
00973 }
00974
00975 /**
00976   * @brief  Returns the NOR operation status.
00977   * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
00978   *                the configuration information for NOR module.
00979   * @param  Address: Device address
00980   * @param  Timeout: NOR progamming Timeout
00981   * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
00982   *         or HAL_NOR_STATUS_TIMEOUT
00983   */
00984 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
00985 {
00986   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
00987   uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
00988   uint32_t tickstart = 0U;
00989
00990   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
00991   HAL_NOR_MspWait(hnor, Timeout);
00992
00993   /* Get tick */
00994   tickstart = HAL_GetTick();
00995   while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
00996   {
00997     /* Check for the Timeout */
00998     if(Timeout != HAL_MAX_DELAY)
00999     {
01000       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
01001       {
01002         status = HAL_NOR_STATUS_TIMEOUT;
01003       }
01004     }
01005
01006     /* Read NOR status register (DQ6 and DQ5) */
01007     tmp_sr1 = *(__IO uint16_t *)Address;
01008     tmp_sr2 = *(__IO uint16_t *)Address;
01009
01010     /* If DQ6 did not toggle between the two reads then return NOR_Success */
01011     if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
01012     {
01013       return HAL_NOR_STATUS_SUCCESS;
01014     }
01015
01016     if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
01017     {
01018       status = HAL_NOR_STATUS_ONGOING;
01019     }
01020
01021     tmp_sr1 = *(__IO uint16_t *)Address;
01022     tmp_sr2 = *(__IO uint16_t *)Address;
01023
01024     /* If DQ6 did not toggle between the two reads then return NOR_Success */
01025     if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
01026     {
01027       return HAL_NOR_STATUS_SUCCESS;
01028     }
01029     else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
01030     {
01031       return HAL_NOR_STATUS_ERROR;
01032     }
01033   }
01034
01035   /* Return the operation status */
01036   return status;
01037 }
01038
01039 /**
01040   * @}
01041   */
01042
01043 /**
01044   * @}
01045   */
01046 /**
01047   * @}
01048   */
01049 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
01050 #endif /* HAL_NOR_MODULE_ENABLED */
01051
01052 /**
01053   * @}
01054   */
01055
01056 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_nor.h Source File

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stm32f1xx_hal_nor.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_nor.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of NOR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_NOR_H
00040 #define __STM32F1xx_HAL_NOR_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_ll_fsmc.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
00054 /** @addtogroup NOR
00055   * @{
00056   */
00057
00058 /** @addtogroup NOR_Private_Constants
00059   * @{
00060   */
00061
00062 /* NOR device IDs addresses */
00063 #define MC_ADDRESS               ((uint16_t)0x0000)
00064 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
00065 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
00066 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
00067
00068 /* NOR CFI IDs addresses */
00069 #define CFI1_ADDRESS             ((uint16_t)0x10)
00070 #define CFI2_ADDRESS             ((uint16_t)0x11)
00071 #define CFI3_ADDRESS             ((uint16_t)0x12)
00072 #define CFI4_ADDRESS             ((uint16_t)0x13)
00073
00074 /* NOR operation wait timeout */
00075 #define NOR_TMEOUT               ((uint16_t)0xFFFF)
00076
00077 /* NOR memory data width */
00078 #define NOR_MEMORY_8B            ((uint8_t)0x0)
00079 #define NOR_MEMORY_16B           ((uint8_t)0x1)
00080
00081 /* NOR memory device read/write start address */
00082 #define NOR_MEMORY_ADRESS1       FSMC_BANK1_1
00083 #define NOR_MEMORY_ADRESS2       FSMC_BANK1_2
00084 #define NOR_MEMORY_ADRESS3       FSMC_BANK1_3
00085 #define NOR_MEMORY_ADRESS4       FSMC_BANK1_4
00086
00087 /**
00088   * @}
00089   */
00090
00091 /** @addtogroup NOR_Private_Macros
00092   * @{
00093   */
00094
00095 /**
00096   * @brief  NOR memory address shifting.
00097   * @param  __NOR_ADDRESS: NOR base address
00098   * @param  __NOR_MEMORY_WIDTH_: NOR memory width
00099   * @param  __ADDRESS__: NOR memory address
00100   * @retval NOR shifted address value
00101   */
00102 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
00103             ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
00104               ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
00105               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
00106
00107 /**
00108   * @brief  NOR memory write data to specified address.
00109   * @param  __ADDRESS__: NOR memory address
00110   * @param  __DATA__: Data to write
00111   * @retval None
00112   */
00113 #define NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
00114
00115 /**
00116   * @}
00117   */
00118
00119 /* Exported typedef ----------------------------------------------------------*/
00120 /** @defgroup NOR_Exported_Types NOR Exported Types
00121   * @{
00122   */
00123
00124 /**
00125   * @brief  HAL SRAM State structures definition
00126   */
00127 typedef enum
00128 {
00129   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
00130   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
00131   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
00132   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
00133   HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected  */
00134 }HAL_NOR_StateTypeDef;
00135
00136 /**
00137   * @brief  FSMC NOR Status typedef
00138   */
00139 typedef enum
00140 {
00141   HAL_NOR_STATUS_SUCCESS = 0U,
00142   HAL_NOR_STATUS_ONGOING,
00143   HAL_NOR_STATUS_ERROR,
00144   HAL_NOR_STATUS_TIMEOUT
00145 }HAL_NOR_StatusTypeDef;
00146
00147 /**
00148   * @brief  FSMC NOR ID typedef
00149   */
00150 typedef struct
00151 {
00152   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
00153
00154   uint16_t Device_Code1;
00155
00156   uint16_t Device_Code2;
00157
00158   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
00159                                     These codes can be accessed by performing read operations with specific
00160                                     control signals and addresses set.They can also be accessed by issuing
00161                                     an Auto Select command                                                   */
00162 }NOR_IDTypeDef;
00163
00164 /**
00165   * @brief  FSMC NOR CFI typedef
00166   */
00167 typedef struct
00168 {
00169   /*!< Defines the information stored in the memory's Common flash interface
00170        which contains a description of various electrical and timing parameters,
00171        density information and functions supported by the memory                   */
00172
00173   uint16_t CFI_1;
00174
00175   uint16_t CFI_2;
00176
00177   uint16_t CFI_3;
00178
00179   uint16_t CFI_4;
00180 }NOR_CFITypeDef;
00181
00182 /**
00183   * @brief  NOR handle Structure definition
00184   */
00185 typedef struct
00186 {
00187   FSMC_NORSRAM_TypeDef          *Instance;    /*!< Register base address                        */
00188
00189   FSMC_NORSRAM_EXTENDED_TypeDef *Extended;    /*!< Extended mode register base address          */
00190
00191   FSMC_NORSRAM_InitTypeDef      Init;         /*!< NOR device control configuration parameters  */
00192
00193   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
00194
00195   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
00196
00197 }NOR_HandleTypeDef;
00198
00199 /**
00200   * @}
00201   */
00202
00203 /* Exported constants --------------------------------------------------------*/
00204 /* Exported macro ------------------------------------------------------------*/
00205
00206 /** @defgroup NOR_Exported_macro NOR Exported Macros
00207   * @{
00208   */
00209
00210 /** @brief Reset NOR handle state
00211   * @param  __HANDLE__: NOR handle
00212   * @retval None
00213   */
00214 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
00215
00216 /**
00217   * @}
00218   */
00219
00220 /* Exported functions --------------------------------------------------------*/
00221 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
00222  *  @{
00223  */
00224
00225 /** @addtogroup NOR_Exported_Functions_Group1
00226  *  @{
00227  */
00228
00229 /* Initialization/de-initialization functions  **********************************/
00230 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
00231 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
00232 void              HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
00233 void              HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
00234 void              HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @addtogroup NOR_Exported_Functions_Group2
00241  *  @{
00242  */
00243
00244 /* I/O operation functions  ***************************************************/
00245 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
00246 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
00247 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00248 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00249
00250 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00251 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00252
00253 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
00254 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
00255 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
00256
00257 /**
00258   * @}
00259   */
00260
00261 /** @addtogroup NOR_Exported_Functions_Group3
00262  *  @{
00263  */
00264
00265 /* NOR Control functions  *****************************************************/
00266 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
00267 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
00268
00269 /**
00270   * @}
00271   */
00272
00273 /** @addtogroup NOR_Exported_Functions_Group4
00274  *  @{
00275  */
00276
00277 /* NOR State functions ********************************************************/
00278 HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
00279 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289
00290 /**
00291   * @}
00292   */
00293
00294 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
00295
00296 /**
00297   * @}
00298   */
00299
00300 #ifdef __cplusplus
00301 }
00302 #endif
00303
00304 #endif /* __STM32F1xx_HAL_NOR_H */
00305
00306 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pccard.c Source File

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stm32f1xx_hal_pccard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_pccard.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   PCCARD HAL module driver.
00008   *          This file provides a generic firmware to drive PCCARD memories mounted
00009   *          as external device.
00010   *
00011   @verbatim
00012  ===============================================================================
00013                         ##### How to use this driver #####
00014  ===============================================================================
00015    [..]
00016      This driver is a generic layered driver which contains a set of APIs used to
00017      control PCCARD/compact flash memories. It uses the FSMC/FSMC layer functions
00018      to interface with PCCARD devices. This driver is used for:
00019
00020     (+) PCCARD/compact flash memory configuration sequence using the function
00021         HAL_PCCARD_Init() with control and timing parameters for both common and
00022         attribute spaces.
00023
00024     (+) Read PCCARD/compact flash memory maker and device IDs using the function
00025         HAL_PCCARD_Read_ID(). The read information is stored in the CompactFlash_ID
00026         structure declared by the function caller.
00027
00028     (+) Access PCCARD/compact flash memory by read/write operations using the functions
00029         HAL_PCCARD_Read_Sector()/HAL_PCCARD_Write_Sector(), to read/write sector.
00030
00031     (+) Perform PCCARD/compact flash Reset chip operation using the function HAL_PCCARD_Reset().
00032
00033     (+) Perform PCCARD/compact flash erase sector operation using the function
00034         HAL_PCCARD_Erase_Sector().
00035
00036     (+) Read the PCCARD/compact flash status operation using the function HAL_PCCARD_ReadStatus().
00037
00038     (+) You can monitor the PCCARD/compact flash  device HAL state by calling the function
00039         HAL_PCCARD_GetState()
00040
00041    [..]
00042      (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash
00043          operations. If a PCCARD/compact flash device contains different operations
00044          and/or implementations, it should be implemented separately.
00045
00046   @endverbatim
00047   ******************************************************************************
00048   * @attention
00049   *
00050   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00051   *
00052   * Redistribution and use in source and binary forms, with or without modification,
00053   * are permitted provided that the following conditions are met:
00054   *   1. Redistributions of source code must retain the above copyright notice,
00055   *      this list of conditions and the following disclaimer.
00056   *   2. Redistributions in binary form must reproduce the above copyright notice,
00057   *      this list of conditions and the following disclaimer in the documentation
00058   *      and/or other materials provided with the distribution.
00059   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00060   *      may be used to endorse or promote products derived from this software
00061   *      without specific prior written permission.
00062   *
00063   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00064   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00065   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00066   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00067   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00068   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00069   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00070   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00071   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00072   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00073   *
00074   ******************************************************************************
00075   */
00076
00077 /* Includes ------------------------------------------------------------------*/
00078 #include "stm32f1xx_hal.h"
00079
00080 /** @addtogroup STM32F1xx_HAL_Driver
00081   * @{
00082   */
00083
00084 #ifdef HAL_PCCARD_MODULE_ENABLED
00085 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
00086
00087 /** @defgroup PCCARD PCCARD
00088   * @brief PCCARD HAL module driver
00089   * @{
00090   */
00091
00092 /* Private typedef -----------------------------------------------------------*/
00093 /* Private define ------------------------------------------------------------*/
00094 /** @defgroup PCCARD_Private_Constants PCCARD Private Constants
00095   * @{
00096   */
00097
00098 #define PCCARD_TIMEOUT_READ_ID      0x0000FFFFU
00099 #define PCCARD_TIMEOUT_SECTOR       0x0000FFFFU
00100 #define PCCARD_TIMEOUT_STATUS       0x01000000U
00101
00102 #define PCCARD_STATUS_OK            (uint8_t)0x58
00103 #define PCCARD_STATUS_WRITE_OK      (uint8_t)0x50
00104 /**
00105   * @}
00106   */
00107
00108 /* Private macro -------------------------------------------------------------*/
00109 /* Private variables ---------------------------------------------------------*/
00110 /* Private function prototypes -----------------------------------------------*/
00111 /* Exported functions ---------------------------------------------------------*/
00112
00113 /** @defgroup PCCARD_Exported_Functions PCCARD Exported Functions
00114   * @{
00115   */
00116
00117 /** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00118   * @brief    Initialization and Configuration functions
00119   *
00120   @verbatim
00121   ==============================================================================
00122           ##### PCCARD Initialization and de-initialization functions #####
00123   ==============================================================================
00124   [..]
00125     This section provides functions allowing to initialize/de-initialize
00126     the PCCARD memory
00127
00128 @endverbatim
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  Perform the PCCARD memory Initialization sequence
00134   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00135   *                the configuration information for PCCARD module.
00136   * @param  ComSpaceTiming: Common space timing structure
00137   * @param  AttSpaceTiming: Attribute space timing structure
00138   * @param  IOSpaceTiming: IO space timing structure
00139   * @retval HAL status
00140   */
00141 HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
00142 {
00143   /* Check the PCCARD controller state */
00144   if(hpccard == NULL)
00145   {
00146      return HAL_ERROR;
00147   }
00148
00149   if(hpccard->State == HAL_PCCARD_STATE_RESET)
00150   {
00151     /* Allocate lock resource and initialize it */
00152     hpccard->Lock = HAL_UNLOCKED;
00153
00154     /* Initialize the low level hardware (MSP) */
00155     HAL_PCCARD_MspInit(hpccard);
00156   }
00157
00158   /* Initialize the PCCARD state */
00159   hpccard->State = HAL_PCCARD_STATE_BUSY;
00160
00161   /* Initialize PCCARD control Interface */
00162   FSMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init));
00163
00164   /* Init PCCARD common space timing Interface */
00165   FSMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming);
00166
00167   /* Init PCCARD attribute space timing Interface */
00168   FSMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming);
00169
00170   /* Init PCCARD IO space timing Interface */
00171   FSMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming);
00172
00173   /* Enable the PCCARD device */
00174   __FSMC_PCCARD_ENABLE(hpccard->Instance);
00175
00176   /* Update the PCCARD state */
00177   hpccard->State = HAL_PCCARD_STATE_READY;
00178
00179   return HAL_OK;
00180
00181 }
00182
00183 /**
00184   * @brief  Perform the PCCARD memory De-initialization sequence
00185   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00186   *                the configuration information for PCCARD module.
00187   * @retval HAL status
00188   */
00189 HAL_StatusTypeDef  HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
00190 {
00191   /* De-Initialize the low level hardware (MSP) */
00192   HAL_PCCARD_MspDeInit(hpccard);
00193
00194   /* Configure the PCCARD registers with their reset values */
00195   FSMC_PCCARD_DeInit(hpccard->Instance);
00196
00197   /* Update the PCCARD controller state */
00198   hpccard->State = HAL_PCCARD_STATE_RESET;
00199
00200   /* Release Lock */
00201   __HAL_UNLOCK(hpccard);
00202
00203   return HAL_OK;
00204 }
00205
00206 /**
00207   * @brief  PCCARD MSP Init
00208   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00209   *                the configuration information for PCCARD module.
00210   * @retval None
00211   */
00212 __weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
00213 {
00214   /* Prevent unused argument(s) compilation warning */
00215   UNUSED(hpccard);
00216   /* NOTE : This function Should not be modified, when the callback is needed,
00217             the HAL_PCCARD_MspInit could be implemented in the user file
00218    */
00219 }
00220
00221 /**
00222   * @brief  PCCARD MSP DeInit
00223   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00224   *                the configuration information for PCCARD module.
00225   * @retval None
00226   */
00227 __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
00228 {
00229   /* Prevent unused argument(s) compilation warning */
00230   UNUSED(hpccard);
00231   /* NOTE : This function Should not be modified, when the callback is needed,
00232             the HAL_PCCARD_MspDeInit could be implemented in the user file
00233    */
00234 }
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
00241   * @brief    Input Output and memory control functions
00242   *
00243   @verbatim
00244   ==============================================================================
00245                 ##### PCCARD Input Output and memory functions #####
00246   ==============================================================================
00247   [..]
00248     This section provides functions allowing to use and control the PCCARD memory
00249
00250 @endverbatim
00251   * @{
00252   */
00253
00254 /**
00255   * @brief  Read Compact Flash's ID.
00256   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00257   *                the configuration information for PCCARD module.
00258   * @param  CompactFlash_ID: Compact flash ID structure.
00259   * @param  pStatus: pointer to compact flash status
00260   * @retval HAL status
00261   *
00262   */
00263 HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
00264 {
00265   uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
00266   uint8_t status = 0U;
00267
00268   /* Process Locked */
00269   __HAL_LOCK(hpccard);
00270
00271   /* Check the PCCARD controller state */
00272   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00273   {
00274      return HAL_BUSY;
00275   }
00276
00277   /* Update the PCCARD controller state */
00278   hpccard->State = HAL_PCCARD_STATE_BUSY;
00279
00280   /* Initialize the CF status */
00281   *pStatus = PCCARD_READY;
00282
00283   /* Send the Identify Command */
00284   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)  = 0xECECU;
00285
00286   /* Read CF IDs and timeout treatment */
00287   do
00288   {
00289      /* Read the CF status */
00290      status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00291
00292      timeout--;
00293   }while((status != PCCARD_STATUS_OK) && timeout);
00294
00295   if(timeout == 0U)
00296   {
00297     *pStatus = PCCARD_TIMEOUT_ERROR;
00298   }
00299   else
00300   {
00301      /* Read CF ID bytes */
00302     for(index = 0U; index < 16U; index++)
00303     {
00304       CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
00305     }
00306   }
00307
00308   /* Update the PCCARD controller state */
00309   hpccard->State = HAL_PCCARD_STATE_READY;
00310
00311   /* Process unlocked */
00312   __HAL_UNLOCK(hpccard);
00313
00314   return HAL_OK;
00315 }
00316
00317 /**
00318   * @brief  Read sector from PCCARD memory
00319   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00320   *                the configuration information for PCCARD module.
00321   * @param  pBuffer: pointer to destination read buffer
00322   * @param  SectorAddress: Sector address to read
00323   * @param  pStatus: pointer to CF status
00324   * @retval HAL status
00325   */
00326 HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
00327 {
00328   uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
00329   uint8_t status = 0U;
00330
00331   /* Process Locked */
00332   __HAL_LOCK(hpccard);
00333
00334   /* Check the PCCARD controller state */
00335   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00336   {
00337      return HAL_BUSY;
00338   }
00339
00340   /* Update the PCCARD controller state */
00341   hpccard->State = HAL_PCCARD_STATE_BUSY;
00342
00343   /* Initialize CF status */
00344   *pStatus = PCCARD_READY;
00345
00346   /* Set the parameters to write a sector */
00347   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
00348   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
00349   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = (uint16_t)0xE4A0;
00350
00351   do
00352   {
00353     /* wait till the Status = 0x80 */
00354     status =  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00355     timeout--;
00356   }while((status == 0x80U) && timeout);
00357
00358   if(timeout == 0U)
00359   {
00360     *pStatus = PCCARD_TIMEOUT_ERROR;
00361   }
00362
00363   timeout = 0xFFFFU;
00364
00365   do
00366   {
00367     /* wait till the Status = PCCARD_STATUS_OK */
00368     status =  *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00369     timeout--;
00370   }while((status != PCCARD_STATUS_OK) && timeout);
00371
00372   if(timeout == 0U)
00373   {
00374     *pStatus = PCCARD_TIMEOUT_ERROR;
00375   }
00376
00377   /* Read bytes */
00378   for(; index < PCCARD_SECTOR_SIZE; index++)
00379   {
00380     *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR);
00381   }
00382
00383   /* Update the PCCARD controller state */
00384   hpccard->State = HAL_PCCARD_STATE_READY;
00385
00386   /* Process unlocked */
00387   __HAL_UNLOCK(hpccard);
00388
00389   return HAL_OK;
00390 }
00391
00392
00393 /**
00394   * @brief  Write sector to PCCARD memory
00395   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00396   *                the configuration information for PCCARD module.
00397   * @param  pBuffer: pointer to source write buffer
00398   * @param  SectorAddress: Sector address to write
00399   * @param  pStatus: pointer to CF status
00400   * @retval HAL status
00401   */
00402 HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,  uint8_t *pStatus)
00403 {
00404   uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
00405   uint8_t status = 0U;
00406
00407   /* Process Locked */
00408   __HAL_LOCK(hpccard);
00409
00410   /* Check the PCCARD controller state */
00411   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00412   {
00413      return HAL_BUSY;
00414   }
00415
00416   /* Update the PCCARD controller state */
00417   hpccard->State = HAL_PCCARD_STATE_BUSY;
00418
00419   /* Initialize CF status */
00420   *pStatus = PCCARD_READY;
00421
00422   /* Set the parameters to write a sector */
00423   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
00424   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
00425   *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = (uint16_t)0x30A0;
00426
00427   do
00428   {
00429     /* Wait till the Status = PCCARD_STATUS_OK */
00430     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00431     timeout--;
00432   }while((status != PCCARD_STATUS_OK) && timeout);
00433
00434   if(timeout == 0U)
00435   {
00436     *pStatus = PCCARD_TIMEOUT_ERROR;
00437   }
00438
00439   /* Write bytes */
00440   for(; index < PCCARD_SECTOR_SIZE; index++)
00441   {
00442     *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
00443   }
00444
00445   do
00446   {
00447     /* Wait till the Status = PCCARD_STATUS_WRITE_OK */
00448     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00449     timeout--;
00450   }while((status != PCCARD_STATUS_WRITE_OK) && timeout);
00451
00452   if(timeout == 0U)
00453   {
00454     *pStatus = PCCARD_TIMEOUT_ERROR;
00455   }
00456
00457   /* Update the PCCARD controller state */
00458   hpccard->State = HAL_PCCARD_STATE_READY;
00459
00460   /* Process unlocked */
00461   __HAL_UNLOCK(hpccard);
00462
00463   return HAL_OK;
00464 }
00465
00466
00467 /**
00468   * @brief  Erase sector from PCCARD memory
00469   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00470   *                the configuration information for PCCARD module.
00471   * @param  SectorAddress: Sector address to erase
00472   * @param  pStatus: pointer to CF status
00473   * @retval HAL status
00474   */
00475 HAL_StatusTypeDef  HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
00476 {
00477   uint32_t timeout = 0x400U;
00478   uint8_t status = 0;
00479
00480   /* Process Locked */
00481   __HAL_LOCK(hpccard);
00482
00483   /* Check the PCCARD controller state */
00484   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00485   {
00486      return HAL_BUSY;
00487   }
00488
00489   /* Update the PCCARD controller state */
00490   hpccard->State = HAL_PCCARD_STATE_BUSY;
00491
00492   /* Initialize CF status */
00493   *pStatus = PCCARD_READY;
00494
00495   /* Set the parameters to write a sector */
00496   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW)  = 0x00;
00497   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00;
00498   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_NUMBER) = SectorAddress;
00499   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT)  = 0x01;
00500   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD)     = 0xA0;
00501   *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD)    = ATA_ERASE_SECTOR_CMD;
00502
00503   /* wait till the CF is ready */
00504   status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00505
00506   while((status != PCCARD_STATUS_WRITE_OK) && timeout)
00507   {
00508     status =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00509     timeout--;
00510   }
00511
00512   if(timeout == 0U)
00513   {
00514     *pStatus = PCCARD_TIMEOUT_ERROR;
00515   }
00516
00517   /* Check the PCCARD controller state */
00518   hpccard->State = HAL_PCCARD_STATE_READY;
00519
00520   /* Process unlocked */
00521   __HAL_UNLOCK(hpccard);
00522
00523   return HAL_OK;
00524 }
00525
00526 /**
00527   * @brief  Reset the PCCARD memory
00528   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00529   *                the configuration information for PCCARD module.
00530   * @retval HAL status
00531   */
00532 HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
00533 {
00534   /* Process Locked */
00535   __HAL_LOCK(hpccard);
00536
00537   /* Check the PCCARD controller state */
00538   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00539   {
00540      return HAL_BUSY;
00541   }
00542
00543   /* Provide an SW reset and Read and verify the:
00544    - CF Configuration Option Register at address 0x98000200 --> 0x80
00545    - Card Configuration and Status Register at address 0x98000202 --> 0x00
00546    - Pin Replacement Register  at address 0x98000204 --> 0x0C
00547    - Socket and Copy Register at address 0x98000206 --> 0x00
00548   */
00549
00550   /* Check the PCCARD controller state */
00551   hpccard->State = HAL_PCCARD_STATE_BUSY;
00552
00553   *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01;
00554
00555   /* Check the PCCARD controller state */
00556   hpccard->State = HAL_PCCARD_STATE_READY;
00557
00558   /* Process unlocked */
00559   __HAL_UNLOCK(hpccard);
00560
00561   return HAL_OK;
00562 }
00563
00564 /**
00565   * @brief  This function handles PCCARD device interrupt request.
00566   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00567   *                the configuration information for PCCARD module.
00568   * @retval HAL status
00569 */
00570 void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
00571 {
00572   /* Check PCCARD interrupt Rising edge flag */
00573   if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE))
00574   {
00575     /* PCCARD interrupt callback*/
00576     HAL_PCCARD_ITCallback(hpccard);
00577
00578     /* Clear PCCARD interrupt Rising edge pending bit */
00579     __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_RISING_EDGE);
00580   }
00581
00582   /* Check PCCARD interrupt Level flag */
00583   if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL))
00584   {
00585     /* PCCARD interrupt callback*/
00586     HAL_PCCARD_ITCallback(hpccard);
00587
00588     /* Clear PCCARD interrupt Level pending bit */
00589     __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_LEVEL);
00590   }
00591
00592   /* Check PCCARD interrupt Falling edge flag */
00593   if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE))
00594   {
00595     /* PCCARD interrupt callback*/
00596     HAL_PCCARD_ITCallback(hpccard);
00597
00598     /* Clear PCCARD interrupt Falling edge pending bit */
00599     __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FALLING_EDGE);
00600   }
00601
00602   /* Check PCCARD interrupt FIFO empty flag */
00603   if(__FSMC_PCCARD_GET_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT))
00604   {
00605     /* PCCARD interrupt callback*/
00606     HAL_PCCARD_ITCallback(hpccard);
00607
00608     /* Clear PCCARD interrupt FIFO empty pending bit */
00609     __FSMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FSMC_FLAG_FEMPT);
00610   }
00611
00612 }
00613
00614 /**
00615   * @brief  PCCARD interrupt feature callback
00616   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00617   *                the configuration information for PCCARD module.
00618   * @retval None
00619   */
00620 __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
00621 {
00622   /* Prevent unused argument(s) compilation warning */
00623   UNUSED(hpccard);
00624   /* NOTE : This function Should not be modified, when the callback is needed,
00625             the HAL_PCCARD_ITCallback could be implemented in the user file
00626    */
00627 }
00628
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
00634  *  @brief   Peripheral State functions
00635  *
00636 @verbatim
00637   ==============================================================================
00638                    ##### PCCARD Peripheral State functions #####
00639   ==============================================================================
00640   [..]
00641     This subsection permits to get in run-time the status of the PCCARD controller
00642     and the data flow.
00643
00644 @endverbatim
00645   * @{
00646   */
00647
00648 /**
00649   * @brief  return the PCCARD controller state
00650   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00651   *                the configuration information for PCCARD module.
00652   * @retval HAL state
00653   */
00654 HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
00655 {
00656   return hpccard->State;
00657 }
00658
00659 /**
00660   * @brief  Get the compact flash memory status
00661   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00662   *                the configuration information for PCCARD module.
00663   * @retval New status of the CF operation. This parameter can be:
00664   *          - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
00665   *            a Timeout error
00666   *          - CompactFlash_READY: when memory is ready for the next operation
00667   *
00668   */
00669 HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
00670 {
00671   uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_cf = 0;
00672
00673   /* Check the PCCARD controller state */
00674   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00675   {
00676      return HAL_PCCARD_STATUS_ONGOING;
00677   }
00678
00679   status_cf =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00680
00681   while((status_cf == PCCARD_BUSY) && timeout)
00682   {
00683     status_cf =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00684     timeout--;
00685   }
00686
00687   if(timeout == 0U)
00688   {
00689     status_cf =  PCCARD_TIMEOUT_ERROR;
00690   }
00691
00692   /* Return the operation status */
00693   return (HAL_PCCARD_StatusTypeDef) status_cf;
00694 }
00695
00696 /**
00697   * @brief  Reads the Compact Flash memory status using the Read status command
00698   * @param  hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
00699   *                the configuration information for PCCARD module.
00700   * @retval The status of the Compact Flash memory. This parameter can be:
00701   *          - CompactFlash_BUSY: when memory is busy
00702   *          - CompactFlash_READY: when memory is ready for the next operation
00703   *          - CompactFlash_ERROR: when the previous operation gererates error
00704   */
00705 HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
00706 {
00707   uint8_t data = 0U, status_cf = PCCARD_BUSY;
00708
00709   /* Check the PCCARD controller state */
00710   if(hpccard->State == HAL_PCCARD_STATE_BUSY)
00711   {
00712      return HAL_PCCARD_STATUS_ONGOING;
00713   }
00714
00715   /* Read status operation */
00716   data =  *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
00717
00718   if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR)
00719   {
00720     status_cf = PCCARD_TIMEOUT_ERROR;
00721   }
00722   else if((data & PCCARD_READY) == PCCARD_READY)
00723   {
00724     status_cf = PCCARD_READY;
00725   }
00726
00727   return (HAL_PCCARD_StatusTypeDef) status_cf;
00728 }
00729
00730 /**
00731   * @}
00732   */
00733
00734 /**
00735   * @}
00736   */
00737 /**
00738   * @}
00739   */
00740
00741 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
00742 #endif /* HAL_PCCARD_MODULE_ENABLED */
00743
00744 /**
00745   * @}
00746   */
00747
00748 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pccard.h Source File

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stm32f1xx_hal_pccard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_pccard.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of PCCARD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_PCCARD_H
00040 #define __STM32F1xx_HAL_PCCARD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_ll_fsmc.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
00054 /** @addtogroup PCCARD
00055   * @{
00056   */
00057
00058 /** @addtogroup PCCARD_Private_Constants
00059   * @{
00060   */
00061
00062 #define PCCARD_DEVICE_ADDRESS           FSMC_BANK4
00063 #define PCCARD_ATTRIBUTE_SPACE_ADDRESS  ((uint32_t)(FSMC_BANK4 + 0x08000000U))  /* Attribute space size to @0x9BFF FFFF */
00064 #define PCCARD_COMMON_SPACE_ADDRESS     PCCARD_DEVICE_ADDRESS                           /* Common space size to @0x93FF FFFF    */
00065 #define PCCARD_IO_SPACE_ADDRESS         ((uint32_t)(FSMC_BANK4 + 0x0C000000U))  /* IO space size to @0x9FFF FFFF        */
00066 #define PCCARD_IO_SPACE_PRIMARY_ADDR    ((uint32_t)(FSMC_BANK4 + 0x0C0001F0U))  /* IO space size to @0x9FFF FFFF        */
00067
00068 /* Compact Flash-ATA registers description */
00069 #define ATA_DATA                        ((uint8_t)0x00)    /* Data register */
00070 #define ATA_SECTOR_COUNT                ((uint8_t)0x02)    /* Sector Count register */
00071 #define ATA_SECTOR_NUMBER               ((uint8_t)0x03)    /* Sector Number register */
00072 #define ATA_CYLINDER_LOW                ((uint8_t)0x04)    /* Cylinder low register */
00073 #define ATA_CYLINDER_HIGH               ((uint8_t)0x05)    /* Cylinder high register */
00074 #define ATA_CARD_HEAD                   ((uint8_t)0x06)    /* Card/Head register */
00075 #define ATA_STATUS_CMD                  ((uint8_t)0x07)    /* Status(read)/Command(write) register */
00076 #define ATA_STATUS_CMD_ALTERNATE        ((uint8_t)0x0E)    /* Alternate Status(read)/Command(write) register */
00077 #define ATA_COMMON_DATA_AREA            ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
00078 #define ATA_CARD_CONFIGURATION          ((uint16_t)0x0202) /* Card Configuration and Status Register */
00079
00080 /* Compact Flash-ATA commands */
00081 #define ATA_READ_SECTOR_CMD             ((uint8_t)0x20)
00082 #define ATA_WRITE_SECTOR_CMD            ((uint8_t)0x30)
00083 #define ATA_ERASE_SECTOR_CMD            ((uint8_t)0xC0)
00084 #define ATA_IDENTIFY_CMD                ((uint8_t)0xEC)
00085
00086 /* Compact Flash status */
00087 #define PCCARD_TIMEOUT_ERROR            ((uint8_t)0x60)
00088 #define PCCARD_BUSY                     ((uint8_t)0x80)
00089 #define PCCARD_PROGR                    ((uint8_t)0x01)
00090 #define PCCARD_READY                    ((uint8_t)0x40)
00091
00092 #define PCCARD_SECTOR_SIZE              255U    /* In half words */
00093
00094
00095 /* Compact Flash redefinition */
00096 #define HAL_CF_Read_ID              HAL_PCCARD_Read_ID
00097 #define HAL_CF_Write_Sector         HAL_PCCARD_Write_Sector
00098 #define HAL_CF_Read_Sector          HAL_PCCARD_Read_Sector
00099 #define HAL_CF_Erase_Sector         HAL_PCCARD_Erase_Sector
00100 #define HAL_CF_Reset                HAL_PCCARD_Reset
00101
00102 #define HAL_CF_GetStatus            HAL_PCCARD_GetStatus
00103 #define HAL_CF_ReadStatus           HAL_PCCARD_ReadStatus
00104
00105 #define CF_SUCCESS                  HAL_PCCARD_STATUS_SUCCESS
00106 #define CF_ONGOING                  HAL_PCCARD_STATUS_ONGOING
00107 #define CF_ERROR                    HAL_PCCARD_STATUS_ERROR
00108 #define CF_TIMEOUT                  HAL_PCCARD_STATUS_TIMEOUT
00109 #define CF_StatusTypedef            HAL_PCCARD_StatusTypeDef
00110
00111 #define CF_DEVICE_ADDRESS           PCCARD_DEVICE_ADDRESS
00112 #define CF_ATTRIBUTE_SPACE_ADDRESS  PCCARD_ATTRIBUTE_SPACE_ADDRESS
00113 #define CF_COMMON_SPACE_ADDRESS     PCCARD_COMMON_SPACE_ADDRESS
00114 #define CF_IO_SPACE_ADDRESS         PCCARD_IO_SPACE_ADDRESS
00115 #define CF_IO_SPACE_PRIMARY_ADDR    PCCARD_IO_SPACE_PRIMARY_ADDR
00116
00117 #define CF_TIMEOUT_ERROR            PCCARD_TIMEOUT_ERROR
00118 #define CF_BUSY                     PCCARD_BUSY
00119 #define CF_PROGR                    PCCARD_PROGR
00120 #define CF_READY                    PCCARD_READY
00121
00122 #define CF_SECTOR_SIZE              PCCARD_SECTOR_SIZE
00123
00124 /**
00125   * @}
00126   */
00127
00128 /* Exported typedef ----------------------------------------------------------*/
00129 /** @defgroup PCCARD_Exported_Types PCCARD Exported Types
00130   * @{
00131   */
00132
00133 /**
00134   * @brief  HAL PCCARD State structures definition
00135   */
00136 typedef enum
00137 {
00138   HAL_PCCARD_STATE_RESET     = 0x00U,    /*!< PCCARD peripheral not yet initialized or disabled */
00139   HAL_PCCARD_STATE_READY     = 0x01U,    /*!< PCCARD peripheral ready                           */
00140   HAL_PCCARD_STATE_BUSY      = 0x02U,    /*!< PCCARD peripheral busy                            */
00141   HAL_PCCARD_STATE_ERROR     = 0x04U     /*!< PCCARD peripheral error                           */
00142 }HAL_PCCARD_StateTypeDef;
00143
00144 typedef enum
00145 {
00146   HAL_PCCARD_STATUS_SUCCESS = 0U,
00147   HAL_PCCARD_STATUS_ONGOING,
00148   HAL_PCCARD_STATUS_ERROR,
00149   HAL_PCCARD_STATUS_TIMEOUT
00150 }HAL_PCCARD_StatusTypeDef;
00151
00152 /**
00153   * @brief  FSMC_PCCARD handle Structure definition
00154   */
00155 typedef struct
00156 {
00157   FSMC_PCCARD_TypeDef           *Instance;              /*!< Register base address for PCCARD device          */
00158
00159   FSMC_PCCARD_InitTypeDef       Init;                   /*!< PCCARD device control configuration parameters   */
00160
00161   __IO HAL_PCCARD_StateTypeDef State;                  /*!< PCCARD device access state                       */
00162
00163   HAL_LockTypeDef              Lock;                   /*!< PCCARD Lock                                      */
00164
00165 }PCCARD_HandleTypeDef;
00166 /**
00167   * @}
00168   */
00169
00170 /* Exported constants --------------------------------------------------------*/
00171 /* Exported macro ------------------------------------------------------------*/
00172 /** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
00173   * @{
00174   */
00175
00176 /** @brief Reset PCCARD handle state
00177   * @param  __HANDLE__: specifies the PCCARD handle.
00178   * @retval None
00179   */
00180 #define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
00181 /**
00182   * @}
00183   */
00184
00185 /* Exported functions --------------------------------------------------------*/
00186 /** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions
00187   * @{
00188   */
00189
00190 /** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
00191   * @{
00192   */
00193 /* Initialization/de-initialization functions  **********************************/
00194 HAL_StatusTypeDef  HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
00195 HAL_StatusTypeDef  HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
00196 void               HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
00197 void               HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
00198 /**
00199   * @}
00200   */
00201
00202 /** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
00203   * @{
00204   */
00205 /* IO operation functions  *****************************************************/
00206 HAL_StatusTypeDef  HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
00207 HAL_StatusTypeDef  HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,  uint8_t *pStatus);
00208 HAL_StatusTypeDef  HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
00209 HAL_StatusTypeDef  HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
00210 HAL_StatusTypeDef  HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
00211 void               HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
00212 void               HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
00213
00214 /**
00215   * @}
00216   */
00217
00218 /** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
00219   * @{
00220   */
00221 /* PCCARD State functions *******************************************************/
00222 HAL_PCCARD_StateTypeDef  HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
00223 HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
00224 HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
00225 /**
00226   * @}
00227   */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /**
00234   * @}
00235   */
00236
00237 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
00238 /**
00239   * @}
00240   */
00241
00242 #ifdef __cplusplus
00243 }
00244 #endif
00245
00246 #endif /* __STM32F1xx_HAL_PCCARD_H */
00247
00248 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pcd.c Source File

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stm32f1xx_hal_pcd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_pcd.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   PCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                     ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       The PCD HAL driver can be used as follows:
00021
00022      (#) Declare a PCD_HandleTypeDef handle structure, for example:
00023          PCD_HandleTypeDef  hpcd;
00024
00025      (#) Fill parameters of Init structure in HCD handle
00026
00027      (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
00028
00029      (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
00030          (##) Enable the PCD/USB Low Level interface clock using the following macro
00031               (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral available
00032                     on STM32F102xx and STM32F103xx devices
00033               (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); For USB OTG FS peripheral available
00034                     on STM32F105xx and STM32F107xx devices
00035
00036          (##) Initialize the related GPIO clocks
00037          (##) Configure PCD pin-out
00038          (##) Configure PCD NVIC interrupt
00039
00040      (#)Associate the Upper USB device stack to the HAL PCD Driver:
00041          (##) hpcd.pData = pdev;
00042
00043      (#)Enable HCD transmission and reception:
00044          (##) HAL_PCD_Start();
00045
00046   @endverbatim
00047   ******************************************************************************
00048   * @attention
00049   *
00050   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00051   *
00052   * Redistribution and use in source and binary forms, with or without modification,
00053   * are permitted provided that the following conditions are met:
00054   *   1. Redistributions of source code must retain the above copyright notice,
00055   *      this list of conditions and the following disclaimer.
00056   *   2. Redistributions in binary form must reproduce the above copyright notice,
00057   *      this list of conditions and the following disclaimer in the documentation
00058   *      and/or other materials provided with the distribution.
00059   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00060   *      may be used to endorse or promote products derived from this software
00061   *      without specific prior written permission.
00062   *
00063   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00064   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00065   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00066   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00067   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00068   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00069   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00070   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00071   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00072   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00073   *
00074   ******************************************************************************
00075   */
00076
00077 /* Includes ------------------------------------------------------------------*/
00078 #include "stm32f1xx_hal.h"
00079
00080 /** @addtogroup STM32F1xx_HAL_Driver
00081   * @{
00082   */
00083
00084
00085
00086 #ifdef HAL_PCD_MODULE_ENABLED
00087
00088 #if defined(STM32F102x6) || defined(STM32F102xB) || \
00089     defined(STM32F103x6) || defined(STM32F103xB) || \
00090     defined(STM32F103xE) || defined(STM32F103xG) || \
00091     defined(STM32F105xC) || defined(STM32F107xC)
00092
00093 /** @defgroup PCD PCD
00094   * @brief PCD HAL module driver
00095   * @{
00096   */
00097
00098 /* Private types -------------------------------------------------------------*/
00099 /* Private variables ---------------------------------------------------------*/
00100 /* Private constants ---------------------------------------------------------*/
00101 /* Private macros ------------------------------------------------------------*/
00102 /** @defgroup PCD_Private_Macros PCD Private Macros
00103   * @{
00104   */
00105 #define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))
00106 #define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))
00107 /**
00108   * @}
00109   */
00110
00111 /* Private functions ---------------------------------------------------------*/
00112 /** @defgroup PCD_Private_Functions PCD Private Functions
00113   * @{
00114   */
00115 #if defined (USB_OTG_FS)
00116 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
00117 #endif /* USB_OTG_FS */
00118
00119 #if defined (USB)
00120 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
00121 #endif /* USB */
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported functions --------------------------------------------------------*/
00127 /** @defgroup PCD_Exported_Functions PCD Exported Functions
00128   * @{
00129   */
00130
00131 /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00132  *  @brief    Initialization and Configuration functions
00133  *
00134 @verbatim
00135  ===============================================================================
00136             ##### Initialization and de-initialization functions #####
00137  ===============================================================================
00138     [..]  This section provides functions allowing to:
00139
00140 @endverbatim
00141   * @{
00142   */
00143
00144 /**
00145   * @brief  Initializes the PCD according to the specified
00146   *         parameters in the PCD_InitTypeDef and create the associated handle.
00147   * @param  hpcd: PCD handle
00148   * @retval HAL status
00149   */
00150 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
00151 {
00152   uint32_t index = 0U;
00153
00154   /* Check the PCD handle allocation */
00155   if(hpcd == NULL)
00156   {
00157     return HAL_ERROR;
00158   }
00159
00160   /* Check the parameters */
00161   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
00162
00163   if(hpcd->State == HAL_PCD_STATE_RESET)
00164   {
00165     /* Allocate lock resource and initialize it */
00166     hpcd->Lock = HAL_UNLOCKED;
00167
00168     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00169     HAL_PCD_MspInit(hpcd);
00170   }
00171
00172   hpcd->State = HAL_PCD_STATE_BUSY;
00173
00174   /* Disable the Interrupts */
00175   __HAL_PCD_DISABLE(hpcd);
00176
00177   /*Init the Core (common init.) */
00178   USB_CoreInit(hpcd->Instance, hpcd->Init);
00179
00180   /* Force Device Mode*/
00181   USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE);
00182
00183   /* Init endpoints structures */
00184   for (index = 0U; index < 15U ; index++)
00185   {
00186     /* Init ep structure */
00187     hpcd->IN_ep[index].is_in = 1U;
00188     hpcd->IN_ep[index].num = index;
00189     hpcd->IN_ep[index].tx_fifo_num = index;
00190     /* Control until ep is actvated */
00191     hpcd->IN_ep[index].type = EP_TYPE_CTRL;
00192     hpcd->IN_ep[index].maxpacket =  0U;
00193     hpcd->IN_ep[index].xfer_buff = 0U;
00194     hpcd->IN_ep[index].xfer_len = 0U;
00195   }
00196
00197   for (index = 0U; index < 15U ; index++)
00198   {
00199     hpcd->OUT_ep[index].is_in = 0U;
00200     hpcd->OUT_ep[index].num = index;
00201     hpcd->IN_ep[index].tx_fifo_num = index;
00202     /* Control until ep is activated */
00203     hpcd->OUT_ep[index].type = EP_TYPE_CTRL;
00204     hpcd->OUT_ep[index].maxpacket = 0U;
00205     hpcd->OUT_ep[index].xfer_buff = 0U;
00206     hpcd->OUT_ep[index].xfer_len = 0U;
00207   }
00208
00209   /* Init Device */
00210   USB_DevInit(hpcd->Instance, hpcd->Init);
00211
00212   hpcd->USB_Address = 0U;
00213   hpcd->State= HAL_PCD_STATE_READY;
00214
00215   USB_DevDisconnect (hpcd->Instance);
00216   return HAL_OK;
00217 }
00218
00219 /**
00220   * @brief  DeInitializes the PCD peripheral
00221   * @param  hpcd: PCD handle
00222   * @retval HAL status
00223   */
00224 HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
00225 {
00226   /* Check the PCD handle allocation */
00227   if(hpcd == NULL)
00228   {
00229     return HAL_ERROR;
00230   }
00231
00232   hpcd->State = HAL_PCD_STATE_BUSY;
00233
00234   /* Stop Device */
00235   HAL_PCD_Stop(hpcd);
00236
00237   /* DeInit the low level hardware */
00238   HAL_PCD_MspDeInit(hpcd);
00239
00240   hpcd->State = HAL_PCD_STATE_RESET;
00241
00242   return HAL_OK;
00243 }
00244
00245 /**
00246   * @brief  Initializes the PCD MSP.
00247   * @param  hpcd: PCD handle
00248   * @retval None
00249   */
00250 __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
00251 {
00252   /* Prevent unused argument(s) compilation warning */
00253   UNUSED(hpcd);
00254   /* NOTE : This function should not be modified, when the callback is needed,
00255             the HAL_PCD_MspInit could be implemented in the user file
00256    */
00257 }
00258
00259 /**
00260   * @brief  DeInitializes PCD MSP.
00261   * @param  hpcd: PCD handle
00262   * @retval None
00263   */
00264 __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
00265 {
00266   /* Prevent unused argument(s) compilation warning */
00267   UNUSED(hpcd);
00268   /* NOTE : This function should not be modified, when the callback is needed,
00269             the HAL_PCD_MspDeInit could be implemented in the user file
00270    */
00271 }
00272
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup PCD_Exported_Functions_Group2 IO operation functions
00278  *  @brief   Data transfers functions
00279  *
00280 @verbatim
00281  ===============================================================================
00282                       ##### IO operation functions #####
00283  ===============================================================================
00284     [..]
00285     This subsection provides a set of functions allowing to manage the PCD data
00286     transfers.
00287
00288 @endverbatim
00289   * @{
00290   */
00291
00292 /**
00293   * @brief  Start The USB Device.
00294   * @param  hpcd: PCD handle
00295   * @retval HAL status
00296   */
00297 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
00298 {
00299   __HAL_LOCK(hpcd);
00300   HAL_PCDEx_SetConnectionState (hpcd, 1);
00301   USB_DevConnect (hpcd->Instance);
00302   __HAL_PCD_ENABLE(hpcd);
00303   __HAL_UNLOCK(hpcd);
00304   return HAL_OK;
00305 }
00306
00307 /**
00308   * @brief  Stop The USB Device.
00309   * @param  hpcd: PCD handle
00310   * @retval HAL status
00311   */
00312 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
00313 {
00314   __HAL_LOCK(hpcd);
00315   __HAL_PCD_DISABLE(hpcd);
00316   USB_StopDevice(hpcd->Instance);
00317   USB_DevDisconnect (hpcd->Instance);
00318   __HAL_UNLOCK(hpcd);
00319   return HAL_OK;
00320 }
00321
00322 #if defined (USB_OTG_FS)
00323 /**
00324   * @brief  This function handles PCD interrupt request.
00325   * @param  hpcd: PCD handle
00326   * @retval HAL status
00327   */
00328 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
00329 {
00330   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
00331   uint32_t index = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
00332   uint32_t fifoemptymsk = 0U, temp = 0U;
00333   USB_OTG_EPTypeDef *ep = NULL;
00334
00335   /* ensure that we are in device mode */
00336   if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
00337   {
00338     /* avoid spurious interrupt */
00339     if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
00340     {
00341       return;
00342     }
00343
00344     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
00345     {
00346      /* incorrect mode, acknowledge the interrupt */
00347       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
00348     }
00349
00350     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
00351     {
00352       epnum = 0U;
00353
00354       /* Read in the device interrupt bits */
00355       ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
00356
00357       while ( ep_intr )
00358       {
00359         if (ep_intr & 0x1U)
00360         {
00361           epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
00362
00363           if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
00364           {
00365             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
00366
00367             HAL_PCD_DataOutStageCallback(hpcd, epnum);
00368           }
00369
00370           if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
00371           {
00372             /* Inform the upper layer that a setup packet is available */
00373             HAL_PCD_SetupStageCallback(hpcd);
00374             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
00375           }
00376
00377           if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
00378           {
00379             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
00380           }
00381         }
00382         epnum++;
00383         ep_intr >>= 1U;
00384       }
00385     }
00386
00387     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
00388     {
00389       /* Read in the device interrupt bits */
00390       ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
00391
00392       epnum = 0U;
00393
00394       while ( ep_intr )
00395       {
00396         if (ep_intr & 0x1U) /* In ITR */
00397         {
00398           epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
00399
00400           if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
00401           {
00402             fifoemptymsk = 0x1U << epnum;
00403             USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
00404
00405             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
00406
00407             HAL_PCD_DataInStageCallback(hpcd, epnum);
00408           }
00409           if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
00410           {
00411             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);
00412           }
00413           if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)
00414           {
00415             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);
00416           }
00417           if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)
00418           {
00419             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);
00420           }
00421           if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
00422           {
00423             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
00424           }
00425           if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
00426           {
00427             PCD_WriteEmptyTxFifo(hpcd , epnum);
00428           }
00429         }
00430         epnum++;
00431         ep_intr >>= 1U;
00432       }
00433     }
00434
00435     /* Handle Resume Interrupt */
00436     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
00437     {
00438      /* Clear the Remote Wake-up signalling */
00439       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
00440
00441      HAL_PCD_ResumeCallback(hpcd);
00442
00443      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
00444     }
00445
00446     /* Handle Suspend Interrupt */
00447     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
00448     {
00449       if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
00450       {
00451
00452         HAL_PCD_SuspendCallback(hpcd);
00453       }
00454       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
00455     }
00456
00457     /* Handle Reset Interrupt */
00458     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
00459     {
00460       USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
00461       USB_FlushTxFifo(hpcd->Instance ,  0x10U);
00462
00463       for (index = 0U; index < hpcd->Init.dev_endpoints ; index++)
00464       {
00465         USBx_INEP(index)->DIEPINT = 0xFFU;
00466         USBx_OUTEP(index)->DOEPINT = 0xFFU;
00467       }
00468       USBx_DEVICE->DAINT = 0xFFFFFFFFU;
00469       USBx_DEVICE->DAINTMSK |= 0x10001U;
00470
00471       USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
00472       USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
00473
00474       /* Set Default Address to 0 */
00475       USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
00476
00477       /* setup EP0 to receive SETUP packets */
00478       USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
00479
00480       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
00481     }
00482
00483     /* Handle Enumeration done Interrupt */
00484     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
00485     {
00486       USB_ActivateSetup(hpcd->Instance);
00487       hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
00488
00489       hpcd->Init.speed            = USB_OTG_SPEED_FULL;
00490       hpcd->Init.ep0_mps          = USB_OTG_FS_MAX_PACKET_SIZE ;
00491       hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
00492
00493       HAL_PCD_ResetCallback(hpcd);
00494
00495       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
00496     }
00497
00498     /* Handle RxQLevel Interrupt */
00499     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
00500     {
00501       USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00502       temp = USBx->GRXSTSP;
00503       ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
00504
00505       if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) ==  STS_DATA_UPDT)
00506       {
00507         if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
00508         {
00509           USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U);
00510           ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
00511           ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
00512         }
00513       }
00514       else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) ==  STS_SETUP_UPDT)
00515       {
00516         USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
00517         ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
00518       }
00519       USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
00520     }
00521
00522     /* Handle SOF Interrupt */
00523     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
00524     {
00525       HAL_PCD_SOFCallback(hpcd);
00526       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
00527     }
00528
00529     /* Handle Incomplete ISO IN Interrupt */
00530     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
00531     {
00532       HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
00533       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
00534     }
00535
00536     /* Handle Incomplete ISO OUT Interrupt */
00537     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
00538     {
00539       HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
00540       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
00541     }
00542
00543     /* Handle Connection event Interrupt */
00544     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
00545     {
00546       HAL_PCD_ConnectCallback(hpcd);
00547       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
00548     }
00549
00550     /* Handle Disconnection event Interrupt */
00551     if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
00552     {
00553       temp = hpcd->Instance->GOTGINT;
00554
00555       if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
00556       {
00557         HAL_PCD_DisconnectCallback(hpcd);
00558       }
00559       hpcd->Instance->GOTGINT |= temp;
00560     }
00561   }
00562 }
00563 #endif /* USB_OTG_FS */
00564
00565 #if defined (USB)
00566 /**
00567   * @brief  This function handles PCD interrupt request.
00568   * @param  hpcd: PCD handle
00569   * @retval HAL status
00570   */
00571 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
00572 {
00573   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
00574   {
00575     /* servicing of the endpoint correct transfer interrupt */
00576     /* clear of the CTR flag into the sub */
00577     PCD_EP_ISR_Handler(hpcd);
00578   }
00579
00580   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
00581   {
00582     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
00583     HAL_PCD_ResetCallback(hpcd);
00584     HAL_PCD_SetAddress(hpcd, 0U);
00585   }
00586
00587   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
00588   {
00589     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
00590   }
00591   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
00592   {
00593     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
00594   }
00595
00596   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
00597   {
00598     hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE);
00599     hpcd->Instance->CNTR &= ~(USB_CNTR_FSUSP);
00600
00601     HAL_PCD_ResumeCallback(hpcd);
00602
00603     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
00604   }
00605
00606   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
00607   {
00608     /* Force low-power mode in the macrocell */
00609     hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
00610
00611     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
00612     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
00613
00614     hpcd->Instance->CNTR |= USB_CNTR_LP_MODE;
00615     if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U)
00616     {
00617       HAL_PCD_SuspendCallback(hpcd);
00618     }
00619   }
00620
00621   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
00622   {
00623     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
00624     HAL_PCD_SOFCallback(hpcd);
00625   }
00626
00627   if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
00628   {
00629     /* clear ESOF flag in ISTR */
00630     __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
00631   }
00632 }
00633 #endif /* USB */
00634
00635 /**
00636   * @brief  Data out stage callbacks
00637   * @param  hpcd: PCD handle
00638   * @param  epnum: endpoint number
00639   * @retval None
00640   */
00641  __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00642 {
00643   /* Prevent unused argument(s) compilation warning */
00644   UNUSED(hpcd);
00645   UNUSED(epnum);
00646   /* NOTE : This function should not be modified, when the callback is needed,
00647             the HAL_PCD_DataOutStageCallback could be implemented in the user file
00648    */
00649 }
00650
00651 /**
00652   * @brief  Data IN stage callbacks
00653   * @param  hpcd: PCD handle
00654   * @param  epnum: endpoint number
00655   * @retval None
00656   */
00657  __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00658 {
00659   /* Prevent unused argument(s) compilation warning */
00660   UNUSED(hpcd);
00661   UNUSED(epnum);
00662   /* NOTE : This function should not be modified, when the callback is needed,
00663             the HAL_PCD_DataInStageCallback could be implemented in the user file
00664    */
00665 }
00666 /**
00667   * @brief  Setup stage callback
00668   * @param  hpcd: PCD handle
00669   * @retval None
00670   */
00671  __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
00672 {
00673   /* Prevent unused argument(s) compilation warning */
00674   UNUSED(hpcd);
00675   /* NOTE : This function should not be modified, when the callback is needed,
00676             the HAL_PCD_SetupStageCallback could be implemented in the user file
00677    */
00678 }
00679
00680 /**
00681   * @brief  USB Start Of Frame callbacks
00682   * @param  hpcd: PCD handle
00683   * @retval None
00684   */
00685  __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
00686 {
00687   /* Prevent unused argument(s) compilation warning */
00688   UNUSED(hpcd);
00689   /* NOTE : This function should not be modified, when the callback is needed,
00690             the HAL_PCD_SOFCallback could be implemented in the user file
00691    */
00692 }
00693
00694 /**
00695   * @brief  USB Reset callbacks
00696   * @param  hpcd: PCD handle
00697   * @retval None
00698   */
00699  __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
00700 {
00701   /* Prevent unused argument(s) compilation warning */
00702   UNUSED(hpcd);
00703   /* NOTE : This function should not be modified, when the callback is needed,
00704             the HAL_PCD_ResetCallback could be implemented in the user file
00705    */
00706 }
00707
00708 /**
00709   * @brief  Suspend event callbacks
00710   * @param  hpcd: PCD handle
00711   * @retval None
00712   */
00713  __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
00714 {
00715   /* Prevent unused argument(s) compilation warning */
00716   UNUSED(hpcd);
00717   /* NOTE : This function should not be modified, when the callback is needed,
00718             the HAL_PCD_SuspendCallback could be implemented in the user file
00719    */
00720 }
00721
00722 /**
00723   * @brief  Resume event callbacks
00724   * @param  hpcd: PCD handle
00725   * @retval None
00726   */
00727  __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
00728 {
00729   /* Prevent unused argument(s) compilation warning */
00730   UNUSED(hpcd);
00731   /* NOTE : This function should not be modified, when the callback is needed,
00732             the HAL_PCD_ResumeCallback could be implemented in the user file
00733    */
00734 }
00735
00736 /**
00737   * @brief  Incomplete ISO OUT callbacks
00738   * @param  hpcd: PCD handle
00739   * @param  epnum: endpoint number
00740   * @retval None
00741   */
00742  __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00743 {
00744   /* Prevent unused argument(s) compilation warning */
00745   UNUSED(hpcd);
00746   UNUSED(epnum);
00747   /* NOTE : This function should not be modified, when the callback is needed,
00748             the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
00749    */
00750 }
00751
00752 /**
00753   * @brief  Incomplete ISO IN  callbacks
00754   * @param  hpcd: PCD handle
00755   * @param  epnum: endpoint number
00756   * @retval None
00757   */
00758  __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
00759 {
00760   /* Prevent unused argument(s) compilation warning */
00761   UNUSED(hpcd);
00762   UNUSED(epnum);
00763   /* NOTE : This function should not be modified, when the callback is needed,
00764             the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
00765    */
00766 }
00767
00768 /**
00769   * @brief  Connection event callbacks
00770   * @param  hpcd: PCD handle
00771   * @retval None
00772   */
00773  __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
00774 {
00775   /* Prevent unused argument(s) compilation warning */
00776   UNUSED(hpcd);
00777   /* NOTE : This function should not be modified, when the callback is needed,
00778             the HAL_PCD_ConnectCallback could be implemented in the user file
00779    */
00780 }
00781
00782 /**
00783   * @brief  Disconnection event callbacks
00784   * @param  hpcd: PCD handle
00785   * @retval None
00786   */
00787  __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
00788 {
00789   /* Prevent unused argument(s) compilation warning */
00790   UNUSED(hpcd);
00791   /* NOTE : This function should not be modified, when the callback is needed,
00792             the HAL_PCD_DisconnectCallback could be implemented in the user file
00793    */
00794 }
00795
00796 /**
00797   * @}
00798   */
00799
00800 /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
00801  *  @brief   management functions
00802  *
00803 @verbatim
00804  ===============================================================================
00805                       ##### Peripheral Control functions #####
00806  ===============================================================================
00807     [..]
00808     This subsection provides a set of functions allowing to control the PCD data
00809     transfers.
00810
00811 @endverbatim
00812   * @{
00813   */
00814
00815 /**
00816   * @brief  Connect the USB device
00817   * @param  hpcd: PCD handle
00818   * @retval HAL status
00819   */
00820 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
00821 {
00822   __HAL_LOCK(hpcd);
00823   HAL_PCDEx_SetConnectionState (hpcd, 1);
00824   USB_DevConnect(hpcd->Instance);
00825   __HAL_UNLOCK(hpcd);
00826   return HAL_OK;
00827 }
00828
00829 /**
00830   * @brief  Disconnect the USB device
00831   * @param  hpcd: PCD handle
00832   * @retval HAL status
00833   */
00834 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
00835 {
00836   __HAL_LOCK(hpcd);
00837   HAL_PCDEx_SetConnectionState (hpcd, 0U);
00838   USB_DevDisconnect(hpcd->Instance);
00839   __HAL_UNLOCK(hpcd);
00840   return HAL_OK;
00841 }
00842
00843 /**
00844   * @brief  Set the USB Device address
00845   * @param  hpcd: PCD handle
00846   * @param  address: new device address
00847   * @retval HAL status
00848   */
00849 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
00850 {
00851   __HAL_LOCK(hpcd);
00852   hpcd->USB_Address = address;
00853   USB_SetDevAddress(hpcd->Instance, address);
00854   __HAL_UNLOCK(hpcd);
00855   return HAL_OK;
00856 }
00857 /**
00858   * @brief  Open and configure an endpoint
00859   * @param  hpcd: PCD handle
00860   * @param  ep_addr: endpoint address
00861   * @param  ep_mps: endpoint max packet size
00862   * @param  ep_type: endpoint type
00863   * @retval HAL status
00864   */
00865 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
00866 {
00867   HAL_StatusTypeDef  ret = HAL_OK;
00868   PCD_EPTypeDef *ep = NULL;
00869
00870   if ((ep_addr & 0x80U) == 0x80U)
00871   {
00872     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
00873   }
00874   else
00875   {
00876     ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
00877   }
00878   ep->num   = ep_addr & 0x7FU;
00879
00880   ep->is_in = (0x80U & ep_addr) != 0U;
00881   ep->maxpacket = ep_mps;
00882   ep->type = ep_type;
00883
00884   __HAL_LOCK(hpcd);
00885   USB_ActivateEndpoint(hpcd->Instance , ep);
00886   __HAL_UNLOCK(hpcd);
00887   return ret;
00888 }
00889
00890 /**
00891   * @brief  Deactivate an endpoint
00892   * @param  hpcd: PCD handle
00893   * @param  ep_addr: endpoint address
00894   * @retval HAL status
00895   */
00896 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
00897 {
00898   PCD_EPTypeDef *ep = NULL;
00899
00900   if ((ep_addr & 0x80U) == 0x80U)
00901   {
00902     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
00903   }
00904   else
00905   {
00906     ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
00907   }
00908   ep->num   = ep_addr & 0x7FU;
00909
00910   ep->is_in = (0x80U & ep_addr) != 0U;
00911
00912   __HAL_LOCK(hpcd);
00913   USB_DeactivateEndpoint(hpcd->Instance , ep);
00914   __HAL_UNLOCK(hpcd);
00915   return HAL_OK;
00916 }
00917
00918
00919 /**
00920   * @brief  Receive an amount of data
00921   * @param  hpcd: PCD handle
00922   * @param  ep_addr: endpoint address
00923   * @param  pBuf: pointer to the reception buffer
00924   * @param  len: amount of data to be received
00925   * @retval HAL status
00926   */
00927 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
00928 {
00929   PCD_EPTypeDef *ep = NULL;
00930
00931   ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
00932
00933   /*setup and start the Xfer */
00934   ep->xfer_buff = pBuf;
00935   ep->xfer_len = len;
00936   ep->xfer_count = 0U;
00937   ep->is_in = 0U;
00938   ep->num = ep_addr & 0x7FU;
00939
00940   if ((ep_addr & 0x7FU) == 0U)
00941   {
00942     USB_EP0StartXfer(hpcd->Instance , ep);
00943   }
00944   else
00945   {
00946     USB_EPStartXfer(hpcd->Instance , ep);
00947   }
00948
00949   return HAL_OK;
00950 }
00951
00952 /**
00953   * @brief  Get Received Data Size
00954   * @param  hpcd: PCD handle
00955   * @param  ep_addr: endpoint address
00956   * @retval Data Size
00957   */
00958 uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
00959 {
00960   return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count;
00961 }
00962 /**
00963   * @brief  Send an amount of data
00964   * @param  hpcd: PCD handle
00965   * @param  ep_addr: endpoint address
00966   * @param  pBuf: pointer to the transmission buffer
00967   * @param  len: amount of data to be sent
00968   * @retval HAL status
00969   */
00970 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
00971 {
00972   PCD_EPTypeDef *ep = NULL;
00973
00974   ep = &hpcd->IN_ep[ep_addr & 0x7FU];
00975
00976   /*setup and start the Xfer */
00977   ep->xfer_buff = pBuf;
00978   ep->xfer_len = len;
00979   ep->xfer_count = 0U;
00980   ep->is_in = 1U;
00981   ep->num = ep_addr & 0x7FU;
00982
00983   if ((ep_addr & 0x7FU) == 0U)
00984   {
00985     USB_EP0StartXfer(hpcd->Instance , ep);
00986   }
00987   else
00988   {
00989     USB_EPStartXfer(hpcd->Instance , ep);
00990   }
00991
00992   return HAL_OK;
00993 }
00994
00995 /**
00996   * @brief  Set a STALL condition over an endpoint
00997   * @param  hpcd: PCD handle
00998   * @param  ep_addr: endpoint address
00999   * @retval HAL status
01000   */
01001 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01002 {
01003   PCD_EPTypeDef *ep = NULL;
01004
01005   if ((0x80U & ep_addr) == 0x80U)
01006   {
01007     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
01008   }
01009   else
01010   {
01011     ep = &hpcd->OUT_ep[ep_addr];
01012   }
01013
01014   ep->is_stall = 1U;
01015   ep->num   = ep_addr & 0x7FU;
01016   ep->is_in = ((ep_addr & 0x80U) == 0x80U);
01017
01018   __HAL_LOCK(hpcd);
01019   USB_EPSetStall(hpcd->Instance , ep);
01020   if((ep_addr & 0x7FU) == 0U)
01021   {
01022     USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
01023   }
01024   __HAL_UNLOCK(hpcd);
01025
01026   return HAL_OK;
01027 }
01028
01029 /**
01030   * @brief  Clear a STALL condition over in an endpoint
01031   * @param  hpcd: PCD handle
01032   * @param  ep_addr: endpoint address
01033   * @retval HAL status
01034   */
01035 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01036 {
01037   PCD_EPTypeDef *ep = NULL;
01038
01039   if ((0x80U & ep_addr) == 0x80U)
01040   {
01041     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
01042   }
01043   else
01044   {
01045     ep = &hpcd->OUT_ep[ep_addr];
01046   }
01047
01048   ep->is_stall = 0U;
01049   ep->num   = ep_addr & 0x7FU;
01050   ep->is_in = ((ep_addr & 0x80U) == 0x80U);
01051
01052   __HAL_LOCK(hpcd);
01053   USB_EPClearStall(hpcd->Instance , ep);
01054   __HAL_UNLOCK(hpcd);
01055
01056   return HAL_OK;
01057 }
01058
01059 /**
01060   * @brief  Flush an endpoint
01061   * @param  hpcd: PCD handle
01062   * @param  ep_addr: endpoint address
01063   * @retval HAL status
01064   */
01065 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
01066 {
01067   __HAL_LOCK(hpcd);
01068
01069   if ((ep_addr & 0x80U) == 0x80U)
01070   {
01071     USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU);
01072   }
01073   else
01074   {
01075     USB_FlushRxFifo(hpcd->Instance);
01076   }
01077
01078   __HAL_UNLOCK(hpcd);
01079
01080   return HAL_OK;
01081 }
01082
01083 /**
01084   * @brief  HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
01085   * @param  hpcd: PCD handle
01086   * @retval HAL status
01087   */
01088 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01089 {
01090   return(USB_ActivateRemoteWakeup(hpcd->Instance));
01091 }
01092
01093 /**
01094   * @brief  HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
01095   * @param  hpcd: PCD handle
01096   * @retval HAL status
01097   */
01098 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
01099 {
01100   return(USB_DeActivateRemoteWakeup(hpcd->Instance));
01101 }
01102 /**
01103   * @}
01104   */
01105
01106 /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
01107  *  @brief   Peripheral State functions
01108  *
01109 @verbatim
01110  ===============================================================================
01111                       ##### Peripheral State functions #####
01112  ===============================================================================
01113     [..]
01114     This subsection permits to get in run-time the status of the peripheral
01115     and the data flow.
01116
01117 @endverbatim
01118   * @{
01119   */
01120
01121 /**
01122   * @brief  Return the PCD state
01123   * @param  hpcd: PCD handle
01124   * @retval HAL state
01125   */
01126 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
01127 {
01128   return hpcd->State;
01129 }
01130
01131 /**
01132   * @}
01133   */
01134
01135 /**
01136   * @}
01137   */
01138
01139 /** @addtogroup PCD_Private_Functions
01140   * @{
01141   */
01142 #if defined (USB_OTG_FS)
01143 /**
01144   * @brief  DCD_WriteEmptyTxFifo
01145   *         check FIFO for the next packet to be loaded
01146   * @param  hpcd: PCD handle
01147   * @param  epnum : endpoint number
01148   *          This parameter can be a value from 0 to 15
01149   * @retval HAL status
01150   */
01151 static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
01152 {
01153   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
01154   USB_OTG_EPTypeDef *ep = NULL;
01155   int32_t len = 0U;
01156   uint32_t len32b = 0U;
01157   uint32_t fifoemptymsk = 0U;
01158
01159   ep = &hpcd->IN_ep[epnum];
01160   len = ep->xfer_len - ep->xfer_count;
01161
01162   if (len > ep->maxpacket)
01163   {
01164     len = ep->maxpacket;
01165   }
01166
01167   len32b = (len + 3) / 4;
01168
01169   while ((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
01170          ep->xfer_count < ep->xfer_len &&
01171          ep->xfer_len != 0U)
01172   {
01173     /* Write the FIFO */
01174     len = ep->xfer_len - ep->xfer_count;
01175
01176     if (len > ep->maxpacket)
01177     {
01178       len = ep->maxpacket;
01179     }
01180     len32b = (len + 3) / 4;
01181
01182     USB_WritePacket(USBx, ep->xfer_buff, epnum, len);
01183
01184     ep->xfer_buff  += len;
01185     ep->xfer_count += len;
01186   }
01187
01188   if(len <= 0U)
01189   {
01190     fifoemptymsk = 0x1 << epnum;
01191     USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
01192
01193   }
01194
01195   return HAL_OK;
01196 }
01197 #endif /* USB_OTG_FS */
01198
01199 #if defined (USB)
01200 /**
01201   * @brief  This function handles PCD Endpoint interrupt request.
01202   * @param  hpcd: PCD handle
01203   * @retval HAL status
01204   */
01205 static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
01206 {
01207   PCD_EPTypeDef *ep = NULL;
01208   uint16_t count = 0U;
01209   uint8_t epindex = 0U;
01210   __IO uint16_t wIstr = 0U;
01211   __IO uint16_t wEPVal = 0U;
01212
01213   /* stay in loop while pending interrupts */
01214   while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U)
01215   {
01216     /* extract highest priority endpoint number */
01217     epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
01218
01219     if (epindex == 0U)
01220     {
01221       /* Decode and service control endpoint interrupt */
01222
01223       /* DIR bit = origin of the interrupt */
01224       if ((wIstr & USB_ISTR_DIR) == 0U)
01225       {
01226         /* DIR = 0 */
01227
01228         /* DIR = 0      => IN  int */
01229         /* DIR = 0 implies that (EP_CTR_TX = 1) always  */
01230         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01231         ep = &hpcd->IN_ep[0U];
01232
01233         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01234         ep->xfer_buff += ep->xfer_count;
01235
01236         /* TX COMPLETE */
01237         HAL_PCD_DataInStageCallback(hpcd, 0U);
01238
01239
01240         if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U))
01241         {
01242           hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
01243           hpcd->USB_Address = 0U;
01244         }
01245
01246       }
01247       else
01248       {
01249         /* DIR = 1 */
01250
01251         /* DIR = 1 & CTR_RX       => SETUP or OUT int */
01252         /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
01253         ep = &hpcd->OUT_ep[0U];
01254         wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
01255
01256         if ((wEPVal & USB_EP_SETUP) != 0U)
01257         {
01258           /* Get SETUP Packet*/
01259           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01260           USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
01261           /* SETUP bit kept frozen while CTR_RX = 1*/
01262           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01263
01264           /* Process SETUP Packet*/
01265           HAL_PCD_SetupStageCallback(hpcd);
01266         }
01267
01268         else if ((wEPVal & USB_EP_CTR_RX) != 0U)
01269         {
01270           PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
01271           /* Get Control Data OUT Packet*/
01272           ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01273
01274           if (ep->xfer_count != 0U)
01275           {
01276             USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
01277             ep->xfer_buff+=ep->xfer_count;
01278           }
01279
01280           /* Process Control Data OUT Packet*/
01281            HAL_PCD_DataOutStageCallback(hpcd, 0U);
01282
01283           PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
01284           PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
01285         }
01286       }
01287     }
01288     else
01289     {
01290       /* Decode and service non control endpoints interrupt  */
01291
01292       /* process related endpoint register */
01293       wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
01294       if ((wEPVal & USB_EP_CTR_RX) != 0U)
01295       {
01296         /* clear int flag */
01297         PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
01298         ep = &hpcd->OUT_ep[epindex];
01299
01300         /* OUT double Buffering*/
01301         if (ep->doublebuffer == 0U)
01302         {
01303           count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
01304           if (count != 0U)
01305           {
01306             USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
01307           }
01308         }
01309         else
01310         {
01311           if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
01312           {
01313             /*read from endpoint BUF0Addr buffer*/
01314             count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
01315             if (count != 0U)
01316             {
01317               USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
01318             }
01319           }
01320           else
01321           {
01322             /*read from endpoint BUF1Addr buffer*/
01323             count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
01324             if (count != 0U)
01325             {
01326               USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
01327             }
01328           }
01329           PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
01330         }
01331         /*multi-packet on the NON control OUT endpoint*/
01332         ep->xfer_count+=count;
01333         ep->xfer_buff+=count;
01334
01335         if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
01336         {
01337           /* RX COMPLETE */
01338           HAL_PCD_DataOutStageCallback(hpcd, ep->num);
01339         }
01340         else
01341         {
01342           HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
01343         }
01344
01345       } /* if((wEPVal & EP_CTR_RX) */
01346
01347       if ((wEPVal & USB_EP_CTR_TX) != 0U)
01348       {
01349         ep = &hpcd->IN_ep[epindex];
01350
01351         /* clear int flag */
01352         PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
01353
01354         /* IN double Buffering*/
01355         if (ep->doublebuffer == 0U)
01356         {
01357           ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01358           if (ep->xfer_count != 0U)
01359           {
01360             USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
01361           }
01362         }
01363         else
01364         {
01365           if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
01366           {
01367             /*read from endpoint BUF0Addr buffer*/
01368             ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
01369             if (ep->xfer_count != 0U)
01370             {
01371               USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
01372             }
01373           }
01374           else
01375           {
01376             /*read from endpoint BUF1Addr buffer*/
01377             ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
01378             if (ep->xfer_count != 0U)
01379             {
01380               USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
01381             }
01382           }
01383           PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
01384         }
01385         /*multi-packet on the NON control IN endpoint*/
01386         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
01387         ep->xfer_buff+=ep->xfer_count;
01388
01389         /* Zero Length Packet? */
01390         if (ep->xfer_len == 0U)
01391         {
01392           /* TX COMPLETE */
01393           HAL_PCD_DataInStageCallback(hpcd, ep->num);
01394         }
01395         else
01396         {
01397           HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
01398         }
01399       }
01400     }
01401   }
01402   return HAL_OK;
01403 }
01404 #endif /* USB */
01405
01406 /**
01407   * @}
01408   */
01409
01410 /**
01411   * @}
01412   */
01413
01414 #endif /* STM32F102x6 || STM32F102xB || */
01415        /* STM32F103x6 || STM32F103xB || */
01416        /* STM32F103xE || STM32F103xG || */
01417        /* STM32F105xC || STM32F107xC    */
01418
01419 #endif /* HAL_PCD_MODULE_ENABLED */
01420
01421
01422 /**
01423   * @}
01424   */
01425
01426 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pcd.h Source File

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stm32f1xx_hal_pcd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_pcd.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of PCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_PCD_H
00040 #define __STM32F1xx_HAL_PCD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F102x6) || defined(STM32F102xB) || \
00047     defined(STM32F103x6) || defined(STM32F103xB) || \
00048     defined(STM32F103xE) || defined(STM32F103xG) || \
00049     defined(STM32F105xC) || defined(STM32F107xC)
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32f1xx_ll_usb.h"
00053
00054 /** @addtogroup STM32F1xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @addtogroup PCD
00059   * @{
00060   */
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 /** @defgroup PCD_Exported_Types PCD Exported Types
00064   * @{
00065   */
00066
00067 /**
00068   * @brief  PCD State structure definition
00069   */
00070 typedef enum
00071 {
00072   HAL_PCD_STATE_RESET   = 0x00U,
00073   HAL_PCD_STATE_READY   = 0x01U,
00074   HAL_PCD_STATE_ERROR   = 0x02U,
00075   HAL_PCD_STATE_BUSY    = 0x03U,
00076   HAL_PCD_STATE_TIMEOUT = 0x04U
00077 } PCD_StateTypeDef;
00078
00079 #if defined (USB)
00080 /**
00081   * @brief  PCD double buffered endpoint direction
00082   */
00083 typedef enum
00084 {
00085   PCD_EP_DBUF_OUT,
00086   PCD_EP_DBUF_IN,
00087   PCD_EP_DBUF_ERR,
00088 }PCD_EP_DBUF_DIR;
00089
00090 /**
00091   * @brief  PCD endpoint buffer number
00092   */
00093 typedef enum
00094 {
00095   PCD_EP_NOBUF,
00096   PCD_EP_BUF0,
00097   PCD_EP_BUF1
00098 }PCD_EP_BUF_NUM;
00099 #endif /* USB */
00100
00101 #if defined (USB_OTG_FS)
00102 typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
00103 typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
00104 typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;
00105 #endif /* USB_OTG_FS */
00106
00107 #if defined (USB)
00108 typedef USB_TypeDef        PCD_TypeDef;
00109 typedef USB_CfgTypeDef     PCD_InitTypeDef;
00110 typedef USB_EPTypeDef      PCD_EPTypeDef;
00111 #endif /* USB */
00112
00113 /**
00114   * @brief  PCD Handle Structure definition
00115   */
00116 typedef struct
00117 {
00118   PCD_TypeDef             *Instance;   /*!< Register base address               */
00119   PCD_InitTypeDef         Init;        /*!< PCD required parameters             */
00120   __IO uint8_t            USB_Address; /*!< USB Address: not used by USB OTG FS */
00121   PCD_EPTypeDef           IN_ep[15U];   /*!< IN endpoint parameters              */
00122   PCD_EPTypeDef           OUT_ep[15U];  /*!< OUT endpoint parameters             */
00123   HAL_LockTypeDef         Lock;        /*!< PCD peripheral status               */
00124   __IO PCD_StateTypeDef   State;       /*!< PCD communication state             */
00125   uint32_t                Setup[12U];   /*!< Setup packet buffer                 */
00126   void                    *pData;      /*!< Pointer to upper stack Handler      */
00127 } PCD_HandleTypeDef;
00128
00129 /**
00130   * @}
00131   */
00132
00133 /* Include PCD HAL Extension module */
00134 #include "stm32f1xx_hal_pcd_ex.h"
00135
00136 /* Exported constants --------------------------------------------------------*/
00137 /** @defgroup PCD_Exported_Constants PCD Exported Constants
00138   * @{
00139   */
00140
00141 /** @defgroup PCD_Speed PCD Speed
00142   * @{
00143   */
00144 #define PCD_SPEED_HIGH                                                0U /* Not Supported */
00145 #define PCD_SPEED_HIGH_IN_FULL                                        1U /* Not Supported */
00146 #define PCD_SPEED_FULL                                                2U
00147 /**
00148   * @}
00149   */
00150
00151 /** @defgroup PCD_PHY_Module PCD PHY Module
00152   * @{
00153   */
00154 #define PCD_PHY_EMBEDDED                                              2U
00155 /**
00156   * @}
00157   */
00158
00159 /** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
00160   * @{
00161   */
00162 #ifndef USBD_FS_TRDT_VALUE
00163  #define USBD_FS_TRDT_VALUE           5U
00164 #endif /* USBD_FS_TRDT_VALUE */
00165 /**
00166   * @}
00167   */
00168
00169 /**
00170   * @}
00171   */
00172
00173 /* Exported macros -----------------------------------------------------------*/
00174 /** @defgroup PCD_Exported_Macros PCD Exported Macros
00175  *  @brief macros to handle interrupts and specific clock configurations
00176  * @{
00177  */
00178 #if defined (USB_OTG_FS)
00179
00180 #define __HAL_PCD_ENABLE(__HANDLE__)                                  USB_EnableGlobalInt ((__HANDLE__)->Instance)
00181 #define __HAL_PCD_DISABLE(__HANDLE__)                                 USB_DisableGlobalInt ((__HANDLE__)->Instance)
00182
00183 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00184 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
00185 #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)                    (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
00186
00187 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)                         *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
00188                                                                       ~(USB_OTG_PCGCCTL_STOPCLK)
00189
00190 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)                           *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
00191
00192 #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)                        ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
00193
00194 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()                      EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
00195 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()                     EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
00196 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()                       EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
00197 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()                     EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
00198
00199 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()                 \
00200                         do{                                               \
00201                             EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
00202                             EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;    \
00203                           } while(0U)
00204
00205 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE()                \
00206                         do{                                               \
00207                             EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);  \
00208                             EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
00209                           } while(0U)
00210
00211 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()         \
00212                         do{                                               \
00213                             EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
00214                             EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
00215                             EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;    \
00216                             EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;    \
00217                           } while(0U)
00218
00219 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()                  (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
00220 #endif /* USB_OTG_FS */
00221
00222 #if defined (USB)
00223 #define __HAL_PCD_ENABLE(__HANDLE__)                                  USB_EnableGlobalInt ((__HANDLE__)->Instance)
00224 #define __HAL_PCD_DISABLE(__HANDLE__)                                 USB_DisableGlobalInt ((__HANDLE__)->Instance)
00225 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)                 ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
00226 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)               (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
00227
00228 #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT()                             EXTI->IMR |= USB_WAKEUP_EXTI_LINE
00229 #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT()                            EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
00230 #define __HAL_USB_WAKEUP_EXTI_GET_FLAG()                              EXTI->PR & (USB_WAKEUP_EXTI_LINE)
00231 #define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG()                            EXTI->PR = USB_WAKEUP_EXTI_LINE
00232
00233 #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE()                 \
00234                         do{                                        \
00235                             EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
00236                             EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;    \
00237                           } while(0U)
00238
00239 #define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE()                \
00240                         do{                                        \
00241                             EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE);  \
00242                             EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
00243                           } while(0U)
00244
00245 #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()         \
00246                         do{                                        \
00247                             EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
00248                             EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
00249                             EXTI->RTSR |= USB_WAKEUP_EXTI_LINE;    \
00250                             EXTI->FTSR |= USB_WAKEUP_EXTI_LINE;    \
00251                           } while(0U)
00252 #endif /* USB */
00253
00254 /**
00255   * @}
00256   */
00257
00258 /* Exported functions --------------------------------------------------------*/
00259 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
00260   * @{
00261   */
00262
00263 /* Initialization/de-initialization functions  ********************************/
00264 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
00265   * @{
00266   */
00267 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
00268 HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
00269 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
00270 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
00271 /**
00272   * @}
00273   */
00274
00275 /* I/O operation functions  ***************************************************/
00276 /* Non-Blocking mode: Interrupt */
00277 /** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
00278   * @{
00279   */
00280 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
00281 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
00282 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
00283
00284 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00285 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00286 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
00287 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
00288 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
00289 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
00290 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
00291 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00292 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
00293 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
00294 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
00295 /**
00296   * @}
00297   */
00298
00299 /* Peripheral Control functions  **********************************************/
00300 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
00301   * @{
00302   */
00303 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
00304 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
00305 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
00306 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
00307 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00308 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00309 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
00310 uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00311 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00312 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00313 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
00314 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00315 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
00316 /**
00317   * @}
00318   */
00319
00320 /* Peripheral State functions  ************************************************/
00321 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
00322   * @{
00323   */
00324 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
00325 /**
00326   * @}
00327   */
00328
00329 /**
00330   * @}
00331   */
00332
00333 /* Private constants ---------------------------------------------------------*/
00334 /** @defgroup PCD_Private_Constants PCD Private Constants
00335   * @{
00336   */
00337 /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
00338   * @{
00339   */
00340 #if defined (USB_OTG_FS)
00341 #define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            0x08U
00342 #define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU
00343 #define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U
00344
00345 #define USB_OTG_FS_WAKEUP_EXTI_LINE                                    0x00040000U  /*!< External interrupt line 18 Connected to the USB EXTI Line */
00346 #endif /* USB_OTG_FS */
00347
00348 #if defined (USB)
00349 #define  USB_WAKEUP_EXTI_LINE                                         0x00040000U  /*!< External interrupt line 18 Connected to the USB EXTI Line */
00350 #endif /* USB */
00351 /**
00352   * @}
00353   */
00354
00355 #if defined (USB)
00356 /** @defgroup PCD_EP0_MPS PCD EP0 MPS
00357   * @{
00358   */
00359 #define PCD_EP0MPS_64                                                 DEP0CTL_MPS_64
00360 #define PCD_EP0MPS_32                                                 DEP0CTL_MPS_32
00361 #define PCD_EP0MPS_16                                                 DEP0CTL_MPS_16
00362 #define PCD_EP0MPS_08                                                 DEP0CTL_MPS_8
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup PCD_ENDP PCD ENDP
00368   * @{
00369   */
00370 #define PCD_ENDP0                                                     ((uint8_t)0)
00371 #define PCD_ENDP1                                                     ((uint8_t)1)
00372 #define PCD_ENDP2                                                     ((uint8_t)2)
00373 #define PCD_ENDP3                                                     ((uint8_t)3)
00374 #define PCD_ENDP4                                                     ((uint8_t)4)
00375 #define PCD_ENDP5                                                     ((uint8_t)5)
00376 #define PCD_ENDP6                                                     ((uint8_t)6)
00377 #define PCD_ENDP7                                                     ((uint8_t)7)
00378 /**
00379   * @}
00380   */
00381
00382 /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
00383   * @{
00384   */
00385 #define PCD_SNG_BUF                                                   0U
00386 #define PCD_DBL_BUF                                                   1U
00387 /**
00388   * @}
00389   */
00390 #endif /* USB */
00391 /**
00392   * @}
00393   */
00394
00395 /* Private macros ------------------------------------------------------------*/
00396 /** @addtogroup PCD_Private_Macros PCD Private Macros
00397  * @{
00398  */
00399 #if defined (USB)
00400 /* SetENDPOINT */
00401 #define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue)  (*(&(USBx)->EP0R + (bEpNum) * 2U)= (uint16_t)(wRegValue))
00402
00403 /* GetENDPOINT */
00404 #define PCD_GET_ENDPOINT(USBx, bEpNum)            (*(&(USBx)->EP0R + (bEpNum) * 2U))
00405
00406 /* ENDPOINT transfer */
00407 #define USB_EP0StartXfer                          USB_EPStartXfer
00408
00409 /**
00410   * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
00411   * @param  USBx: USB peripheral instance register address.
00412   * @param  bEpNum: Endpoint Number.
00413   * @param  wType: Endpoint Type.
00414   * @retval None
00415   */
00416 #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
00417                                            ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
00418
00419 /**
00420   * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
00421   * @param  USBx: USB peripheral instance register address.
00422   * @param  bEpNum: Endpoint Number.
00423   * @retval Endpoint Type
00424   */
00425 #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
00426
00427 /**
00428   * @brief free buffer used from the application realizing it to the line
00429           toggles bit SW_BUF in the double buffered endpoint register
00430   * @param  USBx: USB peripheral instance register address.
00431   * @param  bEpNum: Endpoint Number.
00432   * @param  bDir: Direction
00433   * @retval None
00434   */
00435 #define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
00436 {\
00437   if ((bDir) == PCD_EP_DBUF_OUT)\
00438   { /* OUT double buffered endpoint */\
00439     PCD_TX_DTOG((USBx), (bEpNum));\
00440   }\
00441   else if ((bDir) == PCD_EP_DBUF_IN)\
00442   { /* IN double buffered endpoint */\
00443     PCD_RX_DTOG((USBx), (bEpNum));\
00444   }\
00445 }
00446
00447 /**
00448   * @brief gets direction of the double buffered endpoint
00449   * @param   USBx: USB peripheral instance register address.
00450   * @param   bEpNum: Endpoint Number.
00451   * @retval EP_DBUF_OUT, EP_DBUF_IN,
00452   *         EP_DBUF_ERR if the endpoint counter not yet programmed.
00453   */
00454 #define PCD_GET_DB_DIR(USBx, bEpNum)\
00455 {\
00456   if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
00457     return(PCD_EP_DBUF_OUT);\
00458   else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
00459     return(PCD_EP_DBUF_IN);\
00460   else\
00461     return(PCD_EP_DBUF_ERR);\
00462 }
00463
00464 /**
00465   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
00466   * @param  USBx: USB peripheral instance register address.
00467   * @param  bEpNum: Endpoint Number.
00468   * @param  wState: new state
00469   * @retval None
00470   */
00471 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
00472    \
00473     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
00474    /* toggle first bit ? */     \
00475    if((USB_EPTX_DTOG1 & (wState))!= 0U)\
00476    {                                                                            \
00477      _wRegVal ^= USB_EPTX_DTOG1;        \
00478    }                                                                            \
00479    /* toggle second bit ?  */         \
00480    if((USB_EPTX_DTOG2 & (wState))!= 0U)      \
00481    {                                                                            \
00482      _wRegVal ^= USB_EPTX_DTOG2;        \
00483    }                                                                            \
00484    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\
00485   } /* PCD_SET_EP_TX_STATUS */
00486
00487 /**
00488   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
00489   * @param  USBx: USB peripheral instance register address.
00490   * @param  bEpNum: Endpoint Number.
00491   * @param  wState: new state
00492   * @retval None
00493   */
00494 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
00495     register uint16_t _wRegVal;   \
00496     \
00497     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
00498     /* toggle first bit ? */  \
00499     if((USB_EPRX_DTOG1 & (wState))!= 0U) \
00500     {                                                                             \
00501       _wRegVal ^= USB_EPRX_DTOG1;  \
00502     }                                                                             \
00503     /* toggle second bit ? */  \
00504     if((USB_EPRX_DTOG2 & (wState))!= 0U) \
00505     {                                                                             \
00506       _wRegVal ^= USB_EPRX_DTOG2;  \
00507     }                                                                             \
00508     PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
00509   } /* PCD_SET_EP_RX_STATUS */
00510
00511 /**
00512   * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
00513   * @param  USBx: USB peripheral instance register address.
00514   * @param  bEpNum: Endpoint Number.
00515   * @param  wStaterx: new state.
00516   * @param  wStatetx: new state.
00517   * @retval None
00518   */
00519 #define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
00520     register uint32_t _wRegVal;   \
00521     \
00522     _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
00523     /* toggle first bit ? */  \
00524     if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
00525     {                                                                                    \
00526       _wRegVal ^= USB_EPRX_DTOG1;  \
00527     }                                                                                    \
00528     /* toggle second bit ? */  \
00529     if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
00530     {                                                                                    \
00531       _wRegVal ^= USB_EPRX_DTOG2;  \
00532     }                                                                                    \
00533     /* toggle first bit ? */     \
00534     if((USB_EPTX_DTOG1 & (wStatetx))!= 0U)      \
00535     {                                                                                    \
00536       _wRegVal ^= USB_EPTX_DTOG1;        \
00537     }                                                                                    \
00538     /* toggle second bit ?  */         \
00539     if((USB_EPTX_DTOG2 & (wStatetx))!= 0U)      \
00540     {                                                                                    \
00541       _wRegVal ^= USB_EPTX_DTOG2;        \
00542     }                                                                                    \
00543     PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX);    \
00544   } /* PCD_SET_EP_TXRX_STATUS */
00545
00546 /**
00547   * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
00548   *         /STAT_RX[1:0])
00549   * @param  USBx: USB peripheral instance register address.
00550   * @param  bEpNum: Endpoint Number.
00551   * @retval status
00552   */
00553 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
00554 #define PCD_GET_EP_RX_STATUS(USBx, bEpNum)     ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
00555
00556 /**
00557   * @brief  sets directly the VALID tx/rx-status into the endpoint register
00558   * @param  USBx: USB peripheral instance register address.
00559   * @param  bEpNum: Endpoint Number.
00560   * @retval None
00561   */
00562 #define PCD_SET_EP_TX_VALID(USBx, bEpNum)      (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
00563 #define PCD_SET_EP_RX_VALID(USBx, bEpNum)      (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
00564
00565 /**
00566   * @brief  checks stall condition in an endpoint.
00567   * @param  USBx: USB peripheral instance register address.
00568   * @param  bEpNum: Endpoint Number.
00569   * @retval TRUE = endpoint in stall condition.
00570   */
00571 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
00572                                    == USB_EP_TX_STALL)
00573 #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
00574                                    == USB_EP_RX_STALL)
00575
00576 /**
00577   * @brief  set & clear EP_KIND bit.
00578   * @param  USBx: USB peripheral instance register address.
00579   * @param  bEpNum: Endpoint Number.
00580   * @retval None
00581   */
00582 #define PCD_SET_EP_KIND(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00583                                 (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
00584 #define PCD_CLEAR_EP_KIND(USBx, bEpNum)  (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00585                                 (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
00586
00587 /**
00588   * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
00589   * @param  USBx: USB peripheral instance register address.
00590   * @param  bEpNum: Endpoint Number.
00591   * @retval None
00592   */
00593 #define PCD_SET_OUT_STATUS(USBx, bEpNum)       PCD_SET_EP_KIND((USBx), (bEpNum))
00594 #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)     PCD_CLEAR_EP_KIND((USBx), (bEpNum))
00595
00596 /**
00597   * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
00598   * @param  USBx: USB peripheral instance register address.
00599   * @param  bEpNum: Endpoint Number.
00600   * @retval None
00601   */
00602 #define PCD_SET_EP_DBUF(USBx, bEpNum)          PCD_SET_EP_KIND((USBx), (bEpNum))
00603 #define PCD_CLEAR_EP_DBUF(USBx, bEpNum)        PCD_CLEAR_EP_KIND((USBx), (bEpNum))
00604
00605 /**
00606   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
00607   * @param  USBx: USB peripheral instance register address.
00608   * @param  bEpNum: Endpoint Number.
00609   * @retval None
00610   */
00611 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
00612                                    PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
00613 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
00614                                    PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
00615
00616 /**
00617   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
00618   * @param  USBx: USB peripheral instance register address.
00619   * @param  bEpNum: Endpoint Number.
00620   * @retval None
00621   */
00622 #define PCD_RX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00623                                    USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
00624 #define PCD_TX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
00625                                    USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
00626
00627 /**
00628   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
00629   * @param  USBx: USB peripheral instance register address.
00630   * @param  bEpNum: Endpoint Number.
00631   * @retval None
00632   */
00633 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0U)\
00634                                          {                                                              \
00635                                            PCD_RX_DTOG((USBx), (bEpNum));                               \
00636                                          }
00637 #define PCD_CLEAR_TX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0U)\
00638                                          {                                                              \
00639                                             PCD_TX_DTOG((USBx), (bEpNum));                              \
00640                                          }
00641
00642 /**
00643   * @brief  Sets address in an endpoint register.
00644   * @param  USBx: USB peripheral instance register address.
00645   * @param  bEpNum: Endpoint Number.
00646   * @param  bAddr: Address.
00647   * @retval None
00648   */
00649 #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
00650     USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
00651
00652 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
00653
00654 #define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U)*2U+     ((uint32_t)(USBx) + 0x400U)))
00655 #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+2U)*2U+  ((uint32_t)(USBx) + 0x400U)))
00656 #define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+4U)*2U+  ((uint32_t)(USBx) + 0x400U)))
00657 #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+6U)*2U+  ((uint32_t)(USBx) + 0x400U)))
00658
00659 #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
00660     uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
00661     PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
00662   }
00663
00664 /**
00665   * @brief  sets address of the tx/rx buffer.
00666   * @param  USBx: USB peripheral instance register address.
00667   * @param  bEpNum: Endpoint Number.
00668   * @param  wAddr: address to be set (must be word aligned).
00669   * @retval None
00670   */
00671 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
00672 #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
00673
00674 /**
00675   * @brief  Gets address of the tx/rx buffer.
00676   * @param  USBx: USB peripheral instance register address.
00677   * @param  bEpNum: Endpoint Number.
00678   * @retval address of the buffer.
00679   */
00680 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
00681 #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
00682
00683 /**
00684   * @brief  Sets counter of rx buffer with no. of blocks.
00685   * @param  dwReg: Register
00686   * @param  wCount: Counter.
00687   * @param  wNBlocks: no. of Blocks.
00688   * @retval None
00689   */
00690 #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
00691     (wNBlocks) = (wCount) >> 5U;\
00692     if(((wCount) & 0x1FU) == 0U)\
00693     {                                                  \
00694       (wNBlocks)--;\
00695     }                                                  \
00696     *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | 0x8000U); \
00697   }/* PCD_CALC_BLK32 */
00698
00699 #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
00700     (wNBlocks) = (wCount) >> 1U;\
00701     if(((wCount) & 0x01U) != 0U)\
00702     {                                                  \
00703       (wNBlocks)++;\
00704     }                                                  \
00705     *pdwReg = (uint16_t)((wNBlocks) << 10U);\
00706   }/* PCD_CALC_BLK2 */
00707
00708 #define PCD_SET_EP_CNT_RX_REG(dwReg,wCount)  {\
00709     uint16_t wNBlocks;\
00710     if((wCount) > 62U)                                \
00711     {                                                \
00712       PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);     \
00713     }                                                \
00714     else                                             \
00715     {                                                \
00716       PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);      \
00717     }                                                \
00718   }/* PCD_SET_EP_CNT_RX_REG */
00719
00720 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
00721     uint32_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
00722     PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
00723   }
00724
00725 /**
00726   * @brief  sets counter for the tx/rx buffer.
00727   * @param  USBx: USB peripheral instance register address.
00728   * @param  bEpNum: Endpoint Number.
00729   * @param  wCount: Counter value.
00730   * @retval None
00731   */
00732 #define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
00733
00734
00735 /**
00736   * @brief  gets counter of the tx buffer.
00737   * @param  USBx: USB peripheral instance register address.
00738   * @param  bEpNum: Endpoint Number.
00739   * @retval Counter value
00740   */
00741 #define PCD_GET_EP_TX_CNT(USBx, bEpNum)        ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3FFU)
00742 #define PCD_GET_EP_RX_CNT(USBx, bEpNum)        ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3FFU)
00743
00744 /**
00745   * @brief  Sets buffer 0/1 address in a double buffer endpoint.
00746   * @param  USBx: USB peripheral instance register address.
00747   * @param  bEpNum: Endpoint Number.
00748   * @param  wBuf0Addr: buffer 0 address.
00749   * @retval Counter value
00750   */
00751 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
00752 #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
00753
00754 /**
00755   * @brief  Sets addresses in a double buffer endpoint.
00756   * @param  USBx: USB peripheral instance register address.
00757   * @param  bEpNum: Endpoint Number.
00758   * @param  wBuf0Addr: buffer 0 address.
00759   * @param  wBuf1Addr = buffer 1 address.
00760   * @retval None
00761   */
00762 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
00763     PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
00764     PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
00765   } /* PCD_SET_EP_DBUF_ADDR */
00766
00767 /**
00768   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00769   * @param  USBx: USB peripheral instance register address.
00770   * @param  bEpNum: Endpoint Number.
00771   * @retval None
00772   */
00773 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum)    (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
00774 #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum)    (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
00775
00776 /**
00777   * @brief  Gets buffer 0/1 address of a double buffer endpoint.
00778   * @param  USBx: USB peripheral instance register address.
00779   * @param  bEpNum: Endpoint Number.
00780   * @param  bDir: endpoint dir  EP_DBUF_OUT = OUT
00781   *         EP_DBUF_IN  = IN
00782   * @param  wCount: Counter value
00783   * @retval None
00784   */
00785 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)  { \
00786     if((bDir) == PCD_EP_DBUF_OUT)\
00787       /* OUT endpoint */ \
00788     {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
00789     else if((bDir) == PCD_EP_DBUF_IN)\
00790       /* IN endpoint */ \
00791       *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount);  \
00792   } /* SetEPDblBuf0Count*/
00793
00794 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)  { \
00795     if((bDir) == PCD_EP_DBUF_OUT)\
00796     {/* OUT endpoint */                                       \
00797       PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));           \
00798     }                                                         \
00799     else if((bDir) == PCD_EP_DBUF_IN)\
00800     {/* IN endpoint */                                        \
00801       *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
00802     }                                                         \
00803   } /* SetEPDblBuf1Count */
00804
00805 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
00806     PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
00807     PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
00808   } /* PCD_SET_EP_DBUF_CNT  */
00809
00810 /**
00811   * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
00812   * @param  USBx: USB peripheral instance register address.
00813   * @param  bEpNum: Endpoint Number.
00814   * @retval None
00815   */
00816 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum)     (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
00817 #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum)     (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
00818
00819 #endif /* USB */
00820
00821 /** @defgroup PCD_Instance_definition PCD Instance definition
00822   * @{
00823   */
00824 #define IS_PCD_ALL_INSTANCE                                        IS_USB_ALL_INSTANCE
00825 /**
00826   * @}
00827   */
00828
00829 /**
00830   * @}
00831   */
00832
00833 /**
00834   * @}
00835   */
00836
00837 /**
00838   * @}
00839   */
00840
00841 #endif /* STM32F102x6 || STM32F102xB || */
00842        /* STM32F103x6 || STM32F103xB || */
00843        /* STM32F103xE || STM32F103xG || */
00844        /* STM32F105xC || STM32F107xC    */
00845
00846 #ifdef __cplusplus
00847 }
00848 #endif
00849
00850
00851 #endif /* __STM32F1xx_HAL_PCD_H */
00852
00853 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pcd_ex.c Source File

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stm32f1xx_hal_pcd_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_pcd_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Extended PCD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the USB Peripheral Controller:
00010   *           + Extended features functions: Update FIFO configuration,
00011   *           PMA configuration for EPs
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00017   *
00018   * Redistribution and use in source and binary forms, with or without modification,
00019   * are permitted provided that the following conditions are met:
00020   *   1. Redistributions of source code must retain the above copyright notice,
00021   *      this list of conditions and the following disclaimer.
00022   *   2. Redistributions in binary form must reproduce the above copyright notice,
00023   *      this list of conditions and the following disclaimer in the documentation
00024   *      and/or other materials provided with the distribution.
00025   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00026   *      may be used to endorse or promote products derived from this software
00027   *      without specific prior written permission.
00028   *
00029   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00031   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00032   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00033   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00034   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00035   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00036   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00037   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00038   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32f1xx_hal.h"
00045
00046 /** @addtogroup STM32F1xx_HAL_Driver
00047   * @{
00048   */
00049
00050 #ifdef HAL_PCD_MODULE_ENABLED
00051
00052 #if defined(STM32F102x6) || defined(STM32F102xB) || \
00053     defined(STM32F103x6) || defined(STM32F103xB) || \
00054     defined(STM32F103xE) || defined(STM32F103xG) || \
00055     defined(STM32F105xC) || defined(STM32F107xC)
00056
00057
00058 /** @defgroup PCDEx PCDEx
00059   * @brief PCD Extended HAL module driver
00060   * @{
00061   */
00062
00063
00064 /* Private types -------------------------------------------------------------*/
00065 /* Private variables ---------------------------------------------------------*/
00066 /* Private constants ---------------------------------------------------------*/
00067 /* Private macros ------------------------------------------------------------*/
00068 /* Private functions ---------------------------------------------------------*/
00069 /* Exported functions --------------------------------------------------------*/
00070 /** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
00071   * @{
00072   */
00073
00074 /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00075   * @brief    PCDEx control functions
00076   *
00077 @verbatim
00078  ===============================================================================
00079               ##### Extended Peripheral Control functions #####
00080  ===============================================================================
00081     [..]  This section provides functions allowing to:
00082       (+) Update FIFO (USB_OTG_FS)
00083       (+) Update PMA configuration (USB)
00084
00085 @endverbatim
00086   * @{
00087   */
00088
00089 #if defined (USB_OTG_FS)
00090 /**
00091   * @brief  Set Tx FIFO
00092   * @param  hpcd: PCD handle
00093   * @param  fifo: The number of Tx fifo
00094   * @param  size: Fifo size
00095   * @retval HAL status
00096   */
00097 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
00098 {
00099   uint8_t index = 0;
00100   uint32_t Tx_Offset = 0U;
00101
00102   /*  TXn min size = 16 words. (n  : Transmit FIFO index)
00103       When a TxFIFO is not used, the Configuration should be as follows:
00104           case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00105          --> Txm can use the space allocated for Txn.
00106          case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
00107          --> Txn should be configured with the minimum space of 16 words
00108      The FIFO is used optimally when used TxFIFOs are allocated in the top
00109          of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
00110      When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
00111
00112   Tx_Offset = hpcd->Instance->GRXFSIZ;
00113
00114   if(fifo == 0U)
00115   {
00116     hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16U) | Tx_Offset;
00117   }
00118   else
00119   {
00120     Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
00121     for(index = 0; index < (fifo - 1); index++)
00122     {
00123       Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16U);
00124     }
00125
00126     /* Multiply Tx_Size by 2 to get higher performance */
00127     hpcd->Instance->DIEPTXF[fifo - 1U] = (size << 16U) | Tx_Offset;
00128
00129   }
00130
00131   return HAL_OK;
00132 }
00133
00134 /**
00135   * @brief  Set Rx FIFO
00136   * @param  hpcd: PCD handle
00137   * @param  size: Size of Rx fifo
00138   * @retval HAL status
00139   */
00140 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
00141 {
00142   hpcd->Instance->GRXFSIZ = size;
00143   return HAL_OK;
00144 }
00145 #endif /* USB_OTG_FS */
00146
00147 #if defined (USB)
00148 /**
00149   * @brief  Configure PMA for EP
00150   * @param  hpcd : Device instance
00151   * @param  ep_addr: endpoint address
00152   * @param  ep_kind: endpoint Kind
00153   *                  USB_SNG_BUF: Single Buffer used
00154   *                  USB_DBL_BUF: Double Buffer used
00155   * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
00156   *                   this parameter is 16-bit value providing the address
00157   *                   in PMA allocated to endpoint.
00158   *                   In case of double buffer endpoint this parameter
00159   *                   is a 32-bit value providing the endpoint buffer 0 address
00160   *                   in the LSB part of 32-bit value and endpoint buffer 1 address
00161   *                   in the MSB part of 32-bit value.
00162   * @retval HAL status
00163   */
00164
00165 HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
00166                                        uint16_t ep_addr,
00167                                        uint16_t ep_kind,
00168                                        uint32_t pmaadress)
00169
00170 {
00171   PCD_EPTypeDef *ep = NULL;
00172
00173   /* initialize ep structure*/
00174   if ((ep_addr & 0x80U) == 0x80U)
00175   {
00176     ep = &hpcd->IN_ep[ep_addr & 0x7FU];
00177   }
00178   else
00179   {
00180     ep = &hpcd->OUT_ep[ep_addr];
00181   }
00182
00183   /* Here we check if the endpoint is single or double Buffer*/
00184   if (ep_kind == PCD_SNG_BUF)
00185   {
00186     /*Single Buffer*/
00187     ep->doublebuffer = 0U;
00188     /*Configure te PMA*/
00189     ep->pmaadress = (uint16_t)pmaadress;
00190   }
00191   else /*USB_DBL_BUF*/
00192   {
00193     /*Double Buffer Endpoint*/
00194     ep->doublebuffer = 1U;
00195     /*Configure the PMA*/
00196     ep->pmaaddr0 =  pmaadress & 0x0000FFFFU;
00197     ep->pmaaddr1 =  (pmaadress & 0xFFFF0000U) >> 16U;
00198   }
00199
00200   return HAL_OK;
00201 }
00202 #endif /* USB */
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup PCDEx_Exported_Functions_Group2 Peripheral State functions
00208   * @brief    Manage device connection state
00209   * @{
00210   */
00211 /**
00212   * @brief  Software Device Connection,
00213   *         this function is not required by USB OTG FS peripheral, it is used
00214   *         only by USB Device FS peripheral.
00215   * @param  hpcd: PCD handle
00216   * @param  state: connection state (0 : disconnected / 1: connected)
00217   * @retval None
00218   */
00219 __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
00220 {
00221   /* Prevent unused argument(s) compilation warning */
00222   UNUSED(hpcd);
00223   UNUSED(state);
00224   /* NOTE : This function Should not be modified, when the callback is needed,
00225             the HAL_PCDEx_SetConnectionState could be implemented in the user file
00226    */
00227 }
00228 /**
00229   * @}
00230   */
00231
00232 /**
00233   * @}
00234   */
00235
00236 /**
00237   * @}
00238   */
00239
00240 #endif /* STM32F102x6 || STM32F102xB || */
00241        /* STM32F103x6 || STM32F103xB || */
00242        /* STM32F103xE || STM32F103xG || */
00243        /* STM32F105xC || STM32F107xC    */
00244
00245 #endif /* HAL_PCD_MODULE_ENABLED */
00246
00247
00248 /**
00249   * @}
00250   */
00251
00252 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pcd_ex.h Source File

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stm32f1xx_hal_pcd_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_pcd_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of Extended PCD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_PCD_EX_H
00040 #define __STM32F1xx_HAL_PCD_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 #if defined(STM32F102x6) || defined(STM32F102xB) || \
00047     defined(STM32F103x6) || defined(STM32F103xB) || \
00048     defined(STM32F103xE) || defined(STM32F103xG) || \
00049     defined(STM32F105xC) || defined(STM32F107xC)
00050
00051 /* Includes ------------------------------------------------------------------*/
00052 #include "stm32f1xx_hal_def.h"
00053
00054 /** @addtogroup STM32F1xx_HAL_Driver
00055   * @{
00056   */
00057
00058 /** @addtogroup PCDEx
00059   * @{
00060   */
00061
00062 /* Exported types ------------------------------------------------------------*/
00063 /* Exported constants --------------------------------------------------------*/
00064 /* Exported macros -----------------------------------------------------------*/
00065 /* Exported functions --------------------------------------------------------*/
00066 /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
00067   * @{
00068   */
00069 /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
00070   * @{
00071   */
00072 #if defined (USB_OTG_FS)
00073 HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
00074 HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
00075 #endif /* USB_OTG_FS */
00076
00077 #if defined (USB)
00078 HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
00079                                      uint16_t ep_addr,
00080                                      uint16_t ep_kind,
00081                                      uint32_t pmaadress);
00082 #endif /* USB */
00083 /**
00084   * @}
00085   */
00086
00087 /** @addtogroup PCDEx_Exported_Functions_Group2 Peripheral State functions
00088   * @{
00089   */
00090 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
00091 /**
00092   * @}
00093   */
00094 /**
00095   * @}
00096   */
00097 /**
00098   * @}
00099   */
00100
00101 /**
00102   * @}
00103   */
00104 #endif /* STM32F102x6 || STM32F102xB || */
00105        /* STM32F103x6 || STM32F103xB || */
00106        /* STM32F103xE || STM32F103xG || */
00107        /* STM32F105xC || STM32F107xC    */
00108
00109 #ifdef __cplusplus
00110 }
00111 #endif
00112
00113
00114 #endif /* __STM32F1xx_HAL_PCD_EX_H */
00115
00116 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pwr.c Source File

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stm32f1xx_hal_pwr.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   PWR HAL module driver.
00008   *
00009   *          This file provides firmware functions to manage the following
00010   *          functionalities of the Power Controller (PWR) peripheral:
00011   *           + Initialization/de-initialization functions
00012   *           + Peripheral Control functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00018   *
00019   * Redistribution and use in source and binary forms, with or without modification,
00020   * are permitted provided that the following conditions are met:
00021   *   1. Redistributions of source code must retain the above copyright notice,
00022   *      this list of conditions and the following disclaimer.
00023   *   2. Redistributions in binary form must reproduce the above copyright notice,
00024   *      this list of conditions and the following disclaimer in the documentation
00025   *      and/or other materials provided with the distribution.
00026   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00027   *      may be used to endorse or promote products derived from this software
00028   *      without specific prior written permission.
00029   *
00030   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00031   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00032   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00033   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00034   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00035   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00036   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00037   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00038   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00039   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00040   *
00041   ******************************************************************************
00042   */
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f1xx_hal.h"
00046
00047 /** @addtogroup STM32F1xx_HAL_Driver
00048   * @{
00049   */
00050
00051 /** @defgroup PWR PWR
00052   * @brief    PWR HAL module driver
00053   * @{
00054   */
00055
00056 #ifdef HAL_PWR_MODULE_ENABLED
00057
00058 /* Private typedef -----------------------------------------------------------*/
00059 /* Private define ------------------------------------------------------------*/
00060
00061 /** @defgroup PWR_Private_Constants PWR Private Constants
00062   * @{
00063   */
00064
00065 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00066   * @{
00067   */
00068 #define PVD_MODE_IT               0x00010000U
00069 #define PVD_MODE_EVT              0x00020000U
00070 #define PVD_RISING_EDGE           0x00000001U
00071 #define PVD_FALLING_EDGE          0x00000002U
00072 /**
00073   * @}
00074   */
00075
00076
00077 /** @defgroup PWR_register_alias_address PWR Register alias address
00078   * @{
00079   */
00080 /* ------------- PWR registers bit address in the alias region ---------------*/
00081 #define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
00082 #define PWR_CR_OFFSET            0x00U
00083 #define PWR_CSR_OFFSET           0x04U
00084 #define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
00085 #define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
00086 /**
00087   * @}
00088   */
00089
00090 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
00091   * @{
00092   */
00093 /* --- CR Register ---*/
00094 /* Alias word address of LPSDSR bit */
00095 #define LPSDSR_BIT_NUMBER        PWR_CR_LPDS_Pos
00096 #define CR_LPSDSR_BB             ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))
00097
00098 /* Alias word address of DBP bit */
00099 #define DBP_BIT_NUMBER            PWR_CR_DBP_Pos
00100 #define CR_DBP_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))
00101
00102 /* Alias word address of PVDE bit */
00103 #define PVDE_BIT_NUMBER           PWR_CR_PVDE_Pos
00104 #define CR_PVDE_BB               ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))
00105
00106 /**
00107   * @}
00108   */
00109
00110 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
00111   * @{
00112   */
00113
00114 /* --- CSR Register ---*/
00115 /* Alias word address of EWUP1 bit */
00116 #define CSR_EWUP_BB(VAL)         ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))
00117 /**
00118   * @}
00119   */
00120
00121 /**
00122   * @}
00123   */
00124
00125 /* Private variables ---------------------------------------------------------*/
00126 /* Private function prototypes -----------------------------------------------*/
00127 /** @defgroup PWR_Private_Functions PWR Private Functions
00128  * brief   WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section)
00129  * @{
00130  */
00131 static void PWR_OverloadWfe(void);
00132
00133 /* Private functions ---------------------------------------------------------*/
00134 __NOINLINE
00135 static void PWR_OverloadWfe(void)
00136 {
00137   __asm volatile( "wfe" );
00138   __asm volatile( "nop" );
00139 }
00140
00141 /**
00142   * @}
00143   */
00144
00145
00146 /** @defgroup PWR_Exported_Functions PWR Exported Functions
00147   * @{
00148   */
00149
00150 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00151   *  @brief   Initialization and de-initialization functions
00152   *
00153 @verbatim
00154  ===============================================================================
00155               ##### Initialization and de-initialization functions #####
00156  ===============================================================================
00157     [..]
00158       After reset, the backup domain (RTC registers, RTC backup data
00159       registers) is protected against possible unwanted
00160       write accesses.
00161       To enable access to the RTC Domain and RTC registers, proceed as follows:
00162         (+) Enable the Power Controller (PWR) APB1 interface clock using the
00163             __HAL_RCC_PWR_CLK_ENABLE() macro.
00164         (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
00165
00166 @endverbatim
00167   * @{
00168   */
00169
00170 /**
00171   * @brief  Deinitializes the PWR peripheral registers to their default reset values.
00172   * @retval None
00173   */
00174 void HAL_PWR_DeInit(void)
00175 {
00176   __HAL_RCC_PWR_FORCE_RESET();
00177   __HAL_RCC_PWR_RELEASE_RESET();
00178 }
00179
00180 /**
00181   * @brief  Enables access to the backup domain (RTC registers, RTC
00182   *         backup data registers ).
00183   * @note   If the HSE divided by 128 is used as the RTC clock, the
00184   *         Backup Domain Access should be kept enabled.
00185   * @retval None
00186   */
00187 void HAL_PWR_EnableBkUpAccess(void)
00188 {
00189   /* Enable access to RTC and backup registers */
00190   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
00191 }
00192
00193 /**
00194   * @brief  Disables access to the backup domain (RTC registers, RTC
00195   *         backup data registers).
00196   * @note   If the HSE divided by 128 is used as the RTC clock, the
00197   *         Backup Domain Access should be kept enabled.
00198   * @retval None
00199   */
00200 void HAL_PWR_DisableBkUpAccess(void)
00201 {
00202   /* Disable access to RTC and backup registers */
00203   *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
00204 }
00205
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
00211   * @brief    Low Power modes configuration functions
00212   *
00213 @verbatim
00214  ===============================================================================
00215                  ##### Peripheral Control functions #####
00216  ===============================================================================
00217
00218     *** PVD configuration ***
00219     =========================
00220     [..]
00221       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00222           threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
00223
00224       (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
00225           than the PVD threshold. This event is internally connected to the EXTI
00226           line16 and can generate an interrupt if enabled. This is done through
00227           __HAL_PVD_EXTI_ENABLE_IT() macro.
00228       (+) The PVD is stopped in Standby mode.
00229
00230     *** WakeUp pin configuration ***
00231     ================================
00232     [..]
00233       (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
00234           forced in input pull-down configuration and is active on rising edges.
00235       (+) There is one WakeUp pin:
00236           WakeUp Pin 1 on PA.00.
00237
00238     [..]
00239
00240     *** Low Power modes configuration ***
00241     =====================================
00242      [..]
00243       The device features 3 low-power modes:
00244       (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like
00245                       NVIC, SysTick, etc. are kept running
00246       (+) Stop mode: All clocks are stopped
00247       (+) Standby mode: 1.8V domain powered off
00248
00249
00250    *** Sleep mode ***
00251    ==================
00252     [..]
00253       (+) Entry:
00254           The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
00255               functions with
00256           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00257           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00258
00259       (+) Exit:
00260         (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt
00261              controller (NVIC) can wake up the device from Sleep mode.
00262         (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode.
00263            (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend)
00264            (+++) Any EXTI Line (Internal or External) configured in Event mode
00265
00266    *** Stop mode ***
00267    =================
00268     [..]
00269       The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
00270       clock gating. The voltage regulator can be configured either in normal or low-power mode.
00271       In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
00272       oscillators are disabled. SRAM and register contents are preserved.
00273       In Stop mode, all I/O pins keep the same state as in Run mode.
00274
00275       (+) Entry:
00276            The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx )
00277              function with:
00278           (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
00279           (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
00280           (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
00281           (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
00282       (+) Exit:
00283           (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured
00284           (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode.
00285
00286    *** Standby mode ***
00287    ====================
00288      [..]
00289       The Standby mode allows to achieve the lowest power consumption. It is based on the
00290       Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
00291       consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
00292       switched off. SRAM and register contents are lost except for registers in the Backup domain
00293       and Standby circuitry
00294
00295       (+) Entry:
00296         (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
00297       (+) Exit:
00298         (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in
00299              NRSTpin, IWDG Reset
00300
00301    *** Auto-wakeup (AWU) from low-power mode ***
00302        =============================================
00303        [..]
00304
00305        (+) The MCU can be woken up from low-power mode by an RTC Alarm event,
00306            without depending on an external interrupt (Auto-wakeup mode).
00307
00308        (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
00309
00310            (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
00311                 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
00312
00313    *** PWR Workarounds linked to Silicon Limitation ***
00314        ====================================================
00315        [..]
00316        Below the list of all silicon limitations known on STM32F1xx prouct.
00317
00318        (#)Workarounds Implemented inside PWR HAL Driver
00319           (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function
00320
00321 @endverbatim
00322   * @{
00323   */
00324
00325 /**
00326   * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
00327   * @param  sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
00328   *         information for the PVD.
00329   * @note   Refer to the electrical characteristics of your device datasheet for
00330   *         more details about the voltage threshold corresponding to each
00331   *         detection level.
00332   * @retval None
00333   */
00334 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00335 {
00336   /* Check the parameters */
00337   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00338   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00339
00340   /* Set PLS[7:5] bits according to PVDLevel value */
00341   MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
00342
00343   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00344   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
00345   __HAL_PWR_PVD_EXTI_DISABLE_IT();
00346   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00347   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
00348
00349   /* Configure interrupt mode */
00350   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00351   {
00352     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00353   }
00354
00355   /* Configure event mode */
00356   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00357   {
00358     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
00359   }
00360
00361   /* Configure the edge */
00362   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00363   {
00364     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00365   }
00366
00367   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00368   {
00369     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00370   }
00371 }
00372
00373 /**
00374   * @brief  Enables the Power Voltage Detector(PVD).
00375   * @retval None
00376   */
00377 void HAL_PWR_EnablePVD(void)
00378 {
00379   /* Enable the power voltage detector */
00380   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
00381 }
00382
00383 /**
00384   * @brief  Disables the Power Voltage Detector(PVD).
00385   * @retval None
00386   */
00387 void HAL_PWR_DisablePVD(void)
00388 {
00389   /* Disable the power voltage detector */
00390   *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
00391 }
00392
00393 /**
00394   * @brief Enables the WakeUp PINx functionality.
00395   * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
00396   *        This parameter can be one of the following values:
00397   *           @arg PWR_WAKEUP_PIN1
00398   * @retval None
00399   */
00400 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
00401 {
00402   /* Check the parameter */
00403   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00404   /* Enable the EWUPx pin */
00405   *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
00406 }
00407
00408 /**
00409   * @brief Disables the WakeUp PINx functionality.
00410   * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
00411   *        This parameter can be one of the following values:
00412   *           @arg PWR_WAKEUP_PIN1
00413   * @retval None
00414   */
00415 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00416 {
00417   /* Check the parameter */
00418   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00419   /* Disable the EWUPx pin */
00420   *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
00421 }
00422
00423 /**
00424   * @brief Enters Sleep mode.
00425   * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
00426   * @param Regulator: Regulator state as no effect in SLEEP mode -  allows to support portability from legacy software
00427   * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
00428   *           When WFI entry is used, tick interrupt have to be disabled if not desired as
00429   *           the interrupt wake up source.
00430   *           This parameter can be one of the following values:
00431   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00432   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00433   * @retval None
00434   */
00435 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00436 {
00437   /* Check the parameters */
00438   /* No check on Regulator because parameter not used in SLEEP mode */
00439   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00440
00441   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00442   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00443
00444   /* Select SLEEP mode entry -------------------------------------------------*/
00445   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
00446   {
00447     /* Request Wait For Interrupt */
00448     __WFI();
00449   }
00450   else
00451   {
00452     /* Request Wait For Event */
00453     __SEV();
00454     __WFE();
00455     __WFE();
00456   }
00457 }
00458
00459 /**
00460   * @brief Enters Stop mode.
00461   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
00462   * @note  When exiting Stop mode by using an interrupt or a wakeup event,
00463   *        HSI RC oscillator is selected as system clock.
00464   * @note  When the voltage regulator operates in low power mode, an additional
00465   *         startup delay is incurred when waking up from Stop mode.
00466   *         By keeping the internal regulator ON during Stop mode, the consumption
00467   *         is higher although the startup time is reduced.
00468   * @param Regulator: Specifies the regulator state in Stop mode.
00469   *          This parameter can be one of the following values:
00470   *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
00471   *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
00472   * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
00473   *          This parameter can be one of the following values:
00474   *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
00475   *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
00476   * @retval None
00477   */
00478 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00479 {
00480   /* Check the parameters */
00481   assert_param(IS_PWR_REGULATOR(Regulator));
00482   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
00483
00484   /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
00485   CLEAR_BIT(PWR->CR,  PWR_CR_PDDS);
00486
00487   /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */
00488   MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator);
00489
00490   /* Set SLEEPDEEP bit of Cortex System Control Register */
00491   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00492
00493   /* Select Stop mode entry --------------------------------------------------*/
00494   if(STOPEntry == PWR_STOPENTRY_WFI)
00495   {
00496     /* Request Wait For Interrupt */
00497     __WFI();
00498   }
00499   else
00500   {
00501     /* Request Wait For Event */
00502     __SEV();
00503     PWR_OverloadWfe(); /* WFE redefine locally */
00504     PWR_OverloadWfe(); /* WFE redefine locally */
00505   }
00506   /* Reset SLEEPDEEP bit of Cortex System Control Register */
00507   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00508 }
00509
00510 /**
00511   * @brief Enters Standby mode.
00512   * @note  In Standby mode, all I/O pins are high impedance except for:
00513   *          - Reset pad (still available)
00514   *          - TAMPER pin if configured for tamper or calibration out.
00515   *          - WKUP pin (PA0) if enabled.
00516   * @retval None
00517   */
00518 void HAL_PWR_EnterSTANDBYMode(void)
00519 {
00520   /* Select Standby mode */
00521   SET_BIT(PWR->CR, PWR_CR_PDDS);
00522
00523   /* Set SLEEPDEEP bit of Cortex System Control Register */
00524   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00525
00526   /* This option is used to ensure that store operations are completed */
00527 #if defined ( __CC_ARM)
00528   __force_stores();
00529 #endif
00530   /* Request Wait For Interrupt */
00531   __WFI();
00532 }
00533
00534
00535 /**
00536   * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
00537   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00538   *       re-enters SLEEP mode when an interruption handling is over.
00539   *       Setting this bit is useful when the processor is expected to run only on
00540   *       interruptions handling.
00541   * @retval None
00542   */
00543 void HAL_PWR_EnableSleepOnExit(void)
00544 {
00545   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00546   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00547 }
00548
00549
00550 /**
00551   * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
00552   * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
00553   *       re-enters SLEEP mode when an interruption handling is over.
00554   * @retval None
00555   */
00556 void HAL_PWR_DisableSleepOnExit(void)
00557 {
00558   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00559   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00560 }
00561
00562
00563 /**
00564   * @brief Enables CORTEX M3 SEVONPEND bit.
00565   * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
00566   *       WFE to wake up when an interrupt moves from inactive to pended.
00567   * @retval None
00568   */
00569 void HAL_PWR_EnableSEVOnPend(void)
00570 {
00571   /* Set SEVONPEND bit of Cortex System Control Register */
00572   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00573 }
00574
00575
00576 /**
00577   * @brief Disables CORTEX M3 SEVONPEND bit.
00578   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
00579   *       WFE to wake up when an interrupt moves from inactive to pended.
00580   * @retval None
00581   */
00582 void HAL_PWR_DisableSEVOnPend(void)
00583 {
00584   /* Clear SEVONPEND bit of Cortex System Control Register */
00585   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00586 }
00587
00588
00589
00590 /**
00591   * @brief  This function handles the PWR PVD interrupt request.
00592   * @note   This API should be called under the PVD_IRQHandler().
00593   * @retval None
00594   */
00595 void HAL_PWR_PVD_IRQHandler(void)
00596 {
00597   /* Check PWR exti flag */
00598   if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
00599   {
00600     /* PWR PVD interrupt user callback */
00601     HAL_PWR_PVDCallback();
00602
00603     /* Clear PWR Exti pending bit */
00604     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
00605   }
00606 }
00607
00608 /**
00609   * @brief  PWR PVD interrupt callback
00610   * @retval None
00611   */
00612 __weak void HAL_PWR_PVDCallback(void)
00613 {
00614   /* NOTE : This function Should not be modified, when the callback is needed,
00615             the HAL_PWR_PVDCallback could be implemented in the user file
00616    */
00617 }
00618
00619 /**
00620   * @}
00621   */
00622
00623 /**
00624   * @}
00625   */
00626
00627 #endif /* HAL_PWR_MODULE_ENABLED */
00628 /**
00629   * @}
00630   */
00631
00632 /**
00633   * @}
00634   */
00635
00636 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_pwr.h Source File

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stm32f1xx_hal_pwr.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_pwr.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of PWR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_PWR_H
00040 #define __STM32F1xx_HAL_PWR_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup PWR
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup PWR_Exported_Types PWR Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  PWR PVD configuration structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
00069                             This parameter can be a value of @ref PWR_PVD_detection_level */
00070
00071   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00072                            This parameter can be a value of @ref PWR_PVD_Mode */
00073 }PWR_PVDTypeDef;
00074
00075
00076 /**
00077   * @}
00078   */
00079
00080
00081 /* Internal constants --------------------------------------------------------*/
00082
00083 /** @addtogroup PWR_Private_Constants
00084   * @{
00085   */
00086
00087 #define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
00088
00089 /**
00090   * @}
00091   */
00092
00093
00094 /* Exported constants --------------------------------------------------------*/
00095
00096 /** @defgroup PWR_Exported_Constants PWR Exported Constants
00097   * @{
00098   */
00099
00100 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
00101   * @{
00102   */
00103 #define PWR_PVDLEVEL_0                  PWR_CR_PLS_2V2
00104 #define PWR_PVDLEVEL_1                  PWR_CR_PLS_2V3
00105 #define PWR_PVDLEVEL_2                  PWR_CR_PLS_2V4
00106 #define PWR_PVDLEVEL_3                  PWR_CR_PLS_2V5
00107 #define PWR_PVDLEVEL_4                  PWR_CR_PLS_2V6
00108 #define PWR_PVDLEVEL_5                  PWR_CR_PLS_2V7
00109 #define PWR_PVDLEVEL_6                  PWR_CR_PLS_2V8
00110 #define PWR_PVDLEVEL_7                  PWR_CR_PLS_2V9
00111
00112 /**
00113   * @}
00114   */
00115
00116 /** @defgroup PWR_PVD_Mode PWR PVD Mode
00117   * @{
00118   */
00119 #define PWR_PVD_MODE_NORMAL                 0x00000000U   /*!< basic mode is used */
00120 #define PWR_PVD_MODE_IT_RISING              0x00010001U   /*!< External Interrupt Mode with Rising edge trigger detection */
00121 #define PWR_PVD_MODE_IT_FALLING             0x00010002U   /*!< External Interrupt Mode with Falling edge trigger detection */
00122 #define PWR_PVD_MODE_IT_RISING_FALLING      0x00010003U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00123 #define PWR_PVD_MODE_EVENT_RISING           0x00020001U   /*!< Event Mode with Rising edge trigger detection */
00124 #define PWR_PVD_MODE_EVENT_FALLING          0x00020002U   /*!< Event Mode with Falling edge trigger detection */
00125 #define PWR_PVD_MODE_EVENT_RISING_FALLING   0x00020003U   /*!< Event Mode with Rising/Falling edge trigger detection */
00126
00127 /**
00128   * @}
00129   */
00130
00131
00132 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
00133   * @{
00134   */
00135
00136 #define PWR_WAKEUP_PIN1                 PWR_CSR_EWUP
00137
00138 /**
00139   * @}
00140   */
00141
00142 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
00143   * @{
00144   */
00145 #define PWR_MAINREGULATOR_ON                        0x00000000U
00146 #define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
00147
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
00153   * @{
00154   */
00155 #define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)
00156 #define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)
00157
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
00163   * @{
00164   */
00165 #define PWR_STOPENTRY_WFI               ((uint8_t)0x01)
00166 #define PWR_STOPENTRY_WFE               ((uint8_t)0x02)
00167
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup PWR_Flag PWR Flag
00173   * @{
00174   */
00175 #define PWR_FLAG_WU                     PWR_CSR_WUF
00176 #define PWR_FLAG_SB                     PWR_CSR_SBF
00177 #define PWR_FLAG_PVDO                   PWR_CSR_PVDO
00178
00179
00180 /**
00181   * @}
00182   */
00183
00184 /**
00185   * @}
00186   */
00187
00188 /* Exported macro ------------------------------------------------------------*/
00189 /** @defgroup PWR_Exported_Macros PWR Exported Macros
00190   * @{
00191   */
00192
00193 /** @brief  Check PWR flag is set or not.
00194   * @param  __FLAG__: specifies the flag to check.
00195   *           This parameter can be one of the following values:
00196   *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
00197   *                  was received from the WKUP pin or from the RTC alarm
00198   *                  An additional wakeup event is detected if the WKUP pin is enabled
00199   *                  (by setting the EWUP bit) when the WKUP pin level is already high.
00200   *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
00201   *                  resumed from StandBy mode.
00202   *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
00203   *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
00204   *                  For this reason, this bit is equal to 0 after Standby or reset
00205   *                  until the PVDE bit is set.
00206   * @retval The new state of __FLAG__ (TRUE or FALSE).
00207   */
00208 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
00209
00210 /** @brief  Clear the PWR's pending flags.
00211   * @param  __FLAG__: specifies the flag to clear.
00212   *          This parameter can be one of the following values:
00213   *            @arg PWR_FLAG_WU: Wake Up flag
00214   *            @arg PWR_FLAG_SB: StandBy flag
00215   */
00216 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
00217
00218 /**
00219   * @brief Enable interrupt on PVD Exti Line 16.
00220   * @retval None.
00221   */
00222 #define __HAL_PWR_PVD_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
00223
00224 /**
00225   * @brief Disable interrupt on PVD Exti Line 16.
00226   * @retval None.
00227   */
00228 #define __HAL_PWR_PVD_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
00229
00230 /**
00231   * @brief Enable event on PVD Exti Line 16.
00232   * @retval None.
00233   */
00234 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
00235
00236 /**
00237   * @brief Disable event on PVD Exti Line 16.
00238   * @retval None.
00239   */
00240 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
00241
00242
00243 /**
00244   * @brief  PVD EXTI line configuration: set falling edge trigger.
00245   * @retval None.
00246   */
00247 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
00248
00249
00250 /**
00251   * @brief Disable the PVD Extended Interrupt Falling Trigger.
00252   * @retval None.
00253   */
00254 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
00255
00256
00257 /**
00258   * @brief  PVD EXTI line configuration: set rising edge trigger.
00259   * @retval None.
00260   */
00261 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
00262
00263 /**
00264   * @brief Disable the PVD Extended Interrupt Rising Trigger.
00265   * This parameter can be:
00266   * @retval None.
00267   */
00268 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
00269
00270 /**
00271   * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
00272   * @retval None.
00273   */
00274 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00275
00276 /**
00277   * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
00278   * This parameter can be:
00279   * @retval None.
00280   */
00281 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
00282
00283
00284
00285 /**
00286   * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
00287   * @retval EXTI PVD Line Status.
00288   */
00289 #define __HAL_PWR_PVD_EXTI_GET_FLAG()       (EXTI->PR & (PWR_EXTI_LINE_PVD))
00290
00291 /**
00292   * @brief Clear the PVD EXTI flag.
00293   * @retval None.
00294   */
00295 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()     (EXTI->PR = (PWR_EXTI_LINE_PVD))
00296
00297 /**
00298   * @brief Generate a Software interrupt on selected EXTI line.
00299   * @retval None.
00300   */
00301 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
00302 /**
00303   * @}
00304   */
00305
00306 /* Private macro -------------------------------------------------------------*/
00307 /** @defgroup PWR_Private_Macros PWR Private Macros
00308   * @{
00309   */
00310 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
00311                                  ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
00312                                  ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
00313                                  ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
00314
00315
00316 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
00317                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
00318                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
00319                               ((MODE) == PWR_PVD_MODE_NORMAL))
00320
00321 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
00322
00323 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
00324                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
00325
00326 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
00327
00328 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
00329
00330 /**
00331   * @}
00332   */
00333
00334
00335
00336 /* Exported functions --------------------------------------------------------*/
00337
00338 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
00339   * @{
00340   */
00341
00342 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
00343   * @{
00344   */
00345
00346 /* Initialization and de-initialization functions *******************************/
00347 void HAL_PWR_DeInit(void);
00348 void HAL_PWR_EnableBkUpAccess(void);
00349 void HAL_PWR_DisableBkUpAccess(void);
00350
00351 /**
00352   * @}
00353   */
00354
00355 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
00356   * @{
00357   */
00358
00359 /* Peripheral Control functions  ************************************************/
00360 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
00361 /* #define HAL_PWR_ConfigPVD 12*/
00362 void HAL_PWR_EnablePVD(void);
00363 void HAL_PWR_DisablePVD(void);
00364
00365 /* WakeUp pins configuration functions ****************************************/
00366 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
00367 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
00368
00369 /* Low Power modes configuration functions ************************************/
00370 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
00371 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
00372 void HAL_PWR_EnterSTANDBYMode(void);
00373
00374 void HAL_PWR_EnableSleepOnExit(void);
00375 void HAL_PWR_DisableSleepOnExit(void);
00376 void HAL_PWR_EnableSEVOnPend(void);
00377 void HAL_PWR_DisableSEVOnPend(void);
00378
00379
00380
00381 void HAL_PWR_PVD_IRQHandler(void);
00382 void HAL_PWR_PVDCallback(void);
00383 /**
00384   * @}
00385   */
00386
00387 /**
00388   * @}
00389   */
00390
00391 /**
00392   * @}
00393   */
00394
00395 /**
00396   * @}
00397   */
00398
00399 #ifdef __cplusplus
00400 }
00401 #endif
00402
00403
00404 #endif /* __STM32F1xx_HAL_PWR_H */
00405
00406 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rcc.c Source File

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stm32f1xx_hal_rcc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_rcc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   RCC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Reset and Clock Control (RCC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                       ##### RCC specific features #####
00016   ==============================================================================
00017     [..]
00018       After reset the device is running from Internal High Speed oscillator
00019       (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
00020       and all peripherals are off except internal SRAM, Flash and JTAG.
00021       (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
00022           all peripherals mapped on these buses are running at HSI speed.
00023       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
00024       (+) All GPIOs are in input floating state, except the JTAG pins which
00025           are assigned to be used for debug purpose.
00026     [..] Once the device started from reset, the user application has to:
00027       (+) Configure the clock source to be used to drive the System clock
00028           (if the application needs higher frequency/performance)
00029       (+) Configure the System clock frequency and Flash settings
00030       (+) Configure the AHB and APB buses prescalers
00031       (+) Enable the clock for the peripheral(s) to be used
00032       (+) Configure the clock source(s) for peripherals whose clocks are not
00033           derived from the System clock (I2S, RTC, ADC, USB OTG FS)
00034
00035                       ##### RCC Limitations #####
00036   ==============================================================================
00037     [..]
00038       A delay between an RCC peripheral clock enable and the effective peripheral
00039       enabling should be taken into account in order to manage the peripheral read/write
00040       from/to registers.
00041       (+) This delay depends on the peripheral mapping.
00042         (++) AHB & APB peripherals, 1 dummy read is necessary
00043
00044     [..]
00045       Workarounds:
00046       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
00047           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
00048
00049   @endverbatim
00050   ******************************************************************************
00051   * @attention
00052   *
00053   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00054   *
00055   * Redistribution and use in source and binary forms, with or without modification,
00056   * are permitted provided that the following conditions are met:
00057   *   1. Redistributions of source code must retain the above copyright notice,
00058   *      this list of conditions and the following disclaimer.
00059   *   2. Redistributions in binary form must reproduce the above copyright notice,
00060   *      this list of conditions and the following disclaimer in the documentation
00061   *      and/or other materials provided with the distribution.
00062   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00063   *      may be used to endorse or promote products derived from this software
00064   *      without specific prior written permission.
00065   *
00066   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00067   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00068   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00069   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00070   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00071   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00072   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00073   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00074   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00075   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00076   *
00077   ******************************************************************************
00078 */
00079
00080 /* Includes ------------------------------------------------------------------*/
00081 #include "stm32f1xx_hal.h"
00082
00083 /** @addtogroup STM32F1xx_HAL_Driver
00084   * @{
00085   */
00086
00087 /** @defgroup RCC RCC
00088 * @brief RCC HAL module driver
00089   * @{
00090   */
00091
00092 #ifdef HAL_RCC_MODULE_ENABLED
00093
00094 /* Private typedef -----------------------------------------------------------*/
00095 /* Private define ------------------------------------------------------------*/
00096 /** @defgroup RCC_Private_Constants RCC Private Constants
00097  * @{
00098  */
00099 /**
00100   * @}
00101   */
00102 /* Private macro -------------------------------------------------------------*/
00103 /** @defgroup RCC_Private_Macros RCC Private Macros
00104   * @{
00105   */
00106
00107 #define MCO1_CLK_ENABLE()     __HAL_RCC_GPIOA_CLK_ENABLE()
00108 #define MCO1_GPIO_PORT        GPIOA
00109 #define MCO1_PIN              GPIO_PIN_8
00110
00111 /**
00112   * @}
00113   */
00114
00115 /* Private variables ---------------------------------------------------------*/
00116 /** @defgroup RCC_Private_Variables RCC Private Variables
00117   * @{
00118   */
00119 /**
00120   * @}
00121   */
00122
00123 /* Private function prototypes -----------------------------------------------*/
00124 /* Exported functions ---------------------------------------------------------*/
00125
00126 /** @defgroup RCC_Exported_Functions RCC Exported Functions
00127   * @{
00128   */
00129
00130 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
00131   *  @brief    Initialization and Configuration functions
00132   *
00133   @verbatim
00134   ===============================================================================
00135            ##### Initialization and de-initialization functions #####
00136   ===============================================================================
00137     [..]
00138       This section provides functions allowing to configure the internal/external oscillators
00139       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
00140       and APB2).
00141
00142     [..] Internal/external clock and PLL configuration
00143       (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
00144           the PLL as System clock source.
00145       (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
00146           clock source.
00147
00148       (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x)  crystal oscillator used directly or
00149           through the PLL as System clock source. Can be used also as RTC clock source.
00150
00151       (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
00152
00153       (#) PLL (clocked by HSI or HSE), featuring different output clocks:
00154         (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
00155         (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
00156
00157       (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
00158           and if a HSE clock failure occurs(HSE used directly or through PLL as System
00159           clock source), the System clocks automatically switched to HSI and an interrupt
00160           is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
00161           (Non-Maskable Interrupt) exception vector.
00162
00163       (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
00164           HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
00165
00166     [..] System, AHB and APB buses clocks configuration
00167       (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
00168           HSE and PLL.
00169           The AHB clock (HCLK) is derived from System clock through configurable
00170           prescaler and used to clock the CPU, memory and peripherals mapped
00171           on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
00172           from AHB clock through configurable prescalers and used to clock
00173           the peripherals mapped on these buses. You can use
00174           "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
00175
00176       -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
00177           (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
00178               divided by 128.
00179           (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
00180               to work correctly. This clock is derived of the main PLL through PLL Multiplier.
00181           (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
00182           (+@) IWDG clock which is always the LSI clock.
00183
00184       (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
00185           For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
00186           Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
00187   @endverbatim
00188   * @{
00189   */
00190
00191 /*
00192   Additional consideration on the SYSCLK based on Latency settings:
00193         +-----------------------------------------------+
00194         | Latency       | SYSCLK clock frequency (MHz)  |
00195         |---------------|-------------------------------|
00196         |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
00197         |---------------|-------------------------------|
00198         |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
00199         |---------------|-------------------------------|
00200         |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |
00201         +-----------------------------------------------+
00202   */
00203
00204 /**
00205   * @brief  Resets the RCC clock configuration to the default reset state.
00206   * @note   The default reset state of the clock configuration is given below:
00207   *            - HSI ON and used as system clock source
00208   *            - HSE and PLL OFF
00209   *            - AHB, APB1 and APB2 prescaler set to 1.
00210   *            - CSS and MCO1 OFF
00211   *            - All interrupts disabled
00212   * @note   This function does not modify the configuration of the
00213   *            - Peripheral clocks
00214   *            - LSI, LSE and RTC clocks
00215   * @retval None
00216   */
00217 void HAL_RCC_DeInit(void)
00218 {
00219   /* Switch SYSCLK to HSI */
00220   CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
00221
00222   /* Reset HSEON, CSSON, & PLLON bits */
00223   CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
00224
00225   /* Reset HSEBYP bit */
00226   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00227
00228   /* Reset CFGR register */
00229   CLEAR_REG(RCC->CFGR);
00230
00231   /* Set HSITRIM bits to the reset value */
00232   MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
00233
00234 #if defined(RCC_CFGR2_SUPPORT)
00235   /* Reset CFGR2 register */
00236   CLEAR_REG(RCC->CFGR2);
00237
00238 #endif /* RCC_CFGR2_SUPPORT */
00239   /* Disable all interrupts */
00240   CLEAR_REG(RCC->CIR);
00241
00242   /* Update the SystemCoreClock global variable */
00243   SystemCoreClock = HSI_VALUE;
00244 }
00245
00246 /**
00247   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
00248   *         RCC_OscInitTypeDef.
00249   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
00250   *         contains the configuration information for the RCC Oscillators.
00251   * @note   The PLL is not disabled when used as system clock.
00252   * @note   The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
00253   * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
00254   *         supported by this macro. User should request a transition to LSE Off
00255   *         first and then LSE On or LSE Bypass.
00256   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
00257   *         supported by this macro. User should request a transition to HSE Off
00258   *         first and then HSE On or HSE Bypass.
00259   * @retval HAL status
00260   */
00261 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
00262 {
00263    uint32_t tickstart = 0U;
00264
00265   /* Check the parameters */
00266   assert_param(RCC_OscInitStruct != NULL);
00267   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
00268
00269   /*------------------------------- HSE Configuration ------------------------*/
00270   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
00271   {
00272     /* Check the parameters */
00273     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
00274
00275     /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
00276     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
00277        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
00278     {
00279       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
00280       {
00281         return HAL_ERROR;
00282       }
00283     }
00284     else
00285     {
00286       /* Set the new HSE configuration ---------------------------------------*/
00287       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
00288
00289
00290        /* Check the HSE State */
00291       if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
00292       {
00293         /* Get Start Tick */
00294         tickstart = HAL_GetTick();
00295
00296         /* Wait till HSE is ready */
00297         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00298         {
00299           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00300           {
00301             return HAL_TIMEOUT;
00302           }
00303         }
00304       }
00305       else
00306       {
00307         /* Get Start Tick */
00308         tickstart = HAL_GetTick();
00309
00310         /* Wait till HSE is disabled */
00311         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
00312         {
00313            if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
00314           {
00315             return HAL_TIMEOUT;
00316           }
00317         }
00318       }
00319     }
00320   }
00321   /*----------------------------- HSI Configuration --------------------------*/
00322   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
00323   {
00324     /* Check the parameters */
00325     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
00326     assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
00327
00328     /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
00329     if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
00330        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
00331     {
00332       /* When HSI is used as system clock it will not disabled */
00333       if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
00334       {
00335         return HAL_ERROR;
00336       }
00337       /* Otherwise, just the calibration is allowed */
00338       else
00339       {
00340         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00341         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00342       }
00343     }
00344     else
00345     {
00346       /* Check the HSI State */
00347       if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
00348       {
00349        /* Enable the Internal High Speed oscillator (HSI). */
00350         __HAL_RCC_HSI_ENABLE();
00351
00352         /* Get Start Tick */
00353         tickstart = HAL_GetTick();
00354
00355         /* Wait till HSI is ready */
00356         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00357         {
00358           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00359           {
00360             return HAL_TIMEOUT;
00361           }
00362         }
00363
00364         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
00365         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
00366       }
00367       else
00368       {
00369         /* Disable the Internal High Speed oscillator (HSI). */
00370         __HAL_RCC_HSI_DISABLE();
00371
00372         /* Get Start Tick */
00373         tickstart = HAL_GetTick();
00374
00375         /* Wait till HSI is disabled */
00376         while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
00377         {
00378           if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
00379           {
00380             return HAL_TIMEOUT;
00381           }
00382         }
00383       }
00384     }
00385   }
00386   /*------------------------------ LSI Configuration -------------------------*/
00387   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
00388   {
00389     /* Check the parameters */
00390     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
00391
00392     /* Check the LSI State */
00393     if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
00394     {
00395       /* Enable the Internal Low Speed oscillator (LSI). */
00396       __HAL_RCC_LSI_ENABLE();
00397
00398       /* Get Start Tick */
00399       tickstart = HAL_GetTick();
00400
00401       /* Wait till LSI is ready */
00402       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
00403       {
00404         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00405         {
00406           return HAL_TIMEOUT;
00407         }
00408       }
00409       /*  To have a fully stabilized clock in the specified range, a software delay of 1ms
00410           should be added.*/
00411       HAL_Delay(1);
00412     }
00413     else
00414     {
00415       /* Disable the Internal Low Speed oscillator (LSI). */
00416       __HAL_RCC_LSI_DISABLE();
00417
00418       /* Get Start Tick */
00419       tickstart = HAL_GetTick();
00420
00421       /* Wait till LSI is disabled */
00422       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
00423       {
00424         if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
00425         {
00426           return HAL_TIMEOUT;
00427         }
00428       }
00429     }
00430   }
00431   /*------------------------------ LSE Configuration -------------------------*/
00432   if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
00433   {
00434     FlagStatus       pwrclkchanged = RESET;
00435
00436     /* Check the parameters */
00437     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
00438
00439     /* Update LSE configuration in Backup Domain control register    */
00440     /* Requires to enable write access to Backup Domain of necessary */
00441     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
00442     {
00443       __HAL_RCC_PWR_CLK_ENABLE();
00444       pwrclkchanged = SET;
00445     }
00446
00447     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
00448     {
00449       /* Enable write access to Backup domain */
00450       SET_BIT(PWR->CR, PWR_CR_DBP);
00451
00452       /* Wait for Backup domain Write protection disable */
00453       tickstart = HAL_GetTick();
00454
00455       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
00456       {
00457         if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00458         {
00459           return HAL_TIMEOUT;
00460         }
00461       }
00462     }
00463
00464     /* Set the new LSE configuration -----------------------------------------*/
00465     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
00466     /* Check the LSE State */
00467     if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
00468     {
00469       /* Get Start Tick */
00470       tickstart = HAL_GetTick();
00471
00472       /* Wait till LSE is ready */
00473       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00474       {
00475         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00476         {
00477           return HAL_TIMEOUT;
00478         }
00479       }
00480     }
00481     else
00482     {
00483       /* Get Start Tick */
00484       tickstart = HAL_GetTick();
00485
00486       /* Wait till LSE is disabled */
00487       while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
00488       {
00489         if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
00490         {
00491           return HAL_TIMEOUT;
00492         }
00493       }
00494     }
00495
00496     /* Require to disable power clock if necessary */
00497     if(pwrclkchanged == SET)
00498     {
00499       __HAL_RCC_PWR_CLK_DISABLE();
00500     }
00501   }
00502
00503 #if defined(RCC_CR_PLL2ON)
00504   /*-------------------------------- PLL2 Configuration -----------------------*/
00505   /* Check the parameters */
00506   assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
00507   if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
00508   {
00509     /* This bit can not be cleared if the PLL2 clock is used indirectly as system
00510       clock (i.e. it is used as PLL clock entry that is used as system clock). */
00511     if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
00512         (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
00513         ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
00514     {
00515       return HAL_ERROR;
00516     }
00517     else
00518     {
00519       if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
00520       {
00521         /* Check the parameters */
00522         assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
00523         assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
00524
00525         /* Prediv2 can be written only when the PLLI2S is disabled. */
00526         /* Return an error only if new value is different from the programmed value */
00527         if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
00528           (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
00529         {
00530           return HAL_ERROR;
00531         }
00532
00533         /* Disable the main PLL2. */
00534         __HAL_RCC_PLL2_DISABLE();
00535
00536         /* Get Start Tick */
00537         tickstart = HAL_GetTick();
00538
00539         /* Wait till PLL2 is disabled */
00540         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
00541         {
00542           if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
00543           {
00544             return HAL_TIMEOUT;
00545           }
00546         }
00547
00548         /* Configure the HSE prediv2 factor --------------------------------*/
00549         __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
00550
00551         /* Configure the main PLL2 multiplication factors. */
00552         __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
00553
00554         /* Enable the main PLL2. */
00555         __HAL_RCC_PLL2_ENABLE();
00556
00557         /* Get Start Tick */
00558         tickstart = HAL_GetTick();
00559
00560         /* Wait till PLL2 is ready */
00561         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
00562         {
00563           if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
00564           {
00565             return HAL_TIMEOUT;
00566           }
00567         }
00568       }
00569       else
00570       {
00571        /* Set PREDIV1 source to HSE */
00572         CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
00573
00574         /* Disable the main PLL2. */
00575         __HAL_RCC_PLL2_DISABLE();
00576
00577         /* Get Start Tick */
00578         tickstart = HAL_GetTick();
00579
00580         /* Wait till PLL2 is disabled */
00581         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
00582         {
00583           if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
00584           {
00585             return HAL_TIMEOUT;
00586           }
00587         }
00588       }
00589     }
00590   }
00591
00592 #endif /* RCC_CR_PLL2ON */
00593   /*-------------------------------- PLL Configuration -----------------------*/
00594   /* Check the parameters */
00595   assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
00596   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
00597   {
00598     /* Check if the PLL is used as system clock or not */
00599     if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
00600     {
00601       if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
00602       {
00603         /* Check the parameters */
00604         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
00605         assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
00606
00607         /* Disable the main PLL. */
00608         __HAL_RCC_PLL_DISABLE();
00609
00610         /* Get Start Tick */
00611         tickstart = HAL_GetTick();
00612
00613         /* Wait till PLL is disabled */
00614         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
00615         {
00616           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00617           {
00618             return HAL_TIMEOUT;
00619           }
00620         }
00621
00622         /* Configure the HSE prediv factor --------------------------------*/
00623         /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
00624         if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
00625         {
00626           /* Check the parameter */
00627           assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
00628 #if defined(RCC_CFGR2_PREDIV1SRC)
00629           assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
00630
00631           /* Set PREDIV1 source */
00632           SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
00633 #endif /* RCC_CFGR2_PREDIV1SRC */
00634
00635           /* Set PREDIV1 Value */
00636           __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
00637         }
00638
00639         /* Configure the main PLL clock source and multiplication factors. */
00640         __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
00641                              RCC_OscInitStruct->PLL.PLLMUL);
00642         /* Enable the main PLL. */
00643         __HAL_RCC_PLL_ENABLE();
00644
00645         /* Get Start Tick */
00646         tickstart = HAL_GetTick();
00647
00648         /* Wait till PLL is ready */
00649         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
00650         {
00651           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00652           {
00653             return HAL_TIMEOUT;
00654           }
00655         }
00656       }
00657       else
00658       {
00659         /* Disable the main PLL. */
00660         __HAL_RCC_PLL_DISABLE();
00661
00662         /* Get Start Tick */
00663         tickstart = HAL_GetTick();
00664
00665         /* Wait till PLL is disabled */
00666         while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
00667         {
00668           if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
00669           {
00670             return HAL_TIMEOUT;
00671           }
00672         }
00673       }
00674     }
00675     else
00676     {
00677       return HAL_ERROR;
00678     }
00679   }
00680
00681   return HAL_OK;
00682 }
00683
00684 /**
00685   * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified
00686   *         parameters in the RCC_ClkInitStruct.
00687   * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
00688   *         contains the configuration information for the RCC peripheral.
00689   * @param  FLatency FLASH Latency
00690   *          The value of this parameter depend on device used within the same series
00691   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
00692   *         and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
00693   *
00694   * @note   The HSI is used (enabled by hardware) as system clock source after
00695   *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
00696   *         of failure of the HSE used directly or indirectly as system clock
00697   *         (if the Clock Security System CSS is enabled).
00698   *
00699   * @note   A switch from one clock source to another occurs only if the target
00700   *         clock source is ready (clock stable after start-up delay or PLL locked).
00701   *         If a clock source which is not yet ready is selected, the switch will
00702   *         occur when the clock source will be ready.
00703   *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
00704   *         currently used as system clock source.
00705   * @retval HAL status
00706   */
00707 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
00708 {
00709   uint32_t tickstart = 0U;
00710
00711   /* Check the parameters */
00712   assert_param(RCC_ClkInitStruct != NULL);
00713   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
00714   assert_param(IS_FLASH_LATENCY(FLatency));
00715
00716   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
00717   must be correctly programmed according to the frequency of the CPU clock
00718     (HCLK) of the device. */
00719
00720 #if defined(FLASH_ACR_LATENCY)
00721   /* Increasing the number of wait states because of higher CPU frequency */
00722   if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
00723   {
00724     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00725     __HAL_FLASH_SET_LATENCY(FLatency);
00726
00727     /* Check that the new number of wait states is taken into account to access the Flash
00728     memory by reading the FLASH_ACR register */
00729     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00730     {
00731       return HAL_ERROR;
00732     }
00733   }
00734
00735 #endif /* FLASH_ACR_LATENCY */
00736   /*-------------------------- HCLK Configuration --------------------------*/
00737   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
00738   {
00739     assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
00740     MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
00741   }
00742
00743   /*------------------------- SYSCLK Configuration ---------------------------*/
00744   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
00745   {
00746     assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
00747
00748     /* HSE is selected as System Clock Source */
00749     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00750     {
00751       /* Check the HSE ready flag */
00752       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
00753       {
00754         return HAL_ERROR;
00755       }
00756     }
00757     /* PLL is selected as System Clock Source */
00758     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00759     {
00760       /* Check the PLL ready flag */
00761       if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
00762       {
00763         return HAL_ERROR;
00764       }
00765     }
00766     /* HSI is selected as System Clock Source */
00767     else
00768     {
00769       /* Check the HSI ready flag */
00770       if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
00771       {
00772         return HAL_ERROR;
00773       }
00774     }
00775     __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
00776
00777     /* Get Start Tick */
00778     tickstart = HAL_GetTick();
00779
00780     if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
00781     {
00782       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
00783       {
00784         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00785         {
00786           return HAL_TIMEOUT;
00787         }
00788       }
00789     }
00790     else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
00791     {
00792       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
00793       {
00794         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00795         {
00796           return HAL_TIMEOUT;
00797         }
00798       }
00799     }
00800     else
00801     {
00802       while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
00803       {
00804         if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
00805         {
00806           return HAL_TIMEOUT;
00807         }
00808       }
00809     }
00810   }
00811 #if defined(FLASH_ACR_LATENCY)
00812   /* Decreasing the number of wait states because of lower CPU frequency */
00813   if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
00814   {
00815     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
00816     __HAL_FLASH_SET_LATENCY(FLatency);
00817
00818     /* Check that the new number of wait states is taken into account to access the Flash
00819     memory by reading the FLASH_ACR register */
00820     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
00821     {
00822       return HAL_ERROR;
00823     }
00824   }
00825 #endif /* FLASH_ACR_LATENCY */
00826
00827   /*-------------------------- PCLK1 Configuration ---------------------------*/
00828   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
00829   {
00830     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
00831     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
00832   }
00833
00834   /*-------------------------- PCLK2 Configuration ---------------------------*/
00835   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
00836   {
00837     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
00838     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
00839   }
00840
00841   /* Update the SystemCoreClock global variable */
00842   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
00843
00844   /* Configure the source of time base considering new system clocks settings*/
00845   HAL_InitTick (TICK_INT_PRIORITY);
00846
00847   return HAL_OK;
00848 }
00849
00850 /**
00851   * @}
00852   */
00853
00854 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
00855   *  @brief   RCC clocks control functions
00856   *
00857   @verbatim
00858   ===============================================================================
00859                   ##### Peripheral Control functions #####
00860   ===============================================================================
00861     [..]
00862     This subsection provides a set of functions allowing to control the RCC Clocks
00863     frequencies.
00864
00865   @endverbatim
00866   * @{
00867   */
00868
00869 /**
00870   * @brief  Selects the clock source to output on MCO pin.
00871   * @note   MCO pin should be configured in alternate function mode.
00872   * @param  RCC_MCOx specifies the output direction for the clock source.
00873   *          This parameter can be one of the following values:
00874   *            @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
00875   * @param  RCC_MCOSource specifies the clock source to output.
00876   *          This parameter can be one of the following values:
00877   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK     No clock selected as MCO clock
00878   *            @arg @ref RCC_MCO1SOURCE_SYSCLK      System clock selected as MCO clock
00879   *            @arg @ref RCC_MCO1SOURCE_HSI         HSI selected as MCO clock
00880   *            @arg @ref RCC_MCO1SOURCE_HSE         HSE selected as MCO clock
00881   @if STM32F105xC
00882   *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO source
00883   *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected as MCO source
00884   *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
00885   *            @arg @ref RCC_MCO1SOURCE_EXT_HSE      XT1 external 3-25 MHz oscillator clock selected as MCO source
00886   *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected as MCO source
00887   @endif
00888   @if STM32F107xC
00889   *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO source
00890   *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected as MCO source
00891   *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
00892   *            @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1  external 3-25 MHz oscillator clock selected as MCO source
00893   *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected as MCO source
00894   @endif
00895   * @param  RCC_MCODiv specifies the MCO DIV.
00896   *          This parameter can be one of the following values:
00897   *            @arg @ref RCC_MCODIV_1 no division applied to MCO clock
00898   * @retval None
00899   */
00900 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
00901 {
00902   GPIO_InitTypeDef gpio = {0U};
00903
00904   /* Check the parameters */
00905   assert_param(IS_RCC_MCO(RCC_MCOx));
00906   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
00907   assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
00908
00909   /* Configure the MCO1 pin in alternate function mode */
00910   gpio.Mode      = GPIO_MODE_AF_PP;
00911   gpio.Speed     = GPIO_SPEED_FREQ_HIGH;
00912   gpio.Pull      = GPIO_NOPULL;
00913   gpio.Pin       = MCO1_PIN;
00914
00915   /* MCO1 Clock Enable */
00916   MCO1_CLK_ENABLE();
00917
00918   HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
00919
00920   /* Configure the MCO clock source */
00921   __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
00922 }
00923
00924 /**
00925   * @brief  Enables the Clock Security System.
00926   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
00927   *         is automatically disabled and an interrupt is generated to inform the
00928   *         software about the failure (Clock Security System Interrupt, CSSI),
00929   *         allowing the MCU to perform rescue operations. The CSSI is linked to
00930   *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
00931   * @retval None
00932   */
00933 void HAL_RCC_EnableCSS(void)
00934 {
00935   *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
00936 }
00937
00938 /**
00939   * @brief  Disables the Clock Security System.
00940   * @retval None
00941   */
00942 void HAL_RCC_DisableCSS(void)
00943 {
00944   *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
00945 }
00946
00947 /**
00948   * @brief  Returns the SYSCLK frequency
00949   * @note   The system frequency computed by this function is not the real
00950   *         frequency in the chip. It is calculated based on the predefined
00951   *         constant and the selected clock source:
00952   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
00953   * @note     If SYSCLK source is HSE, function returns a value based on HSE_VALUE
00954   *           divided by PREDIV factor(**)
00955   * @note     If SYSCLK source is PLL, function returns a value based on HSE_VALUE
00956   *           divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
00957   * @note     (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
00958   *               8 MHz) but the real value may vary depending on the variations
00959   *               in voltage and temperature.
00960   * @note     (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
00961   *                8 MHz), user has to ensure that HSE_VALUE is same as the real
00962   *                frequency of the crystal used. Otherwise, this function may
00963   *                have wrong result.
00964   *
00965   * @note   The result of this function could be not correct when using fractional
00966   *         value for HSE crystal.
00967   *
00968   * @note   This function can be used by the user application to compute the
00969   *         baud-rate for the communication peripherals or configure other parameters.
00970   *
00971   * @note   Each time SYSCLK changes, this function must be called to update the
00972   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
00973   *
00974   * @retval SYSCLK frequency
00975   */
00976 uint32_t HAL_RCC_GetSysClockFreq(void)
00977 {
00978 #if defined(RCC_CFGR2_PREDIV1SRC)
00979   const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
00980   const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
00981 #else
00982   const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
00983 #if defined(RCC_CFGR2_PREDIV1)
00984   const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
00985 #else
00986   const uint8_t aPredivFactorTable[2] = {1, 2};
00987 #endif /*RCC_CFGR2_PREDIV1*/
00988
00989 #endif
00990   uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
00991   uint32_t sysclockfreq = 0U;
00992 #if defined(RCC_CFGR2_PREDIV1SRC)
00993   uint32_t prediv2 = 0U, pll2mul = 0U;
00994 #endif /*RCC_CFGR2_PREDIV1SRC*/
00995
00996   tmpreg = RCC->CFGR;
00997
00998   /* Get SYSCLK source -------------------------------------------------------*/
00999   switch (tmpreg & RCC_CFGR_SWS)
01000   {
01001     case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
01002     {
01003       sysclockfreq = HSE_VALUE;
01004       break;
01005     }
01006     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
01007     {
01008       pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
01009       if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
01010       {
01011 #if defined(RCC_CFGR2_PREDIV1)
01012         prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
01013 #else
01014         prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
01015 #endif /*RCC_CFGR2_PREDIV1*/
01016 #if defined(RCC_CFGR2_PREDIV1SRC)
01017
01018         if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
01019         {
01020           /* PLL2 selected as Prediv1 source */
01021           /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
01022           prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
01023           pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
01024           pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
01025         }
01026         else
01027         {
01028           /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
01029           pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
01030         }
01031
01032         /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
01033         /* In this case need to divide pllclk by 2 */
01034         if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
01035         {
01036             pllclk = pllclk / 2;
01037         }
01038 #else
01039         /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
01040         pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
01041 #endif /*RCC_CFGR2_PREDIV1SRC*/
01042       }
01043       else
01044       {
01045         /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
01046         pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
01047       }
01048       sysclockfreq = pllclk;
01049       break;
01050     }
01051     case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
01052     default: /* HSI used as system clock */
01053     {
01054       sysclockfreq = HSI_VALUE;
01055       break;
01056     }
01057   }
01058   return sysclockfreq;
01059 }
01060
01061 /**
01062   * @brief  Returns the HCLK frequency
01063   * @note   Each time HCLK changes, this function must be called to update the
01064   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
01065   *
01066   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
01067   *         and updated within this function
01068   * @retval HCLK frequency
01069   */
01070 uint32_t HAL_RCC_GetHCLKFreq(void)
01071 {
01072   return SystemCoreClock;
01073 }
01074
01075 /**
01076   * @brief  Returns the PCLK1 frequency
01077   * @note   Each time PCLK1 changes, this function must be called to update the
01078   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
01079   * @retval PCLK1 frequency
01080   */
01081 uint32_t HAL_RCC_GetPCLK1Freq(void)
01082 {
01083   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
01084   return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
01085 }
01086
01087 /**
01088   * @brief  Returns the PCLK2 frequency
01089   * @note   Each time PCLK2 changes, this function must be called to update the
01090   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
01091   * @retval PCLK2 frequency
01092   */
01093 uint32_t HAL_RCC_GetPCLK2Freq(void)
01094 {
01095   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
01096   return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
01097 }
01098
01099 /**
01100   * @brief  Configures the RCC_OscInitStruct according to the internal
01101   * RCC configuration registers.
01102   * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
01103   * will be configured.
01104   * @retval None
01105   */
01106 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
01107 {
01108   /* Check the parameters */
01109   assert_param(RCC_OscInitStruct != NULL);
01110
01111   /* Set all possible values for the Oscillator type parameter ---------------*/
01112   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
01113                   | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
01114
01115 #if defined(RCC_CFGR2_PREDIV1SRC)
01116   /* Get the Prediv1 source --------------------------------------------------*/
01117   RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
01118 #endif /* RCC_CFGR2_PREDIV1SRC */
01119
01120   /* Get the HSE configuration -----------------------------------------------*/
01121   if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
01122   {
01123     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
01124   }
01125   else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
01126   {
01127     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
01128   }
01129   else
01130   {
01131     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
01132   }
01133   RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
01134
01135   /* Get the HSI configuration -----------------------------------------------*/
01136   if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
01137   {
01138     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
01139   }
01140   else
01141   {
01142     RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
01143   }
01144
01145   RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
01146
01147   /* Get the LSE configuration -----------------------------------------------*/
01148   if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
01149   {
01150     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
01151   }
01152   else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
01153   {
01154     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
01155   }
01156   else
01157   {
01158     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
01159   }
01160
01161   /* Get the LSI configuration -----------------------------------------------*/
01162   if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
01163   {
01164     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
01165   }
01166   else
01167   {
01168     RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
01169   }
01170
01171
01172   /* Get the PLL configuration -----------------------------------------------*/
01173   if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
01174   {
01175     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
01176   }
01177   else
01178   {
01179     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
01180   }
01181   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
01182   RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
01183 #if defined(RCC_CR_PLL2ON)
01184   /* Get the PLL2 configuration -----------------------------------------------*/
01185   if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
01186   {
01187     RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
01188   }
01189   else
01190   {
01191     RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
01192   }
01193   RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
01194   RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
01195 #endif /* RCC_CR_PLL2ON */
01196 }
01197
01198 /**
01199   * @brief  Get the RCC_ClkInitStruct according to the internal
01200   * RCC configuration registers.
01201   * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
01202   * contains the current clock configuration.
01203   * @param  pFLatency Pointer on the Flash Latency.
01204   * @retval None
01205   */
01206 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
01207 {
01208   /* Check the parameters */
01209   assert_param(RCC_ClkInitStruct != NULL);
01210   assert_param(pFLatency != NULL);
01211
01212   /* Set all possible values for the Clock type parameter --------------------*/
01213   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
01214
01215   /* Get the SYSCLK configuration --------------------------------------------*/
01216   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
01217
01218   /* Get the HCLK configuration ----------------------------------------------*/
01219   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
01220
01221   /* Get the APB1 configuration ----------------------------------------------*/
01222   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
01223
01224   /* Get the APB2 configuration ----------------------------------------------*/
01225   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
01226
01227 #if   defined(FLASH_ACR_LATENCY)
01228   /* Get the Flash Wait State (Latency) configuration ------------------------*/
01229   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
01230 #else
01231   /* For VALUE lines devices, only LATENCY_0 can be set*/
01232   *pFLatency = (uint32_t)FLASH_LATENCY_0;
01233 #endif
01234 }
01235
01236 /**
01237   * @brief This function handles the RCC CSS interrupt request.
01238   * @note This API should be called under the NMI_Handler().
01239   * @retval None
01240   */
01241 void HAL_RCC_NMI_IRQHandler(void)
01242 {
01243   /* Check RCC CSSF flag  */
01244   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
01245   {
01246     /* RCC Clock Security System interrupt user callback */
01247     HAL_RCC_CSSCallback();
01248
01249     /* Clear RCC CSS pending bit */
01250     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
01251   }
01252 }
01253
01254 /**
01255   * @brief  RCC Clock Security System interrupt callback
01256   * @retval none
01257   */
01258 __weak void HAL_RCC_CSSCallback(void)
01259 {
01260   /* NOTE : This function Should not be modified, when the callback is needed,
01261     the HAL_RCC_CSSCallback could be implemented in the user file
01262     */
01263 }
01264
01265 /**
01266   * @}
01267   */
01268
01269 /**
01270   * @}
01271   */
01272
01273 #endif /* HAL_RCC_MODULE_ENABLED */
01274 /**
01275   * @}
01276   */
01277
01278 /**
01279   * @}
01280   */
01281
01282 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rcc.h Source File

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stm32f1xx_hal_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_rcc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of RCC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_RCC_H
00040 #define __STM32F1xx_HAL_RCC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RCC
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058
00059 /** @defgroup RCC_Exported_Types RCC Exported Types
00060   * @{
00061   */
00062
00063 /**
00064   * @brief  RCC PLL configuration structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t PLLState;      /*!< PLLState: The new state of the PLL.
00069                               This parameter can be a value of @ref RCC_PLL_Config */
00070
00071   uint32_t PLLSource;     /*!< PLLSource: PLL entry clock source.
00072                               This parameter must be a value of @ref RCC_PLL_Clock_Source */
00073
00074   uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
00075                               This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
00076 } RCC_PLLInitTypeDef;
00077
00078 /**
00079   * @brief  RCC System, AHB and APB busses clock configuration structure definition
00080   */
00081 typedef struct
00082 {
00083   uint32_t ClockType;             /*!< The clock to be configured.
00084                                        This parameter can be a value of @ref RCC_System_Clock_Type */
00085
00086   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
00087                                        This parameter can be a value of @ref RCC_System_Clock_Source */
00088
00089   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00090                                        This parameter can be a value of @ref RCC_AHB_Clock_Source */
00091
00092   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00093                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00094
00095   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00096                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
00097 } RCC_ClkInitTypeDef;
00098
00099 /**
00100   * @}
00101   */
00102
00103 /* Exported constants --------------------------------------------------------*/
00104 /** @defgroup RCC_Exported_Constants RCC Exported Constants
00105   * @{
00106   */
00107
00108 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
00109   * @{
00110   */
00111
00112 #define RCC_PLLSOURCE_HSI_DIV2      0x00000000U     /*!< HSI clock divided by 2 selected as PLL entry clock source */
00113 #define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC            /*!< HSE clock selected as PLL entry clock source */
00114
00115 /**
00116   * @}
00117   */
00118
00119 /** @defgroup RCC_Oscillator_Type Oscillator Type
00120   * @{
00121   */
00122 #define RCC_OSCILLATORTYPE_NONE            0x00000000U
00123 #define RCC_OSCILLATORTYPE_HSE             0x00000001U
00124 #define RCC_OSCILLATORTYPE_HSI             0x00000002U
00125 #define RCC_OSCILLATORTYPE_LSE             0x00000004U
00126 #define RCC_OSCILLATORTYPE_LSI             0x00000008U
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup RCC_HSE_Config HSE Config
00132   * @{
00133   */
00134 #define RCC_HSE_OFF                      0x00000000U                                /*!< HSE clock deactivation */
00135 #define RCC_HSE_ON                       RCC_CR_HSEON                               /*!< HSE clock activation */
00136 #define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
00137 /**
00138   * @}
00139   */
00140
00141 /** @defgroup RCC_LSE_Config LSE Config
00142   * @{
00143   */
00144 #define RCC_LSE_OFF                      0x00000000U                                    /*!< LSE clock deactivation */
00145 #define RCC_LSE_ON                       RCC_BDCR_LSEON                                 /*!< LSE clock activation */
00146 #define RCC_LSE_BYPASS                   ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
00147
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup RCC_HSI_Config HSI Config
00153   * @{
00154   */
00155 #define RCC_HSI_OFF                      0x00000000U                      /*!< HSI clock deactivation */
00156 #define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
00157
00158 #define RCC_HSICALIBRATION_DEFAULT       0x10U         /* Default HSI calibration trimming value */
00159
00160 /**
00161   * @}
00162   */
00163
00164 /** @defgroup RCC_LSI_Config LSI Config
00165   * @{
00166   */
00167 #define RCC_LSI_OFF                      0x00000000U              /*!< LSI clock deactivation */
00168 #define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
00169
00170 /**
00171   * @}
00172   */
00173
00174 /** @defgroup RCC_PLL_Config PLL Config
00175   * @{
00176   */
00177 #define RCC_PLL_NONE                      0x00000000U  /*!< PLL is not configured */
00178 #define RCC_PLL_OFF                       0x00000001U  /*!< PLL deactivation */
00179 #define RCC_PLL_ON                        0x00000002U  /*!< PLL activation */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /** @defgroup RCC_System_Clock_Type System Clock Type
00186   * @{
00187   */
00188 #define RCC_CLOCKTYPE_SYSCLK             0x00000001U /*!< SYSCLK to configure */
00189 #define RCC_CLOCKTYPE_HCLK               0x00000002U /*!< HCLK to configure */
00190 #define RCC_CLOCKTYPE_PCLK1              0x00000004U /*!< PCLK1 to configure */
00191 #define RCC_CLOCKTYPE_PCLK2              0x00000008U /*!< PCLK2 to configure */
00192
00193 /**
00194   * @}
00195   */
00196
00197 /** @defgroup RCC_System_Clock_Source System Clock Source
00198   * @{
00199   */
00200 #define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
00201 #define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
00202 #define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
00203
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
00209   * @{
00210   */
00211 #define RCC_SYSCLKSOURCE_STATUS_HSI      RCC_CFGR_SWS_HSI            /*!< HSI used as system clock */
00212 #define RCC_SYSCLKSOURCE_STATUS_HSE      RCC_CFGR_SWS_HSE            /*!< HSE used as system clock */
00213 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK   RCC_CFGR_SWS_PLL            /*!< PLL used as system clock */
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
00220   * @{
00221   */
00222 #define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
00223 #define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
00224 #define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
00225 #define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
00226 #define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
00227 #define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
00228 #define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
00229 #define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
00230 #define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
00231
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
00237   * @{
00238   */
00239 #define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
00240 #define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
00241 #define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
00242 #define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
00243 #define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
00244
00245 /**
00246   * @}
00247   */
00248
00249 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
00250   * @{
00251   */
00252 #define RCC_RTCCLKSOURCE_NO_CLK          0x00000000U                 /*!< No clock */
00253 #define RCC_RTCCLKSOURCE_LSE             RCC_BDCR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
00254 #define RCC_RTCCLKSOURCE_LSI             RCC_BDCR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
00255 #define RCC_RTCCLKSOURCE_HSE_DIV128      RCC_BDCR_RTCSEL_HSE                    /*!< HSE oscillator clock divided by 128 used as RTC clock */
00256 /**
00257   * @}
00258   */
00259
00260
00261 /** @defgroup RCC_MCO_Index MCO Index
00262   * @{
00263   */
00264 #define RCC_MCO1                         0x00000000U
00265 #define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
00266
00267 /**
00268   * @}
00269   */
00270
00271 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
00272   * @{
00273   */
00274 #define RCC_MCODIV_1                    0x00000000U
00275
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup RCC_Interrupt Interrupts
00281   * @{
00282   */
00283 #define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF)   /*!< LSI Ready Interrupt flag */
00284 #define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF)   /*!< LSE Ready Interrupt flag */
00285 #define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF)   /*!< HSI Ready Interrupt flag */
00286 #define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF)   /*!< HSE Ready Interrupt flag */
00287 #define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF)   /*!< PLL Ready Interrupt flag */
00288 #define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)      /*!< Clock Security System Interrupt flag */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup RCC_Flag Flags
00294   *        Elements values convention: XXXYYYYYb
00295   *           - YYYYY  : Flag position in the register
00296   *           - XXX  : Register index
00297   *                 - 001: CR register
00298   *                 - 010: BDCR register
00299   *                 - 011: CSR register
00300   * @{
00301   */
00302 /* Flags in the CR register */
00303 #define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
00304 #define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
00305 #define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
00306
00307 /* Flags in the CSR register */
00308 #define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos))   /*!< Internal Low Speed oscillator Ready */
00309 #define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))  /*!< PIN reset flag */
00310 #define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos))  /*!< POR/PDR reset flag */
00311 #define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))  /*!< Software Reset flag */
00312 #define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
00313 #define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
00314 #define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
00315
00316 /* Flags in the BDCR register */
00317 #define RCC_FLAG_LSERDY                  ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
00318
00319 /**
00320   * @}
00321   */
00322
00323 /**
00324   * @}
00325   */
00326
00327 /* Exported macro ------------------------------------------------------------*/
00328
00329 /** @defgroup RCC_Exported_Macros RCC Exported Macros
00330   * @{
00331   */
00332
00333 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
00334   * @brief  Enable or disable the AHB1 peripheral clock.
00335   * @note   After reset, the peripheral clock (used for registers read/write access)
00336   *         is disabled and the application software has to enable this clock before
00337   *         using it.
00338   * @{
00339   */
00340 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
00341                                         __IO uint32_t tmpreg; \
00342                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
00343                                         /* Delay after an RCC peripheral clock enabling */\
00344                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
00345                                         UNUSED(tmpreg); \
00346                                       } while(0U)
00347
00348 #define __HAL_RCC_SRAM_CLK_ENABLE()   do { \
00349                                         __IO uint32_t tmpreg; \
00350                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
00351                                         /* Delay after an RCC peripheral clock enabling */\
00352                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
00353                                         UNUSED(tmpreg); \
00354                                       } while(0U)
00355
00356 #define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
00357                                         __IO uint32_t tmpreg; \
00358                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
00359                                         /* Delay after an RCC peripheral clock enabling */\
00360                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
00361                                         UNUSED(tmpreg); \
00362                                       } while(0U)
00363
00364 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
00365                                         __IO uint32_t tmpreg; \
00366                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
00367                                         /* Delay after an RCC peripheral clock enabling */\
00368                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
00369                                         UNUSED(tmpreg); \
00370                                       } while(0U)
00371
00372 #define __HAL_RCC_DMA1_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
00373 #define __HAL_RCC_SRAM_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
00374 #define __HAL_RCC_FLITF_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
00375 #define __HAL_RCC_CRC_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
00376
00377 /**
00378   * @}
00379   */
00380
00381 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
00382   * @brief  Get the enable or disable status of the AHB peripheral clock.
00383   * @note   After reset, the peripheral clock (used for registers read/write access)
00384   *         is disabled and the application software has to enable this clock before
00385   *         using it.
00386   * @{
00387   */
00388
00389 #define __HAL_RCC_DMA1_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
00390 #define __HAL_RCC_DMA1_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
00391 #define __HAL_RCC_SRAM_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
00392 #define __HAL_RCC_SRAM_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
00393 #define __HAL_RCC_FLITF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
00394 #define __HAL_RCC_FLITF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
00395 #define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
00396 #define __HAL_RCC_CRC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
00397
00398 /**
00399   * @}
00400   */
00401
00402 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
00403   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
00404   * @note   After reset, the peripheral clock (used for registers read/write access)
00405   *         is disabled and the application software has to enable this clock before
00406   *         using it.
00407   * @{
00408   */
00409 #define __HAL_RCC_TIM2_CLK_ENABLE()   do { \
00410                                         __IO uint32_t tmpreg; \
00411                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
00412                                         /* Delay after an RCC peripheral clock enabling */\
00413                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
00414                                         UNUSED(tmpreg); \
00415                                       } while(0U)
00416
00417 #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
00418                                         __IO uint32_t tmpreg; \
00419                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
00420                                         /* Delay after an RCC peripheral clock enabling */\
00421                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
00422                                         UNUSED(tmpreg); \
00423                                       } while(0U)
00424
00425 #define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
00426                                         __IO uint32_t tmpreg; \
00427                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
00428                                         /* Delay after an RCC peripheral clock enabling */\
00429                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
00430                                         UNUSED(tmpreg); \
00431                                       } while(0U)
00432
00433 #define __HAL_RCC_USART2_CLK_ENABLE()   do { \
00434                                         __IO uint32_t tmpreg; \
00435                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
00436                                         /* Delay after an RCC peripheral clock enabling */\
00437                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
00438                                         UNUSED(tmpreg); \
00439                                       } while(0U)
00440
00441 #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
00442                                         __IO uint32_t tmpreg; \
00443                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
00444                                         /* Delay after an RCC peripheral clock enabling */\
00445                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
00446                                         UNUSED(tmpreg); \
00447                                       } while(0U)
00448
00449 #define __HAL_RCC_BKP_CLK_ENABLE()   do { \
00450                                         __IO uint32_t tmpreg; \
00451                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
00452                                         /* Delay after an RCC peripheral clock enabling */\
00453                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
00454                                         UNUSED(tmpreg); \
00455                                       } while(0U)
00456
00457 #define __HAL_RCC_PWR_CLK_ENABLE()   do { \
00458                                         __IO uint32_t tmpreg; \
00459                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
00460                                         /* Delay after an RCC peripheral clock enabling */\
00461                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
00462                                         UNUSED(tmpreg); \
00463                                       } while(0U)
00464
00465 #define __HAL_RCC_TIM2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
00466 #define __HAL_RCC_TIM3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
00467 #define __HAL_RCC_WWDG_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
00468 #define __HAL_RCC_USART2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
00469 #define __HAL_RCC_I2C1_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
00470
00471 #define __HAL_RCC_BKP_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
00472 #define __HAL_RCC_PWR_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
00473
00474 /**
00475   * @}
00476   */
00477
00478 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
00479   * @brief  Get the enable or disable status of the APB1 peripheral clock.
00480   * @note   After reset, the peripheral clock (used for registers read/write access)
00481   *         is disabled and the application software has to enable this clock before
00482   *         using it.
00483   * @{
00484   */
00485
00486 #define __HAL_RCC_TIM2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
00487 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
00488 #define __HAL_RCC_TIM3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
00489 #define __HAL_RCC_TIM3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
00490 #define __HAL_RCC_WWDG_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
00491 #define __HAL_RCC_WWDG_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
00492 #define __HAL_RCC_USART2_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
00493 #define __HAL_RCC_USART2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
00494 #define __HAL_RCC_I2C1_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
00495 #define __HAL_RCC_I2C1_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
00496 #define __HAL_RCC_BKP_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
00497 #define __HAL_RCC_BKP_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
00498 #define __HAL_RCC_PWR_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
00499 #define __HAL_RCC_PWR_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
00500
00501 /**
00502   * @}
00503   */
00504
00505 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
00506   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
00507   * @note   After reset, the peripheral clock (used for registers read/write access)
00508   *         is disabled and the application software has to enable this clock before
00509   *         using it.
00510   * @{
00511   */
00512 #define __HAL_RCC_AFIO_CLK_ENABLE()   do { \
00513                                         __IO uint32_t tmpreg; \
00514                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
00515                                         /* Delay after an RCC peripheral clock enabling */\
00516                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
00517                                         UNUSED(tmpreg); \
00518                                       } while(0U)
00519
00520 #define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
00521                                         __IO uint32_t tmpreg; \
00522                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
00523                                         /* Delay after an RCC peripheral clock enabling */\
00524                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
00525                                         UNUSED(tmpreg); \
00526                                       } while(0U)
00527
00528 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
00529                                         __IO uint32_t tmpreg; \
00530                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
00531                                         /* Delay after an RCC peripheral clock enabling */\
00532                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
00533                                         UNUSED(tmpreg); \
00534                                       } while(0U)
00535
00536 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
00537                                         __IO uint32_t tmpreg; \
00538                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
00539                                         /* Delay after an RCC peripheral clock enabling */\
00540                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
00541                                         UNUSED(tmpreg); \
00542                                       } while(0U)
00543
00544 #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
00545                                         __IO uint32_t tmpreg; \
00546                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
00547                                         /* Delay after an RCC peripheral clock enabling */\
00548                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
00549                                         UNUSED(tmpreg); \
00550                                       } while(0U)
00551
00552 #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
00553                                         __IO uint32_t tmpreg; \
00554                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
00555                                         /* Delay after an RCC peripheral clock enabling */\
00556                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
00557                                         UNUSED(tmpreg); \
00558                                       } while(0U)
00559
00560 #define __HAL_RCC_TIM1_CLK_ENABLE()   do { \
00561                                         __IO uint32_t tmpreg; \
00562                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
00563                                         /* Delay after an RCC peripheral clock enabling */\
00564                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
00565                                         UNUSED(tmpreg); \
00566                                       } while(0U)
00567
00568 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
00569                                         __IO uint32_t tmpreg; \
00570                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
00571                                         /* Delay after an RCC peripheral clock enabling */\
00572                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
00573                                         UNUSED(tmpreg); \
00574                                       } while(0U)
00575
00576 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
00577                                         __IO uint32_t tmpreg; \
00578                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
00579                                         /* Delay after an RCC peripheral clock enabling */\
00580                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
00581                                         UNUSED(tmpreg); \
00582                                       } while(0U)
00583
00584 #define __HAL_RCC_AFIO_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
00585 #define __HAL_RCC_GPIOA_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
00586 #define __HAL_RCC_GPIOB_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
00587 #define __HAL_RCC_GPIOC_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
00588 #define __HAL_RCC_GPIOD_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
00589 #define __HAL_RCC_ADC1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
00590
00591 #define __HAL_RCC_TIM1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
00592 #define __HAL_RCC_SPI1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
00593 #define __HAL_RCC_USART1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
00594
00595 /**
00596   * @}
00597   */
00598
00599 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
00600   * @brief  Get the enable or disable status of the APB2 peripheral clock.
00601   * @note   After reset, the peripheral clock (used for registers read/write access)
00602   *         is disabled and the application software has to enable this clock before
00603   *         using it.
00604   * @{
00605   */
00606
00607 #define __HAL_RCC_AFIO_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
00608 #define __HAL_RCC_AFIO_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
00609 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
00610 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
00611 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
00612 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
00613 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
00614 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
00615 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
00616 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
00617 #define __HAL_RCC_ADC1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
00618 #define __HAL_RCC_ADC1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
00619 #define __HAL_RCC_TIM1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
00620 #define __HAL_RCC_TIM1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
00621 #define __HAL_RCC_SPI1_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
00622 #define __HAL_RCC_SPI1_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
00623 #define __HAL_RCC_USART1_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
00624 #define __HAL_RCC_USART1_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
00625
00626 /**
00627   * @}
00628   */
00629
00630 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
00631   * @brief  Force or release APB1 peripheral reset.
00632   * @{
00633   */
00634 #define __HAL_RCC_APB1_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFFU)
00635 #define __HAL_RCC_TIM2_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
00636 #define __HAL_RCC_TIM3_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
00637 #define __HAL_RCC_WWDG_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
00638 #define __HAL_RCC_USART2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
00639 #define __HAL_RCC_I2C1_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
00640
00641 #define __HAL_RCC_BKP_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
00642 #define __HAL_RCC_PWR_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
00643
00644 #define __HAL_RCC_APB1_RELEASE_RESET()      (RCC->APB1RSTR = 0x00)
00645 #define __HAL_RCC_TIM2_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
00646 #define __HAL_RCC_TIM3_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
00647 #define __HAL_RCC_WWDG_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
00648 #define __HAL_RCC_USART2_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
00649 #define __HAL_RCC_I2C1_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
00650
00651 #define __HAL_RCC_BKP_RELEASE_RESET()        (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
00652 #define __HAL_RCC_PWR_RELEASE_RESET()        (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
00653
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
00659   * @brief  Force or release APB2 peripheral reset.
00660   * @{
00661   */
00662 #define __HAL_RCC_APB2_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFFU)
00663 #define __HAL_RCC_AFIO_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
00664 #define __HAL_RCC_GPIOA_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
00665 #define __HAL_RCC_GPIOB_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
00666 #define __HAL_RCC_GPIOC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
00667 #define __HAL_RCC_GPIOD_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
00668 #define __HAL_RCC_ADC1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
00669
00670 #define __HAL_RCC_TIM1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
00671 #define __HAL_RCC_SPI1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
00672 #define __HAL_RCC_USART1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
00673
00674 #define __HAL_RCC_APB2_RELEASE_RESET()      (RCC->APB2RSTR = 0x00)
00675 #define __HAL_RCC_AFIO_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
00676 #define __HAL_RCC_GPIOA_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
00677 #define __HAL_RCC_GPIOB_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
00678 #define __HAL_RCC_GPIOC_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
00679 #define __HAL_RCC_GPIOD_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
00680 #define __HAL_RCC_ADC1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
00681
00682 #define __HAL_RCC_TIM1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
00683 #define __HAL_RCC_SPI1_RELEASE_RESET()       (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
00684 #define __HAL_RCC_USART1_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
00685
00686 /**
00687   * @}
00688   */
00689
00690 /** @defgroup RCC_HSI_Configuration HSI Configuration
00691   * @{
00692   */
00693
00694 /** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
00695   * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
00696   * @note   HSI can not be stopped if it is used as system clock source. In this case,
00697   *         you have to select another source of the system clock then stop the HSI.
00698   * @note   After enabling the HSI, the application software should wait on HSIRDY
00699   *         flag to be set indicating that HSI clock is stable and can be used as
00700   *         system clock source.
00701   * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
00702   *         clock cycles.
00703   */
00704 #define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
00705 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
00706
00707 /** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
00708   * @note   The calibration is used to compensate for the variations in voltage
00709   *         and temperature that influence the frequency of the internal HSI RC.
00710   * @param  _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
00711   *         (default is RCC_HSICALIBRATION_DEFAULT).
00712   *         This parameter must be a number between 0 and 0x1F.
00713   */
00714 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
00715           (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
00716
00717 /**
00718   * @}
00719   */
00720
00721 /** @defgroup RCC_LSI_Configuration  LSI Configuration
00722   * @{
00723   */
00724
00725 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
00726   * @note   After enabling the LSI, the application software should wait on
00727   *         LSIRDY flag to be set indicating that LSI clock is stable and can
00728   *         be used to clock the IWDG and/or the RTC.
00729   */
00730 #define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
00731
00732 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
00733   * @note   LSI can not be disabled if the IWDG is running.
00734   * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
00735   *         clock cycles.
00736   */
00737 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
00738
00739 /**
00740   * @}
00741   */
00742
00743 /** @defgroup RCC_HSE_Configuration HSE Configuration
00744   * @{
00745   */
00746
00747 /**
00748   * @brief  Macro to configure the External High Speed oscillator (HSE).
00749   * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
00750   *         supported by this macro. User should request a transition to HSE Off
00751   *         first and then HSE On or HSE Bypass.
00752   * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
00753   *         software should wait on HSERDY flag to be set indicating that HSE clock
00754   *         is stable and can be used to clock the PLL and/or system clock.
00755   * @note   HSE state can not be changed if it is used directly or through the
00756   *         PLL as system clock. In this case, you have to select another source
00757   *         of the system clock then change the HSE state (ex. disable it).
00758   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
00759   * @note   This function reset the CSSON bit, so if the clock security system(CSS)
00760   *         was previously enabled you have to enable it again after calling this
00761   *         function.
00762   * @param  __STATE__ specifies the new state of the HSE.
00763   *          This parameter can be one of the following values:
00764   *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
00765   *                              6 HSE oscillator clock cycles.
00766   *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
00767   *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
00768   */
00769 #define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
00770                     do{                                                     \
00771                       if ((__STATE__) == RCC_HSE_ON)                        \
00772                       {                                                     \
00773                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
00774                       }                                                     \
00775                       else if ((__STATE__) == RCC_HSE_OFF)                  \
00776                       {                                                     \
00777                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
00778                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
00779                       }                                                     \
00780                       else if ((__STATE__) == RCC_HSE_BYPASS)               \
00781                       {                                                     \
00782                         SET_BIT(RCC->CR, RCC_CR_HSEBYP);                    \
00783                         SET_BIT(RCC->CR, RCC_CR_HSEON);                     \
00784                       }                                                     \
00785                       else                                                  \
00786                       {                                                     \
00787                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
00788                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
00789                       }                                                     \
00790                     }while(0U)
00791
00792 /**
00793   * @}
00794   */
00795
00796 /** @defgroup RCC_LSE_Configuration LSE Configuration
00797   * @{
00798   */
00799
00800 /**
00801   * @brief  Macro to configure the External Low Speed oscillator (LSE).
00802   * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
00803   * @note   As the LSE is in the Backup domain and write access is denied to
00804   *         this domain after reset, you have to enable write access using
00805   *         @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
00806   *         (to be done once after reset).
00807   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
00808   *         software should wait on LSERDY flag to be set indicating that LSE clock
00809   *         is stable and can be used to clock the RTC.
00810   * @param  __STATE__ specifies the new state of the LSE.
00811   *         This parameter can be one of the following values:
00812   *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
00813   *                              6 LSE oscillator clock cycles.
00814   *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
00815   *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
00816   */
00817 #define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
00818                     do{                                                     \
00819                       if ((__STATE__) == RCC_LSE_ON)                        \
00820                       {                                                     \
00821                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
00822                       }                                                     \
00823                       else if ((__STATE__) == RCC_LSE_OFF)                  \
00824                       {                                                     \
00825                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
00826                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
00827                       }                                                     \
00828                       else if ((__STATE__) == RCC_LSE_BYPASS)               \
00829                       {                                                     \
00830                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                  \
00831                         SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);                   \
00832                       }                                                     \
00833                       else                                                  \
00834                       {                                                     \
00835                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);                 \
00836                         CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);                \
00837                       }                                                     \
00838                     }while(0U)
00839
00840 /**
00841   * @}
00842   */
00843
00844 /** @defgroup RCC_PLL_Configuration PLL Configuration
00845   * @{
00846   */
00847
00848 /** @brief Macro to enable the main PLL.
00849   * @note   After enabling the main PLL, the application software should wait on
00850   *         PLLRDY flag to be set indicating that PLL clock is stable and can
00851   *         be used as system clock source.
00852   * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
00853   */
00854 #define __HAL_RCC_PLL_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
00855
00856 /** @brief Macro to disable the main PLL.
00857   * @note   The main PLL can not be disabled if it is used as system clock source
00858   */
00859 #define __HAL_RCC_PLL_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
00860
00861 /** @brief Macro to configure the main PLL clock source and multiplication factors.
00862   * @note   This function must be used only when the main PLL is disabled.
00863   *
00864   * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
00865   *          This parameter can be one of the following values:
00866   *            @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
00867   *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
00868   * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
00869   *          This parameter can be one of the following values:
00870   *             @arg @ref RCC_PLL_MUL4   PLLVCO = PLL clock entry x 4
00871   *             @arg @ref RCC_PLL_MUL6   PLLVCO = PLL clock entry x 6
00872   @if STM32F105xC
00873   *             @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
00874   @elseif STM32F107xC
00875   *             @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
00876   @else
00877   *             @arg @ref RCC_PLL_MUL2   PLLVCO = PLL clock entry x 2
00878   *             @arg @ref RCC_PLL_MUL3   PLLVCO = PLL clock entry x 3
00879   *             @arg @ref RCC_PLL_MUL10  PLLVCO = PLL clock entry x 10
00880   *             @arg @ref RCC_PLL_MUL11  PLLVCO = PLL clock entry x 11
00881   *             @arg @ref RCC_PLL_MUL12  PLLVCO = PLL clock entry x 12
00882   *             @arg @ref RCC_PLL_MUL13  PLLVCO = PLL clock entry x 13
00883   *             @arg @ref RCC_PLL_MUL14  PLLVCO = PLL clock entry x 14
00884   *             @arg @ref RCC_PLL_MUL15  PLLVCO = PLL clock entry x 15
00885   *             @arg @ref RCC_PLL_MUL16  PLLVCO = PLL clock entry x 16
00886   @endif
00887   *             @arg @ref RCC_PLL_MUL8   PLLVCO = PLL clock entry x 8
00888   *             @arg @ref RCC_PLL_MUL9   PLLVCO = PLL clock entry x 9
00889   *
00890   */
00891 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
00892           MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
00893
00894 /** @brief  Get oscillator clock selected as PLL input clock
00895   * @retval The clock source used for PLL entry. The returned value can be one
00896   *         of the following:
00897   *             @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
00898   *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
00899   */
00900 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
00901
00902 /**
00903   * @}
00904   */
00905
00906 /** @defgroup RCC_Get_Clock_source Get Clock source
00907   * @{
00908   */
00909
00910 /**
00911   * @brief  Macro to configure the system clock source.
00912   * @param  __SYSCLKSOURCE__ specifies the system clock source.
00913   *          This parameter can be one of the following values:
00914   *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
00915   *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
00916   *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
00917   */
00918 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
00919                   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
00920
00921 /** @brief  Macro to get the clock source used as system clock.
00922   * @retval The clock source used as system clock. The returned value can be one
00923   *         of the following:
00924   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
00925   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
00926   *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
00927   */
00928 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
00929
00930 /**
00931   * @}
00932   */
00933
00934 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
00935   * @{
00936   */
00937
00938 #if   defined(RCC_CFGR_MCO_3)
00939 /** @brief  Macro to configure the MCO clock.
00940   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
00941   *         This parameter can be one of the following values:
00942   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
00943   *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System clock (SYSCLK) selected as MCO clock
00944   *            @arg @ref RCC_MCO1SOURCE_HSI          HSI selected as MCO clock
00945   *            @arg @ref RCC_MCO1SOURCE_HSE          HSE selected as MCO clock
00946   *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO clock
00947   *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected by 2 selected as MCO clock
00948   *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
00949   *            @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1  external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
00950   *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected (for Ethernet) as MCO clock
00951   * @param  __MCODIV__ specifies the MCO clock prescaler.
00952   *         This parameter can be one of the following values:
00953   *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
00954   */
00955 #else
00956 /** @brief  Macro to configure the MCO clock.
00957   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
00958   *         This parameter can be one of the following values:
00959   *            @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
00960   *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System clock (SYSCLK) selected as MCO clock
00961   *            @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
00962   *            @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
00963   *            @arg @ref RCC_MCO1SOURCE_PLLCLK  PLL clock divided by 2 selected as MCO clock
00964   * @param  __MCODIV__ specifies the MCO clock prescaler.
00965   *         This parameter can be one of the following values:
00966   *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
00967   */
00968 #endif
00969
00970 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
00971                  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
00972
00973
00974 /**
00975   * @}
00976   */
00977
00978   /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
00979   * @{
00980   */
00981
00982 /** @brief Macro to configure the RTC clock (RTCCLK).
00983   * @note   As the RTC clock configuration bits are in the Backup domain and write
00984   *         access is denied to this domain after reset, you have to enable write
00985   *         access using the Power Backup Access macro before to configure
00986   *         the RTC clock source (to be done once after reset).
00987   * @note   Once the RTC clock is configured it can't be changed unless the
00988   *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
00989   *         a Power On Reset (POR).
00990   *
00991   * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
00992   *          This parameter can be one of the following values:
00993   *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
00994   *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
00995   *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
00996   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
00997   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
00998   *         work in STOP and STANDBY modes, and can be used as wakeup source.
00999   *         However, when the HSE clock is used as RTC clock source, the RTC
01000   *         cannot be used in STOP and STANDBY modes.
01001   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
01002   *         RTC clock source).
01003   */
01004 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
01005
01006 /** @brief Macro to get the RTC clock source.
01007   * @retval The clock source can be one of the following values:
01008   *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
01009   *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
01010   *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
01011   *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
01012   */
01013 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
01014
01015 /** @brief Macro to enable the the RTC clock.
01016   * @note   These macros must be used only after the RTC clock source was selected.
01017   */
01018 #define __HAL_RCC_RTC_ENABLE()          (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
01019
01020 /** @brief Macro to disable the the RTC clock.
01021   * @note  These macros must be used only after the RTC clock source was selected.
01022   */
01023 #define __HAL_RCC_RTC_DISABLE()         (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
01024
01025 /** @brief  Macro to force the Backup domain reset.
01026   * @note   This function resets the RTC peripheral (including the backup registers)
01027   *         and the RTC clock source selection in RCC_BDCR register.
01028   */
01029 #define __HAL_RCC_BACKUPRESET_FORCE()   (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
01030
01031 /** @brief  Macros to release the Backup domain reset.
01032   */
01033 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
01034
01035 /**
01036   * @}
01037   */
01038
01039 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
01040   * @brief macros to manage the specified RCC Flags and interrupts.
01041   * @{
01042   */
01043
01044 /** @brief Enable RCC interrupt.
01045   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
01046   *          This parameter can be any combination of the following values:
01047   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
01048   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
01049   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
01050   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
01051   *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
01052   @if STM32F105xx
01053   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
01054   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
01055   @elsif STM32F107xx
01056   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
01057   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
01058   @endif
01059   */
01060 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
01061
01062 /** @brief Disable RCC interrupt.
01063   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
01064   *          This parameter can be any combination of the following values:
01065   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
01066   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
01067   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
01068   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
01069   *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
01070   @if STM32F105xx
01071   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
01072   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
01073   @elsif STM32F107xx
01074   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
01075   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
01076   @endif
01077   */
01078 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
01079
01080 /** @brief Clear the RCC's interrupt pending bits.
01081   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
01082   *          This parameter can be any combination of the following values:
01083   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
01084   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
01085   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
01086   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
01087   *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
01088   @if STM32F105xx
01089   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
01090   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
01091   @elsif STM32F107xx
01092   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
01093   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
01094   @endif
01095   *            @arg @ref RCC_IT_CSS Clock Security System interrupt
01096   */
01097 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
01098
01099 /** @brief Check the RCC's interrupt has occurred or not.
01100   * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
01101   *          This parameter can be one of the following values:
01102   *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
01103   *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
01104   *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
01105   *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
01106   *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
01107   @if STM32F105xx
01108   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
01109   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
01110   @elsif STM32F107xx
01111   *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
01112   *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
01113   @endif
01114   *            @arg @ref RCC_IT_CSS Clock Security System interrupt
01115   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
01116   */
01117 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
01118
01119 /** @brief Set RMVF bit to clear the reset flags.
01120   *         The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
01121   *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
01122   */
01123 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
01124
01125 /** @brief  Check RCC flag is set or not.
01126   * @param  __FLAG__ specifies the flag to check.
01127   *          This parameter can be one of the following values:
01128   *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
01129   *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
01130   *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
01131   @if STM32F105xx
01132   *            @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
01133   *            @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
01134   @elsif STM32F107xx
01135   *            @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
01136   *            @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
01137   @endif
01138   *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
01139   *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
01140   *            @arg @ref RCC_FLAG_PINRST  Pin reset.
01141   *            @arg @ref RCC_FLAG_PORRST  POR/PDR reset.
01142   *            @arg @ref RCC_FLAG_SFTRST  Software reset.
01143   *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
01144   *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
01145   *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
01146   * @retval The new state of __FLAG__ (TRUE or FALSE).
01147   */
01148 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)?   RCC->CR   : \
01149                                       ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
01150                                                                               RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
01151
01152 /**
01153   * @}
01154   */
01155
01156 /**
01157   * @}
01158   */
01159
01160 /* Include RCC HAL Extension module */
01161 #include "stm32f1xx_hal_rcc_ex.h"
01162
01163 /* Exported functions --------------------------------------------------------*/
01164 /** @addtogroup RCC_Exported_Functions
01165   * @{
01166   */
01167
01168 /** @addtogroup RCC_Exported_Functions_Group1
01169   * @{
01170   */
01171
01172 /* Initialization and de-initialization functions  ******************************/
01173 void              HAL_RCC_DeInit(void);
01174 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
01175 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
01176
01177 /**
01178   * @}
01179   */
01180
01181 /** @addtogroup RCC_Exported_Functions_Group2
01182   * @{
01183   */
01184
01185 /* Peripheral Control functions  ************************************************/
01186 void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
01187 void              HAL_RCC_EnableCSS(void);
01188 void              HAL_RCC_DisableCSS(void);
01189 uint32_t          HAL_RCC_GetSysClockFreq(void);
01190 uint32_t          HAL_RCC_GetHCLKFreq(void);
01191 uint32_t          HAL_RCC_GetPCLK1Freq(void);
01192 uint32_t          HAL_RCC_GetPCLK2Freq(void);
01193 void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
01194 void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
01195
01196 /* CSS NMI IRQ handler */
01197 void              HAL_RCC_NMI_IRQHandler(void);
01198
01199 /* User Callbacks in non blocking mode (IT mode) */
01200 void              HAL_RCC_CSSCallback(void);
01201
01202 /**
01203   * @}
01204   */
01205
01206 /**
01207   * @}
01208   */
01209
01210 /** @addtogroup RCC_Private_Constants
01211   * @{
01212   */
01213
01214 /** @defgroup RCC_Timeout RCC Timeout
01215   * @{
01216   */
01217
01218 /* Disable Backup domain write protection state change timeout */
01219 #define RCC_DBP_TIMEOUT_VALUE          100U    /* 100 ms */
01220 /* LSE state change timeout */
01221 #define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT
01222 #define CLOCKSWITCH_TIMEOUT_VALUE      5000    /* 5 s    */
01223 #define HSE_TIMEOUT_VALUE              HSE_STARTUP_TIMEOUT
01224 #define HSI_TIMEOUT_VALUE              2U      /* 2 ms (minimum Tick + 1) */
01225 #define LSI_TIMEOUT_VALUE              2U      /* 2 ms (minimum Tick + 1) */
01226 #define PLL_TIMEOUT_VALUE              2U      /* 2 ms (minimum Tick + 1) */
01227
01228 /**
01229   * @}
01230   */
01231
01232 /** @defgroup RCC_Register_Offset Register offsets
01233   * @{
01234   */
01235 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
01236 #define RCC_CR_OFFSET             0x00U
01237 #define RCC_CFGR_OFFSET           0x04U
01238 #define RCC_CIR_OFFSET            0x08U
01239 #define RCC_BDCR_OFFSET           0x20U
01240 #define RCC_CSR_OFFSET            0x24U
01241
01242 /**
01243   * @}
01244   */
01245
01246 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
01247   * @brief RCC registers bit address in the alias region
01248   * @{
01249   */
01250 #define RCC_CR_OFFSET_BB          (RCC_OFFSET + RCC_CR_OFFSET)
01251 #define RCC_CFGR_OFFSET_BB        (RCC_OFFSET + RCC_CFGR_OFFSET)
01252 #define RCC_CIR_OFFSET_BB         (RCC_OFFSET + RCC_CIR_OFFSET)
01253 #define RCC_BDCR_OFFSET_BB        (RCC_OFFSET + RCC_BDCR_OFFSET)
01254 #define RCC_CSR_OFFSET_BB         (RCC_OFFSET + RCC_CSR_OFFSET)
01255
01256 /* --- CR Register ---*/
01257 /* Alias word address of HSION bit */
01258 #define RCC_HSION_BIT_NUMBER      RCC_CR_HSION_Pos
01259 #define RCC_CR_HSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
01260 /* Alias word address of HSEON bit */
01261 #define RCC_HSEON_BIT_NUMBER      RCC_CR_HSEON_Pos
01262 #define RCC_CR_HSEON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
01263 /* Alias word address of CSSON bit */
01264 #define RCC_CSSON_BIT_NUMBER      RCC_CR_CSSON_Pos
01265 #define RCC_CR_CSSON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
01266 /* Alias word address of PLLON bit */
01267 #define RCC_PLLON_BIT_NUMBER      RCC_CR_PLLON_Pos
01268 #define RCC_CR_PLLON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
01269
01270 /* --- CSR Register ---*/
01271 /* Alias word address of LSION bit */
01272 #define RCC_LSION_BIT_NUMBER      RCC_CSR_LSION_Pos
01273 #define RCC_CSR_LSION_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
01274
01275 /* Alias word address of RMVF bit */
01276 #define RCC_RMVF_BIT_NUMBER       RCC_CSR_RMVF_Pos
01277 #define RCC_CSR_RMVF_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
01278
01279 /* --- BDCR Registers ---*/
01280 /* Alias word address of LSEON bit */
01281 #define RCC_LSEON_BIT_NUMBER      RCC_BDCR_LSEON_Pos
01282 #define RCC_BDCR_LSEON_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
01283
01284 /* Alias word address of LSEON bit */
01285 #define RCC_LSEBYP_BIT_NUMBER     RCC_BDCR_LSEBYP_Pos
01286 #define RCC_BDCR_LSEBYP_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
01287
01288 /* Alias word address of RTCEN bit */
01289 #define RCC_RTCEN_BIT_NUMBER      RCC_BDCR_RTCEN_Pos
01290 #define RCC_BDCR_RTCEN_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
01291
01292 /* Alias word address of BDRST bit */
01293 #define RCC_BDRST_BIT_NUMBER      RCC_BDCR_BDRST_Pos
01294 #define RCC_BDCR_BDRST_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
01295
01296 /**
01297   * @}
01298   */
01299
01300 /* CR register byte 2 (Bits[23:16]) base address */
01301 #define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
01302
01303 /* CIR register byte 1 (Bits[15:8]) base address */
01304 #define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
01305
01306 /* CIR register byte 2 (Bits[23:16]) base address */
01307 #define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
01308
01309 /* Defines used for Flags */
01310 #define CR_REG_INDEX                     ((uint8_t)1)
01311 #define BDCR_REG_INDEX                   ((uint8_t)2)
01312 #define CSR_REG_INDEX                    ((uint8_t)3)
01313
01314 #define RCC_FLAG_MASK                    ((uint8_t)0x1F)
01315
01316 /**
01317   * @}
01318   */
01319
01320 /** @addtogroup RCC_Private_Macros
01321   * @{
01322   */
01323 /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
01324   * @{
01325   */
01326 #define __HAL_RCC_SYSCFG_CLK_DISABLE    __HAL_RCC_AFIO_CLK_DISABLE
01327 #define __HAL_RCC_SYSCFG_CLK_ENABLE     __HAL_RCC_AFIO_CLK_ENABLE
01328 #define __HAL_RCC_SYSCFG_FORCE_RESET    __HAL_RCC_AFIO_FORCE_RESET
01329 #define __HAL_RCC_SYSCFG_RELEASE_RESET  __HAL_RCC_AFIO_RELEASE_RESET
01330 /**
01331   * @}
01332   */
01333
01334 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
01335                                       ((__SOURCE__) == RCC_PLLSOURCE_HSE))
01336 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
01337                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
01338                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
01339                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
01340                                                (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
01341 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
01342                              ((__HSE__) == RCC_HSE_BYPASS))
01343 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
01344                              ((__LSE__) == RCC_LSE_BYPASS))
01345 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
01346 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
01347 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
01348 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
01349                              ((__PLL__) == RCC_PLL_ON))
01350
01351 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
01352                                (((CLK) & RCC_CLOCKTYPE_HCLK)   == RCC_CLOCKTYPE_HCLK)   || \
01353                                (((CLK) & RCC_CLOCKTYPE_PCLK1)  == RCC_CLOCKTYPE_PCLK1)  || \
01354                                (((CLK) & RCC_CLOCKTYPE_PCLK2)  == RCC_CLOCKTYPE_PCLK2))
01355 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
01356                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
01357                                          ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
01358 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
01359                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
01360                                                 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
01361 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
01362                                ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
01363                                ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
01364                                ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
01365                                ((__HCLK__) == RCC_SYSCLK_DIV512))
01366 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
01367                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
01368                                ((__PCLK__) == RCC_HCLK_DIV16))
01369 #define IS_RCC_MCO(__MCO__)  ((__MCO__) == RCC_MCO)
01370 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
01371 #define IS_RCC_RTCCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
01372                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
01373                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
01374                                           ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
01375
01376 /**
01377   * @}
01378   */
01379
01380 /**
01381   * @}
01382   */
01383
01384 /**
01385   * @}
01386   */
01387
01388 #ifdef __cplusplus
01389 }
01390 #endif
01391
01392 #endif /* __STM32F1xx_HAL_RCC_H */
01393
01394 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01395
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rcc_ex.c Source File

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stm32f1xx_hal_rcc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_rcc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Extended RCC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities RCC extension peripheral:
00010   *           + Extended Peripheral Control functions
00011   *
00012   ******************************************************************************
00013   * @attention
00014   *
00015   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00016   *
00017   * Redistribution and use in source and binary forms, with or without modification,
00018   * are permitted provided that the following conditions are met:
00019   *   1. Redistributions of source code must retain the above copyright notice,
00020   *      this list of conditions and the following disclaimer.
00021   *   2. Redistributions in binary form must reproduce the above copyright notice,
00022   *      this list of conditions and the following disclaimer in the documentation
00023   *      and/or other materials provided with the distribution.
00024   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00025   *      may be used to endorse or promote products derived from this software
00026   *      without specific prior written permission.
00027   *
00028   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00029   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00030   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00031   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00032   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00033   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00034   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00036   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00037   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00038   *
00039   ******************************************************************************
00040   */
00041
00042 /* Includes ------------------------------------------------------------------*/
00043 #include "stm32f1xx_hal.h"
00044
00045 /** @addtogroup STM32F1xx_HAL_Driver
00046   * @{
00047   */
00048
00049 #ifdef HAL_RCC_MODULE_ENABLED
00050
00051 /** @defgroup RCCEx RCCEx
00052   * @brief RCC Extension HAL module driver.
00053   * @{
00054   */
00055
00056 /* Private typedef -----------------------------------------------------------*/
00057 /* Private define ------------------------------------------------------------*/
00058 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
00059   * @{
00060   */
00061 /**
00062   * @}
00063   */
00064
00065 /* Private macro -------------------------------------------------------------*/
00066 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
00067   * @{
00068   */
00069 /**
00070   * @}
00071   */
00072
00073 /* Private variables ---------------------------------------------------------*/
00074 /* Private function prototypes -----------------------------------------------*/
00075 /* Private functions ---------------------------------------------------------*/
00076
00077 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
00078   * @{
00079   */
00080
00081 /** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
00082   *  @brief  Extended Peripheral Control functions
00083   *
00084 @verbatim
00085  ===============================================================================
00086                 ##### Extended Peripheral Control functions  #####
00087  ===============================================================================
00088     [..]
00089     This subsection provides a set of functions allowing to control the RCC Clocks
00090     frequencies.
00091     [..]
00092     (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
00093         select the RTC clock source; in this case the Backup domain will be reset in
00094         order to modify the RTC Clock source, as consequence RTC registers (including
00095         the backup registers) are set to their reset values.
00096
00097 @endverbatim
00098   * @{
00099   */
00100
00101 /**
00102   * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
00103   *         RCC_PeriphCLKInitTypeDef.
00104   * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
00105   *         contains the configuration information for the Extended Peripherals clocks(RTC clock).
00106   *
00107   * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
00108   *         the RTC clock source; in this case the Backup domain will be reset in
00109   *         order to modify the RTC Clock source, as consequence RTC registers (including
00110   *         the backup registers) are set to their reset values.
00111   *
00112   * @note   In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
00113   *         one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
00114   *         manually disable it.
00115   *
00116   * @retval HAL status
00117   */
00118 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00119 {
00120   uint32_t tickstart = 0U, temp_reg = 0U;
00121 #if defined(STM32F105xC) || defined(STM32F107xC)
00122   uint32_t  pllactive = 0U;
00123 #endif /* STM32F105xC || STM32F107xC */
00124
00125   /* Check the parameters */
00126   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
00127
00128   /*------------------------------- RTC/LCD Configuration ------------------------*/
00129   if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
00130   {
00131     /* check for RTC Parameters used to output RTCCLK */
00132     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
00133
00134     FlagStatus       pwrclkchanged = RESET;
00135
00136     /* As soon as function is called to change RTC clock source, activation of the
00137        power domain is done. */
00138     /* Requires to enable write access to Backup Domain of necessary */
00139     if(__HAL_RCC_PWR_IS_CLK_DISABLED())
00140     {
00141     __HAL_RCC_PWR_CLK_ENABLE();
00142       pwrclkchanged = SET;
00143     }
00144
00145     if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
00146     {
00147       /* Enable write access to Backup domain */
00148       SET_BIT(PWR->CR, PWR_CR_DBP);
00149
00150       /* Wait for Backup domain Write protection disable */
00151       tickstart = HAL_GetTick();
00152
00153       while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
00154       {
00155         if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
00156         {
00157           return HAL_TIMEOUT;
00158         }
00159       }
00160     }
00161
00162     /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
00163     temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
00164     if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
00165     {
00166       /* Store the content of BDCR register before the reset of Backup Domain */
00167       temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
00168       /* RTC Clock selection can be changed only if the Backup Domain is reset */
00169       __HAL_RCC_BACKUPRESET_FORCE();
00170       __HAL_RCC_BACKUPRESET_RELEASE();
00171       /* Restore the Content of BDCR register */
00172       RCC->BDCR = temp_reg;
00173
00174       /* Wait for LSERDY if LSE was enabled */
00175       if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
00176       {
00177         /* Get Start Tick */
00178         tickstart = HAL_GetTick();
00179
00180         /* Wait till LSE is ready */
00181         while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
00182         {
00183           if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
00184           {
00185             return HAL_TIMEOUT;
00186           }
00187         }
00188       }
00189     }
00190     __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
00191
00192     /* Require to disable power clock if necessary */
00193     if(pwrclkchanged == SET)
00194     {
00195       __HAL_RCC_PWR_CLK_DISABLE();
00196     }
00197   }
00198
00199   /*------------------------------ ADC clock Configuration ------------------*/
00200   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
00201   {
00202     /* Check the parameters */
00203     assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
00204
00205     /* Configure the ADC clock source */
00206     __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
00207   }
00208
00209 #if defined(STM32F105xC) || defined(STM32F107xC)
00210   /*------------------------------ I2S2 Configuration ------------------------*/
00211   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
00212   {
00213     /* Check the parameters */
00214     assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
00215
00216     /* Configure the I2S2 clock source */
00217     __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
00218   }
00219
00220   /*------------------------------ I2S3 Configuration ------------------------*/
00221   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
00222   {
00223     /* Check the parameters */
00224     assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
00225
00226     /* Configure the I2S3 clock source */
00227     __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
00228   }
00229
00230   /*------------------------------ PLL I2S Configuration ----------------------*/
00231   /* Check that PLLI2S need to be enabled */
00232   if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
00233   {
00234     /* Update flag to indicate that PLL I2S should be active */
00235     pllactive = 1;
00236   }
00237
00238   /* Check if PLL I2S need to be enabled */
00239   if (pllactive == 1)
00240   {
00241     /* Enable PLL I2S only if not active */
00242     if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
00243     {
00244       /* Check the parameters */
00245       assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
00246       assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
00247
00248       /* Prediv2 can be written only when the PLL2 is disabled. */
00249       /* Return an error only if new value is different from the programmed value */
00250       if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
00251         (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
00252       {
00253         return HAL_ERROR;
00254       }
00255
00256       /* Configure the HSE prediv2 factor --------------------------------*/
00257       __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
00258
00259       /* Configure the main PLLI2S multiplication factors. */
00260       __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
00261
00262       /* Enable the main PLLI2S. */
00263       __HAL_RCC_PLLI2S_ENABLE();
00264
00265       /* Get Start Tick*/
00266       tickstart = HAL_GetTick();
00267
00268       /* Wait till PLLI2S is ready */
00269       while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
00270       {
00271         if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
00272         {
00273           return HAL_TIMEOUT;
00274         }
00275       }
00276     }
00277     else
00278     {
00279       /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
00280       if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
00281       {
00282           return HAL_ERROR;
00283       }
00284     }
00285   }
00286 #endif /* STM32F105xC || STM32F107xC */
00287
00288 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
00289  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
00290  || defined(STM32F105xC) || defined(STM32F107xC)
00291   /*------------------------------ USB clock Configuration ------------------*/
00292   if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
00293   {
00294     /* Check the parameters */
00295     assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
00296
00297     /* Configure the USB clock source */
00298     __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
00299   }
00300 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00301
00302   return HAL_OK;
00303 }
00304
00305 /**
00306   * @brief  Get the PeriphClkInit according to the internal
00307   * RCC configuration registers.
00308   * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
00309   *         returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
00310   * @retval None
00311   */
00312 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
00313 {
00314   uint32_t srcclk = 0U;
00315
00316   /* Set all possible values for the extended clock type parameter------------*/
00317   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
00318
00319   /* Get the RTC configuration -----------------------------------------------*/
00320   srcclk = __HAL_RCC_GET_RTC_SOURCE();
00321   /* Source clock is LSE or LSI*/
00322   PeriphClkInit->RTCClockSelection = srcclk;
00323
00324   /* Get the ADC clock configuration -----------------------------------------*/
00325   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
00326   PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
00327
00328 #if defined(STM32F105xC) || defined(STM32F107xC)
00329   /* Get the I2S2 clock configuration -----------------------------------------*/
00330   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
00331   PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
00332
00333   /* Get the I2S3 clock configuration -----------------------------------------*/
00334   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
00335   PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
00336
00337 #endif /* STM32F105xC || STM32F107xC */
00338
00339 #if defined(STM32F103xE) || defined(STM32F103xG)
00340   /* Get the I2S2 clock configuration -----------------------------------------*/
00341   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
00342   PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
00343
00344   /* Get the I2S3 clock configuration -----------------------------------------*/
00345   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
00346   PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
00347
00348 #endif /* STM32F103xE || STM32F103xG */
00349
00350 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
00351  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
00352  || defined(STM32F105xC) || defined(STM32F107xC)
00353   /* Get the USB clock configuration -----------------------------------------*/
00354   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
00355   PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
00356 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00357 }
00358
00359 /**
00360   * @brief  Returns the peripheral clock frequency
00361   * @note   Returns 0 if peripheral clock is unknown
00362   * @param  PeriphClk Peripheral clock identifier
00363   *         This parameter can be one of the following values:
00364   *            @arg @ref RCC_PERIPHCLK_RTC  RTC peripheral clock
00365   *            @arg @ref RCC_PERIPHCLK_ADC  ADC peripheral clock
00366   @if STM32F103xE
00367   *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
00368   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00369   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00370   @endif
00371   @if STM32F103xG
00372   *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
00373   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00374   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00375   *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
00376   @endif
00377   @if STM32F105xC
00378   *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
00379   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00380   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00381   *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
00382   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00383   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00384   *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
00385   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
00386   @endif
00387   @if STM32F107xC
00388   *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
00389   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00390   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00391   *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
00392   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00393   *            @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
00394   *            @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
00395   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
00396   @endif
00397   @if STM32F102xx
00398   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
00399   @endif
00400   @if STM32F103xx
00401   *            @arg @ref RCC_PERIPHCLK_USB  USB peripheral clock
00402   @endif
00403   * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
00404   */
00405 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
00406 {
00407 #if defined(STM32F105xC) || defined(STM32F107xC)
00408   const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
00409   const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
00410
00411   uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
00412   uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
00413 #endif /* STM32F105xC || STM32F107xC */
00414 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
00415     defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
00416   const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
00417   const uint8_t aPredivFactorTable[2] = {1, 2};
00418
00419   uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
00420 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
00421   uint32_t temp_reg = 0U, frequency = 0U;
00422
00423   /* Check the parameters */
00424   assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
00425
00426   switch (PeriphClk)
00427   {
00428 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
00429  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
00430  || defined(STM32F105xC) || defined(STM32F107xC)
00431   case RCC_PERIPHCLK_USB:
00432     {
00433       /* Get RCC configuration ------------------------------------------------------*/
00434       temp_reg = RCC->CFGR;
00435
00436       /* Check if PLL is enabled */
00437       if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
00438       {
00439         pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
00440         if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
00441         {
00442 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
00443  || defined(STM32F100xE)
00444           prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
00445 #else
00446           prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
00447 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
00448
00449 #if defined(STM32F105xC) || defined(STM32F107xC)
00450           if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
00451           {
00452             /* PLL2 selected as Prediv1 source */
00453             /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
00454             prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
00455             pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
00456             pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
00457           }
00458           else
00459           {
00460             /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
00461             pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
00462           }
00463
00464           /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
00465           /* In this case need to divide pllclk by 2 */
00466           if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
00467           {
00468               pllclk = pllclk / 2;
00469           }
00470 #else
00471           if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
00472           {
00473             /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
00474             pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
00475           }
00476 #endif /* STM32F105xC || STM32F107xC */
00477         }
00478         else
00479         {
00480           /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
00481           pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
00482         }
00483
00484         /* Calcul of the USB frequency*/
00485 #if defined(STM32F105xC) || defined(STM32F107xC)
00486         /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
00487         if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
00488         {
00489           /* Prescaler of 2 selected for USB */
00490           frequency = pllclk;
00491         }
00492         else
00493         {
00494           /* Prescaler of 3 selected for USB */
00495           frequency = (2 * pllclk) / 3;
00496         }
00497 #else
00498         /* USBCLK = PLLCLK / USB prescaler */
00499         if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
00500         {
00501           /* No prescaler selected for USB */
00502           frequency = pllclk;
00503         }
00504         else
00505         {
00506           /* Prescaler of 1.5 selected for USB */
00507           frequency = (pllclk * 2) / 3;
00508         }
00509 #endif
00510       }
00511       break;
00512     }
00513 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00514 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
00515   case RCC_PERIPHCLK_I2S2:
00516     {
00517 #if defined(STM32F103xE) || defined(STM32F103xG)
00518       /* SYSCLK used as source clock for I2S2 */
00519       frequency = HAL_RCC_GetSysClockFreq();
00520 #else
00521       if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
00522       {
00523         /* SYSCLK used as source clock for I2S2 */
00524         frequency = HAL_RCC_GetSysClockFreq();
00525       }
00526       else
00527       {
00528          /* Check if PLLI2S is enabled */
00529         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
00530         {
00531           /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
00532           prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
00533           pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
00534           frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
00535         }
00536       }
00537 #endif /* STM32F103xE || STM32F103xG */
00538       break;
00539     }
00540   case RCC_PERIPHCLK_I2S3:
00541     {
00542 #if defined(STM32F103xE) || defined(STM32F103xG)
00543       /* SYSCLK used as source clock for I2S3 */
00544       frequency = HAL_RCC_GetSysClockFreq();
00545 #else
00546       if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
00547       {
00548         /* SYSCLK used as source clock for I2S3 */
00549         frequency = HAL_RCC_GetSysClockFreq();
00550       }
00551       else
00552       {
00553          /* Check if PLLI2S is enabled */
00554         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
00555         {
00556           /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
00557           prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
00558           pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
00559           frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
00560         }
00561       }
00562 #endif /* STM32F103xE || STM32F103xG */
00563       break;
00564     }
00565 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00566   case RCC_PERIPHCLK_RTC:
00567     {
00568       /* Get RCC BDCR configuration ------------------------------------------------------*/
00569       temp_reg = RCC->BDCR;
00570
00571       /* Check if LSE is ready if RTC clock selection is LSE */
00572       if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
00573       {
00574         frequency = LSE_VALUE;
00575       }
00576       /* Check if LSI is ready if RTC clock selection is LSI */
00577       else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
00578       {
00579         frequency = LSI_VALUE;
00580       }
00581       else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
00582       {
00583         frequency = HSE_VALUE / 128U;
00584       }
00585       /* Clock not enabled for RTC*/
00586       else
00587       {
00588         frequency = 0U;
00589       }
00590       break;
00591     }
00592   case RCC_PERIPHCLK_ADC:
00593     {
00594       frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
00595       break;
00596     }
00597   default:
00598     {
00599       break;
00600     }
00601   }
00602   return(frequency);
00603 }
00604
00605 /**
00606   * @}
00607   */
00608
00609 #if defined(STM32F105xC) || defined(STM32F107xC)
00610 /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
00611   *  @brief  PLLI2S Management functions
00612   *
00613 @verbatim
00614  ===============================================================================
00615                 ##### Extended PLLI2S Management functions  #####
00616  ===============================================================================
00617     [..]
00618     This subsection provides a set of functions allowing to control the PLLI2S
00619     activation or deactivation
00620 @endverbatim
00621   * @{
00622   */
00623
00624 /**
00625   * @brief  Enable PLLI2S
00626   * @param  PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
00627   *         contains the configuration information for the PLLI2S
00628   * @note   The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
00629   * @retval HAL status
00630   */
00631 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
00632 {
00633   uint32_t tickstart = 0U;
00634
00635   /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
00636   if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
00637   {
00638     /* Check the parameters */
00639     assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
00640     assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
00641
00642     /* Prediv2 can be written only when the PLL2 is disabled. */
00643     /* Return an error only if new value is different from the programmed value */
00644     if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
00645       (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
00646     {
00647       return HAL_ERROR;
00648     }
00649
00650     /* Disable the main PLLI2S. */
00651     __HAL_RCC_PLLI2S_DISABLE();
00652
00653     /* Get Start Tick*/
00654     tickstart = HAL_GetTick();
00655
00656     /* Wait till PLLI2S is ready */
00657     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
00658     {
00659       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
00660       {
00661         return HAL_TIMEOUT;
00662       }
00663     }
00664
00665     /* Configure the HSE prediv2 factor --------------------------------*/
00666     __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
00667
00668
00669     /* Configure the main PLLI2S multiplication factors. */
00670     __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
00671
00672     /* Enable the main PLLI2S. */
00673     __HAL_RCC_PLLI2S_ENABLE();
00674
00675     /* Get Start Tick*/
00676     tickstart = HAL_GetTick();
00677
00678     /* Wait till PLLI2S is ready */
00679     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
00680     {
00681       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
00682       {
00683         return HAL_TIMEOUT;
00684       }
00685     }
00686   }
00687   else
00688   {
00689     /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
00690     return HAL_ERROR;
00691   }
00692
00693   return HAL_OK;
00694 }
00695
00696 /**
00697   * @brief  Disable PLLI2S
00698   * @note   PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
00699   * @retval HAL status
00700   */
00701 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
00702 {
00703   uint32_t tickstart = 0U;
00704
00705   /* Disable PLL I2S as not requested by I2S2 or I2S3*/
00706   if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
00707   {
00708     /* Disable the main PLLI2S. */
00709     __HAL_RCC_PLLI2S_DISABLE();
00710
00711     /* Get Start Tick*/
00712     tickstart = HAL_GetTick();
00713
00714     /* Wait till PLLI2S is ready */
00715     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
00716     {
00717       if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
00718       {
00719         return HAL_TIMEOUT;
00720       }
00721     }
00722   }
00723   else
00724   {
00725     /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
00726     return HAL_ERROR;
00727   }
00728
00729   return HAL_OK;
00730 }
00731
00732 /**
00733   * @}
00734   */
00735
00736 /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
00737   *  @brief  PLL2 Management functions
00738   *
00739 @verbatim
00740  ===============================================================================
00741                 ##### Extended PLL2 Management functions  #####
00742  ===============================================================================
00743     [..]
00744     This subsection provides a set of functions allowing to control the PLL2
00745     activation or deactivation
00746 @endverbatim
00747   * @{
00748   */
00749
00750 /**
00751   * @brief  Enable PLL2
00752   * @param  PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
00753   *         contains the configuration information for the PLL2
00754   * @note   The PLL2 configuration not modified if used indirectly as system clock.
00755   * @retval HAL status
00756   */
00757 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef  *PLL2Init)
00758 {
00759   uint32_t tickstart = 0U;
00760
00761   /* This bit can not be cleared if the PLL2 clock is used indirectly as system
00762     clock (i.e. it is used as PLL clock entry that is used as system clock). */
00763   if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
00764         (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
00765         ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
00766   {
00767     return HAL_ERROR;
00768   }
00769   else
00770   {
00771     /* Check the parameters */
00772     assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
00773     assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
00774
00775     /* Prediv2 can be written only when the PLLI2S is disabled. */
00776     /* Return an error only if new value is different from the programmed value */
00777     if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
00778       (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
00779     {
00780       return HAL_ERROR;
00781     }
00782
00783     /* Disable the main PLL2. */
00784     __HAL_RCC_PLL2_DISABLE();
00785
00786     /* Get Start Tick*/
00787     tickstart = HAL_GetTick();
00788
00789     /* Wait till PLL2 is disabled */
00790     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
00791     {
00792       if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
00793       {
00794         return HAL_TIMEOUT;
00795       }
00796     }
00797
00798     /* Configure the HSE prediv2 factor --------------------------------*/
00799     __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
00800
00801     /* Configure the main PLL2 multiplication factors. */
00802     __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
00803
00804     /* Enable the main PLL2. */
00805     __HAL_RCC_PLL2_ENABLE();
00806
00807     /* Get Start Tick*/
00808     tickstart = HAL_GetTick();
00809
00810     /* Wait till PLL2 is ready */
00811     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  == RESET)
00812     {
00813       if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
00814       {
00815         return HAL_TIMEOUT;
00816       }
00817     }
00818   }
00819
00820   return HAL_OK;
00821 }
00822
00823 /**
00824   * @brief  Disable PLL2
00825   * @note   PLL2 is not disabled if used indirectly as system clock.
00826   * @retval HAL status
00827   */
00828 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
00829 {
00830   uint32_t tickstart = 0U;
00831
00832   /* This bit can not be cleared if the PLL2 clock is used indirectly as system
00833     clock (i.e. it is used as PLL clock entry that is used as system clock). */
00834   if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
00835         (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
00836         ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
00837   {
00838     return HAL_ERROR;
00839   }
00840   else
00841   {
00842     /* Disable the main PLL2. */
00843     __HAL_RCC_PLL2_DISABLE();
00844
00845     /* Get Start Tick*/
00846     tickstart = HAL_GetTick();
00847
00848     /* Wait till PLL2 is disabled */
00849     while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY)  != RESET)
00850     {
00851       if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
00852       {
00853         return HAL_TIMEOUT;
00854       }
00855     }
00856   }
00857
00858   return HAL_OK;
00859 }
00860
00861 /**
00862   * @}
00863   */
00864 #endif /* STM32F105xC || STM32F107xC */
00865
00866 /**
00867   * @}
00868   */
00869
00870 /**
00871   * @}
00872   */
00873
00874 #endif /* HAL_RCC_MODULE_ENABLED */
00875
00876 /**
00877   * @}
00878   */
00879
00880 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00881
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rcc_ex.h Source File

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stm32f1xx_hal_rcc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_rcc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of RCC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_RCC_EX_H
00040 #define __STM32F1xx_HAL_RCC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RCCEx
00054   * @{
00055   */
00056
00057 /** @addtogroup RCCEx_Private_Constants
00058  * @{
00059  */
00060
00061 #if defined(STM32F105xC) || defined(STM32F107xC)
00062
00063 /* Alias word address of PLLI2SON bit */
00064 #define PLLI2SON_BITNUMBER           RCC_CR_PLL3ON_Pos
00065 #define RCC_CR_PLLI2SON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U)))
00066 /* Alias word address of PLL2ON bit */
00067 #define PLL2ON_BITNUMBER             RCC_CR_PLL2ON_Pos
00068 #define RCC_CR_PLL2ON_BB             ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U)))
00069
00070 #define PLLI2S_TIMEOUT_VALUE         100U  /* 100 ms */
00071 #define PLL2_TIMEOUT_VALUE           100U  /* 100 ms */
00072
00073 #endif /* STM32F105xC || STM32F107xC */
00074
00075
00076 #define CR_REG_INDEX                 ((uint8_t)1)
00077
00078 /**
00079   * @}
00080   */
00081
00082 /** @addtogroup RCCEx_Private_Macros
00083  * @{
00084  */
00085
00086 #if defined(STM32F105xC) || defined(STM32F107xC)
00087 #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
00088                                            ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
00089 #endif /* STM32F105xC || STM32F107xC */
00090
00091 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
00092  || defined(STM32F100xE)
00093 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1)  || ((__DIV__) == RCC_HSE_PREDIV_DIV2)  || \
00094                                     ((__DIV__) == RCC_HSE_PREDIV_DIV3)  || ((__DIV__) == RCC_HSE_PREDIV_DIV4)  || \
00095                                     ((__DIV__) == RCC_HSE_PREDIV_DIV5)  || ((__DIV__) == RCC_HSE_PREDIV_DIV6)  || \
00096                                     ((__DIV__) == RCC_HSE_PREDIV_DIV7)  || ((__DIV__) == RCC_HSE_PREDIV_DIV8)  || \
00097                                     ((__DIV__) == RCC_HSE_PREDIV_DIV9)  || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
00098                                     ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
00099                                     ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
00100                                     ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
00101
00102 #else
00103 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1)  || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
00104 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
00105
00106 #if defined(STM32F105xC) || defined(STM32F107xC)
00107 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4)  || ((__MUL__) == RCC_PLL_MUL5) || \
00108                                  ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL7) || \
00109                                  ((__MUL__) == RCC_PLL_MUL8)  || ((__MUL__) == RCC_PLL_MUL9) || \
00110                                  ((__MUL__) == RCC_PLL_MUL6_5))
00111
00112 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK)  || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
00113                                     || ((__SOURCE__) == RCC_MCO1SOURCE_HSE)     || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
00114                                     || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
00115                                     || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
00116                                     || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
00117
00118 #else
00119 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2)  || ((__MUL__) == RCC_PLL_MUL3)  || \
00120                                  ((__MUL__) == RCC_PLL_MUL4)  || ((__MUL__) == RCC_PLL_MUL5)  || \
00121                                  ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL7)  || \
00122                                  ((__MUL__) == RCC_PLL_MUL8)  || ((__MUL__) == RCC_PLL_MUL9)  || \
00123                                  ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
00124                                  ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
00125                                  ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
00126                                  ((__MUL__) == RCC_PLL_MUL16))
00127
00128 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK)  || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
00129                                     || ((__SOURCE__) == RCC_MCO1SOURCE_HSE)     || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
00130                                     || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
00131
00132 #endif /* STM32F105xC || STM32F107xC*/
00133
00134 #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2)  || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4)   || \
00135                                           ((__ADCCLK__) == RCC_ADCPCLK2_DIV6)  || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
00136
00137 #if defined(STM32F105xC) || defined(STM32F107xC)
00138 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)  || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
00139
00140 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)  || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
00141
00142 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2)  || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
00143
00144 #define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8)   || ((__MUL__) == RCC_PLLI2S_MUL9)  || \
00145                                     ((__MUL__) == RCC_PLLI2S_MUL10)  || ((__MUL__) == RCC_PLLI2S_MUL11)  || \
00146                                     ((__MUL__) == RCC_PLLI2S_MUL12)  || ((__MUL__) == RCC_PLLI2S_MUL13)  || \
00147                                     ((__MUL__) == RCC_PLLI2S_MUL14)  || ((__MUL__) == RCC_PLLI2S_MUL16)  || \
00148                                     ((__MUL__) == RCC_PLLI2S_MUL20))
00149
00150 #define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1)  || ((__DIV__) == RCC_HSE_PREDIV2_DIV2)  || \
00151                                      ((__DIV__) == RCC_HSE_PREDIV2_DIV3)  || ((__DIV__) == RCC_HSE_PREDIV2_DIV4)  || \
00152                                      ((__DIV__) == RCC_HSE_PREDIV2_DIV5)  || ((__DIV__) == RCC_HSE_PREDIV2_DIV6)  || \
00153                                      ((__DIV__) == RCC_HSE_PREDIV2_DIV7)  || ((__DIV__) == RCC_HSE_PREDIV2_DIV8)  || \
00154                                      ((__DIV__) == RCC_HSE_PREDIV2_DIV9)  || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
00155                                      ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
00156                                      ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
00157                                      ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
00158
00159 #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
00160                               ((__PLL__) == RCC_PLL2_ON))
00161
00162 #define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8)  || ((__MUL__) == RCC_PLL2_MUL9)  || \
00163                                   ((__MUL__) == RCC_PLL2_MUL10)  || ((__MUL__) == RCC_PLL2_MUL11)  || \
00164                                   ((__MUL__) == RCC_PLL2_MUL12)  || ((__MUL__) == RCC_PLL2_MUL13)  || \
00165                                   ((__MUL__) == RCC_PLL2_MUL14)  || ((__MUL__) == RCC_PLL2_MUL16)  || \
00166                                   ((__MUL__) == RCC_PLL2_MUL20))
00167
00168 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
00169                ((((__SELECTION__) & RCC_PERIPHCLK_RTC)  == RCC_PERIPHCLK_RTC)  || \
00170                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)  == RCC_PERIPHCLK_ADC)  || \
00171                 (((__SELECTION__) & RCC_PERIPHCLK_I2S2)  == RCC_PERIPHCLK_I2S2)  || \
00172                 (((__SELECTION__) & RCC_PERIPHCLK_I2S3)   == RCC_PERIPHCLK_I2S3)   || \
00173                 (((__SELECTION__) & RCC_PERIPHCLK_USB)   == RCC_PERIPHCLK_USB))
00174
00175 #elif defined(STM32F103xE) || defined(STM32F103xG)
00176
00177 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
00178
00179 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
00180
00181 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
00182                ((((__SELECTION__) & RCC_PERIPHCLK_RTC)  == RCC_PERIPHCLK_RTC)  || \
00183                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)  == RCC_PERIPHCLK_ADC)  || \
00184                 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)  || \
00185                 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)   || \
00186                 (((__SELECTION__) & RCC_PERIPHCLK_USB)  == RCC_PERIPHCLK_USB))
00187
00188
00189 #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
00190  || defined(STM32F103xB)
00191
00192 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
00193                ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)  || \
00194                 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)  || \
00195                 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
00196
00197 #else
00198
00199 #define IS_RCC_PERIPHCLOCK(__SELECTION__)  \
00200                ((((__SELECTION__) & RCC_PERIPHCLK_RTC)  == RCC_PERIPHCLK_RTC)  || \
00201                 (((__SELECTION__) & RCC_PERIPHCLK_ADC)  == RCC_PERIPHCLK_ADC))
00202
00203 #endif /* STM32F105xC || STM32F107xC */
00204
00205 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
00206  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
00207
00208 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL)  || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
00209
00210 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
00211
00212 /**
00213   * @}
00214   */
00215
00216 /* Exported types ------------------------------------------------------------*/
00217
00218 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
00219   * @{
00220   */
00221
00222 #if defined(STM32F105xC) || defined(STM32F107xC)
00223 /**
00224   * @brief  RCC PLL2 configuration structure definition
00225   */
00226 typedef struct
00227 {
00228   uint32_t PLL2State;     /*!< The new state of the PLL2.
00229                               This parameter can be a value of @ref RCCEx_PLL2_Config */
00230
00231   uint32_t PLL2MUL;         /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
00232                               This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
00233
00234 #if defined(STM32F105xC) || defined(STM32F107xC)
00235   uint32_t HSEPrediv2Value;       /*!<  The Prediv2 factor value.
00236                                        This parameter can be a value of @ref RCCEx_Prediv2_Factor */
00237
00238 #endif /* STM32F105xC || STM32F107xC */
00239 } RCC_PLL2InitTypeDef;
00240
00241 #endif /* STM32F105xC || STM32F107xC */
00242
00243 /**
00244   * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
00245   */
00246 typedef struct
00247 {
00248   uint32_t OscillatorType;       /*!< The oscillators to be configured.
00249                                        This parameter can be a value of @ref RCC_Oscillator_Type */
00250
00251 #if defined(STM32F105xC) || defined(STM32F107xC)
00252   uint32_t Prediv1Source;       /*!<  The Prediv1 source value.
00253                                        This parameter can be a value of @ref RCCEx_Prediv1_Source */
00254 #endif /* STM32F105xC || STM32F107xC */
00255
00256   uint32_t HSEState;              /*!< The new state of the HSE.
00257                                        This parameter can be a value of @ref RCC_HSE_Config */
00258
00259   uint32_t HSEPredivValue;       /*!<  The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
00260                                        This parameter can be a value of @ref RCCEx_Prediv1_Factor */
00261
00262   uint32_t LSEState;              /*!<  The new state of the LSE.
00263                                         This parameter can be a value of @ref RCC_LSE_Config */
00264
00265   uint32_t HSIState;              /*!< The new state of the HSI.
00266                                        This parameter can be a value of @ref RCC_HSI_Config */
00267
00268   uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
00269                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
00270
00271   uint32_t LSIState;              /*!<  The new state of the LSI.
00272                                         This parameter can be a value of @ref RCC_LSI_Config */
00273
00274   RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */
00275
00276 #if defined(STM32F105xC) || defined(STM32F107xC)
00277   RCC_PLL2InitTypeDef PLL2;         /*!< PLL2 structure parameters */
00278 #endif /* STM32F105xC || STM32F107xC */
00279 } RCC_OscInitTypeDef;
00280
00281 #if defined(STM32F105xC) || defined(STM32F107xC)
00282 /**
00283   * @brief  RCC PLLI2S configuration structure definition
00284   */
00285 typedef struct
00286 {
00287   uint32_t PLLI2SMUL;         /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
00288                               This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
00289
00290 #if defined(STM32F105xC) || defined(STM32F107xC)
00291   uint32_t HSEPrediv2Value;       /*!<  The Prediv2 factor value.
00292                                        This parameter can be a value of @ref RCCEx_Prediv2_Factor */
00293
00294 #endif /* STM32F105xC || STM32F107xC */
00295 } RCC_PLLI2SInitTypeDef;
00296 #endif /* STM32F105xC || STM32F107xC */
00297
00298 /**
00299   * @brief  RCC extended clocks structure definition
00300   */
00301 typedef struct
00302 {
00303   uint32_t PeriphClockSelection;      /*!< The Extended Clock to be configured.
00304                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
00305
00306   uint32_t RTCClockSelection;         /*!< specifies the RTC clock source.
00307                                        This parameter can be a value of @ref RCC_RTC_Clock_Source */
00308
00309   uint32_t AdcClockSelection;         /*!< ADC clock source
00310                                        This parameter can be a value of @ref RCCEx_ADC_Prescaler */
00311
00312 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
00313  || defined(STM32F107xC)
00314   uint32_t I2s2ClockSelection;         /*!< I2S2 clock source
00315                                        This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
00316
00317   uint32_t I2s3ClockSelection;         /*!< I2S3 clock source
00318                                        This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
00319
00320 #if defined(STM32F105xC) || defined(STM32F107xC)
00321   RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters
00322                                       This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
00323
00324 #endif /* STM32F105xC || STM32F107xC */
00325 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00326
00327 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
00328  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
00329  || defined(STM32F105xC) || defined(STM32F107xC)
00330   uint32_t UsbClockSelection;         /*!< USB clock source
00331                                        This parameter can be a value of @ref RCCEx_USB_Prescaler */
00332
00333 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00334 } RCC_PeriphCLKInitTypeDef;
00335
00336 /**
00337   * @}
00338   */
00339
00340 /* Exported constants --------------------------------------------------------*/
00341
00342 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
00343   * @{
00344   */
00345
00346 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
00347   * @{
00348   */
00349 #define RCC_PERIPHCLK_RTC           0x00000001U
00350 #define RCC_PERIPHCLK_ADC           0x00000002U
00351 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
00352  || defined(STM32F107xC)
00353 #define RCC_PERIPHCLK_I2S2          0x00000004U
00354 #define RCC_PERIPHCLK_I2S3          0x00000008U
00355 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00356 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
00357  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
00358  || defined(STM32F105xC) || defined(STM32F107xC)
00359 #define RCC_PERIPHCLK_USB          0x00000010U
00360 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00361
00362 /**
00363   * @}
00364   */
00365
00366 /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
00367   * @{
00368   */
00369 #define RCC_ADCPCLK2_DIV2              RCC_CFGR_ADCPRE_DIV2
00370 #define RCC_ADCPCLK2_DIV4              RCC_CFGR_ADCPRE_DIV4
00371 #define RCC_ADCPCLK2_DIV6              RCC_CFGR_ADCPRE_DIV6
00372 #define RCC_ADCPCLK2_DIV8              RCC_CFGR_ADCPRE_DIV8
00373
00374 /**
00375   * @}
00376   */
00377
00378 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
00379  || defined(STM32F107xC)
00380 /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
00381   * @{
00382   */
00383 #define RCC_I2S2CLKSOURCE_SYSCLK              0x00000000U
00384 #if defined(STM32F105xC) || defined(STM32F107xC)
00385 #define RCC_I2S2CLKSOURCE_PLLI2S_VCO          RCC_CFGR2_I2S2SRC
00386 #endif /* STM32F105xC || STM32F107xC */
00387
00388 /**
00389   * @}
00390   */
00391
00392 /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
00393   * @{
00394   */
00395 #define RCC_I2S3CLKSOURCE_SYSCLK              0x00000000U
00396 #if defined(STM32F105xC) || defined(STM32F107xC)
00397 #define RCC_I2S3CLKSOURCE_PLLI2S_VCO          RCC_CFGR2_I2S3SRC
00398 #endif /* STM32F105xC || STM32F107xC */
00399
00400 /**
00401   * @}
00402   */
00403
00404 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00405
00406 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
00407  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
00408
00409 /** @defgroup RCCEx_USB_Prescaler USB Prescaler
00410   * @{
00411   */
00412 #define RCC_USBCLKSOURCE_PLL              RCC_CFGR_USBPRE
00413 #define RCC_USBCLKSOURCE_PLL_DIV1_5       0x00000000U
00414
00415 /**
00416   * @}
00417   */
00418
00419 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
00420
00421
00422 #if defined(STM32F105xC) || defined(STM32F107xC)
00423 /** @defgroup RCCEx_USB_Prescaler USB Prescaler
00424   * @{
00425   */
00426 #define RCC_USBCLKSOURCE_PLL_DIV2              RCC_CFGR_OTGFSPRE
00427 #define RCC_USBCLKSOURCE_PLL_DIV3              0x00000000U
00428
00429 /**
00430   * @}
00431   */
00432
00433 /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
00434   * @{
00435   */
00436
00437 #define RCC_PLLI2S_MUL8                   RCC_CFGR2_PLL3MUL8   /*!< PLLI2S input clock * 8 */
00438 #define RCC_PLLI2S_MUL9                   RCC_CFGR2_PLL3MUL9   /*!< PLLI2S input clock * 9 */
00439 #define RCC_PLLI2S_MUL10                  RCC_CFGR2_PLL3MUL10  /*!< PLLI2S input clock * 10 */
00440 #define RCC_PLLI2S_MUL11                  RCC_CFGR2_PLL3MUL11  /*!< PLLI2S input clock * 11 */
00441 #define RCC_PLLI2S_MUL12                  RCC_CFGR2_PLL3MUL12  /*!< PLLI2S input clock * 12 */
00442 #define RCC_PLLI2S_MUL13                  RCC_CFGR2_PLL3MUL13  /*!< PLLI2S input clock * 13 */
00443 #define RCC_PLLI2S_MUL14                  RCC_CFGR2_PLL3MUL14  /*!< PLLI2S input clock * 14 */
00444 #define RCC_PLLI2S_MUL16                  RCC_CFGR2_PLL3MUL16  /*!< PLLI2S input clock * 16 */
00445 #define RCC_PLLI2S_MUL20                  RCC_CFGR2_PLL3MUL20  /*!< PLLI2S input clock * 20 */
00446
00447 /**
00448   * @}
00449   */
00450 #endif /* STM32F105xC || STM32F107xC */
00451
00452 #if defined(STM32F105xC) || defined(STM32F107xC)
00453 /** @defgroup RCCEx_Prediv1_Source Prediv1 Source
00454   * @{
00455   */
00456
00457 #define RCC_PREDIV1_SOURCE_HSE           RCC_CFGR2_PREDIV1SRC_HSE
00458 #define RCC_PREDIV1_SOURCE_PLL2          RCC_CFGR2_PREDIV1SRC_PLL2
00459
00460 /**
00461   * @}
00462   */
00463 #endif /* STM32F105xC || STM32F107xC */
00464
00465 /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
00466   * @{
00467   */
00468
00469 #define RCC_HSE_PREDIV_DIV1              0x00000000U
00470
00471 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
00472  || defined(STM32F100xE)
00473 #define RCC_HSE_PREDIV_DIV2              RCC_CFGR2_PREDIV1_DIV2
00474 #define RCC_HSE_PREDIV_DIV3              RCC_CFGR2_PREDIV1_DIV3
00475 #define RCC_HSE_PREDIV_DIV4              RCC_CFGR2_PREDIV1_DIV4
00476 #define RCC_HSE_PREDIV_DIV5              RCC_CFGR2_PREDIV1_DIV5
00477 #define RCC_HSE_PREDIV_DIV6              RCC_CFGR2_PREDIV1_DIV6
00478 #define RCC_HSE_PREDIV_DIV7              RCC_CFGR2_PREDIV1_DIV7
00479 #define RCC_HSE_PREDIV_DIV8              RCC_CFGR2_PREDIV1_DIV8
00480 #define RCC_HSE_PREDIV_DIV9              RCC_CFGR2_PREDIV1_DIV9
00481 #define RCC_HSE_PREDIV_DIV10             RCC_CFGR2_PREDIV1_DIV10
00482 #define RCC_HSE_PREDIV_DIV11             RCC_CFGR2_PREDIV1_DIV11
00483 #define RCC_HSE_PREDIV_DIV12             RCC_CFGR2_PREDIV1_DIV12
00484 #define RCC_HSE_PREDIV_DIV13             RCC_CFGR2_PREDIV1_DIV13
00485 #define RCC_HSE_PREDIV_DIV14             RCC_CFGR2_PREDIV1_DIV14
00486 #define RCC_HSE_PREDIV_DIV15             RCC_CFGR2_PREDIV1_DIV15
00487 #define RCC_HSE_PREDIV_DIV16             RCC_CFGR2_PREDIV1_DIV16
00488 #else
00489 #define RCC_HSE_PREDIV_DIV2              RCC_CFGR_PLLXTPRE
00490 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
00491
00492 /**
00493   * @}
00494   */
00495
00496 #if defined(STM32F105xC) || defined(STM32F107xC)
00497 /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
00498   * @{
00499   */
00500
00501 #define RCC_HSE_PREDIV2_DIV1                RCC_CFGR2_PREDIV2_DIV1   /*!< PREDIV2 input clock not divided */
00502 #define RCC_HSE_PREDIV2_DIV2                RCC_CFGR2_PREDIV2_DIV2   /*!< PREDIV2 input clock divided by 2 */
00503 #define RCC_HSE_PREDIV2_DIV3                RCC_CFGR2_PREDIV2_DIV3   /*!< PREDIV2 input clock divided by 3 */
00504 #define RCC_HSE_PREDIV2_DIV4                RCC_CFGR2_PREDIV2_DIV4   /*!< PREDIV2 input clock divided by 4 */
00505 #define RCC_HSE_PREDIV2_DIV5                RCC_CFGR2_PREDIV2_DIV5   /*!< PREDIV2 input clock divided by 5 */
00506 #define RCC_HSE_PREDIV2_DIV6                RCC_CFGR2_PREDIV2_DIV6   /*!< PREDIV2 input clock divided by 6 */
00507 #define RCC_HSE_PREDIV2_DIV7                RCC_CFGR2_PREDIV2_DIV7   /*!< PREDIV2 input clock divided by 7 */
00508 #define RCC_HSE_PREDIV2_DIV8                RCC_CFGR2_PREDIV2_DIV8   /*!< PREDIV2 input clock divided by 8 */
00509 #define RCC_HSE_PREDIV2_DIV9                RCC_CFGR2_PREDIV2_DIV9   /*!< PREDIV2 input clock divided by 9 */
00510 #define RCC_HSE_PREDIV2_DIV10               RCC_CFGR2_PREDIV2_DIV10  /*!< PREDIV2 input clock divided by 10 */
00511 #define RCC_HSE_PREDIV2_DIV11               RCC_CFGR2_PREDIV2_DIV11  /*!< PREDIV2 input clock divided by 11 */
00512 #define RCC_HSE_PREDIV2_DIV12               RCC_CFGR2_PREDIV2_DIV12  /*!< PREDIV2 input clock divided by 12 */
00513 #define RCC_HSE_PREDIV2_DIV13               RCC_CFGR2_PREDIV2_DIV13  /*!< PREDIV2 input clock divided by 13 */
00514 #define RCC_HSE_PREDIV2_DIV14               RCC_CFGR2_PREDIV2_DIV14  /*!< PREDIV2 input clock divided by 14 */
00515 #define RCC_HSE_PREDIV2_DIV15               RCC_CFGR2_PREDIV2_DIV15  /*!< PREDIV2 input clock divided by 15 */
00516 #define RCC_HSE_PREDIV2_DIV16               RCC_CFGR2_PREDIV2_DIV16  /*!< PREDIV2 input clock divided by 16 */
00517
00518 /**
00519   * @}
00520   */
00521
00522 /** @defgroup RCCEx_PLL2_Config PLL Config
00523   * @{
00524   */
00525 #define RCC_PLL2_NONE                      0x00000000U
00526 #define RCC_PLL2_OFF                       0x00000001U
00527 #define RCC_PLL2_ON                        0x00000002U
00528
00529 /**
00530   * @}
00531   */
00532
00533 /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
00534   * @{
00535   */
00536
00537 #define RCC_PLL2_MUL8                   RCC_CFGR2_PLL2MUL8   /*!< PLL2 input clock * 8 */
00538 #define RCC_PLL2_MUL9                   RCC_CFGR2_PLL2MUL9   /*!< PLL2 input clock * 9 */
00539 #define RCC_PLL2_MUL10                  RCC_CFGR2_PLL2MUL10  /*!< PLL2 input clock * 10 */
00540 #define RCC_PLL2_MUL11                  RCC_CFGR2_PLL2MUL11  /*!< PLL2 input clock * 11 */
00541 #define RCC_PLL2_MUL12                  RCC_CFGR2_PLL2MUL12  /*!< PLL2 input clock * 12 */
00542 #define RCC_PLL2_MUL13                  RCC_CFGR2_PLL2MUL13  /*!< PLL2 input clock * 13 */
00543 #define RCC_PLL2_MUL14                  RCC_CFGR2_PLL2MUL14  /*!< PLL2 input clock * 14 */
00544 #define RCC_PLL2_MUL16                  RCC_CFGR2_PLL2MUL16  /*!< PLL2 input clock * 16 */
00545 #define RCC_PLL2_MUL20                  RCC_CFGR2_PLL2MUL20  /*!< PLL2 input clock * 20 */
00546
00547 /**
00548   * @}
00549   */
00550
00551 #endif /* STM32F105xC || STM32F107xC */
00552
00553 /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
00554   * @{
00555   */
00556
00557 #if defined(STM32F105xC) || defined(STM32F107xC)
00558 #else
00559 #define RCC_PLL_MUL2                    RCC_CFGR_PLLMULL2
00560 #define RCC_PLL_MUL3                    RCC_CFGR_PLLMULL3
00561 #endif /* STM32F105xC || STM32F107xC */
00562 #define RCC_PLL_MUL4                    RCC_CFGR_PLLMULL4
00563 #define RCC_PLL_MUL5                    RCC_CFGR_PLLMULL5
00564 #define RCC_PLL_MUL6                    RCC_CFGR_PLLMULL6
00565 #define RCC_PLL_MUL7                    RCC_CFGR_PLLMULL7
00566 #define RCC_PLL_MUL8                    RCC_CFGR_PLLMULL8
00567 #define RCC_PLL_MUL9                    RCC_CFGR_PLLMULL9
00568 #if defined(STM32F105xC) || defined(STM32F107xC)
00569 #define RCC_PLL_MUL6_5                  RCC_CFGR_PLLMULL6_5
00570 #else
00571 #define RCC_PLL_MUL10                   RCC_CFGR_PLLMULL10
00572 #define RCC_PLL_MUL11                   RCC_CFGR_PLLMULL11
00573 #define RCC_PLL_MUL12                   RCC_CFGR_PLLMULL12
00574 #define RCC_PLL_MUL13                   RCC_CFGR_PLLMULL13
00575 #define RCC_PLL_MUL14                   RCC_CFGR_PLLMULL14
00576 #define RCC_PLL_MUL15                   RCC_CFGR_PLLMULL15
00577 #define RCC_PLL_MUL16                   RCC_CFGR_PLLMULL16
00578 #endif /* STM32F105xC || STM32F107xC */
00579
00580 /**
00581   * @}
00582   */
00583
00584 /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
00585   * @{
00586   */
00587 #define RCC_MCO1SOURCE_NOCLOCK           ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
00588 #define RCC_MCO1SOURCE_SYSCLK            ((uint32_t)RCC_CFGR_MCO_SYSCLK)
00589 #define RCC_MCO1SOURCE_HSI               ((uint32_t)RCC_CFGR_MCO_HSI)
00590 #define RCC_MCO1SOURCE_HSE               ((uint32_t)RCC_CFGR_MCO_HSE)
00591 #define RCC_MCO1SOURCE_PLLCLK            ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
00592 #if defined(STM32F105xC) || defined(STM32F107xC)
00593 #define RCC_MCO1SOURCE_PLL2CLK           ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
00594 #define RCC_MCO1SOURCE_PLL3CLK_DIV2      ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
00595 #define RCC_MCO1SOURCE_EXT_HSE           ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
00596 #define RCC_MCO1SOURCE_PLL3CLK           ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
00597 #endif /* STM32F105xC || STM32F107xC*/
00598 /**
00599   * @}
00600   */
00601
00602 #if defined(STM32F105xC) || defined(STM32F107xC)
00603 /** @defgroup RCCEx_Interrupt RCCEx Interrupt
00604   * @{
00605   */
00606 #define RCC_IT_PLL2RDY                   ((uint8_t)RCC_CIR_PLL2RDYF)
00607 #define RCC_IT_PLLI2SRDY                 ((uint8_t)RCC_CIR_PLL3RDYF)
00608 /**
00609   * @}
00610   */
00611
00612 /** @defgroup RCCEx_Flag RCCEx Flag
00613   *        Elements values convention: 0XXYYYYYb
00614   *           - YYYYY  : Flag position in the register
00615   *           - XX  : Register index
00616   *                 - 01: CR register
00617   * @{
00618   */
00619 /* Flags in the CR register */
00620 #define RCC_FLAG_PLL2RDY                  ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos))
00621 #define RCC_FLAG_PLLI2SRDY                ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos))
00622 /**
00623   * @}
00624   */
00625 #endif /* STM32F105xC || STM32F107xC*/
00626
00627 /**
00628   * @}
00629   */
00630
00631 /* Exported macro ------------------------------------------------------------*/
00632 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
00633  * @{
00634  */
00635
00636 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
00637   * @brief  Enable or disable the AHB1 peripheral clock.
00638   * @note   After reset, the peripheral clock (used for registers read/write access)
00639   *         is disabled and the application software has to enable this clock before
00640   *         using it.
00641   * @{
00642   */
00643
00644 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
00645  || defined(STM32F103xG) || defined(STM32F105xC) || defined  (STM32F107xC)\
00646  || defined  (STM32F100xE)
00647 #define __HAL_RCC_DMA2_CLK_ENABLE()   do { \
00648                                         __IO uint32_t tmpreg; \
00649                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
00650                                         /* Delay after an RCC peripheral clock enabling */ \
00651                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
00652                                         UNUSED(tmpreg); \
00653                                       } while(0U)
00654
00655 #define __HAL_RCC_DMA2_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
00656 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
00657
00658 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
00659  || defined(STM32F103xG) || defined  (STM32F100xE)
00660 #define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
00661                                         __IO uint32_t tmpreg; \
00662                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
00663                                         /* Delay after an RCC peripheral clock enabling */ \
00664                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
00665                                         UNUSED(tmpreg); \
00666                                       } while(0U)
00667
00668 #define __HAL_RCC_FSMC_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
00669 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
00670
00671 #if defined(STM32F103xE) || defined(STM32F103xG)
00672 #define __HAL_RCC_SDIO_CLK_ENABLE()   do { \
00673                                         __IO uint32_t tmpreg; \
00674                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
00675                                         /* Delay after an RCC peripheral clock enabling */ \
00676                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
00677                                         UNUSED(tmpreg); \
00678                                       } while(0U)
00679
00680
00681 #define __HAL_RCC_SDIO_CLK_DISABLE()        (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
00682 #endif /* STM32F103xE || STM32F103xG */
00683
00684 #if defined(STM32F105xC) || defined(STM32F107xC)
00685 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()   do { \
00686                                         __IO uint32_t tmpreg; \
00687                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
00688                                         /* Delay after an RCC peripheral clock enabling */ \
00689                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
00690                                         UNUSED(tmpreg); \
00691                                       } while(0U)
00692
00693
00694 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
00695 #endif /* STM32F105xC || STM32F107xC*/
00696
00697 #if defined(STM32F107xC)
00698 #define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
00699                                         __IO uint32_t tmpreg; \
00700                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
00701                                         /* Delay after an RCC peripheral clock enabling */ \
00702                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
00703                                         UNUSED(tmpreg); \
00704                                       } while(0U)
00705
00706 #define __HAL_RCC_ETHMACTX_CLK_ENABLE()   do { \
00707                                         __IO uint32_t tmpreg; \
00708                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
00709                                         /* Delay after an RCC peripheral clock enabling */ \
00710                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
00711                                         UNUSED(tmpreg); \
00712                                       } while(0U)
00713
00714 #define __HAL_RCC_ETHMACRX_CLK_ENABLE()   do { \
00715                                         __IO uint32_t tmpreg; \
00716                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
00717                                         /* Delay after an RCC peripheral clock enabling */ \
00718                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
00719                                         UNUSED(tmpreg); \
00720                                       } while(0U)
00721
00722 #define __HAL_RCC_ETHMAC_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
00723 #define __HAL_RCC_ETHMACTX_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
00724 #define __HAL_RCC_ETHMACRX_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
00725
00726 /**
00727   * @brief  Enable ETHERNET clock.
00728   */
00729 #define __HAL_RCC_ETH_CLK_ENABLE() do {                                     \
00730                                         __HAL_RCC_ETHMAC_CLK_ENABLE();      \
00731                                         __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
00732                                         __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
00733                                       } while(0U)
00734 /**
00735   * @brief  Disable ETHERNET clock.
00736   */
00737 #define __HAL_RCC_ETH_CLK_DISABLE()  do {                                      \
00738                                           __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
00739                                           __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
00740                                           __HAL_RCC_ETHMAC_CLK_DISABLE();      \
00741                                         } while(0U)
00742
00743 #endif /* STM32F107xC*/
00744
00745 /**
00746   * @}
00747   */
00748
00749 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
00750   * @brief  Get the enable or disable status of the AHB1 peripheral clock.
00751   * @note   After reset, the peripheral clock (used for registers read/write access)
00752   *         is disabled and the application software has to enable this clock before
00753   *         using it.
00754   * @{
00755   */
00756
00757 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
00758  || defined(STM32F103xG) || defined(STM32F105xC) || defined  (STM32F107xC)\
00759  || defined  (STM32F100xE)
00760 #define __HAL_RCC_DMA2_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
00761 #define __HAL_RCC_DMA2_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
00762 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
00763 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
00764  || defined(STM32F103xG) || defined  (STM32F100xE)
00765 #define __HAL_RCC_FSMC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
00766 #define __HAL_RCC_FSMC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
00767 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
00768 #if defined(STM32F103xE) || defined(STM32F103xG)
00769 #define __HAL_RCC_SDIO_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
00770 #define __HAL_RCC_SDIO_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
00771 #endif /* STM32F103xE || STM32F103xG */
00772 #if defined(STM32F105xC) || defined(STM32F107xC)
00773 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
00774 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
00775 #endif /* STM32F105xC || STM32F107xC*/
00776 #if defined(STM32F107xC)
00777 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
00778 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
00779 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
00780 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
00781 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
00782 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
00783 #endif /* STM32F107xC*/
00784
00785 /**
00786   * @}
00787   */
00788
00789 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
00790   * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
00791   * @note   After reset, the peripheral clock (used for registers read/write access)
00792   *         is disabled and the application software has to enable this clock before
00793   *         using it.
00794   * @{
00795   */
00796
00797 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
00798  || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
00799 #define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
00800                                         __IO uint32_t tmpreg; \
00801                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
00802                                         /* Delay after an RCC peripheral clock enabling */ \
00803                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
00804                                         UNUSED(tmpreg); \
00805                                       } while(0U)
00806
00807 #define __HAL_RCC_CAN1_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
00808 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00809
00810 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
00811  || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
00812  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
00813  || defined(STM32F105xC) || defined(STM32F107xC)
00814 #define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
00815                                         __IO uint32_t tmpreg; \
00816                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
00817                                         /* Delay after an RCC peripheral clock enabling */ \
00818                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
00819                                         UNUSED(tmpreg); \
00820                                       } while(0U)
00821
00822 #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
00823                                         __IO uint32_t tmpreg; \
00824                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
00825                                         /* Delay after an RCC peripheral clock enabling */ \
00826                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
00827                                         UNUSED(tmpreg); \
00828                                       } while(0U)
00829
00830 #define __HAL_RCC_USART3_CLK_ENABLE()   do { \
00831                                         __IO uint32_t tmpreg; \
00832                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
00833                                         /* Delay after an RCC peripheral clock enabling */ \
00834                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
00835                                         UNUSED(tmpreg); \
00836                                       } while(0U)
00837
00838 #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
00839                                         __IO uint32_t tmpreg; \
00840                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
00841                                         /* Delay after an RCC peripheral clock enabling */ \
00842                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
00843                                         UNUSED(tmpreg); \
00844                                       } while(0U)
00845
00846 #define __HAL_RCC_TIM4_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
00847 #define __HAL_RCC_SPI2_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
00848 #define __HAL_RCC_USART3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
00849 #define __HAL_RCC_I2C2_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
00850 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
00851
00852 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
00853  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
00854 #define __HAL_RCC_USB_CLK_ENABLE()   do { \
00855                                         __IO uint32_t tmpreg; \
00856                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
00857                                         /* Delay after an RCC peripheral clock enabling */ \
00858                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
00859                                         UNUSED(tmpreg); \
00860                                       } while(0U)
00861
00862 #define __HAL_RCC_USB_CLK_DISABLE()         (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
00863 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
00864
00865 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
00866  || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
00867 #define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
00868                                         __IO uint32_t tmpreg; \
00869                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
00870                                         /* Delay after an RCC peripheral clock enabling */ \
00871                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
00872                                         UNUSED(tmpreg); \
00873                                       } while(0U)
00874
00875 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
00876                                         __IO uint32_t tmpreg; \
00877                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
00878                                         /* Delay after an RCC peripheral clock enabling */ \
00879                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
00880                                         UNUSED(tmpreg); \
00881                                       } while(0U)
00882
00883 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
00884                                         __IO uint32_t tmpreg; \
00885                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
00886                                         /* Delay after an RCC peripheral clock enabling */ \
00887                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
00888                                         UNUSED(tmpreg); \
00889                                       } while(0U)
00890
00891 #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
00892                                         __IO uint32_t tmpreg; \
00893                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
00894                                         /* Delay after an RCC peripheral clock enabling */ \
00895                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
00896                                         UNUSED(tmpreg); \
00897                                       } while(0U)
00898
00899 #define __HAL_RCC_UART4_CLK_ENABLE()   do { \
00900                                         __IO uint32_t tmpreg; \
00901                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
00902                                         /* Delay after an RCC peripheral clock enabling */ \
00903                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
00904                                         UNUSED(tmpreg); \
00905                                       } while(0U)
00906
00907 #define __HAL_RCC_UART5_CLK_ENABLE()   do { \
00908                                         __IO uint32_t tmpreg; \
00909                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
00910                                         /* Delay after an RCC peripheral clock enabling */ \
00911                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
00912                                         UNUSED(tmpreg); \
00913                                       } while(0U)
00914
00915 #define __HAL_RCC_DAC_CLK_ENABLE()   do { \
00916                                         __IO uint32_t tmpreg; \
00917                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
00918                                         /* Delay after an RCC peripheral clock enabling */ \
00919                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
00920                                         UNUSED(tmpreg); \
00921                                       } while(0U)
00922
00923 #define __HAL_RCC_TIM5_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
00924 #define __HAL_RCC_TIM6_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
00925 #define __HAL_RCC_TIM7_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
00926 #define __HAL_RCC_SPI3_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
00927 #define __HAL_RCC_UART4_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
00928 #define __HAL_RCC_UART5_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
00929 #define __HAL_RCC_DAC_CLK_DISABLE()         (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
00930 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
00931
00932 #if defined(STM32F100xB) || defined  (STM32F100xE)
00933 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
00934                                         __IO uint32_t tmpreg; \
00935                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
00936                                         /* Delay after an RCC peripheral clock enabling */ \
00937                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
00938                                         UNUSED(tmpreg); \
00939                                       } while(0U)
00940
00941 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
00942                                         __IO uint32_t tmpreg; \
00943                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
00944                                         /* Delay after an RCC peripheral clock enabling */ \
00945                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
00946                                         UNUSED(tmpreg); \
00947                                       } while(0U)
00948
00949 #define __HAL_RCC_DAC_CLK_ENABLE()   do { \
00950                                         __IO uint32_t tmpreg; \
00951                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
00952                                         /* Delay after an RCC peripheral clock enabling */ \
00953                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
00954                                         UNUSED(tmpreg); \
00955                                       } while(0U)
00956
00957 #define __HAL_RCC_CEC_CLK_ENABLE()   do { \
00958                                         __IO uint32_t tmpreg; \
00959                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
00960                                         /* Delay after an RCC peripheral clock enabling */ \
00961                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
00962                                         UNUSED(tmpreg); \
00963                                       } while(0U)
00964
00965 #define __HAL_RCC_TIM6_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
00966 #define __HAL_RCC_TIM7_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
00967 #define __HAL_RCC_DAC_CLK_DISABLE()         (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
00968 #define __HAL_RCC_CEC_CLK_DISABLE()         (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
00969 #endif /* STM32F100xB || STM32F100xE */
00970
00971 #ifdef STM32F100xE
00972 #define __HAL_RCC_TIM5_CLK_ENABLE()   do { \
00973                                         __IO uint32_t tmpreg; \
00974                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
00975                                         /* Delay after an RCC peripheral clock enabling */ \
00976                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
00977                                         UNUSED(tmpreg); \
00978                                       } while(0U)
00979
00980 #define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
00981                                         __IO uint32_t tmpreg; \
00982                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
00983                                         /* Delay after an RCC peripheral clock enabling */ \
00984                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
00985                                         UNUSED(tmpreg); \
00986                                       } while(0U)
00987
00988 #define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
00989                                         __IO uint32_t tmpreg; \
00990                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
00991                                         /* Delay after an RCC peripheral clock enabling */ \
00992                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
00993                                         UNUSED(tmpreg); \
00994                                       } while(0U)
00995
00996 #define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
00997                                         __IO uint32_t tmpreg; \
00998                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
00999                                         /* Delay after an RCC peripheral clock enabling */ \
01000                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
01001                                         UNUSED(tmpreg); \
01002                                       } while(0U)
01003
01004 #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \
01005                                         __IO uint32_t tmpreg; \
01006                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
01007                                         /* Delay after an RCC peripheral clock enabling */ \
01008                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
01009                                         UNUSED(tmpreg); \
01010                                       } while(0U)
01011
01012 #define __HAL_RCC_UART4_CLK_ENABLE()   do { \
01013                                         __IO uint32_t tmpreg; \
01014                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
01015                                         /* Delay after an RCC peripheral clock enabling */ \
01016                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
01017                                         UNUSED(tmpreg); \
01018                                       } while(0U)
01019
01020 #define __HAL_RCC_UART5_CLK_ENABLE()   do { \
01021                                         __IO uint32_t tmpreg; \
01022                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
01023                                         /* Delay after an RCC peripheral clock enabling */ \
01024                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
01025                                         UNUSED(tmpreg); \
01026                                       } while(0U)
01027
01028 #define __HAL_RCC_TIM5_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
01029 #define __HAL_RCC_TIM12_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
01030 #define __HAL_RCC_TIM13_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
01031 #define __HAL_RCC_TIM14_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
01032 #define __HAL_RCC_SPI3_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
01033 #define __HAL_RCC_UART4_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
01034 #define __HAL_RCC_UART5_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
01035 #endif /* STM32F100xE */
01036
01037 #if defined(STM32F105xC) || defined(STM32F107xC)
01038 #define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
01039                                         __IO uint32_t tmpreg; \
01040                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
01041                                         /* Delay after an RCC peripheral clock enabling */ \
01042                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
01043                                         UNUSED(tmpreg); \
01044                                       } while(0U)
01045
01046 #define __HAL_RCC_CAN2_CLK_DISABLE()        (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
01047 #endif /* STM32F105xC || STM32F107xC */
01048
01049 #if defined(STM32F101xG) || defined(STM32F103xG)
01050 #define __HAL_RCC_TIM12_CLK_ENABLE()   do { \
01051                                         __IO uint32_t tmpreg; \
01052                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
01053                                         /* Delay after an RCC peripheral clock enabling */ \
01054                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
01055                                         UNUSED(tmpreg); \
01056                                       } while(0U)
01057
01058 #define __HAL_RCC_TIM13_CLK_ENABLE()   do { \
01059                                         __IO uint32_t tmpreg; \
01060                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
01061                                         /* Delay after an RCC peripheral clock enabling */ \
01062                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
01063                                         UNUSED(tmpreg); \
01064                                       } while(0U)
01065
01066 #define __HAL_RCC_TIM14_CLK_ENABLE()   do { \
01067                                         __IO uint32_t tmpreg; \
01068                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
01069                                         /* Delay after an RCC peripheral clock enabling */ \
01070                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
01071                                         UNUSED(tmpreg); \
01072                                       } while(0U)
01073
01074 #define __HAL_RCC_TIM12_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
01075 #define __HAL_RCC_TIM13_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
01076 #define __HAL_RCC_TIM14_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
01077 #endif /* STM32F101xG || STM32F103xG*/
01078
01079 /**
01080   * @}
01081   */
01082
01083 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
01084   * @brief  Get the enable or disable status of the APB1 peripheral clock.
01085   * @note   After reset, the peripheral clock (used for registers read/write access)
01086   *         is disabled and the application software has to enable this clock before
01087   *         using it.
01088   * @{
01089   */
01090
01091 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
01092  || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
01093 #define __HAL_RCC_CAN1_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
01094 #define __HAL_RCC_CAN1_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
01095 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
01096 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
01097  || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
01098  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
01099  || defined(STM32F105xC) || defined(STM32F107xC)
01100 #define __HAL_RCC_TIM4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
01101 #define __HAL_RCC_TIM4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
01102 #define __HAL_RCC_SPI2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
01103 #define __HAL_RCC_SPI2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
01104 #define __HAL_RCC_USART3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
01105 #define __HAL_RCC_USART3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
01106 #define __HAL_RCC_I2C2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
01107 #define __HAL_RCC_I2C2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
01108 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
01109 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
01110  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
01111 #define __HAL_RCC_USB_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
01112 #define __HAL_RCC_USB_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
01113 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
01114 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
01115  || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
01116 #define __HAL_RCC_TIM5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
01117 #define __HAL_RCC_TIM5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
01118 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
01119 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
01120 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
01121 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
01122 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
01123 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
01124 #define __HAL_RCC_UART4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
01125 #define __HAL_RCC_UART4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
01126 #define __HAL_RCC_UART5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
01127 #define __HAL_RCC_UART5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
01128 #define __HAL_RCC_DAC_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
01129 #define __HAL_RCC_DAC_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
01130 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
01131 #if defined(STM32F100xB) || defined  (STM32F100xE)
01132 #define __HAL_RCC_TIM6_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
01133 #define __HAL_RCC_TIM6_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
01134 #define __HAL_RCC_TIM7_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
01135 #define __HAL_RCC_TIM7_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
01136 #define __HAL_RCC_DAC_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
01137 #define __HAL_RCC_DAC_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
01138 #define __HAL_RCC_CEC_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
01139 #define __HAL_RCC_CEC_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
01140 #endif /* STM32F100xB || STM32F100xE */
01141 #ifdef STM32F100xE
01142 #define __HAL_RCC_TIM5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
01143 #define __HAL_RCC_TIM5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
01144 #define __HAL_RCC_TIM12_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
01145 #define __HAL_RCC_TIM12_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
01146 #define __HAL_RCC_TIM13_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
01147 #define __HAL_RCC_TIM13_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
01148 #define __HAL_RCC_TIM14_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
01149 #define __HAL_RCC_TIM14_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
01150 #define __HAL_RCC_SPI3_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
01151 #define __HAL_RCC_SPI3_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
01152 #define __HAL_RCC_UART4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
01153 #define __HAL_RCC_UART4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
01154 #define __HAL_RCC_UART5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
01155 #define __HAL_RCC_UART5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
01156 #define __HAL_RCC_CAN2_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
01157 #define __HAL_RCC_CAN2_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
01158 #endif /* STM32F100xE */
01159 #if defined(STM32F105xC) || defined(STM32F107xC)
01160 #define __HAL_RCC_TIM12_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
01161 #define __HAL_RCC_TIM12_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
01162 #endif /* STM32F105xC || STM32F107xC */
01163 #if defined(STM32F101xG) || defined(STM32F103xG)
01164 #define __HAL_RCC_TIM13_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
01165 #define __HAL_RCC_TIM13_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
01166 #define __HAL_RCC_TIM14_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
01167 #define __HAL_RCC_TIM14_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
01168 #endif /* STM32F101xG || STM32F103xG*/
01169
01170 /**
01171   * @}
01172   */
01173
01174 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
01175   * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
01176   * @note   After reset, the peripheral clock (used for registers read/write access)
01177   *         is disabled and the application software has to enable this clock before
01178   *         using it.
01179   * @{
01180   */
01181
01182 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
01183  || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
01184  || defined(STM32F103xG)
01185 #define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
01186                                         __IO uint32_t tmpreg; \
01187                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
01188                                         /* Delay after an RCC peripheral clock enabling */ \
01189                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
01190                                         UNUSED(tmpreg); \
01191                                       } while(0U)
01192
01193 #define __HAL_RCC_ADC2_CLK_DISABLE()        (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
01194 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
01195
01196 #if defined(STM32F100xB) || defined(STM32F100xE)
01197 #define __HAL_RCC_TIM15_CLK_ENABLE()   do { \
01198                                         __IO uint32_t tmpreg; \
01199                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
01200                                         /* Delay after an RCC peripheral clock enabling */ \
01201                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
01202                                         UNUSED(tmpreg); \
01203                                       } while(0U)
01204
01205 #define __HAL_RCC_TIM16_CLK_ENABLE()   do { \
01206                                         __IO uint32_t tmpreg; \
01207                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
01208                                         /* Delay after an RCC peripheral clock enabling */ \
01209                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
01210                                         UNUSED(tmpreg); \
01211                                       } while(0U)
01212
01213 #define __HAL_RCC_TIM17_CLK_ENABLE()   do { \
01214                                         __IO uint32_t tmpreg; \
01215                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
01216                                         /* Delay after an RCC peripheral clock enabling */ \
01217                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
01218                                         UNUSED(tmpreg); \
01219                                       } while(0U)
01220
01221 #define __HAL_RCC_TIM15_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
01222 #define __HAL_RCC_TIM16_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
01223 #define __HAL_RCC_TIM17_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
01224 #endif /* STM32F100xB || STM32F100xE */
01225
01226 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
01227  || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
01228  || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
01229  || defined(STM32F107xC)
01230 #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
01231                                         __IO uint32_t tmpreg; \
01232                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
01233                                         /* Delay after an RCC peripheral clock enabling */ \
01234                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
01235                                         UNUSED(tmpreg); \
01236                                       } while(0U)
01237
01238 #define __HAL_RCC_GPIOE_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
01239 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
01240
01241 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
01242  || defined(STM32F103xG)
01243 #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
01244                                         __IO uint32_t tmpreg; \
01245                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
01246                                         /* Delay after an RCC peripheral clock enabling */ \
01247                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
01248                                         UNUSED(tmpreg); \
01249                                       } while(0U)
01250
01251 #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
01252                                         __IO uint32_t tmpreg; \
01253                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
01254                                         /* Delay after an RCC peripheral clock enabling */ \
01255                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
01256                                         UNUSED(tmpreg); \
01257                                       } while(0U)
01258
01259 #define __HAL_RCC_GPIOF_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
01260 #define __HAL_RCC_GPIOG_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
01261 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
01262
01263 #if defined(STM32F103xE) || defined(STM32F103xG)
01264 #define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
01265                                         __IO uint32_t tmpreg; \
01266                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
01267                                         /* Delay after an RCC peripheral clock enabling */ \
01268                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
01269                                         UNUSED(tmpreg); \
01270                                       } while(0U)
01271
01272 #define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
01273                                         __IO uint32_t tmpreg; \
01274                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
01275                                         /* Delay after an RCC peripheral clock enabling */ \
01276                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
01277                                         UNUSED(tmpreg); \
01278                                       } while(0U)
01279
01280 #define __HAL_RCC_TIM8_CLK_DISABLE()        (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
01281 #define __HAL_RCC_ADC3_CLK_DISABLE()        (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
01282 #endif /* STM32F103xE || STM32F103xG */
01283
01284 #if defined(STM32F100xE)
01285 #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
01286                                         __IO uint32_t tmpreg; \
01287                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
01288                                         /* Delay after an RCC peripheral clock enabling */ \
01289                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
01290                                         UNUSED(tmpreg); \
01291                                       } while(0U)
01292
01293 #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
01294                                         __IO uint32_t tmpreg; \
01295                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
01296                                         /* Delay after an RCC peripheral clock enabling */ \
01297                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
01298                                         UNUSED(tmpreg); \
01299                                       } while(0U)
01300
01301 #define __HAL_RCC_GPIOF_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
01302 #define __HAL_RCC_GPIOG_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
01303 #endif /* STM32F100xE */
01304
01305 #if defined(STM32F101xG) || defined(STM32F103xG)
01306 #define __HAL_RCC_TIM9_CLK_ENABLE()   do { \
01307                                         __IO uint32_t tmpreg; \
01308                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
01309                                         /* Delay after an RCC peripheral clock enabling */ \
01310                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
01311                                         UNUSED(tmpreg); \
01312                                       } while(0U)
01313
01314 #define __HAL_RCC_TIM10_CLK_ENABLE()   do { \
01315                                         __IO uint32_t tmpreg; \
01316                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
01317                                         /* Delay after an RCC peripheral clock enabling */ \
01318                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
01319                                         UNUSED(tmpreg); \
01320                                       } while(0U)
01321
01322 #define __HAL_RCC_TIM11_CLK_ENABLE()   do { \
01323                                         __IO uint32_t tmpreg; \
01324                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
01325                                         /* Delay after an RCC peripheral clock enabling */ \
01326                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
01327                                         UNUSED(tmpreg); \
01328                                       } while(0U)
01329
01330 #define __HAL_RCC_TIM9_CLK_DISABLE()        (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
01331 #define __HAL_RCC_TIM10_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
01332 #define __HAL_RCC_TIM11_CLK_DISABLE()       (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
01333 #endif /* STM32F101xG || STM32F103xG */
01334
01335 /**
01336   * @}
01337   */
01338
01339 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
01340   * @brief  Get the enable or disable status of the APB2 peripheral clock.
01341   * @note   After reset, the peripheral clock (used for registers read/write access)
01342   *         is disabled and the application software has to enable this clock before
01343   *         using it.
01344   * @{
01345   */
01346
01347 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
01348  || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
01349  || defined(STM32F103xG)
01350 #define __HAL_RCC_ADC2_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
01351 #define __HAL_RCC_ADC2_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
01352 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
01353 #if defined(STM32F100xB) || defined(STM32F100xE)
01354 #define __HAL_RCC_TIM15_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
01355 #define __HAL_RCC_TIM15_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
01356 #define __HAL_RCC_TIM16_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
01357 #define __HAL_RCC_TIM16_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
01358 #define __HAL_RCC_TIM17_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
01359 #define __HAL_RCC_TIM17_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
01360 #endif /* STM32F100xB || STM32F100xE */
01361 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
01362  || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
01363  || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
01364  || defined(STM32F107xC)
01365 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
01366 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
01367 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
01368 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
01369  || defined(STM32F103xG)
01370 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
01371 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
01372 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
01373 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
01374 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
01375 #if defined(STM32F103xE) || defined(STM32F103xG)
01376 #define __HAL_RCC_TIM8_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
01377 #define __HAL_RCC_TIM8_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
01378 #define __HAL_RCC_ADC3_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
01379 #define __HAL_RCC_ADC3_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
01380 #endif /* STM32F103xE || STM32F103xG */
01381 #if defined(STM32F100xE)
01382 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
01383 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
01384 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
01385 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
01386 #endif /* STM32F100xE */
01387 #if defined(STM32F101xG) || defined(STM32F103xG)
01388 #define __HAL_RCC_TIM9_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
01389 #define __HAL_RCC_TIM9_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
01390 #define __HAL_RCC_TIM10_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
01391 #define __HAL_RCC_TIM10_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
01392 #define __HAL_RCC_TIM11_IS_CLK_ENABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
01393 #define __HAL_RCC_TIM11_IS_CLK_DISABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
01394 #endif /* STM32F101xG || STM32F103xG */
01395
01396 /**
01397   * @}
01398   */
01399
01400 #if defined(STM32F105xC) || defined(STM32F107xC)
01401 /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
01402   * @brief  Force or release AHB peripheral reset.
01403   * @{
01404   */
01405 #define __HAL_RCC_AHB_FORCE_RESET()         (RCC->AHBRSTR = 0xFFFFFFFFU)
01406 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET()       (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
01407 #if defined(STM32F107xC)
01408 #define __HAL_RCC_ETHMAC_FORCE_RESET()      (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
01409 #endif /* STM32F107xC */
01410
01411 #define __HAL_RCC_AHB_RELEASE_RESET()       (RCC->AHBRSTR = 0x00)
01412 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()     (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
01413 #if defined(STM32F107xC)
01414 #define __HAL_RCC_ETHMAC_RELEASE_RESET()    (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
01415 #endif /* STM32F107xC */
01416
01417 /**
01418   * @}
01419   */
01420 #endif /* STM32F105xC || STM32F107xC */
01421
01422 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
01423   * @brief  Force or release APB1 peripheral reset.
01424   * @{
01425   */
01426
01427 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
01428  || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
01429 #define __HAL_RCC_CAN1_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
01430
01431 #define __HAL_RCC_CAN1_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
01432 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
01433
01434 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
01435  || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
01436  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
01437  || defined(STM32F105xC) || defined(STM32F107xC)
01438 #define __HAL_RCC_TIM4_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
01439 #define __HAL_RCC_SPI2_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
01440 #define __HAL_RCC_USART3_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
01441 #define __HAL_RCC_I2C2_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
01442
01443 #define __HAL_RCC_TIM4_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
01444 #define __HAL_RCC_SPI2_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
01445 #define __HAL_RCC_USART3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
01446 #define __HAL_RCC_I2C2_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
01447 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
01448
01449 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
01450  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
01451 #define __HAL_RCC_USB_FORCE_RESET()         (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
01452 #define __HAL_RCC_USB_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
01453 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
01454
01455 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
01456  || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
01457 #define __HAL_RCC_TIM5_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
01458 #define __HAL_RCC_TIM6_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
01459 #define __HAL_RCC_TIM7_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
01460 #define __HAL_RCC_SPI3_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
01461 #define __HAL_RCC_UART4_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
01462 #define __HAL_RCC_UART5_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
01463 #define __HAL_RCC_DAC_FORCE_RESET()         (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
01464
01465 #define __HAL_RCC_TIM5_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
01466 #define __HAL_RCC_TIM6_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
01467 #define __HAL_RCC_TIM7_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
01468 #define __HAL_RCC_SPI3_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
01469 #define __HAL_RCC_UART4_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
01470 #define __HAL_RCC_UART5_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
01471 #define __HAL_RCC_DAC_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
01472 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
01473
01474 #if defined(STM32F100xB) || defined  (STM32F100xE)
01475 #define __HAL_RCC_TIM6_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
01476 #define __HAL_RCC_TIM7_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
01477 #define __HAL_RCC_DAC_FORCE_RESET()         (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
01478 #define __HAL_RCC_CEC_FORCE_RESET()         (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
01479
01480 #define __HAL_RCC_TIM6_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
01481 #define __HAL_RCC_TIM7_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
01482 #define __HAL_RCC_DAC_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
01483 #define __HAL_RCC_CEC_RELEASE_RESET()       (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
01484 #endif /* STM32F100xB || STM32F100xE */
01485
01486 #if defined  (STM32F100xE)
01487 #define __HAL_RCC_TIM5_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
01488 #define __HAL_RCC_TIM12_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
01489 #define __HAL_RCC_TIM13_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
01490 #define __HAL_RCC_TIM14_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
01491 #define __HAL_RCC_SPI3_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
01492 #define __HAL_RCC_UART4_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
01493 #define __HAL_RCC_UART5_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
01494
01495 #define __HAL_RCC_TIM5_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
01496 #define __HAL_RCC_TIM12_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
01497 #define __HAL_RCC_TIM13_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
01498 #define __HAL_RCC_TIM14_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
01499 #define __HAL_RCC_SPI3_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
01500 #define __HAL_RCC_UART4_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
01501 #define __HAL_RCC_UART5_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
01502 #endif /* STM32F100xE */
01503
01504 #if defined(STM32F105xC) || defined(STM32F107xC)
01505 #define __HAL_RCC_CAN2_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
01506
01507 #define __HAL_RCC_CAN2_RELEASE_RESET()      (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
01508 #endif /* STM32F105xC || STM32F107xC */
01509
01510 #if defined(STM32F101xG) || defined(STM32F103xG)
01511 #define __HAL_RCC_TIM12_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
01512 #define __HAL_RCC_TIM13_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
01513 #define __HAL_RCC_TIM14_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
01514
01515 #define __HAL_RCC_TIM12_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
01516 #define __HAL_RCC_TIM13_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
01517 #define __HAL_RCC_TIM14_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
01518 #endif /* STM32F101xG || STM32F103xG */
01519
01520 /**
01521   * @}
01522   */
01523
01524 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
01525   * @brief  Force or release APB2 peripheral reset.
01526   * @{
01527   */
01528
01529 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
01530  || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
01531  || defined(STM32F103xG)
01532 #define __HAL_RCC_ADC2_FORCE_RESET()        (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
01533
01534 #define __HAL_RCC_ADC2_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
01535 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
01536
01537 #if defined(STM32F100xB) || defined(STM32F100xE)
01538 #define __HAL_RCC_TIM15_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
01539 #define __HAL_RCC_TIM16_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
01540 #define __HAL_RCC_TIM17_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
01541
01542 #define __HAL_RCC_TIM15_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
01543 #define __HAL_RCC_TIM16_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
01544 #define __HAL_RCC_TIM17_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
01545 #endif /* STM32F100xB || STM32F100xE */
01546
01547 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
01548  || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
01549  || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
01550  || defined(STM32F107xC)
01551 #define __HAL_RCC_GPIOE_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
01552
01553 #define __HAL_RCC_GPIOE_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
01554 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
01555
01556 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
01557  || defined(STM32F103xG)
01558 #define __HAL_RCC_GPIOF_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
01559 #define __HAL_RCC_GPIOG_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
01560
01561 #define __HAL_RCC_GPIOF_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
01562 #define __HAL_RCC_GPIOG_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
01563 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
01564
01565 #if defined(STM32F103xE) || defined(STM32F103xG)
01566 #define __HAL_RCC_TIM8_FORCE_RESET()        (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
01567 #define __HAL_RCC_ADC3_FORCE_RESET()        (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
01568
01569 #define __HAL_RCC_TIM8_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
01570 #define __HAL_RCC_ADC3_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
01571 #endif /* STM32F103xE || STM32F103xG */
01572
01573 #if defined(STM32F100xE)
01574 #define __HAL_RCC_GPIOF_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
01575 #define __HAL_RCC_GPIOG_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
01576
01577 #define __HAL_RCC_GPIOF_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
01578 #define __HAL_RCC_GPIOG_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
01579 #endif /* STM32F100xE */
01580
01581 #if defined(STM32F101xG) || defined(STM32F103xG)
01582 #define __HAL_RCC_TIM9_FORCE_RESET()        (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
01583 #define __HAL_RCC_TIM10_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
01584 #define __HAL_RCC_TIM11_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
01585
01586 #define __HAL_RCC_TIM9_RELEASE_RESET()      (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
01587 #define __HAL_RCC_TIM10_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
01588 #define __HAL_RCC_TIM11_RELEASE_RESET()     (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
01589 #endif /* STM32F101xG || STM32F103xG*/
01590
01591 /**
01592   * @}
01593   */
01594
01595 /** @defgroup RCCEx_HSE_Configuration HSE Configuration
01596   * @{
01597   */
01598
01599 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
01600  || defined(STM32F100xE)
01601 /**
01602   * @brief  Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
01603   * @note   Predivision factor can not be changed if PLL is used as system clock
01604   *         In this case, you have to select another source of the system clock, disable the PLL and
01605   *         then change the HSE predivision factor.
01606   * @param  __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
01607   *         This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
01608   */
01609 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
01610 #else
01611 /**
01612   * @brief  Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
01613   * @note   Predivision factor can not be changed if PLL is used as system clock
01614   *         In this case, you have to select another source of the system clock, disable the PLL and
01615   *         then change the HSE predivision factor.
01616   * @param  __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
01617   *         This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
01618   */
01619 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
01620                   MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
01621
01622 #endif /* STM32F105xC || STM32F107xC */
01623
01624 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
01625  || defined(STM32F100xE)
01626 /**
01627   * @brief  Macro to get prediv1 factor for PLL.
01628   */
01629 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
01630
01631 #else
01632 /**
01633   * @brief  Macro to get prediv1 factor for PLL.
01634   */
01635 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
01636
01637 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
01638
01639 /**
01640   * @}
01641   */
01642
01643 #if defined(STM32F105xC) || defined(STM32F107xC)
01644 /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
01645   * @{
01646   */
01647
01648 /** @brief Macros to enable the main PLLI2S.
01649   * @note   After enabling the main PLLI2S, the application software should wait on
01650   *         PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
01651   *         be used as system clock source.
01652   * @note   The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
01653   */
01654 #define __HAL_RCC_PLLI2S_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
01655
01656 /** @brief Macros to disable the main PLLI2S.
01657   * @note   The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
01658   */
01659 #define __HAL_RCC_PLLI2S_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
01660
01661 /** @brief macros to configure the main PLLI2S multiplication factor.
01662   * @note   This function must be used only when the main PLLI2S is disabled.
01663   *
01664   * @param  __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
01665   *          This parameter can be one of the following values:
01666   *             @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
01667   *             @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
01668   *             @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
01669   *             @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
01670   *             @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
01671   *             @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
01672   *             @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
01673   *             @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
01674   *             @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
01675   *
01676   */
01677 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
01678           MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
01679
01680 /**
01681   * @}
01682   */
01683
01684 #endif /* STM32F105xC || STM32F107xC */
01685
01686 /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
01687   * @brief  Macros to configure clock source of different peripherals.
01688   * @{
01689   */
01690
01691 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
01692  || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
01693 /** @brief  Macro to configure the USB clock.
01694   * @param  __USBCLKSOURCE__ specifies the USB clock source.
01695   *          This parameter can be one of the following values:
01696   *            @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
01697   *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
01698   */
01699 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
01700                   MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
01701
01702 /** @brief  Macro to get the USB clock (USBCLK).
01703   * @retval The clock source can be one of the following values:
01704   *            @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
01705   *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
01706   */
01707 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
01708
01709 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
01710
01711 #if defined(STM32F105xC) || defined(STM32F107xC)
01712
01713 /** @brief  Macro to configure the USB OTSclock.
01714   * @param  __USBCLKSOURCE__ specifies the USB clock source.
01715   *          This parameter can be one of the following values:
01716   *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
01717   *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
01718   */
01719 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
01720                   MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
01721
01722 /** @brief  Macro to get the USB clock (USBCLK).
01723   * @retval The clock source can be one of the following values:
01724   *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
01725   *            @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
01726   */
01727 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
01728
01729 #endif /* STM32F105xC || STM32F107xC */
01730
01731 /** @brief  Macro to configure the ADCx clock (x=1 to 3 depending on devices).
01732   * @param  __ADCCLKSOURCE__ specifies the ADC clock source.
01733   *          This parameter can be one of the following values:
01734   *            @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
01735   *            @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
01736   *            @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
01737   *            @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
01738   */
01739 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
01740                   MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
01741
01742 /** @brief  Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
01743   * @retval The clock source can be one of the following values:
01744   *            @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
01745   *            @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
01746   *            @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
01747   *            @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
01748   */
01749 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
01750
01751 /**
01752   * @}
01753   */
01754
01755 #if defined(STM32F105xC) || defined(STM32F107xC)
01756
01757 /** @addtogroup RCCEx_HSE_Configuration
01758   * @{
01759   */
01760
01761 /**
01762   * @brief  Macro to configure the PLL2 & PLLI2S Predivision factor.
01763   * @note   Predivision factor can not be changed if PLL2 is used indirectly as system clock
01764   *         In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
01765   *         then change the PREDIV2 factor.
01766   * @param  __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
01767   *         This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
01768   */
01769 #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
01770                   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
01771
01772 /**
01773   * @brief  Macro to get prediv2 factor for PLL2 & PLL3.
01774   */
01775 #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
01776
01777 /**
01778   * @}
01779   */
01780
01781 /** @addtogroup RCCEx_PLLI2S_Configuration
01782   * @{
01783   */
01784
01785 /** @brief Macros to enable the main PLL2.
01786   * @note   After enabling the main PLL2, the application software should wait on
01787   *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can
01788   *         be used as system clock source.
01789   * @note   The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
01790   */
01791 #define __HAL_RCC_PLL2_ENABLE()          (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)
01792
01793 /** @brief Macros to disable the main PLL2.
01794   * @note   The main PLL2 can not be disabled if it is used indirectly as system clock source
01795   * @note   The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
01796   */
01797 #define __HAL_RCC_PLL2_DISABLE()         (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)
01798
01799 /** @brief macros to configure the main PLL2 multiplication factor.
01800   * @note   This function must be used only when the main PLL2 is disabled.
01801   *
01802   * @param  __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
01803   *          This parameter can be one of the following values:
01804   *             @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
01805   *             @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
01806   *             @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
01807   *             @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
01808   *             @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
01809   *             @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
01810   *             @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
01811   *             @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
01812   *             @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
01813   *
01814   */
01815 #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
01816           MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
01817
01818 /**
01819   * @}
01820   */
01821
01822 /** @defgroup RCCEx_I2S_Configuration I2S Configuration
01823   * @brief  Macros to configure clock source of I2S peripherals.
01824   * @{
01825   */
01826
01827 /** @brief  Macro to configure the I2S2 clock.
01828   * @param  __I2S2CLKSOURCE__ specifies the I2S2 clock source.
01829   *          This parameter can be one of the following values:
01830   *            @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
01831   *            @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
01832   */
01833 #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
01834                   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
01835
01836 /** @brief  Macro to get the I2S2 clock (I2S2CLK).
01837   * @retval The clock source can be one of the following values:
01838   *            @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
01839   *            @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
01840   */
01841 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
01842
01843 /** @brief  Macro to configure the I2S3 clock.
01844   * @param  __I2S2CLKSOURCE__ specifies the I2S3 clock source.
01845   *          This parameter can be one of the following values:
01846   *            @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
01847   *            @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
01848   */
01849 #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
01850                   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
01851
01852 /** @brief  Macro to get the I2S3 clock (I2S3CLK).
01853   * @retval The clock source can be one of the following values:
01854   *            @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
01855   *            @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
01856   */
01857 #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
01858
01859 /**
01860   * @}
01861   */
01862
01863 #endif /* STM32F105xC || STM32F107xC */
01864 /**
01865   * @}
01866   */
01867
01868 /* Exported functions --------------------------------------------------------*/
01869 /** @addtogroup RCCEx_Exported_Functions
01870   * @{
01871   */
01872
01873 /** @addtogroup RCCEx_Exported_Functions_Group1
01874   * @{
01875   */
01876
01877 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01878 void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
01879 uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
01880
01881 /**
01882   * @}
01883   */
01884
01885 #if defined(STM32F105xC) || defined(STM32F107xC)
01886 /** @addtogroup RCCEx_Exported_Functions_Group2
01887   * @{
01888   */
01889 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit);
01890 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
01891
01892 /**
01893   * @}
01894   */
01895
01896 /** @addtogroup RCCEx_Exported_Functions_Group3
01897   * @{
01898   */
01899 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef  *PLL2Init);
01900 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
01901
01902 /**
01903   * @}
01904   */
01905 #endif /* STM32F105xC || STM32F107xC */
01906
01907 /**
01908   * @}
01909   */
01910
01911 /**
01912   * @}
01913   */
01914
01915 /**
01916   * @}
01917   */
01918
01919 #ifdef __cplusplus
01920 }
01921 #endif
01922
01923 #endif /* __STM32F1xx_HAL_RCC_EX_H */
01924
01925 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
01926
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rtc.c Source File

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stm32f1xx_hal_rtc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_rtc.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   RTC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Real Time Clock (RTC) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + RTC Time and Date functions
00012   *           + RTC Alarm functions
00013   *           + Peripheral Control functions
00014   *           + Peripheral State functions
00015   *
00016   @verbatim
00017   ==============================================================================
00018                   ##### How to use this driver #####
00019   ==================================================================
00020   [..]
00021     (+) Enable the RTC domain access (see description in the section above).
00022     (+) Configure the RTC Prescaler (Asynchronous prescaler to generate RTC 1Hz time base)
00023         using the HAL_RTC_Init() function.
00024
00025   *** Time and Date configuration ***
00026   ===================================
00027   [..]
00028     (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
00029         and HAL_RTC_SetDate() functions.
00030     (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
00031
00032   *** Alarm configuration ***
00033   ===========================
00034   [..]
00035     (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
00036         You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
00037     (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
00038
00039   *** Tamper configuration ***
00040   ============================
00041   [..]
00042     (+) Enable the RTC Tamper and configure the Tamper Level using the
00043         HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
00044         mode using HAL_RTCEx_SetTamper_IT() function.
00045     (+) The TAMPER1 alternate function can be mapped to PC13
00046
00047   *** Backup Data Registers configuration ***
00048   ===========================================
00049   [..]
00050     (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
00051         function.
00052     (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
00053         function.
00054
00055                   ##### WARNING: Drivers Restrictions  #####
00056   ==================================================================
00057   [..] RTC version used on STM32F1 families is version V1. All the features supported by V2
00058        (other families) will be not supported on F1.
00059   [..] As on V2, main RTC features are managed by HW. But on F1, date feature is completely
00060        managed by SW.
00061   [..] Then, there are some restrictions compared to other families:
00062     (+) Only format 24 hours supported in HAL (format 12 hours not supported)
00063     (+) Date is saved in SRAM. Then, when MCU is in STOP or STANDBY mode, date will be lost.
00064         User should implement a way to save date before entering in low power mode (an
00065         example is provided with firmware package based on backup registers)
00066     (+) Date is automatically updated each time a HAL_RTC_GetTime or HAL_RTC_GetDate is called.
00067     (+) Alarm detection is limited to 1 day. It will expire only 1 time (no alarm repetition, need
00068         to program a new alarm)
00069
00070               ##### Backup Domain Operating Condition #####
00071   ==============================================================================
00072   [..] The real-time clock (RTC) and the RTC backup registers can be powered
00073        from the VBAT voltage when the main VDD supply is powered off.
00074        To retain the content of the RTC backup registers and supply the RTC
00075        when VDD is turned off, VBAT pin can be connected to an optional
00076        standby voltage supplied by a battery or by another source.
00077
00078   [..] To allow the RTC operating even when the main digital supply (VDD) is turned
00079        off, the VBAT pin powers the following blocks:
00080     (+) The RTC
00081     (+) The LSE oscillator
00082     (+) PC13 I/O
00083
00084   [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
00085        the following pins are available:
00086     (+) PC13 can be used as a Tamper pin
00087
00088   [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
00089        because VDD is not present), the following pins are available:
00090     (+) PC13 can be used as the Tamper pin
00091
00092                    ##### Backup Domain Reset #####
00093   ==================================================================
00094   [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
00095        to their reset values.
00096   [..] A backup domain reset is generated when one of the following events occurs:
00097     (#) Software reset, triggered by setting the BDRST bit in the
00098         RCC Backup domain control register (RCC_BDCR).
00099     (#) VDD or VBAT power on, if both supplies have previously been powered off.
00100     (#) Tamper detection event resets all data backup registers.
00101
00102                    ##### Backup Domain Access #####
00103   ==================================================================
00104   [..] After reset, the backup domain (RTC registers, RTC backup data
00105        registers and backup SRAM) is protected against possible unwanted write
00106        accesses.
00107   [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
00108     (+) Call the function HAL_RCCEx_PeriphCLKConfig in using RCC_PERIPHCLK_RTC for
00109         PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSE)
00110     (+) Enable the BKP clock in using __HAL_RCC_BKP_CLK_ENABLE()
00111
00112                   ##### RTC and low power modes #####
00113   ==================================================================
00114   [..] The MCU can be woken up from a low power mode by an RTC alternate
00115        function.
00116   [..] The RTC alternate functions are the RTC alarms (Alarm A),
00117        and RTC tamper event detection.
00118        These RTC alternate functions can wake up the system from the Stop and
00119        Standby low power modes.
00120   [..] The system can also wake up from low power modes without depending
00121        on an external interrupt (Auto-wakeup mode), by using the RTC alarm.
00122
00123    @endverbatim
00124   ******************************************************************************
00125   * @attention
00126   *
00127   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00128   *
00129   * Redistribution and use in source and binary forms, with or without modification,
00130   * are permitted provided that the following conditions are met:
00131   *   1. Redistributions of source code must retain the above copyright notice,
00132   *      this list of conditions and the following disclaimer.
00133   *   2. Redistributions in binary form must reproduce the above copyright notice,
00134   *      this list of conditions and the following disclaimer in the documentation
00135   *      and/or other materials provided with the distribution.
00136   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00137   *      may be used to endorse or promote products derived from this software
00138   *      without specific prior written permission.
00139   *
00140   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00141   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00142   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00143   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00144   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00145   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00146   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00147   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00148   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00149   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00150   *
00151   ******************************************************************************
00152   */
00153
00154 /* Includes ------------------------------------------------------------------*/
00155 #include "stm32f1xx_hal.h"
00156
00157 /** @addtogroup STM32F1xx_HAL_Driver
00158   * @{
00159   */
00160
00161 /** @defgroup RTC RTC
00162   * @brief RTC HAL module driver
00163   * @{
00164   */
00165
00166 #ifdef HAL_RTC_MODULE_ENABLED
00167
00168 /* Private typedef -----------------------------------------------------------*/
00169 /* Private define ------------------------------------------------------------*/
00170 /** @defgroup RTC_Private_Constants RTC Private Constants
00171   * @{
00172   */
00173 #define RTC_ALARM_RESETVALUE_REGISTER    (uint16_t)0xFFFF
00174 #define RTC_ALARM_RESETVALUE             0xFFFFFFFFU
00175
00176 /**
00177   * @}
00178   */
00179
00180 /* Private macro -------------------------------------------------------------*/
00181 /** @defgroup RTC_Private_Macros RTC Private Macros
00182   * @{
00183   */
00184 /**
00185   * @}
00186   */
00187
00188 /* Private variables ---------------------------------------------------------*/
00189 /* Private function prototypes -----------------------------------------------*/
00190 /** @defgroup RTC_Private_Functions RTC Private Functions
00191   * @{
00192   */
00193 static uint32_t           RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc);
00194 static HAL_StatusTypeDef  RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter);
00195 static uint32_t           RTC_ReadAlarmCounter(RTC_HandleTypeDef* hrtc);
00196 static HAL_StatusTypeDef  RTC_WriteAlarmCounter(RTC_HandleTypeDef* hrtc, uint32_t AlarmCounter);
00197 static HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
00198 static HAL_StatusTypeDef  RTC_ExitInitMode(RTC_HandleTypeDef* hrtc);
00199 static uint8_t            RTC_ByteToBcd2(uint8_t Value);
00200 static uint8_t            RTC_Bcd2ToByte(uint8_t Value);
00201 static uint8_t            RTC_IsLeapYear(uint16_t nYear);
00202 static void               RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed);
00203 static uint8_t            RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay);
00204
00205 /**
00206   * @}
00207   */
00208
00209 /* Private functions ---------------------------------------------------------*/
00210 /** @defgroup RTC_Exported_Functions RTC Exported Functions
00211   * @{
00212   */
00213
00214 /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
00215  *  @brief    Initialization and Configuration functions
00216  *
00217 @verbatim
00218  ===============================================================================
00219               ##### Initialization and de-initialization functions #####
00220  ===============================================================================
00221    [..] This section provides functions allowing to initialize and configure the
00222          RTC Prescaler (Asynchronous), disable RTC registers Write protection,
00223          enter and exit the RTC initialization mode,
00224          RTC registers synchronization check and reference clock detection enable.
00225          (#) The RTC Prescaler should be programmed to generate the RTC 1Hz time base.
00226          (#) All RTC registers are Write protected. Writing to the RTC registers
00227              is enabled by setting the CNF bit in the RTC_CRL register.
00228          (#) To read the calendar after wakeup from low power modes (Standby or Stop)
00229              the software must first wait for the RSF bit (Register Synchronized Flag)
00230              in the RTC_CRL register to be set by hardware.
00231              The HAL_RTC_WaitForSynchro() function implements the above software
00232              sequence (RSF clear and RSF check).
00233
00234 @endverbatim
00235   * @{
00236   */
00237
00238 /**
00239   * @brief  Initializes the RTC peripheral
00240   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
00241   *                the configuration information for RTC.
00242   * @retval HAL status
00243   */
00244 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
00245 {
00246   uint32_t prescaler = 0U;
00247   /* Check input parameters */
00248   if(hrtc == NULL)
00249   {
00250      return HAL_ERROR;
00251   }
00252
00253   /* Check the parameters */
00254   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00255   assert_param(IS_RTC_CALIB_OUTPUT(hrtc->Init.OutPut));
00256   assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
00257
00258   if(hrtc->State == HAL_RTC_STATE_RESET)
00259   {
00260     /* Allocate lock resource and initialize it */
00261     hrtc->Lock = HAL_UNLOCKED;
00262
00263     /* Initialize RTC MSP */
00264     HAL_RTC_MspInit(hrtc);
00265   }
00266
00267   /* Set RTC state */
00268   hrtc->State = HAL_RTC_STATE_BUSY;
00269
00270   /* Waiting for synchro */
00271   if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
00272   {
00273     /* Set RTC state */
00274     hrtc->State = HAL_RTC_STATE_ERROR;
00275
00276     return HAL_ERROR;
00277   }
00278
00279   /* Set Initialization mode */
00280   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00281   {
00282     /* Set RTC state */
00283     hrtc->State = HAL_RTC_STATE_ERROR;
00284
00285     return HAL_ERROR;
00286   }
00287   else
00288   {
00289     /* Clear Flags Bits */
00290     CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_OW | RTC_FLAG_ALRAF | RTC_FLAG_SEC));
00291
00292     if(hrtc->Init.OutPut != RTC_OUTPUTSOURCE_NONE)
00293     {
00294       /* Disable the selected Tamper pin */
00295       CLEAR_BIT(BKP->CR, BKP_CR_TPE);
00296     }
00297
00298     /* Set the signal which will be routed to RTC Tamper pin*/
00299     MODIFY_REG(BKP->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), hrtc->Init.OutPut);
00300
00301     if (hrtc->Init.AsynchPrediv != RTC_AUTO_1_SECOND)
00302     {
00303       /* RTC Prescaler provided directly by end-user*/
00304       prescaler = hrtc->Init.AsynchPrediv;
00305     }
00306     else
00307     {
00308       /* RTC Prescaler will be automatically calculated to get 1 second timebase */
00309       /* Get the RTCCLK frequency */
00310       prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC);
00311
00312       /* Check that RTC clock is enabled*/
00313       if (prescaler == 0U)
00314       {
00315         /* Should not happen. Frequency is not available*/
00316         hrtc->State = HAL_RTC_STATE_ERROR;
00317         return HAL_ERROR;
00318       }
00319       else
00320       {
00321         /* RTC period = RTCCLK/(RTC_PR + 1) */
00322         prescaler = prescaler - 1U;
00323       }
00324     }
00325
00326     /* Configure the RTC_PRLH / RTC_PRLL */
00327     MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U));
00328     MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL));
00329
00330     /* Wait for synchro */
00331     if(RTC_ExitInitMode(hrtc) != HAL_OK)
00332     {
00333       hrtc->State = HAL_RTC_STATE_ERROR;
00334
00335       return HAL_ERROR;
00336     }
00337
00338     /* Initialize date to 1st of January 2000 */
00339     hrtc->DateToUpdate.Year = 0x00U;
00340     hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY;
00341     hrtc->DateToUpdate.Date = 0x01U;
00342
00343     /* Set RTC state */
00344     hrtc->State = HAL_RTC_STATE_READY;
00345
00346     return HAL_OK;
00347   }
00348 }
00349
00350 /**
00351   * @brief  DeInitializes the RTC peripheral
00352   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
00353   *                the configuration information for RTC.
00354   * @note   This function does not reset the RTC Backup Data registers.
00355   * @retval HAL status
00356   */
00357 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
00358 {
00359   /* Check input parameters */
00360   if(hrtc == NULL)
00361   {
00362      return HAL_ERROR;
00363   }
00364
00365   /* Check the parameters */
00366   assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
00367
00368   /* Set RTC state */
00369   hrtc->State = HAL_RTC_STATE_BUSY;
00370
00371   /* Set Initialization mode */
00372   if(RTC_EnterInitMode(hrtc) != HAL_OK)
00373   {
00374     /* Set RTC state */
00375     hrtc->State = HAL_RTC_STATE_ERROR;
00376
00377     /* Release Lock */
00378     __HAL_UNLOCK(hrtc);
00379
00380     return HAL_ERROR;
00381   }
00382   else
00383   {
00384     CLEAR_REG(hrtc->Instance->CNTL);
00385     CLEAR_REG(hrtc->Instance->CNTH);
00386     WRITE_REG(hrtc->Instance->PRLL, 0x00008000U);
00387     CLEAR_REG(hrtc->Instance->PRLH);
00388
00389     /* Reset All CRH/CRL bits */
00390     CLEAR_REG(hrtc->Instance->CRH);
00391     CLEAR_REG(hrtc->Instance->CRL);
00392
00393     if(RTC_ExitInitMode(hrtc) != HAL_OK)
00394     {
00395       hrtc->State = HAL_RTC_STATE_ERROR;
00396
00397       /* Process Unlocked */
00398       __HAL_UNLOCK(hrtc);
00399
00400       return HAL_ERROR;
00401     }
00402   }
00403
00404   /* Wait for synchro*/
00405   HAL_RTC_WaitForSynchro(hrtc);
00406
00407   /* Clear RSF flag */
00408   CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF);
00409
00410   /* De-Initialize RTC MSP */
00411   HAL_RTC_MspDeInit(hrtc);
00412
00413   hrtc->State = HAL_RTC_STATE_RESET;
00414
00415   /* Release Lock */
00416   __HAL_UNLOCK(hrtc);
00417
00418   return HAL_OK;
00419 }
00420
00421 /**
00422   * @brief  Initializes the RTC MSP.
00423   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
00424   *                the configuration information for RTC.
00425   * @retval None
00426   */
00427 __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
00428 {
00429   /* Prevent unused argument(s) compilation warning */
00430   UNUSED(hrtc);
00431   /* NOTE : This function Should not be modified, when the callback is needed,
00432             the HAL_RTC_MspInit could be implemented in the user file
00433    */
00434 }
00435
00436 /**
00437   * @brief  DeInitializes the RTC MSP.
00438   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
00439   *                the configuration information for RTC.
00440   * @retval None
00441   */
00442 __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
00443 {
00444   /* Prevent unused argument(s) compilation warning */
00445   UNUSED(hrtc);
00446   /* NOTE : This function Should not be modified, when the callback is needed,
00447             the HAL_RTC_MspDeInit could be implemented in the user file
00448    */
00449 }
00450
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup RTC_Exported_Functions_Group2 Time and Date functions
00456  *  @brief   RTC Time and Date functions
00457  *
00458 @verbatim
00459  ===============================================================================
00460                  ##### RTC Time and Date functions #####
00461  ===============================================================================
00462
00463  [..] This section provides functions allowing to configure Time and Date features
00464
00465 @endverbatim
00466   * @{
00467   */
00468
00469 /**
00470   * @brief  Sets RTC current time.
00471   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
00472   *                the configuration information for RTC.
00473   * @param  sTime: Pointer to Time structure
00474   * @param  Format: Specifies the format of the entered parameters.
00475   *          This parameter can be one of the following values:
00476   *            @arg RTC_FORMAT_BIN: Binary data format
00477   *            @arg RTC_FORMAT_BCD: BCD data format
00478   * @retval HAL status
00479   */
00480 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00481 {
00482   uint32_t counter_time = 0U, counter_alarm = 0U;
00483
00484   /* Check input parameters */
00485   if((hrtc == NULL) || (sTime == NULL))
00486   {
00487      return HAL_ERROR;
00488   }
00489
00490  /* Check the parameters */
00491   assert_param(IS_RTC_FORMAT(Format));
00492
00493   /* Process Locked */
00494   __HAL_LOCK(hrtc);
00495
00496   hrtc->State = HAL_RTC_STATE_BUSY;
00497
00498   if(Format == RTC_FORMAT_BIN)
00499   {
00500     assert_param(IS_RTC_HOUR24(sTime->Hours));
00501     assert_param(IS_RTC_MINUTES(sTime->Minutes));
00502     assert_param(IS_RTC_SECONDS(sTime->Seconds));
00503
00504     counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \
00505                         ((uint32_t)sTime->Minutes * 60U) + \
00506                         ((uint32_t)sTime->Seconds));
00507   }
00508   else
00509   {
00510     assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
00511     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
00512     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
00513
00514     counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \
00515               ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60U) + \
00516               ((uint32_t)(RTC_Bcd2ToByte(sTime->Seconds))));
00517   }
00518
00519   /* Write time counter in RTC registers */
00520   if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
00521   {
00522     /* Set RTC state */
00523     hrtc->State = HAL_RTC_STATE_ERROR;
00524
00525     /* Process Unlocked */
00526     __HAL_UNLOCK(hrtc);
00527
00528     return HAL_ERROR;
00529   }
00530   else
00531   {
00532     /* Clear Second and overflow flags */
00533     CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
00534
00535     /* Read current Alarm counter in RTC registers */
00536     counter_alarm = RTC_ReadAlarmCounter(hrtc);
00537
00538     /* Set again alarm to match with new time if enabled */
00539     if (counter_alarm != RTC_ALARM_RESETVALUE)
00540     {
00541       if(counter_alarm < counter_time)
00542       {
00543         /* Add 1 day to alarm counter*/
00544         counter_alarm += (uint32_t)(24U * 3600U);
00545
00546         /* Write new Alarm counter in RTC registers */
00547         if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
00548         {
00549           /* Set RTC state */
00550           hrtc->State = HAL_RTC_STATE_ERROR;
00551
00552           /* Process Unlocked */
00553           __HAL_UNLOCK(hrtc);
00554
00555           return HAL_ERROR;
00556         }
00557       }
00558     }
00559
00560     hrtc->State = HAL_RTC_STATE_READY;
00561
00562    __HAL_UNLOCK(hrtc);
00563
00564    return HAL_OK;
00565   }
00566 }
00567
00568 /**
00569   * @brief  Gets RTC current time.
00570   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
00571   *                the configuration information for RTC.
00572   * @param  sTime: Pointer to Time structure
00573   * @param  Format: Specifies the format of the entered parameters.
00574   *          This parameter can be one of the following values:
00575   *            @arg RTC_FORMAT_BIN: Binary data format
00576   *            @arg RTC_FORMAT_BCD: BCD data format
00577   * @retval HAL status
00578   */
00579 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
00580 {
00581   uint32_t counter_time = 0U, counter_alarm = 0U, days_elapsed = 0U, hours = 0U;
00582
00583   /* Check input parameters */
00584   if((hrtc == NULL) || (sTime == NULL))
00585   {
00586      return HAL_ERROR;
00587   }
00588
00589   /* Check the parameters */
00590   assert_param(IS_RTC_FORMAT(Format));
00591
00592   /* Check if counter overflow occurred */
00593   if (__HAL_RTC_OVERFLOW_GET_FLAG(hrtc, RTC_FLAG_OW))
00594   {
00595       return HAL_ERROR;
00596   }
00597
00598   /* Read the time counter*/
00599   counter_time = RTC_ReadTimeCounter(hrtc);
00600
00601   /* Fill the structure fields with the read parameters */
00602   hours = counter_time / 3600U;
00603   sTime->Minutes  = (uint8_t)((counter_time % 3600U) / 60U);
00604   sTime->Seconds  = (uint8_t)((counter_time % 3600U) % 60U);
00605
00606   if (hours >= 24U)
00607   {
00608     /* Get number of days elapsed from last calculation */
00609     days_elapsed = (hours / 24U);
00610
00611     /* Set Hours in RTC_TimeTypeDef structure*/
00612     sTime->Hours = (hours % 24U);
00613
00614     /* Read Alarm counter in RTC registers */
00615     counter_alarm = RTC_ReadAlarmCounter(hrtc);
00616
00617     /* Calculate remaining time to reach alarm (only if set and not yet expired)*/
00618     if ((counter_alarm != RTC_ALARM_RESETVALUE) && (counter_alarm > counter_time))
00619     {
00620       counter_alarm -= counter_time;
00621     }
00622     else
00623     {
00624       /* In case of counter_alarm < counter_time */
00625       /* Alarm expiration already occurred but alarm not deactivated */
00626       counter_alarm = RTC_ALARM_RESETVALUE;
00627     }
00628
00629     /* Set updated time in decreasing counter by number of days elapsed */
00630     counter_time -= (days_elapsed * 24U * 3600U);
00631
00632     /* Write time counter in RTC registers */
00633     if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
00634     {
00635       return HAL_ERROR;
00636     }
00637
00638     /* Set updated alarm to be set */
00639     if (counter_alarm != RTC_ALARM_RESETVALUE)
00640     {
00641       counter_alarm += counter_time;
00642
00643       /* Write time counter in RTC registers */
00644       if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
00645       {
00646         return HAL_ERROR;
00647       }
00648     }
00649     else
00650     {
00651       /* Alarm already occurred. Set it to reset values to avoid unexpected expiration */
00652       if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
00653       {
00654         return HAL_ERROR;
00655       }
00656     }
00657
00658     /* Update date */
00659     RTC_DateUpdate(hrtc, days_elapsed);
00660   }
00661   else
00662   {
00663     sTime->Hours = hours;
00664   }
00665
00666   /* Check the input parameters format */
00667   if(Format != RTC_FORMAT_BIN)
00668   {
00669     /* Convert the time structure parameters to BCD format */
00670     sTime->Hours    = (uint8_t)RTC_ByteToBcd2(sTime->Hours);
00671     sTime->Minutes  = (uint8_t)RTC_ByteToBcd2(sTime->Minutes);
00672     sTime->Seconds  = (uint8_t)RTC_ByteToBcd2(sTime->Seconds);
00673   }
00674
00675   return HAL_OK;
00676 }
00677
00678
00679 /**
00680   * @brief  Sets RTC current date.
00681   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
00682   *                the configuration information for RTC.
00683   * @param  sDate: Pointer to date structure
00684   * @param  Format: specifies the format of the entered parameters.
00685   *          This parameter can be one of the following values:
00686   *            @arg RTC_FORMAT_BIN: Binary data format
00687   *            @arg RTC_FORMAT_BCD: BCD data format
00688   * @retval HAL status
00689   */
00690 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00691 {
00692   uint32_t counter_time = 0U, counter_alarm = 0U, hours = 0U;
00693
00694   /* Check input parameters */
00695   if((hrtc == NULL) || (sDate == NULL))
00696   {
00697      return HAL_ERROR;
00698   }
00699
00700   /* Check the parameters */
00701   assert_param(IS_RTC_FORMAT(Format));
00702
00703  /* Process Locked */
00704  __HAL_LOCK(hrtc);
00705
00706   hrtc->State = HAL_RTC_STATE_BUSY;
00707
00708   if(Format == RTC_FORMAT_BIN)
00709   {
00710     assert_param(IS_RTC_YEAR(sDate->Year));
00711     assert_param(IS_RTC_MONTH(sDate->Month));
00712     assert_param(IS_RTC_DATE(sDate->Date));
00713
00714     /* Change the current date */
00715     hrtc->DateToUpdate.Year  = sDate->Year;
00716     hrtc->DateToUpdate.Month = sDate->Month;
00717     hrtc->DateToUpdate.Date  = sDate->Date;
00718   }
00719   else
00720   {
00721     assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
00722     assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
00723     assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
00724
00725     /* Change the current date */
00726     hrtc->DateToUpdate.Year  = RTC_Bcd2ToByte(sDate->Year);
00727     hrtc->DateToUpdate.Month = RTC_Bcd2ToByte(sDate->Month);
00728     hrtc->DateToUpdate.Date  = RTC_Bcd2ToByte(sDate->Date);
00729   }
00730
00731   /* WeekDay set by user can be ignored because automatically calculated */
00732   hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(hrtc->DateToUpdate.Year, hrtc->DateToUpdate.Month, hrtc->DateToUpdate.Date);
00733   sDate->WeekDay = hrtc->DateToUpdate.WeekDay;
00734
00735   /* Reset time to be aligned on the same day */
00736   /* Read the time counter*/
00737   counter_time = RTC_ReadTimeCounter(hrtc);
00738
00739   /* Fill the structure fields with the read parameters */
00740   hours = counter_time / 3600U;
00741   if (hours > 24U)
00742   {
00743     /* Set updated time in decreasing counter by number of days elapsed */
00744     counter_time -= ((hours / 24U) * 24U * 3600U);
00745     /* Write time counter in RTC registers */
00746     if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
00747     {
00748       /* Set RTC state */
00749       hrtc->State = HAL_RTC_STATE_ERROR;
00750
00751       /* Process Unlocked */
00752       __HAL_UNLOCK(hrtc);
00753
00754       return HAL_ERROR;
00755     }
00756
00757     /* Read current Alarm counter in RTC registers */
00758     counter_alarm = RTC_ReadAlarmCounter(hrtc);
00759
00760     /* Set again alarm to match with new time if enabled */
00761     if (counter_alarm != RTC_ALARM_RESETVALUE)
00762     {
00763       if(counter_alarm < counter_time)
00764       {
00765         /* Add 1 day to alarm counter*/
00766         counter_alarm += (uint32_t)(24U * 3600U);
00767
00768         /* Write new Alarm counter in RTC registers */
00769         if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
00770         {
00771           /* Set RTC state */
00772           hrtc->State = HAL_RTC_STATE_ERROR;
00773
00774           /* Process Unlocked */
00775           __HAL_UNLOCK(hrtc);
00776
00777           return HAL_ERROR;
00778         }
00779       }
00780     }
00781
00782
00783   }
00784
00785   hrtc->State = HAL_RTC_STATE_READY ;
00786
00787   /* Process Unlocked */
00788   __HAL_UNLOCK(hrtc);
00789
00790   return HAL_OK;
00791 }
00792
00793 /**
00794   * @brief  Gets RTC current date.
00795   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
00796   *                the configuration information for RTC.
00797   * @param  sDate: Pointer to Date structure
00798   * @param  Format: Specifies the format of the entered parameters.
00799   *          This parameter can be one of the following values:
00800   *            @arg RTC_FORMAT_BIN:  Binary data format
00801   *            @arg RTC_FORMAT_BCD:  BCD data format
00802   * @retval HAL status
00803   */
00804 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
00805 {
00806   RTC_TimeTypeDef stime = {0U};
00807
00808   /* Check input parameters */
00809   if((hrtc == NULL) || (sDate == NULL))
00810   {
00811      return HAL_ERROR;
00812   }
00813
00814   /* Check the parameters */
00815   assert_param(IS_RTC_FORMAT(Format));
00816
00817   /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
00818   if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
00819   {
00820     return HAL_ERROR;
00821   }
00822
00823   /* Fill the structure fields with the read parameters */
00824   sDate->WeekDay  = hrtc->DateToUpdate.WeekDay;
00825   sDate->Year     = hrtc->DateToUpdate.Year;
00826   sDate->Month    = hrtc->DateToUpdate.Month;
00827   sDate->Date     = hrtc->DateToUpdate.Date;
00828
00829   /* Check the input parameters format */
00830   if(Format != RTC_FORMAT_BIN)
00831   {
00832     /* Convert the date structure parameters to BCD format */
00833     sDate->Year   = (uint8_t)RTC_ByteToBcd2(sDate->Year);
00834     sDate->Month  = (uint8_t)RTC_ByteToBcd2(sDate->Month);
00835     sDate->Date   = (uint8_t)RTC_ByteToBcd2(sDate->Date);
00836   }
00837   return HAL_OK;
00838 }
00839
00840 /**
00841   * @}
00842   */
00843
00844 /** @defgroup RTC_Exported_Functions_Group3 Alarm functions
00845  *  @brief   RTC Alarm functions
00846  *
00847 @verbatim
00848  ===============================================================================
00849                  ##### RTC Alarm functions #####
00850  ===============================================================================
00851
00852  [..] This section provides functions allowing to configure Alarm feature
00853
00854 @endverbatim
00855   * @{
00856   */
00857
00858 /**
00859   * @brief  Sets the specified RTC Alarm.
00860   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
00861   *                the configuration information for RTC.
00862   * @param  sAlarm: Pointer to Alarm structure
00863   * @param  Format: Specifies the format of the entered parameters.
00864   *          This parameter can be one of the following values:
00865   *             @arg RTC_FORMAT_BIN: Binary data format
00866   *             @arg RTC_FORMAT_BCD: BCD data format
00867   * @retval HAL status
00868   */
00869 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00870 {
00871   uint32_t counter_alarm = 0U, counter_time;
00872   RTC_TimeTypeDef stime = {0U};
00873
00874   /* Check input parameters */
00875   if((hrtc == NULL) || (sAlarm == NULL))
00876   {
00877      return HAL_ERROR;
00878   }
00879
00880   /* Check the parameters */
00881   assert_param(IS_RTC_FORMAT(Format));
00882   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00883
00884   /* Process Locked */
00885   __HAL_LOCK(hrtc);
00886
00887   hrtc->State = HAL_RTC_STATE_BUSY;
00888
00889   /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
00890   if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
00891   {
00892     return HAL_ERROR;
00893   }
00894
00895   /* Convert time in seconds */
00896   counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \
00897                       ((uint32_t)stime.Minutes * 60U) + \
00898                       ((uint32_t)stime.Seconds));
00899
00900   if(Format == RTC_FORMAT_BIN)
00901   {
00902     assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
00903     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
00904     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
00905
00906     counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \
00907                         ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \
00908                         ((uint32_t)sAlarm->AlarmTime.Seconds));
00909   }
00910   else
00911   {
00912     assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
00913     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
00914     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
00915
00916     counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \
00917               ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \
00918               ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
00919   }
00920
00921   /* Check that requested alarm should expire in the same day (otherwise add 1 day) */
00922   if (counter_alarm < counter_time)
00923   {
00924     /* Add 1 day to alarm counter*/
00925     counter_alarm += (uint32_t)(24U * 3600U);
00926   }
00927
00928   /* Write Alarm counter in RTC registers */
00929   if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
00930   {
00931     /* Set RTC state */
00932     hrtc->State = HAL_RTC_STATE_ERROR;
00933
00934     /* Process Unlocked */
00935     __HAL_UNLOCK(hrtc);
00936
00937     return HAL_ERROR;
00938   }
00939   else
00940   {
00941     hrtc->State = HAL_RTC_STATE_READY;
00942
00943    __HAL_UNLOCK(hrtc);
00944
00945    return HAL_OK;
00946   }
00947 }
00948
00949 /**
00950   * @brief  Sets the specified RTC Alarm with Interrupt
00951   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
00952   *                the configuration information for RTC.
00953   * @param  sAlarm: Pointer to Alarm structure
00954   * @param  Format: Specifies the format of the entered parameters.
00955   *          This parameter can be one of the following values:
00956   *             @arg RTC_FORMAT_BIN: Binary data format
00957   *             @arg RTC_FORMAT_BCD: BCD data format
00958   * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
00959   * @retval HAL status
00960   */
00961 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
00962 {
00963   uint32_t counter_alarm = 0U, counter_time;
00964   RTC_TimeTypeDef stime = {0U};
00965
00966   /* Check input parameters */
00967   if((hrtc == NULL) || (sAlarm == NULL))
00968   {
00969      return HAL_ERROR;
00970   }
00971
00972   /* Check the parameters */
00973   assert_param(IS_RTC_FORMAT(Format));
00974   assert_param(IS_RTC_ALARM(sAlarm->Alarm));
00975
00976   /* Process Locked */
00977   __HAL_LOCK(hrtc);
00978
00979   hrtc->State = HAL_RTC_STATE_BUSY;
00980
00981   /* Call HAL_RTC_GetTime function to update date if counter higher than 24 hours */
00982   if (HAL_RTC_GetTime(hrtc, &stime, RTC_FORMAT_BIN) != HAL_OK)
00983   {
00984     return HAL_ERROR;
00985   }
00986
00987   /* Convert time in seconds */
00988   counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \
00989                       ((uint32_t)stime.Minutes * 60U) + \
00990                       ((uint32_t)stime.Seconds));
00991
00992   if(Format == RTC_FORMAT_BIN)
00993   {
00994     assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
00995     assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
00996     assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
00997
00998     counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \
00999       ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \
01000         ((uint32_t)sAlarm->AlarmTime.Seconds));
01001   }
01002   else
01003   {
01004     assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
01005     assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
01006     assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01007
01008     counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \
01009                      ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \
01010                      ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
01011   }
01012
01013   /* Check that requested alarm should expire in the same day (otherwise add 1 day) */
01014   if (counter_alarm < counter_time)
01015   {
01016     /* Add 1 day to alarm counter*/
01017     counter_alarm += (uint32_t)(24U * 3600U);
01018   }
01019
01020   /* Write alarm counter in RTC registers */
01021   if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
01022   {
01023     /* Set RTC state */
01024     hrtc->State = HAL_RTC_STATE_ERROR;
01025
01026     /* Process Unlocked */
01027     __HAL_UNLOCK(hrtc);
01028
01029     return HAL_ERROR;
01030   }
01031   else
01032   {
01033     /* Clear flag alarm A */
01034     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01035
01036     /* Configure the Alarm interrupt */
01037     __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
01038
01039     /* RTC Alarm Interrupt Configuration: EXTI configuration */
01040     __HAL_RTC_ALARM_EXTI_ENABLE_IT();
01041
01042     __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
01043
01044     hrtc->State = HAL_RTC_STATE_READY;
01045
01046    __HAL_UNLOCK(hrtc);
01047
01048    return HAL_OK;
01049   }
01050 }
01051
01052 /**
01053   * @brief  Gets the RTC Alarm value and masks.
01054   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01055   *                the configuration information for RTC.
01056   * @param  sAlarm: Pointer to Date structure
01057   * @param  Alarm: Specifies the Alarm.
01058   *          This parameter can be one of the following values:
01059   *             @arg RTC_ALARM_A: Alarm
01060   * @param  Format: Specifies the format of the entered parameters.
01061   *          This parameter can be one of the following values:
01062   *             @arg RTC_FORMAT_BIN: Binary data format
01063   *             @arg RTC_FORMAT_BCD: BCD data format
01064   * @retval HAL status
01065   */
01066 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
01067 {
01068   uint32_t counter_alarm = 0U;
01069
01070   /* Check input parameters */
01071   if((hrtc == NULL) || (sAlarm == NULL))
01072   {
01073     return HAL_ERROR;
01074   }
01075
01076   /* Check the parameters */
01077   assert_param(IS_RTC_FORMAT(Format));
01078   assert_param(IS_RTC_ALARM(Alarm));
01079
01080   /* Read Alarm counter in RTC registers */
01081   counter_alarm = RTC_ReadAlarmCounter(hrtc);
01082
01083   /* Fill the structure with the read parameters */
01084   /* Set hours in a day range (between 0 to 24)*/
01085   sAlarm->AlarmTime.Hours   = (uint32_t)((counter_alarm / 3600U) % 24U);
01086   sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600U) / 60U);
01087   sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600U) % 60U);
01088
01089   if(Format != RTC_FORMAT_BIN)
01090   {
01091     sAlarm->AlarmTime.Hours   = RTC_ByteToBcd2(sAlarm->AlarmTime.Hours);
01092     sAlarm->AlarmTime.Minutes = RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes);
01093     sAlarm->AlarmTime.Seconds = RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds);
01094   }
01095
01096   return HAL_OK;
01097 }
01098
01099 /**
01100   * @brief  Deactive the specified RTC Alarm
01101   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01102   *                the configuration information for RTC.
01103   * @param  Alarm: Specifies the Alarm.
01104   *          This parameter can be one of the following values:
01105   *            @arg RTC_ALARM_A:  AlarmA
01106   * @retval HAL status
01107   */
01108 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
01109 {
01110   /* Check the parameters */
01111   assert_param(IS_RTC_ALARM(Alarm));
01112
01113   /* Check input parameters */
01114   if(hrtc == NULL)
01115   {
01116      return HAL_ERROR;
01117   }
01118
01119   /* Process Locked */
01120   __HAL_LOCK(hrtc);
01121
01122   hrtc->State = HAL_RTC_STATE_BUSY;
01123
01124   /* In case of interrupt mode is used, the interrupt source must disabled */
01125   __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
01126
01127   /* Set Initialization mode */
01128   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01129   {
01130     /* Set RTC state */
01131     hrtc->State = HAL_RTC_STATE_ERROR;
01132
01133     /* Process Unlocked */
01134     __HAL_UNLOCK(hrtc);
01135
01136     return HAL_ERROR;
01137   }
01138   else
01139   {
01140     /* Clear flag alarm A */
01141     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01142
01143     /* Set to default values ALRH & ALRL registers */
01144     WRITE_REG(hrtc->Instance->ALRH, RTC_ALARM_RESETVALUE_REGISTER);
01145     WRITE_REG(hrtc->Instance->ALRL, RTC_ALARM_RESETVALUE_REGISTER);
01146
01147     /* RTC Alarm Interrupt Configuration: Disable EXTI configuration */
01148     __HAL_RTC_ALARM_EXTI_DISABLE_IT();
01149
01150     /* Wait for synchro */
01151     if(RTC_ExitInitMode(hrtc) != HAL_OK)
01152     {
01153       hrtc->State = HAL_RTC_STATE_ERROR;
01154
01155       /* Process Unlocked */
01156       __HAL_UNLOCK(hrtc);
01157
01158       return HAL_ERROR;
01159     }
01160   }
01161   hrtc->State = HAL_RTC_STATE_READY;
01162
01163   /* Process Unlocked */
01164   __HAL_UNLOCK(hrtc);
01165
01166   return HAL_OK;
01167 }
01168
01169 /**
01170   * @brief  This function handles Alarm interrupt request.
01171   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01172   *                the configuration information for RTC.
01173   * @retval None
01174   */
01175 void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
01176 {
01177   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA))
01178   {
01179     /* Get the status of the Interrupt */
01180     if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET)
01181     {
01182       /* AlarmA callback */
01183       HAL_RTC_AlarmAEventCallback(hrtc);
01184
01185       /* Clear the Alarm interrupt pending bit */
01186       __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
01187     }
01188   }
01189
01190   /* Clear the EXTI's line Flag for RTC Alarm */
01191   __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
01192
01193   /* Change RTC state */
01194   hrtc->State = HAL_RTC_STATE_READY;
01195 }
01196
01197 /**
01198   * @brief  Alarm A callback.
01199   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01200   *                the configuration information for RTC.
01201   * @retval None
01202   */
01203 __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
01204 {
01205   /* Prevent unused argument(s) compilation warning */
01206   UNUSED(hrtc);
01207   /* NOTE : This function Should not be modified, when the callback is needed,
01208             the HAL_RTC_AlarmAEventCallback could be implemented in the user file
01209    */
01210 }
01211
01212 /**
01213   * @brief  This function handles AlarmA Polling request.
01214   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01215   *                the configuration information for RTC.
01216   * @param  Timeout: Timeout duration
01217   * @retval HAL status
01218   */
01219 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
01220 {
01221   uint32_t tickstart = HAL_GetTick();
01222
01223   /* Check input parameters */
01224   if(hrtc == NULL)
01225   {
01226      return HAL_ERROR;
01227   }
01228
01229   while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
01230   {
01231     if(Timeout != HAL_MAX_DELAY)
01232     {
01233       if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
01234       {
01235         hrtc->State = HAL_RTC_STATE_TIMEOUT;
01236         return HAL_TIMEOUT;
01237       }
01238     }
01239   }
01240
01241   /* Clear the Alarm interrupt pending bit */
01242   __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
01243
01244   /* Change RTC state */
01245   hrtc->State = HAL_RTC_STATE_READY;
01246
01247   return HAL_OK;
01248 }
01249
01250 /**
01251   * @}
01252   */
01253
01254 /** @defgroup RTC_Exported_Functions_Group4 Peripheral State functions
01255  *  @brief   Peripheral State functions
01256  *
01257 @verbatim
01258  ===============================================================================
01259                      ##### Peripheral State functions #####
01260  ===============================================================================
01261     [..]
01262     This subsection provides functions allowing to
01263       (+) Get RTC state
01264
01265 @endverbatim
01266   * @{
01267   */
01268 /**
01269   * @brief  Returns the RTC state.
01270   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01271   *                the configuration information for RTC.
01272   * @retval HAL state
01273   */
01274 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
01275 {
01276   return hrtc->State;
01277 }
01278
01279 /**
01280   * @}
01281   */
01282
01283 /** @defgroup RTC_Exported_Functions_Group5 Peripheral Control functions
01284  *  @brief   Peripheral Control functions
01285  *
01286 @verbatim
01287  ===============================================================================
01288                      ##### Peripheral Control functions #####
01289  ===============================================================================
01290     [..]
01291     This subsection provides functions allowing to
01292       (+) Wait for RTC Time and Date Synchronization
01293
01294 @endverbatim
01295   * @{
01296   */
01297
01298 /**
01299   * @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
01300   *   are synchronized with RTC APB clock.
01301   * @note   This function must be called before any read operation after an APB reset
01302   *   or an APB clock stop.
01303   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01304   *                the configuration information for RTC.
01305   * @retval HAL status
01306   */
01307 HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
01308 {
01309   uint32_t tickstart = 0U;
01310
01311   /* Check input parameters */
01312   if(hrtc == NULL)
01313   {
01314      return HAL_ERROR;
01315   }
01316
01317   /* Clear RSF flag */
01318   CLEAR_BIT(hrtc->Instance->CRL, RTC_FLAG_RSF);
01319
01320   tickstart = HAL_GetTick();
01321
01322   /* Wait the registers to be synchronised */
01323   while((hrtc->Instance->CRL & RTC_FLAG_RSF) == (uint32_t)RESET)
01324   {
01325     if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
01326     {
01327       return HAL_TIMEOUT;
01328     }
01329   }
01330
01331   return HAL_OK;
01332 }
01333
01334 /**
01335   * @}
01336   */
01337
01338
01339 /**
01340   * @}
01341   */
01342
01343 /** @addtogroup RTC_Private_Functions
01344   * @{
01345   */
01346
01347
01348 /**
01349   * @brief  Read the time counter available in RTC_CNT registers.
01350   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01351   *                the configuration information for RTC.
01352   * @retval Time counter
01353   */
01354 static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc)
01355 {
01356   uint16_t high1 = 0U, high2 = 0U, low = 0U;
01357   uint32_t timecounter = 0U;
01358
01359   high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
01360   low   = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT);
01361   high2 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
01362
01363   if (high1 != high2)
01364   { /* In this case the counter roll over during reading of CNTL and CNTH registers,
01365        read again CNTL register then return the counter value */
01366     timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT));
01367   }
01368   else
01369   { /* No counter roll over during reading of CNTL and CNTH registers, counter
01370        value is equal to first value of CNTL and CNTH */
01371     timecounter = (((uint32_t) high1 << 16U) | low);
01372   }
01373
01374   return timecounter;
01375 }
01376
01377 /**
01378   * @brief  Write the time counter in RTC_CNT registers.
01379   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01380   *                the configuration information for RTC.
01381   * @param  TimeCounter: Counter to write in RTC_CNT registers
01382   * @retval HAL status
01383   */
01384 static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter)
01385 {
01386   HAL_StatusTypeDef status = HAL_OK;
01387
01388   /* Set Initialization mode */
01389   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01390   {
01391     status = HAL_ERROR;
01392   }
01393   else
01394   {
01395     /* Set RTC COUNTER MSB word */
01396     WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U));
01397     /* Set RTC COUNTER LSB word */
01398     WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT));
01399
01400     /* Wait for synchro */
01401     if(RTC_ExitInitMode(hrtc) != HAL_OK)
01402     {
01403       status = HAL_ERROR;
01404     }
01405   }
01406
01407   return status;
01408 }
01409
01410 /**
01411   * @brief  Read the time counter available in RTC_ALR registers.
01412   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01413   *                the configuration information for RTC.
01414   * @retval Time counter
01415   */
01416 static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef* hrtc)
01417 {
01418   uint16_t high1 = 0U, low = 0U;
01419
01420   high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT);
01421   low   = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT);
01422
01423   return (((uint32_t) high1 << 16U) | low);
01424 }
01425
01426 /**
01427   * @brief  Write the time counter in RTC_ALR registers.
01428   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01429   *                the configuration information for RTC.
01430   * @param  AlarmCounter: Counter to write in RTC_ALR registers
01431   * @retval HAL status
01432   */
01433 static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef* hrtc, uint32_t AlarmCounter)
01434 {
01435   HAL_StatusTypeDef status = HAL_OK;
01436
01437   /* Set Initialization mode */
01438   if(RTC_EnterInitMode(hrtc) != HAL_OK)
01439   {
01440     status = HAL_ERROR;
01441   }
01442   else
01443   {
01444     /* Set RTC COUNTER MSB word */
01445     WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16U));
01446     /* Set RTC COUNTER LSB word */
01447     WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR));
01448
01449     /* Wait for synchro */
01450     if(RTC_ExitInitMode(hrtc) != HAL_OK)
01451     {
01452       status = HAL_ERROR;
01453     }
01454   }
01455
01456   return status;
01457 }
01458
01459 /**
01460   * @brief  Enters the RTC Initialization mode.
01461   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01462   *                the configuration information for RTC.
01463   * @retval HAL status
01464   */
01465 static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
01466 {
01467   uint32_t tickstart = 0U;
01468
01469   tickstart = HAL_GetTick();
01470   /* Wait till RTC is in INIT state and if Time out is reached exit */
01471   while((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
01472   {
01473     if((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
01474     {
01475       return HAL_TIMEOUT;
01476     }
01477   }
01478
01479   /* Disable the write protection for RTC registers */
01480   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
01481
01482
01483   return HAL_OK;
01484 }
01485
01486 /**
01487   * @brief  Exit the RTC Initialization mode.
01488   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01489   *                the configuration information for RTC.
01490   * @retval HAL status
01491   */
01492 static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef* hrtc)
01493 {
01494   uint32_t tickstart = 0U;
01495
01496   /* Disable the write protection for RTC registers */
01497   __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
01498
01499   tickstart = HAL_GetTick();
01500   /* Wait till RTC is in INIT state and if Time out is reached exit */
01501   while((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
01502   {
01503     if((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
01504     {
01505       return HAL_TIMEOUT;
01506     }
01507   }
01508
01509   return HAL_OK;
01510 }
01511
01512 /**
01513   * @brief  Converts a 2 digit decimal to BCD format.
01514   * @param  Value: Byte to be converted
01515   * @retval Converted byte
01516   */
01517 static uint8_t RTC_ByteToBcd2(uint8_t Value)
01518 {
01519   uint32_t bcdhigh = 0U;
01520
01521   while(Value >= 10U)
01522   {
01523     bcdhigh++;
01524     Value -= 10U;
01525   }
01526
01527   return  ((uint8_t)(bcdhigh << 4U) | Value);
01528 }
01529
01530 /**
01531   * @brief  Converts from 2 digit BCD to Binary.
01532   * @param  Value: BCD value to be converted
01533   * @retval Converted word
01534   */
01535 static uint8_t RTC_Bcd2ToByte(uint8_t Value)
01536 {
01537   uint32_t tmp = 0U;
01538   tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U;
01539   return (tmp + (Value & (uint8_t)0x0F));
01540 }
01541
01542 /**
01543   * @brief  Updates date when time is 23:59:59.
01544   * @param  hrtc   pointer to a RTC_HandleTypeDef structure that contains
01545   *                the configuration information for RTC.
01546   * @param  DayElapsed: Number of days elapsed from last date update
01547   * @retval None
01548   */
01549 static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed)
01550 {
01551   uint32_t year = 0U, month = 0U, day = 0U;
01552   uint32_t loop = 0U;
01553
01554   /* Get the current year*/
01555   year = hrtc->DateToUpdate.Year;
01556
01557   /* Get the current month and day */
01558   month = hrtc->DateToUpdate.Month;
01559   day = hrtc->DateToUpdate.Date;
01560
01561   for (loop = 0U; loop < DayElapsed; loop++)
01562   {
01563     if((month == 1U) || (month == 3U) || (month == 5U) || (month == 7U) || \
01564        (month == 8U) || (month == 10U) || (month == 12U))
01565     {
01566       if(day < 31U)
01567       {
01568         day++;
01569       }
01570       /* Date structure member: day = 31 */
01571       else
01572       {
01573         if(month != 12U)
01574         {
01575           month++;
01576           day = 1U;
01577         }
01578         /* Date structure member: day = 31 & month =12 */
01579         else
01580         {
01581           month = 1U;
01582           day = 1U;
01583           year++;
01584         }
01585       }
01586     }
01587     else if((month == 4U) || (month == 6U) || (month == 9U) || (month == 11U))
01588     {
01589       if(day < 30U)
01590       {
01591         day++;
01592       }
01593       /* Date structure member: day = 30 */
01594       else
01595       {
01596         month++;
01597         day = 1U;
01598       }
01599     }
01600     else if(month == 2U)
01601     {
01602       if(day < 28U)
01603       {
01604         day++;
01605       }
01606       else if(day == 28U)
01607       {
01608         /* Leap year */
01609         if(RTC_IsLeapYear(year))
01610         {
01611           day++;
01612         }
01613         else
01614         {
01615           month++;
01616           day = 1U;
01617         }
01618       }
01619       else if(day == 29U)
01620       {
01621         month++;
01622         day = 1U;
01623       }
01624     }
01625   }
01626
01627   /* Update year */
01628   hrtc->DateToUpdate.Year = year;
01629
01630   /* Update day and month */
01631   hrtc->DateToUpdate.Month = month;
01632   hrtc->DateToUpdate.Date = day;
01633
01634   /* Update day of the week */
01635   hrtc->DateToUpdate.WeekDay = RTC_WeekDayNum(year, month, day);
01636 }
01637
01638 /**
01639   * @brief  Check whether the passed year is Leap or not.
01640   * @param  nYear  year to check
01641   * @retval 1: leap year
01642   *         0: not leap year
01643   */
01644 static uint8_t RTC_IsLeapYear(uint16_t nYear)
01645 {
01646   if((nYear % 4U) != 0U)
01647   {
01648     return 0U;
01649   }
01650
01651   if((nYear % 100U) != 0U)
01652   {
01653     return 1U;
01654   }
01655
01656   if((nYear % 400U) == 0U)
01657   {
01658     return 1U;
01659   }
01660   else
01661   {
01662     return 0U;
01663   }
01664 }
01665
01666 /**
01667   * @brief  Determines the week number, the day number and the week day number.
01668   * @param  nYear   year to check
01669   * @param  nMonth  Month to check
01670   * @param  nDay    Day to check
01671   * @note   Day is calculated with hypothesis that year > 2000
01672   * @retval Value which can take one of the following parameters:
01673   *         @arg RTC_WEEKDAY_MONDAY
01674   *         @arg RTC_WEEKDAY_TUESDAY
01675   *         @arg RTC_WEEKDAY_WEDNESDAY
01676   *         @arg RTC_WEEKDAY_THURSDAY
01677   *         @arg RTC_WEEKDAY_FRIDAY
01678   *         @arg RTC_WEEKDAY_SATURDAY
01679   *         @arg RTC_WEEKDAY_SUNDAY
01680   */
01681 static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay)
01682 {
01683   uint32_t year = 0U, weekday = 0U;
01684
01685   year = 2000U + nYear;
01686
01687   if(nMonth < 3U)
01688   {
01689     /*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/
01690     weekday = (((23U * nMonth)/9U) + nDay + 4U + year + ((year-1U)/4U) - ((year-1U)/100U) + ((year-1U)/400U)) % 7U;
01691   }
01692   else
01693   {
01694     /*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/
01695     weekday = (((23U * nMonth)/9U) + nDay + 4U + year + (year/4U) - (year/100U) + (year/400U) - 2U ) % 7U;
01696   }
01697
01698   return (uint8_t)weekday;
01699 }
01700
01701 /**
01702   * @}
01703   */
01704
01705 #endif /* HAL_RTC_MODULE_ENABLED */
01706 /**
01707   * @}
01708   */
01709
01710 /**
01711   * @}
01712   */
01713
01714 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rtc.h Source File

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stm32f1xx_hal_rtc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_rtc.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of RTC HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_RTC_H
00040 #define __STM32F1xx_HAL_RTC_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RTC
00054   * @{
00055   */
00056
00057 /** @addtogroup RTC_Private_Macros
00058   * @{
00059   */
00060
00061 #define IS_RTC_ASYNCH_PREDIV(PREDIV)  (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND))
00062 #define IS_RTC_HOUR24(HOUR)           ((HOUR) <= 23U)
00063 #define IS_RTC_MINUTES(MINUTES)       ((MINUTES) <= 59U)
00064 #define IS_RTC_SECONDS(SECONDS)       ((SECONDS) <= 59U)
00065 #define IS_RTC_FORMAT(FORMAT)         (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
00066 #define IS_RTC_YEAR(YEAR)             ((YEAR) <= 99U)
00067 #define IS_RTC_MONTH(MONTH)           (((MONTH) >= 1U) && ((MONTH) <= 12U))
00068 #define IS_RTC_DATE(DATE)             (((DATE) >= 1U) && ((DATE) <= 31U))
00069 #define IS_RTC_ALARM(ALARM)           ((ALARM) == RTC_ALARM_A)
00070 #define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \
00071                                          ((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \
00072                                          ((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \
00073                                          ((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND))
00074
00075
00076 /**
00077   * @}
00078   */
00079
00080 /** @addtogroup RTC_Private_Constants
00081   * @{
00082   */
00083 /** @defgroup RTC_Timeout_Value Default Timeout Value
00084   * @{
00085   */
00086 #define RTC_TIMEOUT_VALUE           1000U
00087 /**
00088   * @}
00089   */
00090
00091 /** @defgroup RTC_EXTI_Line_Event RTC EXTI Line event
00092   * @{
00093   */
00094 #define RTC_EXTI_LINE_ALARM_EVENT   ((uint32_t)EXTI_IMR_MR17)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
00095 /**
00096   * @}
00097   */
00098
00099
00100 /**
00101   * @}
00102   */
00103
00104 /* Exported types ------------------------------------------------------------*/
00105 /** @defgroup RTC_Exported_Types RTC Exported Types
00106   * @{
00107   */
00108 /**
00109   * @brief  RTC Time structure definition
00110   */
00111 typedef struct
00112 {
00113   uint8_t Hours;            /*!< Specifies the RTC Time Hour.
00114                                  This parameter must be a number between Min_Data = 0 and Max_Data = 23 */
00115
00116   uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
00117                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00118
00119   uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
00120                                  This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
00121
00122 }RTC_TimeTypeDef;
00123
00124 /**
00125   * @brief  RTC Alarm structure definition
00126   */
00127 typedef struct
00128 {
00129   RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
00130
00131   uint32_t Alarm;                /*!< Specifies the alarm ID (only 1 alarm ID for STM32F1).
00132                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
00133 }RTC_AlarmTypeDef;
00134
00135 /**
00136   * @brief  HAL State structures definition
00137   */
00138 typedef enum
00139 {
00140   HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
00141   HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
00142   HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
00143   HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
00144   HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
00145
00146 }HAL_RTCStateTypeDef;
00147
00148 /**
00149   * @brief  RTC Configuration Structure definition
00150   */
00151 typedef struct
00152 {
00153   uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
00154                                  This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF  or RTC_AUTO_1_SECOND
00155                                  If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase */
00156
00157   uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC Tamper pin.
00158                                  This parameter can be a value of @ref RTC_output_source_to_output_on_the_Tamper_pin */
00159
00160 }RTC_InitTypeDef;
00161
00162 /**
00163   * @brief  RTC Date structure definition
00164   */
00165 typedef struct
00166 {
00167   uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate).
00168                          This parameter can be a value of @ref RTC_WeekDay_Definitions */
00169
00170   uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
00171                          This parameter can be a value of @ref RTC_Month_Date_Definitions */
00172
00173   uint8_t Date;     /*!< Specifies the RTC Date.
00174                          This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
00175
00176   uint8_t Year;     /*!< Specifies the RTC Date Year.
00177                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
00178
00179 }RTC_DateTypeDef;
00180
00181 /**
00182   * @brief  Time Handle Structure definition
00183   */
00184 typedef struct
00185 {
00186   RTC_TypeDef                 *Instance;  /*!< Register base address    */
00187
00188   RTC_InitTypeDef             Init;       /*!< RTC required parameters  */
00189
00190   RTC_DateTypeDef             DateToUpdate;       /*!< Current date set by user and updated automatically  */
00191
00192   HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
00193
00194   __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
00195
00196 }RTC_HandleTypeDef;
00197
00198 /**
00199   * @}
00200   */
00201
00202 /* Exported constants --------------------------------------------------------*/
00203 /** @defgroup RTC_Exported_Constants RTC Exported Constants
00204   * @{
00205   */
00206
00207 /** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase
00208   * @{
00209   */
00210 #define RTC_AUTO_1_SECOND                      0xFFFFFFFFU
00211
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
00217   * @{
00218   */
00219 #define RTC_FORMAT_BIN                         0x000000000U
00220 #define RTC_FORMAT_BCD                         0x000000001U
00221
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup RTC_Month_Date_Definitions Month Definitions
00227   * @{
00228   */
00229
00230 /* Coded in BCD format */
00231 #define RTC_MONTH_JANUARY              ((uint8_t)0x01)
00232 #define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
00233 #define RTC_MONTH_MARCH                ((uint8_t)0x03)
00234 #define RTC_MONTH_APRIL                ((uint8_t)0x04)
00235 #define RTC_MONTH_MAY                  ((uint8_t)0x05)
00236 #define RTC_MONTH_JUNE                 ((uint8_t)0x06)
00237 #define RTC_MONTH_JULY                 ((uint8_t)0x07)
00238 #define RTC_MONTH_AUGUST               ((uint8_t)0x08)
00239 #define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
00240 #define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
00241 #define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
00242 #define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
00243
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup RTC_WeekDay_Definitions WeekDay Definitions
00249   * @{
00250   */
00251 #define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
00252 #define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
00253 #define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
00254 #define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
00255 #define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
00256 #define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
00257 #define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x00)
00258
00259 /**
00260   * @}
00261   */
00262
00263 /** @defgroup RTC_Alarms_Definitions Alarms Definitions
00264   * @{
00265   */
00266 #define RTC_ALARM_A                        0U                                 /*!< Specify alarm ID (mainly for legacy purposes) */
00267
00268 /**
00269   * @}
00270   */
00271
00272
00273 /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin
00274   * @{
00275   */
00276
00277 #define RTC_OUTPUTSOURCE_NONE               0x00000000U                       /*!< No output on the TAMPER pin  */
00278 #define RTC_OUTPUTSOURCE_CALIBCLOCK         BKP_RTCCR_CCO                     /*!< RTC clock with a frequency divided by 64 on the TAMPER pin  */
00279 #define RTC_OUTPUTSOURCE_ALARM              BKP_RTCCR_ASOE                    /*!< Alarm pulse signal on the TAMPER pin  */
00280 #define RTC_OUTPUTSOURCE_SECOND             (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin  */
00281
00282 /**
00283   * @}
00284   */
00285
00286 /** @defgroup RTC_Interrupts_Definitions Interrupts Definitions
00287   * @{
00288   */
00289 #define RTC_IT_OW            RTC_CRH_OWIE       /*!< Overflow interrupt */
00290 #define RTC_IT_ALRA          RTC_CRH_ALRIE      /*!< Alarm interrupt */
00291 #define RTC_IT_SEC           RTC_CRH_SECIE      /*!< Second interrupt */
00292 #define RTC_IT_TAMP1         BKP_CSR_TPIE       /*!< TAMPER Pin interrupt enable */
00293 /**
00294   * @}
00295   */
00296
00297 /** @defgroup RTC_Flags_Definitions Flags Definitions
00298   * @{
00299   */
00300 #define RTC_FLAG_RTOFF       RTC_CRL_RTOFF      /*!< RTC Operation OFF flag */
00301 #define RTC_FLAG_RSF         RTC_CRL_RSF        /*!< Registers Synchronized flag */
00302 #define RTC_FLAG_OW          RTC_CRL_OWF        /*!< Overflow flag */
00303 #define RTC_FLAG_ALRAF       RTC_CRL_ALRF       /*!< Alarm flag */
00304 #define RTC_FLAG_SEC         RTC_CRL_SECF       /*!< Second flag */
00305 #define RTC_FLAG_TAMP1F      BKP_CSR_TEF        /*!< Tamper Interrupt Flag */
00306
00307 /**
00308   * @}
00309   */
00310
00311 /**
00312   * @}
00313   */
00314
00315 /* Exported macro ------------------------------------------------------------*/
00316 /** @defgroup RTC_Exported_macros RTC Exported Macros
00317   * @{
00318   */
00319
00320 /** @brief  Reset RTC handle state
00321   * @param  __HANDLE__: RTC handle.
00322   * @retval None
00323   */
00324 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__)              ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
00325
00326 /**
00327   * @brief  Disable the write protection for RTC registers.
00328   * @param  __HANDLE__: specifies the RTC handle.
00329   * @retval None
00330   */
00331 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)         SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
00332
00333 /**
00334   * @brief  Enable the write protection for RTC registers.
00335   * @param  __HANDLE__: specifies the RTC handle.
00336   * @retval None
00337   */
00338 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)          CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
00339
00340 /**
00341   * @brief  Enable the RTC Alarm interrupt.
00342   * @param  __HANDLE__: specifies the RTC handle.
00343   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
00344   *          This parameter can be any combination of the following values:
00345   *            @arg RTC_IT_ALRA: Alarm A interrupt
00346   * @retval None
00347   */
00348 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
00349
00350 /**
00351   * @brief  Disable the RTC Alarm interrupt.
00352   * @param  __HANDLE__: specifies the RTC handle.
00353   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
00354   *         This parameter can be any combination of the following values:
00355   *            @arg RTC_IT_ALRA: Alarm A interrupt
00356   * @retval None
00357   */
00358 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
00359
00360 /**
00361   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
00362   * @param  __HANDLE__: specifies the RTC handle.
00363   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be checked
00364   *         This parameter can be:
00365   *            @arg RTC_IT_ALRA: Alarm A interrupt
00366   * @retval None
00367   */
00368 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
00369
00370 /**
00371   * @brief  Get the selected RTC Alarm's flag status.
00372   * @param  __HANDLE__: specifies the RTC handle.
00373   * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
00374   *          This parameter can be:
00375   *            @arg RTC_FLAG_ALRAF
00376   * @retval None
00377   */
00378 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
00379
00380 /**
00381   * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
00382   * @param  __HANDLE__: specifies the RTC handle.
00383   * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
00384   *         This parameter can be:
00385   *            @arg RTC_IT_ALRA: Alarm A interrupt
00386   * @retval None
00387   */
00388 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET)
00389
00390 /**
00391   * @brief  Clear the RTC Alarm's pending flags.
00392   * @param  __HANDLE__: specifies the RTC handle.
00393   * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
00394   *         This parameter can be:
00395   *            @arg RTC_FLAG_ALRAF
00396   * @retval None
00397   */
00398 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
00399
00400 /**
00401   * @brief Enable interrupt on ALARM Exti Line 17.
00402   * @retval None.
00403   */
00404 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()                  SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
00405
00406 /**
00407   * @brief Disable interrupt on ALARM Exti Line 17.
00408   * @retval None.
00409   */
00410 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()                 CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
00411
00412 /**
00413   * @brief Enable event on ALARM Exti Line 17.
00414   * @retval None.
00415   */
00416 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()               SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
00417
00418 /**
00419   * @brief Disable event on ALARM Exti Line 17.
00420   * @retval None.
00421   */
00422 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()              CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
00423
00424
00425 /**
00426   * @brief  ALARM EXTI line configuration: set falling edge trigger.
00427   * @retval None.
00428   */
00429 #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()        SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
00430
00431
00432 /**
00433   * @brief Disable the ALARM Extended Interrupt Falling Trigger.
00434   * @retval None.
00435   */
00436 #define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()       CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
00437
00438
00439 /**
00440   * @brief  ALARM EXTI line configuration: set rising edge trigger.
00441   * @retval None.
00442   */
00443 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()         SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
00444
00445 /**
00446   * @brief Disable the ALARM Extended Interrupt Rising Trigger.
00447   * This parameter can be:
00448   * @retval None.
00449   */
00450 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()        CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
00451
00452 /**
00453   * @brief  ALARM EXTI line configuration: set rising & falling edge trigger.
00454   * @retval None.
00455   */
00456 #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()      \
00457 do{                                                            \
00458     __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();                 \
00459     __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();                \
00460   } while(0U)
00461
00462 /**
00463   * @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger.
00464   * This parameter can be:
00465   * @retval None.
00466   */
00467 #define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE()      \
00468 do{                                                             \
00469     __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();                 \
00470     __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();                \
00471   } while(0U)
00472
00473 /**
00474   * @brief Check whether the specified ALARM EXTI interrupt flag is set or not.
00475   * @retval EXTI ALARM Line Status.
00476   */
00477 #define __HAL_RTC_ALARM_EXTI_GET_FLAG()                   (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT))
00478
00479 /**
00480   * @brief Clear the ALARM EXTI flag.
00481   * @retval None.
00482   */
00483 #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()                 (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT))
00484
00485 /**
00486   * @brief Generate a Software interrupt on selected EXTI line.
00487   * @retval None.
00488   */
00489 #define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()              SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT)
00490 /**
00491   * @}
00492   */
00493
00494 /* Include RTC HAL Extension module */
00495 #include "stm32f1xx_hal_rtc_ex.h"
00496
00497 /* Exported functions --------------------------------------------------------*/
00498 /** @addtogroup RTC_Exported_Functions
00499   * @{
00500   */
00501
00502
00503 /* Initialization and de-initialization functions  ****************************/
00504 /** @addtogroup RTC_Exported_Functions_Group1
00505   * @{
00506   */
00507 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
00508 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
00509 void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
00510 void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
00511 /**
00512   * @}
00513   */
00514
00515 /* RTC Time and Date functions ************************************************/
00516 /** @addtogroup RTC_Exported_Functions_Group2
00517   * @{
00518   */
00519 HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00520 HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
00521 HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00522 HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
00523 /**
00524   * @}
00525   */
00526
00527 /* RTC Alarm functions ********************************************************/
00528 /** @addtogroup RTC_Exported_Functions_Group3
00529   * @{
00530   */
00531 HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00532 HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
00533 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
00534 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
00535 void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
00536 HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00537 void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
00538 /**
00539   * @}
00540   */
00541
00542 /* Peripheral State functions *************************************************/
00543 /** @addtogroup RTC_Exported_Functions_Group4
00544   * @{
00545   */
00546 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
00547 /**
00548   * @}
00549   */
00550
00551 /* Peripheral Control functions ***********************************************/
00552 /** @addtogroup RTC_Exported_Functions_Group5
00553   * @{
00554   */
00555 HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
00556 /**
00557   * @}
00558   */
00559
00560 /**
00561   * @}
00562   */
00563
00564 /**
00565   * @}
00566   */
00567
00568 /**
00569   * @}
00570   */
00571
00572 #ifdef __cplusplus
00573 }
00574 #endif
00575
00576 #endif /* __STM32F1xx_HAL_RTC_H */
00577
00578 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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STM32F103xB HAL User Manual: stm32f1xx_hal_rtc_ex.c Source File

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stm32f1xx_hal_rtc_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_rtc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Extended RTC HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Real Time Clock (RTC) Extension peripheral:
00010   *           + RTC Tamper functions
00011   *           + Extension Control functions
00012   *           + Extension RTC features functions
00013   *
00014   ******************************************************************************
00015   * @attention
00016   *
00017   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00018   *
00019   * Redistribution and use in source and binary forms, with or without modification,
00020   * are permitted provided that the following conditions are met:
00021   *   1. Redistributions of source code must retain the above copyright notice,
00022   *      this list of conditions and the following disclaimer.
00023   *   2. Redistributions in binary form must reproduce the above copyright notice,
00024   *      this list of conditions and the following disclaimer in the documentation
00025   *      and/or other materials provided with the distribution.
00026   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00027   *      may be used to endorse or promote products derived from this software
00028   *      without specific prior written permission.
00029   *
00030   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00031   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00032   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00033   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00034   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00035   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00036   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00037   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00038   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00039   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00040   *
00041   ******************************************************************************
00042   */
00043
00044 /* Includes ------------------------------------------------------------------*/
00045 #include "stm32f1xx_hal.h"
00046
00047 /** @addtogroup STM32F1xx_HAL_Driver
00048   * @{
00049   */
00050
00051 #ifdef HAL_RTC_MODULE_ENABLED
00052
00053 /** @defgroup RTCEx RTCEx
00054   * @brief RTC Extended HAL module driver
00055   * @{
00056   */
00057
00058 /* Private typedef -----------------------------------------------------------*/
00059 /* Private define ------------------------------------------------------------*/
00060 /* Private macro -------------------------------------------------------------*/
00061 /** @defgroup RTCEx_Private_Macros RTCEx Private Macros
00062   * @{
00063   */
00064 /**
00065   * @}
00066   */
00067
00068 /* Private variables ---------------------------------------------------------*/
00069 /* Private function prototypes -----------------------------------------------*/
00070 /* Private functions ---------------------------------------------------------*/
00071
00072 /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
00073   * @{
00074   */
00075
00076 /** @defgroup RTCEx_Exported_Functions_Group1 RTC Tamper functions
00077   * @brief    RTC Tamper functions
00078   *
00079 @verbatim
00080  ===============================================================================
00081                  ##### RTC Tamper functions #####
00082  ===============================================================================
00083
00084  [..] This section provides functions allowing to configure Tamper feature
00085
00086 @endverbatim
00087   * @{
00088   */
00089
00090 /**
00091   * @brief  Sets Tamper
00092   * @note   By calling this API we disable the tamper interrupt for all tampers.
00093   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00094   *                the configuration information for RTC.
00095   * @param  sTamper: Pointer to Tamper Structure.
00096   * @note   Tamper can be enabled only if ASOE and CCO bit are reset
00097   * @retval HAL status
00098   */
00099 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00100 {
00101   /* Check input parameters */
00102   if((hrtc == NULL) || (sTamper == NULL))
00103   {
00104      return HAL_ERROR;
00105   }
00106
00107   /* Check the parameters */
00108   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00109   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00110
00111   /* Process Locked */
00112   __HAL_LOCK(hrtc);
00113
00114   hrtc->State = HAL_RTC_STATE_BUSY;
00115
00116   if (HAL_IS_BIT_SET(BKP->RTCCR,(BKP_RTCCR_CCO | BKP_RTCCR_ASOE)))
00117   {
00118     hrtc->State = HAL_RTC_STATE_ERROR;
00119
00120     /* Process Unlocked */
00121     __HAL_UNLOCK(hrtc);
00122
00123     return HAL_ERROR;
00124   }
00125
00126   MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger)));
00127
00128   hrtc->State = HAL_RTC_STATE_READY;
00129
00130   /* Process Unlocked */
00131   __HAL_UNLOCK(hrtc);
00132
00133   return HAL_OK;
00134 }
00135
00136 /**
00137   * @brief  Sets Tamper with interrupt.
00138   * @note   By calling this API we force the tamper interrupt for all tampers.
00139   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00140   *                the configuration information for RTC.
00141   * @param  sTamper: Pointer to RTC Tamper.
00142   * @note   Tamper can be enabled only if ASOE and CCO bit are reset
00143   * @retval HAL status
00144   */
00145 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
00146 {
00147   /* Check input parameters */
00148   if((hrtc == NULL) || (sTamper == NULL))
00149   {
00150      return HAL_ERROR;
00151   }
00152
00153   /* Check the parameters */
00154   assert_param(IS_RTC_TAMPER(sTamper->Tamper));
00155   assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
00156
00157   /* Process Locked */
00158   __HAL_LOCK(hrtc);
00159
00160   hrtc->State = HAL_RTC_STATE_BUSY;
00161
00162   if (HAL_IS_BIT_SET(BKP->RTCCR,(BKP_RTCCR_CCO | BKP_RTCCR_ASOE)))
00163   {
00164     hrtc->State = HAL_RTC_STATE_ERROR;
00165
00166     /* Process Unlocked */
00167     __HAL_UNLOCK(hrtc);
00168
00169     return HAL_ERROR;
00170   }
00171
00172   MODIFY_REG(BKP->CR, (BKP_CR_TPE | BKP_CR_TPAL), (sTamper->Tamper | (sTamper->Trigger)));
00173
00174   /* Configure the Tamper Interrupt in the BKP->CSR */
00175   __HAL_RTC_TAMPER_ENABLE_IT(hrtc, RTC_IT_TAMP1);
00176
00177   hrtc->State = HAL_RTC_STATE_READY;
00178
00179   /* Process Unlocked */
00180   __HAL_UNLOCK(hrtc);
00181
00182   return HAL_OK;
00183 }
00184
00185 /**
00186   * @brief  Deactivates Tamper.
00187   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00188   *                the configuration information for RTC.
00189   * @param  Tamper: Selected tamper pin.
00190   *          This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions
00191   * @retval HAL status
00192   */
00193 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
00194 {
00195   /* Check input parameters */
00196   if(hrtc == NULL)
00197   {
00198      return HAL_ERROR;
00199   }
00200
00201   assert_param(IS_RTC_TAMPER(Tamper));
00202
00203   /* Process Locked */
00204   __HAL_LOCK(hrtc);
00205
00206   hrtc->State = HAL_RTC_STATE_BUSY;
00207
00208   /* Disable the selected Tamper pin */
00209   CLEAR_BIT(BKP->CR, BKP_CR_TPE);
00210
00211   /* Disable the Tamper Interrupt in the BKP->CSR */
00212   /* Configure the Tamper Interrupt in the BKP->CSR */
00213   __HAL_RTC_TAMPER_DISABLE_IT(hrtc, RTC_IT_TAMP1);
00214
00215   /* Clear the Tamper interrupt pending bit */
00216   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
00217   SET_BIT(BKP->CSR, BKP_CSR_CTE);
00218
00219   hrtc->State = HAL_RTC_STATE_READY;
00220
00221   /* Process Unlocked */
00222   __HAL_UNLOCK(hrtc);
00223
00224   return HAL_OK;
00225 }
00226
00227 /**
00228   * @brief  This function handles Tamper interrupt request.
00229   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00230   *                the configuration information for RTC.
00231   * @retval None
00232   */
00233 void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc)
00234 {
00235   /* Get the status of the Interrupt */
00236   if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP1))
00237   {
00238     /* Get the TAMPER Interrupt enable bit and pending bit */
00239     if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET)
00240     {
00241       /* Tamper callback */
00242       HAL_RTCEx_Tamper1EventCallback(hrtc);
00243
00244       /* Clear the Tamper interrupt pending bit */
00245       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
00246     }
00247   }
00248
00249   /* Change RTC state */
00250   hrtc->State = HAL_RTC_STATE_READY;
00251 }
00252
00253 /**
00254   * @brief  Tamper 1 callback.
00255   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00256   *                the configuration information for RTC.
00257   * @retval None
00258   */
00259 __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
00260 {
00261   /* Prevent unused argument(s) compilation warning */
00262   UNUSED(hrtc);
00263   /* NOTE : This function Should not be modified, when the callback is needed,
00264             the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
00265    */
00266 }
00267
00268 /**
00269   * @brief  This function handles Tamper1 Polling.
00270   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00271   *                the configuration information for RTC.
00272   * @param  Timeout: Timeout duration
00273   * @retval HAL status
00274   */
00275 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
00276 {
00277   uint32_t tickstart = HAL_GetTick();
00278
00279   /* Check input parameters */
00280   if(hrtc == NULL)
00281   {
00282      return HAL_ERROR;
00283   }
00284
00285   /* Get the status of the Interrupt */
00286   while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
00287   {
00288     if(Timeout != HAL_MAX_DELAY)
00289     {
00290       if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
00291       {
00292         hrtc->State = HAL_RTC_STATE_TIMEOUT;
00293         return HAL_TIMEOUT;
00294       }
00295     }
00296   }
00297
00298   /* Clear the Tamper Flag */
00299   __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
00300
00301   /* Change RTC state */
00302   hrtc->State = HAL_RTC_STATE_READY;
00303
00304   return HAL_OK;
00305 }
00306
00307 /**
00308   * @}
00309   */
00310
00311 /** @defgroup RTCEx_Exported_Functions_Group2 RTC Second functions
00312   * @brief    RTC Second functions
00313   *
00314 @verbatim
00315  ===============================================================================
00316                  ##### RTC Second functions #####
00317  ===============================================================================
00318
00319  [..] This section provides functions implementing second interupt handlers
00320
00321 @endverbatim
00322   * @{
00323   */
00324
00325 /**
00326   * @brief  Sets Interrupt for second
00327   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00328   *                the configuration information for RTC.
00329   * @retval HAL status
00330   */
00331 HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc)
00332 {
00333   /* Check input parameters */
00334   if(hrtc == NULL)
00335   {
00336      return HAL_ERROR;
00337   }
00338
00339   /* Process Locked */
00340   __HAL_LOCK(hrtc);
00341
00342   hrtc->State = HAL_RTC_STATE_BUSY;
00343
00344   /* Enable Second interuption */
00345   __HAL_RTC_SECOND_ENABLE_IT(hrtc, RTC_IT_SEC);
00346
00347   hrtc->State = HAL_RTC_STATE_READY;
00348
00349   /* Process Unlocked */
00350   __HAL_UNLOCK(hrtc);
00351
00352   return HAL_OK;
00353 }
00354
00355 /**
00356   * @brief  Deactivates Second.
00357   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00358   *                the configuration information for RTC.
00359   * @retval HAL status
00360   */
00361 HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc)
00362 {
00363   /* Check input parameters */
00364   if(hrtc == NULL)
00365   {
00366      return HAL_ERROR;
00367   }
00368
00369   /* Process Locked */
00370   __HAL_LOCK(hrtc);
00371
00372   hrtc->State = HAL_RTC_STATE_BUSY;
00373
00374   /* Deactivate Second interuption*/
00375   __HAL_RTC_SECOND_DISABLE_IT(hrtc, RTC_IT_SEC);
00376
00377   hrtc->State = HAL_RTC_STATE_READY;
00378
00379   /* Process Unlocked */
00380   __HAL_UNLOCK(hrtc);
00381
00382   return HAL_OK;
00383 }
00384
00385 /**
00386   * @brief  This function handles second interrupt request.
00387   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00388   *                the configuration information for RTC.
00389   * @retval None
00390   */
00391 void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef* hrtc)
00392 {
00393   if(__HAL_RTC_SECOND_GET_IT_SOURCE(hrtc, RTC_IT_SEC))
00394   {
00395     /* Get the status of the Interrupt */
00396     if(__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_SEC))
00397     {
00398       /* Check if Overrun occurred */
00399       if (__HAL_RTC_SECOND_GET_FLAG(hrtc, RTC_FLAG_OW))
00400       {
00401         /* Second error callback */
00402         HAL_RTCEx_RTCEventErrorCallback(hrtc);
00403
00404         /* Clear flag Second */
00405         __HAL_RTC_OVERFLOW_CLEAR_FLAG(hrtc, RTC_FLAG_OW);
00406
00407         /* Change RTC state */
00408         hrtc->State = HAL_RTC_STATE_ERROR;
00409       }
00410       else
00411       {
00412         /* Second callback */
00413         HAL_RTCEx_RTCEventCallback(hrtc);
00414
00415         /* Change RTC state */
00416         hrtc->State = HAL_RTC_STATE_READY;
00417       }
00418
00419       /* Clear flag Second */
00420       __HAL_RTC_SECOND_CLEAR_FLAG(hrtc, RTC_FLAG_SEC);
00421     }
00422   }
00423 }
00424
00425 /**
00426   * @brief  Second event callback.
00427   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00428   *                the configuration information for RTC.
00429   * @retval None
00430   */
00431 __weak void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc)
00432 {
00433   /* Prevent unused argument(s) compilation warning */
00434   UNUSED(hrtc);
00435   /* NOTE : This function Should not be modified, when the callback is needed,
00436             the HAL_RTCEx_RTCEventCallback could be implemented in the user file
00437    */
00438 }
00439
00440 /**
00441   * @brief  Second event error callback.
00442   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00443   *                the configuration information for RTC.
00444   * @retval None
00445   */
00446 __weak void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc)
00447 {
00448   /* Prevent unused argument(s) compilation warning */
00449   UNUSED(hrtc);
00450   /* NOTE : This function Should not be modified, when the callback is needed,
00451             the HAL_RTCEx_RTCEventErrorCallback could be implemented in the user file
00452    */
00453 }
00454
00455 /**
00456   * @}
00457   */
00458
00459 /** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
00460   * @brief    Extended Peripheral Control functions
00461   *
00462 @verbatim
00463  ===============================================================================
00464               ##### Extension Peripheral Control functions #####
00465  ===============================================================================
00466     [..]
00467     This subsection provides functions allowing to
00468       (+) Writes a data in a specified RTC Backup data register
00469       (+) Read a data in a specified RTC Backup data register
00470       (+) Sets the Smooth calibration parameters.
00471
00472 @endverbatim
00473   * @{
00474   */
00475
00476 /**
00477   * @brief  Writes a data in a specified RTC Backup data register.
00478   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00479   *                the configuration information for RTC.
00480   * @param  BackupRegister: RTC Backup data Register number.
00481   *          This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
00482   *                                 specify the register (depending devices).
00483   * @param  Data: Data to be written in the specified RTC Backup data register.
00484   * @retval None
00485   */
00486 void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
00487 {
00488   uint32_t tmp = 0U;
00489
00490   /* Check the parameters */
00491   assert_param(IS_RTC_BKP(BackupRegister));
00492
00493   tmp = (uint32_t)BKP_BASE;
00494   tmp += (BackupRegister * 4U);
00495
00496   *(__IO uint32_t *) tmp = (Data & BKP_DR1_D);
00497 }
00498
00499 /**
00500   * @brief  Reads data from the specified RTC Backup data Register.
00501   * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
00502   *                the configuration information for RTC.
00503   * @param  BackupRegister: RTC Backup data Register number.
00504   *          This parameter can be: RTC_BKP_DRx where x can be from 1 to 10 (or 42) to
00505   *                                 specify the register (depending devices).
00506   * @retval Read value
00507   */
00508 uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
00509 {
00510   uint32_t backupregister = 0U;
00511   uint32_t pvalue = 0U;
00512
00513   /* Check the parameters */
00514   assert_param(IS_RTC_BKP(BackupRegister));
00515
00516   backupregister = (uint32_t)BKP_BASE;
00517   backupregister += (BackupRegister * 4U);
00518
00519   pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D;
00520
00521   /* Read the specified register */
00522   return pvalue;
00523 }
00524
00525
00526 /**
00527   * @brief  Sets the Smooth calibration parameters.
00528   * @param  hrtc: RTC handle
00529   * @param  SmoothCalibPeriod: Not used (only present for compatibility with another families)
00530   * @param  SmoothCalibPlusPulses: Not used (only present for compatibility with another families)
00531   * @param  SmouthCalibMinusPulsesValue: specifies the RTC Clock Calibration value.
00532   *          This parameter must be a number between 0 and 0x7F.
00533   * @retval HAL status
00534   */
00535 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
00536 {
00537   /* Check input parameters */
00538   if(hrtc == NULL)
00539   {
00540      return HAL_ERROR;
00541   }
00542
00543   /* Check the parameters */
00544   assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
00545
00546   /* Process Locked */
00547   __HAL_LOCK(hrtc);
00548
00549   hrtc->State = HAL_RTC_STATE_BUSY;
00550
00551   /* Sets RTC Clock Calibration value.*/
00552   MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, SmouthCalibMinusPulsesValue);
00553
00554   /* Change RTC state */
00555   hrtc->State = HAL_RTC_STATE_READY;
00556
00557   /* Process Unlocked */
00558   __HAL_UNLOCK(hrtc);
00559
00560   return HAL_OK;
00561 }
00562
00563 /**
00564   * @}
00565   */
00566
00567 /**
00568   * @}
00569   */
00570
00571 /**
00572   * @}
00573   */
00574
00575 #endif /* HAL_RTC_MODULE_ENABLED */
00576
00577 /**
00578   * @}
00579   */
00580
00581 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00582
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_rtc_ex.h Source File

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stm32f1xx_hal_rtc_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_rtc_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of RTC HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_RTC_EX_H
00040 #define __STM32F1xx_HAL_RTC_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup RTCEx
00054   * @{
00055   */
00056
00057 /** @addtogroup RTCEx_Private_Macros
00058   * @{
00059   */
00060
00061 /** @defgroup RTCEx_Alias_For_Legacy Alias define maintained for legacy
00062   * @{
00063   */
00064 #define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler
00065
00066 /**
00067   * @}
00068   */
00069
00070 /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
00071   * @{
00072   */
00073 #define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1)
00074
00075 #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__)  (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
00076                                              ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
00077
00078 #if RTC_BKP_NUMBER > 10U
00079 #define IS_RTC_BKP(BKP)                   (((BKP) <= (uint32_t)RTC_BKP_DR10) || (((BKP) >= (uint32_t)RTC_BKP_DR11) && ((BKP) <= (uint32_t)RTC_BKP_DR42)))
00080 #else
00081 #define IS_RTC_BKP(BKP)                   ((BKP) <= (uint32_t)RTC_BKP_NUMBER)
00082 #endif
00083 #define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU)
00084
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /* Exported types ------------------------------------------------------------*/
00094 /** @defgroup RTCEx_Exported_Types RTCEx Exported Types
00095   * @{
00096   */
00097 /**
00098   * @brief  RTC Tamper structure definition
00099   */
00100 typedef struct
00101 {
00102   uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
00103                                              This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
00104
00105   uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
00106                                              This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
00107
00108 }RTC_TamperTypeDef;
00109
00110 /**
00111   * @}
00112   */
00113
00114 /* Exported constants --------------------------------------------------------*/
00115 /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
00116   * @{
00117   */
00118
00119 /** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions
00120   * @{
00121   */
00122 #define RTC_TAMPER_1                        BKP_CR_TPE            /*!< Select tamper to be enabled (mainly for legacy purposes) */
00123
00124 /**
00125   * @}
00126   */
00127
00128 /** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions
00129   * @{
00130   */
00131 #define RTC_TAMPERTRIGGER_LOWLEVEL          BKP_CR_TPAL           /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
00132 #define RTC_TAMPERTRIGGER_HIGHLEVEL         0x00000000U           /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
00133
00134 /**
00135   * @}
00136   */
00137
00138 /** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions
00139   * @{
00140   */
00141 #if RTC_BKP_NUMBER > 0U
00142 #define RTC_BKP_DR1                         0x00000001U
00143 #define RTC_BKP_DR2                         0x00000002U
00144 #define RTC_BKP_DR3                         0x00000003U
00145 #define RTC_BKP_DR4                         0x00000004U
00146 #define RTC_BKP_DR5                         0x00000005U
00147 #define RTC_BKP_DR6                         0x00000006U
00148 #define RTC_BKP_DR7                         0x00000007U
00149 #define RTC_BKP_DR8                         0x00000008U
00150 #define RTC_BKP_DR9                         0x00000009U
00151 #define RTC_BKP_DR10                        0x0000000AU
00152 #endif /* RTC_BKP_NUMBER > 0 */
00153
00154 #if RTC_BKP_NUMBER > 10U
00155 #define RTC_BKP_DR11                        0x00000010U
00156 #define RTC_BKP_DR12                        0x00000011U
00157 #define RTC_BKP_DR13                        0x00000012U
00158 #define RTC_BKP_DR14                        0x00000013U
00159 #define RTC_BKP_DR15                        0x00000014U
00160 #define RTC_BKP_DR16                        0x00000015U
00161 #define RTC_BKP_DR17                        0x00000016U
00162 #define RTC_BKP_DR18                        0x00000017U
00163 #define RTC_BKP_DR19                        0x00000018U
00164 #define RTC_BKP_DR20                        0x00000019U
00165 #define RTC_BKP_DR21                        0x0000001AU
00166 #define RTC_BKP_DR22                        0x0000001BU
00167 #define RTC_BKP_DR23                        0x0000001CU
00168 #define RTC_BKP_DR24                        0x0000001DU
00169 #define RTC_BKP_DR25                        0x0000001EU
00170 #define RTC_BKP_DR26                        0x0000001FU
00171 #define RTC_BKP_DR27                        0x00000020U
00172 #define RTC_BKP_DR28                        0x00000021U
00173 #define RTC_BKP_DR29                        0x00000022U
00174 #define RTC_BKP_DR30                        0x00000023U
00175 #define RTC_BKP_DR31                        0x00000024U
00176 #define RTC_BKP_DR32                        0x00000025U
00177 #define RTC_BKP_DR33                        0x00000026U
00178 #define RTC_BKP_DR34                        0x00000027U
00179 #define RTC_BKP_DR35                        0x00000028U
00180 #define RTC_BKP_DR36                        0x00000029U
00181 #define RTC_BKP_DR37                        0x0000002AU
00182 #define RTC_BKP_DR38                        0x0000002BU
00183 #define RTC_BKP_DR39                        0x0000002CU
00184 #define RTC_BKP_DR40                        0x0000002DU
00185 #define RTC_BKP_DR41                        0x0000002EU
00186 #define RTC_BKP_DR42                        0x0000002FU
00187 #endif /* RTC_BKP_NUMBER > 10 */
00188
00189 /**
00190   * @}
00191   */
00192
00193 /**
00194   * @}
00195   */
00196
00197 /* Exported macro ------------------------------------------------------------*/
00198 /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
00199   * @{
00200   */
00201
00202 /**
00203   * @brief  Enable the RTC Tamper interrupt.
00204   * @param  __HANDLE__: specifies the RTC handle.
00205   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled
00206   *          This parameter can be any combination of the following values:
00207   *            @arg RTC_IT_TAMP1: Tamper A interrupt
00208   * @retval None
00209   */
00210 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__))
00211
00212 /**
00213   * @brief  Disable the RTC Tamper interrupt.
00214   * @param  __HANDLE__: specifies the RTC handle.
00215   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
00216   *         This parameter can be any combination of the following values:
00217   *            @arg RTC_IT_TAMP1: Tamper A interrupt
00218   * @retval None
00219   */
00220 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT(BKP->CSR, (__INTERRUPT__))
00221
00222 /**
00223   * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
00224   * @param  __HANDLE__: specifies the RTC handle.
00225   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
00226   *         This parameter can be:
00227   *            @arg  RTC_IT_TAMP1
00228   * @retval None
00229   */
00230 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET)
00231
00232 /**
00233   * @brief  Get the selected RTC Tamper's flag status.
00234   * @param  __HANDLE__: specifies the RTC handle.
00235   * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
00236   *         This parameter can be:
00237   *            @arg RTC_FLAG_TAMP1F
00238   * @retval None
00239   */
00240 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)       ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET)
00241
00242 /**
00243   * @brief  Get the selected RTC Tamper's flag status.
00244   * @param  __HANDLE__: specifies the RTC handle.
00245   * @param  __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
00246   *         This parameter can be:
00247   *            @arg  RTC_IT_TAMP1
00248   * @retval None
00249   */
00250 #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)       ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET)
00251
00252 /**
00253   * @brief  Clear the RTC Tamper's pending flags.
00254   * @param  __HANDLE__: specifies the RTC handle.
00255   * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
00256   *         This parameter can be:
00257   *            @arg RTC_FLAG_TAMP1F
00258   * @retval None
00259   */
00260 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)     SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI)
00261
00262 /**
00263   * @brief  Enable the RTC Second interrupt.
00264   * @param  __HANDLE__: specifies the RTC handle.
00265   * @param  __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled
00266   *          This parameter can be any combination of the following values:
00267   *            @arg RTC_IT_SEC: Second A interrupt
00268   * @retval None
00269   */
00270 #define __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
00271
00272 /**
00273   * @brief  Disable the RTC Second interrupt.
00274   * @param  __HANDLE__: specifies the RTC handle.
00275   * @param  __INTERRUPT__: specifies the RTC Second interrupt sources to be disabled.
00276   *         This parameter can be any combination of the following values:
00277   *            @arg RTC_IT_SEC: Second A interrupt
00278   * @retval None
00279   */
00280 #define __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
00281
00282 /**
00283   * @brief  Check whether the specified RTC Second interrupt has occurred or not.
00284   * @param  __HANDLE__: specifies the RTC handle.
00285   * @param  __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled or disabled.
00286   *         This parameter can be:
00287   *            @arg RTC_IT_SEC: Second A interrupt
00288   * @retval None
00289   */
00290 #define __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
00291
00292 /**
00293   * @brief  Get the selected RTC Second's flag status.
00294   * @param  __HANDLE__: specifies the RTC handle.
00295   * @param  __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
00296   *          This parameter can be:
00297   *            @arg RTC_FLAG_SEC
00298   * @retval None
00299   */
00300 #define __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
00301
00302 /**
00303   * @brief  Clear the RTC Second's pending flags.
00304   * @param  __HANDLE__: specifies the RTC handle.
00305   * @param  __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
00306   *         This parameter can be:
00307   *            @arg RTC_FLAG_SEC
00308   * @retval None
00309   */
00310 #define __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
00311
00312 /**
00313   * @brief  Enable the RTC Overflow interrupt.
00314   * @param  __HANDLE__: specifies the RTC handle.
00315   * @param  __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled
00316   *          This parameter can be any combination of the following values:
00317   *            @arg RTC_IT_OW: Overflow A interrupt
00318   * @retval None
00319   */
00320 #define __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
00321
00322 /**
00323   * @brief  Disable the RTC Overflow interrupt.
00324   * @param  __HANDLE__: specifies the RTC handle.
00325   * @param  __INTERRUPT__: specifies the RTC Overflow interrupt sources to be disabled.
00326   *         This parameter can be any combination of the following values:
00327   *            @arg RTC_IT_OW: Overflow A interrupt
00328   * @retval None
00329   */
00330 #define __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
00331
00332 /**
00333   * @brief  Check whether the specified RTC Overflow interrupt has occurred or not.
00334   * @param  __HANDLE__: specifies the RTC handle.
00335   * @param  __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled or disabled.
00336   *         This parameter can be:
00337   *            @arg RTC_IT_OW: Overflow A interrupt
00338   * @retval None
00339   */
00340 #define __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET)
00341
00342 /**
00343   * @brief  Get the selected RTC Overflow's flag status.
00344   * @param  __HANDLE__: specifies the RTC handle.
00345   * @param  __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
00346   *          This parameter can be:
00347   *            @arg RTC_FLAG_OW
00348   * @retval None
00349   */
00350 #define __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__)        (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
00351
00352 /**
00353   * @brief  Clear the RTC Overflow's pending flags.
00354   * @param  __HANDLE__: specifies the RTC handle.
00355   * @param  __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
00356   *         This parameter can be:
00357   *            @arg RTC_FLAG_OW
00358   * @retval None
00359   */
00360 #define __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
00361
00362 /**
00363   * @}
00364   */
00365
00366 /* Exported functions --------------------------------------------------------*/
00367 /** @addtogroup RTCEx_Exported_Functions
00368   * @{
00369   */
00370
00371 /* RTC Tamper functions *****************************************/
00372 /** @addtogroup RTCEx_Exported_Functions_Group1
00373   * @{
00374   */
00375 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00376 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
00377 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
00378 void              HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
00379 void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
00380 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
00381
00382 /**
00383   * @}
00384   */
00385
00386 /* RTC Second functions *****************************************/
00387 /** @addtogroup RTCEx_Exported_Functions_Group2
00388   * @{
00389   */
00390 HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc);
00391 HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc);
00392 void              HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef* hrtc);
00393 void              HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc);
00394 void              HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc);
00395
00396 /**
00397   * @}
00398   */
00399
00400 /* Extension Control functions ************************************************/
00401 /** @addtogroup RTCEx_Exported_Functions_Group3
00402   * @{
00403   */
00404 void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
00405 uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
00406
00407 HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
00408 /**
00409   * @}
00410   */
00411
00412 /**
00413   * @}
00414   */
00415
00416 /**
00417   * @}
00418   */
00419
00420 /**
00421   * @}
00422   */
00423
00424 #ifdef __cplusplus
00425 }
00426 #endif
00427
00428 #endif /* __STM32F1xx_HAL_RTC_EX_H */
00429
00430 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_sd.c Source File

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stm32f1xx_hal_sd.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_sd.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   SD card HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Secure Digital (SD) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + SD card Control functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019   [..]
00020     This driver implements a high level communication layer for read and write from/to
00021     this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by
00022     the user in HAL_SD_MspInit() function (MSP layer).
00023     Basically, the MSP layer configuration should be the same as we provide in the
00024     examples.
00025     You can easily tailor this configuration according to hardware resources.
00026
00027   [..]
00028     This driver is a generic layered driver for SDIO memories which uses the HAL
00029     SDIO driver functions to interface with SD and uSD cards devices.
00030     It is used as follows:
00031
00032     (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
00033         (##) Enable the SDIO interface clock using __HAL_RCC_SDIO_CLK_ENABLE();
00034         (##) SDIO pins configuration for SD card
00035             (+++) Enable the clock for the SDIO GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
00036             (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
00037                   and according to your pin assignment;
00038         (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
00039              and HAL_SD_WriteBlocks_DMA() APIs).
00040             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
00041             (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
00042         (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
00043             (+++) Configure the SDIO and DMA interrupt priorities using functions
00044                   HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
00045             (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
00046             (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
00047                   and __HAL_SD_DISABLE_IT() inside the communication process.
00048             (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
00049                   and __HAL_SD_CLEAR_IT()
00050         (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
00051              and HAL_SD_WriteBlocks_IT() APIs).
00052             (+++) Configure the SDIO interrupt priorities using function
00053                   HAL_NVIC_SetPriority();
00054             (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()
00055             (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
00056                   and __HAL_SD_DISABLE_IT() inside the communication process.
00057             (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
00058                   and __HAL_SD_CLEAR_IT()
00059     (#) At this stage, you can perform SD read/write/erase operations after SD card initialization
00060
00061
00062   *** SD Card Initialization and configuration ***
00063   ================================================
00064   [..]
00065     To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
00066     SDIO IP(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
00067     This function provide the following operations:
00068
00069     (#) Initialize the SDIO peripheral interface with defaullt configuration.
00070         The initialization process is done at 400KHz. You can change or adapt
00071         this frequency by adjusting the "ClockDiv" field.
00072         The SD Card frequency (SDIO_CK) is computed as follows:
00073
00074            SDIO_CK = SDIOCLK / (ClockDiv + 2)
00075
00076         In initialization mode and according to the SD Card standard,
00077         make sure that the SDIO_CK frequency doesn't exceed 400KHz.
00078
00079         This phase of initialization is done through SDIO_Init() and
00080         SDIO_PowerState_ON() SDIO low level APIs.
00081
00082     (#) Initialize the SD card. The API used is HAL_SD_InitCard().
00083         This phase allows the card initialization and identification
00084         and check the SD Card type (Standard Capacity or High Capacity)
00085         The initialization flow is compatible with SD standard.
00086
00087         This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
00088         of plug-off plug-in.
00089
00090     (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
00091         frequency is set to 24MHz. You can change or adapt this frequency by adjusting
00092         the "ClockDiv" field.
00093         In transfer mode and according to the SD Card standard, make sure that the
00094         SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
00095         To be able to use a frequency higher than 24MHz, you should use the SDIO
00096         peripheral in bypass mode. Refer to the corresponding reference manual
00097         for more details.
00098
00099     (#) Select the corresponding SD Card according to the address read with the step 2.
00100
00101     (#) Configure the SD Card in wide bus mode: 4-bits data.
00102
00103   *** SD Card Read operation ***
00104   ==============================
00105   [..]
00106     (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
00107         This function allows the read of 512 bytes blocks.
00108         You can choose either one block read operation or multiple block read operation
00109         by adjusting the "NumberOfBlocks" parameter.
00110         After this, you have to ensure that the transfer is done correctly. The check is done
00111         through HAL_SD_GetCardState() function for SD card state.
00112
00113     (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
00114         This function allows the read of 512 bytes blocks.
00115         You can choose either one block read operation or multiple block read operation
00116         by adjusting the "NumberOfBlocks" parameter.
00117         After this, you have to ensure that the transfer is done correctly. The check is done
00118         through HAL_SD_GetCardState() function for SD card state.
00119         You could also check the DMA transfer process through the SD Rx interrupt event.
00120
00121     (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
00122         This function allows the read of 512 bytes blocks.
00123         You can choose either one block read operation or multiple block read operation
00124         by adjusting the "NumberOfBlocks" parameter.
00125         After this, you have to ensure that the transfer is done correctly. The check is done
00126         through HAL_SD_GetCardState() function for SD card state.
00127         You could also check the IT transfer process through the SD Rx interrupt event.
00128
00129   *** SD Card Write operation ***
00130   ===============================
00131   [..]
00132     (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
00133         This function allows the read of 512 bytes blocks.
00134         You can choose either one block read operation or multiple block read operation
00135         by adjusting the "NumberOfBlocks" parameter.
00136         After this, you have to ensure that the transfer is done correctly. The check is done
00137         through HAL_SD_GetCardState() function for SD card state.
00138
00139     (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
00140         This function allows the read of 512 bytes blocks.
00141         You can choose either one block read operation or multiple block read operation
00142         by adjusting the "NumberOfBlocks" parameter.
00143         After this, you have to ensure that the transfer is done correctly. The check is done
00144         through HAL_SD_GetCardState() function for SD card state.
00145         You could also check the DMA transfer process through the SD Tx interrupt event.
00146
00147     (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
00148         This function allows the read of 512 bytes blocks.
00149         You can choose either one block read operation or multiple block read operation
00150         by adjusting the "NumberOfBlocks" parameter.
00151         After this, you have to ensure that the transfer is done correctly. The check is done
00152         through HAL_SD_GetCardState() function for SD card state.
00153         You could also check the IT transfer process through the SD Tx interrupt event.
00154
00155   *** SD card status ***
00156   ======================
00157   [..]
00158     (+) The SD Status contains status bits that are related to the SD Memory
00159         Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
00160
00161   *** SD card information ***
00162   ===========================
00163   [..]
00164     (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
00165         It returns useful information about the SD card such as block size, card type,
00166         block number ...
00167
00168   *** SD card CSD register ***
00169   ============================
00170   [..]
00171     (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
00172         Some of the CSD parameters are useful for card initialization and identification.
00173
00174   *** SD card CID register ***
00175   ============================
00176   [..]
00177     (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
00178         Some of the CSD parameters are useful for card initialization and identification.
00179
00180   *** SD HAL driver macros list ***
00181   ==================================
00182   [..]
00183     Below the list of most used macros in SD HAL driver.
00184
00185     (+) __HAL_SD_ENABLE : Enable the SD device
00186     (+) __HAL_SD_DISABLE : Disable the SD device
00187     (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer
00188     (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer
00189     (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
00190     (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
00191     (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
00192     (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
00193
00194    [..]
00195     (@) You can refer to the SD HAL driver header file for more useful macros
00196
00197   @endverbatim
00198   ******************************************************************************
00199   * @attention
00200   *
00201   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00202   *
00203   * Redistribution and use in source and binary forms, with or without modification,
00204   * are permitted provided that the following conditions are met:
00205   *   1. Redistributions of source code must retain the above copyright notice,
00206   *      this list of conditions and the following disclaimer.
00207   *   2. Redistributions in binary form must reproduce the above copyright notice,
00208   *      this list of conditions and the following disclaimer in the documentation
00209   *      and/or other materials provided with the distribution.
00210   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00211   *      may be used to endorse or promote products derived from this software
00212   *      without specific prior written permission.
00213   *
00214   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00215   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00216   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00217   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00218   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00219   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00220   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00221   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00222   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00223   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00224   *
00225   ******************************************************************************
00226   */
00227
00228 /* Includes ------------------------------------------------------------------*/
00229 #include "stm32f1xx_hal.h"
00230
00231 #if defined(STM32F103xE) || defined(STM32F103xG)
00232
00233 /** @addtogroup STM32F1xx_HAL_Driver
00234   * @{
00235   */
00236
00237 /** @addtogroup SD
00238   * @{
00239   */
00240 #ifdef HAL_SD_MODULE_ENABLED
00241
00242 /* Private typedef -----------------------------------------------------------*/
00243 /* Private define ------------------------------------------------------------*/
00244 /** @addtogroup SD_Private_Defines
00245   * @{
00246   */
00247
00248 /**
00249   * @}
00250   */
00251
00252 /* Private macro -------------------------------------------------------------*/
00253 /* Private variables ---------------------------------------------------------*/
00254 /* Private function prototypes -----------------------------------------------*/
00255 /* Private functions ---------------------------------------------------------*/
00256 /** @defgroup SD_Private_Functions SD Private Functions
00257   * @{
00258   */
00259 static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
00260 static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
00261 static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
00262 static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
00263 static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
00264 static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
00265 static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
00266 static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd);
00267 static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd);
00268 static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd);
00269 static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00270 static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00271 static void SD_DMAError(DMA_HandleTypeDef *hdma);
00272 static void SD_DMATxAbort(DMA_HandleTypeDef *hdma);
00273 static void SD_DMARxAbort(DMA_HandleTypeDef *hdma);
00274 /**
00275   * @}
00276   */
00277
00278 /* Exported functions --------------------------------------------------------*/
00279 /** @addtogroup SD_Exported_Functions
00280   * @{
00281   */
00282
00283 /** @addtogroup SD_Exported_Functions_Group1
00284  *  @brief   Initialization and de-initialization functions
00285  *
00286 @verbatim
00287   ==============================================================================
00288           ##### Initialization and de-initialization functions #####
00289   ==============================================================================
00290   [..]
00291     This section provides functions allowing to initialize/de-initialize the SD
00292     card device to be ready for use.
00293
00294 @endverbatim
00295   * @{
00296   */
00297
00298 /**
00299   * @brief  Initializes the SD according to the specified parameters in the
00300             SD_HandleTypeDef and create the associated handle.
00301   * @param  hsd: Pointer to the SD handle
00302   * @retval HAL status
00303   */
00304 HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
00305 {
00306   /* Check the SD handle allocation */
00307   if(hsd == NULL)
00308   {
00309     return HAL_ERROR;
00310   }
00311
00312   /* Check the parameters */
00313   assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
00314   assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge));
00315   assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass));
00316   assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
00317   assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide));
00318   assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
00319   assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv));
00320
00321   if(hsd->State == HAL_SD_STATE_RESET)
00322   {
00323     /* Allocate lock resource and initialize it */
00324     hsd->Lock = HAL_UNLOCKED;
00325     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00326     HAL_SD_MspInit(hsd);
00327   }
00328
00329   hsd->State = HAL_SD_STATE_BUSY;
00330
00331   /* Initialize the Card parameters */
00332   HAL_SD_InitCard(hsd);
00333
00334   /* Initialize the error code */
00335   hsd->ErrorCode = HAL_DMA_ERROR_NONE;
00336
00337   /* Initialize the SD operation */
00338   hsd->Context = SD_CONTEXT_NONE;
00339
00340   /* Initialize the SD state */
00341   hsd->State = HAL_SD_STATE_READY;
00342
00343   return HAL_OK;
00344 }
00345
00346 /**
00347   * @brief  Initializes the SD Card.
00348   * @param  hsd: Pointer to SD handle
00349   * @note   This function initializes the SD card. It could be used when a card
00350             re-initialization is needed.
00351   * @retval HAL status
00352   */
00353 HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
00354 {
00355   uint32_t errorstate = HAL_SD_ERROR_NONE;
00356   SD_InitTypeDef Init;
00357
00358   /* Default SDIO peripheral configuration for SD card initialization */
00359   Init.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
00360   Init.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
00361   Init.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
00362   Init.BusWide             = SDIO_BUS_WIDE_1B;
00363   Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
00364   Init.ClockDiv            = SDIO_INIT_CLK_DIV;
00365
00366   /* Initialize SDIO peripheral interface with default configuration */
00367   SDIO_Init(hsd->Instance, Init);
00368
00369   /* Disable SDIO Clock */
00370   __HAL_SD_DISABLE(hsd);
00371
00372   /* Set Power State to ON */
00373   SDIO_PowerState_ON(hsd->Instance);
00374
00375   /* Enable SDIO Clock */
00376   __HAL_SD_ENABLE(hsd);
00377
00378   /* Required power up waiting time before starting the SD initialization
00379   sequence */
00380   HAL_Delay(2U);
00381
00382   /* Identify card operating voltage */
00383   errorstate = SD_PowerON(hsd);
00384   if(errorstate != HAL_SD_ERROR_NONE)
00385   {
00386     hsd->State = HAL_SD_STATE_READY;
00387     hsd->ErrorCode |= errorstate;
00388     return HAL_ERROR;
00389   }
00390
00391   /* Card initialization */
00392   errorstate = SD_InitCard(hsd);
00393   if(errorstate != HAL_SD_ERROR_NONE)
00394   {
00395     hsd->State = HAL_SD_STATE_READY;
00396     hsd->ErrorCode |= errorstate;
00397     return HAL_ERROR;
00398   }
00399
00400   return HAL_OK;
00401 }
00402
00403 /**
00404   * @brief  De-Initializes the SD card.
00405   * @param  hsd: Pointer to SD handle
00406   * @retval HAL status
00407   */
00408 HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
00409 {
00410   /* Check the SD handle allocation */
00411   if(hsd == NULL)
00412   {
00413     return HAL_ERROR;
00414   }
00415
00416   /* Check the parameters */
00417   assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
00418
00419   hsd->State = HAL_SD_STATE_BUSY;
00420
00421   /* Set SD power state to off */
00422   SD_PowerOFF(hsd);
00423
00424   /* De-Initialize the MSP layer */
00425   HAL_SD_MspDeInit(hsd);
00426
00427   hsd->ErrorCode = HAL_SD_ERROR_NONE;
00428   hsd->State = HAL_SD_STATE_RESET;
00429
00430   return HAL_OK;
00431 }
00432
00433
00434 /**
00435   * @brief  Initializes the SD MSP.
00436   * @param  hsd: Pointer to SD handle
00437   * @retval None
00438   */
00439 __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
00440 {
00441   /* Prevent unused argument(s) compilation warning */
00442   UNUSED(hsd);
00443
00444   /* NOTE : This function Should not be modified, when the callback is needed,
00445             the HAL_SD_MspInit could be implemented in the user file
00446    */
00447 }
00448
00449 /**
00450   * @brief  De-Initialize SD MSP.
00451   * @param  hsd: Pointer to SD handle
00452   * @retval None
00453   */
00454 __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
00455 {
00456   /* Prevent unused argument(s) compilation warning */
00457   UNUSED(hsd);
00458
00459   /* NOTE : This function Should not be modified, when the callback is needed,
00460             the HAL_SD_MspDeInit could be implemented in the user file
00461    */
00462 }
00463
00464 /**
00465   * @}
00466   */
00467
00468 /** @addtogroup SD_Exported_Functions_Group2
00469  *  @brief   Data transfer functions
00470  *
00471 @verbatim
00472   ==============================================================================
00473                         ##### IO operation functions #####
00474   ==============================================================================
00475   [..]
00476     This subsection provides a set of functions allowing to manage the data
00477     transfer from/to SD card.
00478
00479 @endverbatim
00480   * @{
00481   */
00482
00483 /**
00484   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00485   *         is managed by polling mode.
00486   * @note   This API should be followed by a check on the card state through
00487   *         HAL_SD_GetCardState().
00488   * @param  hsd: Pointer to SD handle
00489   * @param  pData: pointer to the buffer that will contain the received data
00490   * @param  BlockAdd: Block Address from where data is to be read
00491   * @param  NumberOfBlocks: Number of SD blocks to read
00492   * @param  Timeout: Specify timeout value
00493   * @retval HAL status
00494   */
00495 HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
00496 {
00497   SDIO_DataInitTypeDef config;
00498   uint32_t errorstate = HAL_SD_ERROR_NONE;
00499   uint32_t tickstart = HAL_GetTick();
00500   uint32_t count = 0U, *tempbuff = (uint32_t *)pData;
00501
00502   if(NULL == pData)
00503   {
00504     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
00505     return HAL_ERROR;
00506   }
00507
00508   if(hsd->State == HAL_SD_STATE_READY)
00509   {
00510     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
00511
00512     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00513     {
00514       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00515       return HAL_ERROR;
00516     }
00517
00518     hsd->State = HAL_SD_STATE_BUSY;
00519
00520     /* Initialize data control register */
00521     hsd->Instance->DCTRL = 0U;
00522
00523     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00524     {
00525       BlockAdd *= 512U;
00526     }
00527
00528     /* Set Block Size for Card */
00529     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00530     if(errorstate != HAL_SD_ERROR_NONE)
00531     {
00532       /* Clear all the static flags */
00533       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00534       hsd->ErrorCode |= errorstate;
00535       hsd->State = HAL_SD_STATE_READY;
00536       return HAL_ERROR;
00537     }
00538
00539     /* Configure the SD DPSM (Data Path State Machine) */
00540     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00541     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
00542     config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
00543     config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
00544     config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
00545     config.DPSM          = SDIO_DPSM_ENABLE;
00546     SDIO_ConfigData(hsd->Instance, &config);
00547
00548     /* Read block(s) in polling mode */
00549     if(NumberOfBlocks > 1U)
00550     {
00551       hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
00552
00553       /* Read Multi Block command */
00554       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
00555     }
00556     else
00557     {
00558       hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
00559
00560       /* Read Single Block command */
00561       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
00562     }
00563     if(errorstate != HAL_SD_ERROR_NONE)
00564     {
00565       /* Clear all the static flags */
00566       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00567       hsd->ErrorCode |= errorstate;
00568       hsd->State = HAL_SD_STATE_READY;
00569       return HAL_ERROR;
00570     }
00571
00572     /* Poll on SDIO flags */
00573     while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR))
00574     {
00575       if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
00576       {
00577         /* Read data from SDIO Rx FIFO */
00578         for(count = 0U; count < 8U; count++)
00579         {
00580           *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
00581         }
00582         tempbuff += 8U;
00583       }
00584
00585       if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
00586       {
00587         /* Clear all the static flags */
00588         __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00589         hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
00590         hsd->State= HAL_SD_STATE_READY;
00591         return HAL_TIMEOUT;
00592       }
00593     }
00594
00595     /* Send stop transmission command in case of multiblock read */
00596     if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00597     {
00598       if(hsd->SdCard.CardType != CARD_SECURED)
00599       {
00600         /* Send stop transmission command */
00601         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
00602         if(errorstate != HAL_SD_ERROR_NONE)
00603         {
00604           /* Clear all the static flags */
00605           __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00606           hsd->ErrorCode |= errorstate;
00607           hsd->State = HAL_SD_STATE_READY;
00608           return HAL_ERROR;
00609         }
00610       }
00611     }
00612
00613     /* Get error state */
00614     if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
00615     {
00616       /* Clear all the static flags */
00617       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00618       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
00619       hsd->State = HAL_SD_STATE_READY;
00620       return HAL_ERROR;
00621     }
00622     else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
00623     {
00624       /* Clear all the static flags */
00625       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00626       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
00627       hsd->State = HAL_SD_STATE_READY;
00628       return HAL_ERROR;
00629     }
00630     else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
00631     {
00632       /* Clear all the static flags */
00633       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00634       hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
00635       hsd->State = HAL_SD_STATE_READY;
00636       return HAL_ERROR;
00637     }
00638
00639     /* Empty FIFO if there is still any data */
00640     while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
00641     {
00642       *tempbuff = SDIO_ReadFIFO(hsd->Instance);
00643       tempbuff++;
00644
00645       if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
00646       {
00647         /* Clear all the static flags */
00648         __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00649         hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
00650         hsd->State= HAL_SD_STATE_READY;
00651         return HAL_ERROR;
00652       }
00653     }
00654
00655     /* Clear all the static flags */
00656     __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00657
00658     hsd->State = HAL_SD_STATE_READY;
00659
00660     return HAL_OK;
00661   }
00662   else
00663   {
00664     hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
00665     return HAL_ERROR;
00666   }
00667 }
00668
00669 /**
00670   * @brief  Allows to write block(s) to a specified address in a card. The Data
00671   *         transfer is managed by polling mode.
00672   * @note   This API should be followed by a check on the card state through
00673   *         HAL_SD_GetCardState().
00674   * @param  hsd: Pointer to SD handle
00675   * @param  pData: pointer to the buffer that will contain the data to transmit
00676   * @param  BlockAdd: Block Address where data will be written
00677   * @param  NumberOfBlocks: Number of SD blocks to write
00678   * @param  Timeout: Specify timeout value
00679   * @retval HAL status
00680   */
00681 HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
00682 {
00683   SDIO_DataInitTypeDef config;
00684   uint32_t errorstate = HAL_SD_ERROR_NONE;
00685   uint32_t tickstart = HAL_GetTick();
00686   uint32_t count = 0U;
00687   uint32_t *tempbuff = (uint32_t *)pData;
00688
00689   if(NULL == pData)
00690   {
00691     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
00692     return HAL_ERROR;
00693   }
00694
00695   if(hsd->State == HAL_SD_STATE_READY)
00696   {
00697     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
00698
00699     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00700     {
00701       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00702       return HAL_ERROR;
00703     }
00704
00705     hsd->State = HAL_SD_STATE_BUSY;
00706
00707     /* Initialize data control register */
00708     hsd->Instance->DCTRL = 0U;
00709
00710     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00711     {
00712       BlockAdd *= 512U;
00713     }
00714
00715     /* Set Block Size for Card */
00716     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00717     if(errorstate != HAL_SD_ERROR_NONE)
00718     {
00719       /* Clear all the static flags */
00720       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00721       hsd->ErrorCode |= errorstate;
00722       hsd->State = HAL_SD_STATE_READY;
00723       return HAL_ERROR;
00724     }
00725
00726     /* Write Blocks in Polling mode */
00727     if(NumberOfBlocks > 1U)
00728     {
00729       hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
00730
00731       /* Write Multi Block command */
00732       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
00733     }
00734     else
00735     {
00736       hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
00737
00738       /* Write Single Block command */
00739       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
00740     }
00741     if(errorstate != HAL_SD_ERROR_NONE)
00742     {
00743       /* Clear all the static flags */
00744       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00745       hsd->ErrorCode |= errorstate;
00746       hsd->State = HAL_SD_STATE_READY;
00747       return HAL_ERROR;
00748     }
00749
00750     /* Configure the SD DPSM (Data Path State Machine) */
00751     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00752     config.DataLength    = NumberOfBlocks * BLOCKSIZE;
00753     config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
00754     config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
00755     config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
00756     config.DPSM          = SDIO_DPSM_ENABLE;
00757     SDIO_ConfigData(hsd->Instance, &config);
00758
00759     /* Write block(s) in polling mode */
00760     while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
00761     {
00762       if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
00763       {
00764         /* Write data to SDIO Tx FIFO */
00765         for(count = 0U; count < 8U; count++)
00766         {
00767           SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
00768         }
00769         tempbuff += 8U;
00770       }
00771
00772       if((Timeout == 0U)||((HAL_GetTick()-tickstart) >=  Timeout))
00773       {
00774         /* Clear all the static flags */
00775         __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00776         hsd->ErrorCode |= errorstate;
00777         hsd->State = HAL_SD_STATE_READY;
00778         return HAL_TIMEOUT;
00779       }
00780     }
00781
00782     /* Send stop transmission command in case of multiblock write */
00783     if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
00784     {
00785       if(hsd->SdCard.CardType != CARD_SECURED)
00786       {
00787         /* Send stop transmission command */
00788         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
00789         if(errorstate != HAL_SD_ERROR_NONE)
00790         {
00791           /* Clear all the static flags */
00792           __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00793           hsd->ErrorCode |= errorstate;
00794           hsd->State = HAL_SD_STATE_READY;
00795           return HAL_ERROR;
00796         }
00797       }
00798     }
00799
00800     /* Get error state */
00801     if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
00802     {
00803       /* Clear all the static flags */
00804       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00805       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
00806       hsd->State = HAL_SD_STATE_READY;
00807       return HAL_ERROR;
00808     }
00809     else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
00810     {
00811       /* Clear all the static flags */
00812       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00813       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
00814       hsd->State = HAL_SD_STATE_READY;
00815       return HAL_ERROR;
00816     }
00817     else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
00818     {
00819       /* Clear all the static flags */
00820       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00821       hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
00822       hsd->State = HAL_SD_STATE_READY;
00823       return HAL_ERROR;
00824     }
00825
00826     /* Clear all the static flags */
00827     __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00828
00829     hsd->State = HAL_SD_STATE_READY;
00830
00831     return HAL_OK;
00832   }
00833   else
00834   {
00835     hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
00836     return HAL_ERROR;
00837   }
00838 }
00839
00840 /**
00841   * @brief  Reads block(s) from a specified address in a card. The Data transfer
00842   *         is managed in interrupt mode.
00843   * @note   This API should be followed by a check on the card state through
00844   *         HAL_SD_GetCardState().
00845   * @note   You could also check the IT transfer process through the SD Rx
00846   *         interrupt event.
00847   * @param  hsd: Pointer to SD handle
00848   * @param  pData: Pointer to the buffer that will contain the received data
00849   * @param  BlockAdd: Block Address from where data is to be read
00850   * @param  NumberOfBlocks: Number of blocks to read.
00851   * @retval HAL status
00852   */
00853 HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00854 {
00855   SDIO_DataInitTypeDef config;
00856   uint32_t errorstate = HAL_SD_ERROR_NONE;
00857
00858   if(NULL == pData)
00859   {
00860     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
00861     return HAL_ERROR;
00862   }
00863
00864   if(hsd->State == HAL_SD_STATE_READY)
00865   {
00866     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
00867
00868     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00869     {
00870       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00871       return HAL_ERROR;
00872     }
00873
00874     hsd->State = HAL_SD_STATE_BUSY;
00875
00876     /* Initialize data control register */
00877     hsd->Instance->DCTRL = 0U;
00878
00879     hsd->pRxBuffPtr = (uint32_t *)pData;
00880     hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
00881
00882     __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR));
00883
00884     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00885     {
00886       BlockAdd *= 512U;
00887     }
00888
00889     /* Configure the SD DPSM (Data Path State Machine) */
00890     config.DataTimeOut   = SDMMC_DATATIMEOUT;
00891     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
00892     config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
00893     config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
00894     config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
00895     config.DPSM          = SDIO_DPSM_ENABLE;
00896     SDIO_ConfigData(hsd->Instance, &config);
00897
00898     /* Set Block Size for Card */
00899     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00900     if(errorstate != HAL_SD_ERROR_NONE)
00901     {
00902       /* Clear all the static flags */
00903       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00904       hsd->ErrorCode |= errorstate;
00905       hsd->State = HAL_SD_STATE_READY;
00906       return HAL_ERROR;
00907     }
00908
00909     /* Read Blocks in IT mode */
00910     if(NumberOfBlocks > 1U)
00911     {
00912       hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
00913
00914       /* Read Multi Block command */
00915       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
00916     }
00917     else
00918     {
00919       hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
00920
00921       /* Read Single Block command */
00922       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
00923     }
00924     if(errorstate != HAL_SD_ERROR_NONE)
00925     {
00926       /* Clear all the static flags */
00927       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00928       hsd->ErrorCode |= errorstate;
00929       hsd->State = HAL_SD_STATE_READY;
00930       return HAL_ERROR;
00931     }
00932
00933     return HAL_OK;
00934   }
00935   else
00936   {
00937     return HAL_BUSY;
00938   }
00939 }
00940
00941 /**
00942   * @brief  Writes block(s) to a specified address in a card. The Data transfer
00943   *         is managed in interrupt mode.
00944   * @note   This API should be followed by a check on the card state through
00945   *         HAL_SD_GetCardState().
00946   * @note   You could also check the IT transfer process through the SD Tx
00947   *         interrupt event.
00948   * @param  hsd: Pointer to SD handle
00949   * @param  pData: Pointer to the buffer that will contain the data to transmit
00950   * @param  BlockAdd: Block Address where data will be written
00951   * @param  NumberOfBlocks: Number of blocks to write
00952   * @retval HAL status
00953   */
00954 HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
00955 {
00956   SDIO_DataInitTypeDef config;
00957   uint32_t errorstate = HAL_SD_ERROR_NONE;
00958
00959   if(NULL == pData)
00960   {
00961     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
00962     return HAL_ERROR;
00963   }
00964
00965   if(hsd->State == HAL_SD_STATE_READY)
00966   {
00967     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
00968
00969     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
00970     {
00971       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
00972       return HAL_ERROR;
00973     }
00974
00975     hsd->State = HAL_SD_STATE_BUSY;
00976
00977     /* Initialize data control register */
00978     hsd->Instance->DCTRL = 0U;
00979
00980     hsd->pTxBuffPtr = (uint32_t *)pData;
00981     hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
00982
00983     /* Enable transfer interrupts */
00984     __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));
00985
00986     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
00987     {
00988       BlockAdd *= 512U;
00989     }
00990
00991     /* Set Block Size for Card */
00992     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
00993     if(errorstate != HAL_SD_ERROR_NONE)
00994     {
00995       /* Clear all the static flags */
00996       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
00997       hsd->ErrorCode |= errorstate;
00998       hsd->State = HAL_SD_STATE_READY;
00999       return HAL_ERROR;
01000     }
01001
01002     /* Write Blocks in Polling mode */
01003     if(NumberOfBlocks > 1U)
01004     {
01005       hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
01006
01007       /* Write Multi Block command */
01008       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
01009     }
01010     else
01011     {
01012       hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
01013
01014       /* Write Single Block command */
01015       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
01016     }
01017     if(errorstate != HAL_SD_ERROR_NONE)
01018     {
01019       /* Clear all the static flags */
01020       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01021       hsd->ErrorCode |= errorstate;
01022       hsd->State = HAL_SD_STATE_READY;
01023       return HAL_ERROR;
01024     }
01025
01026     /* Configure the SD DPSM (Data Path State Machine) */
01027     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01028     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01029     config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
01030     config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
01031     config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
01032     config.DPSM          = SDIO_DPSM_ENABLE;
01033     SDIO_ConfigData(hsd->Instance, &config);
01034
01035     return HAL_OK;
01036   }
01037   else
01038   {
01039     return HAL_BUSY;
01040   }
01041 }
01042
01043 /**
01044   * @brief  Reads block(s) from a specified address in a card. The Data transfer
01045   *         is managed by DMA mode.
01046   * @note   This API should be followed by a check on the card state through
01047   *         HAL_SD_GetCardState().
01048   * @note   You could also check the DMA transfer process through the SD Rx
01049   *         interrupt event.
01050   * @param  hsd: Pointer SD handle
01051   * @param  pData: Pointer to the buffer that will contain the received data
01052   * @param  BlockAdd: Block Address from where data is to be read
01053   * @param  NumberOfBlocks: Number of blocks to read.
01054   * @retval HAL status
01055   */
01056 HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01057 {
01058   SDIO_DataInitTypeDef config;
01059   uint32_t errorstate = HAL_SD_ERROR_NONE;
01060
01061   if(NULL == pData)
01062   {
01063     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01064     return HAL_ERROR;
01065   }
01066
01067   if(hsd->State == HAL_SD_STATE_READY)
01068   {
01069     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
01070
01071     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
01072     {
01073       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01074       return HAL_ERROR;
01075     }
01076
01077     hsd->State = HAL_SD_STATE_BUSY;
01078
01079     /* Initialize data control register */
01080     hsd->Instance->DCTRL = 0U;
01081
01082     __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
01083
01084     /* Set the DMA transfer complete callback */
01085     hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
01086
01087     /* Set the DMA error callback */
01088     hsd->hdmarx->XferErrorCallback = SD_DMAError;
01089
01090     /* Set the DMA Abort callback */
01091     hsd->hdmarx->XferAbortCallback = NULL;
01092
01093     /* Enable the DMA Channel */
01094     HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
01095
01096     /* Enable SD DMA transfer */
01097     __HAL_SD_DMA_ENABLE(hsd);
01098
01099     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01100     {
01101       BlockAdd *= 512U;
01102     }
01103
01104     /* Configure the SD DPSM (Data Path State Machine) */
01105     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01106     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01107     config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
01108     config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
01109     config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
01110     config.DPSM          = SDIO_DPSM_ENABLE;
01111     SDIO_ConfigData(hsd->Instance, &config);
01112
01113     /* Set Block Size for Card */
01114     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
01115     if(errorstate != HAL_SD_ERROR_NONE)
01116     {
01117       /* Clear all the static flags */
01118       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01119       hsd->ErrorCode |= errorstate;
01120       hsd->State = HAL_SD_STATE_READY;
01121       return HAL_ERROR;
01122     }
01123
01124     /* Read Blocks in DMA mode */
01125     if(NumberOfBlocks > 1U)
01126     {
01127       hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
01128
01129       /* Read Multi Block command */
01130       errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
01131     }
01132     else
01133     {
01134       hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
01135
01136       /* Read Single Block command */
01137       errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
01138     }
01139     if(errorstate != HAL_SD_ERROR_NONE)
01140     {
01141       /* Clear all the static flags */
01142       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01143       hsd->ErrorCode |= errorstate;
01144       hsd->State = HAL_SD_STATE_READY;
01145       return HAL_ERROR;
01146     }
01147
01148     return HAL_OK;
01149   }
01150   else
01151   {
01152     return HAL_BUSY;
01153   }
01154 }
01155
01156 /**
01157   * @brief  Writes block(s) to a specified address in a card. The Data transfer
01158   *         is managed by DMA mode.
01159   * @note   This API should be followed by a check on the card state through
01160   *         HAL_SD_GetCardState().
01161   * @note   You could also check the DMA transfer process through the SD Tx
01162   *         interrupt event.
01163   * @param  hsd: Pointer to SD handle
01164   * @param  pData: Pointer to the buffer that will contain the data to transmit
01165   * @param  BlockAdd: Block Address where data will be written
01166   * @param  NumberOfBlocks: Number of blocks to write
01167   * @retval HAL status
01168   */
01169 HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
01170 {
01171   SDIO_DataInitTypeDef config;
01172   uint32_t errorstate = HAL_SD_ERROR_NONE;
01173
01174   if(NULL == pData)
01175   {
01176     hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01177     return HAL_ERROR;
01178   }
01179
01180   if(hsd->State == HAL_SD_STATE_READY)
01181   {
01182     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
01183
01184     if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
01185     {
01186       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01187       return HAL_ERROR;
01188     }
01189
01190     hsd->State = HAL_SD_STATE_BUSY;
01191
01192     /* Initialize data control register */
01193     hsd->Instance->DCTRL = 0U;
01194
01195     /* Enable SD Error interrupts */
01196     __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
01197
01198     /* Set the DMA transfer complete callback */
01199     hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
01200
01201     /* Set the DMA error callback */
01202     hsd->hdmatx->XferErrorCallback = SD_DMAError;
01203
01204     /* Set the DMA Abort callback */
01205     hsd->hdmatx->XferAbortCallback = NULL;
01206
01207     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01208     {
01209       BlockAdd *= 512U;
01210     }
01211
01212     /* Set Block Size for Card */
01213     errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
01214     if(errorstate != HAL_SD_ERROR_NONE)
01215     {
01216       /* Clear all the static flags */
01217       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01218       hsd->ErrorCode |= errorstate;
01219       hsd->State = HAL_SD_STATE_READY;
01220       return HAL_ERROR;
01221     }
01222
01223     /* Write Blocks in Polling mode */
01224     if(NumberOfBlocks > 1U)
01225     {
01226       hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
01227
01228       /* Write Multi Block command */
01229       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
01230     }
01231     else
01232     {
01233       hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
01234
01235       /* Write Single Block command */
01236       errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
01237     }
01238     if(errorstate != HAL_SD_ERROR_NONE)
01239     {
01240       /* Clear all the static flags */
01241       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01242       hsd->ErrorCode |= errorstate;
01243       hsd->State = HAL_SD_STATE_READY;
01244       return HAL_ERROR;
01245     }
01246
01247     /* Enable SDIO DMA transfer */
01248     __HAL_SD_DMA_ENABLE(hsd);
01249
01250     /* Enable the DMA Channel */
01251     HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
01252
01253     /* Configure the SD DPSM (Data Path State Machine) */
01254     config.DataTimeOut   = SDMMC_DATATIMEOUT;
01255     config.DataLength    = BLOCKSIZE * NumberOfBlocks;
01256     config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
01257     config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
01258     config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
01259     config.DPSM          = SDIO_DPSM_ENABLE;
01260     SDIO_ConfigData(hsd->Instance, &config);
01261
01262     return HAL_OK;
01263   }
01264   else
01265   {
01266     return HAL_BUSY;
01267   }
01268 }
01269
01270 /**
01271   * @brief  Erases the specified memory area of the given SD card.
01272   * @note   This API should be followed by a check on the card state through
01273   *         HAL_SD_GetCardState().
01274   * @param  hsd: Pointer to SD handle
01275   * @param  BlockStartAdd: Start Block address
01276   * @param  BlockEndAdd: End Block address
01277   * @retval HAL status
01278   */
01279 HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
01280 {
01281   uint32_t errorstate = HAL_SD_ERROR_NONE;
01282
01283   if(hsd->State == HAL_SD_STATE_READY)
01284   {
01285     hsd->ErrorCode = HAL_DMA_ERROR_NONE;
01286
01287     if(BlockEndAdd < BlockStartAdd)
01288     {
01289       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
01290       return HAL_ERROR;
01291     }
01292
01293     if(BlockEndAdd > (hsd->SdCard.LogBlockNbr))
01294     {
01295       hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
01296       return HAL_ERROR;
01297     }
01298
01299     hsd->State = HAL_SD_STATE_BUSY;
01300
01301     /* Check if the card command class supports erase command */
01302     if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U)
01303     {
01304       /* Clear all the static flags */
01305       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01306       hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
01307       hsd->State = HAL_SD_STATE_READY;
01308       return HAL_ERROR;
01309     }
01310
01311     if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
01312     {
01313       /* Clear all the static flags */
01314       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01315       hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
01316       hsd->State = HAL_SD_STATE_READY;
01317       return HAL_ERROR;
01318     }
01319
01320     /* Get start and end block for high capacity cards */
01321     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
01322     {
01323       BlockStartAdd *= 512U;
01324       BlockEndAdd   *= 512U;
01325     }
01326
01327     /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
01328     if(hsd->SdCard.CardType != CARD_SECURED)
01329     {
01330       /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
01331       errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd);
01332       if(errorstate != HAL_SD_ERROR_NONE)
01333       {
01334         /* Clear all the static flags */
01335         __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01336         hsd->ErrorCode |= errorstate;
01337         hsd->State = HAL_SD_STATE_READY;
01338         return HAL_ERROR;
01339       }
01340
01341       /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
01342       errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd);
01343       if(errorstate != HAL_SD_ERROR_NONE)
01344       {
01345         /* Clear all the static flags */
01346         __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01347         hsd->ErrorCode |= errorstate;
01348         hsd->State = HAL_SD_STATE_READY;
01349         return HAL_ERROR;
01350       }
01351     }
01352
01353     /* Send CMD38 ERASE */
01354     errorstate = SDMMC_CmdErase(hsd->Instance);
01355     if(errorstate != HAL_SD_ERROR_NONE)
01356     {
01357       /* Clear all the static flags */
01358       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01359       hsd->ErrorCode |= errorstate;
01360       hsd->State = HAL_SD_STATE_READY;
01361       return HAL_ERROR;
01362     }
01363
01364     hsd->State = HAL_SD_STATE_READY;
01365
01366     return HAL_OK;
01367   }
01368   else
01369   {
01370     return HAL_BUSY;
01371   }
01372 }
01373
01374 /**
01375   * @brief  This function handles SD card interrupt request.
01376   * @param  hsd: Pointer to SD handle
01377   * @retval None
01378   */
01379 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
01380 {
01381   uint32_t errorstate = HAL_SD_ERROR_NONE;
01382
01383   /* Check for SDIO interrupt flags */
01384   if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DATAEND) != RESET)
01385   {
01386     __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);
01387
01388     __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
01389                              SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
01390
01391     if((hsd->Context & SD_CONTEXT_IT) != RESET)
01392     {
01393       if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
01394       {
01395         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
01396         if(errorstate != HAL_SD_ERROR_NONE)
01397         {
01398           hsd->ErrorCode |= errorstate;
01399           HAL_SD_ErrorCallback(hsd);
01400         }
01401       }
01402
01403       /* Clear all the static flags */
01404       __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01405
01406       hsd->State = HAL_SD_STATE_READY;
01407       if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
01408       {
01409         HAL_SD_RxCpltCallback(hsd);
01410       }
01411       else
01412       {
01413         HAL_SD_TxCpltCallback(hsd);
01414       }
01415     }
01416     else if((hsd->Context & SD_CONTEXT_DMA) != RESET)
01417     {
01418       if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
01419       {
01420         errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
01421         if(errorstate != HAL_SD_ERROR_NONE)
01422         {
01423           hsd->ErrorCode |= errorstate;
01424           HAL_SD_ErrorCallback(hsd);
01425         }
01426       }
01427       if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
01428       {
01429         /* Disable the DMA transfer for transmit request by setting the DMAEN bit
01430         in the SD DCTRL register */
01431         hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
01432
01433         hsd->State = HAL_SD_STATE_READY;
01434
01435         HAL_SD_TxCpltCallback(hsd);
01436       }
01437     }
01438   }
01439
01440   else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXFIFOHE) != RESET)
01441   {
01442     __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_TXFIFOHE);
01443
01444     SD_Write_IT(hsd);
01445   }
01446
01447   else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXFIFOHF) != RESET)
01448   {
01449     __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXFIFOHF);
01450
01451     SD_Read_IT(hsd);
01452   }
01453
01454   else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET)
01455   {
01456     /* Set Error code */
01457     if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL) != RESET)
01458     {
01459       hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
01460     }
01461     if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DTIMEOUT) != RESET)
01462     {
01463       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
01464     }
01465     if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXOVERR) != RESET)
01466     {
01467       hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
01468     }
01469     if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXUNDERR) != RESET)
01470     {
01471       hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
01472     }
01473     if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_STBITERR) != RESET)
01474     {
01475       hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
01476     }
01477
01478     /* Clear All flags */
01479     __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR);
01480
01481     /* Disable all interrupts */
01482     __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
01483                              SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR);
01484
01485     if((hsd->Context & SD_CONTEXT_DMA) != RESET)
01486     {
01487       /* Abort the SD DMA Streams */
01488       if(hsd->hdmatx != NULL)
01489       {
01490         /* Set the DMA Tx abort callback */
01491         hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
01492         /* Abort DMA in IT mode */
01493         if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
01494         {
01495           SD_DMATxAbort(hsd->hdmatx);
01496         }
01497       }
01498       else if(hsd->hdmarx != NULL)
01499       {
01500         /* Set the DMA Rx abort callback */
01501         hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
01502         /* Abort DMA in IT mode */
01503         if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
01504         {
01505           SD_DMARxAbort(hsd->hdmarx);
01506         }
01507       }
01508       else
01509       {
01510         hsd->ErrorCode = HAL_SD_ERROR_NONE;
01511         hsd->State = HAL_SD_STATE_READY;
01512         HAL_SD_AbortCallback(hsd);
01513       }
01514     }
01515     else if((hsd->Context & SD_CONTEXT_IT) != RESET)
01516     {
01517       /* Set the SD state to ready to be able to start again the process */
01518       hsd->State = HAL_SD_STATE_READY;
01519       HAL_SD_ErrorCallback(hsd);
01520     }
01521   }
01522 }
01523
01524 /**
01525   * @brief return the SD state
01526   * @param hsd: Pointer to sd handle
01527   * @retval HAL state
01528   */
01529 HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
01530 {
01531   return hsd->State;
01532 }
01533
01534 /**
01535 * @brief  Return the SD error code
01536 * @param  hsd : Pointer to a SD_HandleTypeDef structure that contains
01537   *              the configuration information.
01538 * @retval SD Error Code
01539 */
01540 uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
01541 {
01542   return hsd->ErrorCode;
01543 }
01544
01545 /**
01546   * @brief Tx Transfer completed callbacks
01547   * @param hsd: Pointer to SD handle
01548   * @retval None
01549   */
01550  __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
01551 {
01552   /* Prevent unused argument(s) compilation warning */
01553   UNUSED(hsd);
01554
01555   /* NOTE : This function should not be modified, when the callback is needed,
01556             the HAL_SD_TxCpltCallback can be implemented in the user file
01557    */
01558 }
01559
01560 /**
01561   * @brief Rx Transfer completed callbacks
01562   * @param hsd: Pointer SD handle
01563   * @retval None
01564   */
01565 __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
01566 {
01567   /* Prevent unused argument(s) compilation warning */
01568   UNUSED(hsd);
01569
01570   /* NOTE : This function should not be modified, when the callback is needed,
01571             the HAL_SD_RxCpltCallback can be implemented in the user file
01572    */
01573 }
01574
01575 /**
01576   * @brief SD error callbacks
01577   * @param hsd: Pointer SD handle
01578   * @retval None
01579   */
01580 __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
01581 {
01582   /* Prevent unused argument(s) compilation warning */
01583   UNUSED(hsd);
01584
01585   /* NOTE : This function should not be modified, when the callback is needed,
01586             the HAL_SD_ErrorCallback can be implemented in the user file
01587    */
01588 }
01589
01590 /**
01591   * @brief SD Abort callbacks
01592   * @param hsd: Pointer SD handle
01593   * @retval None
01594   */
01595 __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
01596 {
01597   /* Prevent unused argument(s) compilation warning */
01598   UNUSED(hsd);
01599
01600   /* NOTE : This function should not be modified, when the callback is needed,
01601             the HAL_SD_ErrorCallback can be implemented in the user file
01602    */
01603 }
01604
01605
01606 /**
01607   * @}
01608   */
01609
01610 /** @addtogroup SD_Exported_Functions_Group3
01611  *  @brief   management functions
01612  *
01613 @verbatim
01614   ==============================================================================
01615                       ##### Peripheral Control functions #####
01616   ==============================================================================
01617   [..]
01618     This subsection provides a set of functions allowing to control the SD card
01619     operations and get the related information
01620
01621 @endverbatim
01622   * @{
01623   */
01624
01625 /**
01626   * @brief  Returns information the information of the card which are stored on
01627   *         the CID register.
01628   * @param  hsd: Pointer to SD handle
01629   * @param  pCID: Pointer to a HAL_SD_CIDTypeDef structure that
01630   *         contains all CID register parameters
01631   * @retval HAL status
01632   */
01633 HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
01634 {
01635   uint32_t tmp = 0U;
01636
01637   /* Byte 0 */
01638   tmp = (uint8_t)((hsd->CID[0U] & 0xFF000000U) >> 24U);
01639   pCID->ManufacturerID = tmp;
01640
01641   /* Byte 1 */
01642   tmp = (uint8_t)((hsd->CID[0U] & 0x00FF0000U) >> 16U);
01643   pCID->OEM_AppliID = tmp << 8U;
01644
01645   /* Byte 2 */
01646   tmp = (uint8_t)((hsd->CID[0U] & 0x000000FF00U) >> 8U);
01647   pCID->OEM_AppliID |= tmp;
01648
01649   /* Byte 3 */
01650   tmp = (uint8_t)(hsd->CID[0U] & 0x000000FFU);
01651   pCID->ProdName1 = tmp << 24U;
01652
01653   /* Byte 4 */
01654   tmp = (uint8_t)((hsd->CID[1U] & 0xFF000000U) >> 24U);
01655   pCID->ProdName1 |= tmp << 16;
01656
01657   /* Byte 5 */
01658   tmp = (uint8_t)((hsd->CID[1U] & 0x00FF0000U) >> 16U);
01659   pCID->ProdName1 |= tmp << 8U;
01660
01661   /* Byte 6 */
01662   tmp = (uint8_t)((hsd->CID[1U] & 0x0000FF00U) >> 8U);
01663   pCID->ProdName1 |= tmp;
01664
01665   /* Byte 7 */
01666   tmp = (uint8_t)(hsd->CID[1U] & 0x000000FFU);
01667   pCID->ProdName2 = tmp;
01668
01669   /* Byte 8 */
01670   tmp = (uint8_t)((hsd->CID[2U] & 0xFF000000U) >> 24U);
01671   pCID->ProdRev = tmp;
01672
01673   /* Byte 9 */
01674   tmp = (uint8_t)((hsd->CID[2U] & 0x00FF0000U) >> 16U);
01675   pCID->ProdSN = tmp << 24U;
01676
01677   /* Byte 10 */
01678   tmp = (uint8_t)((hsd->CID[2U] & 0x0000FF00U) >> 8U);
01679   pCID->ProdSN |= tmp << 16U;
01680
01681   /* Byte 11 */
01682   tmp = (uint8_t)(hsd->CID[2U] & 0x000000FFU);
01683   pCID->ProdSN |= tmp << 8U;
01684
01685   /* Byte 12 */
01686   tmp = (uint8_t)((hsd->CID[3U] & 0xFF000000U) >> 24U);
01687   pCID->ProdSN |= tmp;
01688
01689   /* Byte 13 */
01690   tmp = (uint8_t)((hsd->CID[3U] & 0x00FF0000U) >> 16U);
01691   pCID->Reserved1   |= (tmp & 0xF0U) >> 4U;
01692   pCID->ManufactDate = (tmp & 0x0FU) << 8U;
01693
01694   /* Byte 14 */
01695   tmp = (uint8_t)((hsd->CID[3U] & 0x0000FF00U) >> 8U);
01696   pCID->ManufactDate |= tmp;
01697
01698   /* Byte 15 */
01699   tmp = (uint8_t)(hsd->CID[3U] & 0x000000FFU);
01700   pCID->CID_CRC   = (tmp & 0xFEU) >> 1U;
01701   pCID->Reserved2 = 1U;
01702
01703   return HAL_OK;
01704 }
01705
01706 /**
01707   * @brief  Returns information the information of the card which are stored on
01708   *         the CSD register.
01709   * @param  hsd: Pointer to SD handle
01710   * @param  pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
01711   *         contains all CSD register parameters
01712   * @retval HAL status
01713   */
01714 HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
01715 {
01716   uint32_t tmp = 0U;
01717
01718   /* Byte 0 */
01719   tmp = (hsd->CSD[0U] & 0xFF000000U) >> 24U;
01720   pCSD->CSDStruct      = (uint8_t)((tmp & 0xC0U) >> 6U);
01721   pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
01722   pCSD->Reserved1      = tmp & 0x03U;
01723
01724   /* Byte 1 */
01725   tmp = (hsd->CSD[0U] & 0x00FF0000U) >> 16U;
01726   pCSD->TAAC = (uint8_t)tmp;
01727
01728   /* Byte 2 */
01729   tmp = (hsd->CSD[0U] & 0x0000FF00U) >> 8U;
01730   pCSD->NSAC = (uint8_t)tmp;
01731
01732   /* Byte 3 */
01733   tmp = hsd->CSD[0U] & 0x000000FFU;
01734   pCSD->MaxBusClkFrec = (uint8_t)tmp;
01735
01736   /* Byte 4 */
01737   tmp = (hsd->CSD[1U] & 0xFF000000U) >> 24U;
01738   pCSD->CardComdClasses = (uint16_t)(tmp << 4U);
01739
01740   /* Byte 5 */
01741   tmp = (hsd->CSD[1U] & 0x00FF0000U) >> 16U;
01742   pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U);
01743   pCSD->RdBlockLen       = (uint8_t)(tmp & 0x0FU);
01744
01745   /* Byte 6 */
01746   tmp = (hsd->CSD[1U] & 0x0000FF00U) >> 8U;
01747   pCSD->PartBlockRead   = (uint8_t)((tmp & 0x80U) >> 7U);
01748   pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
01749   pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
01750   pCSD->DSRImpl         = (uint8_t)((tmp & 0x10U) >> 4U);
01751   pCSD->Reserved2       = 0U; /*!< Reserved */
01752
01753   if(hsd->SdCard.CardType == CARD_SDSC)
01754   {
01755     pCSD->DeviceSize = (tmp & 0x03U) << 10U;
01756
01757     /* Byte 7 */
01758     tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
01759     pCSD->DeviceSize |= (tmp) << 2U;
01760
01761     /* Byte 8 */
01762     tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
01763     pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U;
01764
01765     pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
01766     pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U);
01767
01768     /* Byte 9 */
01769     tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
01770     pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
01771     pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
01772     pCSD->DeviceSizeMul      = (tmp & 0x03U) << 1U;
01773     /* Byte 10 */
01774     tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
01775     pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U;
01776
01777     hsd->SdCard.BlockNbr  = (pCSD->DeviceSize + 1U) ;
01778     hsd->SdCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U));
01779     hsd->SdCard.BlockSize = 1U << (pCSD->RdBlockLen);
01780
01781     hsd->SdCard.LogBlockNbr =  (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
01782     hsd->SdCard.LogBlockSize = 512U;
01783   }
01784   else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
01785   {
01786     /* Byte 7 */
01787     tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
01788     pCSD->DeviceSize = (tmp & 0x3FU) << 16U;
01789
01790     /* Byte 8 */
01791     tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
01792
01793     pCSD->DeviceSize |= (tmp << 8U);
01794
01795     /* Byte 9 */
01796     tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
01797
01798     pCSD->DeviceSize |= (tmp);
01799
01800     /* Byte 10 */
01801     tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
01802
01803     hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1U) * 1024U);
01804     hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512U;
01805   }
01806   else
01807   {
01808     /* Clear all the static flags */
01809     __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01810     hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
01811     hsd->State = HAL_SD_STATE_READY;
01812     return HAL_ERROR;
01813   }
01814
01815   pCSD->EraseGrSize = (tmp & 0x40U) >> 6U;
01816   pCSD->EraseGrMul  = (tmp & 0x3FU) << 1U;
01817
01818   /* Byte 11 */
01819   tmp = (uint8_t)(hsd->CSD[2U] & 0x000000FFU);
01820   pCSD->EraseGrMul     |= (tmp & 0x80U) >> 7U;
01821   pCSD->WrProtectGrSize = (tmp & 0x7FU);
01822
01823   /* Byte 12 */
01824   tmp = (uint8_t)((hsd->CSD[3U] & 0xFF000000U) >> 24U);
01825   pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U;
01826   pCSD->ManDeflECC        = (tmp & 0x60U) >> 5U;
01827   pCSD->WrSpeedFact       = (tmp & 0x1CU) >> 2U;
01828   pCSD->MaxWrBlockLen     = (tmp & 0x03U) << 2U;
01829
01830   /* Byte 13 */
01831   tmp = (uint8_t)((hsd->CSD[3U] & 0x00FF0000U) >> 16U);
01832   pCSD->MaxWrBlockLen      |= (tmp & 0xC0U) >> 6U;
01833   pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
01834   pCSD->Reserved3           = 0U;
01835   pCSD->ContentProtectAppli = (tmp & 0x01U);
01836
01837   /* Byte 14 */
01838   tmp = (uint8_t)((hsd->CSD[3U] & 0x0000FF00U) >> 8U);
01839   pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U;
01840   pCSD->CopyFlag         = (tmp & 0x40U) >> 6U;
01841   pCSD->PermWrProtect    = (tmp & 0x20U) >> 5U;
01842   pCSD->TempWrProtect    = (tmp & 0x10U) >> 4U;
01843   pCSD->FileFormat       = (tmp & 0x0CU) >> 2U;
01844   pCSD->ECC              = (tmp & 0x03U);
01845
01846   /* Byte 15 */
01847   tmp = (uint8_t)(hsd->CSD[3U] & 0x000000FFU);
01848   pCSD->CSD_CRC   = (tmp & 0xFEU) >> 1U;
01849   pCSD->Reserved4 = 1U;
01850
01851   return HAL_OK;
01852 }
01853
01854 /**
01855   * @brief  Gets the SD status info.
01856   * @param  hsd: Pointer to SD handle
01857   * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
01858   *         will contain the SD card status information
01859   * @retval HAL status
01860   */
01861 HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
01862 {
01863   uint32_t tmp = 0U;
01864   uint32_t sd_status[16U];
01865   uint32_t errorstate = HAL_SD_ERROR_NONE;
01866
01867   errorstate = SD_SendSDStatus(hsd, sd_status);
01868   if(errorstate != HAL_OK)
01869   {
01870     /* Clear all the static flags */
01871     __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
01872     hsd->ErrorCode |= errorstate;
01873     hsd->State = HAL_SD_STATE_READY;
01874     return HAL_ERROR;
01875   }
01876   else
01877   {
01878     /* Byte 0 */
01879     tmp = (sd_status[0U] & 0xC0U) >> 6U;
01880     pStatus->DataBusWidth = (uint8_t)tmp;
01881
01882     /* Byte 0 */
01883     tmp = (sd_status[0U] & 0x20U) >> 5U;
01884     pStatus->SecuredMode = (uint8_t)tmp;
01885
01886     /* Byte 2 */
01887     tmp = (sd_status[0U] & 0x00FF0000U) >> 16U;
01888     pStatus->CardType = (uint16_t)(tmp << 8U);
01889
01890     /* Byte 3 */
01891     tmp = (sd_status[0U] & 0xFF000000U) >> 24U;
01892     pStatus->CardType |= (uint16_t)tmp;
01893
01894     /* Byte 4 */
01895     tmp = (sd_status[1U] & 0xFFU);
01896     pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24U);
01897
01898     /* Byte 5 */
01899     tmp = (sd_status[1U] & 0xFF00U) >> 8U;
01900     pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16U);
01901
01902     /* Byte 6 */
01903     tmp = (sd_status[1U] & 0xFF0000U) >> 16U;
01904     pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8U);
01905
01906     /* Byte 7 */
01907     tmp = (sd_status[1U] & 0xFF000000U) >> 24U;
01908     pStatus->ProtectedAreaSize |= (uint32_t)tmp;
01909
01910     /* Byte 8 */
01911     tmp = (sd_status[2U] & 0xFFU);
01912     pStatus->SpeedClass = (uint8_t)tmp;
01913
01914     /* Byte 9 */
01915     tmp = (sd_status[2U] & 0xFF00U) >> 8U;
01916     pStatus->PerformanceMove = (uint8_t)tmp;
01917
01918     /* Byte 10 */
01919     tmp = (sd_status[2U] & 0xF00000U) >> 20U;
01920     pStatus->AllocationUnitSize = (uint8_t)tmp;
01921
01922     /* Byte 11 */
01923     tmp = (sd_status[2U] & 0xFF000000U) >> 24U;
01924     pStatus->EraseSize = (uint16_t)(tmp << 8U);
01925
01926     /* Byte 12 */
01927     tmp = (sd_status[3U] & 0xFFU);
01928     pStatus->EraseSize |= (uint16_t)tmp;
01929
01930     /* Byte 13 */
01931     tmp = (sd_status[3U] & 0xFC00U) >> 10U;
01932     pStatus->EraseTimeout = (uint8_t)tmp;
01933
01934     /* Byte 13 */
01935     tmp = (sd_status[3U] & 0x0300U) >> 8U;
01936     pStatus->EraseOffset = (uint8_t)tmp;
01937   }
01938
01939   return HAL_OK;
01940 }
01941
01942 /**
01943   * @brief  Gets the SD card info.
01944   * @param  hsd: Pointer to SD handle
01945   * @param  pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
01946   *         will contain the SD card status information
01947   * @retval HAL status
01948   */
01949 HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
01950 {
01951   pCardInfo->CardType     = (uint32_t)(hsd->SdCard.CardType);
01952   pCardInfo->CardVersion  = (uint32_t)(hsd->SdCard.CardVersion);
01953   pCardInfo->Class        = (uint32_t)(hsd->SdCard.Class);
01954   pCardInfo->RelCardAdd   = (uint32_t)(hsd->SdCard.RelCardAdd);
01955   pCardInfo->BlockNbr     = (uint32_t)(hsd->SdCard.BlockNbr);
01956   pCardInfo->BlockSize    = (uint32_t)(hsd->SdCard.BlockSize);
01957   pCardInfo->LogBlockNbr  = (uint32_t)(hsd->SdCard.LogBlockNbr);
01958   pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
01959
01960   return HAL_OK;
01961 }
01962
01963 /**
01964   * @brief  Enables wide bus operation for the requested card if supported by
01965   *         card.
01966   * @param  hsd: Pointer to SD handle
01967   * @param  WideMode: Specifies the SD card wide bus mode
01968   *          This parameter can be one of the following values:
01969   *            @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
01970   *            @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
01971   *            @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
01972   * @retval HAL status
01973   */
01974 HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
01975 {
01976   SDIO_InitTypeDef Init;
01977   uint32_t errorstate = HAL_SD_ERROR_NONE;
01978
01979   /* Check the parameters */
01980   assert_param(IS_SDIO_BUS_WIDE(WideMode));
01981
01982   /* Chnage Satte */
01983   hsd->State = HAL_SD_STATE_BUSY;
01984
01985   if(hsd->SdCard.CardType != CARD_SECURED)
01986   {
01987     if(WideMode == SDIO_BUS_WIDE_8B)
01988     {
01989       hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
01990     }
01991     else if(WideMode == SDIO_BUS_WIDE_4B)
01992     {
01993       errorstate = SD_WideBus_Enable(hsd);
01994
01995       hsd->ErrorCode |= errorstate;
01996     }
01997     else if(WideMode == SDIO_BUS_WIDE_1B)
01998     {
01999       errorstate = SD_WideBus_Disable(hsd);
02000
02001       hsd->ErrorCode |= errorstate;
02002     }
02003     else
02004     {
02005       /* WideMode is not a valid argument*/
02006       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
02007     }
02008   }
02009   else
02010   {
02011     /* MMC Card does not support this feature */
02012     hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02013   }
02014
02015   if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
02016   {
02017     /* Clear all the static flags */
02018     __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02019     hsd->State = HAL_SD_STATE_READY;
02020     return HAL_ERROR;
02021   }
02022   else
02023   {
02024     /* Configure the SDIO peripheral */
02025     Init.ClockEdge           = hsd->Init.ClockEdge;
02026     Init.ClockBypass         = hsd->Init.ClockBypass;
02027     Init.ClockPowerSave      = hsd->Init.ClockPowerSave;
02028     Init.BusWide             = WideMode;
02029     Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
02030     Init.ClockDiv            = hsd->Init.ClockDiv;
02031     SDIO_Init(hsd->Instance, Init);
02032   }
02033
02034   /* Change State */
02035   hsd->State = HAL_SD_STATE_READY;
02036
02037   return HAL_OK;
02038 }
02039
02040
02041 /**
02042   * @brief  Gets the current sd card data state.
02043   * @param  hsd: pointer to SD handle
02044   * @retval Card state
02045   */
02046 HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
02047 {
02048   HAL_SD_CardStateTypeDef cardstate =  HAL_SD_CARD_TRANSFER;
02049   uint32_t errorstate = HAL_SD_ERROR_NONE;
02050   uint32_t resp1 = 0;
02051
02052   errorstate = SD_SendStatus(hsd, &resp1);
02053   if(errorstate != HAL_OK)
02054   {
02055     hsd->ErrorCode |= errorstate;
02056   }
02057
02058   cardstate = (HAL_SD_CardStateTypeDef)((resp1 >> 9U) & 0x0FU);
02059
02060   return cardstate;
02061 }
02062
02063 /**
02064   * @brief  Abort the current transfer and disable the SD.
02065   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
02066   *                the configuration information for SD module.
02067   * @retval HAL status
02068   */
02069 HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
02070 {
02071   HAL_SD_CardStateTypeDef CardState;
02072
02073   /* DIsable All interrupts */
02074   __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
02075                            SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
02076
02077   /* Clear All flags */
02078   __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02079
02080   if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
02081   {
02082     /* Disable the SD DMA request */
02083     hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
02084
02085     /* Abort the SD DMA Tx Stream */
02086     if(hsd->hdmatx != NULL)
02087     {
02088       HAL_DMA_Abort(hsd->hdmatx);
02089     }
02090     /* Abort the SD DMA Rx Stream */
02091     if(hsd->hdmarx != NULL)
02092     {
02093       HAL_DMA_Abort(hsd->hdmarx);
02094     }
02095   }
02096
02097   hsd->State = HAL_SD_STATE_READY;
02098   CardState = HAL_SD_GetCardState(hsd);
02099   if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
02100   {
02101     hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
02102   }
02103   if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
02104   {
02105     return HAL_ERROR;
02106   }
02107   return HAL_OK;
02108 }
02109
02110 /**
02111   * @brief  Abort the current transfer and disable the SD (IT mode).
02112   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
02113   *                the configuration information for SD module.
02114   * @retval HAL status
02115   */
02116 HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
02117 {
02118   HAL_SD_CardStateTypeDef CardState;
02119
02120   /* DIsable All interrupts */
02121   __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
02122                            SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
02123
02124   /* Clear All flags */
02125   __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02126
02127   if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
02128   {
02129     /* Disable the SD DMA request */
02130     hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
02131
02132     /* Abort the SD DMA Tx Stream */
02133     if(hsd->hdmatx != NULL)
02134     {
02135       hsd->hdmatx->XferAbortCallback =  SD_DMATxAbort;
02136       if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
02137       {
02138         hsd->hdmatx = NULL;
02139       }
02140     }
02141     /* Abort the SD DMA Rx Stream */
02142     if(hsd->hdmarx != NULL)
02143     {
02144       hsd->hdmarx->XferAbortCallback =  SD_DMARxAbort;
02145       if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
02146       {
02147         hsd->hdmarx = NULL;
02148       }
02149     }
02150   }
02151
02152   /* No transfer ongoing on both DMA channels*/
02153   if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
02154   {
02155     CardState = HAL_SD_GetCardState(hsd);
02156     hsd->State = HAL_SD_STATE_READY;
02157     if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
02158     {
02159       hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
02160     }
02161     if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
02162     {
02163       return HAL_ERROR;
02164     }
02165     else
02166     {
02167       HAL_SD_AbortCallback(hsd);
02168     }
02169   }
02170
02171   return HAL_OK;
02172 }
02173
02174 /**
02175   * @}
02176   */
02177
02178 /**
02179   * @}
02180   */
02181
02182 /* Private function ----------------------------------------------------------*/
02183 /** @addtogroup SD_Private_Functions
02184   * @{
02185   */
02186
02187 /**
02188   * @brief  DMA SD transmit process complete callback
02189   * @param  hdma: DMA handle
02190   * @retval None
02191   */
02192 static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02193 {
02194   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
02195
02196   /* Enable DATAEND Interrupt */
02197   __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
02198 }
02199
02200 /**
02201   * @brief  DMA SD receive process complete callback
02202   * @param  hdma: DMA handle
02203   * @retval None
02204   */
02205 static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02206 {
02207   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
02208   uint32_t errorstate = HAL_SD_ERROR_NONE;
02209
02210   /* Send stop command in multiblock write */
02211   if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
02212   {
02213     errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
02214     if(errorstate != HAL_SD_ERROR_NONE)
02215     {
02216       hsd->ErrorCode |= errorstate;
02217       HAL_SD_ErrorCallback(hsd);
02218     }
02219   }
02220
02221   /* Disable the DMA transfer for transmit request by setting the DMAEN bit
02222   in the SD DCTRL register */
02223   hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
02224
02225   /* Clear all the static flags */
02226   __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02227
02228   hsd->State = HAL_SD_STATE_READY;
02229
02230   HAL_SD_RxCpltCallback(hsd);
02231 }
02232
02233 /**
02234   * @brief  DMA SD communication error callback
02235   * @param  hdma: DMA handle
02236   * @retval None
02237   */
02238 static void SD_DMAError(DMA_HandleTypeDef *hdma)
02239 {
02240   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
02241   HAL_SD_CardStateTypeDef CardState;
02242
02243   if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
02244   {
02245     /* Clear All flags */
02246     __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02247
02248     /* Disable All interrupts */
02249     __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
02250       SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
02251
02252     hsd->ErrorCode |= HAL_SD_ERROR_DMA;
02253     CardState = HAL_SD_GetCardState(hsd);
02254     if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
02255     {
02256       hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
02257     }
02258
02259     hsd->State= HAL_SD_STATE_READY;
02260   }
02261
02262   HAL_SD_ErrorCallback(hsd);
02263 }
02264
02265 /**
02266   * @brief  DMA SD Tx Abort callback
02267   * @param  hdma: DMA handle
02268   * @retval None
02269   */
02270 static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
02271 {
02272   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
02273   HAL_SD_CardStateTypeDef CardState;
02274
02275   if(hsd->hdmatx != NULL)
02276   {
02277     hsd->hdmatx = NULL;
02278   }
02279
02280   /* All DMA channels are aborted */
02281   if(hsd->hdmarx == NULL)
02282   {
02283     CardState = HAL_SD_GetCardState(hsd);
02284     hsd->ErrorCode = HAL_SD_ERROR_NONE;
02285     hsd->State = HAL_SD_STATE_READY;
02286     if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
02287     {
02288       hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
02289
02290       if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
02291       {
02292         HAL_SD_AbortCallback(hsd);
02293       }
02294       else
02295       {
02296         HAL_SD_ErrorCallback(hsd);
02297       }
02298     }
02299   }
02300 }
02301
02302 /**
02303   * @brief  DMA SD Rx Abort callback
02304   * @param  hdma: DMA handle
02305   * @retval None
02306   */
02307 static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
02308 {
02309   SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
02310   HAL_SD_CardStateTypeDef CardState;
02311
02312   if(hsd->hdmarx != NULL)
02313   {
02314     hsd->hdmarx = NULL;
02315   }
02316
02317   /* All DMA channels are aborted */
02318   if(hsd->hdmatx == NULL)
02319   {
02320     CardState = HAL_SD_GetCardState(hsd);
02321     hsd->ErrorCode = HAL_SD_ERROR_NONE;
02322     hsd->State = HAL_SD_STATE_READY;
02323     if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
02324     {
02325       hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
02326
02327       if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
02328       {
02329         HAL_SD_AbortCallback(hsd);
02330       }
02331       else
02332       {
02333         HAL_SD_ErrorCallback(hsd);
02334       }
02335     }
02336   }
02337 }
02338
02339
02340 /**
02341   * @brief  Initializes the sd card.
02342   * @param  hsd: Pointer to SD handle
02343   * @retval SD Card error state
02344   */
02345 static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
02346 {
02347   HAL_SD_CardCSDTypeDef CSD;
02348   uint32_t errorstate = HAL_SD_ERROR_NONE;
02349   uint16_t sd_rca = 1U;
02350
02351   /* Check the power State */
02352   if(SDIO_GetPowerState(hsd->Instance) == 0U)
02353   {
02354     /* Power off */
02355     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
02356   }
02357
02358   if(hsd->SdCard.CardType != CARD_SECURED)
02359   {
02360     /* Send CMD2 ALL_SEND_CID */
02361     errorstate = SDMMC_CmdSendCID(hsd->Instance);
02362     if(errorstate != HAL_SD_ERROR_NONE)
02363     {
02364       return errorstate;
02365     }
02366     else
02367     {
02368       /* Get Card identification number data */
02369       hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
02370       hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
02371       hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
02372       hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
02373     }
02374   }
02375
02376   if(hsd->SdCard.CardType != CARD_SECURED)
02377   {
02378     /* Send CMD3 SET_REL_ADDR with argument 0 */
02379     /* SD Card publishes its RCA. */
02380     errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
02381     if(errorstate != HAL_SD_ERROR_NONE)
02382     {
02383       return errorstate;
02384     }
02385   }
02386   if(hsd->SdCard.CardType != CARD_SECURED)
02387   {
02388     /* Get the SD card RCA */
02389     hsd->SdCard.RelCardAdd = sd_rca;
02390
02391     /* Send CMD9 SEND_CSD with argument as card's RCA */
02392     errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
02393     if(errorstate != HAL_SD_ERROR_NONE)
02394     {
02395       return errorstate;
02396     }
02397     else
02398     {
02399       /* Get Card Specific Data */
02400       hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
02401       hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
02402       hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
02403       hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
02404     }
02405   }
02406
02407   /* Get the Card Class */
02408   hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);
02409
02410   /* Get CSD parameters */
02411   HAL_SD_GetCardCSD(hsd, &CSD);
02412
02413   /* Select the Card */
02414   errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
02415   if(errorstate != HAL_SD_ERROR_NONE)
02416   {
02417     return errorstate;
02418   }
02419
02420   /* Configure SDIO peripheral interface */
02421   SDIO_Init(hsd->Instance, hsd->Init);
02422
02423   /* All cards are initialized */
02424   return HAL_SD_ERROR_NONE;
02425 }
02426
02427 /**
02428   * @brief  Enquires cards about their operating voltage and configures clock
02429   *         controls and stores SD information that will be needed in future
02430   *         in the SD handle.
02431   * @param  hsd: Pointer to SD handle
02432   * @retval error state
02433   */
02434 static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
02435 {
02436   __IO uint32_t count = 0U;
02437   uint32_t response = 0U, validvoltage = 0U;
02438   uint32_t errorstate = HAL_SD_ERROR_NONE;
02439
02440   /* CMD0: GO_IDLE_STATE */
02441   errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
02442   if(errorstate != HAL_SD_ERROR_NONE)
02443   {
02444     return errorstate;
02445   }
02446
02447   /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
02448   errorstate = SDMMC_CmdOperCond(hsd->Instance);
02449   if(errorstate != HAL_SD_ERROR_NONE)
02450   {
02451     hsd->SdCard.CardVersion = CARD_V1_X;
02452
02453     /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
02454     while(validvoltage == 0U)
02455     {
02456       if(count++ == SDMMC_MAX_VOLT_TRIAL)
02457       {
02458         return HAL_SD_ERROR_INVALID_VOLTRANGE;
02459       }
02460
02461       /* SEND CMD55 APP_CMD with RCA as 0 */
02462       errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U);
02463       if(errorstate != HAL_SD_ERROR_NONE)
02464       {
02465         return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02466       }
02467
02468       /* Send CMD41 */
02469       errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY);
02470       if(errorstate != HAL_SD_ERROR_NONE)
02471       {
02472         return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
02473       }
02474
02475       /* Get command response */
02476       response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
02477
02478       /* Get operating voltage*/
02479       validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
02480     }
02481     /* Card type is SDSC */
02482     hsd->SdCard.CardType = CARD_SDSC;
02483   }
02484   else
02485   {
02486     hsd->SdCard.CardVersion = CARD_V2_X;
02487
02488     /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
02489     while(validvoltage == 0U)
02490     {
02491       if(count++ == SDMMC_MAX_VOLT_TRIAL)
02492       {
02493         return HAL_SD_ERROR_INVALID_VOLTRANGE;
02494       }
02495
02496       /* SEND CMD55 APP_CMD with RCA as 0 */
02497       errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U);
02498       if(errorstate != HAL_SD_ERROR_NONE)
02499       {
02500         return errorstate;
02501       }
02502
02503       /* Send CMD41 */
02504       errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY);
02505       if(errorstate != HAL_SD_ERROR_NONE)
02506       {
02507         return errorstate;
02508       }
02509
02510       /* Get command response */
02511       response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
02512
02513       /* Get operating voltage*/
02514       validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
02515     }
02516
02517     if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
02518     {
02519       hsd->SdCard.CardType = CARD_SDHC_SDXC;
02520     }
02521     else
02522     {
02523       hsd->SdCard.CardType = CARD_SDSC;
02524     }
02525   }
02526
02527   return HAL_SD_ERROR_NONE;
02528 }
02529
02530 /**
02531   * @brief  Turns the SDIO output signals off.
02532   * @param  hsd: Pointer to SD handle
02533   * @retval HAL status
02534   */
02535 static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)
02536 {
02537   /* Set Power State to OFF */
02538   SDIO_PowerState_OFF(hsd->Instance);
02539
02540   return HAL_OK;
02541 }
02542
02543 /**
02544   * @brief  Send Status info command.
02545   * @param  hsd: pointer to SD handle
02546   * @param  pSDstatus: Pointer to the buffer that will contain the SD card status
02547   *         SD Status register)
02548   * @retval error state
02549   */
02550 static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
02551 {
02552   SDIO_DataInitTypeDef config;
02553   uint32_t errorstate = HAL_SD_ERROR_NONE;
02554   uint32_t tickstart = HAL_GetTick();
02555   uint32_t count = 0U;
02556
02557   /* Check SD response */
02558   if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
02559   {
02560     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
02561   }
02562
02563   /* Set block size for card if it is not equal to current block size for card */
02564   errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
02565   if(errorstate != HAL_SD_ERROR_NONE)
02566   {
02567     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
02568     return errorstate;
02569   }
02570
02571   /* Send CMD55 */
02572   errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
02573   if(errorstate != HAL_SD_ERROR_NONE)
02574   {
02575     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
02576     return errorstate;
02577   }
02578
02579   /* Configure the SD DPSM (Data Path State Machine) */
02580   config.DataTimeOut   = SDMMC_DATATIMEOUT;
02581   config.DataLength    = 64U;
02582   config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
02583   config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
02584   config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
02585   config.DPSM          = SDIO_DPSM_ENABLE;
02586   SDIO_ConfigData(hsd->Instance, &config);
02587
02588   /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
02589   errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
02590   if(errorstate != HAL_SD_ERROR_NONE)
02591   {
02592     hsd->ErrorCode |= HAL_SD_ERROR_NONE;
02593     return errorstate;
02594   }
02595
02596   /* Get status data */
02597   while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
02598   {
02599     if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
02600     {
02601       for(count = 0U; count < 8U; count++)
02602       {
02603         *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
02604       }
02605
02606       pSDstatus += 8U;
02607     }
02608
02609     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
02610     {
02611       return HAL_SD_ERROR_TIMEOUT;
02612     }
02613   }
02614
02615   if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
02616   {
02617     return HAL_SD_ERROR_DATA_TIMEOUT;
02618   }
02619   else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
02620   {
02621     return HAL_SD_ERROR_DATA_CRC_FAIL;
02622   }
02623   else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
02624   {
02625     return HAL_SD_ERROR_RX_OVERRUN;
02626   }
02627
02628   while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
02629   {
02630     *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
02631     pSDstatus++;
02632
02633     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
02634     {
02635       return HAL_SD_ERROR_TIMEOUT;
02636     }
02637   }
02638
02639   /* Clear all the static status flags*/
02640   __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02641
02642   return HAL_SD_ERROR_NONE;
02643 }
02644
02645 /**
02646   * @brief  Returns the current card's status.
02647   * @param  hsd: Pointer to SD handle
02648   * @param  pCardStatus: pointer to the buffer that will contain the SD card
02649   *         status (Card Status register)
02650   * @retval error state
02651   */
02652 static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
02653 {
02654   uint32_t errorstate = HAL_SD_ERROR_NONE;
02655
02656   if(pCardStatus == NULL)
02657   {
02658     return HAL_SD_ERROR_PARAM;
02659   }
02660
02661   /* Send Status command */
02662   errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
02663   if(errorstate != HAL_OK)
02664   {
02665     return errorstate;
02666   }
02667
02668   /* Get SD card status */
02669   *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
02670
02671   return HAL_SD_ERROR_NONE;
02672 }
02673
02674 /**
02675   * @brief  Enables the SDIO wide bus mode.
02676   * @param  hsd: pointer to SD handle
02677   * @retval error state
02678   */
02679 static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
02680 {
02681   uint32_t scr[2U] = {0U, 0U};
02682   uint32_t errorstate = HAL_SD_ERROR_NONE;
02683
02684   if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
02685   {
02686     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
02687   }
02688
02689   /* Get SCR Register */
02690   errorstate = SD_FindSCR(hsd, scr);
02691   if(errorstate != HAL_OK)
02692   {
02693     return errorstate;
02694   }
02695
02696   /* If requested card supports wide bus operation */
02697   if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
02698   {
02699     /* Send CMD55 APP_CMD with argument as card's RCA.*/
02700     errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
02701     if(errorstate != HAL_OK)
02702     {
02703       return errorstate;
02704     }
02705
02706     /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
02707     errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
02708     if(errorstate != HAL_OK)
02709     {
02710       return errorstate;
02711     }
02712
02713     return HAL_SD_ERROR_NONE;
02714   }
02715   else
02716   {
02717     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
02718   }
02719 }
02720
02721 /**
02722   * @brief  Disables the SDIO wide bus mode.
02723   * @param  hsd: Pointer to SD handle
02724   * @retval error state
02725   */
02726 static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
02727 {
02728   uint32_t scr[2U] = {0U, 0U};
02729   uint32_t errorstate = HAL_SD_ERROR_NONE;
02730
02731   if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
02732   {
02733     return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
02734   }
02735
02736   /* Get SCR Register */
02737   errorstate = SD_FindSCR(hsd, scr);
02738   if(errorstate != HAL_OK)
02739   {
02740     return errorstate;
02741   }
02742
02743   /* If requested card supports 1 bit mode operation */
02744   if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
02745   {
02746     /* Send CMD55 APP_CMD with argument as card's RCA */
02747     errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
02748     if(errorstate != HAL_OK)
02749     {
02750       return errorstate;
02751     }
02752
02753     /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
02754     errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
02755     if(errorstate != HAL_OK)
02756     {
02757       return errorstate;
02758     }
02759
02760     return HAL_SD_ERROR_NONE;
02761   }
02762   else
02763   {
02764     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
02765   }
02766 }
02767
02768
02769 /**
02770   * @brief  Finds the SD card SCR register value.
02771   * @param  hsd: Pointer to SD handle
02772   * @param  pSCR: pointer to the buffer that will contain the SCR value
02773   * @retval error state
02774   */
02775 static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
02776 {
02777   SDIO_DataInitTypeDef config;
02778   uint32_t errorstate = HAL_SD_ERROR_NONE;
02779   uint32_t tickstart = HAL_GetTick();
02780   uint32_t index = 0U;
02781   uint32_t tempscr[2U] = {0U, 0U};
02782
02783   /* Set Block Size To 8 Bytes */
02784   errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
02785   if(errorstate != HAL_OK)
02786   {
02787     return errorstate;
02788   }
02789
02790   /* Send CMD55 APP_CMD with argument as card's RCA */
02791   errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
02792   if(errorstate != HAL_OK)
02793   {
02794     return errorstate;
02795   }
02796
02797   config.DataTimeOut   = SDMMC_DATATIMEOUT;
02798   config.DataLength    = 8U;
02799   config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
02800   config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
02801   config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
02802   config.DPSM          = SDIO_DPSM_ENABLE;
02803   SDIO_ConfigData(hsd->Instance, &config);
02804
02805   /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
02806   errorstate = SDMMC_CmdSendSCR(hsd->Instance);
02807   if(errorstate != HAL_OK)
02808   {
02809     return errorstate;
02810   }
02811
02812   while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
02813   {
02814     if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
02815     {
02816       *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
02817       index++;
02818     }
02819
02820     if((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
02821     {
02822       return HAL_SD_ERROR_TIMEOUT;
02823     }
02824   }
02825
02826   if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
02827   {
02828     __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
02829
02830     return HAL_SD_ERROR_DATA_TIMEOUT;
02831   }
02832   else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
02833   {
02834     __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
02835
02836     return HAL_SD_ERROR_DATA_CRC_FAIL;
02837   }
02838   else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
02839   {
02840     __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
02841
02842     return HAL_SD_ERROR_RX_OVERRUN;
02843   }
02844   else
02845   {
02846     /* No error flag set */
02847     /* Clear all the static flags */
02848     __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
02849
02850     *(pSCR + 1U) = ((tempscr[0U] & SDMMC_0TO7BITS) << 24U)  | ((tempscr[0U] & SDMMC_8TO15BITS) << 8U) |\
02851       ((tempscr[0U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0U] & SDMMC_24TO31BITS) >> 24U);
02852
02853     *(pSCR) = ((tempscr[1U] & SDMMC_0TO7BITS) << 24U)  | ((tempscr[1U] & SDMMC_8TO15BITS) << 8U) |\
02854       ((tempscr[1U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1U] & SDMMC_24TO31BITS) >> 24U);
02855   }
02856
02857   return HAL_SD_ERROR_NONE;
02858 }
02859
02860 /**
02861   * @brief  Wrap up reading in non-blocking mode.
02862   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
02863   *              the configuration information.
02864   * @retval HAL status
02865   */
02866 static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd)
02867 {
02868   uint32_t count = 0U;
02869   uint32_t* tmp;
02870
02871   tmp = (uint32_t*)hsd->pRxBuffPtr;
02872
02873   /* Read data from SDIO Rx FIFO */
02874   for(count = 0U; count < 8U; count++)
02875   {
02876     *(tmp + count) = SDIO_ReadFIFO(hsd->Instance);
02877   }
02878
02879   hsd->pRxBuffPtr += 8U;
02880
02881   return HAL_OK;
02882 }
02883
02884 /**
02885   * @brief  Wrap up writing in non-blocking mode.
02886   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
02887   *              the configuration information.
02888   * @retval HAL status
02889   */
02890 static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd)
02891 {
02892   uint32_t count = 0U;
02893   uint32_t* tmp;
02894
02895   tmp = (uint32_t*)hsd->pTxBuffPtr;
02896
02897   /* Write data to SDIO Tx FIFO */
02898   for(count = 0U; count < 8U; count++)
02899   {
02900     SDIO_WriteFIFO(hsd->Instance, (tmp + count));
02901   }
02902
02903   hsd->pTxBuffPtr += 8U;
02904
02905   return HAL_OK;
02906 }
02907
02908 /**
02909   * @}
02910   */
02911
02912 #endif /* STM32F103xE || STM32F103xG */
02913
02914 #endif /* HAL_SD_MODULE_ENABLED */
02915
02916 /**
02917   * @}
02918   */
02919
02920 /**
02921   * @}
02922   */
02923
02924 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_sd.h Source File

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stm32f1xx_hal_sd.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_sd.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of SD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_SD_H
00040 #define __STM32F1xx_HAL_SD_H
00041
00042 #if defined(STM32F103xE) || defined(STM32F103xG)
00043
00044 #ifdef __cplusplus
00045  extern "C" {
00046 #endif
00047
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32f1xx_ll_sdmmc.h"
00050
00051 /** @addtogroup STM32F1xx_HAL_Driver
00052   * @{
00053   */
00054
00055 /** @defgroup SD SD
00056   * @brief SD HAL module driver
00057   * @{
00058   */
00059
00060 /* Exported types ------------------------------------------------------------*/
00061 /** @defgroup SD_Exported_Types SD Exported Types
00062   * @{
00063   */
00064
00065 /** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
00066   * @{
00067   */
00068 typedef enum
00069 {
00070   HAL_SD_STATE_RESET                  = 0x00000000U,  /*!< SD not yet initialized or disabled  */
00071   HAL_SD_STATE_READY                  = 0x00000001U,  /*!< SD initialized and ready for use    */
00072   HAL_SD_STATE_TIMEOUT                = 0x00000002U,  /*!< SD Timeout state                    */
00073   HAL_SD_STATE_BUSY                   = 0x00000003U,  /*!< SD process ongoing                  */
00074   HAL_SD_STATE_PROGRAMMING            = 0x00000004U,  /*!< SD Programming State                */
00075   HAL_SD_STATE_RECEIVING              = 0x00000005U,  /*!< SD Receinving State                 */
00076   HAL_SD_STATE_TRANSFER               = 0x00000006U,  /*!< SD Transfert State                  */
00077   HAL_SD_STATE_ERROR                  = 0x0000000FU   /*!< SD is in error state                */
00078 }HAL_SD_StateTypeDef;
00079 /**
00080   * @}
00081   */
00082
00083 /** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
00084   * @{
00085   */
00086 typedef enum
00087 {
00088   HAL_SD_CARD_READY                  = 0x00000001U,  /*!< Card state is ready                     */
00089   HAL_SD_CARD_IDENTIFICATION         = 0x00000002U,  /*!< Card is in identification state         */
00090   HAL_SD_CARD_STANDBY                = 0x00000003U,  /*!< Card is in standby state                */
00091   HAL_SD_CARD_TRANSFER               = 0x00000004U,  /*!< Card is in transfer state               */
00092   HAL_SD_CARD_SENDING                = 0x00000005U,  /*!< Card is sending an operation            */
00093   HAL_SD_CARD_RECEIVING              = 0x00000006U,  /*!< Card is receiving operation information */
00094   HAL_SD_CARD_PROGRAMMING            = 0x00000007U,  /*!< Card is in programming state            */
00095   HAL_SD_CARD_DISCONNECTED           = 0x00000008U,  /*!< Card is disconnected                    */
00096   HAL_SD_CARD_ERROR                  = 0x000000FFU   /*!< Card response Error                     */
00097 }HAL_SD_CardStateTypeDef;
00098 /**
00099   * @}
00100   */
00101
00102 /** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
00103   * @{
00104   */
00105 #define SD_InitTypeDef      SDIO_InitTypeDef
00106 #define SD_TypeDef          SDIO_TypeDef
00107
00108 /**
00109   * @brief  SD Card Information Structure definition
00110   */
00111 typedef struct
00112 {
00113   uint32_t CardType;                     /*!< Specifies the card Type                         */
00114
00115   uint32_t CardVersion;                  /*!< Specifies the card version                      */
00116
00117   uint32_t Class;                        /*!< Specifies the class of the card class           */
00118
00119   uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
00120
00121   uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
00122
00123   uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */
00124
00125   uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */
00126
00127   uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */
00128
00129 }HAL_SD_CardInfoTypeDef;
00130
00131 /**
00132   * @brief  SD handle Structure definition
00133   */
00134 typedef struct
00135 {
00136   SD_TypeDef                   *Instance;        /*!< SD registers base address           */
00137
00138   SD_InitTypeDef               Init;             /*!< SD required parameters              */
00139
00140   HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
00141
00142   uint32_t                     *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
00143
00144   uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
00145
00146   uint32_t                     *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
00147
00148   uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
00149
00150   __IO uint32_t                Context;          /*!< SD transfer context                 */
00151
00152   __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
00153
00154   __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */
00155
00156   DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters         */
00157
00158   DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters         */
00159
00160   HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
00161
00162   uint32_t                     CSD[4];           /*!< SD card specific data table         */
00163
00164   uint32_t                     CID[4];           /*!< SD card identification number table */
00165
00166 }SD_HandleTypeDef;
00167
00168 /**
00169   * @}
00170   */
00171
00172 /** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
00173   * @{
00174   */
00175 typedef struct
00176 {
00177   __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
00178   __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
00179   __IO uint8_t  Reserved1;            /*!< Reserved                              */
00180   __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
00181   __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
00182   __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
00183   __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
00184   __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
00185   __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
00186   __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
00187   __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
00188   __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
00189   __IO uint8_t  Reserved2;            /*!< Reserved                              */
00190   __IO uint32_t DeviceSize;           /*!< Device Size                           */
00191   __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
00192   __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
00193   __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
00194   __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
00195   __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
00196   __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
00197   __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
00198   __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
00199   __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
00200   __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
00201   __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
00202   __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
00203   __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
00204   __IO uint8_t  Reserved3;            /*!< Reserved                              */
00205   __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
00206   __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
00207   __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
00208   __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
00209   __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
00210   __IO uint8_t  FileFormat;           /*!< File format                           */
00211   __IO uint8_t  ECC;                  /*!< ECC code                              */
00212   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
00213   __IO uint8_t  Reserved4;            /*!< Always 1                              */
00214
00215 }HAL_SD_CardCSDTypeDef;
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
00221   * @{
00222   */
00223 typedef struct
00224 {
00225   __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
00226   __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
00227   __IO uint32_t ProdName1;       /*!< Product Name part1    */
00228   __IO uint8_t  ProdName2;       /*!< Product Name part2    */
00229   __IO uint8_t  ProdRev;         /*!< Product Revision      */
00230   __IO uint32_t ProdSN;          /*!< Product Serial Number */
00231   __IO uint8_t  Reserved1;       /*!< Reserved1             */
00232   __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
00233   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
00234   __IO uint8_t  Reserved2;       /*!< Always 1              */
00235
00236 }HAL_SD_CardCIDTypeDef;
00237 /**
00238   * @}
00239   */
00240
00241 /** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
00242   * @{
00243   */
00244 typedef struct
00245 {
00246   __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */
00247   __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */
00248   __IO uint16_t CardType;               /*!< Carries information about card type                        */
00249   __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */
00250   __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */
00251   __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */
00252   __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */
00253   __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */
00254   __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */
00255   __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */
00256
00257 }HAL_SD_CardStatusTypeDef;
00258 /**
00259   * @}
00260   */
00261
00262 /**
00263   * @}
00264   */
00265
00266 /* Exported constants --------------------------------------------------------*/
00267 /** @defgroup SD_Exported_Constants Exported Constants
00268   * @{
00269   */
00270
00271 #define BLOCKSIZE   512U /*!< Block size is 512 bytes */
00272
00273 /** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
00274   * @{
00275   */
00276 #define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */
00277 #define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */
00278 #define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */
00279 #define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */
00280 #define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */
00281 #define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */
00282 #define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
00283 #define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
00284 #define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the
00285                                                                                        number of transferred bytes does not match the block length   */
00286 #define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
00287 #define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
00288 #define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
00289 #define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock
00290                                                                                        command or if there was an attempt to access a locked card    */
00291 #define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
00292 #define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
00293 #define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
00294 #define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */
00295 #define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */
00296 #define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */
00297 #define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */
00298 #define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */
00299 #define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
00300 #define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
00301 #define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out
00302                                                                                        of erase sequence command was received                        */
00303 #define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
00304 #define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */
00305 #define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */
00306 #define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */
00307 #define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */
00308 #define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */
00309 #define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */
00310 #define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */
00311 #define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */
00312
00313 /**
00314   * @}
00315   */
00316
00317 /** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
00318   * @{
00319   */
00320 #define   SD_CONTEXT_NONE                 0x00000000U  /*!< None                             */
00321 #define   SD_CONTEXT_READ_SINGLE_BLOCK    0x00000001U  /*!< Read single block operation      */
00322 #define   SD_CONTEXT_READ_MULTIPLE_BLOCK  0x00000002U  /*!< Read multiple blocks operation   */
00323 #define   SD_CONTEXT_WRITE_SINGLE_BLOCK   0x00000010U  /*!< Write single block operation     */
00324 #define   SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U  /*!< Write multiple blocks operation  */
00325 #define   SD_CONTEXT_IT                   0x00000008U  /*!< Process in Interrupt mode        */
00326 #define   SD_CONTEXT_DMA                  0x00000080U  /*!< Process in DMA mode              */
00327
00328 /**
00329   * @}
00330   */
00331
00332 /** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
00333   * @{
00334   */
00335 #define CARD_SDSC                  0x00000000U
00336 #define CARD_SDHC_SDXC             0x00000001U
00337 #define CARD_SECURED               0x00000003U
00338
00339 /**
00340   * @}
00341   */
00342
00343 /** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
00344   * @{
00345   */
00346 #define CARD_V1_X                  0x00000000U
00347 #define CARD_V2_X                  0x00000001U
00348 /**
00349   * @}
00350   */
00351
00352 /**
00353   * @}
00354   */
00355
00356 /* Exported macro ------------------------------------------------------------*/
00357 /** @defgroup SD_Exported_macros SD Exported Macros
00358  *  @brief macros to handle interrupts and specific clock configurations
00359  * @{
00360  */
00361
00362 /**
00363   * @brief  Enable the SD device.
00364   * @retval None
00365   */
00366 #define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
00367
00368 /**
00369   * @brief  Disable the SD device.
00370   * @retval None
00371   */
00372 #define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
00373
00374 /**
00375   * @brief  Enable the SDMMC DMA transfer.
00376   * @retval None
00377   */
00378 #define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
00379
00380 /**
00381   * @brief  Disable the SDMMC DMA transfer.
00382   * @retval None
00383   */
00384 #define __HAL_SD_DMA_DISABLE(__HANDLE__)  __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
00385
00386 /**
00387   * @brief  Enable the SD device interrupt.
00388   * @param  __HANDLE__: SD Handle
00389   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
00390   *         This parameter can be one or a combination of the following values:
00391   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00392   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00393   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00394   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00395   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00396   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00397   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00398   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00399   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00400   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00401   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
00402   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
00403   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
00404   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00405   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00406   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
00407   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
00408   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
00409   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
00410   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
00411   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
00412   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00413   * @retval None
00414   */
00415 #define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00416
00417 /**
00418   * @brief  Disable the SD device interrupt.
00419   * @param  __HANDLE__: SD Handle
00420   * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
00421   *          This parameter can be one or a combination of the following values:
00422   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00423   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00424   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00425   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00426   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00427   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00428   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00429   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00430   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00431   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00432   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
00433   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
00434   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
00435   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00436   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00437   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
00438   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
00439   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
00440   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
00441   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
00442   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
00443   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00444   * @retval None
00445   */
00446 #define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00447
00448 /**
00449   * @brief  Check whether the specified SD flag is set or not.
00450   * @param  __HANDLE__: SD Handle
00451   * @param  __FLAG__: specifies the flag to check.
00452   *          This parameter can be one of the following values:
00453   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
00454   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00455   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
00456   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
00457   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
00458   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
00459   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
00460   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
00461   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00462   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00463   *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
00464   *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
00465   *            @arg SDIO_FLAG_RXACT:    Data receive in progress
00466   *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
00467   *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
00468   *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
00469   *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
00470   *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
00471   *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
00472   *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
00473   *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
00474   *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
00475   * @retval The new state of SD FLAG (SET or RESET).
00476   */
00477 #define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
00478
00479 /**
00480   * @brief  Clear the SD's pending flags.
00481   * @param  __HANDLE__: SD Handle
00482   * @param  __FLAG__: specifies the flag to clear.
00483   *          This parameter can be one or a combination of the following values:
00484   *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
00485   *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
00486   *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
00487   *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
00488   *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
00489   *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
00490   *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
00491   *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
00492   *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
00493   *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
00494   *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
00495   * @retval None
00496   */
00497 #define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
00498
00499 /**
00500   * @brief  Check whether the specified SD interrupt has occurred or not.
00501   * @param  __HANDLE__: SD Handle
00502   * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
00503   *          This parameter can be one of the following values:
00504   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00505   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00506   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00507   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00508   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00509   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00510   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00511   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00512   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
00513   *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
00514   *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
00515   *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
00516   *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
00517   *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
00518   *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
00519   *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
00520   *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
00521   *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
00522   *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
00523   *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
00524   *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
00525   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00526   * @retval The new state of SD IT (SET or RESET).
00527   */
00528 #define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00529
00530 /**
00531   * @brief  Clear the SD's interrupt pending bits.
00532   * @param  __HANDLE__: SD Handle
00533   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00534   *          This parameter can be one or a combination of the following values:
00535   *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
00536   *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
00537   *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
00538   *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
00539   *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
00540   *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
00541   *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
00542   *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
00543   *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
00544   *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
00545   * @retval None
00546   */
00547 #define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
00548
00549 /**
00550   * @}
00551   */
00552
00553 /* Exported functions --------------------------------------------------------*/
00554 /** @defgroup SD_Exported_Functions SD Exported Functions
00555   * @{
00556   */
00557
00558 /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
00559   * @{
00560   */
00561 HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
00562 HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
00563 HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
00564 void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
00565 void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
00566 /**
00567   * @}
00568   */
00569
00570 /** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
00571   * @{
00572   */
00573 /* Blocking mode: Polling */
00574 HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
00575 HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
00576 HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
00577 /* Non-Blocking mode: IT */
00578 HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00579 HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00580 /* Non-Blocking mode: DMA */
00581 HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00582 HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
00583
00584 void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
00585
00586 /* Callback in non blocking modes (DMA) */
00587 void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
00588 void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
00589 void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
00590 void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
00591 /**
00592   * @}
00593   */
00594
00595 /** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
00596   * @{
00597   */
00598 HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
00599 /**
00600   * @}
00601   */
00602
00603 /** @defgroup SD_Exported_Functions_Group4 SD card related functions
00604   * @{
00605   */
00606 HAL_StatusTypeDef       HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
00607 HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
00608 HAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
00609 HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
00610 HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
00611 HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
00612 /**
00613   * @}
00614   */
00615
00616 /** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
00617   * @{
00618   */
00619 HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
00620 uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
00621 /**
00622   * @}
00623   */
00624
00625 /** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
00626   * @{
00627   */
00628 HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
00629 HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
00630 /**
00631   * @}
00632   */
00633
00634 /* Private types -------------------------------------------------------------*/
00635 /** @defgroup SD_Private_Types SD Private Types
00636   * @{
00637   */
00638
00639 /**
00640   * @}
00641   */
00642
00643 /* Private defines -----------------------------------------------------------*/
00644 /** @defgroup SD_Private_Defines SD Private Defines
00645   * @{
00646   */
00647
00648 /**
00649   * @}
00650   */
00651
00652 /* Private variables ---------------------------------------------------------*/
00653 /** @defgroup SD_Private_Variables SD Private Variables
00654   * @{
00655   */
00656
00657 /**
00658   * @}
00659   */
00660
00661 /* Private constants ---------------------------------------------------------*/
00662 /** @defgroup SD_Private_Constants SD Private Constants
00663   * @{
00664   */
00665
00666 /**
00667   * @}
00668   */
00669
00670 /* Private macros ------------------------------------------------------------*/
00671 /** @defgroup SD_Private_Macros SD Private Macros
00672   * @{
00673   */
00674
00675 /**
00676   * @}
00677   */
00678
00679 /* Private functions prototypes ----------------------------------------------*/
00680 /** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
00681   * @{
00682   */
00683
00684 /**
00685   * @}
00686   */
00687
00688 /* Private functions ---------------------------------------------------------*/
00689 /** @defgroup SD_Private_Functions SD Private Functions
00690   * @{
00691   */
00692
00693 /**
00694   * @}
00695   */
00696
00697
00698 /**
00699   * @}
00700   */
00701
00702 /**
00703   * @}
00704   */
00705
00706 /**
00707   * @}
00708   */
00709 #ifdef __cplusplus
00710 }
00711 #endif
00712
00713 #endif /* STM32F103xE || STM32F103xG */
00714
00715 #endif /* __STM32F1xx_HAL_SD_H */
00716
00717 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_smartcard.c Source File

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stm32f1xx_hal_smartcard.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_smartcard.c
00004   * @author  MCD Application Team
00005   * @version V1.5.0
00006   * @date    06-May-2016
00007   * @brief   SMARTCARD HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the SMARTCARD peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     The SMARTCARD HAL driver can be used as follows:
00020
00021     (#) Declare a SMARTCARD_HandleTypeDef handle structure.
00022     (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
00023         (##) Enable the USARTx interface clock.
00024         (##) SMARTCARD pins configuration:
00025             (+++) Enable the clock for the SMARTCARD GPIOs.
00026             (+++) Configure the SMARTCARD pins as alternate function pull-up.
00027         (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
00028              and HAL_SMARTCARD_Receive_IT() APIs):
00029             (+++) Configure the USARTx interrupt priority.
00030             (+++) Enable the NVIC USART IRQ handle.
00031         (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
00032              and HAL_SMARTCARD_Receive_DMA() APIs):
00033             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00034             (+++) Enable the DMAx interface clock.
00035             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00036             (+++) Configure the DMA Tx/Rx channel.
00037             (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00039             (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
00040                   (used for last byte sending completion detection in DMA non circular mode)
00041
00042     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00043         flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
00044
00045     (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
00046         (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00047              by calling the customized HAL_SMARTCARD_MspInit() API.
00048      [..]
00049        (@)The specific SMARTCARD interrupts (Transmission complete interrupt,
00050           RXNE interrupt and Error Interrupts) will be managed using the macros
00051           __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
00052
00053      [..]
00054         Three operation modes are available within this driver:
00055
00056     *** Polling mode IO operation ***
00057     =================================
00058     [..]
00059       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
00060       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
00061     *** Interrupt mode IO operation ***
00062     ===================================
00063     [..]
00064       (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
00065       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
00066           add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
00067       (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
00068       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
00069           add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
00070       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00071           add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
00072
00073     *** DMA mode IO operation ***
00074     ==============================
00075     [..]
00076       (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
00077       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
00078           add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
00079       (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
00080       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
00081           add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
00082       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
00083           add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
00084
00085     *** SMARTCARD HAL driver macros list ***
00086     =============================================
00087     [..]
00088       Below the list of most used macros in SMARTCARD HAL driver.
00089
00090       (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
00091       (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
00092       (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
00093       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
00094       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
00095       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
00096
00097     [..]
00098       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
00099
00100   @endverbatim
00101      [..]
00102        (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
00103            in the data register is transmitted but is changed by the parity bit.
00104            Depending on the frame length defined by the M bit (8-bits or 9-bits),
00105            the possible SMARTCARD frame formats are as listed in the following table:
00106     +-------------------------------------------------------------+
00107     |   M bit |  PCE bit  |            SMARTCARD frame            |
00108     |---------------------|---------------------------------------|
00109     |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00110     +-------------------------------------------------------------+
00111   ******************************************************************************
00112   * @attention
00113   *
00114   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00115   *
00116   * Redistribution and use in source and binary forms, with or without modification,
00117   * are permitted provided that the following conditions are met:
00118   *   1. Redistributions of source code must retain the above copyright notice,
00119   *      this list of conditions and the following disclaimer.
00120   *   2. Redistributions in binary form must reproduce the above copyright notice,
00121   *      this list of conditions and the following disclaimer in the documentation
00122   *      and/or other materials provided with the distribution.
00123   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00124   *      may be used to endorse or promote products derived from this software
00125   *      without specific prior written permission.
00126   *
00127   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00128   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00129   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00130   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00131   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00132   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00133   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00134   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00135   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00136   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00137   *
00138   ******************************************************************************
00139   */
00140
00141 /* Includes ------------------------------------------------------------------*/
00142 #include "stm32f1xx_hal.h"
00143
00144 /** @addtogroup STM32F1xx_HAL_Driver
00145   * @{
00146   */
00147
00148 /** @defgroup SMARTCARD SMARTCARD
00149   * @brief HAL SMARTCARD module driver
00150   * @{
00151   */
00152 #ifdef HAL_SMARTCARD_MODULE_ENABLED
00153 /* Private typedef -----------------------------------------------------------*/
00154 /* Private define ------------------------------------------------------------*/
00155 /** @addtogroup SMARTCARD_Private_Constants
00156   * @{
00157   */
00158 /**
00159   * @}
00160   */
00161 /* Private macro -------------------------------------------------------------*/
00162 /* Private variables ---------------------------------------------------------*/
00163 /* Private function prototypes -----------------------------------------------*/
00164 /** @addtogroup SMARTCARD_Private_Functions
00165   * @{
00166   */
00167 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
00168 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
00169 static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
00170 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
00171 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
00172 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
00173 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00174 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00175 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
00176 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00177 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00178 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00179 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00180 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00181 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00182 /**
00183   * @}
00184   */
00185 /* Exported functions --------------------------------------------------------*/
00186 /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
00187   * @{
00188   */
00189
00190 /** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
00191   *  @brief    Initialization and Configuration functions
00192   *
00193 @verbatim
00194   ==============================================================================
00195             ##### Initialization and Configuration functions #####
00196   ==============================================================================
00197   [..]
00198   This subsection provides a set of functions allowing to initialize the USART
00199   in Smartcard mode.
00200   [..]
00201   The Smartcard interface is designed to support asynchronous protocol Smartcards as
00202   defined in the ISO 7816-3 standard.
00203   [..]
00204   The USART can provide a clock to the smartcard through the SCLK output.
00205   In smartcard mode, SCLK is not associated to the communication but is simply derived
00206   from the internal peripheral input clock through a 5-bit prescaler.
00207   [..]
00208   (+) For the Smartcard mode only these parameters can be configured:
00209       (++) Baud Rate
00210       (++) Word Length => Should be 9 bits (8 bits + parity)
00211       (++) Stop Bit
00212       (++) Parity: => Should be enabled
00213       (++) USART polarity
00214       (++) USART phase
00215       (++) USART LastBit
00216       (++) Receiver/transmitter modes
00217       (++) Prescaler
00218       (++) GuardTime
00219       (++) NACKState: The Smartcard NACK state
00220
00221      (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
00222         (++) Word Length = 9 Bits
00223         (++) 1.5 Stop Bit
00224         (++) Even parity
00225         (++) BaudRate = 12096 baud
00226         (++) Tx and Rx enabled
00227   [..]
00228   Please refer to the ISO 7816-3 specification for more details.
00229
00230   [..]
00231    (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended
00232        to use 1.5 stop bits for both transmitting and receiving to avoid switching
00233        between the two configurations.
00234   [..]
00235     The HAL_SMARTCARD_Init() function follows the USART  SmartCard configuration
00236     procedure (details for the procedure are available in reference manual (RM0329)).
00237
00238 @endverbatim
00239   * @{
00240   */
00241
00242 /**
00243   * @brief Initializes the SmartCard mode according to the specified
00244   *         parameters in the SMARTCARD_InitTypeDef and create the associated handle.
00245   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00246   *                the configuration information for SMARTCARD module.
00247   * @retval HAL status
00248   */
00249 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
00250 {
00251   /* Check the SMARTCARD handle allocation */
00252   if(hsc == NULL)
00253   {
00254     return HAL_ERROR;
00255   }
00256
00257   /* Check the parameters */
00258   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
00259
00260
00261   if(hsc->gState == HAL_SMARTCARD_STATE_RESET)
00262   {
00263     /* Allocate lock resource and initialize it */
00264     hsc->Lock = HAL_UNLOCKED;
00265
00266     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00267     HAL_SMARTCARD_MspInit(hsc);
00268   }
00269
00270   hsc->gState = HAL_SMARTCARD_STATE_BUSY;
00271
00272   /* Set the Prescaler */
00273   MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
00274
00275   /* Set the Guard Time */
00276   MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8U));
00277
00278   /* Set the Smartcard Communication parameters */
00279   SMARTCARD_SetConfig(hsc);
00280
00281   /* In SmartCard mode, the following bits must be kept cleared:
00282   - LINEN bit in the USART_CR2 register
00283   - HDSEL and IREN bits in the USART_CR3 register.*/
00284   CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
00285   CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
00286
00287   /* Enable the SMARTCARD Parity Error Interrupt */
00288   SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
00289
00290   /* Enable the SMARTCARD Framing Error Interrupt */
00291   SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
00292
00293   /* Enable the Peripheral */
00294   __HAL_SMARTCARD_ENABLE(hsc);
00295
00296   /* Configure the Smartcard NACK state */
00297   MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
00298
00299   /* Enable the SC mode by setting the SCEN bit in the CR3 register */
00300   hsc->Instance->CR3 |= (USART_CR3_SCEN);
00301
00302   /* Initialize the SMARTCARD state*/
00303   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00304   hsc->gState= HAL_SMARTCARD_STATE_READY;
00305   hsc->RxState= HAL_SMARTCARD_STATE_READY;
00306
00307   return HAL_OK;
00308 }
00309
00310 /**
00311   * @brief DeInitializes the USART SmartCard peripheral
00312   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00313   *                the configuration information for SMARTCARD module.
00314   * @retval HAL status
00315   */
00316 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
00317 {
00318   /* Check the SMARTCARD handle allocation */
00319   if(hsc == NULL)
00320   {
00321     return HAL_ERROR;
00322   }
00323
00324   /* Check the parameters */
00325   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
00326
00327   hsc->gState = HAL_SMARTCARD_STATE_BUSY;
00328
00329   /* DeInit the low level hardware */
00330   HAL_SMARTCARD_MspDeInit(hsc);
00331
00332   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00333   hsc->gState = HAL_SMARTCARD_STATE_RESET;
00334   hsc->RxState = HAL_SMARTCARD_STATE_RESET;
00335
00336   /* Release Lock */
00337   __HAL_UNLOCK(hsc);
00338
00339   return HAL_OK;
00340 }
00341
00342 /**
00343   * @brief SMARTCARD MSP Init.
00344   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00345   *                the configuration information for SMARTCARD module.
00346   * @retval None
00347   */
00348 __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
00349 {
00350   /* Prevent unused argument(s) compilation warning */
00351   UNUSED(hsc);
00352   /* NOTE: This function should not be modified, when the callback is needed,
00353            the HAL_SMARTCARD_MspInit could be implemented in the user file
00354    */
00355 }
00356
00357 /**
00358   * @brief SMARTCARD MSP DeInit
00359   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00360   *                the configuration information for SMARTCARD module.
00361   * @retval None
00362   */
00363 __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
00364 {
00365   /* Prevent unused argument(s) compilation warning */
00366   UNUSED(hsc);
00367   /* NOTE: This function should not be modified, when the callback is needed,
00368            the HAL_SMARTCARD_MspDeInit could be implemented in the user file
00369    */
00370 }
00371
00372 /**
00373   * @}
00374   */
00375
00376 /** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
00377   *  @brief   SMARTCARD Transmit and Receive functions
00378   *
00379 @verbatim
00380  ===============================================================================
00381                       ##### IO operation functions #####
00382  ===============================================================================
00383  [..]
00384    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
00385
00386  [..]
00387     (#) Smartcard is a single wire half duplex communication protocol.
00388     The Smartcard interface is designed to support asynchronous protocol Smartcards as
00389     defined in the ISO 7816-3 standard.
00390     (#) The USART should be configured as:
00391        (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
00392        (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
00393
00394     (#) There are two modes of transfer:
00395        (++) Blocking mode: The communication is performed in polling mode.
00396             The HAL status of all data processing is returned by the same function
00397             after finishing transfer.
00398        (++) Non Blocking mode: The communication is performed using Interrupts
00399            or DMA, These APIs return the HAL status.
00400            The end of the data processing will be indicated through the
00401            dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
00402            using DMA mode.
00403            The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
00404            will be executed respectively at the end of the Transmit or Receive process
00405            The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
00406
00407     (#) Blocking mode APIs are :
00408         (++) HAL_SMARTCARD_Transmit()
00409         (++) HAL_SMARTCARD_Receive()
00410
00411     (#) Non Blocking mode APIs with Interrupt are :
00412         (++) HAL_SMARTCARD_Transmit_IT()
00413         (++) HAL_SMARTCARD_Receive_IT()
00414         (++) HAL_SMARTCARD_IRQHandler()
00415
00416     (#) Non Blocking mode functions with DMA are :
00417         (++) HAL_SMARTCARD_Transmit_DMA()
00418         (++) HAL_SMARTCARD_Receive_DMA()
00419
00420     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00421         (++) HAL_SMARTCARD_TxCpltCallback()
00422         (++) HAL_SMARTCARD_RxCpltCallback()
00423         (++) HAL_SMARTCARD_ErrorCallback()
00424
00425 @endverbatim
00426   * @{
00427   */
00428
00429 /**
00430   * @brief Send an amount of data in blocking mode
00431   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00432   *                the configuration information for SMARTCARD module.
00433   * @param pData: pointer to data buffer
00434   * @param Size: amount of data to be sent
00435   * @param Timeout: Timeout duration
00436   * @retval HAL status
00437   */
00438 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00439 {
00440   uint16_t* tmp;
00441   uint32_t tickstart = 0U;
00442
00443   if(hsc->gState == HAL_SMARTCARD_STATE_READY)
00444   {
00445     if((pData == NULL) || (Size == 0U))
00446     {
00447       return  HAL_ERROR;
00448     }
00449
00450     /* Process Locked */
00451     __HAL_LOCK(hsc);
00452
00453     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00454     hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00455
00456     /* Init tickstart for timeout managment */
00457     tickstart = HAL_GetTick();
00458
00459     hsc->TxXferSize = Size;
00460     hsc->TxXferCount = Size;
00461     while(hsc->TxXferCount > 0U)
00462     {
00463       hsc->TxXferCount--;
00464       if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00465       {
00466         return HAL_TIMEOUT;
00467       }
00468       tmp = (uint16_t*) pData;
00469       hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
00470       pData +=1U;
00471     }
00472
00473     if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00474     {
00475       return HAL_TIMEOUT;
00476     }
00477
00478         /* At end of Tx process, restore hsc->gState to Ready */
00479     hsc->gState = HAL_SMARTCARD_STATE_READY;
00480
00481     /* Process Unlocked */
00482     __HAL_UNLOCK(hsc);
00483
00484     return HAL_OK;
00485   }
00486   else
00487   {
00488     return HAL_BUSY;
00489   }
00490 }
00491
00492 /**
00493   * @brief Receive an amount of data in blocking mode
00494   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00495   *                the configuration information for SMARTCARD module.
00496   * @param pData: pointer to data buffer
00497   * @param Size: amount of data to be received
00498   * @param Timeout: Timeout duration
00499   * @retval HAL status
00500   */
00501 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00502 {
00503   uint16_t* tmp;
00504   uint32_t tickstart = 0U;
00505
00506   if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
00507   {
00508     if((pData == NULL) || (Size == 0U))
00509     {
00510       return  HAL_ERROR;
00511     }
00512
00513     /* Process Locked */
00514     __HAL_LOCK(hsc);
00515
00516     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00517     hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
00518
00519     /* Init tickstart for timeout managment */
00520     tickstart = HAL_GetTick();
00521
00522     hsc->RxXferSize = Size;
00523     hsc->RxXferCount = Size;
00524
00525     /* Check the remain data to be received */
00526     while(hsc->RxXferCount > 0U)
00527     {
00528       hsc->RxXferCount--;
00529       if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00530       {
00531         return HAL_TIMEOUT;
00532       }
00533       tmp = (uint16_t*) pData;
00534       *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
00535       pData +=1U;
00536     }
00537
00538     /* At end of Rx process, restore hsc->RxState to Ready */
00539     hsc->RxState = HAL_SMARTCARD_STATE_READY;
00540
00541     /* Process Unlocked */
00542     __HAL_UNLOCK(hsc);
00543
00544     return HAL_OK;
00545   }
00546   else
00547   {
00548     return HAL_BUSY;
00549   }
00550 }
00551
00552 /**
00553   * @brief Send an amount of data in non blocking mode
00554   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00555   *                the configuration information for SMARTCARD module.
00556   * @param pData: pointer to data buffer
00557   * @param Size: amount of data to be sent
00558   * @retval HAL status
00559   */
00560 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00561 {
00562   /* Check that a Tx process is not already ongoing */
00563   if(hsc->gState == HAL_SMARTCARD_STATE_READY)
00564   {
00565     if((pData == NULL) || (Size == 0U))
00566     {
00567       return HAL_ERROR;
00568     }
00569     /* Process Locked */
00570     __HAL_LOCK(hsc);
00571
00572     hsc->pTxBuffPtr = pData;
00573     hsc->TxXferSize = Size;
00574     hsc->TxXferCount = Size;
00575
00576     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00577     hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00578
00579     /* Process Unlocked */
00580     __HAL_UNLOCK(hsc);
00581
00582     /* Enable the SMARTCARD Parity Error Interrupt */
00583     SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
00584
00585     /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00586     CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
00587
00588     /* Enable the SMARTCARD Transmit data register empty Interrupt */
00589     SET_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
00590
00591     return HAL_OK;
00592   }
00593   else
00594   {
00595     return HAL_BUSY;
00596   }
00597 }
00598
00599 /**
00600   * @brief Receive an amount of data in non blocking mode
00601   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00602   *                the configuration information for SMARTCARD module.
00603   * @param pData: pointer to data buffer
00604   * @param Size: amount of data to be received
00605   * @retval HAL status
00606   */
00607 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00608 {
00609   /* Check that a Rx process is not already ongoing */
00610   if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
00611   {
00612     if((pData == NULL) || (Size == 0U))
00613     {
00614       return HAL_ERROR;
00615     }
00616
00617     /* Process Locked */
00618     __HAL_LOCK(hsc);
00619
00620     hsc->pRxBuffPtr = pData;
00621     hsc->RxXferSize = Size;
00622     hsc->RxXferCount = Size;
00623
00624     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00625     hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
00626
00627     /* Process Unlocked */
00628     __HAL_UNLOCK(hsc);
00629
00630     /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
00631     SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
00632
00633     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00634     SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
00635
00636     return HAL_OK;
00637   }
00638   else
00639   {
00640     return HAL_BUSY;
00641   }
00642 }
00643
00644 /**
00645   * @brief Send an amount of data in non blocking mode
00646   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00647   *                the configuration information for SMARTCARD module.
00648   * @param pData: pointer to data buffer
00649   * @param Size: amount of data to be sent
00650   * @retval HAL status
00651   */
00652 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00653 {
00654   uint32_t *tmp;
00655
00656   /* Check that a Tx process is not already ongoing */
00657   if(hsc->gState == HAL_SMARTCARD_STATE_READY)
00658   {
00659     if((pData == NULL) || (Size == 0U))
00660     {
00661       return HAL_ERROR;
00662     }
00663
00664     /* Process Locked */
00665     __HAL_LOCK(hsc);
00666
00667     hsc->pTxBuffPtr = pData;
00668     hsc->TxXferSize = Size;
00669     hsc->TxXferCount = Size;
00670
00671     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00672     hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
00673
00674     /* Set the SMARTCARD DMA transfer complete callback */
00675     hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
00676
00677     /* Set the DMA error callback */
00678     hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
00679
00680     /* Set the DMA abort callback */
00681     hsc->hdmatx->XferAbortCallback = NULL;
00682
00683     /* Enable the SMARTCARD transmit DMA Channel */
00684     tmp = (uint32_t*)&pData;
00685     HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
00686
00687     /* Clear the TC flag in the SR register by writing 0 to it */
00688     __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
00689
00690     /* Process Unlocked */
00691     __HAL_UNLOCK(hsc);
00692
00693     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00694     in the SMARTCARD CR3 register */
00695     SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
00696
00697     return HAL_OK;
00698   }
00699   else
00700   {
00701     return HAL_BUSY;
00702   }
00703 }
00704
00705 /**
00706   * @brief Receive an amount of data in non blocking mode
00707   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
00708   *                the configuration information for SMARTCARD module.
00709   * @param pData: pointer to data buffer
00710   * @param Size: amount of data to be received
00711   * @note   When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
00712   * @retval HAL status
00713   */
00714 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
00715 {
00716   uint32_t *tmp;
00717
00718   /* Check that a Rx process is not already ongoing */
00719   if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
00720   {
00721     if((pData == NULL) || (Size == 0U))
00722     {
00723       return HAL_ERROR;
00724     }
00725
00726     /* Process Locked */
00727     __HAL_LOCK(hsc);
00728
00729     hsc->pRxBuffPtr = pData;
00730     hsc->RxXferSize = Size;
00731
00732     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00733     hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
00734
00735     /* Set the SMARTCARD DMA transfer complete callback */
00736     hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
00737
00738     /* Set the DMA error callback */
00739     hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
00740
00741     /* Set the DMA abort callback */
00742     hsc->hdmatx->XferAbortCallback = NULL;
00743
00744     /* Enable the DMA Channel */
00745     tmp = (uint32_t*)&pData;
00746     HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
00747
00748     /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
00749     __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
00750
00751     /* Process Unlocked */
00752     __HAL_UNLOCK(hsc);
00753
00754     /* Enable the SMARTCARD Parity Error Interrupt */
00755     SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
00756
00757     /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
00758     SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
00759
00760     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
00761     in the SMARTCARD CR3 register */
00762     SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
00763
00764     return HAL_OK;
00765   }
00766   else
00767   {
00768     return HAL_BUSY;
00769   }
00770 }
00771
00772 /**
00773   * @brief  Abort ongoing transfers (blocking mode).
00774   * @param  hsc SMARTCARD handle.
00775   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
00776   *         This procedure performs following operations :
00777   *           - Disable PPP Interrupts
00778   *           - Disable the DMA transfer in the peripheral register (if enabled)
00779   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00780   *           - Set handle State to READY
00781   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00782   * @retval HAL status
00783 */
00784 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
00785 {
00786   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
00787   CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
00788   CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
00789
00790   /* Disable the SMARTCARD DMA Tx request if enabled */
00791   if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
00792   {
00793     CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
00794
00795     /* Abort the SMARTCARD DMA Tx channel: use blocking DMA Abort API (no callback) */
00796     if(hsc->hdmatx != NULL)
00797     {
00798       /* Set the SMARTCARD DMA Abort callback to Null.
00799          No call back execution at end of DMA abort procedure */
00800       hsc->hdmatx->XferAbortCallback = NULL;
00801
00802       HAL_DMA_Abort(hsc->hdmatx);
00803     }
00804   }
00805
00806   /* Disable the SMARTCARD DMA Rx request if enabled */
00807   if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
00808   {
00809     CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
00810
00811     /* Abort the SMARTCARD DMA Rx channel: use blocking DMA Abort API (no callback) */
00812     if(hsc->hdmarx != NULL)
00813     {
00814       /* Set the SMARTCARD DMA Abort callback to Null.
00815          No call back execution at end of DMA abort procedure */
00816       hsc->hdmarx->XferAbortCallback = NULL;
00817
00818       HAL_DMA_Abort(hsc->hdmarx);
00819     }
00820   }
00821
00822   /* Reset Tx and Rx transfer counters */
00823   hsc->TxXferCount = 0x00U;
00824   hsc->RxXferCount = 0x00U;
00825
00826   /* Reset ErrorCode */
00827   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
00828
00829   /* Restore hsc->RxState and hsc->gState to Ready */
00830   hsc->RxState = HAL_SMARTCARD_STATE_READY;
00831   hsc->gState = HAL_SMARTCARD_STATE_READY;
00832
00833   return HAL_OK;
00834 }
00835
00836 /**
00837   * @brief  Abort ongoing Transmit transfer (blocking mode).
00838   * @param  hsc SMARTCARD handle.
00839   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
00840   *         This procedure performs following operations :
00841   *           - Disable PPP Interrupts
00842   *           - Disable the DMA transfer in the peripheral register (if enabled)
00843   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00844   *           - Set handle State to READY
00845   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00846   * @retval HAL status
00847 */
00848 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc)
00849 {
00850   /* Disable TXEIE and TCIE interrupts */
00851   CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
00852
00853   /* Disable the SMARTCARD DMA Tx request if enabled */
00854   if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
00855   {
00856     CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
00857
00858     /* Abort the SMARTCARD DMA Tx channel: use blocking DMA Abort API (no callback) */
00859     if(hsc->hdmatx != NULL)
00860     {
00861       /* Set the SMARTCARD DMA Abort callback to Null.
00862          No call back execution at end of DMA abort procedure */
00863       hsc->hdmatx->XferAbortCallback = NULL;
00864
00865       HAL_DMA_Abort(hsc->hdmatx);
00866     }
00867   }
00868
00869   /* Reset Tx transfer counter */
00870   hsc->TxXferCount = 0x00U;
00871
00872   /* Restore hsc->gState to Ready */
00873   hsc->gState = HAL_SMARTCARD_STATE_READY;
00874
00875   return HAL_OK;
00876 }
00877
00878 /**
00879   * @brief  Abort ongoing Receive transfer (blocking mode).
00880   * @param  hsc SMARTCARD handle.
00881   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
00882   *         This procedure performs following operations :
00883   *           - Disable PPP Interrupts
00884   *           - Disable the DMA transfer in the peripheral register (if enabled)
00885   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
00886   *           - Set handle State to READY
00887   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
00888   * @retval HAL status
00889 */
00890 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc)
00891 {
00892   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
00893   CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
00894   CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
00895
00896   /* Disable the SMARTCARD DMA Rx request if enabled */
00897   if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
00898   {
00899     CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
00900
00901     /* Abort the SMARTCARD DMA Rx channel: use blocking DMA Abort API (no callback) */
00902     if(hsc->hdmarx != NULL)
00903     {
00904       /* Set the SMARTCARD DMA Abort callback to Null.
00905          No call back execution at end of DMA abort procedure */
00906       hsc->hdmarx->XferAbortCallback = NULL;
00907
00908       HAL_DMA_Abort(hsc->hdmarx);
00909     }
00910   }
00911
00912   /* Reset Rx transfer counter */
00913   hsc->RxXferCount = 0x00U;
00914
00915   /* Restore hsc->RxState to Ready */
00916   hsc->RxState = HAL_SMARTCARD_STATE_READY;
00917
00918   return HAL_OK;
00919 }
00920
00921 /**
00922   * @brief  Abort ongoing transfers (Interrupt mode).
00923   * @param  hsc SMARTCARD handle.
00924   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
00925   *         This procedure performs following operations :
00926   *           - Disable PPP Interrupts
00927   *           - Disable the DMA transfer in the peripheral register (if enabled)
00928   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
00929   *           - Set handle State to READY
00930   *           - At abort completion, call user abort complete callback
00931   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
00932   *         considered as completed only when user abort complete callback is executed (not when exiting function).
00933   * @retval HAL status
00934 */
00935 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
00936 {
00937   uint32_t AbortCplt = 0x01U;
00938
00939   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
00940   CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
00941   CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
00942
00943   /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
00944      before any call to DMA Abort functions */
00945   /* DMA Tx Handle is valid */
00946   if(hsc->hdmatx != NULL)
00947   {
00948     /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
00949        Otherwise, set it to NULL */
00950     if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
00951     {
00952       hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
00953     }
00954     else
00955     {
00956       hsc->hdmatx->XferAbortCallback = NULL;
00957     }
00958   }
00959   /* DMA Rx Handle is valid */
00960   if(hsc->hdmarx != NULL)
00961   {
00962     /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
00963        Otherwise, set it to NULL */
00964     if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
00965     {
00966       hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
00967     }
00968     else
00969     {
00970       hsc->hdmarx->XferAbortCallback = NULL;
00971     }
00972   }
00973
00974   /* Disable the SMARTCARD DMA Tx request if enabled */
00975   if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
00976   {
00977     /* Disable DMA Tx at SMARTCARD level */
00978     CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
00979
00980     /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
00981     if(hsc->hdmatx != NULL)
00982     {
00983       /* SMARTCARD Tx DMA Abort callback has already been initialised :
00984          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
00985
00986       /* Abort DMA TX */
00987       if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
00988       {
00989         hsc->hdmatx->XferAbortCallback = NULL;
00990       }
00991       else
00992       {
00993         AbortCplt = 0x00U;
00994       }
00995     }
00996   }
00997
00998   /* Disable the SMARTCARD DMA Rx request if enabled */
00999   if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
01000   {
01001     CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
01002
01003     /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
01004     if(hsc->hdmarx != NULL)
01005     {
01006       /* SMARTCARD Rx DMA Abort callback has already been initialised :
01007          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01008
01009       /* Abort DMA RX */
01010       if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
01011       {
01012         hsc->hdmarx->XferAbortCallback = NULL;
01013         AbortCplt = 0x01U;
01014       }
01015       else
01016       {
01017         AbortCplt = 0x00U;
01018       }
01019     }
01020   }
01021
01022   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01023   if(AbortCplt == 0x01U)
01024   {
01025     /* Reset Tx and Rx transfer counters */
01026     hsc->TxXferCount = 0x00U;
01027     hsc->RxXferCount = 0x00U;
01028
01029     /* Reset ErrorCode */
01030     hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01031
01032     /* Restore hsc->gState and hsc->RxState to Ready */
01033     hsc->gState  = HAL_SMARTCARD_STATE_READY;
01034     hsc->RxState = HAL_SMARTCARD_STATE_READY;
01035
01036     /* As no DMA to be aborted, call directly user Abort complete callback */
01037     HAL_SMARTCARD_AbortCpltCallback(hsc);
01038   }
01039   return HAL_OK;
01040 }
01041
01042 /**
01043   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01044   * @param  hsc SMARTCARD handle.
01045   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01046   *         This procedure performs following operations :
01047   *           - Disable PPP Interrupts
01048   *           - Disable the DMA transfer in the peripheral register (if enabled)
01049   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01050   *           - Set handle State to READY
01051   *           - At abort completion, call user abort complete callback
01052   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01053   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01054   * @retval HAL status
01055 */
01056 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
01057 {
01058   /* Disable TXEIE and TCIE interrupts */
01059   CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01060
01061   /* Disable the SMARTCARD DMA Tx request if enabled */
01062   if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
01063   {
01064     CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
01065
01066     /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
01067     if(hsc->hdmatx != NULL)
01068     {
01069       /* Set the SMARTCARD DMA Abort callback :
01070          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01071       hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
01072
01073       /* Abort DMA TX */
01074       if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
01075       {
01076         /* Call Directly hsc->hdmatx->XferAbortCallback function in case of error */
01077         hsc->hdmatx->XferAbortCallback(hsc->hdmatx);
01078       }
01079     }
01080     else
01081     {
01082       /* Reset Tx transfer counter */
01083       hsc->TxXferCount = 0x00U;
01084
01085       /* Restore hsc->gState to Ready */
01086       hsc->gState = HAL_SMARTCARD_STATE_READY;
01087
01088       /* As no DMA to be aborted, call directly user Abort complete callback */
01089       HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
01090     }
01091   }
01092   else
01093   {
01094     /* Reset Tx transfer counter */
01095     hsc->TxXferCount = 0x00U;
01096
01097     /* Restore hsc->gState to Ready */
01098     hsc->gState = HAL_SMARTCARD_STATE_READY;
01099
01100     /* As no DMA to be aborted, call directly user Abort complete callback */
01101     HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
01102   }
01103
01104   return HAL_OK;
01105 }
01106
01107 /**
01108   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01109   * @param  hsc SMARTCARD handle.
01110   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01111   *         This procedure performs following operations :
01112   *           - Disable PPP Interrupts
01113   *           - Disable the DMA transfer in the peripheral register (if enabled)
01114   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01115   *           - Set handle State to READY
01116   *           - At abort completion, call user abort complete callback
01117   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01118   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01119   * @retval HAL status
01120 */
01121 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
01122 {
01123   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01124   CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01125   CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
01126
01127   /* Disable the SMARTCARD DMA Rx request if enabled */
01128   if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
01129   {
01130     CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
01131
01132     /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
01133     if(hsc->hdmarx != NULL)
01134     {
01135       /* Set the SMARTCARD DMA Abort callback :
01136          will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
01137       hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
01138
01139       /* Abort DMA RX */
01140       if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
01141       {
01142         /* Call Directly hsc->hdmarx->XferAbortCallback function in case of error */
01143         hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
01144       }
01145     }
01146     else
01147     {
01148       /* Reset Rx transfer counter */
01149       hsc->RxXferCount = 0x00U;
01150
01151       /* Restore hsc->RxState to Ready */
01152       hsc->RxState = HAL_SMARTCARD_STATE_READY;
01153
01154       /* As no DMA to be aborted, call directly user Abort complete callback */
01155       HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
01156     }
01157   }
01158   else
01159   {
01160     /* Reset Rx transfer counter */
01161     hsc->RxXferCount = 0x00U;
01162
01163     /* Restore hsc->RxState to Ready */
01164     hsc->RxState = HAL_SMARTCARD_STATE_READY;
01165
01166     /* As no DMA to be aborted, call directly user Abort complete callback */
01167     HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
01168   }
01169
01170   return HAL_OK;
01171 }
01172
01173 /**
01174   * @brief This function handles SMARTCARD interrupt request.
01175   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01176   *                the configuration information for SMARTCARD module.
01177   * @retval None
01178   */
01179 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
01180 {
01181   uint32_t isrflags   = READ_REG(hsc->Instance->SR);
01182   uint32_t cr1its     = READ_REG(hsc->Instance->CR1);
01183   uint32_t cr3its     = READ_REG(hsc->Instance->CR3);
01184   uint32_t dmarequest = 0x00U;
01185   uint32_t errorflags = 0x00U;
01186
01187   /* If no error occurs */
01188   errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
01189   if(errorflags == RESET)
01190   {
01191     /* SMARTCARD in mode Receiver -------------------------------------------------*/
01192     if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01193     {
01194       SMARTCARD_Receive_IT(hsc);
01195       return;
01196     }
01197   }
01198
01199   /* If some errors occur */
01200   if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
01201   {
01202     /* SMARTCARD parity error interrupt occurred ---------------------------*/
01203     if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01204     {
01205       hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
01206     }
01207
01208     /* SMARTCARD noise error interrupt occurred ----------------------------*/
01209     if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01210     {
01211       hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
01212     }
01213
01214     /* SMARTCARD frame error interrupt occurred ----------------------------*/
01215     if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01216     {
01217       hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
01218     }
01219
01220     /* SMARTCARD Over-Run interrupt occurred -------------------------------*/
01221     if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01222     {
01223       hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
01224     }
01225
01226     /* Call SMARTCARD Error Call back function if need be ------------------*/
01227     if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
01228     {
01229       /* SMARTCARD in mode Receiver ----------------------------------------*/
01230       if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01231       {
01232         SMARTCARD_Receive_IT(hsc);
01233       }
01234
01235       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01236          consider error as blocking */
01237       dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
01238       if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
01239       {
01240         /* Blocking error : transfer is aborted
01241            Set the SMARTCARD state ready to be able to start again the process,
01242            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01243         SMARTCARD_EndRxTransfer(hsc);
01244
01245         /* Disable the SMARTCARD DMA Rx request if enabled */
01246         if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
01247         {
01248           CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
01249
01250           /* Abort the SMARTCARD DMA Rx channel */
01251           if(hsc->hdmarx != NULL)
01252           {
01253             /* Set the SMARTCARD DMA Abort callback :
01254                will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
01255             hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
01256             if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
01257             {
01258               /* Call Directly XferAbortCallback function in case of error */
01259               hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
01260             }
01261           }
01262           else
01263           {
01264             /* Call user error callback */
01265             HAL_SMARTCARD_ErrorCallback(hsc);
01266           }
01267         }
01268         else
01269         {
01270           /* Call user error callback */
01271           HAL_SMARTCARD_ErrorCallback(hsc);
01272         }
01273       }
01274       else
01275       {
01276         /* Non Blocking error : transfer could go on.
01277            Error is notified to user through user error callback */
01278         HAL_SMARTCARD_ErrorCallback(hsc);
01279         hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01280       }
01281     }
01282     return;
01283   } /* End if some error occurs */
01284
01285   /* SMARTCARD in mode Transmitter -------------------------------------------*/
01286   if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01287   {
01288     SMARTCARD_Transmit_IT(hsc);
01289     return;
01290   }
01291
01292   /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
01293   if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01294   {
01295     SMARTCARD_EndTransmit_IT(hsc);
01296     return;
01297   }
01298 }
01299
01300 /**
01301   * @brief Tx Transfer completed callbacks
01302   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01303   *                the configuration information for SMARTCARD module.
01304   * @retval None
01305   */
01306 __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
01307 {
01308   /* Prevent unused argument(s) compilation warning */
01309   UNUSED(hsc);
01310   /* NOTE : This function Should not be modified, when the callback is needed,
01311             the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
01312    */
01313 }
01314
01315 /**
01316   * @brief Rx Transfer completed callbacks
01317   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01318   *                the configuration information for SMARTCARD module.
01319   * @retval None
01320   */
01321 __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
01322 {
01323   /* Prevent unused argument(s) compilation warning */
01324   UNUSED(hsc);
01325   /* NOTE : This function Should not be modified, when the callback is needed,
01326             the HAL_SMARTCARD_RxCpltCallback could be implemented in the user file
01327    */
01328 }
01329
01330 /**
01331   * @brief SMARTCARD error callbacks
01332   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01333   *                the configuration information for SMARTCARD module.
01334   * @retval None
01335   */
01336 __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
01337 {
01338   /* Prevent unused argument(s) compilation warning */
01339   UNUSED(hsc);
01340   /* NOTE : This function Should not be modified, when the callback is needed,
01341             the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
01342    */
01343 }
01344
01345 /**
01346   * @brief  SMARTCARD Abort Complete callback.
01347   * @param  hsc SMARTCARD handle.
01348   * @retval None
01349   */
01350 __weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
01351 {
01352   /* Prevent unused argument(s) compilation warning */
01353   UNUSED(hsc);
01354
01355   /* NOTE : This function should not be modified, when the callback is needed,
01356             the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
01357    */
01358 }
01359
01360 /**
01361   * @brief  SMARTCARD Abort Transmit Complete callback.
01362   * @param  hsc SMARTCARD handle.
01363   * @retval None
01364   */
01365 __weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
01366 {
01367     /* Prevent unused argument(s) compilation warning */
01368     UNUSED(hsc);
01369
01370     /* NOTE : This function should not be modified, when the callback is needed,
01371               the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
01372      */
01373 }
01374
01375 /**
01376   * @brief  SMARTCARD Abort ReceiveComplete callback.
01377   * @param  hsc SMARTCARD handle.
01378   * @retval None
01379   */
01380 __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
01381 {
01382     /* Prevent unused argument(s) compilation warning */
01383     UNUSED(hsc);
01384
01385     /* NOTE : This function should not be modified, when the callback is needed,
01386               the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
01387      */
01388 }
01389
01390 /**
01391   * @}
01392   */
01393
01394 /** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
01395   *  @brief   SMARTCARD State and Errors functions
01396   *
01397 @verbatim
01398  ===============================================================================
01399                 ##### Peripheral State and Errors functions #####
01400  ===============================================================================
01401     [..]
01402     This subsection provides a set of functions allowing to control the SmartCard.
01403      (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
01404      (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
01405 @endverbatim
01406   * @{
01407   */
01408
01409 /**
01410   * @brief return the SMARTCARD state
01411   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01412   *                the configuration information for SMARTCARD module.
01413   * @retval HAL state
01414   */
01415 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
01416 {
01417   uint32_t temp1= 0x00U, temp2 = 0x00U;
01418   temp1 = hsc->gState;
01419   temp2 = hsc->RxState;
01420
01421   return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
01422 }
01423
01424 /**
01425   * @brief  Return the SMARTCARD error code
01426   * @param  hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains
01427   *              the configuration information for the specified SMARTCARD.
01428   * @retval SMARTCARD Error Code
01429   */
01430 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
01431 {
01432   return hsc->ErrorCode;
01433 }
01434
01435 /**
01436   * @}
01437   */
01438
01439 /**
01440   * @brief DMA SMARTCARD transmit process complete callback
01441   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01442   *                the configuration information for the specified DMA module.
01443   * @retval None
01444   */
01445 static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01446 {
01447   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01448
01449   hsc->TxXferCount = 0U;
01450
01451   /* Disable the DMA transfer for transmit request by setting the DMAT bit
01452      in the USART CR3 register */
01453   CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
01454
01455   /* Enable the SMARTCARD Transmit Complete Interrupt */
01456   SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
01457 }
01458
01459 /**
01460   * @brief DMA SMARTCARD receive process complete callback
01461   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01462   *                the configuration information for the specified DMA module.
01463   * @retval None
01464   */
01465 static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01466 {
01467   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01468
01469   hsc->RxXferCount = 0U;
01470
01471   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01472   CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01473   CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
01474
01475   /* Disable the DMA transfer for the receiver request by setting the DMAR bit
01476   in the USART CR3 register */
01477   CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
01478
01479   /* At end of Rx process, restore hsc->RxState to Ready */
01480   hsc->RxState = HAL_SMARTCARD_STATE_READY;
01481
01482   HAL_SMARTCARD_RxCpltCallback(hsc);
01483 }
01484
01485 /**
01486   * @brief DMA SMARTCARD communication error callback
01487   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01488   *                the configuration information for the specified DMA module.
01489   * @retval None
01490   */
01491 static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
01492 {
01493   uint32_t dmarequest = 0x00U;
01494   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01495   hsc->RxXferCount = 0U;
01496   hsc->TxXferCount = 0U;
01497   hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
01498
01499   /* Stop SMARTCARD DMA Tx request if ongoing */
01500   dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT);
01501   if((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest)
01502   {
01503     SMARTCARD_EndTxTransfer(hsc);
01504   }
01505
01506   /* Stop SMARTCARD DMA Rx request if ongoing */
01507   dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
01508   if((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest)
01509   {
01510     SMARTCARD_EndRxTransfer(hsc);
01511   }
01512
01513   HAL_SMARTCARD_ErrorCallback(hsc);
01514 }
01515
01516 /**
01517   * @brief  This function handles SMARTCARD Communication Timeout.
01518   * @param  hsc: SMARTCARD handle
01519   * @param  Flag: specifies the SMARTCARD flag to check.
01520   * @param  Status: The new Flag status (SET or RESET).
01521   * @param  Timeout: Timeout duration
01522   * @param  Tickstart: tick start value
01523   * @retval HAL status
01524   */
01525 static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01526 {
01527   /* Wait until flag is set */
01528   while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
01529   {
01530     /* Check for the Timeout */
01531     if(Timeout != HAL_MAX_DELAY)
01532     {
01533       if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
01534       {
01535         /* Disable TXE and RXNE interrupts for the interrupt process */
01536         CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
01537         CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
01538
01539         hsc->gState= HAL_SMARTCARD_STATE_READY;
01540         hsc->RxState= HAL_SMARTCARD_STATE_READY;
01541
01542         /* Process Unlocked */
01543         __HAL_UNLOCK(hsc);
01544
01545         return HAL_TIMEOUT;
01546       }
01547     }
01548   }
01549   return HAL_OK;
01550 }
01551
01552 /**
01553   * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
01554   * @param  hsc: SMARTCARD handle.
01555   * @retval None
01556   */
01557 static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
01558 {
01559   /* At end of Tx process, restore hsc->gState to Ready */
01560   hsc->gState = HAL_SMARTCARD_STATE_READY;
01561
01562   /* Disable TXEIE and TCIE interrupts */
01563   CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01564 }
01565
01566
01567 /**
01568   * @brief  End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
01569   * @param  hsc: SMARTCARD handle.
01570   * @retval None
01571   */
01572 static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
01573 {
01574   /* At end of Rx process, restore hsc->RxState to Ready */
01575   hsc->RxState = HAL_SMARTCARD_STATE_READY;
01576
01577   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01578   CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01579   CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
01580 }
01581
01582
01583
01584 /**
01585   * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
01586   *         (To be called at end of DMA Abort procedure following error occurrence).
01587   * @param  hdma DMA handle.
01588   * @retval None
01589   */
01590 static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
01591 {
01592   SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01593   hsc->RxXferCount = 0x00U;
01594   hsc->TxXferCount = 0x00U;
01595
01596   HAL_SMARTCARD_ErrorCallback(hsc);
01597 }
01598
01599 /**
01600   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
01601   *         (To be called at end of DMA Tx Abort procedure following user abort request).
01602   * @note   When this callback is executed, User Abort complete call back is called only if no
01603   *         Abort still ongoing for Rx DMA Handle.
01604   * @param  hdma DMA handle.
01605   * @retval None
01606   */
01607 static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
01608 {
01609   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01610
01611   hsc->hdmatx->XferAbortCallback = NULL;
01612
01613   /* Check if an Abort process is still ongoing */
01614   if(hsc->hdmarx != NULL)
01615   {
01616     if(hsc->hdmarx->XferAbortCallback != NULL)
01617     {
01618       return;
01619     }
01620   }
01621
01622   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
01623   hsc->TxXferCount = 0x00U;
01624   hsc->RxXferCount = 0x00U;
01625
01626   /* Reset ErrorCode */
01627   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01628
01629   /* Restore hsc->gState and hsc->RxState to Ready */
01630   hsc->gState  = HAL_SMARTCARD_STATE_READY;
01631   hsc->RxState = HAL_SMARTCARD_STATE_READY;
01632
01633   /* Call user Abort complete callback */
01634   HAL_SMARTCARD_AbortCpltCallback(hsc);
01635 }
01636
01637 /**
01638   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
01639   *         (To be called at end of DMA Rx Abort procedure following user abort request).
01640   * @note   When this callback is executed, User Abort complete call back is called only if no
01641   *         Abort still ongoing for Tx DMA Handle.
01642   * @param  hdma DMA handle.
01643   * @retval None
01644   */
01645 static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
01646 {
01647   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01648
01649   hsc->hdmarx->XferAbortCallback = NULL;
01650
01651   /* Check if an Abort process is still ongoing */
01652   if(hsc->hdmatx != NULL)
01653   {
01654     if(hsc->hdmatx->XferAbortCallback != NULL)
01655     {
01656       return;
01657     }
01658   }
01659
01660   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
01661   hsc->TxXferCount = 0x00U;
01662   hsc->RxXferCount = 0x00U;
01663
01664   /* Reset ErrorCode */
01665   hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
01666
01667   /* Restore hsc->gState and hsc->RxState to Ready */
01668   hsc->gState  = HAL_SMARTCARD_STATE_READY;
01669   hsc->RxState = HAL_SMARTCARD_STATE_READY;
01670
01671   /* Call user Abort complete callback */
01672   HAL_SMARTCARD_AbortCpltCallback(hsc);
01673 }
01674
01675 /**
01676   * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
01677   *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
01678   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
01679   *         and leads to user Tx Abort Complete callback execution).
01680   * @param  hdma DMA handle.
01681   * @retval None
01682   */
01683 static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
01684 {
01685   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01686
01687   hsc->TxXferCount = 0x00U;
01688
01689   /* Restore hsc->gState to Ready */
01690   hsc->gState = HAL_SMARTCARD_STATE_READY;
01691
01692   /* Call user Abort complete callback */
01693   HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
01694 }
01695
01696 /**
01697   * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
01698   *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
01699   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
01700   *         and leads to user Rx Abort Complete callback execution).
01701   * @param  hdma DMA handle.
01702   * @retval None
01703   */
01704 static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
01705 {
01706   SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01707
01708   hsc->RxXferCount = 0x00U;
01709
01710   /* Restore hsc->RxState to Ready */
01711   hsc->RxState = HAL_SMARTCARD_STATE_READY;
01712
01713   /* Call user Abort complete callback */
01714   HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
01715 }
01716
01717 /**
01718   * @brief Send an amount of data in non blocking mode
01719   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01720   *                the configuration information for SMARTCARD module.
01721   * @retval HAL status
01722   */
01723 static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
01724 {
01725   uint16_t* tmp;
01726
01727   /* Check that a Tx process is ongoing */
01728   if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
01729   {
01730     tmp = (uint16_t*) hsc->pTxBuffPtr;
01731     hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
01732     hsc->pTxBuffPtr += 1U;
01733
01734     if(--hsc->TxXferCount == 0U)
01735     {
01736       /* Disable the SMARTCARD Transmit data register empty Interrupt */
01737       CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
01738
01739       /* Enable the SMARTCARD Transmit Complete Interrupt */
01740       SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
01741     }
01742
01743     return HAL_OK;
01744   }
01745   else
01746   {
01747     return HAL_BUSY;
01748   }
01749 }
01750
01751 /**
01752   * @brief  Wraps up transmission in non blocking mode.
01753   * @param  hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
01754   *                the configuration information for the specified SMARTCARD module.
01755   * @retval HAL status
01756   */
01757 static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
01758 {
01759   /* Disable the SMARTCARD Transmit Complete Interrupt */
01760   CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TCIE);
01761
01762   /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01763   CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
01764
01765   /* Tx process is ended, restore hsmartcard->gState to Ready */
01766   hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
01767
01768   HAL_SMARTCARD_TxCpltCallback(hsmartcard);
01769
01770   return HAL_OK;
01771 }
01772
01773 /**
01774   * @brief Receive an amount of data in non blocking mode
01775   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01776   *                the configuration information for SMARTCARD module.
01777   * @retval HAL status
01778   */
01779 static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
01780 {
01781   uint16_t* tmp;
01782
01783   /* Check that a Rx process is ongoing */
01784   if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
01785   {
01786     tmp = (uint16_t*) hsc->pRxBuffPtr;
01787     *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
01788     hsc->pRxBuffPtr += 1U;
01789
01790     if(--hsc->RxXferCount == 0U)
01791     {
01792       CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
01793
01794       /* Disable the SMARTCARD Parity Error Interrupt */
01795       CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
01796
01797       /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
01798       CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
01799
01800           /* Rx process is completed, restore hsc->RxState to Ready */
01801       hsc->RxState = HAL_SMARTCARD_STATE_READY;
01802
01803       HAL_SMARTCARD_RxCpltCallback(hsc);
01804
01805       return HAL_OK;
01806     }
01807     return HAL_OK;
01808   }
01809   else
01810   {
01811     return HAL_BUSY;
01812   }
01813 }
01814
01815 /**
01816   * @brief Configure the SMARTCARD peripheral
01817   * @param  hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
01818   *                the configuration information for SMARTCARD module.
01819   * @retval None
01820   */
01821 static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
01822 {
01823   uint32_t tmpreg = 0x00U;
01824
01825   /* Check the parameters */
01826   assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
01827   assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
01828   assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
01829   assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
01830   assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));
01831   assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
01832   assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
01833   assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
01834   assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
01835   assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
01836
01837
01838   /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
01839      receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
01840   CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
01841
01842   /*---------------------------- USART CR2 Configuration ---------------------*/
01843   tmpreg = hsc->Instance->CR2;
01844   /* Clear CLKEN, CPOL, CPHA and LBCL bits */
01845   tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL));
01846   /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/
01847   /* Set CPOL bit according to hsc->Init.CLKPolarity value */
01848   /* Set CPHA bit according to hsc->Init.CLKPhase value */
01849   /* Set LBCL bit according to hsc->Init.CLKLastBit value */
01850   /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
01851   tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity |
01852                       hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
01853   /* Write to USART CR2 */
01854   WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
01855
01856   tmpreg = hsc->Instance->CR2;
01857
01858   /* Clear STOP[13:12] bits */
01859   tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
01860
01861   /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
01862   tmpreg |= (uint32_t)(hsc->Init.StopBits);
01863
01864   /* Write to USART CR2 */
01865   WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
01866
01867   /*-------------------------- USART CR1 Configuration -----------------------*/
01868   tmpreg = hsc->Instance->CR1;
01869
01870   /* Clear M, PCE, PS, TE and RE bits */
01871   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
01872                                    USART_CR1_RE));
01873
01874   /* Configure the SMARTCARD Word Length, Parity and mode:
01875      Set the M bits according to hsc->Init.WordLength value
01876      Set PCE and PS bits according to hsc->Init.Parity value
01877      Set TE and RE bits according to hsc->Init.Mode value */
01878   tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode;
01879
01880   /* Write to USART CR1 */
01881   WRITE_REG(hsc->Instance->CR1, (uint32_t)tmpreg);
01882
01883   /*-------------------------- USART CR3 Configuration -----------------------*/
01884   /* Clear CTSE and RTSE bits */
01885   CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
01886
01887   /*-------------------------- USART BRR Configuration -----------------------*/
01888
01889   if(hsc->Instance == USART1)
01890   {
01891     hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
01892   }
01893   else
01894   {
01895     hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
01896   }
01897 }
01898
01899 /**
01900   * @}
01901   */
01902
01903 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
01904 /**
01905   * @}
01906   */
01907
01908 /**
01909   * @}
01910   */
01911
01912 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_smartcard.h Source File

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stm32f1xx_hal_smartcard.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_smartcard.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of SMARTCARD HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_SMARTCARD_H
00040 #define __STM32F1xx_HAL_SMARTCARD_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SMARTCARD
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief SMARTCARD Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the SmartCard communication baud rate.
00068                                            The baud rate is computed using the following formula:
00069                                            - IntegerDivider = ((PCLKx) / (16 * (hsmartcard->Init.BaudRate)))
00070                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
00071
00072   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00073                                            This parameter can be a value of @ref SMARTCARD_Word_Length */
00074
00075   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00076                                            This parameter can be a value of @ref SMARTCARD_Stop_Bits */
00077
00078   uint32_t Parity;                    /*!< Specifies the parity mode.
00079                                            This parameter can be a value of @ref SMARTCARD_Parity
00080                                            @note When parity is enabled, the computed parity is inserted
00081                                                  at the MSB position of the transmitted data (9th bit when
00082                                                  the word length is set to 9 data bits; 8th bit when the
00083                                                  word length is set to 8 data bits).*/
00084
00085   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00086                                            This parameter can be a value of @ref SMARTCARD_Mode */
00087
00088   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00089                                            This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
00090
00091   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00092                                            This parameter can be a value of @ref SMARTCARD_Clock_Phase */
00093
00094   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00095                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00096                                            This parameter can be a value of @ref SMARTCARD_Last_Bit */
00097
00098   uint32_t Prescaler;                 /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
00099                                            to provide the smartcard clock. The value given in the register (5 significant bits)
00100                                            is multiplied by 2 to give the division factor of the source clock frequency.
00101                                            This parameter can be a value of @ref SMARTCARD_Prescaler */
00102
00103   uint32_t GuardTime;                 /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
00104
00105   uint32_t NACKState;                 /*!< Specifies the SmartCard NACK Transmission state
00106                                            This parameter can be a value of @ref SMARTCARD_NACK_State */
00107 }SMARTCARD_InitTypeDef;
00108
00109 /**
00110   * @brief HAL SMARTCARD State structures definition
00111   * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
00112   *        - gState contains SMARTCARD state information related to global Handle management
00113   *          and also information related to Tx operations.
00114   *          gState value coding follow below described bitmap :
00115   *          b7-b6  Error information
00116   *             00 : No Error
00117   *             01 : (Not Used)
00118   *             10 : Timeout
00119   *             11 : Error
00120   *          b5     IP initilisation status
00121   *             0  : Reset (IP not initialized)
00122   *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
00123   *          b4-b3  (not used)
00124   *             xx : Should be set to 00
00125   *          b2     Intrinsic process state
00126   *             0  : Ready
00127   *             1  : Busy (IP busy with some configuration or internal operations)
00128   *          b1     (not used)
00129   *             x  : Should be set to 0
00130   *          b0     Tx state
00131   *             0  : Ready (no Tx operation ongoing)
00132   *             1  : Busy (Tx operation ongoing)
00133   *        - RxState contains information related to Rx operations.
00134   *          RxState value coding follow below described bitmap :
00135   *          b7-b6  (not used)
00136   *             xx : Should be set to 00
00137   *          b5     IP initilisation status
00138   *             0  : Reset (IP not initialized)
00139   *             1  : Init done (IP not initialized)
00140   *          b4-b2  (not used)
00141   *            xxx : Should be set to 000
00142   *          b1     Rx state
00143   *             0  : Ready (no Rx operation ongoing)
00144   *             1  : Busy (Rx operation ongoing)
00145   *          b0     (not used)
00146   *             x  : Should be set to 0.
00147   */
00148 typedef enum
00149 {
00150   HAL_SMARTCARD_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
00151                                                         Value is allowed for gState and RxState */
00152   HAL_SMARTCARD_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
00153                                                         Value is allowed for gState and RxState */
00154   HAL_SMARTCARD_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
00155                                                         Value is allowed for gState only */
00156   HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
00157                                                         Value is allowed for gState only */
00158   HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
00159                                                         Value is allowed for RxState only */
00160   HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
00161                                                         Not to be used for neither gState nor RxState.
00162                                                         Value is result of combination (Or) between gState and RxState values */
00163   HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
00164                                                         Value is allowed for gState only */
00165   HAL_SMARTCARD_STATE_ERROR             = 0xE0U     /*!< Error
00166                                                         Value is allowed for gState only */
00167 }HAL_SMARTCARD_StateTypeDef;
00168
00169 /**
00170   * @brief  SMARTCARD handle Structure definition
00171   */
00172 typedef struct
00173 {
00174   USART_TypeDef                    *Instance;        /*!< USART registers base address */
00175
00176   SMARTCARD_InitTypeDef            Init;             /*!< SmartCard communication parameters */
00177
00178   uint8_t                          *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer */
00179
00180   uint16_t                         TxXferSize;       /*!< SmartCard Tx Transfer size */
00181
00182   __IO uint16_t                    TxXferCount;      /*!< SmartCard Tx Transfer Counter */
00183
00184   uint8_t                          *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer */
00185
00186   uint16_t                         RxXferSize;       /*!< SmartCard Rx Transfer size */
00187
00188   __IO uint16_t                    RxXferCount;      /*!< SmartCard Rx Transfer Counter */
00189
00190   DMA_HandleTypeDef                *hdmatx;          /*!< SmartCard Tx DMA Handle parameters */
00191
00192   DMA_HandleTypeDef                *hdmarx;          /*!< SmartCard Rx DMA Handle parameters */
00193
00194   HAL_LockTypeDef                  Lock;             /*!< Locking object */
00195
00196   __IO HAL_SMARTCARD_StateTypeDef  gState;           /*!< SmartCard state information related to global Handle management
00197                                                         and also related to Tx operations.
00198                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00199
00200   __IO HAL_SMARTCARD_StateTypeDef  RxState;          /*!< SmartCard state information related to Rx operations.
00201                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
00202
00203   __IO uint32_t                    ErrorCode;        /*!< SmartCard Error code */
00204 }SMARTCARD_HandleTypeDef;
00205
00206 /**
00207   * @}
00208   */
00209
00210 /* Exported constants --------------------------------------------------------*/
00211 /** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported constants
00212   * @{
00213   */
00214
00215 /** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
00216   * @{
00217   */
00218 #define HAL_SMARTCARD_ERROR_NONE         0x00000000U   /*!< No error            */
00219 #define HAL_SMARTCARD_ERROR_PE           0x00000001U   /*!< Parity error        */
00220 #define HAL_SMARTCARD_ERROR_NE           0x00000002U   /*!< Noise error         */
00221 #define HAL_SMARTCARD_ERROR_FE           0x00000004U   /*!< Frame error         */
00222 #define HAL_SMARTCARD_ERROR_ORE          0x00000008U   /*!< OverRun error       */
00223 #define HAL_SMARTCARD_ERROR_DMA          0x00000010U   /*!< DMA transfer error  */
00224 /**
00225   * @}
00226   */
00227
00228 /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
00229   * @{
00230   */
00231 #define SMARTCARD_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
00237   * @{
00238   */
00239 #define SMARTCARD_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
00240 #define SMARTCARD_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
00241 /**
00242   * @}
00243   */
00244
00245 /** @defgroup SMARTCARD_Parity SMARTCARD Parity
00246   * @{
00247   */
00248 #define SMARTCARD_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00249 #define SMARTCARD_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup SMARTCARD_Mode SMARTCARD Mode
00255   * @{
00256   */
00257 #define SMARTCARD_MODE_RX                        ((uint32_t)USART_CR1_RE)
00258 #define SMARTCARD_MODE_TX                        ((uint32_t)USART_CR1_TE)
00259 #define SMARTCARD_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup SMARTCARD_Clock_Polarity  SMARTCARD Clock Polarity
00265   * @{
00266   */
00267 #define SMARTCARD_POLARITY_LOW                   0x00000000U
00268 #define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
00269 /**
00270   * @}
00271   */
00272
00273 /** @defgroup SMARTCARD_Clock_Phase  SMARTCARD Clock Phase
00274   * @{
00275   */
00276 #define SMARTCARD_PHASE_1EDGE                    0x00000000U
00277 #define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
00278 /**
00279   * @}
00280   */
00281
00282 /** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit
00283   * @{
00284   */
00285 #define SMARTCARD_LASTBIT_DISABLE                0x00000000U
00286 #define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup SMARTCARD_NACK_State  SMARTCARD NACK State
00292   * @{
00293   */
00294 #define SMARTCARD_NACK_ENABLE                  ((uint32_t)USART_CR3_NACK)
00295 #define SMARTCARD_NACK_DISABLE                 0x00000000U
00296 /**
00297   * @}
00298   */
00299
00300 /** @defgroup SMARTCARD_DMA_Requests  SMARTCARD DMA requests
00301   * @{
00302   */
00303 #define SMARTCARD_DMAREQ_TX                    ((uint32_t)USART_CR3_DMAT)
00304 #define SMARTCARD_DMAREQ_RX                    ((uint32_t)USART_CR3_DMAR)
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup SMARTCARD_Prescaler  SMARTCARD Prescaler
00310   * @{
00311   */
00312 #define SMARTCARD_PRESCALER_SYSCLK_DIV2         0x00000001U          /*!< SYSCLK divided by 2 */
00313 #define SMARTCARD_PRESCALER_SYSCLK_DIV4         0x00000002U          /*!< SYSCLK divided by 4 */
00314 #define SMARTCARD_PRESCALER_SYSCLK_DIV6         0x00000003U          /*!< SYSCLK divided by 6 */
00315 #define SMARTCARD_PRESCALER_SYSCLK_DIV8         0x00000004U          /*!< SYSCLK divided by 8 */
00316 #define SMARTCARD_PRESCALER_SYSCLK_DIV10        0x00000005U          /*!< SYSCLK divided by 10 */
00317 #define SMARTCARD_PRESCALER_SYSCLK_DIV12        0x00000006U          /*!< SYSCLK divided by 12 */
00318 #define SMARTCARD_PRESCALER_SYSCLK_DIV14        0x00000007U          /*!< SYSCLK divided by 14 */
00319 #define SMARTCARD_PRESCALER_SYSCLK_DIV16        0x00000008U          /*!< SYSCLK divided by 16 */
00320 #define SMARTCARD_PRESCALER_SYSCLK_DIV18        0x00000009U          /*!< SYSCLK divided by 18 */
00321 #define SMARTCARD_PRESCALER_SYSCLK_DIV20        0x0000000AU          /*!< SYSCLK divided by 20 */
00322 #define SMARTCARD_PRESCALER_SYSCLK_DIV22        0x0000000BU          /*!< SYSCLK divided by 22 */
00323 #define SMARTCARD_PRESCALER_SYSCLK_DIV24        0x0000000CU          /*!< SYSCLK divided by 24 */
00324 #define SMARTCARD_PRESCALER_SYSCLK_DIV26        0x0000000DU          /*!< SYSCLK divided by 26 */
00325 #define SMARTCARD_PRESCALER_SYSCLK_DIV28        0x0000000EU          /*!< SYSCLK divided by 28 */
00326 #define SMARTCARD_PRESCALER_SYSCLK_DIV30        0x0000000FU          /*!< SYSCLK divided by 30 */
00327 #define SMARTCARD_PRESCALER_SYSCLK_DIV32        0x00000010U          /*!< SYSCLK divided by 32 */
00328 #define SMARTCARD_PRESCALER_SYSCLK_DIV34        0x00000011U          /*!< SYSCLK divided by 34 */
00329 #define SMARTCARD_PRESCALER_SYSCLK_DIV36        0x00000012U          /*!< SYSCLK divided by 36 */
00330 #define SMARTCARD_PRESCALER_SYSCLK_DIV38        0x00000013U          /*!< SYSCLK divided by 38 */
00331 #define SMARTCARD_PRESCALER_SYSCLK_DIV40        0x00000014U          /*!< SYSCLK divided by 40 */
00332 #define SMARTCARD_PRESCALER_SYSCLK_DIV42        0x00000015U          /*!< SYSCLK divided by 42 */
00333 #define SMARTCARD_PRESCALER_SYSCLK_DIV44        0x00000016U          /*!< SYSCLK divided by 44 */
00334 #define SMARTCARD_PRESCALER_SYSCLK_DIV46        0x00000017U          /*!< SYSCLK divided by 46 */
00335 #define SMARTCARD_PRESCALER_SYSCLK_DIV48        0x00000018U          /*!< SYSCLK divided by 48 */
00336 #define SMARTCARD_PRESCALER_SYSCLK_DIV50        0x00000019U          /*!< SYSCLK divided by 50 */
00337 #define SMARTCARD_PRESCALER_SYSCLK_DIV52        0x0000001AU          /*!< SYSCLK divided by 52 */
00338 #define SMARTCARD_PRESCALER_SYSCLK_DIV54        0x0000001BU          /*!< SYSCLK divided by 54 */
00339 #define SMARTCARD_PRESCALER_SYSCLK_DIV56        0x0000001CU          /*!< SYSCLK divided by 56 */
00340 #define SMARTCARD_PRESCALER_SYSCLK_DIV58        0x0000001DU          /*!< SYSCLK divided by 58 */
00341 #define SMARTCARD_PRESCALER_SYSCLK_DIV60        0x0000001EU          /*!< SYSCLK divided by 60 */
00342 #define SMARTCARD_PRESCALER_SYSCLK_DIV62        0x0000001FU          /*!< SYSCLK divided by 62 */
00343 /**
00344   * @}
00345   */
00346
00347 /** @defgroup SmartCard_Flags  SMARTCARD Flags
00348   *        Elements values convention: 0xXXXX
00349   *           - 0xXXXX  : Flag mask in the SR register
00350   * @{
00351   */
00352 #define SMARTCARD_FLAG_TXE                      ((uint32_t)USART_SR_TXE)
00353 #define SMARTCARD_FLAG_TC                       ((uint32_t)USART_SR_TC)
00354 #define SMARTCARD_FLAG_RXNE                     ((uint32_t)USART_SR_RXNE)
00355 #define SMARTCARD_FLAG_IDLE                     ((uint32_t)USART_SR_IDLE)
00356 #define SMARTCARD_FLAG_ORE                      ((uint32_t)USART_SR_ORE)
00357 #define SMARTCARD_FLAG_NE                       ((uint32_t)USART_SR_NE)
00358 #define SMARTCARD_FLAG_FE                       ((uint32_t)USART_SR_FE)
00359 #define SMARTCARD_FLAG_PE                       ((uint32_t)USART_SR_PE)
00360 /**
00361   * @}
00362   */
00363
00364 /** @defgroup SmartCard_Interrupt_definition  SMARTCARD Interrupts Definition
00365   *        Elements values convention: 0xY000XXXX
00366   *           - XXXX  : Interrupt mask in the XX register
00367   *           - Y  : Interrupt source register (2bits)
00368   *                 - 01: CR1 register
00369   *                 - 11: CR3 register
00370   * @{
00371   */
00372 #define SMARTCARD_IT_PE                         ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
00373 #define SMARTCARD_IT_TXE                        ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
00374 #define SMARTCARD_IT_TC                         ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
00375 #define SMARTCARD_IT_RXNE                       ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
00376 #define SMARTCARD_IT_IDLE                       ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
00377 #define SMARTCARD_IT_ERR                        ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
00378 /**
00379   * @}
00380   */
00381
00382 /**
00383   * @}
00384   */
00385
00386 /* Exported macro ------------------------------------------------------------*/
00387 /** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
00388   * @{
00389   */
00390
00391 /** @brief Reset SMARTCARD handle gstate & RxState
00392   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00393   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00394   */
00395 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                        \
00396                                                             (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
00397                                                             (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
00398                                                           } while(0U)
00399
00400 /** @brief  Flush the Smartcard DR register
00401   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00402   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00403   */
00404 #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
00405
00406 /** @brief  Check whether the specified Smartcard flag is set or not.
00407   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00408   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00409   * @param  __FLAG__: specifies the flag to check.
00410   *         This parameter can be one of the following values:
00411   *            @arg SMARTCARD_FLAG_TXE:  Transmit data register empty flag
00412   *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag
00413   *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
00414   *            @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
00415   *            @arg SMARTCARD_FLAG_ORE:  OverRun Error flag
00416   *            @arg SMARTCARD_FLAG_NE:   Noise Error flag
00417   *            @arg SMARTCARD_FLAG_FE:   Framing Error flag
00418   *            @arg SMARTCARD_FLAG_PE:   Parity Error flag
00419   * @retval The new state of __FLAG__ (TRUE or FALSE).
00420   */
00421 #define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00422
00423 /** @brief  Clear the specified Smartcard pending flags.
00424   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00425   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00426   * @param  __FLAG__: specifies the flag to check.
00427   *         This parameter can be any combination of the following values:
00428   *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag.
00429   *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
00430   *
00431   * @note   PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun
00432   *          error) flags are cleared by software sequence: a read operation to
00433   *          USART_SR register followed by a read operation to USART_DR register.
00434   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
00435   * @note   TC flag can be also cleared by software sequence: a read operation to
00436   *          USART_SR register followed by a write operation to USART_DR register.
00437   * @note   TXE flag is cleared only by a write to the USART_DR register.
00438   */
00439 #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00440
00441 /** @brief  Clear the SMARTCARD PE pending flag.
00442   * @param  __HANDLE__: specifies the USART Handle.
00443   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00444   */
00445 #define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)     \
00446   do{                                                \
00447     __IO uint32_t tmpreg = 0x00U;                    \
00448     tmpreg = (__HANDLE__)->Instance->SR;             \
00449     tmpreg = (__HANDLE__)->Instance->DR;             \
00450     UNUSED(tmpreg);                                  \
00451   } while(0U)
00452
00453 /** @brief  Clear the SMARTCARD FE pending flag.
00454   * @param  __HANDLE__: specifies the USART Handle.
00455   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00456   */
00457 #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
00458
00459 /** @brief  Clear the SMARTCARD NE pending flag.
00460   * @param  __HANDLE__: specifies the USART Handle.
00461   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00462   */
00463 #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
00464
00465 /** @brief  Clear the SMARTCARD ORE pending flag.
00466   * @param  __HANDLE__: specifies the USART Handle.
00467   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00468   */
00469 #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
00470
00471 /** @brief  Clear the SMARTCARD IDLE pending flag.
00472   * @param  __HANDLE__: specifies the USART Handle.
00473   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00474   */
00475 #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
00476
00477 /** @brief  Enable the specified SmartCard interrupt.
00478   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00479   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00480   * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
00481   *          This parameter can be one of the following values:
00482   *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
00483   *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
00484   *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
00485   *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
00486   *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
00487   *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overRun error)
00488   */
00489 #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
00490                                                                  ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
00491
00492 /** @brief  Disable the specified SmartCard interrupt.
00493   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00494   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00495   * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
00496   *          This parameter can be one of the following values:
00497   *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
00498   *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
00499   *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
00500   *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
00501   *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
00502   *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overRun error)
00503   */
00504 #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
00505                                                                  ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
00506
00507 /** @brief  Checks whether the specified SmartCard interrupt has occurred or not.
00508   * @param  __HANDLE__: specifies the SmartCard Handle.
00509   * @param  __IT__: specifies the SMARTCARD interrupt source to check.
00510   *          This parameter can be one of the following values:
00511   *            @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
00512   *            @arg SMARTCARD_IT_TC:  Transmission complete interrupt
00513   *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
00514   *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
00515   *            @arg SMARTCARD_IT_ERR: Error interrupt
00516   *            @arg SMARTCARD_IT_PE: Parity Error interrupt
00517   * @retval The new state of __IT__ (TRUE or FALSE).
00518   */
00519 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
00520
00521 /** @brief  Enable the USART associated to the SMARTCARD Handle
00522   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00523   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00524   */
00525 #define __HAL_SMARTCARD_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
00526
00527 /** @brief  Disable the USART associated to the SMARTCARD Handle
00528   * @param  __HANDLE__: specifies the SMARTCARD Handle.
00529   *         SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
00530   */
00531 #define __HAL_SMARTCARD_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00532
00533 /** @brief  Macros to enable the SmartCard DMA request.
00534   * @param  __HANDLE__: specifies the SmartCard Handle.
00535   * @param  __REQUEST__: specifies the SmartCard DMA request.
00536   *          This parameter can be one of the following values:
00537   *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
00538   *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
00539   */
00540 #define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    ((__HANDLE__)->Instance->CR3 |=  (__REQUEST__))
00541
00542 /** @brief  Macros to disable the SmartCard DMA request.
00543   * @param  __HANDLE__: specifies the SmartCard Handle.
00544   * @param  __REQUEST__: specifies the SmartCard DMA request.
00545   *          This parameter can be one of the following values:
00546   *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
00547   *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
00548   */
00549 #define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   ((__HANDLE__)->Instance->CR3 &=  ~(__REQUEST__))
00550
00551 /**
00552   * @}
00553   */
00554 /* Exported functions --------------------------------------------------------*/
00555 /** @addtogroup SMARTCARD_Exported_Functions
00556   * @{
00557   */
00558
00559 /** @addtogroup SMARTCARD_Exported_Functions_Group1
00560   * @{
00561   */
00562 /* Initialization/de-initialization functions  **********************************/
00563 HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
00564 HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
00565 HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
00566 void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
00567 void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
00568 /**
00569   * @}
00570   */
00571
00572 /** @addtogroup SMARTCARD_Exported_Functions_Group2
00573   * @{
00574   */
00575 /* IO operation functions *******************************************************/
00576 HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00577 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00578 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00579 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00580 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00581 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
00582 /* Transfer Abort functions */
00583 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
00584 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
00585 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
00586 HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
00587 HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
00588 HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
00589
00590 void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
00591 void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
00592 void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
00593 void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
00594 void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
00595 void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
00596 void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
00597 /**
00598   * @}
00599   */
00600
00601 /** @addtogroup SMARTCARD_Exported_Functions_Group3
00602   * @{
00603   */
00604 /* Peripheral State functions  **************************************************/
00605 HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
00606 uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
00607 /**
00608   * @}
00609   */
00610
00611 /**
00612   * @}
00613   */
00614 /* Private types -------------------------------------------------------------*/
00615 /* Private variables ---------------------------------------------------------*/
00616 /* Private constants ---------------------------------------------------------*/
00617 /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
00618   * @{
00619   */
00620
00621 /** @brief SMARTCARD interruptions flag mask
00622   *
00623   */
00624 #define SMARTCARD_IT_MASK                     0x0000FFFFU
00625
00626 #define SMARTCARD_CR1_REG_INDEX               1U
00627 #define SMARTCARD_CR3_REG_INDEX               3U
00628 /**
00629   * @}
00630   */
00631
00632 /* Private macros --------------------------------------------------------*/
00633 /** @defgroup SMARTCARD_Private_Macros   SMARTCARD Private Macros
00634   * @{
00635   */
00636 #define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
00637 #define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
00638                                          ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
00639 #define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
00640                                      ((PARITY) == SMARTCARD_PARITY_ODD))
00641 #define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
00642 #define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
00643 #define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
00644 #define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
00645                                        ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
00646 #define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
00647                                        ((NACK) == SMARTCARD_NACK_DISABLE))
00648 #define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
00649
00650 #define SMARTCARD_DIV(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
00651 #define SMARTCARD_DIVMANT(_PCLK_, _BAUD_)        (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
00652 #define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_)        (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
00653 /* SMARTCARD BRR = mantissa + overflow + fraction
00654             = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
00655 #define SMARTCARD_BRR(_PCLK_, _BAUD_)            (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
00656                                                   (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
00657                                                   (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
00658 /**
00659   * @}
00660   */
00661
00662 /* Private functions ---------------------------------------------------------*/
00663 /** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
00664   * @{
00665   */
00666
00667 /**
00668   * @}
00669   */
00670
00671 /**
00672   * @}
00673   */
00674
00675 /**
00676   * @}
00677   */
00678
00679 #ifdef __cplusplus
00680 }
00681 #endif
00682
00683 #endif /* __STM32F1xx_HAL_SMARTCARD_H */
00684
00685 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_spi.c Source File

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stm32f1xx_hal_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_spi.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   SPI HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State functions
00014   *
00015   @verbatim
00016   ==============================================================================
00017                         ##### How to use this driver #####
00018   ==============================================================================
00019     [..]
00020       The SPI HAL driver can be used as follows:
00021
00022       (#) Declare a SPI_HandleTypeDef handle structure, for example:
00023           SPI_HandleTypeDef  hspi;
00024
00025       (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
00026           (##) Enable the SPIx interface clock
00027           (##) SPI pins configuration
00028               (+++) Enable the clock for the SPI GPIOs
00029               (+++) Configure these SPI pins as alternate function push-pull
00030           (##) NVIC configuration if you need to use interrupt process
00031               (+++) Configure the SPIx interrupt priority
00032               (+++) Enable the NVIC SPI IRQ handle
00033           (##) DMA Configuration if you need to use DMA process
00034               (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
00035               (+++) Enable the DMAx clock
00036               (+++) Configure the DMA handle parameters
00037               (+++) Configure the DMA Tx or Rx Channel
00038               (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
00039               (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
00040
00041       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
00042           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
00043
00044       (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
00045           (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00046               by calling the customized HAL_SPI_MspInit() API.
00047      [..]
00048        Circular mode restriction:
00049       (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
00050           (##) Master 2Lines RxOnly
00051           (##) Master 1Line Rx
00052       (#) The CRC feature is not managed when the DMA circular mode is enabled
00053       (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
00054           the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
00055      [..]
00056        Master Receive mode restriction:
00057       (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
00058           bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
00059           does not initiate a new transfer the following procedure has to be respected:
00060           (##) HAL_SPI_DeInit()
00061           (##) HAL_SPI_Init()
00062
00063   @endverbatim
00064
00065     Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
00066     the following tables resume the max SPI frequency reached with data size 8bits/16bits,
00067     according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
00068
00069    DataSize = SPI_DATASIZE_8BIT:
00070    +--------------------------------------------------------------------------------------------------+
00071    |         |                | 2Lines Fullduplex     |     2Lines RxOnly     |        1Line          |
00072    | Process | Tranfert mode  |-----------------------|-----------------------|-----------------------|
00073    |         |                |  Master   |  Slave    |  Master   |  Slave    |  Master   |  Slave    |
00074    |==================================================================================================|
00075    |    T    |     Polling    |  fPCLK/8  | fPCLK/8   |    NA     |    NA     |    NA     |    NA     |
00076    |    X    |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00077    |    /    |     Interrupt  |  fPCLK/32 | fPCLK/32  |    NA     |    NA     |    NA     |    NA     |
00078    |    R    |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00079    |    X    |       DMA      |  fPCLK/2  | fPCLK/4   |    NA     |    NA     |    NA     |    NA     |
00080    |=========|================|===========|===========|===========|===========|===========|===========|
00081    |         |     Polling    |  fPCLK/4  | fPCLK/8   | fPCLK/128 | fPCLK/16  | fPCLK/128 | fPCLK/8   |
00082    |         |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00083    |    R    |     Interrupt  |  fPCLK/32 | fPCLK/16  | fPCLK/128 | fPCLK/16  | fPCLK/128 | fPCLK/16  |
00084    |    X    |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00085    |         |       DMA      |  fPCLK/2  |  fPCLK/2  | fPCLK/128 | fPCLK/16  | fPCLK/128 | fPCLK/2   |
00086    |=========|================|===========|===========|===========|===========|===========|===========|
00087    |         |     Polling    |  fPCLK/4  |  fPCLK/4  |    NA     |    NA     |  fPCLK/4  | fPCLK/64  |
00088    |         |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00089    |    T    |     Interrupt  |  fPCLK/8  | fPCLK/16  |    NA     |    NA     |  fPCLK/8  | fPCLK/128 |
00090    |    X    |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00091    |         |       DMA      |  fPCLK/2  |  fPCLK/4  |    NA     |    NA     |  fPCLK/2  | fPCLK/64  |
00092    +--------------------------------------------------------------------------------------------------+
00093
00094    DataSize = SPI_DATASIZE_16BIT:
00095    +--------------------------------------------------------------------------------------------------+
00096    |         |                | 2Lines Fullduplex     |     2Lines RxOnly     |        1Line          |
00097    | Process | Tranfert mode  |-----------------------|-----------------------|-----------------------|
00098    |         |                |  Master   |  Slave    |  Master   |  Slave    |  Master   |  Slave    |
00099    |==================================================================================================|
00100    |    T    |     Polling    |  fPCLK/2  | fPCLK/4   |    NA     |    NA     |    NA     |    NA     |
00101    |    X    |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00102    |    /    |     Interrupt  |  fPCLK/16 | fPCLK/16  |    NA     |    NA     |    NA     |    NA     |
00103    |    R    |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00104    |    X    |       DMA      |  fPCLK/2  | fPCLK/4   |    NA     |    NA     |    NA     |    NA     |
00105    |=========|================|===========|===========|===========|===========|===========|===========|
00106    |         |     Polling    |  fPCLK/2  |  fPCLK/4  | fPCLK/64  | fPCLK/8   | fPCLK/64  | fPCLK/4   |
00107    |         |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00108    |    R    |     Interrupt  |  fPCLK/16 |  fPCLK/8  | fPCLK/128 | fPCLK/8   | fPCLK/128 | fPCLK/8   |
00109    |    X    |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00110    |         |       DMA      |  fPCLK/2  |  fPCLK/2  | fPCLK/128 | fPCLK/8   | fPCLK/128 | fPCLK/2   |
00111    |=========|================|===========|===========|===========|===========|===========|===========|
00112    |         |     Polling    |  fPCLK/2  |  fPCLK/4  |    NA     |    NA     |  fPCLK/2  | fPCLK/64  |
00113    |         |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00114    |    T    |     Interrupt  |  fPCLK/4  |  fPCLK/8  |    NA     |    NA     |  fPCLK/4  | fPCLK/256 |
00115    |    X    |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
00116    |         |       DMA      |  fPCLK/2  |  fPCLK/4  |    NA     |    NA     |  fPCLK/2  | fPCLK/32  |
00117    +--------------------------------------------------------------------------------------------------+
00118      [..]
00119        (@) The max SPI frequency depend on SPI data size (8bits, 16bits),
00120            SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
00121        (@)
00122             (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
00123             (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
00124             (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
00125   ******************************************************************************
00126   * @attention
00127   *
00128   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00129   *
00130   * Redistribution and use in source and binary forms, with or without modification,
00131   * are permitted provided that the following conditions are met:
00132   *   1. Redistributions of source code must retain the above copyright notice,
00133   *      this list of conditions and the following disclaimer.
00134   *   2. Redistributions in binary form must reproduce the above copyright notice,
00135   *      this list of conditions and the following disclaimer in the documentation
00136   *      and/or other materials provided with the distribution.
00137   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00138   *      may be used to endorse or promote products derived from this software
00139   *      without specific prior written permission.
00140   *
00141   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00142   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00143   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00144   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00145   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00146   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00147   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00148   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00149   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00150   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00151   *
00152   ******************************************************************************
00153   */
00154
00155 /* Includes ------------------------------------------------------------------*/
00156 #include "stm32f1xx_hal.h"
00157
00158 /** @addtogroup STM32F1xx_HAL_Driver
00159   * @{
00160   */
00161 /** @defgroup SPI SPI
00162   * @brief SPI HAL module driver
00163   * @{
00164   */
00165 #ifdef HAL_SPI_MODULE_ENABLED
00166
00167 /* Private typedef -----------------------------------------------------------*/
00168 /* Private defines -----------------------------------------------------------*/
00169 /** @defgroup SPI_Private_Constants SPI Private Constants
00170   * @{
00171   */
00172 #define SPI_DEFAULT_TIMEOUT 100U
00173 /**
00174   * @}
00175   */
00176
00177 /* Private macros ------------------------------------------------------------*/
00178 /* Private variables ---------------------------------------------------------*/
00179 /* Private function prototypes -----------------------------------------------*/
00180 /** @addtogroup SPI_Private_Functions
00181   * @{
00182   */
00183 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00184 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00185 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00186 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
00187 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
00188 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
00189 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
00190 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00191 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00192 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00193 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
00194 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00195 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00196 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00197 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00198 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00199 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
00200 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00201 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
00202 #if (USE_SPI_CRC != 0U)
00203 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00204 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00205 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
00206 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
00207 #endif /* USE_SPI_CRC */
00208 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
00209 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
00210 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
00211 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
00212 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
00213 static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
00214 /**
00215   * @}
00216   */
00217
00218 /* Exported functions --------------------------------------------------------*/
00219 /** @defgroup SPI_Exported_Functions SPI Exported Functions
00220   * @{
00221   */
00222
00223 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
00224  *  @brief    Initialization and Configuration functions
00225  *
00226 @verbatim
00227  ===============================================================================
00228               ##### Initialization and de-initialization functions #####
00229  ===============================================================================
00230     [..]  This subsection provides a set of functions allowing to initialize and
00231           de-initialize the SPIx peripheral:
00232
00233       (+) User must implement HAL_SPI_MspInit() function in which he configures
00234           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00235
00236       (+) Call the function HAL_SPI_Init() to configure the selected device with
00237           the selected configuration:
00238         (++) Mode
00239         (++) Direction
00240         (++) Data Size
00241         (++) Clock Polarity and Phase
00242         (++) NSS Management
00243         (++) BaudRate Prescaler
00244         (++) FirstBit
00245         (++) TIMode
00246         (++) CRC Calculation
00247         (++) CRC Polynomial if CRC enabled
00248
00249       (+) Call the function HAL_SPI_DeInit() to restore the default configuration
00250           of the selected SPIx peripheral.
00251
00252 @endverbatim
00253   * @{
00254   */
00255
00256 /**
00257   * @brief  Initialize the SPI according to the specified parameters
00258   *         in the SPI_InitTypeDef and initialize the associated handle.
00259   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00260   *               the configuration information for SPI module.
00261   * @retval HAL status
00262   */
00263 __weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00264 {
00265   /* Check the SPI handle allocation */
00266   if(hspi == NULL)
00267   {
00268     return HAL_ERROR;
00269   }
00270
00271   /* Check the parameters */
00272   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00273   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00274   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00275   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00276   assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00277   assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00278   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00279   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00280   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00281
00282 #if (USE_SPI_CRC != 0U)
00283   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00284   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00285   {
00286     assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00287   }
00288 #else
00289   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00290 #endif /* USE_SPI_CRC */
00291
00292   if(hspi->State == HAL_SPI_STATE_RESET)
00293   {
00294     /* Allocate lock resource and initialize it */
00295     hspi->Lock = HAL_UNLOCKED;
00296
00297     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00298     HAL_SPI_MspInit(hspi);
00299   }
00300
00301   hspi->State = HAL_SPI_STATE_BUSY;
00302
00303   /* Disable the selected SPI peripheral */
00304   __HAL_SPI_DISABLE(hspi);
00305
00306   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
00307   /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
00308   Communication speed, First bit and CRC calculation state */
00309   WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
00310                                   hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
00311                                   hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation) );
00312
00313   /* Configure : NSS management */
00314   WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
00315
00316 #if (USE_SPI_CRC != 0U)
00317   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
00318   /* Configure : CRC Polynomial */
00319   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00320   {
00321     WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
00322   }
00323 #endif /* USE_SPI_CRC */
00324
00325 #if defined(SPI_I2SCFGR_I2SMOD)
00326   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
00327   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00328 #endif /* SPI_I2SCFGR_I2SMOD */
00329
00330   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00331   hspi->State     = HAL_SPI_STATE_READY;
00332
00333   return HAL_OK;
00334 }
00335
00336 /**
00337   * @brief  De Initialize the SPI peripheral.
00338   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00339   *               the configuration information for SPI module.
00340   * @retval HAL status
00341   */
00342 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
00343 {
00344   /* Check the SPI handle allocation */
00345   if(hspi == NULL)
00346   {
00347     return HAL_ERROR;
00348   }
00349
00350   /* Check SPI Instance parameter */
00351   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00352
00353   hspi->State = HAL_SPI_STATE_BUSY;
00354
00355   /* Disable the SPI Peripheral Clock */
00356   __HAL_SPI_DISABLE(hspi);
00357
00358   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
00359   HAL_SPI_MspDeInit(hspi);
00360
00361   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00362   hspi->State = HAL_SPI_STATE_RESET;
00363
00364   /* Release Lock */
00365   __HAL_UNLOCK(hspi);
00366
00367   return HAL_OK;
00368 }
00369
00370 /**
00371   * @brief  Initialize the SPI MSP.
00372   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00373   *               the configuration information for SPI module.
00374   * @retval None
00375   */
00376 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
00377 {
00378   /* Prevent unused argument(s) compilation warning */
00379   UNUSED(hspi);
00380   /* NOTE : This function should not be modified, when the callback is needed,
00381             the HAL_SPI_MspInit should be implemented in the user file
00382   */
00383 }
00384
00385 /**
00386   * @brief  De-Initialize the SPI MSP.
00387   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00388   *               the configuration information for SPI module.
00389   * @retval None
00390   */
00391 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
00392 {
00393   /* Prevent unused argument(s) compilation warning */
00394   UNUSED(hspi);
00395   /* NOTE : This function should not be modified, when the callback is needed,
00396             the HAL_SPI_MspDeInit should be implemented in the user file
00397   */
00398 }
00399
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
00405  *  @brief   Data transfers functions
00406  *
00407 @verbatim
00408   ==============================================================================
00409                       ##### IO operation functions #####
00410  ===============================================================================
00411  [..]
00412     This subsection provides a set of functions allowing to manage the SPI
00413     data transfers.
00414
00415     [..] The SPI supports master and slave mode :
00416
00417     (#) There are two modes of transfer:
00418        (++) Blocking mode: The communication is performed in polling mode.
00419             The HAL status of all data processing is returned by the same function
00420             after finishing transfer.
00421        (++) No-Blocking mode: The communication is performed using Interrupts
00422             or DMA, These APIs return the HAL status.
00423             The end of the data processing will be indicated through the
00424             dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
00425             using DMA mode.
00426             The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
00427             will be executed respectively at the end of the transmit or Receive process
00428             The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
00429
00430     (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
00431         exist for 1Line (simplex) and 2Lines (full duplex) modes.
00432
00433 @endverbatim
00434   * @{
00435   */
00436
00437 /**
00438   * @brief  Transmit an amount of data in blocking mode.
00439   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00440   *               the configuration information for SPI module.
00441   * @param  pData: pointer to data buffer
00442   * @param  Size: amount of data to be sent
00443   * @param  Timeout: Timeout duration
00444   * @retval HAL status
00445   */
00446 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00447 {
00448   uint32_t tickstart = 0U;
00449   HAL_StatusTypeDef errorcode = HAL_OK;
00450
00451   /* Check Direction parameter */
00452   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
00453
00454   /* Process Locked */
00455   __HAL_LOCK(hspi);
00456
00457   /* Init tickstart for timeout management*/
00458   tickstart = HAL_GetTick();
00459
00460   if(hspi->State != HAL_SPI_STATE_READY)
00461   {
00462     errorcode = HAL_BUSY;
00463     goto error;
00464   }
00465
00466   if((pData == NULL ) || (Size == 0U))
00467   {
00468     errorcode = HAL_ERROR;
00469     goto error;
00470   }
00471
00472   /* Set the transaction information */
00473   hspi->State       = HAL_SPI_STATE_BUSY_TX;
00474   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00475   hspi->pTxBuffPtr  = (uint8_t *)pData;
00476   hspi->TxXferSize  = Size;
00477   hspi->TxXferCount = Size;
00478
00479   /*Init field not used in handle to zero */
00480   hspi->pRxBuffPtr  = (uint8_t *)NULL;
00481   hspi->RxXferSize  = 0U;
00482   hspi->RxXferCount = 0U;
00483   hspi->TxISR       = NULL;
00484   hspi->RxISR       = NULL;
00485
00486   /* Configure communication direction : 1Line */
00487   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
00488   {
00489     SPI_1LINE_TX(hspi);
00490   }
00491
00492 #if (USE_SPI_CRC != 0U)
00493   /* Reset CRC Calculation */
00494   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00495   {
00496     SPI_RESET_CRC(hspi);
00497   }
00498 #endif /* USE_SPI_CRC */
00499
00500   /* Check if the SPI is already enabled */
00501   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00502   {
00503     /* Enable SPI peripheral */
00504     __HAL_SPI_ENABLE(hspi);
00505   }
00506
00507   /* Transmit data in 16 Bit mode */
00508   if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
00509   {
00510     if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
00511     {
00512       hspi->Instance->DR = *((uint16_t *)pData);
00513       pData += sizeof(uint16_t);
00514       hspi->TxXferCount--;
00515     }
00516     /* Transmit data in 16 Bit mode */
00517     while (hspi->TxXferCount > 0U)
00518     {
00519       /* Wait until TXE flag is set to send data */
00520       if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00521       {
00522           hspi->Instance->DR = *((uint16_t *)pData);
00523           pData += sizeof(uint16_t);
00524           hspi->TxXferCount--;
00525       }
00526       else
00527       {
00528         /* Timeout management */
00529         if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00530         {
00531           errorcode = HAL_TIMEOUT;
00532           goto error;
00533         }
00534       }
00535     }
00536   }
00537   /* Transmit data in 8 Bit mode */
00538   else
00539   {
00540     if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
00541     {
00542       *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
00543       pData += sizeof(uint8_t);
00544       hspi->TxXferCount--;
00545     }
00546     while (hspi->TxXferCount > 0U)
00547     {
00548       /* Wait until TXE flag is set to send data */
00549       if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
00550       {
00551         *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
00552         pData += sizeof(uint8_t);
00553         hspi->TxXferCount--;
00554       }
00555       else
00556       {
00557         /* Timeout management */
00558         if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00559         {
00560           errorcode = HAL_TIMEOUT;
00561           goto error;
00562         }
00563       }
00564     }
00565   }
00566
00567   /* Wait until TXE flag */
00568   if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
00569   {
00570     errorcode = HAL_TIMEOUT;
00571     goto error;
00572   }
00573
00574   /* Check Busy flag */
00575   if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
00576   {
00577     errorcode = HAL_ERROR;
00578     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
00579     goto error;
00580   }
00581
00582   /* Clear overrun flag in 2 Lines communication mode because received is not read */
00583   if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
00584   {
00585     __HAL_SPI_CLEAR_OVRFLAG(hspi);
00586   }
00587 #if (USE_SPI_CRC != 0U)
00588   /* Enable CRC Transmission */
00589   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00590   {
00591      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00592   }
00593 #endif /* USE_SPI_CRC */
00594
00595   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00596   {
00597     errorcode = HAL_ERROR;
00598   }
00599
00600 error:
00601   hspi->State = HAL_SPI_STATE_READY;
00602   /* Process Unlocked */
00603   __HAL_UNLOCK(hspi);
00604   return errorcode;
00605 }
00606
00607 /**
00608   * @brief  Receive an amount of data in blocking mode.
00609   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00610   *               the configuration information for SPI module.
00611   * @param  pData: pointer to data buffer
00612   * @param  Size: amount of data to be received
00613   * @param  Timeout: Timeout duration
00614   * @retval HAL status
00615   */
00616 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00617 {
00618 #if (USE_SPI_CRC != 0U)
00619   __IO uint16_t tmpreg = 0U;
00620 #endif /* USE_SPI_CRC */
00621   uint32_t tickstart = 0U;
00622   HAL_StatusTypeDef errorcode = HAL_OK;
00623
00624   if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
00625   {
00626      hspi->State = HAL_SPI_STATE_BUSY_RX;
00627      /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
00628     return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
00629   }
00630
00631   /* Process Locked */
00632   __HAL_LOCK(hspi);
00633
00634   /* Init tickstart for timeout management*/
00635   tickstart = HAL_GetTick();
00636
00637   if(hspi->State != HAL_SPI_STATE_READY)
00638   {
00639     errorcode = HAL_BUSY;
00640     goto error;
00641   }
00642
00643   if((pData == NULL ) || (Size == 0U))
00644   {
00645     errorcode = HAL_ERROR;
00646     goto error;
00647   }
00648
00649   /* Set the transaction information */
00650   hspi->State       = HAL_SPI_STATE_BUSY_RX;
00651   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00652   hspi->pRxBuffPtr  = (uint8_t *)pData;
00653   hspi->RxXferSize  = Size;
00654   hspi->RxXferCount = Size;
00655
00656   /*Init field not used in handle to zero */
00657   hspi->pTxBuffPtr  = (uint8_t *)NULL;
00658   hspi->TxXferSize  = 0U;
00659   hspi->TxXferCount = 0U;
00660   hspi->RxISR       = NULL;
00661   hspi->TxISR       = NULL;
00662
00663 #if (USE_SPI_CRC != 0U)
00664   /* Reset CRC Calculation */
00665   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00666   {
00667     SPI_RESET_CRC(hspi);
00668     /* this is done to handle the CRCNEXT before the latest data */
00669     hspi->RxXferCount--;
00670   }
00671 #endif /* USE_SPI_CRC */
00672
00673   /* Configure communication direction: 1Line */
00674   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
00675   {
00676     SPI_1LINE_RX(hspi);
00677   }
00678
00679   /* Check if the SPI is already enabled */
00680   if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
00681   {
00682     /* Enable SPI peripheral */
00683     __HAL_SPI_ENABLE(hspi);
00684   }
00685
00686     /* Receive data in 8 Bit mode */
00687   if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
00688   {
00689     /* Transfer loop */
00690     while(hspi->RxXferCount > 0U)
00691     {
00692       /* Check the RXNE flag */
00693       if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
00694       {
00695         /* read the received data */
00696         (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR;
00697         pData += sizeof(uint8_t);
00698         hspi->RxXferCount--;
00699       }
00700       else
00701       {
00702         /* Timeout management */
00703         if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00704         {
00705           errorcode = HAL_TIMEOUT;
00706           goto error;
00707         }
00708       }
00709     }
00710   }
00711   else
00712   {
00713     /* Transfer loop */
00714     while(hspi->RxXferCount > 0U)
00715     {
00716       /* Check the RXNE flag */
00717       if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
00718       {
00719         *((uint16_t*)pData) = hspi->Instance->DR;
00720         pData += sizeof(uint16_t);
00721         hspi->RxXferCount--;
00722       }
00723       else
00724       {
00725         /* Timeout management */
00726         if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout)))
00727         {
00728           errorcode = HAL_TIMEOUT;
00729           goto error;
00730         }
00731       }
00732     }
00733   }
00734
00735 #if (USE_SPI_CRC != 0U)
00736   /* Handle the CRC Transmission */
00737   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00738   {
00739     /* freeze the CRC before the latest data */
00740     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00741
00742     /* Read the latest data */
00743     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
00744     {
00745       /* the latest data has not been received */
00746       errorcode = HAL_TIMEOUT;
00747       goto error;
00748     }
00749
00750     /* Receive last data in 16 Bit mode */
00751     if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
00752     {
00753       *((uint16_t*)pData) = hspi->Instance->DR;
00754     }
00755     /* Receive last data in 8 Bit mode */
00756     else
00757     {
00758       (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
00759     }
00760
00761     /* Wait the CRC data */
00762     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
00763     {
00764       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00765       errorcode = HAL_TIMEOUT;
00766       goto error;
00767     }
00768
00769     /* Read CRC to Flush DR and RXNE flag */
00770     tmpreg = hspi->Instance->DR;
00771     /* To avoid GCC warning */
00772     UNUSED(tmpreg);
00773   }
00774 #endif /* USE_SPI_CRC */
00775
00776   /* Check the end of the transaction */
00777   if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
00778   {
00779     /* Disable SPI peripheral */
00780     __HAL_SPI_DISABLE(hspi);
00781   }
00782
00783 #if (USE_SPI_CRC != 0U)
00784     /* Check if CRC error occurred */
00785     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
00786     {
00787       /* Check if CRC error is valid or not (workaround to be applied or not) */
00788       if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
00789       {
00790         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00791
00792         /* Reset CRC Calculation */
00793         SPI_RESET_CRC(hspi);
00794       }
00795       else
00796       {
00797         __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
00798       }
00799     }
00800 #endif /* USE_SPI_CRC */
00801
00802   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
00803   {
00804     errorcode = HAL_ERROR;
00805   }
00806
00807 error :
00808   hspi->State = HAL_SPI_STATE_READY;
00809   __HAL_UNLOCK(hspi);
00810   return errorcode;
00811 }
00812
00813 /**
00814   * @brief  Transmit and Receive an amount of data in blocking mode.
00815   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00816   *               the configuration information for SPI module.
00817   * @param  pTxData: pointer to transmission data buffer
00818   * @param  pRxData: pointer to reception data buffer
00819   * @param  Size: amount of data to be sent and received
00820   * @param  Timeout: Timeout duration
00821   * @retval HAL status
00822   */
00823 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00824 {
00825   uint32_t tmp = 0U, tmp1 = 0U;
00826 #if (USE_SPI_CRC != 0U)
00827   __IO uint16_t tmpreg1 = 0U;
00828 #endif /* USE_SPI_CRC */
00829   uint32_t tickstart = 0U;
00830   /* Variable used to alternate Rx and Tx during transfer */
00831   uint32_t txallowed = 1U;
00832   HAL_StatusTypeDef errorcode = HAL_OK;
00833
00834   /* Check Direction parameter */
00835   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
00836
00837   /* Process Locked */
00838   __HAL_LOCK(hspi);
00839
00840   /* Init tickstart for timeout management*/
00841   tickstart = HAL_GetTick();
00842
00843   tmp  = hspi->State;
00844   tmp1 = hspi->Init.Mode;
00845
00846   if(!((tmp == HAL_SPI_STATE_READY) || \
00847     ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
00848   {
00849     errorcode = HAL_BUSY;
00850     goto error;
00851   }
00852
00853   if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00854   {
00855     errorcode = HAL_ERROR;
00856     goto error;
00857   }
00858
00859   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
00860   if(hspi->State == HAL_SPI_STATE_READY)
00861   {
00862     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
00863   }
00864
00865   /* Set the transaction information */
00866   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
00867   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
00868   hspi->RxXferCount = Size;
00869   hspi->RxXferSize  = Size;
00870   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
00871   hspi->TxXferCount = Size;
00872   hspi->TxXferSize  = Size;
00873
00874   /*Init field not used in handle to zero */
00875   hspi->RxISR       = NULL;
00876   hspi->TxISR       = NULL;
00877
00878 #if (USE_SPI_CRC != 0U)
00879   /* Reset CRC Calculation */
00880   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00881   {
00882     SPI_RESET_CRC(hspi);
00883   }
00884 #endif /* USE_SPI_CRC */
00885
00886   /* Check if the SPI is already enabled */
00887   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
00888   {
00889     /* Enable SPI peripheral */
00890     __HAL_SPI_ENABLE(hspi);
00891   }
00892
00893   /* Transmit and Receive data in 16 Bit mode */
00894   if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
00895   {
00896     if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
00897     {
00898       hspi->Instance->DR = *((uint16_t *)pTxData);
00899       pTxData += sizeof(uint16_t);
00900       hspi->TxXferCount--;
00901     }
00902     while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
00903     {
00904       /* Check TXE flag */
00905       if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
00906       {
00907         hspi->Instance->DR = *((uint16_t *)pTxData);
00908         pTxData += sizeof(uint16_t);
00909         hspi->TxXferCount--;
00910         /* Next Data is a reception (Rx). Tx not allowed */
00911         txallowed = 0U;
00912
00913 #if (USE_SPI_CRC != 0U)
00914         /* Enable CRC Transmission */
00915         if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
00916         {
00917           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00918         }
00919 #endif /* USE_SPI_CRC */
00920       }
00921
00922       /* Check RXNE flag */
00923       if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
00924       {
00925         *((uint16_t *)pRxData) = hspi->Instance->DR;
00926         pRxData += sizeof(uint16_t);
00927         hspi->RxXferCount--;
00928         /* Next Data is a Transmission (Tx). Tx is allowed */
00929         txallowed = 1U;
00930       }
00931       if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
00932       {
00933         errorcode = HAL_TIMEOUT;
00934         goto error;
00935       }
00936     }
00937   }
00938   /* Transmit and Receive data in 8 Bit mode */
00939   else
00940   {
00941     if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
00942     {
00943       *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData);
00944       pTxData += sizeof(uint8_t);
00945       hspi->TxXferCount--;
00946     }
00947     while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
00948     {
00949       /* check TXE flag */
00950       if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
00951       {
00952         *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
00953         hspi->TxXferCount--;
00954         /* Next Data is a reception (Rx). Tx not allowed */
00955         txallowed = 0U;
00956
00957 #if (USE_SPI_CRC != 0U)
00958         /* Enable CRC Transmission */
00959         if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
00960         {
00961           SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
00962         }
00963 #endif /* USE_SPI_CRC */
00964       }
00965
00966       /* Wait until RXNE flag is reset */
00967       if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
00968       {
00969         (*(uint8_t *)pRxData++) = hspi->Instance->DR;
00970         hspi->RxXferCount--;
00971         /* Next Data is a Transmission (Tx). Tx is allowed */
00972         txallowed = 1U;
00973       }
00974       if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >=  Timeout))
00975       {
00976         errorcode = HAL_TIMEOUT;
00977         goto error;
00978       }
00979     }
00980   }
00981
00982 #if (USE_SPI_CRC != 0U)
00983   /* Read CRC from DR to close CRC calculation process */
00984   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00985   {
00986     /* Wait until TXE flag */
00987     if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
00988     {
00989       /* Error on the CRC reception */
00990       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
00991       errorcode = HAL_TIMEOUT;
00992       goto error;
00993     }
00994     /* Read CRC */
00995     tmpreg1 = hspi->Instance->DR;
00996     /* To avoid GCC warning */
00997     UNUSED(tmpreg1);
00998   }
00999
01000   /* Check if CRC error occurred */
01001   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
01002   {
01003     /* Check if CRC error is valid or not (workaround to be applied or not) */
01004     if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
01005     {
01006       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
01007
01008       /* Reset CRC Calculation */
01009       SPI_RESET_CRC(hspi);
01010
01011           errorcode = HAL_ERROR;
01012     }
01013     else
01014     {
01015       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
01016     }
01017   }
01018 #endif /* USE_SPI_CRC */
01019
01020   /* Wait until TXE flag */
01021   if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
01022   {
01023     errorcode = HAL_TIMEOUT;
01024     goto error;
01025   }
01026
01027   /* Check Busy flag */
01028   if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
01029   {
01030     errorcode = HAL_ERROR;
01031     hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
01032     goto error;
01033   }
01034
01035   /* Clear overrun flag in 2 Lines communication mode because received is not read */
01036   if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
01037   {
01038     __HAL_SPI_CLEAR_OVRFLAG(hspi);
01039   }
01040
01041 error :
01042   hspi->State = HAL_SPI_STATE_READY;
01043   __HAL_UNLOCK(hspi);
01044   return errorcode;
01045 }
01046
01047 /**
01048   * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
01049   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01050   *               the configuration information for SPI module.
01051   * @param  pData: pointer to data buffer
01052   * @param  Size: amount of data to be sent
01053   * @retval HAL status
01054   */
01055 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01056 {
01057   HAL_StatusTypeDef errorcode = HAL_OK;
01058
01059   /* Check Direction parameter */
01060   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01061
01062   /* Process Locked */
01063   __HAL_LOCK(hspi);
01064
01065   if((pData == NULL) || (Size == 0U))
01066   {
01067     errorcode = HAL_ERROR;
01068     goto error;
01069   }
01070
01071   if(hspi->State != HAL_SPI_STATE_READY)
01072   {
01073     errorcode = HAL_BUSY;
01074     goto error;
01075   }
01076
01077   /* Set the transaction information */
01078   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01079   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01080   hspi->pTxBuffPtr  = (uint8_t *)pData;
01081   hspi->TxXferSize  = Size;
01082   hspi->TxXferCount = Size;
01083
01084   /* Init field not used in handle to zero */
01085   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01086   hspi->RxXferSize  = 0U;
01087   hspi->RxXferCount = 0U;
01088   hspi->RxISR       = NULL;
01089
01090   /* Set the function for IT treatment */
01091   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01092   {
01093     hspi->TxISR = SPI_TxISR_16BIT;
01094   }
01095   else
01096   {
01097     hspi->TxISR = SPI_TxISR_8BIT;
01098   }
01099
01100   /* Configure communication direction : 1Line */
01101   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01102   {
01103     SPI_1LINE_TX(hspi);
01104   }
01105
01106 #if (USE_SPI_CRC != 0U)
01107   /* Reset CRC Calculation */
01108   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01109   {
01110     SPI_RESET_CRC(hspi);
01111   }
01112 #endif /* USE_SPI_CRC */
01113
01114   if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
01115   {
01116     /* Enable TXE interrupt */
01117     __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
01118   }
01119   else
01120   {
01121     /* Enable TXE and ERR interrupt */
01122     __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
01123   }
01124
01125   /* Check if the SPI is already enabled */
01126   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01127   {
01128     /* Enable SPI peripheral */
01129     __HAL_SPI_ENABLE(hspi);
01130   }
01131
01132 error :
01133   __HAL_UNLOCK(hspi);
01134   return errorcode;
01135 }
01136
01137 /**
01138   * @brief  Receive an amount of data in non-blocking mode with Interrupt.
01139   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01140   *               the configuration information for SPI module.
01141   * @param  pData: pointer to data buffer
01142   * @param  Size: amount of data to be sent
01143   * @retval HAL status
01144   */
01145 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01146 {
01147   HAL_StatusTypeDef errorcode = HAL_OK;
01148
01149   if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
01150   {
01151      hspi->State = HAL_SPI_STATE_BUSY_RX;
01152      /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01153      return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
01154   }
01155
01156   /* Process Locked */
01157   __HAL_LOCK(hspi);
01158
01159   if(hspi->State != HAL_SPI_STATE_READY)
01160   {
01161     errorcode = HAL_BUSY;
01162     goto error;
01163   }
01164
01165   if((pData == NULL) || (Size == 0U))
01166   {
01167     errorcode = HAL_ERROR;
01168     goto error;
01169   }
01170
01171   /* Set the transaction information */
01172   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01173   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01174   hspi->pRxBuffPtr  = (uint8_t *)pData;
01175   hspi->RxXferSize  = Size;
01176   hspi->RxXferCount = Size;
01177
01178   /* Init field not used in handle to zero */
01179   hspi->pTxBuffPtr  = (uint8_t *)NULL;
01180   hspi->TxXferSize  = 0U;
01181   hspi->TxXferCount = 0U;
01182   hspi->TxISR       = NULL;
01183
01184   /* Set the function for IT treatment */
01185   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01186   {
01187     hspi->RxISR = SPI_RxISR_16BIT;
01188   }
01189   else
01190   {
01191     hspi->RxISR = SPI_RxISR_8BIT;
01192   }
01193
01194   /* Configure communication direction : 1Line */
01195   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01196   {
01197     SPI_1LINE_RX(hspi);
01198   }
01199
01200 #if (USE_SPI_CRC != 0U)
01201   /* Reset CRC Calculation */
01202   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01203   {
01204     SPI_RESET_CRC(hspi);
01205   }
01206 #endif /* USE_SPI_CRC */
01207
01208   /* Enable TXE and ERR interrupt */
01209   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
01210
01211   /* Note : The SPI must be enabled after unlocking current process
01212             to avoid the risk of SPI interrupt handle execution before current
01213             process unlock */
01214
01215   /* Check if the SPI is already enabled */
01216   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01217   {
01218     /* Enable SPI peripheral */
01219     __HAL_SPI_ENABLE(hspi);
01220   }
01221
01222 error :
01223   /* Process Unlocked */
01224   __HAL_UNLOCK(hspi);
01225   return errorcode;
01226 }
01227
01228 /**
01229   * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
01230   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01231   *               the configuration information for SPI module.
01232   * @param  pTxData: pointer to transmission data buffer
01233   * @param  pRxData: pointer to reception data buffer
01234   * @param  Size: amount of data to be sent and received
01235   * @retval HAL status
01236   */
01237 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01238 {
01239   uint32_t tmp = 0U, tmp1 = 0U;
01240   HAL_StatusTypeDef errorcode = HAL_OK;
01241
01242   /* Check Direction parameter */
01243   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01244
01245   /* Process locked */
01246   __HAL_LOCK(hspi);
01247
01248   tmp  = hspi->State;
01249   tmp1 = hspi->Init.Mode;
01250
01251   if(!((tmp == HAL_SPI_STATE_READY) || \
01252     ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
01253   {
01254     errorcode = HAL_BUSY;
01255     goto error;
01256   }
01257
01258   if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
01259   {
01260     errorcode = HAL_ERROR;
01261     goto error;
01262   }
01263
01264   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01265   if(hspi->State == HAL_SPI_STATE_READY)
01266   {
01267     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01268   }
01269
01270   /* Set the transaction information */
01271   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01272   hspi->pTxBuffPtr  = (uint8_t *)pTxData;
01273   hspi->TxXferSize  = Size;
01274   hspi->TxXferCount = Size;
01275   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
01276   hspi->RxXferSize  = Size;
01277   hspi->RxXferCount = Size;
01278
01279   /* Set the function for IT treatment */
01280   if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
01281   {
01282     hspi->RxISR     = SPI_2linesRxISR_16BIT;
01283     hspi->TxISR     = SPI_2linesTxISR_16BIT;
01284   }
01285   else
01286   {
01287     hspi->RxISR     = SPI_2linesRxISR_8BIT;
01288     hspi->TxISR     = SPI_2linesTxISR_8BIT;
01289   }
01290
01291 #if (USE_SPI_CRC != 0U)
01292   /* Reset CRC Calculation */
01293   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01294   {
01295     SPI_RESET_CRC(hspi);
01296   }
01297 #endif /* USE_SPI_CRC */
01298
01299   /* Enable TXE, RXNE and ERR interrupt */
01300   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
01301
01302   /* Check if the SPI is already enabled */
01303   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01304   {
01305     /* Enable SPI peripheral */
01306     __HAL_SPI_ENABLE(hspi);
01307   }
01308
01309 error :
01310   /* Process Unlocked */
01311   __HAL_UNLOCK(hspi);
01312   return errorcode;
01313 }
01314
01315 /**
01316   * @brief  Transmit an amount of data in non-blocking mode with DMA.
01317   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01318   *               the configuration information for SPI module.
01319   * @param  pData: pointer to data buffer
01320   * @param  Size: amount of data to be sent
01321   * @retval HAL status
01322   */
01323 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01324 {
01325   HAL_StatusTypeDef errorcode = HAL_OK;
01326
01327   /* Check Direction parameter */
01328   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
01329
01330   /* Process Locked */
01331   __HAL_LOCK(hspi);
01332
01333   if(hspi->State != HAL_SPI_STATE_READY)
01334   {
01335     errorcode = HAL_BUSY;
01336     goto error;
01337   }
01338
01339   if((pData == NULL) || (Size == 0U))
01340   {
01341     errorcode = HAL_ERROR;
01342     goto error;
01343   }
01344
01345   /* Set the transaction information */
01346   hspi->State       = HAL_SPI_STATE_BUSY_TX;
01347   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01348   hspi->pTxBuffPtr  = (uint8_t *)pData;
01349   hspi->TxXferSize  = Size;
01350   hspi->TxXferCount = Size;
01351
01352   /* Init field not used in handle to zero */
01353   hspi->pRxBuffPtr  = (uint8_t *)NULL;
01354   hspi->TxISR       = NULL;
01355   hspi->RxISR       = NULL;
01356   hspi->RxXferSize  = 0U;
01357   hspi->RxXferCount = 0U;
01358
01359   /* Configure communication direction : 1Line */
01360   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01361   {
01362     SPI_1LINE_TX(hspi);
01363   }
01364
01365 #if (USE_SPI_CRC != 0U)
01366   /* Reset CRC Calculation */
01367   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01368   {
01369     SPI_RESET_CRC(hspi);
01370   }
01371 #endif /* USE_SPI_CRC */
01372
01373   /* Set the SPI TxDMA Half transfer complete callback */
01374   hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
01375
01376   /* Set the SPI TxDMA transfer complete callback */
01377   hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
01378
01379   /* Set the DMA error callback */
01380   hspi->hdmatx->XferErrorCallback = SPI_DMAError;
01381
01382   /* Set the DMA AbortCpltCallback */
01383   hspi->hdmatx->XferAbortCallback = NULL;
01384
01385   /* Enable the Tx DMA Stream */
01386   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
01387
01388   /* Check if the SPI is already enabled */
01389   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01390   {
01391     /* Enable SPI peripheral */
01392     __HAL_SPI_ENABLE(hspi);
01393   }
01394
01395   /* Enable the SPI Error Interrupt Bit */
01396   SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
01397
01398   /* Enable Tx DMA Request */
01399   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01400
01401 error :
01402   /* Process Unlocked */
01403   __HAL_UNLOCK(hspi);
01404   return errorcode;
01405 }
01406
01407 /**
01408   * @brief  Receive an amount of data in non-blocking mode with DMA.
01409   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01410   *               the configuration information for SPI module.
01411   * @param  pData: pointer to data buffer
01412   * @note   When the CRC feature is enabled the pData Length must be Size + 1.
01413   * @param  Size: amount of data to be sent
01414   * @retval HAL status
01415   */
01416 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
01417 {
01418   HAL_StatusTypeDef errorcode = HAL_OK;
01419
01420   if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
01421   {
01422      hspi->State = HAL_SPI_STATE_BUSY_RX;
01423      /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
01424      return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
01425   }
01426
01427   /* Process Locked */
01428   __HAL_LOCK(hspi);
01429
01430   if(hspi->State != HAL_SPI_STATE_READY)
01431   {
01432     errorcode = HAL_BUSY;
01433     goto error;
01434   }
01435
01436   if((pData == NULL) || (Size == 0U))
01437   {
01438     errorcode = HAL_ERROR;
01439     goto error;
01440   }
01441
01442   /* Set the transaction information */
01443   hspi->State       = HAL_SPI_STATE_BUSY_RX;
01444   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01445   hspi->pRxBuffPtr  = (uint8_t *)pData;
01446   hspi->RxXferSize  = Size;
01447   hspi->RxXferCount = Size;
01448
01449   /*Init field not used in handle to zero */
01450   hspi->RxISR       = NULL;
01451   hspi->TxISR       = NULL;
01452   hspi->TxXferSize  = 0U;
01453   hspi->TxXferCount = 0U;
01454
01455   /* Configure communication direction : 1Line */
01456   if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
01457   {
01458     SPI_1LINE_RX(hspi);
01459   }
01460
01461 #if (USE_SPI_CRC != 0U)
01462   /* Reset CRC Calculation */
01463   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01464   {
01465     SPI_RESET_CRC(hspi);
01466   }
01467 #endif /* USE_SPI_CRC */
01468
01469   /* Set the SPI RxDMA Half transfer complete callback */
01470   hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01471
01472   /* Set the SPI Rx DMA transfer complete callback */
01473   hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
01474
01475   /* Set the DMA error callback */
01476   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01477
01478  /* Set the DMA AbortCpltCallback */
01479   hspi->hdmarx->XferAbortCallback = NULL;
01480
01481   /* Enable the Rx DMA Stream */
01482   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
01483
01484   /* Check if the SPI is already enabled */
01485   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01486   {
01487     /* Enable SPI peripheral */
01488     __HAL_SPI_ENABLE(hspi);
01489   }
01490
01491   /* Enable the SPI Error Interrupt Bit */
01492   SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
01493
01494   /* Enable Rx DMA Request */
01495   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
01496
01497 error:
01498   /* Process Unlocked */
01499   __HAL_UNLOCK(hspi);
01500   return errorcode;
01501 }
01502
01503 /**
01504   * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
01505   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01506   *               the configuration information for SPI module.
01507   * @param  pTxData: pointer to transmission data buffer
01508   * @param  pRxData: pointer to reception data buffer
01509   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
01510   * @param  Size: amount of data to be sent
01511   * @retval HAL status
01512   */
01513 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01514 {
01515   uint32_t tmp = 0U, tmp1 = 0U;
01516   HAL_StatusTypeDef errorcode = HAL_OK;
01517
01518   /* Check Direction parameter */
01519   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
01520
01521   /* Process locked */
01522   __HAL_LOCK(hspi);
01523
01524   tmp  = hspi->State;
01525   tmp1 = hspi->Init.Mode;
01526   if(!((tmp == HAL_SPI_STATE_READY) ||
01527       ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
01528   {
01529     errorcode = HAL_BUSY;
01530     goto error;
01531   }
01532
01533   if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
01534   {
01535     errorcode = HAL_ERROR;
01536     goto error;
01537   }
01538
01539   /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
01540   if(hspi->State == HAL_SPI_STATE_READY)
01541   {
01542     hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
01543   }
01544
01545   /* Set the transaction information */
01546   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
01547   hspi->pTxBuffPtr  = (uint8_t*)pTxData;
01548   hspi->TxXferSize  = Size;
01549   hspi->TxXferCount = Size;
01550   hspi->pRxBuffPtr  = (uint8_t*)pRxData;
01551   hspi->RxXferSize  = Size;
01552   hspi->RxXferCount = Size;
01553
01554   /* Init field not used in handle to zero */
01555   hspi->RxISR       = NULL;
01556   hspi->TxISR       = NULL;
01557
01558 #if (USE_SPI_CRC != 0U)
01559   /* Reset CRC Calculation */
01560   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
01561   {
01562     SPI_RESET_CRC(hspi);
01563   }
01564 #endif /* USE_SPI_CRC */
01565
01566   /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
01567   if(hspi->State == HAL_SPI_STATE_BUSY_RX)
01568   {
01569     /* Set the SPI Rx DMA Half transfer complete callback */
01570     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
01571     hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
01572   }
01573   else
01574   {
01575     /* Set the SPI Tx/Rx DMA Half transfer complete callback */
01576     hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
01577     hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
01578   }
01579
01580   /* Set the DMA error callback */
01581   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
01582
01583   /* Set the DMA AbortCpltCallback */
01584   hspi->hdmarx->XferAbortCallback = NULL;
01585
01586   /* Enable the Rx DMA Stream */
01587   HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
01588
01589   /* Enable Rx DMA Request */
01590   SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
01591
01592   /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
01593   is performed in DMA reception complete callback  */
01594   hspi->hdmatx->XferHalfCpltCallback = NULL;
01595   hspi->hdmatx->XferCpltCallback     = NULL;
01596   hspi->hdmatx->XferErrorCallback    = NULL;
01597   hspi->hdmatx->XferAbortCallback    = NULL;
01598
01599   /* Enable the Tx DMA Stream */
01600   HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
01601
01602   /* Check if the SPI is already enabled */
01603   if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
01604   {
01605     /* Enable SPI peripheral */
01606     __HAL_SPI_ENABLE(hspi);
01607   }
01608   /* Enable the SPI Error Interrupt Bit */
01609   SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
01610
01611   /* Enable Tx DMA Request */
01612   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
01613
01614 error :
01615   /* Process Unlocked */
01616   __HAL_UNLOCK(hspi);
01617   return errorcode;
01618 }
01619
01620 /**
01621   * @brief  Abort ongoing transfer (blocking mode).
01622   * @param  hspi SPI handle.
01623   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
01624   *         started in Interrupt or DMA mode.
01625   *         This procedure performs following operations :
01626   *           - Disable SPI Interrupts (depending of transfer direction)
01627   *           - Disable the DMA transfer in the peripheral register (if enabled)
01628   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01629   *           - Set handle State to READY
01630   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01631   * @note   Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
01632   *         before starting new SPI receive process.
01633   * @retval HAL status
01634 */
01635 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
01636 {
01637   __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
01638
01639   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
01640   if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
01641   {
01642     hspi->TxISR = SPI_AbortTx_ISR;
01643   }
01644
01645   if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
01646   {
01647     hspi->RxISR = SPI_AbortRx_ISR;
01648   }
01649
01650   /* Clear ERRIE interrupts in case of DMA Mode */
01651   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
01652
01653   /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
01654   if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
01655   {
01656     /* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */
01657     if(hspi->hdmatx != NULL)
01658     {
01659       /* Set the SPI DMA Abort callback :
01660       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
01661       hspi->hdmatx->XferAbortCallback = NULL;
01662
01663       /* Abort DMA Tx Handle linked to SPI Peripheral */
01664       HAL_DMA_Abort(hspi->hdmatx);
01665
01666       /* Disable Tx DMA Request */
01667       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
01668
01669       /* Wait until TXE flag is set */
01670       do
01671       {
01672         if(count-- == 0U)
01673         {
01674           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
01675           break;
01676         }
01677       }
01678       while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
01679     }
01680     /* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */
01681     if(hspi->hdmarx != NULL)
01682     {
01683       /* Set the SPI DMA Abort callback :
01684       will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
01685       hspi->hdmarx->XferAbortCallback = NULL;
01686
01687       /* Abort DMA Rx Handle linked to SPI Peripheral */
01688       HAL_DMA_Abort(hspi->hdmarx);
01689
01690       /* Disable peripheral */
01691       __HAL_SPI_DISABLE(hspi);
01692
01693       /* Disable Rx DMA Request */
01694       CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
01695
01696     }
01697   }
01698   /* Reset Tx and Rx transfer counters */
01699   hspi->RxXferCount = 0U;
01700   hspi->TxXferCount = 0U;
01701
01702   /* Reset errorCode */
01703   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
01704
01705   /* Clear the Error flags in the SR register */
01706   __HAL_SPI_CLEAR_OVRFLAG(hspi);
01707
01708   /* Restore hspi->state to ready */
01709   hspi->State = HAL_SPI_STATE_READY;
01710
01711   return HAL_OK;
01712 }
01713
01714 /**
01715   * @brief  Abort ongoing transfer (Interrupt mode).
01716   * @param  hspi SPI handle.
01717   * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
01718   *         started in Interrupt or DMA mode.
01719   *         This procedure performs following operations :
01720   *           - Disable SPI Interrupts (depending of transfer direction)
01721   *           - Disable the DMA transfer in the peripheral register (if enabled)
01722   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01723   *           - Set handle State to READY
01724   *           - At abort completion, call user abort complete callback
01725   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01726   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01727   * @note   Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
01728   *         before starting new SPI receive process.
01729   * @retval HAL status
01730 */
01731 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
01732 {
01733   uint32_t abortcplt;
01734
01735   /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
01736   if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
01737   {
01738     hspi->TxISR = SPI_AbortTx_ISR;
01739   }
01740
01741   if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
01742   {
01743     hspi->RxISR = SPI_AbortRx_ISR;
01744   }
01745
01746   /* Clear ERRIE interrupts in case of DMA Mode */
01747   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
01748
01749   abortcplt = 1U;
01750
01751   /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
01752      before any call to DMA Abort functions */
01753   /* DMA Tx Handle is valid */
01754   if(hspi->hdmatx != NULL)
01755   {
01756     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
01757        Otherwise, set it to NULL */
01758     if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
01759     {
01760       hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
01761     }
01762     else
01763     {
01764       hspi->hdmatx->XferAbortCallback = NULL;
01765     }
01766   }
01767   /* DMA Rx Handle is valid */
01768   if(hspi->hdmarx != NULL)
01769   {
01770     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
01771        Otherwise, set it to NULL */
01772     if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
01773     {
01774       hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
01775     }
01776     else
01777     {
01778       hspi->hdmarx->XferAbortCallback = NULL;
01779     }
01780   }
01781
01782   /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
01783   if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
01784   {
01785     /* Abort the SPI DMA Tx channel */
01786     if(hspi->hdmatx != NULL)
01787     {
01788       /* Abort DMA Tx Handle linked to SPI Peripheral */
01789       if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
01790       {
01791         hspi->hdmatx->XferAbortCallback = NULL;
01792       }
01793       else
01794       {
01795         abortcplt = 0U;
01796       }
01797     }
01798     /* Abort the SPI DMA Rx channel */
01799     if(hspi->hdmarx != NULL)
01800     {
01801       /* Abort DMA Rx Handle linked to SPI Peripheral */
01802       if(HAL_DMA_Abort_IT(hspi->hdmarx)!=  HAL_OK)
01803       {
01804         hspi->hdmarx->XferAbortCallback = NULL;
01805         abortcplt = 1U;
01806       }
01807       else
01808       {
01809         abortcplt = 0U;
01810       }
01811     }
01812   }
01813
01814   /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
01815   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
01816   {
01817     /* Abort the SPI DMA Tx channel */
01818     if(hspi->hdmatx != NULL)
01819     {
01820       /* Abort DMA Tx Handle linked to SPI Peripheral */
01821       if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
01822       {
01823         hspi->hdmatx->XferAbortCallback = NULL;
01824       }
01825       else
01826       {
01827         abortcplt = 0U;
01828       }
01829     }
01830   }
01831   /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
01832   if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
01833   {
01834     /* Abort the SPI DMA Rx channel */
01835     if(hspi->hdmarx != NULL)
01836     {
01837       /* Abort DMA Rx Handle linked to SPI Peripheral */
01838       if(HAL_DMA_Abort_IT(hspi->hdmarx)!=  HAL_OK)
01839       {
01840         hspi->hdmarx->XferAbortCallback = NULL;
01841       }
01842       else
01843       {
01844         abortcplt = 0U;
01845       }
01846     }
01847   }
01848
01849   if(abortcplt == 1U)
01850   {
01851     /* Reset Tx and Rx transfer counters */
01852     hspi->RxXferCount = 0U;
01853     hspi->TxXferCount = 0U;
01854
01855     /* Reset errorCode */
01856     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
01857
01858     /* Clear the Error flags in the SR register */
01859     __HAL_SPI_CLEAR_OVRFLAG(hspi);
01860
01861     /* Restore hspi->State to Ready */
01862     hspi->State = HAL_SPI_STATE_READY;
01863
01864     /* As no DMA to be aborted, call directly user Abort complete callback */
01865     HAL_SPI_AbortCpltCallback(hspi);
01866   }
01867   return HAL_OK;
01868 }
01869
01870 /**
01871   * @brief  Pause the DMA Transfer.
01872   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01873   *               the configuration information for the specified SPI module.
01874   * @retval HAL status
01875   */
01876 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
01877 {
01878   /* Process Locked */
01879   __HAL_LOCK(hspi);
01880
01881   /* Disable the SPI DMA Tx & Rx requests */
01882   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01883
01884   /* Process Unlocked */
01885   __HAL_UNLOCK(hspi);
01886
01887   return HAL_OK;
01888 }
01889
01890 /**
01891   * @brief  Resume the DMA Transfer.
01892   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01893   *               the configuration information for the specified SPI module.
01894   * @retval HAL status
01895   */
01896 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
01897 {
01898   /* Process Locked */
01899   __HAL_LOCK(hspi);
01900
01901   /* Enable the SPI DMA Tx & Rx requests */
01902   SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01903
01904   /* Process Unlocked */
01905   __HAL_UNLOCK(hspi);
01906
01907   return HAL_OK;
01908 }
01909
01910 /**
01911   * @brief Stop the DMA Transfer.
01912   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01913   *               the configuration information for the specified SPI module.
01914   * @retval HAL status
01915   */
01916 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
01917 {
01918   /* The Lock is not implemented on this API to allow the user application
01919      to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
01920      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
01921      and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
01922      */
01923
01924   /* Abort the SPI DMA tx Stream */
01925   if(hspi->hdmatx != NULL)
01926   {
01927     HAL_DMA_Abort(hspi->hdmatx);
01928   }
01929   /* Abort the SPI DMA rx Stream */
01930   if(hspi->hdmarx != NULL)
01931   {
01932     HAL_DMA_Abort(hspi->hdmarx);
01933   }
01934
01935   /* Disable the SPI DMA Tx & Rx requests */
01936   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
01937   hspi->State = HAL_SPI_STATE_READY;
01938   return HAL_OK;
01939 }
01940
01941 /**
01942   * @brief  Handle SPI interrupt request.
01943   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
01944   *               the configuration information for the specified SPI module.
01945   * @retval None
01946   */
01947 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
01948 {
01949   uint32_t itsource = hspi->Instance->CR2;
01950   uint32_t itflag   = hspi->Instance->SR;
01951
01952   /* SPI in mode Receiver ----------------------------------------------------*/
01953   if(((itflag & SPI_FLAG_OVR) == RESET) &&
01954      ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
01955   {
01956     hspi->RxISR(hspi);
01957     return;
01958   }
01959
01960   /* SPI in mode Transmitter -------------------------------------------------*/
01961   if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
01962   {
01963     hspi->TxISR(hspi);
01964     return;
01965   }
01966
01967   /* SPI in Error Treatment --------------------------------------------------*/
01968   if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
01969   {
01970     /* SPI Overrun error interrupt occurred ----------------------------------*/
01971     if((itflag & SPI_FLAG_OVR) != RESET)
01972     {
01973       if(hspi->State != HAL_SPI_STATE_BUSY_TX)
01974       {
01975         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
01976         __HAL_SPI_CLEAR_OVRFLAG(hspi);
01977       }
01978       else
01979       {
01980         __HAL_SPI_CLEAR_OVRFLAG(hspi);
01981         return;
01982       }
01983     }
01984
01985     /* SPI Mode Fault error interrupt occurred -------------------------------*/
01986     if((itflag & SPI_FLAG_MODF) != RESET)
01987     {
01988       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
01989       __HAL_SPI_CLEAR_MODFFLAG(hspi);
01990     }
01991
01992     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
01993     {
01994       /* Disable all interrupts */
01995       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
01996
01997       hspi->State = HAL_SPI_STATE_READY;
01998       /* Disable the SPI DMA requests if enabled */
01999       if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
02000       {
02001         CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
02002
02003         /* Abort the SPI DMA Rx channel */
02004         if(hspi->hdmarx != NULL)
02005         {
02006           /* Set the SPI DMA Abort callback :
02007           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02008           hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
02009           HAL_DMA_Abort_IT(hspi->hdmarx);
02010         }
02011         /* Abort the SPI DMA Tx channel */
02012         if(hspi->hdmatx != NULL)
02013         {
02014           /* Set the SPI DMA Abort callback :
02015           will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
02016           hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
02017           HAL_DMA_Abort_IT(hspi->hdmatx);
02018         }
02019       }
02020       else
02021       {
02022         /* Call user error callback */
02023         HAL_SPI_ErrorCallback(hspi);
02024       }
02025     }
02026     return;
02027   }
02028 }
02029
02030 /**
02031   * @brief Tx Transfer completed callback.
02032   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02033   *               the configuration information for SPI module.
02034   * @retval None
02035   */
02036 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
02037 {
02038   /* Prevent unused argument(s) compilation warning */
02039   UNUSED(hspi);
02040   /* NOTE : This function should not be modified, when the callback is needed,
02041             the HAL_SPI_TxCpltCallback should be implemented in the user file
02042   */
02043 }
02044
02045 /**
02046   * @brief Rx Transfer completed callback.
02047   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02048   *               the configuration information for SPI module.
02049   * @retval None
02050   */
02051 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
02052 {
02053   /* Prevent unused argument(s) compilation warning */
02054   UNUSED(hspi);
02055   /* NOTE : This function should not be modified, when the callback is needed,
02056             the HAL_SPI_RxCpltCallback should be implemented in the user file
02057   */
02058 }
02059
02060 /**
02061   * @brief Tx and Rx Transfer completed callback.
02062   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02063   *               the configuration information for SPI module.
02064   * @retval None
02065   */
02066 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
02067 {
02068   /* Prevent unused argument(s) compilation warning */
02069   UNUSED(hspi);
02070   /* NOTE : This function should not be modified, when the callback is needed,
02071             the HAL_SPI_TxRxCpltCallback should be implemented in the user file
02072   */
02073 }
02074
02075 /**
02076   * @brief Tx Half Transfer completed callback.
02077   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02078   *               the configuration information for SPI module.
02079   * @retval None
02080   */
02081 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02082 {
02083   /* Prevent unused argument(s) compilation warning */
02084   UNUSED(hspi);
02085   /* NOTE : This function should not be modified, when the callback is needed,
02086             the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
02087   */
02088 }
02089
02090 /**
02091   * @brief Rx Half Transfer completed callback.
02092   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02093   *               the configuration information for SPI module.
02094   * @retval None
02095   */
02096 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02097 {
02098   /* Prevent unused argument(s) compilation warning */
02099   UNUSED(hspi);
02100   /* NOTE : This function should not be modified, when the callback is needed,
02101             the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
02102   */
02103 }
02104
02105 /**
02106   * @brief Tx and Rx Half Transfer callback.
02107   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02108   *               the configuration information for SPI module.
02109   * @retval None
02110   */
02111 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
02112 {
02113   /* Prevent unused argument(s) compilation warning */
02114   UNUSED(hspi);
02115   /* NOTE : This function should not be modified, when the callback is needed,
02116             the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
02117   */
02118 }
02119
02120 /**
02121   * @brief SPI error callback.
02122   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02123   *               the configuration information for SPI module.
02124   * @retval None
02125   */
02126  __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
02127 {
02128   /* Prevent unused argument(s) compilation warning */
02129   UNUSED(hspi);
02130   /* NOTE : This function should not be modified, when the callback is needed,
02131             the HAL_SPI_ErrorCallback should be implemented in the user file
02132    */
02133   /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
02134             and user can use HAL_SPI_GetError() API to check the latest error occurred
02135   */
02136 }
02137
02138 /**
02139   * @brief  SPI Abort Complete callback.
02140   * @param  hspi SPI handle.
02141   * @retval None
02142   */
02143 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
02144 {
02145   /* Prevent unused argument(s) compilation warning */
02146   UNUSED(hspi);
02147
02148   /* NOTE : This function should not be modified, when the callback is needed,
02149             the HAL_SPI_AbortCpltCallback can be implemented in the user file.
02150    */
02151 }
02152
02153 /**
02154   * @}
02155   */
02156
02157 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
02158   * @brief   SPI control functions
02159   *
02160 @verbatim
02161  ===============================================================================
02162                       ##### Peripheral State and Errors functions #####
02163  ===============================================================================
02164     [..]
02165     This subsection provides a set of functions allowing to control the SPI.
02166      (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
02167      (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
02168 @endverbatim
02169   * @{
02170   */
02171
02172 /**
02173   * @brief  Return the SPI handle state.
02174   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02175   *               the configuration information for SPI module.
02176   * @retval SPI state
02177   */
02178 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
02179 {
02180   /* Return SPI handle state */
02181   return hspi->State;
02182 }
02183
02184 /**
02185   * @brief  Return the SPI error code.
02186   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02187   *               the configuration information for SPI module.
02188   * @retval SPI error code in bitmap format
02189   */
02190 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
02191 {
02192   /* Return SPI ErrorCode */
02193   return hspi->ErrorCode;
02194 }
02195
02196 /**
02197   * @}
02198   */
02199
02200 /**
02201   * @}
02202   */
02203
02204 /** @addtogroup SPI_Private_Functions
02205   * @brief   Private functions
02206   * @{
02207   */
02208
02209 /**
02210   * @brief DMA SPI transmit process complete callback.
02211   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02212   *               the configuration information for the specified DMA module.
02213   * @retval None
02214   */
02215 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02216 {
02217   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02218   uint32_t tickstart = 0U;
02219
02220   /* Init tickstart for timeout managment*/
02221   tickstart = HAL_GetTick();
02222
02223   /* DMA Normal Mode */
02224   if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
02225   {
02226     /* Disable Tx DMA Request */
02227     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
02228
02229     /* Check the end of the transaction */
02230     if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02231     {
02232       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02233     }
02234
02235     /* Clear overrun flag in 2 Lines communication mode because received data is not read */
02236     if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
02237     {
02238       __HAL_SPI_CLEAR_OVRFLAG(hspi);
02239     }
02240
02241     hspi->TxXferCount = 0U;
02242     hspi->State = HAL_SPI_STATE_READY;
02243
02244     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02245     {
02246       HAL_SPI_ErrorCallback(hspi);
02247       return;
02248     }
02249   }
02250   HAL_SPI_TxCpltCallback(hspi);
02251 }
02252
02253 /**
02254   * @brief DMA SPI receive process complete callback.
02255   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02256   *               the configuration information for the specified DMA module.
02257   * @retval None
02258   */
02259 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02260 {
02261   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02262 #if (USE_SPI_CRC != 0U)
02263   uint32_t tickstart = 0U;
02264   __IO uint16_t tmpreg = 0U;
02265
02266   /* Init tickstart for timeout management*/
02267   tickstart = HAL_GetTick();
02268 #endif /* USE_SPI_CRC */
02269
02270   if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
02271   {
02272 #if (USE_SPI_CRC != 0U)
02273     /* CRC handling */
02274     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02275     {
02276       /* Wait until RXNE flag */
02277       if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02278       {
02279         /* Error on the CRC reception */
02280         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02281       }
02282       /* Read CRC */
02283       tmpreg = hspi->Instance->DR;
02284       /* To avoid GCC warning */
02285       UNUSED(tmpreg);
02286     }
02287 #endif /* USE_SPI_CRC */
02288
02289     /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
02290     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02291
02292     /* Check the end of the transaction */
02293     if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02294     {
02295       /* Disable SPI peripheral */
02296       __HAL_SPI_DISABLE(hspi);
02297     }
02298
02299     hspi->RxXferCount = 0U;
02300     hspi->State = HAL_SPI_STATE_READY;
02301
02302 #if (USE_SPI_CRC != 0U)
02303     /* Check if CRC error occurred */
02304     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
02305     {
02306       /* Check if CRC error is valid or not (workaround to be applied or not) */
02307       if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
02308       {
02309         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02310
02311         /* Reset CRC Calculation */
02312         SPI_RESET_CRC(hspi);
02313     }
02314       else
02315       {
02316         __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02317       }
02318     }
02319 #endif /* USE_SPI_CRC */
02320
02321     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02322     {
02323       HAL_SPI_ErrorCallback(hspi);
02324       return;
02325     }
02326   }
02327   HAL_SPI_RxCpltCallback(hspi);
02328 }
02329
02330 /**
02331   * @brief  DMA SPI transmit receive process complete callback.
02332   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02333   *               the configuration information for the specified DMA module.
02334   * @retval None
02335   */
02336 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02337 {
02338   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02339   uint32_t tickstart = 0U;
02340 #if (USE_SPI_CRC != 0U)
02341   __IO int16_t tmpreg = 0U;
02342 #endif /* USE_SPI_CRC */
02343   /* Init tickstart for timeout management*/
02344   tickstart = HAL_GetTick();
02345
02346   if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
02347   {
02348 #if (USE_SPI_CRC != 0U)
02349     /* CRC handling */
02350     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02351     {
02352       /* Wait the CRC data */
02353       if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02354       {
02355         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02356       }
02357       /* Read CRC to Flush DR and RXNE flag */
02358       tmpreg = hspi->Instance->DR;
02359       /* To avoid GCC warning */
02360       UNUSED(tmpreg);
02361     }
02362 #endif /* USE_SPI_CRC */
02363     /* Check the end of the transaction */
02364     if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
02365     {
02366       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02367     }
02368
02369     /* Disable Rx/Tx DMA Request */
02370     CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02371
02372     hspi->TxXferCount = 0U;
02373     hspi->RxXferCount = 0U;
02374     hspi->State = HAL_SPI_STATE_READY;
02375
02376 #if (USE_SPI_CRC != 0U)
02377     /* Check if CRC error occurred */
02378     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
02379     {
02380       /* Check if CRC error is valid or not (workaround to be applied or not) */
02381       if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
02382       {
02383         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
02384
02385         /* Reset CRC Calculation */
02386         SPI_RESET_CRC(hspi);
02387     }
02388       else
02389       {
02390         __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
02391       }
02392     }
02393 #endif /* USE_SPI_CRC */
02394
02395     if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
02396     {
02397       HAL_SPI_ErrorCallback(hspi);
02398       return;
02399     }
02400   }
02401   HAL_SPI_TxRxCpltCallback(hspi);
02402 }
02403
02404 /**
02405   * @brief  DMA SPI half transmit process complete callback.
02406   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02407   *               the configuration information for the specified DMA module.
02408   * @retval None
02409   */
02410 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
02411 {
02412   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02413
02414   HAL_SPI_TxHalfCpltCallback(hspi);
02415 }
02416
02417 /**
02418   * @brief  DMA SPI half receive process complete callback
02419   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02420   *               the configuration information for the specified DMA module.
02421   * @retval None
02422   */
02423 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
02424 {
02425   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02426
02427   HAL_SPI_RxHalfCpltCallback(hspi);
02428 }
02429
02430 /**
02431   * @brief  DMA SPI half transmit receive process complete callback.
02432   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02433   *               the configuration information for the specified DMA module.
02434   * @retval None
02435   */
02436 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
02437 {
02438   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02439
02440   HAL_SPI_TxRxHalfCpltCallback(hspi);
02441 }
02442
02443 /**
02444   * @brief  DMA SPI communication error callback.
02445   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02446   *               the configuration information for the specified DMA module.
02447   * @retval None
02448   */
02449 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
02450 {
02451   SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02452
02453 /* Stop the disable DMA transfer on SPI side */
02454   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
02455
02456   SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
02457   hspi->State = HAL_SPI_STATE_READY;
02458   HAL_SPI_ErrorCallback(hspi);
02459 }
02460
02461 /**
02462   * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
02463   *         (To be called at end of DMA Abort procedure following error occurrence).
02464   * @param  hdma DMA handle.
02465   * @retval None
02466   */
02467 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02468 {
02469   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02470   hspi->RxXferCount = 0U;
02471   hspi->TxXferCount = 0U;
02472
02473   HAL_SPI_ErrorCallback(hspi);
02474 }
02475
02476 /**
02477   * @brief  DMA SPI Tx communication abort callback, when initiated by user
02478   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02479   * @note   When this callback is executed, User Abort complete call back is called only if no
02480   *         Abort still ongoing for Rx DMA Handle.
02481   * @param  hdma DMA handle.
02482   * @retval None
02483   */
02484 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02485 {
02486   __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
02487   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02488
02489   hspi->hdmatx->XferAbortCallback = NULL;
02490
02491   /* Disable Tx DMA Request */
02492   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN );
02493
02494   /* Wait until TXE flag is set */
02495   do
02496   {
02497     if(count-- == 0U)
02498     {
02499       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02500       break;
02501     }
02502   }
02503   while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
02504
02505   /* Check if an Abort process is still ongoing */
02506   if(hspi->hdmarx != NULL)
02507   {
02508     if(hspi->hdmarx->XferAbortCallback != NULL)
02509     {
02510       return;
02511     }
02512   }
02513
02514   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02515   hspi->RxXferCount = 0U;
02516   hspi->TxXferCount = 0U;
02517
02518   /* Reset errorCode */
02519   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02520
02521   /* Restore hspi->State to Ready */
02522   hspi->State  = HAL_SPI_STATE_READY;
02523
02524   /* Call user Abort complete callback */
02525   HAL_SPI_AbortCpltCallback(hspi);
02526 }
02527
02528 /**
02529   * @brief  DMA SPI Rx communication abort callback, when initiated by user
02530   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02531   * @note   When this callback is executed, User Abort complete call back is called only if no
02532   *         Abort still ongoing for Tx DMA Handle.
02533   * @param  hdma DMA handle.
02534   * @retval None
02535   */
02536 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02537 {
02538   SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02539
02540   /* Disable SPI Peripheral */
02541   __HAL_SPI_DISABLE(hspi);
02542
02543   hspi->hdmarx->XferAbortCallback = NULL;
02544
02545   /* Disable Rx DMA Request */
02546   CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
02547
02548   /* Check if an Abort process is still ongoing */
02549   if(hspi->hdmatx != NULL)
02550   {
02551     if(hspi->hdmatx->XferAbortCallback != NULL)
02552     {
02553       return;
02554     }
02555   }
02556
02557   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02558   hspi->RxXferCount = 0U;
02559   hspi->TxXferCount = 0U;
02560
02561   /* Reset errorCode */
02562   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
02563
02564   /* Clear the Error flags in the SR register */
02565   __HAL_SPI_CLEAR_OVRFLAG(hspi);
02566
02567   /* Restore hspi->State to Ready */
02568   hspi->State  = HAL_SPI_STATE_READY;
02569
02570   /* Call user Abort complete callback */
02571   HAL_SPI_AbortCpltCallback(hspi);
02572 }
02573
02574 /**
02575   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
02576   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02577   *               the configuration information for SPI module.
02578   * @retval None
02579   */
02580 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02581 {
02582   /* Receive data in 8bit mode */
02583   *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
02584   hspi->RxXferCount--;
02585
02586   /* check end of the reception */
02587   if(hspi->RxXferCount == 0U)
02588   {
02589 #if (USE_SPI_CRC != 0U)
02590     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02591     {
02592       hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
02593       return;
02594     }
02595 #endif /* USE_SPI_CRC */
02596
02597     /* Disable RXNE interrupt */
02598     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02599
02600     if(hspi->TxXferCount == 0U)
02601     {
02602       SPI_CloseRxTx_ISR(hspi);
02603     }
02604   }
02605 }
02606
02607 #if (USE_SPI_CRC != 0U)
02608 /**
02609   * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
02610   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02611   *               the configuration information for SPI module.
02612   * @retval None
02613   */
02614 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
02615 {
02616   __IO uint8_t tmpreg = 0U;
02617
02618   /* Read data register to flush CRC */
02619   tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
02620
02621   /* To avoid GCC warning */
02622
02623   UNUSED(tmpreg);
02624
02625    /* Disable RXNE interrupt */
02626   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02627
02628   if(hspi->TxXferCount == 0U)
02629   {
02630     SPI_CloseRxTx_ISR(hspi);
02631   }
02632 }
02633 #endif /* USE_SPI_CRC */
02634
02635 /**
02636   * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
02637   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02638   *               the configuration information for SPI module.
02639   * @retval None
02640   */
02641 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02642 {
02643   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
02644   hspi->TxXferCount--;
02645
02646   /* check the end of the transmission */
02647   if(hspi->TxXferCount == 0U)
02648   {
02649 #if (USE_SPI_CRC != 0U)
02650     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02651     {
02652       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02653       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
02654       return;
02655     }
02656 #endif /* USE_SPI_CRC */
02657
02658     /* Disable TXE interrupt */
02659     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
02660
02661     if(hspi->RxXferCount == 0U)
02662     {
02663       SPI_CloseRxTx_ISR(hspi);
02664     }
02665   }
02666 }
02667
02668 /**
02669   * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
02670   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02671   *               the configuration information for SPI module.
02672   * @retval None
02673   */
02674 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02675 {
02676   /* Receive data in 16 Bit mode */
02677   *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
02678   hspi->pRxBuffPtr += sizeof(uint16_t);
02679   hspi->RxXferCount--;
02680
02681   if(hspi->RxXferCount == 0U)
02682   {
02683 #if (USE_SPI_CRC != 0U)
02684     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02685     {
02686       hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
02687       return;
02688     }
02689 #endif /* USE_SPI_CRC */
02690
02691     /* Disable RXNE interrupt */
02692     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02693
02694     if(hspi->TxXferCount == 0U)
02695     {
02696       SPI_CloseRxTx_ISR(hspi);
02697     }
02698   }
02699 }
02700
02701 #if (USE_SPI_CRC != 0U)
02702 /**
02703   * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
02704   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02705   *               the configuration information for SPI module.
02706   * @retval None
02707   */
02708 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
02709 {
02710   /* Receive data in 16 Bit mode */
02711   __IO uint16_t tmpreg = 0U;
02712
02713   /* Read data register to flush CRC */
02714   tmpreg = hspi->Instance->DR;
02715
02716   /* To avoid GCC warning */
02717   UNUSED(tmpreg);
02718
02719   /* Disable RXNE interrupt */
02720   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
02721
02722   SPI_CloseRxTx_ISR(hspi);
02723 }
02724 #endif /* USE_SPI_CRC */
02725
02726 /**
02727   * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
02728   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02729   *               the configuration information for SPI module.
02730   * @retval None
02731   */
02732 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02733 {
02734   /* Transmit data in 16 Bit mode */
02735   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
02736   hspi->pTxBuffPtr += sizeof(uint16_t);
02737   hspi->TxXferCount--;
02738
02739   /* Enable CRC Transmission */
02740   if(hspi->TxXferCount == 0U)
02741   {
02742 #if (USE_SPI_CRC != 0U)
02743     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02744     {
02745       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02746       __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
02747       return;
02748     }
02749 #endif /* USE_SPI_CRC */
02750
02751     /* Disable TXE interrupt */
02752     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
02753
02754     if(hspi->RxXferCount == 0U)
02755     {
02756       SPI_CloseRxTx_ISR(hspi);
02757     }
02758   }
02759 }
02760
02761 #if (USE_SPI_CRC != 0U)
02762 /**
02763   * @brief  Manage the CRC 8-bit receive in Interrupt context.
02764   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02765   *               the configuration information for SPI module.
02766   * @retval None
02767   */
02768 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
02769 {
02770   __IO uint8_t tmpreg = 0U;
02771
02772   /* Read data register to flush CRC */
02773   tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
02774
02775   /* To avoid GCC warning */
02776   UNUSED(tmpreg);
02777
02778   SPI_CloseRx_ISR(hspi);
02779 }
02780 #endif /* USE_SPI_CRC */
02781
02782 /**
02783   * @brief  Manage the receive 8-bit in Interrupt context.
02784   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02785   *               the configuration information for SPI module.
02786   * @retval None
02787   */
02788 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02789 {
02790   *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
02791   hspi->RxXferCount--;
02792
02793 #if (USE_SPI_CRC != 0U)
02794   /* Enable CRC Transmission */
02795   if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
02796   {
02797     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02798   }
02799 #endif /* USE_SPI_CRC */
02800
02801   if(hspi->RxXferCount == 0U)
02802   {
02803 #if (USE_SPI_CRC != 0U)
02804     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02805     {
02806       hspi->RxISR =  SPI_RxISR_8BITCRC;
02807       return;
02808     }
02809 #endif /* USE_SPI_CRC */
02810     SPI_CloseRx_ISR(hspi);
02811   }
02812 }
02813
02814 #if (USE_SPI_CRC != 0U)
02815 /**
02816   * @brief  Manage the CRC 16-bit receive in Interrupt context.
02817   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02818   *               the configuration information for SPI module.
02819   * @retval None
02820   */
02821 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
02822 {
02823   __IO uint16_t tmpreg = 0U;
02824
02825   /* Read data register to flush CRC */
02826   tmpreg = hspi->Instance->DR;
02827
02828   /* To avoid GCC warning */
02829   UNUSED(tmpreg);
02830
02831   /* Disable RXNE and ERR interrupt */
02832   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
02833
02834   SPI_CloseRx_ISR(hspi);
02835 }
02836 #endif /* USE_SPI_CRC */
02837
02838 /**
02839   * @brief  Manage the 16-bit receive in Interrupt context.
02840   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02841   *               the configuration information for SPI module.
02842   * @retval None
02843   */
02844 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02845 {
02846   *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
02847   hspi->pRxBuffPtr += sizeof(uint16_t);
02848   hspi->RxXferCount--;
02849
02850 #if (USE_SPI_CRC != 0U)
02851   /* Enable CRC Transmission */
02852   if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
02853   {
02854     SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02855   }
02856 #endif /* USE_SPI_CRC */
02857
02858   if(hspi->RxXferCount == 0U)
02859   {
02860 #if (USE_SPI_CRC != 0U)
02861     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02862     {
02863       hspi->RxISR = SPI_RxISR_16BITCRC;
02864       return;
02865     }
02866 #endif /* USE_SPI_CRC */
02867     SPI_CloseRx_ISR(hspi);
02868   }
02869 }
02870
02871 /**
02872   * @brief  Handle the data 8-bit transmit in Interrupt mode.
02873   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02874   *               the configuration information for SPI module.
02875   * @retval None
02876   */
02877 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
02878 {
02879   *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
02880   hspi->TxXferCount--;
02881
02882   if(hspi->TxXferCount == 0U)
02883   {
02884 #if (USE_SPI_CRC != 0U)
02885     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02886     {
02887       /* Enable CRC Transmission */
02888       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02889     }
02890 #endif /* USE_SPI_CRC */
02891     SPI_CloseTx_ISR(hspi);
02892   }
02893 }
02894
02895 /**
02896   * @brief  Handle the data 16-bit transmit in Interrupt mode.
02897   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02898   *               the configuration information for SPI module.
02899   * @retval None
02900   */
02901 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
02902 {
02903   /* Transmit data in 16 Bit mode */
02904   hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
02905   hspi->pTxBuffPtr += sizeof(uint16_t);
02906   hspi->TxXferCount--;
02907
02908   if(hspi->TxXferCount == 0U)
02909   {
02910 #if (USE_SPI_CRC != 0U)
02911     if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02912     {
02913       /* Enable CRC Transmission */
02914       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
02915     }
02916 #endif /* USE_SPI_CRC */
02917     SPI_CloseTx_ISR(hspi);
02918   }
02919 }
02920
02921 /**
02922   * @brief Handle SPI Communication Timeout.
02923   * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
02924   *              the configuration information for SPI module.
02925   * @param Flag: SPI flag to check
02926   * @param State: flag state to check
02927   * @param Timeout: Timeout duration
02928   * @param Tickstart: tick start value
02929   * @retval HAL status
02930   */
02931 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
02932 {
02933   while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State)
02934   {
02935     if(Timeout != HAL_MAX_DELAY)
02936     {
02937       if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
02938       {
02939         /* Disable the SPI and reset the CRC: the CRC value should be cleared
02940         on both master and slave sides in order to resynchronize the master
02941         and slave for their respective CRC calculation */
02942
02943         /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
02944         __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
02945
02946         if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
02947         {
02948           /* Disable SPI peripheral */
02949           __HAL_SPI_DISABLE(hspi);
02950         }
02951
02952         /* Reset CRC Calculation */
02953         if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
02954         {
02955           SPI_RESET_CRC(hspi);
02956         }
02957
02958         hspi->State= HAL_SPI_STATE_READY;
02959
02960         /* Process Unlocked */
02961         __HAL_UNLOCK(hspi);
02962
02963         return HAL_TIMEOUT;
02964       }
02965     }
02966   }
02967
02968   return HAL_OK;
02969 }
02970 /**
02971   * @brief Handle to check BSY flag before start a new transaction.
02972   * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
02973   *              the configuration information for SPI module.
02974   * @param Timeout: Timeout duration
02975   * @param Tickstart: tick start value
02976   * @retval HAL status
02977   */
02978 static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
02979 {
02980   /* Control the BSY flag */
02981   if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
02982   {
02983     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
02984     return HAL_TIMEOUT;
02985   }
02986   return HAL_OK;
02987 }
02988
02989 /**
02990   * @brief  Handle the end of the RXTX transaction.
02991   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
02992   *               the configuration information for SPI module.
02993   * @retval None
02994   */
02995 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
02996 {
02997   uint32_t tickstart = 0U;
02998   __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
02999   /* Init tickstart for timeout managment*/
03000   tickstart = HAL_GetTick();
03001
03002   /* Disable ERR interrupt */
03003   __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
03004
03005   /* Wait until TXE flag is set */
03006   do
03007   {
03008     if(count-- == 0U)
03009     {
03010       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03011       break;
03012     }
03013   }
03014   while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
03015
03016   /* Check the end of the transaction */
03017   if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
03018   {
03019     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03020   }
03021
03022   /* Clear overrun flag in 2 Lines communication mode because received is not read */
03023   if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
03024   {
03025     __HAL_SPI_CLEAR_OVRFLAG(hspi);
03026   }
03027
03028 #if (USE_SPI_CRC != 0U)
03029   /* Check if CRC error occurred */
03030   if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
03031   {
03032     /* Check if CRC error is valid or not (workaround to be applied or not) */
03033     if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
03034     {
03035       hspi->State = HAL_SPI_STATE_READY;
03036       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03037
03038       /* Reset CRC Calculation */
03039       SPI_RESET_CRC(hspi);
03040
03041     HAL_SPI_ErrorCallback(hspi);
03042     }
03043     else
03044     {
03045       __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03046     }
03047   }
03048   else
03049   {
03050 #endif /* USE_SPI_CRC */
03051     if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
03052     {
03053       if(hspi->State == HAL_SPI_STATE_BUSY_RX)
03054       {
03055         hspi->State = HAL_SPI_STATE_READY;
03056         HAL_SPI_RxCpltCallback(hspi);
03057       }
03058       else
03059       {
03060         hspi->State = HAL_SPI_STATE_READY;
03061         HAL_SPI_TxRxCpltCallback(hspi);
03062       }
03063     }
03064     else
03065     {
03066       hspi->State = HAL_SPI_STATE_READY;
03067       HAL_SPI_ErrorCallback(hspi);
03068     }
03069 #if (USE_SPI_CRC != 0U)
03070   }
03071 #endif /* USE_SPI_CRC */
03072 }
03073
03074 /**
03075   * @brief  Handle the end of the RX transaction.
03076   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03077   *               the configuration information for SPI module.
03078   * @retval None
03079   */
03080 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
03081 {
03082     /* Disable RXNE and ERR interrupt */
03083     __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
03084
03085     /* Check the end of the transaction */
03086     if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
03087     {
03088       /* Disable SPI peripheral */
03089       __HAL_SPI_DISABLE(hspi);
03090     }
03091
03092     /* Clear overrun flag in 2 Lines communication mode because received is not read */
03093     if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
03094     {
03095       __HAL_SPI_CLEAR_OVRFLAG(hspi);
03096     }
03097     hspi->State = HAL_SPI_STATE_READY;
03098
03099 #if (USE_SPI_CRC != 0U)
03100     /* Check if CRC error occurred */
03101     if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
03102     {
03103       /* Check if CRC error is valid or not (workaround to be applied or not) */
03104       if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
03105       {
03106         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
03107
03108         /* Reset CRC Calculation */
03109         SPI_RESET_CRC(hspi);
03110
03111          HAL_SPI_ErrorCallback(hspi);
03112       }
03113       else
03114       {
03115         __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
03116       }
03117     }
03118     else
03119     {
03120 #endif /* USE_SPI_CRC */
03121       if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
03122       {
03123         HAL_SPI_RxCpltCallback(hspi);
03124       }
03125       else
03126       {
03127         HAL_SPI_ErrorCallback(hspi);
03128       }
03129 #if (USE_SPI_CRC != 0U)
03130     }
03131 #endif /* USE_SPI_CRC */
03132 }
03133
03134 /**
03135   * @brief  Handle the end of the TX transaction.
03136   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03137   *               the configuration information for SPI module.
03138   * @retval None
03139   */
03140 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
03141 {
03142   uint32_t tickstart = 0U;
03143   __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
03144
03145   /* Init tickstart for timeout management*/
03146   tickstart = HAL_GetTick();
03147
03148   /* Wait until TXE flag is set */
03149   do
03150   {
03151     if(count-- == 0U)
03152     {
03153       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03154       break;
03155     }
03156   }
03157   while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
03158
03159   /* Disable TXE and ERR interrupt */
03160   __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
03161
03162   /* Check Busy flag */
03163   if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
03164   {
03165     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03166   }
03167
03168   /* Clear overrun flag in 2 Lines communication mode because received is not read */
03169   if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
03170   {
03171     __HAL_SPI_CLEAR_OVRFLAG(hspi);
03172   }
03173
03174   hspi->State = HAL_SPI_STATE_READY;
03175   if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
03176   {
03177     HAL_SPI_ErrorCallback(hspi);
03178   }
03179   else
03180   {
03181     HAL_SPI_TxCpltCallback(hspi);
03182   }
03183 }
03184
03185 /**
03186   * @}
03187   */
03188
03189 /**
03190   * @brief  Handle abort a Tx or Rx transaction.
03191   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03192   *               the configuration information for SPI module.
03193   * @retval None
03194   */
03195 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
03196 {
03197   __IO uint32_t tmpreg = 0U;
03198   __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
03199
03200   /* Wait until TXE flag is set */
03201   do
03202   {
03203     if(count-- == 0U)
03204     {
03205       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
03206       break;
03207     }
03208   }
03209   while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
03210
03211   /* Disable SPI Peripheral */
03212   __HAL_SPI_DISABLE(hspi);
03213
03214   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
03215   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
03216
03217   /* Flush DR Register */
03218   tmpreg = (*(__IO uint32_t *)&hspi->Instance->DR);
03219
03220   /* To avoid GCC warning */
03221   UNUSED(tmpreg);
03222 }
03223
03224 /**
03225   * @brief  Handle abort a Tx or Rx transaction.
03226   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03227   *               the configuration information for SPI module.
03228   * @retval None
03229   */
03230 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
03231 {
03232   /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
03233   CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
03234
03235   /* Disable SPI Peripheral */
03236   __HAL_SPI_DISABLE(hspi);
03237 }
03238
03239 /**
03240   * @brief  Checks if encountered CRC error could be corresponding to wrongly detected errors
03241   *         according to SPI instance, Device type, and revision ID.
03242   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
03243   *               the configuration information for SPI module.
03244   * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
03245 */
03246 __weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
03247 {
03248   return (SPI_VALID_CRC_ERROR);
03249 }
03250 /**
03251   * @}
03252   */
03253 #endif /* HAL_SPI_MODULE_ENABLED */
03254
03255 /**
03256   * @}
03257   */
03258
03259 /**
03260   * @}
03261   */
03262
03263 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_spi.h Source File

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stm32f1xx_hal_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_spi.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of SPI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_SPI_H
00040 #define __STM32F1xx_HAL_SPI_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup SPI
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup SPI_Exported_Types SPI Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  SPI Configuration Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Mode;               /*!< Specifies the SPI operating mode.
00068                                     This parameter can be a value of @ref SPI_Mode */
00069
00070   uint32_t Direction;          /*!< Specifies the SPI Directional mode state.
00071                                     This parameter can be a value of @ref SPI_Direction */
00072
00073   uint32_t DataSize;           /*!< Specifies the SPI data size.
00074                                     This parameter can be a value of @ref SPI_Data_Size */
00075
00076   uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.
00077                                     This parameter can be a value of @ref SPI_Clock_Polarity */
00078
00079   uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.
00080                                     This parameter can be a value of @ref SPI_Clock_Phase */
00081
00082   uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by
00083                                     hardware (NSS pin) or by software using the SSI bit.
00084                                     This parameter can be a value of @ref SPI_Slave_Select_management */
00085
00086   uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be
00087                                     used to configure the transmit and receive SCK clock.
00088                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
00089                                     @note The communication clock is derived from the master
00090                                      clock. The slave clock does not need to be set. */
00091
00092   uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.
00093                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
00094
00095   uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.
00096                                     This parameter can be a value of @ref SPI_TI_mode */
00097
00098   uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.
00099                                     This parameter can be a value of @ref SPI_CRC_Calculation */
00100
00101   uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.
00102                                     This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
00103 }SPI_InitTypeDef;
00104
00105 /**
00106   * @brief  HAL SPI State structure definition
00107   */
00108 typedef enum
00109 {
00110   HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
00111   HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
00112   HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
00113   HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
00114   HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
00115   HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
00116   HAL_SPI_STATE_ERROR      = 0x06U     /*!< SPI error state                                    */
00117 }HAL_SPI_StateTypeDef;
00118
00119 /**
00120   * @brief  SPI handle Structure definition
00121   */
00122 typedef struct __SPI_HandleTypeDef
00123 {
00124   SPI_TypeDef                *Instance;    /*!< SPI registers base address */
00125
00126   SPI_InitTypeDef            Init;         /*!< SPI communication parameters */
00127
00128   uint8_t                    *pTxBuffPtr;  /*!< Pointer to SPI Tx transfer Buffer */
00129
00130   uint16_t                   TxXferSize;   /*!< SPI Tx Transfer size */
00131
00132   __IO uint16_t              TxXferCount;  /*!< SPI Tx Transfer Counter */
00133
00134   uint8_t                    *pRxBuffPtr;  /*!< Pointer to SPI Rx transfer Buffer */
00135
00136   uint16_t                   RxXferSize;   /*!< SPI Rx Transfer size */
00137
00138   __IO uint16_t              RxXferCount;  /*!< SPI Rx Transfer Counter */
00139
00140   void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */
00141
00142   void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */
00143
00144   DMA_HandleTypeDef          *hdmatx;      /*!< SPI Tx DMA Handle parameters   */
00145
00146   DMA_HandleTypeDef          *hdmarx;      /*!< SPI Rx DMA Handle parameters   */
00147
00148   HAL_LockTypeDef            Lock;         /*!< Locking object                 */
00149
00150   __IO HAL_SPI_StateTypeDef  State;        /*!< SPI communication state */
00151
00152   __IO uint32_t              ErrorCode;    /*!< SPI Error code */
00153
00154 }SPI_HandleTypeDef;
00155
00156 /**
00157   * @}
00158   */
00159
00160 /* Exported constants --------------------------------------------------------*/
00161 /** @defgroup SPI_Exported_Constants SPI Exported Constants
00162   * @{
00163   */
00164
00165 /** @defgroup SPI_Error_Code SPI Error Code
00166   * @{
00167   */
00168 #define HAL_SPI_ERROR_NONE              0x00000000U   /*!< No error             */
00169 #define HAL_SPI_ERROR_MODF              0x00000001U   /*!< MODF error           */
00170 #define HAL_SPI_ERROR_CRC               0x00000002U   /*!< CRC error            */
00171 #define HAL_SPI_ERROR_OVR               0x00000004U   /*!< OVR error            */
00172 #define HAL_SPI_ERROR_FRE               0x00000008U   /*!< FRE error            */
00173 #define HAL_SPI_ERROR_DMA               0x00000010U   /*!< DMA transfer error   */
00174 #define HAL_SPI_ERROR_FLAG              0x00000020U   /*!< Flag: RXNE,TXE, BSY  */
00175 /**
00176   * @}
00177   */
00178
00179 /** @defgroup SPI_Mode SPI Mode
00180   * @{
00181   */
00182 #define SPI_MODE_SLAVE                  0x00000000U
00183 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup SPI_Direction SPI Direction Mode
00189   * @{
00190   */
00191 #define SPI_DIRECTION_2LINES            0x00000000U
00192 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
00193 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup SPI_Data_Size SPI Data Size
00199   * @{
00200   */
00201 #define SPI_DATASIZE_8BIT               0x00000000U
00202 #define SPI_DATASIZE_16BIT              SPI_CR1_DFF
00203 /**
00204   * @}
00205   */
00206
00207 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
00208   * @{
00209   */
00210 #define SPI_POLARITY_LOW                0x00000000U
00211 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
00212 /**
00213   * @}
00214   */
00215
00216 /** @defgroup SPI_Clock_Phase SPI Clock Phase
00217   * @{
00218   */
00219 #define SPI_PHASE_1EDGE                 0x00000000U
00220 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
00221 /**
00222   * @}
00223   */
00224
00225 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
00226   * @{
00227   */
00228 #define SPI_NSS_SOFT                    SPI_CR1_SSM
00229 #define SPI_NSS_HARD_INPUT              0x00000000U
00230 #define SPI_NSS_HARD_OUTPUT             ((uint32_t)(SPI_CR2_SSOE << 16))
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
00236   * @{
00237   */
00238 #define SPI_BAUDRATEPRESCALER_2         0x00000000U
00239 #define SPI_BAUDRATEPRESCALER_4         SPI_CR1_BR_0
00240 #define SPI_BAUDRATEPRESCALER_8         SPI_CR1_BR_1
00241 #define SPI_BAUDRATEPRESCALER_16        (uint32_t)(SPI_CR1_BR_1 | SPI_CR1_BR_0)
00242 #define SPI_BAUDRATEPRESCALER_32        SPI_CR1_BR_2
00243 #define SPI_BAUDRATEPRESCALER_64        (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_0)
00244 #define SPI_BAUDRATEPRESCALER_128       (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1)
00245 #define SPI_BAUDRATEPRESCALER_256       (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
00246
00247 /**
00248   * @}
00249   */
00250
00251 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
00252   * @{
00253   */
00254 #define SPI_FIRSTBIT_MSB                0x00000000U
00255 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup SPI_TI_mode SPI TI Mode
00261   * @{
00262   */
00263 #define SPI_TIMODE_DISABLE             0x00000000U
00264 /**
00265   * @}
00266   */
00267
00268 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
00269   * @{
00270   */
00271 #define SPI_CRCCALCULATION_DISABLE     0x00000000U
00272 #define SPI_CRCCALCULATION_ENABLE      SPI_CR1_CRCEN
00273 /**
00274   * @}
00275   */
00276
00277 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
00278   * @{
00279   */
00280 #define SPI_IT_TXE                      SPI_CR2_TXEIE
00281 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
00282 #define SPI_IT_ERR                      SPI_CR2_ERRIE
00283 /**
00284   * @}
00285   */
00286
00287 /** @defgroup SPI_Flags_definition SPI Flags Definition
00288   * @{
00289   */
00290 #define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */
00291 #define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */
00292 #define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */
00293 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
00294 #define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */
00295 #define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */
00296 /**
00297   * @}
00298   */
00299
00300 /**
00301   * @}
00302   */
00303
00304 /* Exported macro ------------------------------------------------------------*/
00305 /** @defgroup SPI_Exported_Macros SPI Exported Macros
00306   * @{
00307   */
00308
00309 /** @brief  Reset SPI handle state.
00310   * @param  __HANDLE__: specifies the SPI Handle.
00311   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00312   * @retval None
00313   */
00314 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
00315
00316 /** @brief  Enable the specified SPI interrupts.
00317   * @param  __HANDLE__: specifies the SPI handle.
00318   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00319   * @param  __INTERRUPT__: specifies the interrupt source to enable.
00320   *         This parameter can be one of the following values:
00321   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00322   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00323   *            @arg SPI_IT_ERR: Error interrupt enable
00324   * @retval None
00325   */
00326 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
00327
00328 /** @brief  Disable the specified SPI interrupts.
00329   * @param  __HANDLE__: specifies the SPI handle.
00330   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00331   * @param  __INTERRUPT__: specifies the interrupt source to disable.
00332   *         This parameter can be one of the following values:
00333   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00334   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00335   *            @arg SPI_IT_ERR: Error interrupt enable
00336   * @retval None
00337   */
00338 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
00339
00340 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
00341   * @param  __HANDLE__: specifies the SPI Handle.
00342   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00343   * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
00344   *          This parameter can be one of the following values:
00345   *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable
00346   *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
00347   *             @arg SPI_IT_ERR: Error interrupt enable
00348   * @retval The new state of __IT__ (TRUE or FALSE).
00349   */
00350 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
00351
00352 /** @brief  Check whether the specified SPI flag is set or not.
00353   * @param  __HANDLE__: specifies the SPI Handle.
00354   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00355   * @param  __FLAG__: specifies the flag to check.
00356   *         This parameter can be one of the following values:
00357   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
00358   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
00359   *            @arg SPI_FLAG_CRCERR: CRC error flag
00360   *            @arg SPI_FLAG_MODF: Mode fault flag
00361   *            @arg SPI_FLAG_OVR: Overrun flag
00362   *            @arg SPI_FLAG_BSY: Busy flag
00363   * @retval The new state of __FLAG__ (TRUE or FALSE).
00364   */
00365 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
00366
00367 /** @brief  Clear the SPI CRCERR pending flag.
00368   * @param  __HANDLE__: specifies the SPI Handle.
00369   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00370   * @retval None
00371   */
00372 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
00373
00374 /** @brief  Clear the SPI MODF pending flag.
00375   * @param  __HANDLE__: specifies the SPI Handle.
00376   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00377   * @retval None
00378   */
00379 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)       \
00380 do{                                                \
00381     __IO uint32_t tmpreg_modf = 0x00U;             \
00382     tmpreg_modf = (__HANDLE__)->Instance->SR;      \
00383     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
00384     UNUSED(tmpreg_modf);                           \
00385   } while(0U)
00386
00387 /** @brief  Clear the SPI OVR pending flag.
00388   * @param  __HANDLE__: specifies the SPI Handle.
00389   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00390   * @retval None
00391   */
00392 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
00393 do{                                                \
00394     __IO uint32_t tmpreg_ovr = 0x00U;              \
00395     tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
00396     tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
00397     UNUSED(tmpreg_ovr);                            \
00398   } while(0U)
00399
00400
00401 /** @brief  Enable the SPI peripheral.
00402   * @param  __HANDLE__: specifies the SPI Handle.
00403   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00404   * @retval None
00405   */
00406 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
00407
00408 /** @brief  Disable the SPI peripheral.
00409   * @param  __HANDLE__: specifies the SPI Handle.
00410   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00411   * @retval None
00412   */
00413 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
00414 /**
00415   * @}
00416   */
00417
00418 /* Exported functions --------------------------------------------------------*/
00419 /** @addtogroup SPI_Exported_Functions
00420   * @{
00421   */
00422
00423 /** @addtogroup SPI_Exported_Functions_Group1
00424   * @{
00425   */
00426 /* Initialization/de-initialization functions  **********************************/
00427 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
00428 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
00429 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
00430 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
00431 /**
00432   * @}
00433   */
00434
00435 /** @addtogroup SPI_Exported_Functions_Group2
00436   * @{
00437   */
00438 /* I/O operation functions  *****************************************************/
00439 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00440 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00441 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00442 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00443 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00444 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00445 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00446 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
00447 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00448 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
00449 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
00450 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
00451 /* Transfer Abort functions */
00452 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
00453 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
00454
00455 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
00456 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
00457 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
00458 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
00459 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00460 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00461 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
00462 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
00463 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
00464 /**
00465   * @}
00466   */
00467
00468 /** @addtogroup SPI_Exported_Functions_Group3
00469   * @{
00470   */
00471 /* Peripheral State and Error functions ***************************************/
00472 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
00473 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
00474 /**
00475   * @}
00476   */
00477
00478 /**
00479   * @}
00480   */
00481
00482 /* Private types -------------------------------------------------------------*/
00483 /* Private variables ---------------------------------------------------------*/
00484 /* Private constants ---------------------------------------------------------*/
00485 /** @defgroup SPI_Private_Constants SPI Private Constants
00486   * @{
00487   */
00488 #define SPI_INVALID_CRC_ERROR     0U          /* CRC error wrongly detected */
00489 #define SPI_VALID_CRC_ERROR       1U          /* CRC error is true */
00490 /**
00491   * @}
00492   */
00493 /* Private macros ------------------------------------------------------------*/
00494 /** @defgroup SPI_Private_Macros SPI Private Macros
00495   * @{
00496   */
00497
00498 /** @brief  Set the SPI transmit-only mode.
00499   * @param  __HANDLE__: specifies the SPI Handle.
00500   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00501   * @retval None
00502   */
00503 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
00504
00505 /** @brief  Set the SPI receive-only mode.
00506   * @param  __HANDLE__: specifies the SPI Handle.
00507   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00508   * @retval None
00509   */
00510 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
00511
00512 /** @brief  Reset the CRC calculation of the SPI.
00513   * @param  __HANDLE__: specifies the SPI Handle.
00514   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
00515   * @retval None
00516   */
00517 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
00518                                      (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
00519
00520 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
00521                            ((MODE) == SPI_MODE_MASTER))
00522
00523 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
00524                                 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
00525                                 ((MODE) == SPI_DIRECTION_1LINE))
00526
00527 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
00528
00529 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)  || \
00530                                                 ((MODE) == SPI_DIRECTION_1LINE))
00531
00532 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
00533                                    ((DATASIZE) == SPI_DATASIZE_8BIT))
00534
00535 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
00536                            ((CPOL) == SPI_POLARITY_HIGH))
00537
00538 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
00539                            ((CPHA) == SPI_PHASE_2EDGE))
00540
00541 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
00542                          ((NSS) == SPI_NSS_HARD_INPUT) || \
00543                          ((NSS) == SPI_NSS_HARD_OUTPUT))
00544
00545 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
00546                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
00547                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
00548                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
00549                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
00550                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
00551                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
00552                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
00553
00554 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
00555                                ((BIT) == SPI_FIRSTBIT_LSB))
00556
00557 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
00558                                              ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
00559
00560 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
00561
00562 /**
00563   * @}
00564   */
00565
00566 /* Private functions ---------------------------------------------------------*/
00567 /** @defgroup SPI_Private_Functions SPI Private Functions
00568   * @{
00569   */
00570 uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
00571 /**
00572   * @}
00573   */
00574
00575 /**
00576   * @}
00577   */
00578
00579 /**
00580   * @}
00581   */
00582
00583 #ifdef __cplusplus
00584 }
00585 #endif
00586
00587 #endif /* __STM32F1xx_HAL_SPI_H */
00588
00589 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_spi_ex.c Source File

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stm32f1xx_hal_spi_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_spi_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Extended SPI HAL module driver.
00008   *
00009   *          This file provides firmware functions to manage the following
00010   *          functionalities SPI extension peripheral:
00011   *           + Extended Peripheral Control functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00017   *
00018   * Redistribution and use in source and binary forms, with or without modification,
00019   * are permitted provided that the following conditions are met:
00020   *   1. Redistributions of source code must retain the above copyright notice,
00021   *      this list of conditions and the following disclaimer.
00022   *   2. Redistributions in binary form must reproduce the above copyright notice,
00023   *      this list of conditions and the following disclaimer in the documentation
00024   *      and/or other materials provided with the distribution.
00025   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00026   *      may be used to endorse or promote products derived from this software
00027   *      without specific prior written permission.
00028   *
00029   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00031   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00032   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00033   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00034   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00035   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00036   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00037   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00038   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039   *
00040   ******************************************************************************
00041   */
00042
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32f1xx_hal.h"
00045
00046 /** @addtogroup STM32F1xx_HAL_Driver
00047   * @{
00048   */
00049
00050 /** @addtogroup SPI
00051   * @{
00052   */
00053 #ifdef HAL_SPI_MODULE_ENABLED
00054
00055 /** @defgroup SPI_Private_Variables SPI Private Variables
00056   * @{
00057   */
00058 #if (USE_SPI_CRC != 0U)
00059 /* Variable used to determine if device is impacted by implementation of workaround
00060    related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
00061     - STM32F101CDE/STM32F103CDE
00062     - Revision ID : Z
00063     - SPI2
00064     - In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
00065       the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
00066         + If the value is 0, the complete data transfer is successful.
00067         + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
00068       If CRCERR is found reset, the complete data transfer is considered successful.
00069 */
00070 uint8_t uCRCErrorWorkaroundCheck = 0U;
00071 #endif /* USE_SPI_CRC */
00072 /**
00073   * @}
00074   */
00075
00076
00077 /* Private typedef -----------------------------------------------------------*/
00078 /* Private define ------------------------------------------------------------*/
00079 /* Private macro -------------------------------------------------------------*/
00080 /* Private variables ---------------------------------------------------------*/
00081 /* Private function prototypes -----------------------------------------------*/
00082 /* Private functions ---------------------------------------------------------*/
00083
00084 /** @addtogroup SPI_Exported_Functions
00085   * @{
00086   */
00087
00088 /** @addtogroup SPI_Exported_Functions_Group1
00089   *
00090   * @{
00091   */
00092
00093 /**
00094   * @brief  Initializes the SPI according to the specified parameters
00095   *         in the SPI_InitTypeDef and create the associated handle.
00096   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00097   *                the configuration information for SPI module.
00098   * @retval HAL status
00099   */
00100 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
00101 {
00102   /* Check the SPI handle allocation */
00103   if(hspi == NULL)
00104   {
00105     return HAL_ERROR;
00106   }
00107
00108   /* Check the parameters */
00109   assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
00110   assert_param(IS_SPI_MODE(hspi->Init.Mode));
00111   assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
00112   assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
00113   assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
00114   assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
00115   assert_param(IS_SPI_NSS(hspi->Init.NSS));
00116   assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
00117   assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
00118
00119 #if (USE_SPI_CRC != 0U)
00120   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
00121   if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
00122   {
00123     assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
00124   }
00125 #else
00126   hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
00127 #endif /* USE_SPI_CRC */
00128
00129   if(hspi->State == HAL_SPI_STATE_RESET)
00130   {
00131     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
00132     HAL_SPI_MspInit(hspi);
00133   }
00134
00135   hspi->State = HAL_SPI_STATE_BUSY;
00136
00137   /* Disble the selected SPI peripheral */
00138   __HAL_SPI_DISABLE(hspi);
00139
00140   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
00141   /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
00142   Communication speed, First bit and CRC calculation state */
00143   WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
00144                                   hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
00145                                   hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation) );
00146
00147   /* Configure : NSS management */
00148   WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
00149
00150   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
00151   /* Configure : CRC Polynomial */
00152   WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
00153
00154 #if defined(SPI_I2SCFGR_I2SMOD)
00155   /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
00156   CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00157 #endif /* SPI_I2SCFGR_I2SMOD */
00158
00159 #if (USE_SPI_CRC != 0U)
00160 #if defined (STM32F101xE) || defined (STM32F103xE)
00161   /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
00162      CRC errors wrongly detected */
00163   /* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
00164      Revision ID information is only available in Debug mode, so Workaround could not be implemented
00165      to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
00166      So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
00167   uCRCErrorWorkaroundCheck = 0U;
00168 #else
00169   uCRCErrorWorkaroundCheck = 0U;
00170 #endif /* STM32F101xE || STM32F103xE */
00171 #endif /* USE_SPI_CRC */
00172
00173   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
00174   hspi->State = HAL_SPI_STATE_READY;
00175
00176   return HAL_OK;
00177 }
00178
00179 /**
00180   * @}
00181   */
00182
00183 /**
00184   * @}
00185   */
00186
00187 /** @addtogroup SPI_Private_Functions
00188   * @{
00189   */
00190 #if (USE_SPI_CRC != 0U)
00191 /**
00192   * @brief  Checks if encountered CRC error could be corresponding to wrongly detected errors
00193   *         according to SPI instance, Device type, and revision ID.
00194   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
00195   *               the configuration information for SPI module.
00196   * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
00197 */
00198 uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
00199 {
00200 #if defined (STM32F101xE) || defined (STM32F103xE)
00201   /* Check how to handle this CRC error (workaround to be applied or not) */
00202   /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
00203   if ( (uCRCErrorWorkaroundCheck != 0U) && (hspi->Instance == SPI2) )
00204   {
00205     if (hspi->Instance->RXCRCR == 0U)
00206     {
00207       return (SPI_INVALID_CRC_ERROR);
00208     }
00209   }
00210   return (SPI_VALID_CRC_ERROR);
00211 #else
00212   return (SPI_VALID_CRC_ERROR);
00213 #endif
00214 }
00215 #endif /* USE_SPI_CRC */
00216
00217 /**
00218   * @}
00219   */
00220
00221 #endif /* HAL_SPI_MODULE_ENABLED */
00222 /**
00223   * @}
00224   */
00225
00226 /**
00227   * @}
00228   */
00229
00230 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_sram.c Source File

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stm32f1xx_hal_sram.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_sram.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   SRAM HAL module driver.
00008   *          This file provides a generic firmware to drive SRAM memories
00009   *          mounted as external device.
00010   *
00011   @verbatim
00012   ==============================================================================
00013                           ##### How to use this driver #####
00014   ==============================================================================
00015   [..]
00016     This driver is a generic layered driver which contains a set of APIs used to
00017     control SRAM memories. It uses the FSMC layer functions to interface
00018     with SRAM devices.
00019     The following sequence should be followed to configure the FSMC to interface
00020     with SRAM/PSRAM memories:
00021
00022    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
00023           SRAM_HandleTypeDef  hsram; and:
00024
00025        (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
00026             values of the structure member.
00027
00028        (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
00029             base register instance for NOR or SRAM device
00030
00031        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
00032             base register instance for NOR or SRAM extended mode
00033
00034    (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended
00035        mode timings; for example:
00036           FSMC_NORSRAM_TimingTypeDef  Timing and FSMC_NORSRAM_TimingTypeDef  ExTiming;
00037       and fill its fields with the allowed values of the structure member.
00038
00039    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
00040        performs the following sequence:
00041
00042        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
00043        (##) Control register configuration using the FSMC NORSRAM interface function
00044             FSMC_NORSRAM_Init()
00045        (##) Timing register configuration using the FSMC NORSRAM interface function
00046             FSMC_NORSRAM_Timing_Init()
00047        (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function
00048             FSMC_NORSRAM_Extended_Timing_Init()
00049        (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()
00050
00051    (#) At this stage you can perform read/write accesses from/to the memory connected
00052        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
00053        following APIs:
00054        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
00055        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
00056
00057    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
00058        HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
00059
00060    (#) You can continuously monitor the SRAM device HAL state by calling the function
00061        HAL_SRAM_GetState()
00062
00063   @endverbatim
00064   ******************************************************************************
00065   * @attention
00066   *
00067   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00068   *
00069   * Redistribution and use in source and binary forms, with or without modification,
00070   * are permitted provided that the following conditions are met:
00071   *   1. Redistributions of source code must retain the above copyright notice,
00072   *      this list of conditions and the following disclaimer.
00073   *   2. Redistributions in binary form must reproduce the above copyright notice,
00074   *      this list of conditions and the following disclaimer in the documentation
00075   *      and/or other materials provided with the distribution.
00076   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00077   *      may be used to endorse or promote products derived from this software
00078   *      without specific prior written permission.
00079   *
00080   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00081   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00082   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00083   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00084   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00085   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00086   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00087   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00088   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00089   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00090   *
00091   ******************************************************************************
00092   */
00093
00094 /* Includes ------------------------------------------------------------------*/
00095 #include "stm32f1xx_hal.h"
00096
00097 /** @addtogroup STM32F1xx_HAL_Driver
00098   * @{
00099   */
00100
00101 #ifdef HAL_SRAM_MODULE_ENABLED
00102
00103 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
00104
00105 /** @defgroup SRAM SRAM
00106   * @brief SRAM driver modules
00107   * @{
00108   */
00109 /* Private typedef -----------------------------------------------------------*/
00110 /* Private define ------------------------------------------------------------*/
00111 /* Private macro -------------------------------------------------------------*/
00112 /* Private variables ---------------------------------------------------------*/
00113 /* Private function prototypes -----------------------------------------------*/
00114 /* Exported functions --------------------------------------------------------*/
00115
00116 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
00117   * @{
00118   */
00119
00120 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00121   * @brief    Initialization and Configuration functions.
00122   *
00123   @verbatim
00124   ==============================================================================
00125            ##### SRAM Initialization and de_initialization functions #####
00126   ==============================================================================
00127     [..]  This section provides functions allowing to initialize/de-initialize
00128           the SRAM memory
00129
00130 @endverbatim
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  Performs the SRAM device initialization sequence
00136   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00137   *                the configuration information for SRAM module.
00138   * @param  Timing: Pointer to SRAM control timing structure
00139   * @param  ExtTiming: Pointer to SRAM extended mode timing structure
00140   * @retval HAL status
00141   */
00142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
00143 {
00144   /* Check the SRAM handle parameter */
00145   if(hsram == NULL)
00146   {
00147      return HAL_ERROR;
00148   }
00149
00150   if(hsram->State == HAL_SRAM_STATE_RESET)
00151   {
00152     /* Allocate lock resource and initialize it */
00153     hsram->Lock = HAL_UNLOCKED;
00154
00155     /* Initialize the low level hardware (MSP) */
00156     HAL_SRAM_MspInit(hsram);
00157   }
00158
00159   /* Initialize SRAM control Interface */
00160   FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
00161
00162   /* Initialize SRAM timing Interface */
00163   FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
00164
00165   /* Initialize SRAM extended mode timing Interface */
00166   FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);
00167
00168   /* Enable the NORSRAM device */
00169   __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
00170
00171   return HAL_OK;
00172 }
00173
00174 /**
00175   * @brief  Performs the SRAM device De-initialization sequence.
00176   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00177   *                the configuration information for SRAM module.
00178   * @retval HAL status
00179   */
00180 HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
00181 {
00182   /* De-Initialize the low level hardware (MSP) */
00183   HAL_SRAM_MspDeInit(hsram);
00184
00185   /* Configure the SRAM registers with their reset values */
00186   FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
00187
00188   hsram->State = HAL_SRAM_STATE_RESET;
00189
00190   /* Release Lock */
00191   __HAL_UNLOCK(hsram);
00192
00193   return HAL_OK;
00194 }
00195
00196 /**
00197   * @brief  SRAM MSP Init.
00198   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00199   *                the configuration information for SRAM module.
00200   * @retval None
00201   */
00202 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
00203 {
00204   /* Prevent unused argument(s) compilation warning */
00205   UNUSED(hsram);
00206   /* NOTE : This function Should not be modified, when the callback is needed,
00207             the HAL_SRAM_MspInit could be implemented in the user file
00208    */
00209 }
00210
00211 /**
00212   * @brief  SRAM MSP DeInit.
00213   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00214   *                the configuration information for SRAM module.
00215   * @retval None
00216   */
00217 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
00218 {
00219   /* Prevent unused argument(s) compilation warning */
00220   UNUSED(hsram);
00221   /* NOTE : This function Should not be modified, when the callback is needed,
00222             the HAL_SRAM_MspDeInit could be implemented in the user file
00223    */
00224 }
00225
00226 /**
00227   * @brief  DMA transfer complete callback.
00228   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
00229   *                the configuration information for SRAM module.
00230   * @retval None
00231   */
00232 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
00233 {
00234   /* Prevent unused argument(s) compilation warning */
00235   UNUSED(hdma);
00236   /* NOTE : This function Should not be modified, when the callback is needed,
00237             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
00238    */
00239 }
00240
00241 /**
00242   * @brief  DMA transfer complete error callback.
00243   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
00244   *                the configuration information for SRAM module.
00245   * @retval None
00246   */
00247 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
00248 {
00249   /* Prevent unused argument(s) compilation warning */
00250   UNUSED(hdma);
00251   /* NOTE : This function Should not be modified, when the callback is needed,
00252             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
00253    */
00254 }
00255
00256 /**
00257   * @}
00258   */
00259
00260 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
00261   * @brief    Input Output and memory control functions
00262   *
00263   @verbatim
00264   ==============================================================================
00265                   ##### SRAM Input and Output functions #####
00266   ==============================================================================
00267   [..]
00268     This section provides functions allowing to use and control the SRAM memory
00269
00270 @endverbatim
00271   * @{
00272   */
00273
00274 /**
00275   * @brief  Reads 8-bit buffer from SRAM memory.
00276   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00277   *                the configuration information for SRAM module.
00278   * @param  pAddress: Pointer to read start address
00279   * @param  pDstBuffer: Pointer to destination buffer
00280   * @param  BufferSize: Size of the buffer to read from memory
00281   * @retval HAL status
00282   */
00283 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00284 {
00285   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00286
00287   /* Process Locked */
00288   __HAL_LOCK(hsram);
00289
00290   /* Update the SRAM controller state */
00291   hsram->State = HAL_SRAM_STATE_BUSY;
00292
00293   /* Read data from memory */
00294   for(; BufferSize != 0U; BufferSize--)
00295   {
00296     *pDstBuffer = *(__IO uint8_t *)psramaddress;
00297     pDstBuffer++;
00298     psramaddress++;
00299   }
00300
00301   /* Update the SRAM controller state */
00302   hsram->State = HAL_SRAM_STATE_READY;
00303
00304   /* Process unlocked */
00305   __HAL_UNLOCK(hsram);
00306
00307   return HAL_OK;
00308 }
00309
00310 /**
00311   * @brief  Writes 8-bit buffer to SRAM memory.
00312   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00313   *                the configuration information for SRAM module.
00314   * @param  pAddress: Pointer to write start address
00315   * @param  pSrcBuffer: Pointer to source buffer to write
00316   * @param  BufferSize: Size of the buffer to write to memory
00317   * @retval HAL status
00318   */
00319 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00320 {
00321   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00322
00323   /* Check the SRAM controller state */
00324   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00325   {
00326     return  HAL_ERROR;
00327   }
00328
00329   /* Process Locked */
00330   __HAL_LOCK(hsram);
00331
00332   /* Update the SRAM controller state */
00333   hsram->State = HAL_SRAM_STATE_BUSY;
00334
00335   /* Write data to memory */
00336   for(; BufferSize != 0U; BufferSize--)
00337   {
00338     *(__IO uint8_t *)psramaddress = *pSrcBuffer;
00339     pSrcBuffer++;
00340     psramaddress++;
00341   }
00342
00343   /* Update the SRAM controller state */
00344   hsram->State = HAL_SRAM_STATE_READY;
00345
00346   /* Process unlocked */
00347   __HAL_UNLOCK(hsram);
00348
00349   return HAL_OK;
00350 }
00351
00352 /**
00353   * @brief  Reads 16-bit buffer from SRAM memory.
00354   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00355   *                the configuration information for SRAM module.
00356   * @param  pAddress: Pointer to read start address
00357   * @param  pDstBuffer: Pointer to destination buffer
00358   * @param  BufferSize: Size of the buffer to read from memory
00359   * @retval HAL status
00360   */
00361 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00362 {
00363   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00364
00365   /* Process Locked */
00366   __HAL_LOCK(hsram);
00367
00368   /* Update the SRAM controller state */
00369   hsram->State = HAL_SRAM_STATE_BUSY;
00370
00371   /* Read data from memory */
00372   for(; BufferSize != 0U; BufferSize--)
00373   {
00374     *pDstBuffer = *(__IO uint16_t *)psramaddress;
00375     pDstBuffer++;
00376     psramaddress++;
00377   }
00378
00379   /* Update the SRAM controller state */
00380   hsram->State = HAL_SRAM_STATE_READY;
00381
00382   /* Process unlocked */
00383   __HAL_UNLOCK(hsram);
00384
00385   return HAL_OK;
00386 }
00387
00388 /**
00389   * @brief  Writes 16-bit buffer to SRAM memory.
00390   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00391   *                the configuration information for SRAM module.
00392   * @param  pAddress: Pointer to write start address
00393   * @param  pSrcBuffer: Pointer to source buffer to write
00394   * @param  BufferSize: Size of the buffer to write to memory
00395   * @retval HAL status
00396   */
00397 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00398 {
00399   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00400
00401   /* Check the SRAM controller state */
00402   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00403   {
00404     return  HAL_ERROR;
00405   }
00406
00407   /* Process Locked */
00408   __HAL_LOCK(hsram);
00409
00410   /* Update the SRAM controller state */
00411   hsram->State = HAL_SRAM_STATE_BUSY;
00412
00413   /* Write data to memory */
00414   for(; BufferSize != 0U; BufferSize--)
00415   {
00416     *(__IO uint16_t *)psramaddress = *pSrcBuffer;
00417     pSrcBuffer++;
00418     psramaddress++;
00419   }
00420
00421   /* Update the SRAM controller state */
00422   hsram->State = HAL_SRAM_STATE_READY;
00423
00424   /* Process unlocked */
00425   __HAL_UNLOCK(hsram);
00426
00427   return HAL_OK;
00428 }
00429
00430 /**
00431   * @brief  Reads 32-bit buffer from SRAM memory.
00432   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00433   *                the configuration information for SRAM module.
00434   * @param  pAddress: Pointer to read start address
00435   * @param  pDstBuffer: Pointer to destination buffer
00436   * @param  BufferSize: Size of the buffer to read from memory
00437   * @retval HAL status
00438   */
00439 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00440 {
00441   /* Process Locked */
00442   __HAL_LOCK(hsram);
00443
00444   /* Update the SRAM controller state */
00445   hsram->State = HAL_SRAM_STATE_BUSY;
00446
00447   /* Read data from memory */
00448   for(; BufferSize != 0U; BufferSize--)
00449   {
00450     *pDstBuffer = *(__IO uint32_t *)pAddress;
00451     pDstBuffer++;
00452     pAddress++;
00453   }
00454
00455   /* Update the SRAM controller state */
00456   hsram->State = HAL_SRAM_STATE_READY;
00457
00458   /* Process unlocked */
00459   __HAL_UNLOCK(hsram);
00460
00461   return HAL_OK;
00462 }
00463
00464 /**
00465   * @brief  Writes 32-bit buffer to SRAM memory.
00466   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00467   *                the configuration information for SRAM module.
00468   * @param  pAddress: Pointer to write start address
00469   * @param  pSrcBuffer: Pointer to source buffer to write
00470   * @param  BufferSize: Size of the buffer to write to memory
00471   * @retval HAL status
00472   */
00473 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00474 {
00475   /* Check the SRAM controller state */
00476   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00477   {
00478     return  HAL_ERROR;
00479   }
00480
00481   /* Process Locked */
00482   __HAL_LOCK(hsram);
00483
00484   /* Update the SRAM controller state */
00485   hsram->State = HAL_SRAM_STATE_BUSY;
00486
00487   /* Write data to memory */
00488   for(; BufferSize != 0U; BufferSize--)
00489   {
00490     *(__IO uint32_t *)pAddress = *pSrcBuffer;
00491     pSrcBuffer++;
00492     pAddress++;
00493   }
00494
00495   /* Update the SRAM controller state */
00496   hsram->State = HAL_SRAM_STATE_READY;
00497
00498   /* Process unlocked */
00499   __HAL_UNLOCK(hsram);
00500
00501   return HAL_OK;
00502 }
00503
00504 /**
00505   * @brief  Reads a Words data from the SRAM memory using DMA transfer.
00506   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00507   *                the configuration information for SRAM module.
00508   * @param  pAddress: Pointer to read start address
00509   * @param  pDstBuffer: Pointer to destination buffer
00510   * @param  BufferSize: Size of the buffer to read from memory
00511   * @retval HAL status
00512   */
00513 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00514 {
00515   /* Process Locked */
00516   __HAL_LOCK(hsram);
00517
00518   /* Update the SRAM controller state */
00519   hsram->State = HAL_SRAM_STATE_BUSY;
00520
00521   /* Configure DMA user callbacks */
00522   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00523   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00524
00525   /* Enable the DMA Channel */
00526   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
00527
00528   /* Update the SRAM controller state */
00529   hsram->State = HAL_SRAM_STATE_READY;
00530
00531   /* Process unlocked */
00532   __HAL_UNLOCK(hsram);
00533
00534   return HAL_OK;
00535 }
00536
00537 /**
00538   * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
00539   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00540   *                the configuration information for SRAM module.
00541   * @param  pAddress: Pointer to write start address
00542   * @param  pSrcBuffer: Pointer to source buffer to write
00543   * @param  BufferSize: Size of the buffer to write to memory
00544   * @retval HAL status
00545   */
00546 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00547 {
00548   /* Check the SRAM controller state */
00549   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00550   {
00551     return  HAL_ERROR;
00552   }
00553
00554   /* Process Locked */
00555   __HAL_LOCK(hsram);
00556
00557   /* Update the SRAM controller state */
00558   hsram->State = HAL_SRAM_STATE_BUSY;
00559
00560   /* Configure DMA user callbacks */
00561   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00562   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00563
00564   /* Enable the DMA Channel */
00565   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
00566
00567   /* Update the SRAM controller state */
00568   hsram->State = HAL_SRAM_STATE_READY;
00569
00570   /* Process unlocked */
00571   __HAL_UNLOCK(hsram);
00572
00573   return HAL_OK;
00574 }
00575
00576 /**
00577   * @}
00578   */
00579
00580 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
00581  *  @brief   Control functions
00582  *
00583 @verbatim
00584   ==============================================================================
00585                         ##### SRAM Control functions #####
00586   ==============================================================================
00587   [..]
00588     This subsection provides a set of functions allowing to control dynamically
00589     the SRAM interface.
00590
00591 @endverbatim
00592   * @{
00593   */
00594
00595 /**
00596   * @brief  Enables dynamically SRAM write operation.
00597   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00598   *                the configuration information for SRAM module.
00599   * @retval HAL status
00600   */
00601 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
00602 {
00603   /* Process Locked */
00604   __HAL_LOCK(hsram);
00605
00606   /* Enable write operation */
00607   FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
00608
00609   /* Update the SRAM controller state */
00610   hsram->State = HAL_SRAM_STATE_READY;
00611
00612   /* Process unlocked */
00613   __HAL_UNLOCK(hsram);
00614
00615   return HAL_OK;
00616 }
00617
00618 /**
00619   * @brief  Disables dynamically SRAM write operation.
00620   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00621   *                the configuration information for SRAM module.
00622   * @retval HAL status
00623   */
00624 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
00625 {
00626   /* Process Locked */
00627   __HAL_LOCK(hsram);
00628
00629   /* Update the SRAM controller state */
00630   hsram->State = HAL_SRAM_STATE_BUSY;
00631
00632   /* Disable write operation */
00633   FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
00634
00635   /* Update the SRAM controller state */
00636   hsram->State = HAL_SRAM_STATE_PROTECTED;
00637
00638   /* Process unlocked */
00639   __HAL_UNLOCK(hsram);
00640
00641   return HAL_OK;
00642 }
00643
00644 /**
00645   * @}
00646   */
00647
00648 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
00649  *  @brief   Peripheral State functions
00650  *
00651 @verbatim
00652   ==============================================================================
00653                       ##### SRAM State functions #####
00654   ==============================================================================
00655   [..]
00656     This subsection permits to get in run-time the status of the SRAM controller
00657     and the data flow.
00658
00659 @endverbatim
00660   * @{
00661   */
00662
00663 /**
00664   * @brief  Returns the SRAM controller state
00665   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00666   *                the configuration information for SRAM module.
00667   * @retval HAL state
00668   */
00669 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
00670 {
00671   return hsram->State;
00672 }
00673
00674 /**
00675   * @}
00676   */
00677
00678 /**
00679   * @}
00680   */
00681
00682 /**
00683   * @}
00684   */
00685 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
00686 #endif /* HAL_SRAM_MODULE_ENABLED */
00687
00688 /**
00689   * @}
00690   */
00691
00692 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_sram.h Source File

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stm32f1xx_hal_sram.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_sram.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of SRAM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_SRAM_H
00040 #define __STM32F1xx_HAL_SRAM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_ll_fsmc.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
00054
00055 /** @addtogroup SRAM
00056   * @{
00057   */
00058
00059 /* Exported typedef ----------------------------------------------------------*/
00060
00061 /** @defgroup SRAM_Exported_Types SRAM Exported Types
00062   * @{
00063   */
00064 /**
00065   * @brief  HAL SRAM State structures definition
00066   */
00067 typedef enum
00068 {
00069   HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
00070   HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
00071   HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
00072   HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
00073   HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
00074
00075 }HAL_SRAM_StateTypeDef;
00076
00077 /**
00078   * @brief  SRAM handle Structure definition
00079   */
00080 typedef struct
00081 {
00082   FSMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
00083
00084   FSMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
00085
00086   FSMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
00087
00088   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
00089
00090   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
00091
00092   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
00093
00094 }SRAM_HandleTypeDef;
00095
00096 /**
00097   * @}
00098   */
00099
00100 /* Exported constants --------------------------------------------------------*/
00101 /* Exported macro ------------------------------------------------------------*/
00102
00103 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
00104   * @{
00105   */
00106
00107 /** @brief Reset SRAM handle state
00108   * @param  __HANDLE__: SRAM handle
00109   * @retval None
00110   */
00111 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
00112
00113 /**
00114   * @}
00115   */
00116
00117 /* Exported functions --------------------------------------------------------*/
00118
00119 /** @addtogroup SRAM_Exported_Functions
00120  *  @{
00121  */
00122
00123 /** @addtogroup SRAM_Exported_Functions_Group1
00124  *  @{
00125  */
00126
00127 /* Initialization/de-initialization functions  **********************************/
00128 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
00129 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
00130 void              HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
00131 void              HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
00132
00133 void              HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
00134 void              HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
00135
00136 /**
00137   * @}
00138   */
00139
00140 /** @addtogroup SRAM_Exported_Functions_Group2
00141  *  @{
00142  */
00143
00144 /* I/O operation functions  *****************************************************/
00145 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
00146 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
00147 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
00148 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
00149 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00150 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00151 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
00152 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
00153
00154 /**
00155   * @}
00156   */
00157
00158 /** @addtogroup SRAM_Exported_Functions_Group3
00159  *  @{
00160  */
00161
00162 /* SRAM Control functions  ******************************************************/
00163 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
00164 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
00165
00166 /**
00167   * @}
00168   */
00169
00170 /** @addtogroup SRAM_Exported_Functions_Group4
00171  *  @{
00172  */
00173
00174 /* SRAM State functions *********************************************************/
00175 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
00176
00177 /**
00178   * @}
00179   */
00180
00181 /**
00182   * @}
00183   */
00184
00185 /**
00186   * @}
00187   */
00188
00189 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
00190
00191 /**
00192   * @}
00193   */
00194
00195 #ifdef __cplusplus
00196 }
00197 #endif
00198
00199 #endif /* __STM32F1xx_HAL_SRAM_H */
00200
00201 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:23 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_tim.c Source File

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stm32f1xx_hal_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_tim.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   TIM HAL module driver
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer (TIM) peripheral:
00010   *           + Time Base Initialization
00011   *           + Time Base Start
00012   *           + Time Base Start Interruption
00013   *           + Time Base Start DMA
00014   *           + Time Output Compare/PWM Initialization
00015   *           + Time Output Compare/PWM Channel Configuration
00016   *           + Time Output Compare/PWM  Start
00017   *           + Time Output Compare/PWM  Start Interruption
00018   *           + Time Output Compare/PWM Start DMA
00019   *           + Time Input Capture Initialization
00020   *           + Time Input Capture Channel Configuration
00021   *           + Time Input Capture Start
00022   *           + Time Input Capture Start Interruption
00023   *           + Time Input Capture Start DMA
00024   *           + Time One Pulse Initialization
00025   *           + Time One Pulse Channel Configuration
00026   *           + Time One Pulse Start
00027   *           + Time Encoder Interface Initialization
00028   *           + Time Encoder Interface Start
00029   *           + Time Encoder Interface Start Interruption
00030   *           + Time Encoder Interface Start DMA
00031   *           + Commutation Event configuration with Interruption and DMA
00032   *           + Time OCRef clear configuration
00033   *           + Time External Clock configuration
00034   @verbatim
00035   ==============================================================================
00036                       ##### TIMER Generic features #####
00037   ==============================================================================
00038   [..] The Timer features include:
00039        (#) 16-bit up, down, up/down auto-reload counter.
00040        (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
00041            counter clock frequency either by any factor between 1 and 65536.
00042        (#) Up to 4 independent channels for:
00043            (++) Input Capture
00044            (++) Output Compare
00045            (++) PWM generation (Edge and Center-aligned Mode)
00046            (++) One-pulse mode output
00047
00048             ##### How to use this driver #####
00049   ==============================================================================
00050     [..]
00051      (#) Initialize the TIM low level resources by implementing the following functions
00052          depending from feature used :
00053            (++) Time Base : HAL_TIM_Base_MspInit()
00054            (++) Input Capture : HAL_TIM_IC_MspInit()
00055            (++) Output Compare : HAL_TIM_OC_MspInit()
00056            (++) PWM generation : HAL_TIM_PWM_MspInit()
00057            (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00058            (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
00059
00060      (#) Initialize the TIM low level resources :
00061         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00062         (##) TIM pins configuration
00063             (+++) Enable the clock for the TIM GPIOs using the following function:
00064              __HAL_RCC_GPIOx_CLK_ENABLE();
00065             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00066
00067      (#) The external Clock can be configured, if needed (the default clock is the
00068          internal clock from the APBx), using the following function:
00069          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00070          any start function.
00071
00072      (#) Configure the TIM in the desired functioning mode using one of the
00073        Initialization function of this driver:
00074        (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
00075        (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
00076             Output Compare signal.
00077        (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
00078             PWM signal.
00079        (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
00080             external signal.
00081          (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
00082               in One Pulse Mode.
00083        (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
00084
00085      (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
00086            (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
00087            (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
00088            (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
00089            (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
00090            (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
00091            (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
00092
00093      (#) The DMA Burst is managed with the two following functions:
00094          HAL_TIM_DMABurst_WriteStart()
00095          HAL_TIM_DMABurst_ReadStart()
00096
00097   @endverbatim
00098   ******************************************************************************
00099   * @attention
00100   *
00101   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00102   *
00103   * Redistribution and use in source and binary forms, with or without modification,
00104   * are permitted provided that the following conditions are met:
00105   *   1. Redistributions of source code must retain the above copyright notice,
00106   *      this list of conditions and the following disclaimer.
00107   *   2. Redistributions in binary form must reproduce the above copyright notice,
00108   *      this list of conditions and the following disclaimer in the documentation
00109   *      and/or other materials provided with the distribution.
00110   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00111   *      may be used to endorse or promote products derived from this software
00112   *      without specific prior written permission.
00113   *
00114   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00115   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00116   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00117   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00118   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00119   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00120   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00121   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00122   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00123   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00124   *
00125   ******************************************************************************
00126   */
00127
00128 /* Includes ------------------------------------------------------------------*/
00129 #include "stm32f1xx_hal.h"
00130
00131 /** @addtogroup STM32F1xx_HAL_Driver
00132   * @{
00133   */
00134
00135 /** @defgroup TIM TIM
00136   * @brief TIM HAL module driver
00137   * @{
00138   */
00139
00140 #ifdef HAL_TIM_MODULE_ENABLED
00141
00142 /* Private typedef -----------------------------------------------------------*/
00143 /* Private define ------------------------------------------------------------*/
00144 /* Private macro -------------------------------------------------------------*/
00145 /* Private variables ---------------------------------------------------------*/
00146 /* Private function prototypes -----------------------------------------------*/
00147 /** @defgroup TIM_Private_Functions TIM Private Functions
00148   * @{
00149   */
00150 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00151 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00152 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
00153 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00154 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00155                        uint32_t TIM_ICFilter);
00156 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
00157 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00158                        uint32_t TIM_ICFilter);
00159 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
00160                        uint32_t TIM_ICFilter);
00161 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
00162                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
00163 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
00164 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
00165 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
00166 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
00167                                      TIM_SlaveConfigTypeDef * sSlaveConfig);
00168
00169 /**
00170   * @}
00171   */
00172
00173 /* Exported functions ---------------------------------------------------------*/
00174
00175 /** @defgroup TIM_Exported_Functions TIM Exported Functions
00176   * @{
00177   */
00178
00179 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
00180  *  @brief    Time Base functions
00181  *
00182 @verbatim
00183   ==============================================================================
00184               ##### Time Base functions #####
00185   ==============================================================================
00186   [..]
00187     This section provides functions allowing to:
00188     (+) Initialize and configure the TIM base.
00189     (+) De-initialize the TIM base.
00190     (+) Start the Time Base.
00191     (+) Stop the Time Base.
00192     (+) Start the Time Base and enable interrupt.
00193     (+) Stop the Time Base and disable interrupt.
00194     (+) Start the Time Base and enable DMA transfer.
00195     (+) Stop the Time Base and disable DMA transfer.
00196
00197 @endverbatim
00198   * @{
00199   */
00200 /**
00201   * @brief  Initializes the TIM Time base Unit according to the specified
00202   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00203   * @param  htim : TIM Base handle
00204   * @retval HAL status
00205   */
00206 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
00207 {
00208   /* Check the TIM handle allocation */
00209   if(htim == NULL)
00210   {
00211     return HAL_ERROR;
00212   }
00213
00214   /* Check the parameters */
00215   assert_param(IS_TIM_INSTANCE(htim->Instance));
00216   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00217   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00218   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00219
00220   if(htim->State == HAL_TIM_STATE_RESET)
00221   {
00222     /* Allocate lock resource and initialize it */
00223     htim->Lock = HAL_UNLOCKED;
00224
00225     /* Init the low level hardware : GPIO, CLOCK, NVIC */
00226     HAL_TIM_Base_MspInit(htim);
00227   }
00228
00229   /* Set the TIM state */
00230   htim->State= HAL_TIM_STATE_BUSY;
00231
00232   /* Set the Time Base configuration */
00233   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00234
00235   /* Initialize the TIM state*/
00236   htim->State= HAL_TIM_STATE_READY;
00237
00238   return HAL_OK;
00239 }
00240
00241 /**
00242   * @brief  DeInitializes the TIM Base peripheral
00243   * @param  htim : TIM Base handle
00244   * @retval HAL status
00245   */
00246 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
00247 {
00248   /* Check the parameters */
00249   assert_param(IS_TIM_INSTANCE(htim->Instance));
00250
00251   htim->State = HAL_TIM_STATE_BUSY;
00252
00253   /* Disable the TIM Peripheral Clock */
00254   __HAL_TIM_DISABLE(htim);
00255
00256   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00257   HAL_TIM_Base_MspDeInit(htim);
00258
00259   /* Change TIM state */
00260   htim->State = HAL_TIM_STATE_RESET;
00261
00262   /* Release Lock */
00263   __HAL_UNLOCK(htim);
00264
00265   return HAL_OK;
00266 }
00267
00268 /**
00269   * @brief  Initializes the TIM Base MSP.
00270   * @param  htim : TIM handle
00271   * @retval None
00272   */
00273 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
00274 {
00275   /* Prevent unused argument(s) compilation warning */
00276   UNUSED(htim);
00277   /* NOTE : This function Should not be modified, when the callback is needed,
00278             the HAL_TIM_Base_MspInit could be implemented in the user file
00279    */
00280 }
00281
00282 /**
00283   * @brief  DeInitializes TIM Base MSP.
00284   * @param  htim : TIM handle
00285   * @retval None
00286   */
00287 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
00288 {
00289   /* Prevent unused argument(s) compilation warning */
00290   UNUSED(htim);
00291   /* NOTE : This function Should not be modified, when the callback is needed,
00292             the HAL_TIM_Base_MspDeInit could be implemented in the user file
00293    */
00294 }
00295
00296
00297 /**
00298   * @brief  Starts the TIM Base generation.
00299   * @param  htim : TIM handle
00300   * @retval HAL status
00301 */
00302 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
00303 {
00304   /* Check the parameters */
00305   assert_param(IS_TIM_INSTANCE(htim->Instance));
00306
00307   /* Set the TIM state */
00308   htim->State= HAL_TIM_STATE_BUSY;
00309
00310   /* Enable the Peripheral */
00311   __HAL_TIM_ENABLE(htim);
00312
00313   /* Change the TIM state*/
00314   htim->State= HAL_TIM_STATE_READY;
00315
00316   /* Return function status */
00317   return HAL_OK;
00318 }
00319
00320 /**
00321   * @brief  Stops the TIM Base generation.
00322   * @param  htim : TIM handle
00323   * @retval HAL status
00324 */
00325 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
00326 {
00327   /* Check the parameters */
00328   assert_param(IS_TIM_INSTANCE(htim->Instance));
00329
00330   /* Set the TIM state */
00331   htim->State= HAL_TIM_STATE_BUSY;
00332
00333   /* Disable the Peripheral */
00334   __HAL_TIM_DISABLE(htim);
00335
00336   /* Change the TIM state*/
00337   htim->State= HAL_TIM_STATE_READY;
00338
00339   /* Return function status */
00340   return HAL_OK;
00341 }
00342
00343 /**
00344   * @brief  Starts the TIM Base generation in interrupt mode.
00345   * @param  htim : TIM handle
00346   * @retval HAL status
00347 */
00348 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
00349 {
00350   /* Check the parameters */
00351   assert_param(IS_TIM_INSTANCE(htim->Instance));
00352
00353    /* Enable the TIM Update interrupt */
00354    __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
00355
00356    /* Enable the Peripheral */
00357   __HAL_TIM_ENABLE(htim);
00358
00359   /* Return function status */
00360   return HAL_OK;
00361 }
00362
00363 /**
00364   * @brief  Stops the TIM Base generation in interrupt mode.
00365   * @param  htim : TIM handle
00366   * @retval HAL status
00367 */
00368 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
00369 {
00370   /* Check the parameters */
00371   assert_param(IS_TIM_INSTANCE(htim->Instance));
00372   /* Disable the TIM Update interrupt */
00373   __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
00374
00375   /* Disable the Peripheral */
00376   __HAL_TIM_DISABLE(htim);
00377
00378   /* Return function status */
00379   return HAL_OK;
00380 }
00381
00382 /**
00383   * @brief  Starts the TIM Base generation in DMA mode.
00384   * @param  htim : TIM handle
00385   * @param  pData : The source Buffer address.
00386   * @param  Length : The length of data to be transferred from memory to peripheral.
00387   * @retval HAL status
00388 */
00389 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00390 {
00391   /* Check the parameters */
00392   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00393
00394   if((htim->State == HAL_TIM_STATE_BUSY))
00395   {
00396      return HAL_BUSY;
00397   }
00398   else if((htim->State == HAL_TIM_STATE_READY))
00399   {
00400     if((pData == 0U) && (Length > 0U))
00401     {
00402       return HAL_ERROR;
00403     }
00404     else
00405     {
00406       htim->State = HAL_TIM_STATE_BUSY;
00407     }
00408   }
00409   /* Set the DMA Period elapsed callback */
00410   htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
00411
00412   /* Set the DMA error callback */
00413   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
00414
00415   /* Enable the DMA channel */
00416   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
00417
00418   /* Enable the TIM Update DMA request */
00419   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
00420
00421   /* Enable the Peripheral */
00422   __HAL_TIM_ENABLE(htim);
00423
00424   /* Return function status */
00425   return HAL_OK;
00426 }
00427
00428 /**
00429   * @brief  Stops the TIM Base generation in DMA mode.
00430   * @param  htim : TIM handle
00431   * @retval HAL status
00432 */
00433 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
00434 {
00435   /* Check the parameters */
00436   assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
00437
00438   /* Disable the TIM Update DMA request */
00439   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
00440
00441   /* Disable the Peripheral */
00442   __HAL_TIM_DISABLE(htim);
00443
00444   /* Change the htim state */
00445   htim->State = HAL_TIM_STATE_READY;
00446
00447   /* Return function status */
00448   return HAL_OK;
00449 }
00450
00451 /**
00452   * @}
00453   */
00454
00455 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
00456  *  @brief    Time Output Compare functions
00457  *
00458 @verbatim
00459   ==============================================================================
00460                   ##### Time Output Compare functions #####
00461   ==============================================================================
00462   [..]
00463     This section provides functions allowing to:
00464     (+) Initialize and configure the TIM Output Compare.
00465     (+) De-initialize the TIM Output Compare.
00466     (+) Start the Time Output Compare.
00467     (+) Stop the Time Output Compare.
00468     (+) Start the Time Output Compare and enable interrupt.
00469     (+) Stop the Time Output Compare and disable interrupt.
00470     (+) Start the Time Output Compare and enable DMA transfer.
00471     (+) Stop the Time Output Compare and disable DMA transfer.
00472
00473 @endverbatim
00474   * @{
00475   */
00476 /**
00477   * @brief  Initializes the TIM Output Compare according to the specified
00478   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00479   * @param  htim : TIM Output Compare handle
00480   * @retval HAL status
00481   */
00482 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
00483 {
00484   /* Check the TIM handle allocation */
00485   if(htim == NULL)
00486   {
00487     return HAL_ERROR;
00488   }
00489
00490   /* Check the parameters */
00491   assert_param(IS_TIM_INSTANCE(htim->Instance));
00492   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00493   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00494   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00495
00496   if(htim->State == HAL_TIM_STATE_RESET)
00497   {
00498     /* Allocate lock resource and initialize it */
00499     htim->Lock = HAL_UNLOCKED;
00500
00501     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00502     HAL_TIM_OC_MspInit(htim);
00503   }
00504
00505   /* Set the TIM state */
00506   htim->State= HAL_TIM_STATE_BUSY;
00507
00508   /* Init the base time for the Output Compare */
00509   TIM_Base_SetConfig(htim->Instance,  &htim->Init);
00510
00511   /* Initialize the TIM state*/
00512   htim->State= HAL_TIM_STATE_READY;
00513
00514   return HAL_OK;
00515 }
00516
00517 /**
00518   * @brief  DeInitializes the TIM peripheral
00519   * @param  htim : TIM Output Compare handle
00520   * @retval HAL status
00521   */
00522 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
00523 {
00524   /* Check the parameters */
00525   assert_param(IS_TIM_INSTANCE(htim->Instance));
00526
00527    htim->State = HAL_TIM_STATE_BUSY;
00528
00529   /* Disable the TIM Peripheral Clock */
00530   __HAL_TIM_DISABLE(htim);
00531
00532   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
00533   HAL_TIM_OC_MspDeInit(htim);
00534
00535   /* Change TIM state */
00536   htim->State = HAL_TIM_STATE_RESET;
00537
00538   /* Release Lock */
00539   __HAL_UNLOCK(htim);
00540
00541   return HAL_OK;
00542 }
00543
00544 /**
00545   * @brief  Initializes the TIM Output Compare MSP.
00546   * @param  htim : TIM handle
00547   * @retval None
00548   */
00549 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
00550 {
00551   /* Prevent unused argument(s) compilation warning */
00552   UNUSED(htim);
00553   /* NOTE : This function Should not be modified, when the callback is needed,
00554             the HAL_TIM_OC_MspInit could be implemented in the user file
00555    */
00556 }
00557
00558 /**
00559   * @brief  DeInitializes TIM Output Compare MSP.
00560   * @param  htim : TIM handle
00561   * @retval None
00562   */
00563 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
00564 {
00565   /* Prevent unused argument(s) compilation warning */
00566   UNUSED(htim);
00567   /* NOTE : This function Should not be modified, when the callback is needed,
00568             the HAL_TIM_OC_MspDeInit could be implemented in the user file
00569    */
00570 }
00571
00572 /**
00573   * @brief  Starts the TIM Output Compare signal generation.
00574   * @param  htim : TIM Output Compare handle
00575   * @param  Channel : TIM Channel to be enabled
00576   *          This parameter can be one of the following values:
00577   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00578   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00579   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00580   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00581   * @retval HAL status
00582 */
00583 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00584 {
00585   /* Check the parameters */
00586   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00587
00588   /* Enable the Output compare channel */
00589   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00590
00591   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00592   {
00593     /* Enable the main output */
00594     __HAL_TIM_MOE_ENABLE(htim);
00595   }
00596
00597   /* Enable the Peripheral */
00598   __HAL_TIM_ENABLE(htim);
00599
00600   /* Return function status */
00601   return HAL_OK;
00602 }
00603
00604 /**
00605   * @brief  Stops the TIM Output Compare signal generation.
00606   * @param  htim : TIM handle
00607   * @param  Channel : TIM Channel to be disabled
00608   *          This parameter can be one of the following values:
00609   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00610   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00611   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00612   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00613   * @retval HAL status
00614 */
00615 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00616 {
00617   /* Check the parameters */
00618   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00619
00620   /* Disable the Output compare channel */
00621   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00622
00623   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00624   {
00625     /* Disable the Main Ouput */
00626     __HAL_TIM_MOE_DISABLE(htim);
00627   }
00628
00629   /* Disable the Peripheral */
00630   __HAL_TIM_DISABLE(htim);
00631
00632   /* Return function status */
00633   return HAL_OK;
00634 }
00635
00636 /**
00637   * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
00638   * @param  htim : TIM OC handle
00639   * @param  Channel : TIM Channel to be enabled
00640   *          This parameter can be one of the following values:
00641   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00642   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00643   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00644   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00645   * @retval HAL status
00646 */
00647 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00648 {
00649   /* Check the parameters */
00650   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00651
00652   switch (Channel)
00653   {
00654     case TIM_CHANNEL_1:
00655     {
00656       /* Enable the TIM Capture/Compare 1 interrupt */
00657       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00658     }
00659     break;
00660
00661     case TIM_CHANNEL_2:
00662     {
00663       /* Enable the TIM Capture/Compare 2 interrupt */
00664       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00665     }
00666     break;
00667
00668     case TIM_CHANNEL_3:
00669     {
00670       /* Enable the TIM Capture/Compare 3 interrupt */
00671       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00672     }
00673     break;
00674
00675     case TIM_CHANNEL_4:
00676     {
00677       /* Enable the TIM Capture/Compare 4 interrupt */
00678       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00679     }
00680     break;
00681
00682     default:
00683     break;
00684   }
00685
00686   /* Enable the Output compare channel */
00687   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00688
00689   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00690   {
00691     /* Enable the main output */
00692     __HAL_TIM_MOE_ENABLE(htim);
00693   }
00694
00695   /* Enable the Peripheral */
00696   __HAL_TIM_ENABLE(htim);
00697
00698   /* Return function status */
00699   return HAL_OK;
00700 }
00701
00702 /**
00703   * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
00704   * @param  htim : TIM Output Compare handle
00705   * @param  Channel : TIM Channel to be disabled
00706   *          This parameter can be one of the following values:
00707   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00708   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00709   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00710   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00711   * @retval HAL status
00712 */
00713 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00714 {
00715   /* Check the parameters */
00716   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00717
00718   switch (Channel)
00719   {
00720     case TIM_CHANNEL_1:
00721     {
00722       /* Disable the TIM Capture/Compare 1 interrupt */
00723       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00724     }
00725     break;
00726
00727     case TIM_CHANNEL_2:
00728     {
00729       /* Disable the TIM Capture/Compare 2 interrupt */
00730       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00731     }
00732     break;
00733
00734     case TIM_CHANNEL_3:
00735     {
00736       /* Disable the TIM Capture/Compare 3 interrupt */
00737       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00738     }
00739     break;
00740
00741     case TIM_CHANNEL_4:
00742     {
00743       /* Disable the TIM Capture/Compare 4 interrupt */
00744       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00745     }
00746     break;
00747
00748     default:
00749     break;
00750   }
00751
00752   /* Disable the Output compare channel */
00753   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00754
00755   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00756   {
00757     /* Disable the Main Ouput */
00758     __HAL_TIM_MOE_DISABLE(htim);
00759   }
00760
00761   /* Disable the Peripheral */
00762   __HAL_TIM_DISABLE(htim);
00763
00764   /* Return function status */
00765   return HAL_OK;
00766 }
00767
00768 /**
00769   * @brief  Starts the TIM Output Compare signal generation in DMA mode.
00770   * @param  htim : TIM Output Compare handle
00771   * @param  Channel : TIM Channel to be enabled
00772   *          This parameter can be one of the following values:
00773   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00774   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00775   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00776   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00777   * @param  pData : The source Buffer address.
00778   * @param  Length : The length of data to be transferred from memory to TIM peripheral
00779   * @retval HAL status
00780 */
00781 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00782 {
00783   /* Check the parameters */
00784   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00785
00786   if((htim->State == HAL_TIM_STATE_BUSY))
00787   {
00788      return HAL_BUSY;
00789   }
00790   else if((htim->State == HAL_TIM_STATE_READY))
00791   {
00792     if(((uint32_t)pData == 0U) && (Length > 0U))
00793     {
00794       return HAL_ERROR;
00795     }
00796     else
00797     {
00798       htim->State = HAL_TIM_STATE_BUSY;
00799     }
00800   }
00801   switch (Channel)
00802   {
00803     case TIM_CHANNEL_1:
00804     {
00805       /* Set the DMA Period elapsed callback */
00806       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00807
00808       /* Set the DMA error callback */
00809       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00810
00811       /* Enable the DMA channel */
00812       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00813
00814       /* Enable the TIM Capture/Compare 1 DMA request */
00815       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00816     }
00817     break;
00818
00819     case TIM_CHANNEL_2:
00820     {
00821       /* Set the DMA Period elapsed callback */
00822       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00823
00824       /* Set the DMA error callback */
00825       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00826
00827       /* Enable the DMA channel */
00828       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00829
00830       /* Enable the TIM Capture/Compare 2 DMA request */
00831       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00832     }
00833     break;
00834
00835     case TIM_CHANNEL_3:
00836     {
00837       /* Set the DMA Period elapsed callback */
00838       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00839
00840       /* Set the DMA error callback */
00841       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00842
00843       /* Enable the DMA channel */
00844       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00845
00846       /* Enable the TIM Capture/Compare 3 DMA request */
00847       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00848     }
00849     break;
00850
00851     case TIM_CHANNEL_4:
00852     {
00853      /* Set the DMA Period elapsed callback */
00854       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
00855
00856       /* Set the DMA error callback */
00857       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
00858
00859       /* Enable the DMA channel */
00860       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00861
00862       /* Enable the TIM Capture/Compare 4 DMA request */
00863       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00864     }
00865     break;
00866
00867     default:
00868     break;
00869   }
00870
00871   /* Enable the Output compare channel */
00872   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
00873
00874   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00875   {
00876     /* Enable the main output */
00877     __HAL_TIM_MOE_ENABLE(htim);
00878   }
00879
00880   /* Enable the Peripheral */
00881   __HAL_TIM_ENABLE(htim);
00882
00883   /* Return function status */
00884   return HAL_OK;
00885 }
00886
00887 /**
00888   * @brief  Stops the TIM Output Compare signal generation in DMA mode.
00889   * @param  htim : TIM Output Compare handle
00890   * @param  Channel : TIM Channel to be disabled
00891   *          This parameter can be one of the following values:
00892   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00893   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00894   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00895   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00896   * @retval HAL status
00897 */
00898 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00899 {
00900   /* Check the parameters */
00901   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
00902
00903   switch (Channel)
00904   {
00905     case TIM_CHANNEL_1:
00906     {
00907       /* Disable the TIM Capture/Compare 1 DMA request */
00908       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00909     }
00910     break;
00911
00912     case TIM_CHANNEL_2:
00913     {
00914       /* Disable the TIM Capture/Compare 2 DMA request */
00915       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00916     }
00917     break;
00918
00919     case TIM_CHANNEL_3:
00920     {
00921       /* Disable the TIM Capture/Compare 3 DMA request */
00922       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00923     }
00924     break;
00925
00926     case TIM_CHANNEL_4:
00927     {
00928       /* Disable the TIM Capture/Compare 4 interrupt */
00929       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00930     }
00931     break;
00932
00933     default:
00934     break;
00935   }
00936
00937   /* Disable the Output compare channel */
00938   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
00939
00940   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
00941   {
00942     /* Disable the Main Ouput */
00943     __HAL_TIM_MOE_DISABLE(htim);
00944   }
00945
00946   /* Disable the Peripheral */
00947   __HAL_TIM_DISABLE(htim);
00948
00949   /* Change the htim state */
00950   htim->State = HAL_TIM_STATE_READY;
00951
00952   /* Return function status */
00953   return HAL_OK;
00954 }
00955
00956 /**
00957   * @}
00958   */
00959
00960 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
00961  *  @brief    Time PWM functions
00962  *
00963 @verbatim
00964   ==============================================================================
00965                           ##### Time PWM functions #####
00966   ==============================================================================
00967   [..]
00968     This section provides functions allowing to:
00969     (+) Initialize and configure the TIM PWM.
00970     (+) De-initialize the TIM PWM.
00971     (+) Start the Time PWM.
00972     (+) Stop the Time PWM.
00973     (+) Start the Time PWM and enable interrupt.
00974     (+) Stop the Time PWM and disable interrupt.
00975     (+) Start the Time PWM and enable DMA transfer.
00976     (+) Stop the Time PWM and disable DMA transfer.
00977
00978 @endverbatim
00979   * @{
00980   */
00981 /**
00982   * @brief  Initializes the TIM PWM Time Base according to the specified
00983   *         parameters in the TIM_HandleTypeDef and create the associated handle.
00984   * @param  htim : TIM handle
00985   * @retval HAL status
00986   */
00987 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
00988 {
00989   /* Check the TIM handle allocation */
00990   if(htim == NULL)
00991   {
00992     return HAL_ERROR;
00993   }
00994
00995   /* Check the parameters */
00996   assert_param(IS_TIM_INSTANCE(htim->Instance));
00997   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00998   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00999   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01000
01001   if(htim->State == HAL_TIM_STATE_RESET)
01002   {
01003     /* Allocate lock resource and initialize it */
01004     htim->Lock = HAL_UNLOCKED;
01005
01006     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01007     HAL_TIM_PWM_MspInit(htim);
01008   }
01009
01010   /* Set the TIM state */
01011   htim->State= HAL_TIM_STATE_BUSY;
01012
01013   /* Init the base time for the PWM */
01014   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01015
01016   /* Initialize the TIM state*/
01017   htim->State= HAL_TIM_STATE_READY;
01018
01019   return HAL_OK;
01020 }
01021
01022 /**
01023   * @brief  DeInitializes the TIM peripheral
01024   * @param  htim : TIM handle
01025   * @retval HAL status
01026   */
01027 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
01028 {
01029   /* Check the parameters */
01030   assert_param(IS_TIM_INSTANCE(htim->Instance));
01031
01032   htim->State = HAL_TIM_STATE_BUSY;
01033
01034   /* Disable the TIM Peripheral Clock */
01035   __HAL_TIM_DISABLE(htim);
01036
01037   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01038   HAL_TIM_PWM_MspDeInit(htim);
01039
01040   /* Change TIM state */
01041   htim->State = HAL_TIM_STATE_RESET;
01042
01043   /* Release Lock */
01044   __HAL_UNLOCK(htim);
01045
01046   return HAL_OK;
01047 }
01048
01049 /**
01050   * @brief  Initializes the TIM PWM MSP.
01051   * @param  htim : TIM handle
01052   * @retval None
01053   */
01054 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
01055 {
01056   /* Prevent unused argument(s) compilation warning */
01057   UNUSED(htim);
01058   /* NOTE : This function Should not be modified, when the callback is needed,
01059             the HAL_TIM_PWM_MspInit could be implemented in the user file
01060    */
01061 }
01062
01063 /**
01064   * @brief  DeInitializes TIM PWM MSP.
01065   * @param  htim : TIM handle
01066   * @retval None
01067   */
01068 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
01069 {
01070   /* Prevent unused argument(s) compilation warning */
01071   UNUSED(htim);
01072   /* NOTE : This function Should not be modified, when the callback is needed,
01073             the HAL_TIM_PWM_MspDeInit could be implemented in the user file
01074    */
01075 }
01076
01077 /**
01078   * @brief  Starts the PWM signal generation.
01079   * @param  htim : TIM handle
01080   * @param  Channel : TIM Channels to be enabled
01081   *          This parameter can be one of the following values:
01082   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01083   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01084   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01085   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01086   * @retval HAL status
01087 */
01088 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
01089 {
01090   /* Check the parameters */
01091   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01092
01093   /* Enable the Capture compare channel */
01094   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01095
01096   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01097   {
01098     /* Enable the main output */
01099     __HAL_TIM_MOE_ENABLE(htim);
01100   }
01101
01102   /* Enable the Peripheral */
01103   __HAL_TIM_ENABLE(htim);
01104
01105   /* Return function status */
01106   return HAL_OK;
01107 }
01108
01109 /**
01110   * @brief  Stops the PWM signal generation.
01111   * @param  htim : TIM handle
01112   * @param  Channel : TIM Channels to be disabled
01113   *          This parameter can be one of the following values:
01114   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01115   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01116   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01117   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01118   * @retval HAL status
01119 */
01120 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01121 {
01122   /* Check the parameters */
01123   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01124
01125   /* Disable the Capture compare channel */
01126   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01127
01128   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01129   {
01130     /* Disable the Main Ouput */
01131     __HAL_TIM_MOE_DISABLE(htim);
01132   }
01133
01134   /* Disable the Peripheral */
01135   __HAL_TIM_DISABLE(htim);
01136
01137   /* Change the htim state */
01138   htim->State = HAL_TIM_STATE_READY;
01139
01140   /* Return function status */
01141   return HAL_OK;
01142 }
01143
01144 /**
01145   * @brief  Starts the PWM signal generation in interrupt mode.
01146   * @param  htim : TIM handle
01147   * @param  Channel : TIM Channel to be enabled
01148   *          This parameter can be one of the following values:
01149   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01150   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01151   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01152   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01153   * @retval HAL status
01154 */
01155 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01156 {
01157   /* Check the parameters */
01158   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01159
01160   switch (Channel)
01161   {
01162     case TIM_CHANNEL_1:
01163     {
01164       /* Enable the TIM Capture/Compare 1 interrupt */
01165       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01166     }
01167     break;
01168
01169     case TIM_CHANNEL_2:
01170     {
01171       /* Enable the TIM Capture/Compare 2 interrupt */
01172       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01173     }
01174     break;
01175
01176     case TIM_CHANNEL_3:
01177     {
01178       /* Enable the TIM Capture/Compare 3 interrupt */
01179       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01180     }
01181     break;
01182
01183     case TIM_CHANNEL_4:
01184     {
01185       /* Enable the TIM Capture/Compare 4 interrupt */
01186       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01187     }
01188     break;
01189
01190     default:
01191     break;
01192   }
01193
01194   /* Enable the Capture compare channel */
01195   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01196
01197   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01198   {
01199     /* Enable the main output */
01200     __HAL_TIM_MOE_ENABLE(htim);
01201   }
01202
01203   /* Enable the Peripheral */
01204   __HAL_TIM_ENABLE(htim);
01205
01206   /* Return function status */
01207   return HAL_OK;
01208 }
01209
01210 /**
01211   * @brief  Stops the PWM signal generation in interrupt mode.
01212   * @param  htim : TIM handle
01213   * @param  Channel : TIM Channels to be disabled
01214   *          This parameter can be one of the following values:
01215   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01216   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01217   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01218   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01219   * @retval HAL status
01220 */
01221 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01222 {
01223   /* Check the parameters */
01224   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01225
01226   switch (Channel)
01227   {
01228     case TIM_CHANNEL_1:
01229     {
01230       /* Disable the TIM Capture/Compare 1 interrupt */
01231       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01232     }
01233     break;
01234
01235     case TIM_CHANNEL_2:
01236     {
01237       /* Disable the TIM Capture/Compare 2 interrupt */
01238       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01239     }
01240     break;
01241
01242     case TIM_CHANNEL_3:
01243     {
01244       /* Disable the TIM Capture/Compare 3 interrupt */
01245       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01246     }
01247     break;
01248
01249     case TIM_CHANNEL_4:
01250     {
01251       /* Disable the TIM Capture/Compare 4 interrupt */
01252       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01253     }
01254     break;
01255
01256     default:
01257     break;
01258   }
01259
01260   /* Disable the Capture compare channel */
01261   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01262
01263   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01264   {
01265     /* Disable the Main Ouput */
01266     __HAL_TIM_MOE_DISABLE(htim);
01267   }
01268
01269   /* Disable the Peripheral */
01270   __HAL_TIM_DISABLE(htim);
01271
01272   /* Return function status */
01273   return HAL_OK;
01274 }
01275
01276 /**
01277   * @brief  Starts the TIM PWM signal generation in DMA mode.
01278   * @param  htim : TIM handle
01279   * @param  Channel : TIM Channels to be enabled
01280   *          This parameter can be one of the following values:
01281   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01282   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01283   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01284   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01285   * @param  pData : The source Buffer address.
01286   * @param  Length : The length of data to be transferred from memory to TIM peripheral
01287   * @retval HAL status
01288 */
01289 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01290 {
01291   /* Check the parameters */
01292   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01293
01294   if((htim->State == HAL_TIM_STATE_BUSY))
01295   {
01296      return HAL_BUSY;
01297   }
01298   else if((htim->State == HAL_TIM_STATE_READY))
01299   {
01300     if(((uint32_t)pData == 0U) && (Length > 0U))
01301     {
01302       return HAL_ERROR;
01303     }
01304     else
01305     {
01306       htim->State = HAL_TIM_STATE_BUSY;
01307     }
01308   }
01309   switch (Channel)
01310   {
01311     case TIM_CHANNEL_1:
01312     {
01313       /* Set the DMA Period elapsed callback */
01314       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01315
01316       /* Set the DMA error callback */
01317       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01318
01319       /* Enable the DMA channel */
01320       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01321
01322       /* Enable the TIM Capture/Compare 1 DMA request */
01323       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01324     }
01325     break;
01326
01327     case TIM_CHANNEL_2:
01328     {
01329       /* Set the DMA Period elapsed callback */
01330       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01331
01332       /* Set the DMA error callback */
01333       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01334
01335       /* Enable the DMA channel */
01336       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01337
01338       /* Enable the TIM Capture/Compare 2 DMA request */
01339       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01340     }
01341     break;
01342
01343     case TIM_CHANNEL_3:
01344     {
01345       /* Set the DMA Period elapsed callback */
01346       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01347
01348       /* Set the DMA error callback */
01349       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01350
01351       /* Enable the DMA channel */
01352       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01353
01354       /* Enable the TIM Output Capture/Compare 3 request */
01355       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01356     }
01357     break;
01358
01359     case TIM_CHANNEL_4:
01360     {
01361      /* Set the DMA Period elapsed callback */
01362       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01363
01364       /* Set the DMA error callback */
01365       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01366
01367       /* Enable the DMA channel */
01368       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01369
01370       /* Enable the TIM Capture/Compare 4 DMA request */
01371       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01372     }
01373     break;
01374
01375     default:
01376     break;
01377   }
01378
01379   /* Enable the Capture compare channel */
01380   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01381
01382   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01383   {
01384     /* Enable the main output */
01385     __HAL_TIM_MOE_ENABLE(htim);
01386   }
01387
01388   /* Enable the Peripheral */
01389   __HAL_TIM_ENABLE(htim);
01390
01391   /* Return function status */
01392   return HAL_OK;
01393 }
01394
01395 /**
01396   * @brief  Stops the TIM PWM signal generation in DMA mode.
01397   * @param  htim : TIM handle
01398   * @param  Channel : TIM Channels to be disabled
01399   *          This parameter can be one of the following values:
01400   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01401   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01402   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01403   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01404   * @retval HAL status
01405 */
01406 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01407 {
01408   /* Check the parameters */
01409   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01410
01411   switch (Channel)
01412   {
01413     case TIM_CHANNEL_1:
01414     {
01415       /* Disable the TIM Capture/Compare 1 DMA request */
01416       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01417     }
01418     break;
01419
01420     case TIM_CHANNEL_2:
01421     {
01422       /* Disable the TIM Capture/Compare 2 DMA request */
01423       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01424     }
01425     break;
01426
01427     case TIM_CHANNEL_3:
01428     {
01429       /* Disable the TIM Capture/Compare 3 DMA request */
01430       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01431     }
01432     break;
01433
01434     case TIM_CHANNEL_4:
01435     {
01436       /* Disable the TIM Capture/Compare 4 interrupt */
01437       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01438     }
01439     break;
01440
01441     default:
01442     break;
01443   }
01444
01445   /* Disable the Capture compare channel */
01446   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01447
01448   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
01449   {
01450     /* Disable the Main Ouput */
01451     __HAL_TIM_MOE_DISABLE(htim);
01452   }
01453
01454   /* Disable the Peripheral */
01455   __HAL_TIM_DISABLE(htim);
01456
01457   /* Change the htim state */
01458   htim->State = HAL_TIM_STATE_READY;
01459
01460   /* Return function status */
01461   return HAL_OK;
01462 }
01463
01464 /**
01465   * @}
01466   */
01467
01468 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
01469  *  @brief    Time Input Capture functions
01470  *
01471 @verbatim
01472   ==============================================================================
01473               ##### Time Input Capture functions #####
01474   ==============================================================================
01475  [..]
01476    This section provides functions allowing to:
01477    (+) Initialize and configure the TIM Input Capture.
01478    (+) De-initialize the TIM Input Capture.
01479    (+) Start the Time Input Capture.
01480    (+) Stop the Time Input Capture.
01481    (+) Start the Time Input Capture and enable interrupt.
01482    (+) Stop the Time Input Capture and disable interrupt.
01483    (+) Start the Time Input Capture and enable DMA transfer.
01484    (+) Stop the Time Input Capture and disable DMA transfer.
01485
01486 @endverbatim
01487   * @{
01488   */
01489 /**
01490   * @brief  Initializes the TIM Input Capture Time base according to the specified
01491   *         parameters in the TIM_HandleTypeDef and create the associated handle.
01492   * @param  htim : TIM Input Capture handle
01493   * @retval HAL status
01494   */
01495 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
01496 {
01497   /* Check the TIM handle allocation */
01498   if(htim == NULL)
01499   {
01500     return HAL_ERROR;
01501   }
01502
01503   /* Check the parameters */
01504   assert_param(IS_TIM_INSTANCE(htim->Instance));
01505   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01506   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01507   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01508
01509   if(htim->State == HAL_TIM_STATE_RESET)
01510   {
01511     /* Allocate lock resource and initialize it */
01512     htim->Lock = HAL_UNLOCKED;
01513
01514     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01515     HAL_TIM_IC_MspInit(htim);
01516   }
01517
01518   /* Set the TIM state */
01519   htim->State= HAL_TIM_STATE_BUSY;
01520
01521   /* Init the base time for the input capture */
01522   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01523
01524   /* Initialize the TIM state*/
01525   htim->State= HAL_TIM_STATE_READY;
01526
01527   return HAL_OK;
01528 }
01529
01530 /**
01531   * @brief  DeInitializes the TIM peripheral
01532   * @param  htim : TIM Input Capture handle
01533   * @retval HAL status
01534   */
01535 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
01536 {
01537   /* Check the parameters */
01538   assert_param(IS_TIM_INSTANCE(htim->Instance));
01539
01540   htim->State = HAL_TIM_STATE_BUSY;
01541
01542   /* Disable the TIM Peripheral Clock */
01543   __HAL_TIM_DISABLE(htim);
01544
01545   /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
01546   HAL_TIM_IC_MspDeInit(htim);
01547
01548   /* Change TIM state */
01549   htim->State = HAL_TIM_STATE_RESET;
01550
01551   /* Release Lock */
01552   __HAL_UNLOCK(htim);
01553
01554   return HAL_OK;
01555 }
01556
01557 /**
01558   * @brief  Initializes the TIM Input Capture MSP.
01559   * @param  htim : TIM handle
01560   * @retval None
01561   */
01562 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
01563 {
01564   /* Prevent unused argument(s) compilation warning */
01565   UNUSED(htim);
01566   /* NOTE : This function Should not be modified, when the callback is needed,
01567             the HAL_TIM_IC_MspInit could be implemented in the user file
01568    */
01569 }
01570
01571 /**
01572   * @brief  DeInitializes TIM Input Capture MSP.
01573   * @param  htim : TIM handle
01574   * @retval None
01575   */
01576 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
01577 {
01578   /* Prevent unused argument(s) compilation warning */
01579   UNUSED(htim);
01580   /* NOTE : This function Should not be modified, when the callback is needed,
01581             the HAL_TIM_IC_MspDeInit could be implemented in the user file
01582    */
01583 }
01584
01585 /**
01586   * @brief  Starts the TIM Input Capture measurement.
01587   * @param  htim : TIM Input Capture handle
01588   * @param  Channel : TIM Channels to be enabled
01589   *          This parameter can be one of the following values:
01590   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01591   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01592   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01593   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01594   * @retval HAL status
01595 */
01596 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
01597 {
01598   /* Check the parameters */
01599   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01600
01601   /* Enable the Input Capture channel */
01602   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01603
01604   /* Enable the Peripheral */
01605   __HAL_TIM_ENABLE(htim);
01606
01607   /* Return function status */
01608   return HAL_OK;
01609 }
01610
01611 /**
01612   * @brief  Stops the TIM Input Capture measurement.
01613   * @param  htim : TIM handle
01614   * @param  Channel : TIM Channels to be disabled
01615   *          This parameter can be one of the following values:
01616   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01617   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01618   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01619   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01620   * @retval HAL status
01621 */
01622 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
01623 {
01624   /* Check the parameters */
01625   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01626
01627   /* Disable the Input Capture channel */
01628   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01629
01630   /* Disable the Peripheral */
01631   __HAL_TIM_DISABLE(htim);
01632
01633   /* Return function status */
01634   return HAL_OK;
01635 }
01636
01637 /**
01638   * @brief  Starts the TIM Input Capture measurement in interrupt mode.
01639   * @param  htim : TIM Input Capture handle
01640   * @param  Channel : TIM Channels to be enabled
01641   *          This parameter can be one of the following values:
01642   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01643   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01644   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01645   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01646   * @retval HAL status
01647 */
01648 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01649 {
01650   /* Check the parameters */
01651   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01652
01653   switch (Channel)
01654   {
01655     case TIM_CHANNEL_1:
01656     {
01657       /* Enable the TIM Capture/Compare 1 interrupt */
01658       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01659     }
01660     break;
01661
01662     case TIM_CHANNEL_2:
01663     {
01664       /* Enable the TIM Capture/Compare 2 interrupt */
01665       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01666     }
01667     break;
01668
01669     case TIM_CHANNEL_3:
01670     {
01671       /* Enable the TIM Capture/Compare 3 interrupt */
01672       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01673     }
01674     break;
01675
01676     case TIM_CHANNEL_4:
01677     {
01678       /* Enable the TIM Capture/Compare 4 interrupt */
01679       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01680     }
01681     break;
01682
01683     default:
01684     break;
01685   }
01686   /* Enable the Input Capture channel */
01687   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01688
01689   /* Enable the Peripheral */
01690   __HAL_TIM_ENABLE(htim);
01691
01692   /* Return function status */
01693   return HAL_OK;
01694 }
01695
01696 /**
01697   * @brief  Stops the TIM Input Capture measurement in interrupt mode.
01698   * @param  htim : TIM handle
01699   * @param  Channel : TIM Channels to be disabled
01700   *          This parameter can be one of the following values:
01701   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01702   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01703   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01704   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01705   * @retval HAL status
01706 */
01707 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
01708 {
01709   /* Check the parameters */
01710   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01711
01712   switch (Channel)
01713   {
01714     case TIM_CHANNEL_1:
01715     {
01716       /* Disable the TIM Capture/Compare 1 interrupt */
01717       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01718     }
01719     break;
01720
01721     case TIM_CHANNEL_2:
01722     {
01723       /* Disable the TIM Capture/Compare 2 interrupt */
01724       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01725     }
01726     break;
01727
01728     case TIM_CHANNEL_3:
01729     {
01730       /* Disable the TIM Capture/Compare 3 interrupt */
01731       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01732     }
01733     break;
01734
01735     case TIM_CHANNEL_4:
01736     {
01737       /* Disable the TIM Capture/Compare 4 interrupt */
01738       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01739     }
01740     break;
01741
01742     default:
01743     break;
01744   }
01745
01746   /* Disable the Input Capture channel */
01747   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01748
01749   /* Disable the Peripheral */
01750   __HAL_TIM_DISABLE(htim);
01751
01752   /* Return function status */
01753   return HAL_OK;
01754 }
01755
01756 /**
01757   * @brief  Starts the TIM Input Capture measurement in DMA mode.
01758   * @param  htim : TIM Input Capture handle
01759   * @param  Channel : TIM Channels to be enabled
01760   *          This parameter can be one of the following values:
01761   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01762   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01763   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01764   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01765   * @param  pData : The destination Buffer address.
01766   * @param  Length : The length of data to be transferred from TIM peripheral to memory.
01767   * @retval HAL status
01768 */
01769 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01770 {
01771   /* Check the parameters */
01772   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01773   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01774
01775   if((htim->State == HAL_TIM_STATE_BUSY))
01776   {
01777      return HAL_BUSY;
01778   }
01779   else if((htim->State == HAL_TIM_STATE_READY))
01780   {
01781     if((pData == 0U) && (Length > 0U))
01782     {
01783       return HAL_ERROR;
01784     }
01785     else
01786     {
01787       htim->State = HAL_TIM_STATE_BUSY;
01788     }
01789   }
01790
01791   switch (Channel)
01792   {
01793     case TIM_CHANNEL_1:
01794     {
01795       /* Set the DMA Period elapsed callback */
01796       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
01797
01798       /* Set the DMA error callback */
01799       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01800
01801       /* Enable the DMA channel */
01802       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
01803
01804       /* Enable the TIM Capture/Compare 1 DMA request */
01805       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01806     }
01807     break;
01808
01809     case TIM_CHANNEL_2:
01810     {
01811       /* Set the DMA Period elapsed callback */
01812       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
01813
01814       /* Set the DMA error callback */
01815       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01816
01817       /* Enable the DMA channel */
01818       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
01819
01820       /* Enable the TIM Capture/Compare 2  DMA request */
01821       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01822     }
01823     break;
01824
01825     case TIM_CHANNEL_3:
01826     {
01827       /* Set the DMA Period elapsed callback */
01828       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
01829
01830       /* Set the DMA error callback */
01831       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01832
01833       /* Enable the DMA channel */
01834       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
01835
01836       /* Enable the TIM Capture/Compare 3  DMA request */
01837       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01838     }
01839     break;
01840
01841     case TIM_CHANNEL_4:
01842     {
01843       /* Set the DMA Period elapsed callback */
01844       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
01845
01846       /* Set the DMA error callback */
01847       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01848
01849       /* Enable the DMA channel */
01850       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
01851
01852       /* Enable the TIM Capture/Compare 4  DMA request */
01853       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01854     }
01855     break;
01856
01857     default:
01858     break;
01859   }
01860
01861   /* Enable the Input Capture channel */
01862   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
01863
01864   /* Enable the Peripheral */
01865   __HAL_TIM_ENABLE(htim);
01866
01867   /* Return function status */
01868   return HAL_OK;
01869 }
01870
01871 /**
01872   * @brief  Stops the TIM Input Capture measurement in DMA mode.
01873   * @param  htim : TIM Input Capture handle
01874   * @param  Channel : TIM Channels to be disabled
01875   *          This parameter can be one of the following values:
01876   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01877   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01878   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01879   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01880   * @retval HAL status
01881 */
01882 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01883 {
01884   /* Check the parameters */
01885   assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
01886   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
01887
01888   switch (Channel)
01889   {
01890     case TIM_CHANNEL_1:
01891     {
01892       /* Disable the TIM Capture/Compare 1 DMA request */
01893       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01894     }
01895     break;
01896
01897     case TIM_CHANNEL_2:
01898     {
01899       /* Disable the TIM Capture/Compare 2 DMA request */
01900       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01901     }
01902     break;
01903
01904     case TIM_CHANNEL_3:
01905     {
01906       /* Disable the TIM Capture/Compare 3  DMA request */
01907       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01908     }
01909     break;
01910
01911     case TIM_CHANNEL_4:
01912     {
01913       /* Disable the TIM Capture/Compare 4  DMA request */
01914       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01915     }
01916     break;
01917
01918     default:
01919     break;
01920   }
01921
01922   /* Disable the Input Capture channel */
01923   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
01924
01925   /* Disable the Peripheral */
01926   __HAL_TIM_DISABLE(htim);
01927
01928   /* Change the htim state */
01929   htim->State = HAL_TIM_STATE_READY;
01930
01931   /* Return function status */
01932   return HAL_OK;
01933 }
01934 /**
01935   * @}
01936   */
01937
01938 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
01939  *  @brief    Time One Pulse functions
01940  *
01941 @verbatim
01942   ==============================================================================
01943                         ##### Time One Pulse functions #####
01944   ==============================================================================
01945   [..]
01946     This section provides functions allowing to:
01947     (+) Initialize and configure the TIM One Pulse.
01948     (+) De-initialize the TIM One Pulse.
01949     (+) Start the Time One Pulse.
01950     (+) Stop the Time One Pulse.
01951     (+) Start the Time One Pulse and enable interrupt.
01952     (+) Stop the Time One Pulse and disable interrupt.
01953     (+) Start the Time One Pulse and enable DMA transfer.
01954     (+) Stop the Time One Pulse and disable DMA transfer.
01955
01956 @endverbatim
01957   * @{
01958   */
01959 /**
01960   * @brief  Initializes the TIM One Pulse Time Base according to the specified
01961   *         parameters in the TIM_HandleTypeDef and create the associated handle.
01962   * @param  htim : TIM OnePulse handle
01963   * @param  OnePulseMode : Select the One pulse mode.
01964   *         This parameter can be one of the following values:
01965   *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
01966   *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
01967   * @retval HAL status
01968   */
01969 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
01970 {
01971   /* Check the TIM handle allocation */
01972   if(htim == NULL)
01973   {
01974     return HAL_ERROR;
01975   }
01976
01977   /* Check the parameters */
01978   assert_param(IS_TIM_INSTANCE(htim->Instance));
01979   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
01980   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
01981   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
01982   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
01983
01984   if(htim->State == HAL_TIM_STATE_RESET)
01985   {
01986     /* Allocate lock resource and initialize it */
01987     htim->Lock = HAL_UNLOCKED;
01988
01989     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
01990     HAL_TIM_OnePulse_MspInit(htim);
01991   }
01992
01993   /* Set the TIM state */
01994   htim->State= HAL_TIM_STATE_BUSY;
01995
01996   /* Configure the Time base in the One Pulse Mode */
01997   TIM_Base_SetConfig(htim->Instance, &htim->Init);
01998
01999   /* Reset the OPM Bit */
02000   htim->Instance->CR1 &= ~TIM_CR1_OPM;
02001
02002   /* Configure the OPM Mode */
02003   htim->Instance->CR1 |= OnePulseMode;
02004
02005   /* Initialize the TIM state*/
02006   htim->State= HAL_TIM_STATE_READY;
02007
02008   return HAL_OK;
02009 }
02010
02011 /**
02012   * @brief  DeInitializes the TIM One Pulse
02013   * @param  htim : TIM One Pulse handle
02014   * @retval HAL status
02015   */
02016 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
02017 {
02018   /* Check the parameters */
02019   assert_param(IS_TIM_INSTANCE(htim->Instance));
02020
02021   htim->State = HAL_TIM_STATE_BUSY;
02022
02023   /* Disable the TIM Peripheral Clock */
02024   __HAL_TIM_DISABLE(htim);
02025
02026   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02027   HAL_TIM_OnePulse_MspDeInit(htim);
02028
02029   /* Change TIM state */
02030   htim->State = HAL_TIM_STATE_RESET;
02031
02032   /* Release Lock */
02033   __HAL_UNLOCK(htim);
02034
02035   return HAL_OK;
02036 }
02037
02038 /**
02039   * @brief  Initializes the TIM One Pulse MSP.
02040   * @param  htim : TIM handle
02041   * @retval None
02042   */
02043 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
02044 {
02045   /* Prevent unused argument(s) compilation warning */
02046   UNUSED(htim);
02047   /* NOTE : This function Should not be modified, when the callback is needed,
02048             the HAL_TIM_OnePulse_MspInit could be implemented in the user file
02049    */
02050 }
02051
02052 /**
02053   * @brief  DeInitializes TIM One Pulse MSP.
02054   * @param  htim : TIM handle
02055   * @retval None
02056   */
02057 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
02058 {
02059   /* Prevent unused argument(s) compilation warning */
02060   UNUSED(htim);
02061   /* NOTE : This function Should not be modified, when the callback is needed,
02062             the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
02063    */
02064 }
02065
02066 /**
02067   * @brief  Starts the TIM One Pulse signal generation.
02068   * @param  htim : TIM One Pulse handle
02069   * @param  OutputChannel : TIM Channels to be enabled
02070   *          This parameter can be one of the following values:
02071   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02072   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02073   * @retval HAL status
02074 */
02075 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02076 {
02077   /* Enable the Capture compare and the Input Capture channels
02078     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02079     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02080     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02081     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02082
02083     No need to enable the counter, it's enabled automatically by hardware
02084     (the counter starts in response to a stimulus and generate a pulse */
02085
02086   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02087   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02088
02089   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02090   {
02091     /* Enable the main output */
02092     __HAL_TIM_MOE_ENABLE(htim);
02093   }
02094
02095   /* Return function status */
02096   return HAL_OK;
02097 }
02098
02099 /**
02100   * @brief  Stops the TIM One Pulse signal generation.
02101   * @param  htim : TIM One Pulse handle
02102   * @param  OutputChannel : TIM Channels to be disable
02103   *          This parameter can be one of the following values:
02104   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02105   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02106   * @retval HAL status
02107 */
02108 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02109 {
02110   /* Disable the Capture compare and the Input Capture channels
02111   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02112   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02113   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02114   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02115
02116   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02117   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02118
02119   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02120   {
02121     /* Disable the Main Ouput */
02122     __HAL_TIM_MOE_DISABLE(htim);
02123   }
02124
02125   /* Disable the Peripheral */
02126   __HAL_TIM_DISABLE(htim);
02127
02128   /* Return function status */
02129   return HAL_OK;
02130 }
02131
02132 /**
02133   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
02134   * @param  htim : TIM One Pulse handle
02135   * @param  OutputChannel : TIM Channels to be enabled
02136   *          This parameter can be one of the following values:
02137   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02138   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02139   * @retval HAL status
02140 */
02141 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02142 {
02143   /* Enable the Capture compare and the Input Capture channels
02144     (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02145     if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02146     if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02147     in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
02148
02149     No need to enable the counter, it's enabled automatically by hardware
02150     (the counter starts in response to a stimulus and generate a pulse */
02151
02152   /* Enable the TIM Capture/Compare 1 interrupt */
02153   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02154
02155   /* Enable the TIM Capture/Compare 2 interrupt */
02156   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02157
02158   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02159   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02160
02161   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02162   {
02163     /* Enable the main output */
02164     __HAL_TIM_MOE_ENABLE(htim);
02165   }
02166
02167   /* Return function status */
02168   return HAL_OK;
02169 }
02170
02171 /**
02172   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
02173   * @param  htim : TIM One Pulse handle
02174   * @param  OutputChannel : TIM Channels to be enabled
02175   *          This parameter can be one of the following values:
02176   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02177   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02178   * @retval HAL status
02179 */
02180 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
02181 {
02182   /* Disable the TIM Capture/Compare 1 interrupt */
02183   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02184
02185   /* Disable the TIM Capture/Compare 2 interrupt */
02186   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02187
02188   /* Disable the Capture compare and the Input Capture channels
02189   (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
02190   if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
02191   if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
02192   in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
02193   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02194   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02195
02196   if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
02197   {
02198     /* Disable the Main Ouput */
02199     __HAL_TIM_MOE_DISABLE(htim);
02200   }
02201
02202   /* Disable the Peripheral */
02203    __HAL_TIM_DISABLE(htim);
02204
02205   /* Return function status */
02206   return HAL_OK;
02207 }
02208
02209 /**
02210   * @}
02211   */
02212
02213 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
02214  *  @brief    Time Encoder functions
02215  *
02216 @verbatim
02217   ==============================================================================
02218                           ##### Time Encoder functions #####
02219   ==============================================================================
02220   [..]
02221     This section provides functions allowing to:
02222     (+) Initialize and configure the TIM Encoder.
02223     (+) De-initialize the TIM Encoder.
02224     (+) Start the Time Encoder.
02225     (+) Stop the Time Encoder.
02226     (+) Start the Time Encoder and enable interrupt.
02227     (+) Stop the Time Encoder and disable interrupt.
02228     (+) Start the Time Encoder and enable DMA transfer.
02229     (+) Stop the Time Encoder and disable DMA transfer.
02230
02231 @endverbatim
02232   * @{
02233   */
02234 /**
02235   * @brief  Initializes the TIM Encoder Interface and create the associated handle.
02236   * @param  htim : TIM Encoder Interface handle
02237   * @param  sConfig : TIM Encoder Interface configuration structure
02238   * @retval HAL status
02239   */
02240 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
02241 {
02242   uint32_t tmpsmcr = 0U;
02243   uint32_t tmpccmr1 = 0U;
02244   uint32_t tmpccer = 0U;
02245
02246   /* Check the TIM handle allocation */
02247   if(htim == NULL)
02248   {
02249     return HAL_ERROR;
02250   }
02251
02252   /* Check the parameters */
02253   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02254   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
02255   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
02256   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
02257   assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
02258   assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
02259   assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
02260   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
02261   assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
02262   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
02263   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
02264   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
02265   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
02266
02267   if(htim->State == HAL_TIM_STATE_RESET)
02268   {
02269     /* Allocate lock resource and initialize it */
02270     htim->Lock = HAL_UNLOCKED;
02271
02272     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
02273     HAL_TIM_Encoder_MspInit(htim);
02274   }
02275
02276   /* Set the TIM state */
02277   htim->State= HAL_TIM_STATE_BUSY;
02278
02279   /* Reset the SMS bits */
02280   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
02281
02282   /* Configure the Time base in the Encoder Mode */
02283   TIM_Base_SetConfig(htim->Instance, &htim->Init);
02284
02285   /* Get the TIMx SMCR register value */
02286   tmpsmcr = htim->Instance->SMCR;
02287
02288   /* Get the TIMx CCMR1 register value */
02289   tmpccmr1 = htim->Instance->CCMR1;
02290
02291   /* Get the TIMx CCER register value */
02292   tmpccer = htim->Instance->CCER;
02293
02294   /* Set the encoder Mode */
02295   tmpsmcr |= sConfig->EncoderMode;
02296
02297   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
02298   tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
02299   tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
02300
02301   /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
02302   tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
02303   tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
02304   tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
02305   tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
02306
02307   /* Set the TI1 and the TI2 Polarities */
02308   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
02309   tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
02310   tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
02311
02312   /* Write to TIMx SMCR */
02313   htim->Instance->SMCR = tmpsmcr;
02314
02315   /* Write to TIMx CCMR1 */
02316   htim->Instance->CCMR1 = tmpccmr1;
02317
02318   /* Write to TIMx CCER */
02319   htim->Instance->CCER = tmpccer;
02320
02321   /* Initialize the TIM state*/
02322   htim->State= HAL_TIM_STATE_READY;
02323
02324   return HAL_OK;
02325 }
02326
02327
02328 /**
02329   * @brief  DeInitializes the TIM Encoder interface
02330   * @param  htim : TIM Encoder handle
02331   * @retval HAL status
02332   */
02333 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
02334 {
02335   /* Check the parameters */
02336   assert_param(IS_TIM_INSTANCE(htim->Instance));
02337
02338   htim->State = HAL_TIM_STATE_BUSY;
02339
02340   /* Disable the TIM Peripheral Clock */
02341   __HAL_TIM_DISABLE(htim);
02342
02343   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
02344   HAL_TIM_Encoder_MspDeInit(htim);
02345
02346   /* Change TIM state */
02347   htim->State = HAL_TIM_STATE_RESET;
02348
02349   /* Release Lock */
02350   __HAL_UNLOCK(htim);
02351
02352   return HAL_OK;
02353 }
02354
02355 /**
02356   * @brief  Initializes the TIM Encoder Interface MSP.
02357   * @param  htim : TIM handle
02358   * @retval None
02359   */
02360 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
02361 {
02362   /* Prevent unused argument(s) compilation warning */
02363   UNUSED(htim);
02364   /* NOTE : This function Should not be modified, when the callback is needed,
02365             the HAL_TIM_Encoder_MspInit could be implemented in the user file
02366    */
02367 }
02368
02369 /**
02370   * @brief  DeInitializes TIM Encoder Interface MSP.
02371   * @param  htim : TIM handle
02372   * @retval None
02373   */
02374 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
02375 {
02376   /* Prevent unused argument(s) compilation warning */
02377   UNUSED(htim);
02378   /* NOTE : This function Should not be modified, when the callback is needed,
02379             the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
02380    */
02381 }
02382
02383 /**
02384   * @brief  Starts the TIM Encoder Interface.
02385   * @param  htim : TIM Encoder Interface handle
02386   * @param  Channel : TIM Channels to be enabled
02387   *          This parameter can be one of the following values:
02388   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02389   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02390   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02391   * @retval HAL status
02392 */
02393 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
02394 {
02395   /* Check the parameters */
02396   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02397
02398   /* Enable the encoder interface channels */
02399   switch (Channel)
02400   {
02401     case TIM_CHANNEL_1:
02402   {
02403     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02404       break;
02405   }
02406     case TIM_CHANNEL_2:
02407   {
02408     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02409       break;
02410   }
02411     default :
02412   {
02413      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02414      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02415      break;
02416     }
02417   }
02418   /* Enable the Peripheral */
02419   __HAL_TIM_ENABLE(htim);
02420
02421   /* Return function status */
02422   return HAL_OK;
02423 }
02424
02425 /**
02426   * @brief  Stops the TIM Encoder Interface.
02427   * @param  htim : TIM Encoder Interface handle
02428   * @param  Channel : TIM Channels to be disabled
02429   *          This parameter can be one of the following values:
02430   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02431   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02432   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02433   * @retval HAL status
02434 */
02435 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
02436 {
02437   /* Check the parameters */
02438     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02439
02440    /* Disable the Input Capture channels 1 and 2
02441     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02442   switch (Channel)
02443   {
02444     case TIM_CHANNEL_1:
02445   {
02446      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02447       break;
02448   }
02449     case TIM_CHANNEL_2:
02450   {
02451     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02452       break;
02453   }
02454     default :
02455   {
02456     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02457     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02458      break;
02459     }
02460   }
02461
02462   /* Disable the Peripheral */
02463   __HAL_TIM_DISABLE(htim);
02464
02465   /* Return function status */
02466   return HAL_OK;
02467 }
02468
02469 /**
02470   * @brief  Starts the TIM Encoder Interface in interrupt mode.
02471   * @param  htim : TIM Encoder Interface handle
02472   * @param  Channel : TIM Channels to be enabled
02473   *          This parameter can be one of the following values:
02474   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02475   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02476   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02477   * @retval HAL status
02478 */
02479 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02480 {
02481   /* Check the parameters */
02482   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02483
02484   /* Enable the encoder interface channels */
02485   /* Enable the capture compare Interrupts 1 and/or 2 */
02486   switch (Channel)
02487   {
02488     case TIM_CHANNEL_1:
02489   {
02490     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02491     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02492       break;
02493   }
02494     case TIM_CHANNEL_2:
02495   {
02496     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02497     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02498       break;
02499   }
02500     default :
02501   {
02502      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02503      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02504      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
02505      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
02506      break;
02507     }
02508   }
02509
02510   /* Enable the Peripheral */
02511   __HAL_TIM_ENABLE(htim);
02512
02513   /* Return function status */
02514   return HAL_OK;
02515 }
02516
02517 /**
02518   * @brief  Stops the TIM Encoder Interface in interrupt mode.
02519   * @param  htim : TIM Encoder Interface handle
02520   * @param  Channel : TIM Channels to be disabled
02521   *          This parameter can be one of the following values:
02522   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02523   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02524   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02525   * @retval HAL status
02526 */
02527 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
02528 {
02529   /* Check the parameters */
02530   assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02531
02532   /* Disable the Input Capture channels 1 and 2
02533     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02534   if(Channel == TIM_CHANNEL_1)
02535   {
02536     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02537
02538     /* Disable the capture compare Interrupts 1 */
02539   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02540   }
02541   else if(Channel == TIM_CHANNEL_2)
02542   {
02543     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02544
02545     /* Disable the capture compare Interrupts 2 */
02546   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02547   }
02548   else
02549   {
02550     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02551     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02552
02553     /* Disable the capture compare Interrupts 1 and 2 */
02554     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
02555     __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
02556   }
02557
02558   /* Disable the Peripheral */
02559   __HAL_TIM_DISABLE(htim);
02560
02561   /* Change the htim state */
02562   htim->State = HAL_TIM_STATE_READY;
02563
02564   /* Return function status */
02565   return HAL_OK;
02566 }
02567
02568 /**
02569   * @brief  Starts the TIM Encoder Interface in DMA mode.
02570   * @param  htim : TIM Encoder Interface handle
02571   * @param  Channel : TIM Channels to be enabled
02572   *          This parameter can be one of the following values:
02573   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02574   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02575   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02576   * @param  pData1 : The destination Buffer address for IC1.
02577   * @param  pData2 : The destination Buffer address for IC2.
02578   * @param  Length : The length of data to be transferred from TIM peripheral to memory.
02579   * @retval HAL status
02580 */
02581 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
02582 {
02583   /* Check the parameters */
02584   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02585
02586   if((htim->State == HAL_TIM_STATE_BUSY))
02587   {
02588      return HAL_BUSY;
02589   }
02590   else if((htim->State == HAL_TIM_STATE_READY))
02591   {
02592     if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
02593     {
02594       return HAL_ERROR;
02595     }
02596     else
02597     {
02598       htim->State = HAL_TIM_STATE_BUSY;
02599     }
02600   }
02601
02602   switch (Channel)
02603   {
02604     case TIM_CHANNEL_1:
02605     {
02606       /* Set the DMA Period elapsed callback */
02607       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02608
02609       /* Set the DMA error callback */
02610       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02611
02612       /* Enable the DMA channel */
02613       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
02614
02615       /* Enable the TIM Input Capture DMA request */
02616       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02617
02618       /* Enable the Peripheral */
02619       __HAL_TIM_ENABLE(htim);
02620
02621       /* Enable the Capture compare channel */
02622       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02623     }
02624     break;
02625
02626     case TIM_CHANNEL_2:
02627     {
02628       /* Set the DMA Period elapsed callback */
02629       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02630
02631       /* Set the DMA error callback */
02632       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
02633       /* Enable the DMA channel */
02634       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02635
02636       /* Enable the TIM Input Capture  DMA request */
02637       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02638
02639       /* Enable the Peripheral */
02640       __HAL_TIM_ENABLE(htim);
02641
02642       /* Enable the Capture compare channel */
02643       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02644     }
02645     break;
02646
02647     case TIM_CHANNEL_ALL:
02648     {
02649       /* Set the DMA Period elapsed callback */
02650       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
02651
02652       /* Set the DMA error callback */
02653       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
02654
02655       /* Enable the DMA channel */
02656       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
02657
02658       /* Set the DMA Period elapsed callback */
02659       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
02660
02661       /* Set the DMA error callback */
02662       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
02663
02664       /* Enable the DMA channel */
02665       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
02666
02667      /* Enable the Peripheral */
02668       __HAL_TIM_ENABLE(htim);
02669
02670       /* Enable the Capture compare channel */
02671       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
02672       TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
02673
02674       /* Enable the TIM Input Capture  DMA request */
02675       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
02676       /* Enable the TIM Input Capture  DMA request */
02677       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
02678     }
02679     break;
02680
02681     default:
02682     break;
02683   }
02684   /* Return function status */
02685   return HAL_OK;
02686 }
02687
02688 /**
02689   * @brief  Stops the TIM Encoder Interface in DMA mode.
02690   * @param  htim : TIM Encoder Interface handle
02691   * @param  Channel : TIM Channels to be enabled
02692   *          This parameter can be one of the following values:
02693   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02694   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02695   *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
02696   * @retval HAL status
02697 */
02698 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
02699 {
02700   /* Check the parameters */
02701   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
02702
02703   /* Disable the Input Capture channels 1 and 2
02704     (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
02705   if(Channel == TIM_CHANNEL_1)
02706   {
02707     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02708
02709     /* Disable the capture compare DMA Request 1 */
02710     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02711   }
02712   else if(Channel == TIM_CHANNEL_2)
02713   {
02714     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02715
02716     /* Disable the capture compare DMA Request 2 */
02717     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02718   }
02719   else
02720   {
02721     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
02722     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
02723
02724     /* Disable the capture compare DMA Request 1 and 2 */
02725     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
02726     __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
02727   }
02728
02729   /* Disable the Peripheral */
02730   __HAL_TIM_DISABLE(htim);
02731
02732   /* Change the htim state */
02733   htim->State = HAL_TIM_STATE_READY;
02734
02735   /* Return function status */
02736   return HAL_OK;
02737 }
02738
02739 /**
02740   * @}
02741   */
02742 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
02743  *  @brief    IRQ handler management
02744  *
02745 @verbatim
02746   ==============================================================================
02747                         ##### IRQ handler management #####
02748   ==============================================================================
02749   [..]
02750     This section provides Timer IRQ handler function.
02751
02752 @endverbatim
02753   * @{
02754   */
02755 /**
02756   * @brief  This function handles TIM interrupts requests.
02757   * @param  htim : TIM  handle
02758   * @retval None
02759   */
02760 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
02761 {
02762   /* Capture compare 1 event */
02763   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
02764   {
02765     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
02766     {
02767       {
02768         __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
02769         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
02770
02771         /* Input capture event */
02772         if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
02773         {
02774           HAL_TIM_IC_CaptureCallback(htim);
02775         }
02776         /* Output compare event */
02777         else
02778         {
02779           HAL_TIM_OC_DelayElapsedCallback(htim);
02780           HAL_TIM_PWM_PulseFinishedCallback(htim);
02781         }
02782         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02783       }
02784     }
02785   }
02786   /* Capture compare 2 event */
02787   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
02788   {
02789     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
02790     {
02791       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
02792       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
02793       /* Input capture event */
02794       if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
02795       {
02796         HAL_TIM_IC_CaptureCallback(htim);
02797       }
02798       /* Output compare event */
02799       else
02800       {
02801         HAL_TIM_OC_DelayElapsedCallback(htim);
02802         HAL_TIM_PWM_PulseFinishedCallback(htim);
02803       }
02804       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02805     }
02806   }
02807   /* Capture compare 3 event */
02808   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
02809   {
02810     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
02811     {
02812       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
02813       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
02814       /* Input capture event */
02815       if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
02816       {
02817         HAL_TIM_IC_CaptureCallback(htim);
02818       }
02819       /* Output compare event */
02820       else
02821       {
02822         HAL_TIM_OC_DelayElapsedCallback(htim);
02823         HAL_TIM_PWM_PulseFinishedCallback(htim);
02824       }
02825       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02826     }
02827   }
02828   /* Capture compare 4 event */
02829   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
02830   {
02831     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
02832     {
02833       __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
02834       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
02835       /* Input capture event */
02836       if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
02837       {
02838         HAL_TIM_IC_CaptureCallback(htim);
02839       }
02840       /* Output compare event */
02841       else
02842       {
02843         HAL_TIM_OC_DelayElapsedCallback(htim);
02844         HAL_TIM_PWM_PulseFinishedCallback(htim);
02845       }
02846       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
02847     }
02848   }
02849   /* TIM Update event */
02850   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
02851   {
02852     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
02853     {
02854       __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
02855       HAL_TIM_PeriodElapsedCallback(htim);
02856     }
02857   }
02858   /* TIM Break input event */
02859   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
02860   {
02861     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
02862     {
02863       __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
02864       HAL_TIMEx_BreakCallback(htim);
02865     }
02866   }
02867   /* TIM Trigger detection event */
02868   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
02869   {
02870     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
02871     {
02872       __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
02873       HAL_TIM_TriggerCallback(htim);
02874     }
02875   }
02876   /* TIM commutation event */
02877   if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
02878   {
02879     if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
02880     {
02881       __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
02882       HAL_TIMEx_CommutationCallback(htim);
02883     }
02884   }
02885 }
02886
02887 /**
02888   * @}
02889   */
02890
02891 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
02892  *  @brief      Peripheral Control functions
02893  *
02894 @verbatim
02895   ==============================================================================
02896                    ##### Peripheral Control functions #####
02897   ==============================================================================
02898  [..]
02899    This section provides functions allowing to:
02900       (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
02901       (+) Configure External Clock source.
02902       (+) Configure Complementary channels, break features and dead time.
02903       (+) Configure Master and the Slave synchronization.
02904       (+) Configure the DMA Burst Mode.
02905
02906 @endverbatim
02907   * @{
02908   */
02909
02910 /**
02911   * @brief  Initializes the TIM Output Compare Channels according to the specified
02912   *         parameters in the TIM_OC_InitTypeDef.
02913   * @param  htim : TIM Output Compare handle
02914   * @param  sConfig : TIM Output Compare configuration structure
02915   * @param  Channel : TIM Channels to be enabled
02916   *          This parameter can be one of the following values:
02917   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02918   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02919   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02920   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02921   * @retval HAL status
02922   */
02923 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
02924 {
02925   /* Check the parameters */
02926   assert_param(IS_TIM_CHANNELS(Channel));
02927   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
02928   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
02929
02930   /* Check input state */
02931   __HAL_LOCK(htim);
02932
02933   htim->State = HAL_TIM_STATE_BUSY;
02934
02935   switch (Channel)
02936   {
02937     case TIM_CHANNEL_1:
02938     {
02939       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
02940       /* Configure the TIM Channel 1 in Output Compare */
02941       TIM_OC1_SetConfig(htim->Instance, sConfig);
02942     }
02943     break;
02944
02945     case TIM_CHANNEL_2:
02946     {
02947       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
02948       /* Configure the TIM Channel 2 in Output Compare */
02949       TIM_OC2_SetConfig(htim->Instance, sConfig);
02950     }
02951     break;
02952
02953     case TIM_CHANNEL_3:
02954     {
02955        assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
02956       /* Configure the TIM Channel 3 in Output Compare */
02957       TIM_OC3_SetConfig(htim->Instance, sConfig);
02958     }
02959     break;
02960
02961     case TIM_CHANNEL_4:
02962     {
02963       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
02964        /* Configure the TIM Channel 4 in Output Compare */
02965        TIM_OC4_SetConfig(htim->Instance, sConfig);
02966     }
02967     break;
02968
02969     default:
02970     break;
02971   }
02972   htim->State = HAL_TIM_STATE_READY;
02973
02974   __HAL_UNLOCK(htim);
02975
02976   return HAL_OK;
02977 }
02978
02979 /**
02980   * @brief  Initializes the TIM Input Capture Channels according to the specified
02981   *         parameters in the TIM_IC_InitTypeDef.
02982   * @param  htim : TIM IC handle
02983   * @param  sConfig : TIM Input Capture configuration structure
02984   * @param  Channel : TIM Channels to be enabled
02985   *          This parameter can be one of the following values:
02986   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
02987   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
02988   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
02989   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
02990   * @retval HAL status
02991   */
02992 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
02993 {
02994   /* Check the parameters */
02995   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
02996   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
02997   assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
02998   assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
02999   assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
03000
03001   __HAL_LOCK(htim);
03002
03003   htim->State = HAL_TIM_STATE_BUSY;
03004
03005   if (Channel == TIM_CHANNEL_1)
03006   {
03007     /* TI1 Configuration */
03008     TIM_TI1_SetConfig(htim->Instance,
03009                sConfig->ICPolarity,
03010                sConfig->ICSelection,
03011                sConfig->ICFilter);
03012
03013     /* Reset the IC1PSC Bits */
03014     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03015
03016     /* Set the IC1PSC value */
03017     htim->Instance->CCMR1 |= sConfig->ICPrescaler;
03018   }
03019   else if (Channel == TIM_CHANNEL_2)
03020   {
03021     /* TI2 Configuration */
03022     assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03023
03024     TIM_TI2_SetConfig(htim->Instance,
03025                       sConfig->ICPolarity,
03026                       sConfig->ICSelection,
03027                       sConfig->ICFilter);
03028
03029     /* Reset the IC2PSC Bits */
03030     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03031
03032     /* Set the IC2PSC value */
03033     htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
03034   }
03035   else if (Channel == TIM_CHANNEL_3)
03036   {
03037     /* TI3 Configuration */
03038     assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03039
03040     TIM_TI3_SetConfig(htim->Instance,
03041                sConfig->ICPolarity,
03042                sConfig->ICSelection,
03043                sConfig->ICFilter);
03044
03045     /* Reset the IC3PSC Bits */
03046     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
03047
03048     /* Set the IC3PSC value */
03049     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
03050   }
03051   else
03052   {
03053     /* TI4 Configuration */
03054     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03055
03056     TIM_TI4_SetConfig(htim->Instance,
03057                sConfig->ICPolarity,
03058                sConfig->ICSelection,
03059                sConfig->ICFilter);
03060
03061     /* Reset the IC4PSC Bits */
03062     htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
03063
03064     /* Set the IC4PSC value */
03065     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
03066   }
03067
03068   htim->State = HAL_TIM_STATE_READY;
03069
03070   __HAL_UNLOCK(htim);
03071
03072   return HAL_OK;
03073 }
03074
03075 /**
03076   * @brief  Initializes the TIM PWM  channels according to the specified
03077   *         parameters in the TIM_OC_InitTypeDef.
03078   * @param  htim : TIM handle
03079   * @param  sConfig : TIM PWM configuration structure
03080   * @param  Channel : TIM Channels to be enabled
03081   *          This parameter can be one of the following values:
03082   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03083   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03084   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
03085   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
03086   * @retval HAL status
03087   */
03088 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
03089 {
03090   __HAL_LOCK(htim);
03091
03092   /* Check the parameters */
03093   assert_param(IS_TIM_CHANNELS(Channel));
03094   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
03095   assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
03096   assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
03097
03098   htim->State = HAL_TIM_STATE_BUSY;
03099
03100   switch (Channel)
03101   {
03102     case TIM_CHANNEL_1:
03103     {
03104       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03105       /* Configure the Channel 1 in PWM mode */
03106       TIM_OC1_SetConfig(htim->Instance, sConfig);
03107
03108       /* Set the Preload enable bit for channel1 */
03109       htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
03110
03111       /* Configure the Output Fast mode */
03112       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
03113       htim->Instance->CCMR1 |= sConfig->OCFastMode;
03114     }
03115     break;
03116
03117     case TIM_CHANNEL_2:
03118     {
03119       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03120       /* Configure the Channel 2 in PWM mode */
03121       TIM_OC2_SetConfig(htim->Instance, sConfig);
03122
03123       /* Set the Preload enable bit for channel2 */
03124       htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
03125
03126       /* Configure the Output Fast mode */
03127       htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
03128       htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
03129     }
03130     break;
03131
03132     case TIM_CHANNEL_3:
03133     {
03134       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03135       /* Configure the Channel 3 in PWM mode */
03136       TIM_OC3_SetConfig(htim->Instance, sConfig);
03137
03138       /* Set the Preload enable bit for channel3 */
03139       htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
03140
03141      /* Configure the Output Fast mode */
03142       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
03143       htim->Instance->CCMR2 |= sConfig->OCFastMode;
03144     }
03145     break;
03146
03147     case TIM_CHANNEL_4:
03148     {
03149       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03150       /* Configure the Channel 4 in PWM mode */
03151       TIM_OC4_SetConfig(htim->Instance, sConfig);
03152
03153       /* Set the Preload enable bit for channel4 */
03154       htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
03155
03156      /* Configure the Output Fast mode */
03157       htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
03158       htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
03159     }
03160     break;
03161
03162     default:
03163     break;
03164   }
03165
03166   htim->State = HAL_TIM_STATE_READY;
03167
03168   __HAL_UNLOCK(htim);
03169
03170   return HAL_OK;
03171 }
03172
03173 /**
03174   * @brief  Initializes the TIM One Pulse Channels according to the specified
03175   *         parameters in the TIM_OnePulse_InitTypeDef.
03176   * @param  htim : TIM One Pulse handle
03177   * @param  sConfig : TIM One Pulse configuration structure
03178   * @param  OutputChannel : TIM Channels to be enabled
03179   *          This parameter can be one of the following values:
03180   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03181   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03182   * @param  InputChannel : TIM Channels to be enabled
03183   *          This parameter can be one of the following values:
03184   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
03185   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
03186   * @retval HAL status
03187   */
03188 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
03189 {
03190   TIM_OC_InitTypeDef temp1;
03191
03192   /* Check the parameters */
03193   assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
03194   assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
03195
03196   if(OutputChannel != InputChannel)
03197   {
03198   __HAL_LOCK(htim);
03199
03200   htim->State = HAL_TIM_STATE_BUSY;
03201
03202   /* Extract the Ouput compare configuration from sConfig structure */
03203   temp1.OCMode = sConfig->OCMode;
03204   temp1.Pulse = sConfig->Pulse;
03205   temp1.OCPolarity = sConfig->OCPolarity;
03206   temp1.OCNPolarity = sConfig->OCNPolarity;
03207   temp1.OCIdleState = sConfig->OCIdleState;
03208   temp1.OCNIdleState = sConfig->OCNIdleState;
03209
03210     switch (OutputChannel)
03211   {
03212     case TIM_CHANNEL_1:
03213     {
03214         assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03215
03216       TIM_OC1_SetConfig(htim->Instance, &temp1);
03217     }
03218     break;
03219     case TIM_CHANNEL_2:
03220     {
03221         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03222
03223       TIM_OC2_SetConfig(htim->Instance, &temp1);
03224     }
03225     break;
03226     default:
03227     break;
03228   }
03229   switch (InputChannel)
03230   {
03231     case TIM_CHANNEL_1:
03232     {
03233       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
03234
03235       TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
03236                         sConfig->ICSelection, sConfig->ICFilter);
03237
03238       /* Reset the IC1PSC Bits */
03239     htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
03240
03241       /* Select the Trigger source */
03242         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03243       htim->Instance->SMCR |= TIM_TS_TI1FP1;
03244
03245       /* Select the Slave Mode */
03246         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03247       htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03248     }
03249     break;
03250     case TIM_CHANNEL_2:
03251     {
03252       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03253
03254       TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
03255                  sConfig->ICSelection, sConfig->ICFilter);
03256
03257       /* Reset the IC2PSC Bits */
03258         htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
03259
03260       /* Select the Trigger source */
03261         htim->Instance->SMCR &= ~TIM_SMCR_TS;
03262       htim->Instance->SMCR |= TIM_TS_TI2FP2;
03263
03264       /* Select the Slave Mode */
03265         htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03266       htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
03267     }
03268     break;
03269
03270     default:
03271     break;
03272   }
03273
03274   htim->State = HAL_TIM_STATE_READY;
03275
03276   __HAL_UNLOCK(htim);
03277
03278   return HAL_OK;
03279 }
03280   else
03281   {
03282     return HAL_ERROR;
03283   }
03284 }
03285
03286 /**
03287   * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
03288   * @param  htim : TIM handle
03289   * @param  BurstBaseAddress : TIM Base address from where the DMA will start the Data write
03290   *         This parameter can be one of the following values:
03291   *            @arg TIM_DMABASE_CR1
03292   *            @arg TIM_DMABASE_CR2
03293   *            @arg TIM_DMABASE_SMCR
03294   *            @arg TIM_DMABASE_DIER
03295   *            @arg TIM_DMABASE_SR
03296   *            @arg TIM_DMABASE_EGR
03297   *            @arg TIM_DMABASE_CCMR1
03298   *            @arg TIM_DMABASE_CCMR2
03299   *            @arg TIM_DMABASE_CCER
03300   *            @arg TIM_DMABASE_CNT
03301   *            @arg TIM_DMABASE_PSC
03302   *            @arg TIM_DMABASE_ARR
03303   *            @arg TIM_DMABASE_RCR
03304   *            @arg TIM_DMABASE_CCR1
03305   *            @arg TIM_DMABASE_CCR2
03306   *            @arg TIM_DMABASE_CCR3
03307   *            @arg TIM_DMABASE_CCR4
03308   *            @arg TIM_DMABASE_BDTR
03309   *            @arg TIM_DMABASE_DCR
03310   * @param  BurstRequestSrc : TIM DMA Request sources
03311   *         This parameter can be one of the following values:
03312   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03313   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03314   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03315   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03316   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03317   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03318   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03319   * @param  BurstBuffer : The Buffer address.
03320   * @param  BurstLength : DMA Burst length. This parameter can be one value
03321   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03322   * @retval HAL status
03323   */
03324 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03325                                               uint32_t* BurstBuffer, uint32_t  BurstLength)
03326 {
03327   /* Check the parameters */
03328   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03329   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03330   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03331   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03332
03333   if((htim->State == HAL_TIM_STATE_BUSY))
03334   {
03335      return HAL_BUSY;
03336   }
03337   else if((htim->State == HAL_TIM_STATE_READY))
03338   {
03339     if((BurstBuffer == 0U) && (BurstLength > 0U))
03340     {
03341       return HAL_ERROR;
03342     }
03343     else
03344     {
03345       htim->State = HAL_TIM_STATE_BUSY;
03346     }
03347   }
03348   switch(BurstRequestSrc)
03349   {
03350     case TIM_DMA_UPDATE:
03351     {
03352       /* Set the DMA Period elapsed callback */
03353       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03354
03355       /* Set the DMA error callback */
03356       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03357
03358       /* Enable the DMA channel */
03359       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03360     }
03361     break;
03362     case TIM_DMA_CC1:
03363     {
03364       /* Set the DMA Period elapsed callback */
03365       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03366
03367       /* Set the DMA error callback */
03368       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03369
03370       /* Enable the DMA channel */
03371       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03372     }
03373     break;
03374     case TIM_DMA_CC2:
03375     {
03376       /* Set the DMA Period elapsed callback */
03377       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03378
03379       /* Set the DMA error callback */
03380       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03381
03382       /* Enable the DMA channel */
03383       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03384     }
03385     break;
03386     case TIM_DMA_CC3:
03387     {
03388       /* Set the DMA Period elapsed callback */
03389       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03390
03391       /* Set the DMA error callback */
03392       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03393
03394       /* Enable the DMA channel */
03395       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03396     }
03397     break;
03398     case TIM_DMA_CC4:
03399     {
03400       /* Set the DMA Period elapsed callback */
03401       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMADelayPulseCplt;
03402
03403       /* Set the DMA error callback */
03404       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
03405
03406       /* Enable the DMA channel */
03407       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03408     }
03409     break;
03410     case TIM_DMA_COM:
03411     {
03412       /* Set the DMA Period elapsed callback */
03413       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
03414
03415       /* Set the DMA error callback */
03416       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
03417
03418       /* Enable the DMA channel */
03419       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03420     }
03421     break;
03422     case TIM_DMA_TRIGGER:
03423     {
03424       /* Set the DMA Period elapsed callback */
03425       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03426
03427       /* Set the DMA error callback */
03428       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
03429
03430       /* Enable the DMA channel */
03431       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
03432     }
03433     break;
03434     default:
03435     break;
03436   }
03437    /* configure the DMA Burst Mode */
03438    htim->Instance->DCR = BurstBaseAddress | BurstLength;
03439
03440    /* Enable the TIM DMA Request */
03441    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03442
03443    htim->State = HAL_TIM_STATE_READY;
03444
03445   /* Return function status */
03446   return HAL_OK;
03447 }
03448
03449 /**
03450   * @brief  Stops the TIM DMA Burst mode
03451   * @param  htim : TIM handle
03452   * @param  BurstRequestSrc : TIM DMA Request sources to disable
03453   * @retval HAL status
03454   */
03455 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03456 {
03457   /* Check the parameters */
03458   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03459
03460   /* Abort the DMA transfer (at least disable the DMA channel) */
03461   switch(BurstRequestSrc)
03462   {
03463     case TIM_DMA_UPDATE:
03464     {
03465       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03466     }
03467     break;
03468     case TIM_DMA_CC1:
03469     {
03470       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03471     }
03472     break;
03473     case TIM_DMA_CC2:
03474     {
03475       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03476     }
03477     break;
03478     case TIM_DMA_CC3:
03479     {
03480       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03481     }
03482     break;
03483     case TIM_DMA_CC4:
03484     {
03485       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03486     }
03487     break;
03488     case TIM_DMA_COM:
03489     {
03490       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03491     }
03492     break;
03493     case TIM_DMA_TRIGGER:
03494     {
03495       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03496     }
03497     break;
03498     default:
03499     break;
03500   }
03501
03502   /* Disable the TIM Update DMA request */
03503   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03504
03505   /* Return function status */
03506   return HAL_OK;
03507 }
03508
03509 /**
03510   * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
03511   * @param  htim : TIM handle
03512   * @param  BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
03513   *         This parameter can be one of the following values:
03514   *            @arg TIM_DMABASE_CR1
03515   *            @arg TIM_DMABASE_CR2
03516   *            @arg TIM_DMABASE_SMCR
03517   *            @arg TIM_DMABASE_DIER
03518   *            @arg TIM_DMABASE_SR
03519   *            @arg TIM_DMABASE_EGR
03520   *            @arg TIM_DMABASE_CCMR1
03521   *            @arg TIM_DMABASE_CCMR2
03522   *            @arg TIM_DMABASE_CCER
03523   *            @arg TIM_DMABASE_CNT
03524   *            @arg TIM_DMABASE_PSC
03525   *            @arg TIM_DMABASE_ARR
03526   *            @arg TIM_DMABASE_RCR
03527   *            @arg TIM_DMABASE_CCR1
03528   *            @arg TIM_DMABASE_CCR2
03529   *            @arg TIM_DMABASE_CCR3
03530   *            @arg TIM_DMABASE_CCR4
03531   *            @arg TIM_DMABASE_BDTR
03532   *            @arg TIM_DMABASE_DCR
03533   * @param  BurstRequestSrc : TIM DMA Request sources
03534   *         This parameter can be one of the following values:
03535   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
03536   *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
03537   *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
03538   *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
03539   *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
03540   *            @arg TIM_DMA_COM: TIM Commutation DMA source
03541   *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
03542   * @param  BurstBuffer : The Buffer address.
03543   * @param  BurstLength : DMA Burst length. This parameter can be one value
03544   *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
03545   * @retval HAL status
03546   */
03547 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
03548                                              uint32_t  *BurstBuffer, uint32_t  BurstLength)
03549 {
03550   /* Check the parameters */
03551   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
03552   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
03553   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03554   assert_param(IS_TIM_DMA_LENGTH(BurstLength));
03555
03556   if((htim->State == HAL_TIM_STATE_BUSY))
03557   {
03558      return HAL_BUSY;
03559   }
03560   else if((htim->State == HAL_TIM_STATE_READY))
03561   {
03562     if((BurstBuffer == 0U) && (BurstLength > 0U))
03563     {
03564       return HAL_ERROR;
03565     }
03566     else
03567     {
03568       htim->State = HAL_TIM_STATE_BUSY;
03569     }
03570   }
03571   switch(BurstRequestSrc)
03572   {
03573     case TIM_DMA_UPDATE:
03574     {
03575       /* Set the DMA Period elapsed callback */
03576       htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
03577
03578       /* Set the DMA error callback */
03579       htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
03580
03581       /* Enable the DMA channel */
03582        HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03583     }
03584     break;
03585     case TIM_DMA_CC1:
03586     {
03587       /* Set the DMA Period elapsed callback */
03588       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMACaptureCplt;
03589
03590       /* Set the DMA error callback */
03591       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
03592
03593       /* Enable the DMA channel */
03594       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03595     }
03596     break;
03597     case TIM_DMA_CC2:
03598     {
03599       /* Set the DMA Period elapsed callback */
03600       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMACaptureCplt;
03601
03602       /* Set the DMA error callback */
03603       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
03604
03605       /* Enable the DMA channel */
03606       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03607     }
03608     break;
03609     case TIM_DMA_CC3:
03610     {
03611       /* Set the DMA Period elapsed callback */
03612       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMACaptureCplt;
03613
03614       /* Set the DMA error callback */
03615       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
03616
03617       /* Enable the DMA channel */
03618       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03619     }
03620     break;
03621     case TIM_DMA_CC4:
03622     {
03623       /* Set the DMA Period elapsed callback */
03624       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMACaptureCplt;
03625
03626       /* Set the DMA error callback */
03627       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
03628
03629       /* Enable the DMA channel */
03630       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03631     }
03632     break;
03633     case TIM_DMA_COM:
03634     {
03635       /* Set the DMA Period elapsed callback */
03636       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;
03637
03638       /* Set the DMA error callback */
03639       htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
03640
03641       /* Enable the DMA channel */
03642       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03643     }
03644     break;
03645     case TIM_DMA_TRIGGER:
03646     {
03647       /* Set the DMA Period elapsed callback */
03648       htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
03649
03650       /* Set the DMA error callback */
03651       htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
03652
03653       /* Enable the DMA channel */
03654       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
03655     }
03656     break;
03657     default:
03658     break;
03659   }
03660
03661   /* configure the DMA Burst Mode */
03662   htim->Instance->DCR = BurstBaseAddress | BurstLength;
03663
03664   /* Enable the TIM DMA Request */
03665   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
03666
03667   htim->State = HAL_TIM_STATE_READY;
03668
03669   /* Return function status */
03670   return HAL_OK;
03671 }
03672
03673 /**
03674   * @brief  Stop the DMA burst reading
03675   * @param  htim : TIM handle
03676   * @param  BurstRequestSrc : TIM DMA Request sources to disable.
03677   * @retval HAL status
03678   */
03679 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
03680 {
03681   /* Check the parameters */
03682   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
03683
03684   /* Abort the DMA transfer (at least disable the DMA channel) */
03685   switch(BurstRequestSrc)
03686   {
03687     case TIM_DMA_UPDATE:
03688     {
03689       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
03690     }
03691     break;
03692     case TIM_DMA_CC1:
03693     {
03694       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
03695     }
03696     break;
03697     case TIM_DMA_CC2:
03698     {
03699       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
03700     }
03701     break;
03702     case TIM_DMA_CC3:
03703     {
03704       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
03705     }
03706     break;
03707     case TIM_DMA_CC4:
03708     {
03709       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
03710     }
03711     break;
03712     case TIM_DMA_COM:
03713     {
03714       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
03715     }
03716     break;
03717     case TIM_DMA_TRIGGER:
03718     {
03719       HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
03720     }
03721     break;
03722     default:
03723     break;
03724   }
03725
03726   /* Disable the TIM Update DMA request */
03727   __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
03728
03729   /* Return function status */
03730   return HAL_OK;
03731 }
03732
03733 /**
03734   * @brief  Generate a software event
03735   * @param  htim : TIM handle
03736   * @param  EventSource : specifies the event source.
03737   *          This parameter can be one of the following values:
03738   *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
03739   *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
03740   *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
03741   *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
03742   *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
03743   *            @arg TIM_EVENTSOURCE_COM: Timer COM event source
03744   *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
03745   *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
03746   * @note TIM6 and TIM7 can only generate an update event.
03747   * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
03748   * @retval HAL status
03749   */
03750
03751 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
03752 {
03753   /* Check the parameters */
03754   assert_param(IS_TIM_INSTANCE(htim->Instance));
03755   assert_param(IS_TIM_EVENT_SOURCE(EventSource));
03756
03757   /* Process Locked */
03758   __HAL_LOCK(htim);
03759
03760   /* Change the TIM state */
03761   htim->State = HAL_TIM_STATE_BUSY;
03762
03763   /* Set the event sources */
03764   htim->Instance->EGR = EventSource;
03765
03766   /* Change the TIM state */
03767   htim->State = HAL_TIM_STATE_READY;
03768
03769   __HAL_UNLOCK(htim);
03770
03771   /* Return function status */
03772   return HAL_OK;
03773 }
03774
03775 /**
03776   * @brief  Configures the OCRef clear feature
03777   * @param  htim : TIM handle
03778   * @param  sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
03779   *         contains the OCREF clear feature and parameters for the TIM peripheral.
03780   * @param  Channel : specifies the TIM Channel
03781   *          This parameter can be one of the following values:
03782   *            @arg TIM_CHANNEL_1: TIM Channel 1
03783   *            @arg TIM_CHANNEL_2: TIM Channel 2
03784   *            @arg TIM_CHANNEL_3: TIM Channel 3
03785   *            @arg TIM_CHANNEL_4: TIM Channel 4
03786   * @retval HAL status
03787   */
03788 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
03789 {
03790   uint32_t tmpsmcr = 0U;
03791
03792   /* Check the parameters */
03793   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
03794   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
03795   assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
03796   assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
03797   assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
03798
03799   /* Process Locked */
03800   __HAL_LOCK(htim);
03801
03802   htim->State = HAL_TIM_STATE_BUSY;
03803
03804   switch (sClearInputConfig->ClearInputSource)
03805   {
03806     case TIM_CLEARINPUTSOURCE_NONE:
03807     {
03808
03809       /* Clear the ETR Bits */
03810       tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
03811
03812       /* Set TIMx_SMCR */
03813       htim->Instance->SMCR = tmpsmcr;
03814    }
03815     break;
03816
03817     case TIM_CLEARINPUTSOURCE_ETR:
03818     {
03819       TIM_ETR_SetConfig(htim->Instance,
03820                         sClearInputConfig->ClearInputPrescaler,
03821                         sClearInputConfig->ClearInputPolarity,
03822                         sClearInputConfig->ClearInputFilter);
03823
03824     }
03825     break;
03826     default:
03827     break;
03828   }
03829
03830   switch (Channel)
03831   {
03832     case TIM_CHANNEL_1:
03833       {
03834         if(sClearInputConfig->ClearInputState != RESET)
03835         {
03836           /* Enable the Ocref clear feature for Channel 1 */
03837           htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
03838         }
03839         else
03840         {
03841           /* Disable the Ocref clear feature for Channel 1 */
03842         htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
03843         }
03844       }
03845       break;
03846     case TIM_CHANNEL_2:
03847       {
03848         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
03849         if(sClearInputConfig->ClearInputState != RESET)
03850         {
03851           /* Enable the Ocref clear feature for Channel 2 */
03852           htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
03853         }
03854         else
03855         {
03856           /* Disable the Ocref clear feature for Channel 2 */
03857           htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
03858         }
03859       }
03860     break;
03861     case TIM_CHANNEL_3:
03862       {
03863         assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
03864         if(sClearInputConfig->ClearInputState != RESET)
03865         {
03866           /* Enable the Ocref clear feature for Channel 3 */
03867           htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
03868         }
03869         else
03870         {
03871           /* Disable the Ocref clear feature for Channel 3 */
03872         htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
03873         }
03874       }
03875     break;
03876     case TIM_CHANNEL_4:
03877       {
03878         assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
03879         if(sClearInputConfig->ClearInputState != RESET)
03880         {
03881           /* Enable the Ocref clear feature for Channel 4 */
03882           htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
03883         }
03884         else
03885         {
03886           /* Disable the Ocref clear feature for Channel 4 */
03887         htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
03888         }
03889       }
03890     break;
03891     default:
03892     break;
03893   }
03894
03895   htim->State = HAL_TIM_STATE_READY;
03896
03897   __HAL_UNLOCK(htim);
03898
03899   return HAL_OK;
03900 }
03901
03902 /**
03903   * @brief   Configures the clock source to be used
03904   * @param  htim : TIM handle
03905   * @param  sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
03906   *         contains the clock source information for the TIM peripheral.
03907   * @retval HAL status
03908   */
03909 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
03910 {
03911   uint32_t tmpsmcr = 0U;
03912
03913   /* Process Locked */
03914   __HAL_LOCK(htim);
03915
03916   htim->State = HAL_TIM_STATE_BUSY;
03917
03918   /* Check the parameters */
03919   assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
03920
03921   /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
03922   tmpsmcr = htim->Instance->SMCR;
03923   tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
03924   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
03925   htim->Instance->SMCR = tmpsmcr;
03926
03927   switch (sClockSourceConfig->ClockSource)
03928   {
03929   case TIM_CLOCKSOURCE_INTERNAL:
03930     {
03931       assert_param(IS_TIM_INSTANCE(htim->Instance));
03932       /* Disable slave mode to clock the prescaler directly with the internal clock */
03933       htim->Instance->SMCR &= ~TIM_SMCR_SMS;
03934     }
03935     break;
03936
03937   case TIM_CLOCKSOURCE_ETRMODE1:
03938     {
03939       /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
03940       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
03941
03942       /* Check ETR input conditioning related parameters */
03943       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
03944       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
03945       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
03946
03947       /* Configure the ETR Clock source */
03948       TIM_ETR_SetConfig(htim->Instance,
03949                         sClockSourceConfig->ClockPrescaler,
03950                         sClockSourceConfig->ClockPolarity,
03951                         sClockSourceConfig->ClockFilter);
03952       /* Get the TIMx SMCR register value */
03953       tmpsmcr = htim->Instance->SMCR;
03954       /* Reset the SMS and TS Bits */
03955       tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
03956       /* Select the External clock mode1 and the ETRF trigger */
03957       tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
03958       /* Write to TIMx SMCR */
03959       htim->Instance->SMCR = tmpsmcr;
03960     }
03961     break;
03962
03963   case TIM_CLOCKSOURCE_ETRMODE2:
03964     {
03965       /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
03966       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
03967
03968       /* Check ETR input conditioning related parameters */
03969       assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
03970       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
03971       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
03972
03973       /* Configure the ETR Clock source */
03974       TIM_ETR_SetConfig(htim->Instance,
03975                         sClockSourceConfig->ClockPrescaler,
03976                         sClockSourceConfig->ClockPolarity,
03977                         sClockSourceConfig->ClockFilter);
03978       /* Enable the External clock mode2 */
03979       htim->Instance->SMCR |= TIM_SMCR_ECE;
03980     }
03981     break;
03982
03983   case TIM_CLOCKSOURCE_TI1:
03984     {
03985       /* Check whether or not the timer instance supports external clock mode 1 */
03986       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
03987
03988       /* Check TI1 input conditioning related parameters */
03989       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
03990       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
03991
03992       TIM_TI1_ConfigInputStage(htim->Instance,
03993                                sClockSourceConfig->ClockPolarity,
03994                                sClockSourceConfig->ClockFilter);
03995       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
03996     }
03997     break;
03998   case TIM_CLOCKSOURCE_TI2:
03999     {
04000       /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
04001       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04002
04003        /* Check TI2 input conditioning related parameters */
04004       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04005       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04006
04007       TIM_TI2_ConfigInputStage(htim->Instance,
04008                                sClockSourceConfig->ClockPolarity,
04009                                sClockSourceConfig->ClockFilter);
04010       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
04011     }
04012     break;
04013   case TIM_CLOCKSOURCE_TI1ED:
04014     {
04015       /* Check whether or not the timer instance supports external clock mode 1 */
04016       assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
04017
04018       /* Check TI1 input conditioning related parameters */
04019       assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
04020       assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
04021
04022       TIM_TI1_ConfigInputStage(htim->Instance,
04023                                sClockSourceConfig->ClockPolarity,
04024                                sClockSourceConfig->ClockFilter);
04025       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
04026     }
04027     break;
04028   case TIM_CLOCKSOURCE_ITR0:
04029     {
04030       /* Check whether or not the timer instance supports external clock mode 1 */
04031       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04032
04033       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
04034     }
04035     break;
04036   case TIM_CLOCKSOURCE_ITR1:
04037     {
04038       /* Check whether or not the timer instance supports external clock mode 1 */
04039       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04040
04041       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
04042     }
04043     break;
04044   case TIM_CLOCKSOURCE_ITR2:
04045     {
04046       /* Check whether or not the timer instance supports external clock mode 1 */
04047       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04048
04049       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
04050     }
04051     break;
04052   case TIM_CLOCKSOURCE_ITR3:
04053     {
04054       /* Check whether or not the timer instance supports external clock mode 1 */
04055       assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
04056
04057       TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
04058     }
04059     break;
04060
04061   default:
04062     break;
04063   }
04064   htim->State = HAL_TIM_STATE_READY;
04065
04066   __HAL_UNLOCK(htim);
04067
04068   return HAL_OK;
04069 }
04070
04071 /**
04072   * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
04073   *         or a XOR combination between CH1_input, CH2_input & CH3_input
04074   * @param  htim : TIM handle.
04075   * @param  TI1_Selection : Indicate whether or not channel 1 is connected to the
04076   *         output of a XOR gate.
04077   *          This parameter can be one of the following values:
04078   *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
04079   *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
04080   *            pins are connected to the TI1 input (XOR combination)
04081   * @retval HAL status
04082   */
04083 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
04084 {
04085   uint32_t tmpcr2 = 0U;
04086
04087   /* Check the parameters */
04088   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
04089   assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
04090
04091   /* Get the TIMx CR2 register value */
04092   tmpcr2 = htim->Instance->CR2;
04093
04094   /* Reset the TI1 selection */
04095   tmpcr2 &= ~TIM_CR2_TI1S;
04096
04097   /* Set the the TI1 selection */
04098   tmpcr2 |= TI1_Selection;
04099
04100   /* Write to TIMxCR2 */
04101   htim->Instance->CR2 = tmpcr2;
04102
04103   return HAL_OK;
04104 }
04105
04106 /**
04107   * @brief  Configures the TIM in Slave mode
04108   * @param  htim : TIM handle.
04109   * @param  sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
04110   *         contains the selected trigger (internal trigger input, filtered
04111   *         timer input or external trigger input) and the ) and the Slave
04112   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04113   * @retval HAL status
04114   */
04115 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
04116 {
04117   /* Check the parameters */
04118   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04119   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04120   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04121
04122   __HAL_LOCK(htim);
04123
04124   htim->State = HAL_TIM_STATE_BUSY;
04125
04126   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04127
04128   /* Disable Trigger Interrupt */
04129   __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
04130
04131   /* Disable Trigger DMA request */
04132   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04133
04134   htim->State = HAL_TIM_STATE_READY;
04135
04136   __HAL_UNLOCK(htim);
04137
04138   return HAL_OK;
04139     }
04140
04141 /**
04142   * @brief  Configures the TIM in Slave mode in interrupt mode
04143   * @param  htim: TIM handle.
04144   * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
04145   *         contains the selected trigger (internal trigger input, filtered
04146   *         timer input or external trigger input) and the ) and the Slave
04147   *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
04148   * @retval HAL status
04149   */
04150 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
04151                                                         TIM_SlaveConfigTypeDef * sSlaveConfig)
04152     {
04153       /* Check the parameters */
04154   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
04155   assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
04156   assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
04157
04158   __HAL_LOCK(htim);
04159
04160   htim->State = HAL_TIM_STATE_BUSY;
04161
04162   TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
04163
04164   /* Enable Trigger Interrupt */
04165   __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
04166
04167   /* Disable Trigger DMA request */
04168   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
04169
04170   htim->State = HAL_TIM_STATE_READY;
04171
04172   __HAL_UNLOCK(htim);
04173
04174   return HAL_OK;
04175 }
04176
04177 /**
04178   * @brief  Read the captured value from Capture Compare unit
04179   * @param  htim : TIM handle.
04180   * @param  Channel : TIM Channels to be enabled
04181   *          This parameter can be one of the following values:
04182   *            @arg TIM_CHANNEL_1 : TIM Channel 1 selected
04183   *            @arg TIM_CHANNEL_2 : TIM Channel 2 selected
04184   *            @arg TIM_CHANNEL_3 : TIM Channel 3 selected
04185   *            @arg TIM_CHANNEL_4 : TIM Channel 4 selected
04186   * @retval Captured value
04187   */
04188 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
04189 {
04190   uint32_t tmpreg = 0U;
04191
04192   __HAL_LOCK(htim);
04193
04194   switch (Channel)
04195   {
04196   case TIM_CHANNEL_1:
04197     {
04198       /* Check the parameters */
04199       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04200
04201       /* Return the capture 1 value */
04202       tmpreg =  htim->Instance->CCR1;
04203
04204       break;
04205     }
04206   case TIM_CHANNEL_2:
04207     {
04208       /* Check the parameters */
04209       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04210
04211       /* Return the capture 2 value */
04212       tmpreg =   htim->Instance->CCR2;
04213
04214       break;
04215     }
04216
04217   case TIM_CHANNEL_3:
04218     {
04219       /* Check the parameters */
04220       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
04221
04222       /* Return the capture 3 value */
04223       tmpreg =   htim->Instance->CCR3;
04224
04225       break;
04226     }
04227
04228   case TIM_CHANNEL_4:
04229     {
04230       /* Check the parameters */
04231       assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
04232
04233       /* Return the capture 4 value */
04234       tmpreg =   htim->Instance->CCR4;
04235
04236       break;
04237     }
04238
04239   default:
04240     break;
04241   }
04242
04243   __HAL_UNLOCK(htim);
04244   return tmpreg;
04245 }
04246
04247 /**
04248   * @}
04249   */
04250
04251 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
04252  *  @brief    TIM Callbacks functions
04253  *
04254 @verbatim
04255   ==============================================================================
04256                         ##### TIM Callbacks functions #####
04257   ==============================================================================
04258  [..]
04259    This section provides TIM callback functions:
04260    (+) Timer Period elapsed callback
04261    (+) Timer Output Compare callback
04262    (+) Timer Input capture callback
04263    (+) Timer Trigger callback
04264    (+) Timer Error callback
04265
04266 @endverbatim
04267   * @{
04268   */
04269
04270 /**
04271   * @brief  Period elapsed callback in non blocking mode
04272   * @param  htim : TIM handle
04273   * @retval None
04274   */
04275 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
04276 {
04277   /* Prevent unused argument(s) compilation warning */
04278   UNUSED(htim);
04279   /* NOTE : This function Should not be modified, when the callback is needed,
04280             the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
04281    */
04282
04283 }
04284 /**
04285   * @brief  Output Compare callback in non blocking mode
04286   * @param  htim : TIM OC handle
04287   * @retval None
04288   */
04289 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
04290 {
04291   /* Prevent unused argument(s) compilation warning */
04292   UNUSED(htim);
04293   /* NOTE : This function Should not be modified, when the callback is needed,
04294             the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
04295    */
04296 }
04297 /**
04298   * @brief  Input Capture callback in non blocking mode
04299   * @param  htim : TIM IC handle
04300   * @retval None
04301   */
04302 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
04303 {
04304   /* Prevent unused argument(s) compilation warning */
04305   UNUSED(htim);
04306   /* NOTE : This function Should not be modified, when the callback is needed,
04307             the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
04308    */
04309 }
04310
04311 /**
04312   * @brief  PWM Pulse finished callback in non blocking mode
04313   * @param  htim : TIM handle
04314   * @retval None
04315   */
04316 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
04317 {
04318   /* Prevent unused argument(s) compilation warning */
04319   UNUSED(htim);
04320   /* NOTE : This function Should not be modified, when the callback is needed,
04321             the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
04322    */
04323 }
04324
04325 /**
04326   * @brief  Hall Trigger detection callback in non blocking mode
04327   * @param  htim : TIM handle
04328   * @retval None
04329   */
04330 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
04331 {
04332   /* Prevent unused argument(s) compilation warning */
04333   UNUSED(htim);
04334   /* NOTE : This function Should not be modified, when the callback is needed,
04335             the HAL_TIM_TriggerCallback could be implemented in the user file
04336    */
04337 }
04338
04339 /**
04340   * @brief  Timer error callback in non blocking mode
04341   * @param  htim : TIM handle
04342   * @retval None
04343   */
04344 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
04345 {
04346   /* Prevent unused argument(s) compilation warning */
04347   UNUSED(htim);
04348   /* NOTE : This function Should not be modified, when the callback is needed,
04349             the HAL_TIM_ErrorCallback could be implemented in the user file
04350    */
04351 }
04352
04353 /**
04354   * @}
04355   */
04356
04357 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
04358  *  @brief   Peripheral State functions
04359  *
04360 @verbatim
04361   ==============================================================================
04362                         ##### Peripheral State functions #####
04363   ==============================================================================
04364     [..]
04365     This subsection permit to get in run-time the status of the peripheral
04366     and the data flow.
04367
04368 @endverbatim
04369   * @{
04370   */
04371
04372 /**
04373   * @brief  Return the TIM Base state
04374   * @param  htim : TIM Base handle
04375   * @retval HAL state
04376   */
04377 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
04378 {
04379   return htim->State;
04380 }
04381
04382 /**
04383   * @brief  Return the TIM OC state
04384   * @param  htim : TIM Ouput Compare handle
04385   * @retval HAL state
04386   */
04387 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
04388 {
04389   return htim->State;
04390 }
04391
04392 /**
04393   * @brief  Return the TIM PWM state
04394   * @param  htim : TIM handle
04395   * @retval HAL state
04396   */
04397 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
04398 {
04399   return htim->State;
04400 }
04401
04402 /**
04403   * @brief  Return the TIM Input Capture state
04404   * @param  htim : TIM IC handle
04405   * @retval HAL state
04406   */
04407 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
04408 {
04409   return htim->State;
04410 }
04411
04412 /**
04413   * @brief  Return the TIM One Pulse Mode state
04414   * @param  htim : TIM OPM handle
04415   * @retval HAL state
04416   */
04417 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
04418 {
04419   return htim->State;
04420 }
04421
04422 /**
04423   * @brief  Return the TIM Encoder Mode state
04424   * @param  htim : TIM Encoder handle
04425   * @retval HAL state
04426   */
04427 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
04428 {
04429   return htim->State;
04430 }
04431
04432 /**
04433   * @}
04434   */
04435
04436 /**
04437   * @}
04438   */
04439
04440 /** @addtogroup TIM_Private_Functions
04441   * @{
04442   */
04443
04444 /**
04445   * @brief  TIM DMA error callback
04446   * @param  hdma : pointer to DMA handle.
04447   * @retval None
04448   */
04449 void TIM_DMAError(DMA_HandleTypeDef *hdma)
04450 {
04451   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04452
04453   htim->State= HAL_TIM_STATE_READY;
04454
04455   HAL_TIM_ErrorCallback(htim);
04456 }
04457
04458 /**
04459   * @brief  TIM DMA Delay Pulse complete callback.
04460   * @param  hdma : pointer to DMA handle.
04461   * @retval None
04462   */
04463 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
04464 {
04465   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04466
04467   htim->State= HAL_TIM_STATE_READY;
04468
04469   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04470   {
04471     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04472   }
04473   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04474   {
04475     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04476   }
04477   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04478   {
04479     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04480   }
04481   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04482   {
04483     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04484   }
04485
04486   HAL_TIM_PWM_PulseFinishedCallback(htim);
04487
04488   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04489 }
04490 /**
04491   * @brief  TIM DMA Capture complete callback.
04492   * @param  hdma : pointer to DMA handle.
04493   * @retval None
04494   */
04495 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
04496 {
04497   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04498
04499   htim->State= HAL_TIM_STATE_READY;
04500
04501   if (hdma == htim->hdma[TIM_DMA_ID_CC1])
04502   {
04503     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
04504   }
04505   else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
04506   {
04507     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
04508   }
04509   else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
04510   {
04511     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
04512   }
04513   else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
04514   {
04515     htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
04516   }
04517
04518   HAL_TIM_IC_CaptureCallback(htim);
04519
04520   htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
04521 }
04522
04523 /**
04524   * @brief  TIM DMA Period Elapse complete callback.
04525   * @param  hdma : pointer to DMA handle.
04526   * @retval None
04527   */
04528 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
04529 {
04530   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04531
04532   htim->State= HAL_TIM_STATE_READY;
04533
04534   HAL_TIM_PeriodElapsedCallback(htim);
04535 }
04536
04537 /**
04538   * @brief  TIM DMA Trigger callback.
04539   * @param  hdma : pointer to DMA handle.
04540   * @retval None
04541   */
04542 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
04543 {
04544   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04545
04546   htim->State= HAL_TIM_STATE_READY;
04547
04548   HAL_TIM_TriggerCallback(htim);
04549 }
04550
04551 /**
04552   * @brief  Time Base configuration
04553   * @param  TIMx : TIM periheral
04554   * @param  Structure : TIM Base configuration structure
04555   * @retval None
04556   */
04557 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
04558 {
04559   uint32_t tmpcr1 = 0U;
04560   tmpcr1 = TIMx->CR1;
04561
04562   /* Set TIM Time Base Unit parameters ---------------------------------------*/
04563   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
04564   {
04565     /* Select the Counter Mode */
04566     tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
04567     tmpcr1 |= Structure->CounterMode;
04568   }
04569
04570   if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
04571   {
04572     /* Set the clock division */
04573     tmpcr1 &= ~TIM_CR1_CKD;
04574     tmpcr1 |= (uint32_t)Structure->ClockDivision;
04575   }
04576
04577   /* Set the auto-reload preload */
04578   tmpcr1 &= ~TIM_CR1_ARPE;
04579   tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
04580
04581   TIMx->CR1 = tmpcr1;
04582
04583   /* Set the Autoreload value */
04584   TIMx->ARR = (uint32_t)Structure->Period ;
04585
04586   /* Set the Prescaler value */
04587   TIMx->PSC = (uint32_t)Structure->Prescaler;
04588
04589   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
04590   {
04591     /* Set the Repetition Counter value */
04592     TIMx->RCR = Structure->RepetitionCounter;
04593   }
04594
04595   /* Generate an update event to reload the Prescaler
04596      and the repetition counter(only for TIM1 and TIM8) value immediatly */
04597   TIMx->EGR = TIM_EGR_UG;
04598 }
04599
04600 /**
04601   * @brief  Time Ouput Compare 1 configuration
04602   * @param  TIMx to select the TIM peripheral
04603   * @param  OC_Config : The ouput configuration structure
04604   * @retval None
04605   */
04606 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04607 {
04608   uint32_t tmpccmrx = 0U;
04609   uint32_t tmpccer = 0U;
04610   uint32_t tmpcr2 = 0U;
04611
04612    /* Disable the Channel 1: Reset the CC1E Bit */
04613   TIMx->CCER &= ~TIM_CCER_CC1E;
04614
04615   /* Get the TIMx CCER register value */
04616   tmpccer = TIMx->CCER;
04617   /* Get the TIMx CR2 register value */
04618   tmpcr2 =  TIMx->CR2;
04619
04620   /* Get the TIMx CCMR1 register value */
04621   tmpccmrx = TIMx->CCMR1;
04622
04623   /* Reset the Output Compare Mode Bits */
04624   tmpccmrx &= ~TIM_CCMR1_OC1M;
04625   tmpccmrx &= ~TIM_CCMR1_CC1S;
04626   /* Select the Output Compare Mode */
04627   tmpccmrx |= OC_Config->OCMode;
04628
04629   /* Reset the Output Polarity level */
04630   tmpccer &= ~TIM_CCER_CC1P;
04631   /* Set the Output Compare Polarity */
04632   tmpccer |= OC_Config->OCPolarity;
04633
04634   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
04635   {
04636     /* Check parameters */
04637     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04638
04639     /* Reset the Output N Polarity level */
04640     tmpccer &= ~TIM_CCER_CC1NP;
04641     /* Set the Output N Polarity */
04642     tmpccer |= OC_Config->OCNPolarity;
04643     /* Reset the Output N State */
04644     tmpccer &= ~TIM_CCER_CC1NE;
04645   }
04646
04647   if(IS_TIM_BREAK_INSTANCE(TIMx))
04648   {
04649     /* Check parameters */
04650     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04651     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04652
04653     /* Reset the Output Compare and Output Compare N IDLE State */
04654     tmpcr2 &= ~TIM_CR2_OIS1;
04655     tmpcr2 &= ~TIM_CR2_OIS1N;
04656     /* Set the Output Idle state */
04657     tmpcr2 |= OC_Config->OCIdleState;
04658     /* Set the Output N Idle state */
04659     tmpcr2 |= OC_Config->OCNIdleState;
04660   }
04661   /* Write to TIMx CR2 */
04662   TIMx->CR2 = tmpcr2;
04663
04664   /* Write to TIMx CCMR1 */
04665   TIMx->CCMR1 = tmpccmrx;
04666
04667   /* Set the Capture Compare Register value */
04668   TIMx->CCR1 = OC_Config->Pulse;
04669
04670   /* Write to TIMx CCER */
04671   TIMx->CCER = tmpccer;
04672 }
04673
04674 /**
04675   * @brief  Time Ouput Compare 2 configuration
04676   * @param  TIMx  to select the TIM peripheral
04677   * @param  OC_Config : The ouput configuration structure
04678   * @retval None
04679   */
04680 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04681 {
04682   uint32_t tmpccmrx = 0U;
04683   uint32_t tmpccer = 0U;
04684   uint32_t tmpcr2 = 0U;
04685
04686   /* Disable the Channel 2: Reset the CC2E Bit */
04687   TIMx->CCER &= ~TIM_CCER_CC2E;
04688
04689   /* Get the TIMx CCER register value */
04690   tmpccer = TIMx->CCER;
04691   /* Get the TIMx CR2 register value */
04692   tmpcr2 =  TIMx->CR2;
04693
04694   /* Get the TIMx CCMR1 register value */
04695   tmpccmrx = TIMx->CCMR1;
04696
04697   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04698   tmpccmrx &= ~TIM_CCMR1_OC2M;
04699   tmpccmrx &= ~TIM_CCMR1_CC2S;
04700
04701   /* Select the Output Compare Mode */
04702   tmpccmrx |= (OC_Config->OCMode << 8U);
04703
04704   /* Reset the Output Polarity level */
04705   tmpccer &= ~TIM_CCER_CC2P;
04706   /* Set the Output Compare Polarity */
04707   tmpccer |= (OC_Config->OCPolarity << 4U);
04708
04709   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
04710   {
04711     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04712
04713     /* Reset the Output N Polarity level */
04714     tmpccer &= ~TIM_CCER_CC2NP;
04715     /* Set the Output N Polarity */
04716     tmpccer |= (OC_Config->OCNPolarity << 4U);
04717     /* Reset the Output N State */
04718     tmpccer &= ~TIM_CCER_CC2NE;
04719
04720   }
04721
04722   if(IS_TIM_BREAK_INSTANCE(TIMx))
04723   {
04724     /* Check parameters */
04725     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04726     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04727
04728     /* Reset the Output Compare and Output Compare N IDLE State */
04729     tmpcr2 &= ~TIM_CR2_OIS2;
04730     tmpcr2 &= ~TIM_CR2_OIS2N;
04731     /* Set the Output Idle state */
04732     tmpcr2 |= (OC_Config->OCIdleState << 2);
04733     /* Set the Output N Idle state */
04734     tmpcr2 |= (OC_Config->OCNIdleState << 2);
04735   }
04736
04737   /* Write to TIMx CR2 */
04738   TIMx->CR2 = tmpcr2;
04739
04740   /* Write to TIMx CCMR1 */
04741   TIMx->CCMR1 = tmpccmrx;
04742
04743   /* Set the Capture Compare Register value */
04744   TIMx->CCR2 = OC_Config->Pulse;
04745
04746   /* Write to TIMx CCER */
04747   TIMx->CCER = tmpccer;
04748 }
04749
04750 /**
04751   * @brief  Time Ouput Compare 3 configuration
04752   * @param  TIMx  to select the TIM peripheral
04753   * @param  OC_Config : The ouput configuration structure
04754   * @retval None
04755   */
04756 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04757 {
04758   uint32_t tmpccmrx = 0U;
04759   uint32_t tmpccer = 0U;
04760   uint32_t tmpcr2 = 0U;
04761
04762   /* Disable the Channel 3: Reset the CC2E Bit */
04763   TIMx->CCER &= ~TIM_CCER_CC3E;
04764
04765   /* Get the TIMx CCER register value */
04766   tmpccer = TIMx->CCER;
04767   /* Get the TIMx CR2 register value */
04768   tmpcr2 =  TIMx->CR2;
04769
04770   /* Get the TIMx CCMR2 register value */
04771   tmpccmrx = TIMx->CCMR2;
04772
04773   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04774   tmpccmrx &= ~TIM_CCMR2_OC3M;
04775   tmpccmrx &= ~TIM_CCMR2_CC3S;
04776   /* Select the Output Compare Mode */
04777   tmpccmrx |= OC_Config->OCMode;
04778
04779   /* Reset the Output Polarity level */
04780   tmpccer &= ~TIM_CCER_CC3P;
04781   /* Set the Output Compare Polarity */
04782   tmpccer |= (OC_Config->OCPolarity << 8U);
04783
04784   if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
04785   {
04786     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
04787
04788     /* Reset the Output N Polarity level */
04789     tmpccer &= ~TIM_CCER_CC3NP;
04790     /* Set the Output N Polarity */
04791     tmpccer |= (OC_Config->OCNPolarity << 8U);
04792     /* Reset the Output N State */
04793     tmpccer &= ~TIM_CCER_CC3NE;
04794   }
04795
04796   if(IS_TIM_BREAK_INSTANCE(TIMx))
04797   {
04798     /* Check parameters */
04799     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
04800     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04801
04802     /* Reset the Output Compare and Output Compare N IDLE State */
04803     tmpcr2 &= ~TIM_CR2_OIS3;
04804     tmpcr2 &= ~TIM_CR2_OIS3N;
04805     /* Set the Output Idle state */
04806     tmpcr2 |= (OC_Config->OCIdleState << 4U);
04807     /* Set the Output N Idle state */
04808     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
04809   }
04810
04811   /* Write to TIMx CR2 */
04812   TIMx->CR2 = tmpcr2;
04813
04814   /* Write to TIMx CCMR2 */
04815   TIMx->CCMR2 = tmpccmrx;
04816
04817   /* Set the Capture Compare Register value */
04818   TIMx->CCR3 = OC_Config->Pulse;
04819
04820   /* Write to TIMx CCER */
04821   TIMx->CCER = tmpccer;
04822 }
04823
04824 /**
04825   * @brief  Time Ouput Compare 4 configuration
04826   * @param  TIMx  to select the TIM peripheral
04827   * @param  OC_Config : The ouput configuration structure
04828   * @retval None
04829   */
04830 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
04831 {
04832   uint32_t tmpccmrx = 0U;
04833   uint32_t tmpccer = 0U;
04834   uint32_t tmpcr2 = 0U;
04835
04836   /* Disable the Channel 4: Reset the CC4E Bit */
04837   TIMx->CCER &= ~TIM_CCER_CC4E;
04838
04839   /* Get the TIMx CCER register value */
04840   tmpccer = TIMx->CCER;
04841   /* Get the TIMx CR2 register value */
04842   tmpcr2 =  TIMx->CR2;
04843
04844   /* Get the TIMx CCMR2 register value */
04845   tmpccmrx = TIMx->CCMR2;
04846
04847   /* Reset the Output Compare mode and Capture/Compare selection Bits */
04848   tmpccmrx &= ~TIM_CCMR2_OC4M;
04849   tmpccmrx &= ~TIM_CCMR2_CC4S;
04850
04851   /* Select the Output Compare Mode */
04852   tmpccmrx |= (OC_Config->OCMode << 8U);
04853
04854   /* Reset the Output Polarity level */
04855   tmpccer &= ~TIM_CCER_CC4P;
04856   /* Set the Output Compare Polarity */
04857   tmpccer |= (OC_Config->OCPolarity << 12U);
04858
04859   if(IS_TIM_BREAK_INSTANCE(TIMx))
04860   {
04861     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
04862
04863    /* Reset the Output Compare IDLE State */
04864     tmpcr2 &= ~TIM_CR2_OIS4;
04865     /* Set the Output Idle state */
04866     tmpcr2 |= (OC_Config->OCIdleState << 6);
04867   }
04868
04869   /* Write to TIMx CR2 */
04870   TIMx->CR2 = tmpcr2;
04871
04872   /* Write to TIMx CCMR2 */
04873   TIMx->CCMR2 = tmpccmrx;
04874
04875   /* Set the Capture Compare Register value */
04876   TIMx->CCR4 = OC_Config->Pulse;
04877
04878   /* Write to TIMx CCER */
04879   TIMx->CCER = tmpccer;
04880 }
04881
04882
04883 /**
04884   * @brief  Time Slave configuration
04885   * @param  htim: pointer to a TIM_HandleTypeDef structure that contains
04886   *                the configuration information for TIM module.
04887   * @param  sSlaveConfig: The slave configuration structure
04888   * @retval None
04889   */
04890 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
04891                               TIM_SlaveConfigTypeDef * sSlaveConfig)
04892 {
04893   uint32_t tmpsmcr = 0U;
04894   uint32_t tmpccmr1 = 0U;
04895   uint32_t tmpccer = 0U;
04896
04897   /* Get the TIMx SMCR register value */
04898   tmpsmcr = htim->Instance->SMCR;
04899
04900   /* Reset the Trigger Selection Bits */
04901   tmpsmcr &= ~TIM_SMCR_TS;
04902   /* Set the Input Trigger source */
04903   tmpsmcr |= sSlaveConfig->InputTrigger;
04904
04905   /* Reset the slave mode Bits */
04906   tmpsmcr &= ~TIM_SMCR_SMS;
04907   /* Set the slave mode */
04908   tmpsmcr |= sSlaveConfig->SlaveMode;
04909
04910   /* Write to TIMx SMCR */
04911   htim->Instance->SMCR = tmpsmcr;
04912
04913   /* Configure the trigger prescaler, filter, and polarity */
04914   switch (sSlaveConfig->InputTrigger)
04915   {
04916   case TIM_TS_ETRF:
04917     {
04918       /* Check the parameters */
04919       assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
04920       assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
04921       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
04922       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04923       /* Configure the ETR Trigger source */
04924       TIM_ETR_SetConfig(htim->Instance,
04925                         sSlaveConfig->TriggerPrescaler,
04926                         sSlaveConfig->TriggerPolarity,
04927                         sSlaveConfig->TriggerFilter);
04928     }
04929     break;
04930
04931   case TIM_TS_TI1F_ED:
04932     {
04933       /* Check the parameters */
04934       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04935       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04936
04937       /* Disable the Channel 1: Reset the CC1E Bit */
04938       tmpccer = htim->Instance->CCER;
04939       htim->Instance->CCER &= ~TIM_CCER_CC1E;
04940       tmpccmr1 = htim->Instance->CCMR1;
04941
04942       /* Set the filter */
04943       tmpccmr1 &= ~TIM_CCMR1_IC1F;
04944       tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
04945
04946       /* Write to TIMx CCMR1 and CCER registers */
04947       htim->Instance->CCMR1 = tmpccmr1;
04948       htim->Instance->CCER = tmpccer;
04949
04950     }
04951     break;
04952
04953   case TIM_TS_TI1FP1:
04954     {
04955       /* Check the parameters */
04956       assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
04957       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
04958       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04959
04960       /* Configure TI1 Filter and Polarity */
04961       TIM_TI1_ConfigInputStage(htim->Instance,
04962                                sSlaveConfig->TriggerPolarity,
04963                                sSlaveConfig->TriggerFilter);
04964     }
04965     break;
04966
04967   case TIM_TS_TI2FP2:
04968     {
04969       /* Check the parameters */
04970       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04971       assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
04972       assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
04973
04974       /* Configure TI2 Filter and Polarity */
04975       TIM_TI2_ConfigInputStage(htim->Instance,
04976                                 sSlaveConfig->TriggerPolarity,
04977                                 sSlaveConfig->TriggerFilter);
04978     }
04979     break;
04980
04981   case TIM_TS_ITR0:
04982     {
04983       /* Check the parameter */
04984       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04985     }
04986     break;
04987
04988   case TIM_TS_ITR1:
04989     {
04990       /* Check the parameter */
04991       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04992     }
04993     break;
04994
04995   case TIM_TS_ITR2:
04996     {
04997       /* Check the parameter */
04998       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
04999     }
05000     break;
05001
05002   case TIM_TS_ITR3:
05003     {
05004       /* Check the parameter */
05005       assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
05006     }
05007     break;
05008
05009   default:
05010     break;
05011   }
05012 }
05013
05014 /**
05015   * @brief  Configure the TI1 as Input.
05016   * @param  TIMx  to select the TIM peripheral.
05017   * @param  TIM_ICPolarity : The Input Polarity.
05018   *          This parameter can be one of the following values:
05019   *            @arg TIM_ICPOLARITY_RISING
05020   *            @arg TIM_ICPOLARITY_FALLING
05021   * @param  TIM_ICSelection : specifies the input to be used.
05022   *          This parameter can be one of the following values:
05023   *            @arg TIM_ICSELECTION_DIRECTTI:    TIM Input 1 is selected to be connected to IC1.
05024   *            @arg TIM_ICSELECTION_INDIRECTTI:  TIM Input 1 is selected to be connected to IC2.
05025   *            @arg TIM_ICSELECTION_TRC:         TIM Input 1 is selected to be connected to TRC.
05026   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05027   *          This parameter must be a value between 0x00 and 0x0F.
05028   * @retval None
05029   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
05030   *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be
05031   *        protected against un-initialized filter and polarity values.
05032   */
05033 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05034                        uint32_t TIM_ICFilter)
05035 {
05036   uint32_t tmpccmr1 = 0U;
05037   uint32_t tmpccer = 0U;
05038
05039   /* Disable the Channel 1: Reset the CC1E Bit */
05040   TIMx->CCER &= ~TIM_CCER_CC1E;
05041   tmpccmr1 = TIMx->CCMR1;
05042   tmpccer = TIMx->CCER;
05043
05044   /* Select the Input */
05045   if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
05046   {
05047     tmpccmr1 &= ~TIM_CCMR1_CC1S;
05048     tmpccmr1 |= TIM_ICSelection;
05049   }
05050   else
05051   {
05052     tmpccmr1 |= TIM_CCMR1_CC1S_0;
05053   }
05054
05055   /* Set the filter */
05056   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05057   tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
05058
05059   /* Select the Polarity and set the CC1E Bit */
05060   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05061   tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
05062
05063   /* Write to TIMx CCMR1 and CCER registers */
05064   TIMx->CCMR1 = tmpccmr1;
05065   TIMx->CCER = tmpccer;
05066 }
05067
05068 /**
05069   * @brief  Configure the Polarity and Filter for TI1.
05070   * @param  TIMx  to select the TIM peripheral.
05071   * @param  TIM_ICPolarity : The Input Polarity.
05072   *          This parameter can be one of the following values:
05073   *            @arg TIM_ICPOLARITY_RISING
05074   *            @arg TIM_ICPOLARITY_FALLING
05075   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05076   *          This parameter must be a value between 0x00 and 0x0F.
05077   * @retval None
05078   */
05079 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05080 {
05081   uint32_t tmpccmr1 = 0U;
05082   uint32_t tmpccer = 0U;
05083
05084   /* Disable the Channel 1: Reset the CC1E Bit */
05085   tmpccer = TIMx->CCER;
05086   TIMx->CCER &= ~TIM_CCER_CC1E;
05087   tmpccmr1 = TIMx->CCMR1;
05088
05089   /* Set the filter */
05090   tmpccmr1 &= ~TIM_CCMR1_IC1F;
05091   tmpccmr1 |= (TIM_ICFilter << 4U);
05092
05093   /* Select the Polarity and set the CC1E Bit */
05094   tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
05095   tmpccer |= TIM_ICPolarity;
05096
05097   /* Write to TIMx CCMR1 and CCER registers */
05098   TIMx->CCMR1 = tmpccmr1;
05099   TIMx->CCER = tmpccer;
05100 }
05101
05102 /**
05103   * @brief  Configure the TI2 as Input.
05104   * @param  TIMx  to select the TIM peripheral
05105   * @param  TIM_ICPolarity : The Input Polarity.
05106   *          This parameter can be one of the following values:
05107   *            @arg TIM_ICPOLARITY_RISING
05108   *            @arg TIM_ICPOLARITY_FALLING
05109   * @param  TIM_ICSelection : specifies the input to be used.
05110   *          This parameter can be one of the following values:
05111   *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 2 is selected to be connected to IC2.
05112   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
05113   *            @arg TIM_ICSELECTION_TRC:        TIM Input 2 is selected to be connected to TRC.
05114   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05115   *          This parameter must be a value between 0x00 and 0x0F.
05116   * @retval None
05117   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
05118   *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be
05119   *        protected against un-initialized filter and polarity values.
05120   */
05121 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05122                        uint32_t TIM_ICFilter)
05123 {
05124   uint32_t tmpccmr1 = 0U;
05125   uint32_t tmpccer = 0U;
05126
05127   /* Disable the Channel 2: Reset the CC2E Bit */
05128   TIMx->CCER &= ~TIM_CCER_CC2E;
05129   tmpccmr1 = TIMx->CCMR1;
05130   tmpccer = TIMx->CCER;
05131
05132   /* Select the Input */
05133   tmpccmr1 &= ~TIM_CCMR1_CC2S;
05134   tmpccmr1 |= (TIM_ICSelection << 8U);
05135
05136   /* Set the filter */
05137   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05138   tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
05139
05140   /* Select the Polarity and set the CC2E Bit */
05141   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05142   tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
05143
05144   /* Write to TIMx CCMR1 and CCER registers */
05145   TIMx->CCMR1 = tmpccmr1 ;
05146   TIMx->CCER = tmpccer;
05147 }
05148
05149 /**
05150   * @brief  Configure the Polarity and Filter for TI2.
05151   * @param  TIMx  to select the TIM peripheral.
05152   * @param  TIM_ICPolarity : The Input Polarity.
05153   *          This parameter can be one of the following values:
05154   *            @arg TIM_ICPOLARITY_RISING
05155   *            @arg TIM_ICPOLARITY_FALLING
05156   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05157   *          This parameter must be a value between 0x00 and 0x0F.
05158   * @retval None
05159   */
05160 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
05161 {
05162   uint32_t tmpccmr1 = 0U;
05163   uint32_t tmpccer = 0U;
05164
05165   /* Disable the Channel 2: Reset the CC2E Bit */
05166   TIMx->CCER &= ~TIM_CCER_CC2E;
05167   tmpccmr1 = TIMx->CCMR1;
05168   tmpccer = TIMx->CCER;
05169
05170   /* Set the filter */
05171   tmpccmr1 &= ~TIM_CCMR1_IC2F;
05172   tmpccmr1 |= (TIM_ICFilter << 12U);
05173
05174   /* Select the Polarity and set the CC2E Bit */
05175   tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
05176   tmpccer |= (TIM_ICPolarity << 4U);
05177
05178   /* Write to TIMx CCMR1 and CCER registers */
05179   TIMx->CCMR1 = tmpccmr1 ;
05180   TIMx->CCER = tmpccer;
05181 }
05182
05183 /**
05184   * @brief  Configure the TI3 as Input.
05185   * @param  TIMx  to select the TIM peripheral
05186   * @param  TIM_ICPolarity : The Input Polarity.
05187   *          This parameter can be one of the following values:
05188   *            @arg TIM_ICPOLARITY_RISING
05189   *            @arg TIM_ICPOLARITY_FALLING
05190   * @param  TIM_ICSelection : specifies the input to be used.
05191   *          This parameter can be one of the following values:
05192   *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 3 is selected to be connected to IC3.
05193   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
05194   *            @arg TIM_ICSELECTION_TRC:        TIM Input 3 is selected to be connected to TRC.
05195   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05196   *          This parameter must be a value between 0x00 and 0x0F.
05197   * @retval None
05198   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
05199   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
05200   *        protected against un-initialized filter and polarity values.
05201   */
05202 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05203                        uint32_t TIM_ICFilter)
05204 {
05205   uint32_t tmpccmr2 = 0U;
05206   uint32_t tmpccer = 0U;
05207
05208   /* Disable the Channel 3: Reset the CC3E Bit */
05209   TIMx->CCER &= ~TIM_CCER_CC3E;
05210   tmpccmr2 = TIMx->CCMR2;
05211   tmpccer = TIMx->CCER;
05212
05213   /* Select the Input */
05214   tmpccmr2 &= ~TIM_CCMR2_CC3S;
05215   tmpccmr2 |= TIM_ICSelection;
05216
05217   /* Set the filter */
05218   tmpccmr2 &= ~TIM_CCMR2_IC3F;
05219   tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
05220
05221   /* Select the Polarity and set the CC3E Bit */
05222   tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
05223   tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
05224
05225   /* Write to TIMx CCMR2 and CCER registers */
05226   TIMx->CCMR2 = tmpccmr2;
05227   TIMx->CCER = tmpccer;
05228 }
05229
05230 /**
05231   * @brief  Configure the TI4 as Input.
05232   * @param  TIMx to select the TIM peripheral
05233   * @param  TIM_ICPolarity : The Input Polarity.
05234   *          This parameter can be one of the following values:
05235   *            @arg TIM_ICPOLARITY_RISING
05236   *            @arg TIM_ICPOLARITY_FALLING
05237   * @param  TIM_ICSelection : specifies the input to be used.
05238   *          This parameter can be one of the following values:
05239   *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 4 is selected to be connected to IC4.
05240   *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
05241   *            @arg TIM_ICSELECTION_TRC:        TIM Input 4 is selected to be connected to TRC.
05242   * @param  TIM_ICFilter : Specifies the Input Capture Filter.
05243   *          This parameter must be a value between 0x00 and 0x0F.
05244   * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
05245   *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be
05246   *        protected against un-initialized filter and polarity values.
05247   * @retval None
05248   */
05249 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
05250                        uint32_t TIM_ICFilter)
05251 {
05252   uint32_t tmpccmr2 = 0U;
05253   uint32_t tmpccer = 0U;
05254
05255   /* Disable the Channel 4: Reset the CC4E Bit */
05256   TIMx->CCER &= ~TIM_CCER_CC4E;
05257   tmpccmr2 = TIMx->CCMR2;
05258   tmpccer = TIMx->CCER;
05259
05260   /* Select the Input */
05261   tmpccmr2 &= ~TIM_CCMR2_CC4S;
05262   tmpccmr2 |= (TIM_ICSelection << 8U);
05263
05264   /* Set the filter */
05265   tmpccmr2 &= ~TIM_CCMR2_IC4F;
05266   tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
05267
05268   /* Select the Polarity and set the CC4E Bit */
05269   tmpccer &= ~TIM_CCER_CC4P;
05270   tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
05271
05272   /* Write to TIMx CCMR2 and CCER registers */
05273   TIMx->CCMR2 = tmpccmr2;
05274   TIMx->CCER = tmpccer ;
05275 }
05276
05277 /**
05278   * @brief  Selects the Input Trigger source
05279   * @param  TIMx  to select the TIM peripheral
05280   * @param  InputTriggerSource : The Input Trigger source.
05281   *          This parameter can be one of the following values:
05282   *            @arg TIM_TS_ITR0 : Internal Trigger 0
05283   *            @arg TIM_TS_ITR1 : Internal Trigger 1
05284   *            @arg TIM_TS_ITR2 : Internal Trigger 2
05285   *            @arg TIM_TS_ITR3 : Internal Trigger 3
05286   *            @arg TIM_TS_TI1F_ED : TI1 Edge Detector
05287   *            @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
05288   *            @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
05289   *            @arg TIM_TS_ETRF : External Trigger input
05290   * @retval None
05291   */
05292 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
05293 {
05294   uint32_t tmpsmcr = 0U;
05295
05296    /* Get the TIMx SMCR register value */
05297    tmpsmcr = TIMx->SMCR;
05298    /* Reset the TS Bits */
05299    tmpsmcr &= ~TIM_SMCR_TS;
05300    /* Set the Input Trigger source and the slave mode*/
05301    tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
05302    /* Write to TIMx SMCR */
05303    TIMx->SMCR = tmpsmcr;
05304 }
05305 /**
05306   * @brief  Configures the TIMx External Trigger (ETR).
05307   * @param  TIMx  to select the TIM peripheral
05308   * @param  TIM_ExtTRGPrescaler : The external Trigger Prescaler.
05309   *          This parameter can be one of the following values:
05310   *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
05311   *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
05312   *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
05313   *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
05314   * @param  TIM_ExtTRGPolarity : The external Trigger Polarity.
05315   *          This parameter can be one of the following values:
05316   *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
05317   *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
05318   * @param  ExtTRGFilter : External Trigger Filter.
05319   *          This parameter must be a value between 0x00 and 0x0F
05320   * @retval None
05321   */
05322 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
05323                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
05324 {
05325   uint32_t tmpsmcr = 0U;
05326
05327   tmpsmcr = TIMx->SMCR;
05328
05329   /* Reset the ETR Bits */
05330   tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
05331
05332   /* Set the Prescaler, the Filter value and the Polarity */
05333   tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
05334
05335   /* Write to TIMx SMCR */
05336   TIMx->SMCR = tmpsmcr;
05337 }
05338
05339 /**
05340   * @brief  Enables or disables the TIM Capture Compare Channel x.
05341   * @param  TIMx  to select the TIM peripheral
05342   * @param  Channel : specifies the TIM Channel
05343   *          This parameter can be one of the following values:
05344   *            @arg TIM_CHANNEL_1: TIM Channel 1
05345   *            @arg TIM_CHANNEL_2: TIM Channel 2
05346   *            @arg TIM_CHANNEL_3: TIM Channel 3
05347   *            @arg TIM_CHANNEL_4: TIM Channel 4
05348   * @param  ChannelState : specifies the TIM Channel CCxE bit new state.
05349   *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
05350   * @retval None
05351   */
05352 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
05353 {
05354   uint32_t tmp = 0U;
05355
05356   /* Check the parameters */
05357   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
05358   assert_param(IS_TIM_CHANNELS(Channel));
05359
05360   tmp = TIM_CCER_CC1E << Channel;
05361
05362   /* Reset the CCxE Bit */
05363   TIMx->CCER &= ~tmp;
05364
05365   /* Set or reset the CCxE Bit */
05366   TIMx->CCER |=  (uint32_t)(ChannelState << Channel);
05367 }
05368
05369 /**
05370   * @}
05371   */
05372
05373 #endif /* HAL_TIM_MODULE_ENABLED */
05374 /**
05375   * @}
05376   */
05377
05378 /**
05379   * @}
05380   */
05381 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_tim.h Source File

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stm32f1xx_hal_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_tim.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of TIM HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_TIM_H
00040 #define __STM32F1xx_HAL_TIM_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TIM
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIM_Exported_Types TIM Exported Types
00059   * @{
00060   */
00061 /**
00062   * @brief  TIM Time base Configuration Structure definition
00063   */
00064 typedef struct
00065 {
00066   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00067                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00068
00069   uint32_t CounterMode;       /*!< Specifies the counter mode.
00070                                    This parameter can be a value of @ref TIM_Counter_Mode */
00071
00072   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
00073                                    Auto-Reload Register at the next update event.
00074                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
00075
00076   uint32_t ClockDivision;     /*!< Specifies the clock division.
00077                                    This parameter can be a value of @ref TIM_ClockDivision */
00078
00079   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00080                                     reaches zero, an update event is generated and counting restarts
00081                                     from the RCR value (N).
00082                                     This means in PWM mode that (N+1) corresponds to:
00083                                         - the number of PWM periods in edge-aligned mode
00084                                         - the number of half PWM period in center-aligned mode
00085                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00086                                      @note This parameter is valid only for TIM1 and TIM8. */
00087
00088   uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
00089                                     This parameter can be a value of @ref TIM_AutoReloadPreload */
00090 } TIM_Base_InitTypeDef;
00091
00092 /**
00093   * @brief  TIM Output Compare Configuration Structure definition
00094   */
00095 typedef struct
00096 {
00097   uint32_t OCMode;        /*!< Specifies the TIM mode.
00098                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00099
00100   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00101                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00102
00103   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00104                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00105
00106   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00107                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00108                                @note This parameter is valid only for TIM1 and TIM8. */
00109
00110   uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
00111                                This parameter can be a value of @ref TIM_Output_Fast_State
00112                                @note This parameter is valid only in PWM1 and PWM2 mode. */
00113
00114
00115   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00116                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00117                                @note This parameter is valid only for TIM1 and TIM8. */
00118
00119   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00120                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00121                                @note This parameter is valid only for TIM1 and TIM8. */
00122 } TIM_OC_InitTypeDef;
00123
00124 /**
00125   * @brief  TIM One Pulse Mode Configuration Structure definition
00126   */
00127 typedef struct
00128 {
00129   uint32_t OCMode;        /*!< Specifies the TIM mode.
00130                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
00131
00132   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00133                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00134
00135   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00136                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
00137
00138   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00139                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
00140                                @note This parameter is valid only for TIM1 and TIM8. */
00141
00142   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00143                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
00144                                @note This parameter is valid only for TIM1 and TIM8. */
00145
00146   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00147                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
00148                                @note This parameter is valid only for TIM1 and TIM8. */
00149
00150   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00151                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00152
00153   uint32_t ICSelection;   /*!< Specifies the input.
00154                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00155
00156   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00157                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00158 } TIM_OnePulse_InitTypeDef;
00159
00160
00161 /**
00162   * @brief  TIM Input Capture Configuration Structure definition
00163   */
00164 typedef struct
00165 {
00166   uint32_t  ICPolarity;   /*!< Specifies the active edge of the input signal.
00167                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00168
00169   uint32_t ICSelection;  /*!< Specifies the input.
00170                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00171
00172   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
00173                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00174
00175   uint32_t ICFilter;     /*!< Specifies the input capture filter.
00176                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00177 } TIM_IC_InitTypeDef;
00178
00179 /**
00180   * @brief  TIM Encoder Configuration Structure definition
00181   */
00182 typedef struct
00183 {
00184   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
00185                                This parameter can be a value of @ref TIM_Encoder_Mode */
00186
00187   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
00188                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00189
00190   uint32_t IC1Selection;  /*!< Specifies the input.
00191                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
00192
00193   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
00194                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00195
00196   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
00197                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00198
00199   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
00200                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00201
00202   uint32_t IC2Selection;  /*!< Specifies the input.
00203                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
00204
00205   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
00206                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00207
00208   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
00209                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00210 } TIM_Encoder_InitTypeDef;
00211
00212
00213 /**
00214   * @brief  TIM Clock Configuration Handle Structure definition
00215   */
00216 typedef struct
00217 {
00218   uint32_t ClockSource;     /*!< TIM clock sources
00219                                  This parameter can be a value of @ref TIM_Clock_Source */
00220   uint32_t ClockPolarity;   /*!< TIM clock polarity
00221                                  This parameter can be a value of @ref TIM_Clock_Polarity */
00222   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
00223                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
00224   uint32_t ClockFilter;    /*!< TIM clock filter
00225                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00226 }TIM_ClockConfigTypeDef;
00227
00228 /**
00229   * @brief  TIM Clear Input Configuration Handle Structure definition
00230   */
00231 typedef struct
00232 {
00233   uint32_t ClearInputState;      /*!< TIM clear Input state
00234                                       This parameter can be ENABLE or DISABLE */
00235   uint32_t ClearInputSource;     /*!< TIM clear Input sources
00236                                       This parameter can be a value of @ref TIM_ClearInput_Source */
00237   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
00238                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
00239   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
00240                                       This parameter can be a value of @ref TIM_ClearInput_Prescaler */
00241   uint32_t ClearInputFilter;    /*!< TIM Clear Input filter
00242                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00243 }TIM_ClearInputConfigTypeDef;
00244
00245 /**
00246   * @brief  TIM Slave configuration Structure definition
00247   */
00248 typedef struct {
00249   uint32_t  SlaveMode;      /*!< Slave mode selection
00250                                This parameter can be a value of @ref TIM_Slave_Mode */
00251   uint32_t  InputTrigger;      /*!< Input Trigger source
00252                                   This parameter can be a value of @ref TIM_Trigger_Selection */
00253   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
00254                                   This parameter can be a value of @ref TIM_Trigger_Polarity */
00255   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
00256                                   This parameter can be a value of @ref TIM_Trigger_Prescaler */
00257   uint32_t  TriggerFilter;     /*!< Input trigger filter
00258                                   This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00259
00260 }TIM_SlaveConfigTypeDef;
00261
00262 /**
00263   * @brief  HAL State structures definition
00264   */
00265 typedef enum
00266 {
00267   HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
00268   HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
00269   HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
00270   HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
00271   HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
00272 }HAL_TIM_StateTypeDef;
00273
00274 /**
00275   * @brief  HAL Active channel structures definition
00276   */
00277 typedef enum
00278 {
00279   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
00280   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
00281   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
00282   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
00283   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
00284 }HAL_TIM_ActiveChannel;
00285
00286 /**
00287   * @brief  TIM Time Base Handle Structure definition
00288   */
00289 typedef struct
00290 {
00291   TIM_TypeDef                 *Instance;     /*!< Register base address             */
00292   TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */
00293   HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */
00294   DMA_HandleTypeDef           *hdma[7U];     /*!< DMA Handlers array
00295                                                 This array is accessed by a @ref TIM_DMA_Handle_index */
00296   HAL_LockTypeDef             Lock;          /*!< Locking object                    */
00297   __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */
00298 }TIM_HandleTypeDef;
00299
00300 /**
00301   * @}
00302   */
00303
00304 /* Exported constants --------------------------------------------------------*/
00305 /** @defgroup TIM_Exported_Constants TIM Exported Constants
00306   * @{
00307   */
00308
00309 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
00310   * @{
00311   */
00312 #define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
00313 #define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
00314 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
00315 /**
00316   * @}
00317   */
00318
00319 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
00320   * @{
00321   */
00322 #define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
00323 #define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
00324 /**
00325   * @}
00326   */
00327
00328 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
00329   * @{
00330   */
00331 #define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
00332 #define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
00333 #define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
00334 #define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
00335 /**
00336   * @}
00337   */
00338
00339 /** @defgroup TIM_Counter_Mode TIM Counter Mode
00340   * @{
00341   */
00342 #define TIM_COUNTERMODE_UP                 0x00000000U
00343 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
00344 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
00345 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
00346 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
00347 /**
00348   * @}
00349   */
00350
00351 /** @defgroup TIM_ClockDivision TIM ClockDivision
00352   * @{
00353   */
00354 #define TIM_CLOCKDIVISION_DIV1                       0x00000000U
00355 #define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
00356 #define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
00357 /**
00358   * @}
00359   */
00360
00361 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
00362   * @{
00363   */
00364 #define TIM_AUTORELOAD_PRELOAD_DISABLE                0x0000U              /*!< TIMx_ARR register is not buffered */
00365 #define TIM_AUTORELOAD_PRELOAD_ENABLE                 (TIM_CR1_ARPE)       /*!< TIMx_ARR register is buffered */
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
00371   * @{
00372   */
00373 #define TIM_OCMODE_TIMING                   0x00000000U
00374 #define TIM_OCMODE_ACTIVE                   (TIM_CCMR1_OC1M_0)
00375 #define TIM_OCMODE_INACTIVE                 (TIM_CCMR1_OC1M_1)
00376 #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
00377 #define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
00378 #define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M)
00379 #define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
00380 #define TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)
00381 /**
00382   * @}
00383   */
00384
00385 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
00386   * @{
00387   */
00388 #define TIM_OUTPUTSTATE_DISABLE            0x00000000U
00389 #define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
00390 /**
00391   * @}
00392   */
00393
00394 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
00395   * @{
00396   */
00397 #define TIM_OCFAST_DISABLE                0x00000000U
00398 #define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
00399 /**
00400   * @}
00401   */
00402
00403 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
00404   * @{
00405   */
00406 #define TIM_OUTPUTNSTATE_DISABLE            0x00000000U
00407 #define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)
00408 /**
00409   * @}
00410   */
00411
00412 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
00413   * @{
00414   */
00415 #define TIM_OCPOLARITY_HIGH                0x00000000U
00416 #define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
00417 /**
00418   * @}
00419   */
00420
00421 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
00422   * @{
00423   */
00424 #define TIM_OCNPOLARITY_HIGH               0x00000000U
00425 #define TIM_OCNPOLARITY_LOW                (TIM_CCER_CC1NP)
00426 /**
00427   * @}
00428   */
00429
00430 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
00431   * @{
00432   */
00433 #define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
00434 #define TIM_OCIDLESTATE_RESET              0x00000000U
00435 /**
00436   * @}
00437   */
00438
00439 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
00440   * @{
00441   */
00442 #define TIM_OCNIDLESTATE_SET               (TIM_CR2_OIS1N)
00443 #define TIM_OCNIDLESTATE_RESET             0x00000000U
00444 /**
00445   * @}
00446   */
00447
00448 /** @defgroup TIM_Channel TIM Channel
00449   * @{
00450   */
00451 #define TIM_CHANNEL_1                      0x00000000U
00452 #define TIM_CHANNEL_2                      0x00000004U
00453 #define TIM_CHANNEL_3                      0x00000008U
00454 #define TIM_CHANNEL_4                      0x0000000CU
00455 #define TIM_CHANNEL_ALL                    0x00000018U
00456 /**
00457   * @}
00458   */
00459
00460 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
00461   * @{
00462   */
00463 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
00464 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
00465 /**
00466   * @}
00467   */
00468
00469 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
00470   * @{
00471   */
00472 #define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00473                                                                                connected to IC1, IC2, IC3 or IC4, respectively */
00474 #define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
00475                                                                                connected to IC2, IC1, IC4 or IC3, respectively */
00476 #define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
00477 /**
00478   * @}
00479   */
00480
00481 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
00482   * @{
00483   */
00484 #define TIM_ICPSC_DIV1                     0x00000000U              /*!< Capture performed each time an edge is detected on the capture input */
00485 #define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
00486 #define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
00487 #define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
00488 /**
00489   * @}
00490   */
00491
00492 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
00493   * @{
00494   */
00495 #define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
00496 #define TIM_OPMODE_REPETITIVE              0x00000000U
00497 /**
00498   * @}
00499   */
00500
00501 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
00502   * @{
00503   */
00504 #define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
00505 #define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
00506 #define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
00507 /**
00508   * @}
00509   */
00510
00511 /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
00512   * @{
00513   */
00514 #define TIM_IT_UPDATE           (TIM_DIER_UIE)
00515 #define TIM_IT_CC1              (TIM_DIER_CC1IE)
00516 #define TIM_IT_CC2              (TIM_DIER_CC2IE)
00517 #define TIM_IT_CC3              (TIM_DIER_CC3IE)
00518 #define TIM_IT_CC4              (TIM_DIER_CC4IE)
00519 #define TIM_IT_COM              (TIM_DIER_COMIE)
00520 #define TIM_IT_TRIGGER          (TIM_DIER_TIE)
00521 #define TIM_IT_BREAK            (TIM_DIER_BIE)
00522 /**
00523   * @}
00524   */
00525
00526 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
00527   * @{
00528   */
00529 #define TIM_COMMUTATION_TRGI              (TIM_CR2_CCUS)
00530 #define TIM_COMMUTATION_SOFTWARE          0x00000000U
00531
00532 /**
00533   * @}
00534   */
00535
00536 /** @defgroup TIM_DMA_sources TIM DMA Sources
00537   * @{
00538   */
00539 #define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
00540 #define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
00541 #define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
00542 #define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
00543 #define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
00544 #define TIM_DMA_COM                        (TIM_DIER_COMDE)
00545 #define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
00546 /**
00547   * @}
00548   */
00549
00550 /** @defgroup TIM_Event_Source TIM Event Source
00551   * @{
00552   */
00553 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG
00554 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G
00555 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G
00556 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G
00557 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G
00558 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG
00559 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG
00560 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup TIM_Flag_definition TIM Flag Definition
00566   * @{
00567   */
00568 #define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
00569 #define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
00570 #define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
00571 #define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
00572 #define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
00573 #define TIM_FLAG_COM                       (TIM_SR_COMIF)
00574 #define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
00575 #define TIM_FLAG_BREAK                     (TIM_SR_BIF)
00576 #define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
00577 #define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
00578 #define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
00579 #define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
00580 /**
00581   * @}
00582   */
00583
00584 /** @defgroup TIM_Clock_Source TIM Clock Source
00585   * @{
00586   */
00587 #define TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
00588 #define TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
00589 #define TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
00590 #define TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
00591 #define TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
00592 #define TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
00593 #define TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
00594 #define TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
00595 #define TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
00596 #define TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
00597 /**
00598   * @}
00599   */
00600
00601 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
00602   * @{
00603   */
00604 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
00605 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
00606 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
00607 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
00608 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
00609 /**
00610   * @}
00611   */
00612
00613 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
00614   * @{
00615   */
00616 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00617 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
00618 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
00619 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
00620 /**
00621   * @}
00622   */
00623
00624 /** @defgroup TIM_ClearInput_Source TIM ClearInput Source
00625   * @{
00626   */
00627 #define TIM_CLEARINPUTSOURCE_ETR           0x00000001U
00628 #define TIM_CLEARINPUTSOURCE_NONE          0x00000000U
00629 /**
00630   * @}
00631   */
00632
00633 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
00634   * @{
00635   */
00636 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED                    /*!< Polarity for ETRx pin */
00637 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED                 /*!< Polarity for ETRx pin */
00638 /**
00639   * @}
00640   */
00641
00642 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
00643   * @{
00644   */
00645 #define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
00646 #define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
00647 #define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
00648 #define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8        /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
00649 /**
00650   * @}
00651   */
00652
00653 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
00654   * @{
00655   */
00656 #define TIM_OSSR_ENABLE         (TIM_BDTR_OSSR)
00657 #define TIM_OSSR_DISABLE        0x00000000U
00658 /**
00659   * @}
00660   */
00661
00662 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
00663   * @{
00664   */
00665 #define TIM_OSSI_ENABLE        (TIM_BDTR_OSSI)
00666 #define TIM_OSSI_DISABLE       0x00000000U
00667 /**
00668   * @}
00669   */
00670
00671 /** @defgroup TIM_Lock_level TIM Lock level
00672   * @{
00673   */
00674 #define TIM_LOCKLEVEL_OFF          0x00000000U
00675 #define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
00676 #define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
00677 #define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
00678 /**
00679   * @}
00680   */
00681
00682 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
00683   * @{
00684   */
00685 #define TIM_BREAK_ENABLE          (TIM_BDTR_BKE)
00686 #define TIM_BREAK_DISABLE         0x00000000U
00687 /**
00688   * @}
00689   */
00690
00691 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
00692   * @{
00693   */
00694 #define TIM_BREAKPOLARITY_LOW        0x00000000U
00695 #define TIM_BREAKPOLARITY_HIGH       (TIM_BDTR_BKP)
00696 /**
00697   * @}
00698   */
00699 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
00700   * @{
00701   */
00702 #define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
00703 #define TIM_AUTOMATICOUTPUT_DISABLE          0x00000000U
00704 /**
00705   * @}
00706   */
00707
00708 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
00709   * @{
00710   */
00711 #define TIM_TRGO_RESET            0x00000000U
00712 #define TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
00713 #define TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
00714 #define TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00715 #define TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
00716 #define TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
00717 #define TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
00718 #define TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
00719 /**
00720   * @}
00721   */
00722
00723 /** @defgroup TIM_Slave_Mode TIM Slave Mode
00724   * @{
00725   */
00726 #define TIM_SLAVEMODE_DISABLE              0x00000000U
00727 #define TIM_SLAVEMODE_RESET                0x00000004U
00728 #define TIM_SLAVEMODE_GATED                0x00000005U
00729 #define TIM_SLAVEMODE_TRIGGER              0x00000006U
00730 #define TIM_SLAVEMODE_EXTERNAL1            0x00000007U
00731 /**
00732   * @}
00733   */
00734
00735 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
00736   * @{
00737   */
00738 #define TIM_MASTERSLAVEMODE_ENABLE          0x00000080U
00739 #define TIM_MASTERSLAVEMODE_DISABLE         0x00000000U
00740 /**
00741   * @}
00742   */
00743
00744 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
00745   * @{
00746   */
00747 #define TIM_TS_ITR0                        0x00000000U
00748 #define TIM_TS_ITR1                        0x00000010U
00749 #define TIM_TS_ITR2                        0x00000020U
00750 #define TIM_TS_ITR3                        0x00000030U
00751 #define TIM_TS_TI1F_ED                     0x00000040U
00752 #define TIM_TS_TI1FP1                      0x00000050U
00753 #define TIM_TS_TI2FP2                      0x00000060U
00754 #define TIM_TS_ETRF                        0x00000070U
00755 #define TIM_TS_NONE                        0x0000FFFFU
00756 /**
00757   * @}
00758   */
00759
00760 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
00761   * @{
00762   */
00763 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx trigger sources */
00764 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx trigger sources */
00765 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00766 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00767 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
00768 /**
00769   * @}
00770   */
00771
00772 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
00773   * @{
00774   */
00775 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
00776 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
00777 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
00778 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
00779 /**
00780   * @}
00781   */
00782
00783 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
00784   * @{
00785   */
00786 #define TIM_TI1SELECTION_CH1                0x00000000U
00787 #define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
00788 /**
00789   * @}
00790   */
00791
00792 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
00793   * @{
00794   */
00795 #define TIM_DMABASE_CR1                    0x00000000U
00796 #define TIM_DMABASE_CR2                    0x00000001U
00797 #define TIM_DMABASE_SMCR                   0x00000002U
00798 #define TIM_DMABASE_DIER                   0x00000003U
00799 #define TIM_DMABASE_SR                     0x00000004U
00800 #define TIM_DMABASE_EGR                    0x00000005U
00801 #define TIM_DMABASE_CCMR1                  0x00000006U
00802 #define TIM_DMABASE_CCMR2                  0x00000007U
00803 #define TIM_DMABASE_CCER                   0x00000008U
00804 #define TIM_DMABASE_CNT                    0x00000009U
00805 #define TIM_DMABASE_PSC                    0x0000000AU
00806 #define TIM_DMABASE_ARR                    0x0000000BU
00807 #define TIM_DMABASE_RCR                    0x0000000CU
00808 #define TIM_DMABASE_CCR1                   0x0000000DU
00809 #define TIM_DMABASE_CCR2                   0x0000000EU
00810 #define TIM_DMABASE_CCR3                   0x0000000FU
00811 #define TIM_DMABASE_CCR4                   0x00000010U
00812 #define TIM_DMABASE_BDTR                   0x00000011U
00813 #define TIM_DMABASE_DCR                    0x00000012U
00814 /**
00815   * @}
00816   */
00817
00818 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
00819   * @{
00820   */
00821 #define TIM_DMABURSTLENGTH_1TRANSFER           0x00000000U
00822 #define TIM_DMABURSTLENGTH_2TRANSFERS          0x00000100U
00823 #define TIM_DMABURSTLENGTH_3TRANSFERS          0x00000200U
00824 #define TIM_DMABURSTLENGTH_4TRANSFERS          0x00000300U
00825 #define TIM_DMABURSTLENGTH_5TRANSFERS          0x00000400U
00826 #define TIM_DMABURSTLENGTH_6TRANSFERS          0x00000500U
00827 #define TIM_DMABURSTLENGTH_7TRANSFERS          0x00000600U
00828 #define TIM_DMABURSTLENGTH_8TRANSFERS          0x00000700U
00829 #define TIM_DMABURSTLENGTH_9TRANSFERS          0x00000800U
00830 #define TIM_DMABURSTLENGTH_10TRANSFERS         0x00000900U
00831 #define TIM_DMABURSTLENGTH_11TRANSFERS         0x00000A00U
00832 #define TIM_DMABURSTLENGTH_12TRANSFERS         0x00000B00U
00833 #define TIM_DMABURSTLENGTH_13TRANSFERS         0x00000C00U
00834 #define TIM_DMABURSTLENGTH_14TRANSFERS         0x00000D00U
00835 #define TIM_DMABURSTLENGTH_15TRANSFERS         0x00000E00U
00836 #define TIM_DMABURSTLENGTH_16TRANSFERS         0x00000F00U
00837 #define TIM_DMABURSTLENGTH_17TRANSFERS         0x00001000U
00838 #define TIM_DMABURSTLENGTH_18TRANSFERS         0x00001100U
00839 /**
00840   * @}
00841   */
00842
00843 /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
00844   * @{
00845   */
00846 #define TIM_DMA_ID_UPDATE                ((uint16_t)0x0)       /*!< Index of the DMA handle used for Update DMA requests */
00847 #define TIM_DMA_ID_CC1                   ((uint16_t)0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
00848 #define TIM_DMA_ID_CC2                   ((uint16_t)0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
00849 #define TIM_DMA_ID_CC3                   ((uint16_t)0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
00850 #define TIM_DMA_ID_CC4                   ((uint16_t)0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
00851 #define TIM_DMA_ID_COMMUTATION           ((uint16_t)0x5)       /*!< Index of the DMA handle used for Commutation DMA requests */
00852 #define TIM_DMA_ID_TRIGGER               ((uint16_t)0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
00853 /**
00854   * @}
00855   */
00856
00857 /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
00858   * @{
00859   */
00860 #define TIM_CCx_ENABLE                   0x00000001U
00861 #define TIM_CCx_DISABLE                  0x00000000U
00862 #define TIM_CCxN_ENABLE                  0x00000004U
00863 #define TIM_CCxN_DISABLE                 0x00000000U
00864 /**
00865   * @}
00866   */
00867
00868 /**
00869   * @}
00870   */
00871
00872 /* Private Constants -----------------------------------------------------------*/
00873 /** @defgroup TIM_Private_Constants TIM Private Constants
00874   * @{
00875   */
00876
00877 /* The counter of a timer instance is disabled only if all the CCx and CCxN
00878    channels have been disabled */
00879 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
00880 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
00881
00882 /**
00883   * @}
00884   */
00885
00886 /* Private Macros -----------------------------------------------------------*/
00887 /** @defgroup TIM_Private_Macros TIM Private Macros
00888  * @{
00889  */
00890
00891 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP)              || \
00892                                    ((MODE) == TIM_COUNTERMODE_DOWN)            || \
00893                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
00894                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
00895                                    ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
00896
00897 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
00898                                        ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
00899                                        ((DIV) == TIM_CLOCKDIVISION_DIV4))
00900
00901 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
00902                                             ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
00903
00904 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
00905                                ((MODE) == TIM_OCMODE_PWM2))
00906
00907 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)       || \
00908                           ((MODE) == TIM_OCMODE_ACTIVE)           || \
00909                           ((MODE) == TIM_OCMODE_INACTIVE)         || \
00910                           ((MODE) == TIM_OCMODE_TOGGLE)           || \
00911                           ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
00912                           ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
00913
00914 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
00915                                   ((STATE) == TIM_OCFAST_ENABLE))
00916
00917 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
00918                                       ((POLARITY) == TIM_OCPOLARITY_LOW))
00919
00920 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
00921                                        ((POLARITY) == TIM_OCNPOLARITY_LOW))
00922
00923 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
00924                                     ((STATE) == TIM_OCIDLESTATE_RESET))
00925
00926 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
00927                                      ((STATE) == TIM_OCNIDLESTATE_RESET))
00928
00929 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00930                                   ((CHANNEL) == TIM_CHANNEL_2) || \
00931                                   ((CHANNEL) == TIM_CHANNEL_3) || \
00932                                   ((CHANNEL) == TIM_CHANNEL_4) || \
00933                                   ((CHANNEL) == TIM_CHANNEL_ALL))
00934
00935 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00936                                       ((CHANNEL) == TIM_CHANNEL_2))
00937
00938 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
00939                                                 ((CHANNEL) == TIM_CHANNEL_2) || \
00940                                                 ((CHANNEL) == TIM_CHANNEL_3))
00941
00942 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING)   || \
00943                                       ((POLARITY) == TIM_ICPOLARITY_FALLING))
00944
00945 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI)   || \
00946                                         ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
00947                                         ((SELECTION) == TIM_ICSELECTION_TRC))
00948
00949 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
00950                                         ((PRESCALER) == TIM_ICPSC_DIV2) || \
00951                                         ((PRESCALER) == TIM_ICPSC_DIV4) || \
00952                                         ((PRESCALER) == TIM_ICPSC_DIV8))
00953
00954 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
00955                                ((MODE) == TIM_OPMODE_REPETITIVE))
00956
00957 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
00958                                    ((MODE) == TIM_ENCODERMODE_TI2) || \
00959                                    ((MODE) == TIM_ENCODERMODE_TI12))
00960
00961 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
00962
00963 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
00964
00965 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
00966                                    ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
00967                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
00968                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
00969                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
00970                                    ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
00971                                    ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
00972                                    ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
00973                                    ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
00974                                    ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
00975
00976 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
00977                                         ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
00978                                         ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
00979                                         ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
00980                                         ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
00981
00982 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
00983                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
00984                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
00985                                           ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
00986
00987 #define IS_TIM_CLOCKFILTER(ICFILTER)       ((ICFILTER) <= 0x0FU)
00988
00989 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)      || \
00990                                           ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
00991
00992 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
00993                                               ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
00994
00995 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)   (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
00996                                                   ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
00997                                                   ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
00998                                                   ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
00999
01000 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
01001
01002 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
01003                                   ((STATE) == TIM_OSSR_DISABLE))
01004
01005 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
01006                                   ((STATE) == TIM_OSSI_DISABLE))
01007
01008 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
01009                                   ((LEVEL) == TIM_LOCKLEVEL_1)   || \
01010                                   ((LEVEL) == TIM_LOCKLEVEL_2)   || \
01011                                   ((LEVEL) == TIM_LOCKLEVEL_3))
01012
01013 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
01014                                    ((STATE) == TIM_BREAK_DISABLE))
01015
01016 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
01017                                          ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
01018
01019 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
01020                                               ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
01021
01022 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET)  || \
01023                                     ((SOURCE) == TIM_TRGO_ENABLE) || \
01024                                     ((SOURCE) == TIM_TRGO_UPDATE) || \
01025                                     ((SOURCE) == TIM_TRGO_OC1)    || \
01026                                     ((SOURCE) == TIM_TRGO_OC1REF) || \
01027                                     ((SOURCE) == TIM_TRGO_OC2REF) || \
01028                                     ((SOURCE) == TIM_TRGO_OC3REF) || \
01029                                     ((SOURCE) == TIM_TRGO_OC4REF))
01030
01031 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
01032                                  ((MODE) == TIM_SLAVEMODE_GATED)   || \
01033                                  ((MODE) == TIM_SLAVEMODE_RESET)   || \
01034                                  ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
01035                                  ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
01036
01037 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
01038                                  ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
01039
01040 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0)    || \
01041                                              ((SELECTION) == TIM_TS_ITR1)    || \
01042                                              ((SELECTION) == TIM_TS_ITR2)    || \
01043                                              ((SELECTION) == TIM_TS_ITR3)    || \
01044                                              ((SELECTION) == TIM_TS_TI1F_ED) || \
01045                                              ((SELECTION) == TIM_TS_TI1FP1)  || \
01046                                              ((SELECTION) == TIM_TS_TI2FP2)  || \
01047                                              ((SELECTION) == TIM_TS_ETRF))
01048
01049 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
01050                                                            ((SELECTION) == TIM_TS_ITR1) || \
01051                                                            ((SELECTION) == TIM_TS_ITR2) || \
01052                                                            ((SELECTION) == TIM_TS_ITR3) || \
01053                                                            ((SELECTION) == TIM_TS_NONE))
01054
01055 #define IS_TIM_TRIGGERPOLARITY(POLARITY)     (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
01056                                               ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
01057                                               ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
01058                                               ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
01059                                               ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
01060
01061 #define IS_TIM_TRIGGERPRESCALER(PRESCALER)  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
01062                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
01063                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
01064                                              ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
01065
01066 #define IS_TIM_TRIGGERFILTER(ICFILTER)     ((ICFILTER) <= 0x0FU)
01067
01068 #define IS_TIM_TI1SELECTION(TI1SELECTION)   (((TI1SELECTION) == TIM_TI1SELECTION_CH1)            || \
01069                                              ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
01070
01071 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1)   || \
01072                                ((BASE) == TIM_DMABASE_CR2)   || \
01073                                ((BASE) == TIM_DMABASE_SMCR)  || \
01074                                ((BASE) == TIM_DMABASE_DIER)  || \
01075                                ((BASE) == TIM_DMABASE_SR)    || \
01076                                ((BASE) == TIM_DMABASE_EGR)   || \
01077                                ((BASE) == TIM_DMABASE_CCMR1) || \
01078                                ((BASE) == TIM_DMABASE_CCMR2) || \
01079                                ((BASE) == TIM_DMABASE_CCER)  || \
01080                                ((BASE) == TIM_DMABASE_CNT)   || \
01081                                ((BASE) == TIM_DMABASE_PSC)   || \
01082                                ((BASE) == TIM_DMABASE_ARR)   || \
01083                                ((BASE) == TIM_DMABASE_RCR)   || \
01084                                ((BASE) == TIM_DMABASE_CCR1)  || \
01085                                ((BASE) == TIM_DMABASE_CCR2)  || \
01086                                ((BASE) == TIM_DMABASE_CCR3)  || \
01087                                ((BASE) == TIM_DMABASE_CCR4)  || \
01088                                ((BASE) == TIM_DMABASE_BDTR)  || \
01089                                ((BASE) == TIM_DMABASE_DCR))
01090
01091 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
01092                                    ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
01093                                    ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
01094                                    ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
01095                                    ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
01096                                    ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
01097                                    ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
01098                                    ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
01099                                    ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
01100                                    ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
01101                                    ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
01102                                    ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
01103                                    ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
01104                                    ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
01105                                    ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
01106                                    ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
01107                                    ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
01108                                    ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
01109
01110 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
01111
01112 /** @brief Set TIM IC prescaler
01113   * @param  __HANDLE__: TIM handle
01114   * @param  __CHANNEL__: specifies TIM Channel
01115   * @param  __ICPSC__: specifies the prescaler value.
01116   * @retval None
01117   */
01118 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
01119 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
01120  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
01121  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
01122  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
01123
01124 /** @brief Reset TIM IC prescaler
01125   * @param  __HANDLE__: TIM handle
01126   * @param  __CHANNEL__: specifies TIM Channel
01127   * @retval None
01128   */
01129 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
01130 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
01131  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
01132  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
01133  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
01134
01135
01136 /** @brief Set TIM IC polarity
01137   * @param  __HANDLE__: TIM handle
01138   * @param  __CHANNEL__: specifies TIM Channel
01139   * @param  __POLARITY__: specifies TIM Channel Polarity
01140   * @retval None
01141   */
01142 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
01143 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
01144  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
01145  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
01146  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
01147
01148 /** @brief Reset TIM IC polarity
01149   * @param  __HANDLE__: TIM handle
01150   * @param  __CHANNEL__: specifies TIM Channel
01151   * @retval None
01152   */
01153 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
01154 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
01155  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
01156  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
01157  ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
01158
01159 /**
01160   * @}
01161   */
01162
01163 /* Private Functions --------------------------------------------------------*/
01164 /** @addtogroup TIM_Private_Functions
01165  * @{
01166  */
01167 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
01168 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
01169 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
01170 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
01171 void TIM_DMAError(DMA_HandleTypeDef *hdma);
01172 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
01173 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
01174 /**
01175   * @}
01176   */
01177
01178 /* Exported macros -----------------------------------------------------------*/
01179 /** @defgroup TIM_Exported_Macros TIM Exported Macros
01180   * @{
01181   */
01182
01183 /** @brief  Reset TIM handle state
01184   * @param  __HANDLE__: TIM handle.
01185   * @retval None
01186   */
01187 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
01188
01189 /**
01190   * @brief  Enable the TIM peripheral.
01191   * @param  __HANDLE__: TIM handle
01192   * @retval None
01193  */
01194 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
01195
01196 /**
01197   * @brief  Enable the TIM main Output.
01198   * @param  __HANDLE__: TIM handle
01199   * @retval None
01200   */
01201 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
01202
01203 /**
01204   * @brief  Disable the TIM peripheral.
01205   * @param  __HANDLE__: TIM handle
01206   * @retval None
01207   */
01208 #define __HAL_TIM_DISABLE(__HANDLE__) \
01209                         do { \
01210                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
01211                             { \
01212                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
01213                             { \
01214                               (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
01215                             } \
01216                           } \
01217                         } while(0U)
01218 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
01219    channels have been disabled */
01220 /**
01221   * @brief  Disable the TIM main Output.
01222   * @param  __HANDLE__: TIM handle
01223   * @retval None
01224   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
01225   */
01226 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
01227                         do { \
01228                           if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
01229                           { \
01230                             if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
01231                             { \
01232                               (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
01233                             } \
01234                             } \
01235                         } while(0U)
01236
01237 /**
01238   * @brief  Disable the TIM main Output.
01239   * @param  __HANDLE__: TIM handle
01240   * @retval None
01241   * @note The Main Output Enable of a timer instance is disabled unconditionally
01242   */
01243 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
01244
01245 /**
01246   * @brief  Enables the specified TIM interrupt.
01247   * @param  __HANDLE__: specifies the TIM Handle.
01248   * @param  __INTERRUPT__: specifies the TIM interrupt source to enable.
01249   *          This parameter can be one of the following values:
01250   *            @arg TIM_IT_UPDATE: Update interrupt
01251   *            @arg TIM_IT_CC1:  Capture/Compare 1 interrupt
01252   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01253   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01254   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01255   *            @arg TIM_IT_COM:  Commutation interrupt
01256   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01257   *            @arg TIM_IT_BREAK: Break interrupt
01258   * @retval None
01259   */
01260 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
01261
01262 /**
01263   * @brief  Disables the specified TIM interrupt.
01264   * @param  __HANDLE__: specifies the TIM Handle.
01265   * @param  __INTERRUPT__: specifies the TIM interrupt source to disable.
01266   *          This parameter can be one of the following values:
01267   *            @arg TIM_IT_UPDATE: Update interrupt
01268   *            @arg TIM_IT_CC1:  Capture/Compare 1 interrupt
01269   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
01270   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
01271   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
01272   *            @arg TIM_IT_COM:  Commutation interrupt
01273   *            @arg TIM_IT_TRIGGER: Trigger interrupt
01274   *            @arg TIM_IT_BREAK: Break interrupt
01275   * @retval None
01276   */
01277 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
01278
01279 /**
01280   * @brief  Enables the specified DMA request.
01281   * @param  __HANDLE__: specifies the TIM Handle.
01282   * @param  __DMA__: specifies the TIM DMA request to enable.
01283   *          This parameter can be one of the following values:
01284   *            @arg TIM_DMA_UPDATE: Update DMA request
01285   *            @arg TIM_DMA_CC1:  Capture/Compare 1 DMA request
01286   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01287   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01288   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01289   *            @arg TIM_DMA_COM:  Commutation DMA request
01290   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01291   * @retval None
01292   */
01293 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
01294
01295 /**
01296   * @brief  Disables the specified DMA request.
01297   * @param  __HANDLE__: specifies the TIM Handle.
01298   * @param  __DMA__: specifies the TIM DMA request to disable.
01299   *          This parameter can be one of the following values:
01300   *            @arg TIM_DMA_UPDATE: Update DMA request
01301   *            @arg TIM_DMA_CC1:  Capture/Compare 1 DMA request
01302   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
01303   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
01304   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
01305   *            @arg TIM_DMA_COM:  Commutation DMA request
01306   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
01307   * @retval None
01308   */
01309 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
01310
01311 /**
01312   * @brief  Checks whether the specified TIM interrupt flag is set or not.
01313   * @param  __HANDLE__: specifies the TIM Handle.
01314   * @param  __FLAG__: specifies the TIM interrupt flag to check.
01315   *        This parameter can be one of the following values:
01316   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01317   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01318   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01319   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01320   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01321   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01322   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01323   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01324   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01325   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01326   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01327   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01328   * @retval The new state of __FLAG__ (TRUE or FALSE).
01329   */
01330 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
01331
01332 /**
01333   * @brief  Clears the specified TIM interrupt flag.
01334   * @param  __HANDLE__: specifies the TIM Handle.
01335   * @param  __FLAG__: specifies the TIM interrupt flag to clear.
01336   *        This parameter can be one of the following values:
01337   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
01338   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
01339   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
01340   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
01341   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
01342   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
01343   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
01344   *            @arg TIM_FLAG_BREAK: Break interrupt flag
01345   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
01346   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
01347   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
01348   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
01349   * @retval The new state of __FLAG__ (TRUE or FALSE).
01350   */
01351 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
01352
01353 /**
01354   * @brief  Checks whether the specified TIM interrupt has occurred or not.
01355   * @param  __HANDLE__: TIM handle
01356   * @param  __INTERRUPT__: specifies the TIM interrupt source to check.
01357   * @retval The state of TIM_IT (SET or RESET).
01358   */
01359 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
01360
01361 /**
01362   * @brief Clear the TIM interrupt pending bits
01363   * @param  __HANDLE__: TIM handle
01364   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
01365   * @retval None
01366   */
01367 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
01368
01369 /**
01370   * @brief  Indicates whether or not the TIM Counter is used as downcounter
01371   * @param  __HANDLE__: TIM handle.
01372   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
01373   * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
01374 mode.
01375   */
01376 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)            (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
01377
01378 /**
01379   * @brief  Sets the TIM active prescaler register value on update event.
01380   * @param  __HANDLE__: TIM handle.
01381   * @param  __PRESC__: specifies the active prescaler register new value.
01382   * @retval None
01383   */
01384 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
01385
01386 /**
01387   * @brief  Sets the TIM Capture Compare Register value on runtime without
01388   *         calling another time ConfigChannel function.
01389   * @param  __HANDLE__: TIM handle.
01390   * @param  __CHANNEL__ : TIM Channels to be configured.
01391   *          This parameter can be one of the following values:
01392   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01393   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01394   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01395   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01396   * @param  __COMPARE__: specifies the Capture Compare register new value.
01397   * @retval None
01398   */
01399 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
01400 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
01401
01402 /**
01403   * @brief  Gets the TIM Capture Compare Register value on runtime
01404   * @param  __HANDLE__: TIM handle.
01405   * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
01406   *          This parameter can be one of the following values:
01407   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
01408   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
01409   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
01410   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
01411   * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
01412   */
01413 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
01414   (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
01415
01416 /**
01417   * @brief  Sets the TIM Counter Register value on runtime.
01418   * @param  __HANDLE__: TIM handle.
01419   * @param  __COUNTER__: specifies the Counter register new value.
01420   * @retval None
01421   */
01422 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
01423
01424 /**
01425   * @brief  Gets the TIM Counter Register value on runtime.
01426   * @param  __HANDLE__: TIM handle.
01427   * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
01428   */
01429 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
01430    ((__HANDLE__)->Instance->CNT)
01431
01432 /**
01433   * @brief  Sets the TIM Autoreload Register value on runtime without calling
01434   *         another time any Init function.
01435   * @param  __HANDLE__: TIM handle.
01436   * @param  __AUTORELOAD__: specifies the Counter register new value.
01437   * @retval None
01438   */
01439 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
01440                         do{                                                    \
01441                               (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
01442                               (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
01443                           } while(0U)
01444
01445 /**
01446   * @brief  Gets the TIM Autoreload Register value on runtime
01447   * @param  __HANDLE__: TIM handle.
01448   * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
01449   */
01450 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
01451    ((__HANDLE__)->Instance->ARR)
01452
01453 /**
01454   * @brief  Sets the TIM Clock Division value on runtime without calling
01455   *         another time any Init function.
01456   * @param  __HANDLE__: TIM handle.
01457   * @param  __CKD__: specifies the clock division value.
01458   *          This parameter can be one of the following value:
01459   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01460   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01461   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01462   * @retval None
01463   */
01464 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
01465                         do{                                                             \
01466                               (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
01467                               (__HANDLE__)->Instance->CR1 |= (__CKD__);                 \
01468                               (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
01469                           } while(0U)
01470
01471 /**
01472   * @brief  Gets the TIM Clock Division value on runtime
01473   * @param  __HANDLE__: TIM handle.
01474   * @retval The clock division can be one of the following values:
01475   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
01476   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
01477   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
01478   */
01479 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  \
01480    ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
01481
01482 /**
01483   * @brief  Sets the TIM Input Capture prescaler on runtime without calling
01484   *         another time HAL_TIM_IC_ConfigChannel() function.
01485   * @param  __HANDLE__: TIM handle.
01486   * @param  __CHANNEL__ : TIM Channels to be configured.
01487   *          This parameter can be one of the following values:
01488   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01489   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01490   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01491   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01492   * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
01493   *          This parameter can be one of the following values:
01494   *            @arg TIM_ICPSC_DIV1: no prescaler
01495   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01496   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01497   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01498   * @retval None
01499   */
01500 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
01501                         do{                                                    \
01502                               TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
01503                               TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
01504                           } while(0U)
01505
01506 /**
01507   * @brief  Gets the TIM Input Capture prescaler on runtime
01508   * @param  __HANDLE__: TIM handle.
01509   * @param  __CHANNEL__: TIM Channels to be configured.
01510   *          This parameter can be one of the following values:
01511   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
01512   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
01513   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
01514   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
01515   * @retval The input capture prescaler can be one of the following values:
01516   *            @arg TIM_ICPSC_DIV1: no prescaler
01517   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
01518   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
01519   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
01520   */
01521 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
01522   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
01523    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
01524    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
01525    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
01526
01527 /**
01528   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register
01529   * @param  __HANDLE__: TIM handle.
01530   * @note  When the USR bit of the TIMx_CR1 register is set, only counter
01531   *        overflow/underflow generates an update interrupt or DMA request (if
01532   *        enabled)
01533   * @retval None
01534   */
01535 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
01536     ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
01537
01538 /**
01539   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register
01540   * @param  __HANDLE__: TIM handle.
01541   * @note  When the USR bit of the TIMx_CR1 register is reset, any of the
01542   *        following events generate an update interrupt or DMA request (if
01543   *        enabled):
01544   *          (+) Counter overflow/underflow
01545   *          (+) Setting the UG bit
01546   *          (+) Update generation through the slave mode controller
01547   * @retval None
01548   */
01549 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
01550       ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
01551
01552 /**
01553   * @brief  Sets the TIM Capture x input polarity on runtime.
01554   * @param  __HANDLE__: TIM handle.
01555   * @param  __CHANNEL__: TIM Channels to be configured.
01556   *          This parameter can be one of the following values:
01557   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01558   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01559   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01560   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01561   * @param  __POLARITY__: Polarity for TIx source
01562   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
01563   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
01564   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
01565   * @note  The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized  for TIM Channel 4.
01566   * @retval None
01567   */
01568 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
01569         do{                                                                     \
01570           TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
01571           TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
01572         }while(0U)
01573
01574 /**
01575   * @}
01576   */
01577
01578 /* Include TIM HAL Extension module */
01579 #include "stm32f1xx_hal_tim_ex.h"
01580
01581 /* Exported functions --------------------------------------------------------*/
01582 /** @addtogroup TIM_Exported_Functions
01583   * @{
01584   */
01585
01586 /** @addtogroup TIM_Exported_Functions_Group1
01587  * @{
01588  */
01589 /* Time Base functions ********************************************************/
01590 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
01591 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
01592 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
01593 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
01594 /* Blocking mode: Polling */
01595 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
01596 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
01597 /* Non-Blocking mode: Interrupt */
01598 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
01599 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
01600 /* Non-Blocking mode: DMA */
01601 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
01602 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
01603 /**
01604   * @}
01605   */
01606
01607 /** @addtogroup TIM_Exported_Functions_Group2
01608  * @{
01609  */
01610 /* Timer Output Compare functions **********************************************/
01611 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
01612 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
01613 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
01614 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
01615 /* Blocking mode: Polling */
01616 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01617 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01618 /* Non-Blocking mode: Interrupt */
01619 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01620 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01621 /* Non-Blocking mode: DMA */
01622 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01623 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01624
01625 /**
01626   * @}
01627   */
01628
01629 /** @addtogroup TIM_Exported_Functions_Group3
01630  * @{
01631  */
01632 /* Timer PWM functions *********************************************************/
01633 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
01634 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
01635 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
01636 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
01637 /* Blocking mode: Polling */
01638 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01639 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01640 /* Non-Blocking mode: Interrupt */
01641 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01642 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01643 /* Non-Blocking mode: DMA */
01644 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01645 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01646 /**
01647   * @}
01648   */
01649
01650 /** @addtogroup TIM_Exported_Functions_Group4
01651  * @{
01652  */
01653 /* Timer Input Capture functions ***********************************************/
01654 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
01655 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
01656 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
01657 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
01658 /* Blocking mode: Polling */
01659 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01660 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01661 /* Non-Blocking mode: Interrupt */
01662 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01663 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01664 /* Non-Blocking mode: DMA */
01665 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
01666 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01667 /**
01668   * @}
01669   */
01670
01671 /** @addtogroup TIM_Exported_Functions_Group5
01672  * @{
01673  */
01674 /* Timer One Pulse functions ***************************************************/
01675 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
01676 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
01677 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
01678 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
01679 /* Blocking mode: Polling */
01680 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01681 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01682 /* Non-Blocking mode: Interrupt */
01683 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01684 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
01685 /**
01686   * @}
01687   */
01688
01689 /** @addtogroup TIM_Exported_Functions_Group6
01690  * @{
01691  */
01692 /* Timer Encoder functions *****************************************************/
01693 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
01694 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
01695 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
01696 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
01697  /* Blocking mode: Polling */
01698 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
01699 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
01700 /* Non-Blocking mode: Interrupt */
01701 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01702 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
01703 /* Non-Blocking mode: DMA */
01704 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
01705 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
01706
01707 /**
01708   * @}
01709   */
01710
01711 /** @addtogroup TIM_Exported_Functions_Group7
01712  * @{
01713  */
01714 /* Interrupt Handler functions  **********************************************/
01715 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
01716 /**
01717   * @}
01718   */
01719
01720 /** @addtogroup TIM_Exported_Functions_Group8
01721  * @{
01722  */
01723 /* Control functions  *********************************************************/
01724 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01725 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
01726 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
01727 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
01728 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
01729 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
01730 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
01731 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01732 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
01733 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01734                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01735 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01736 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
01737                                               uint32_t  *BurstBuffer, uint32_t  BurstLength);
01738 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
01739 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
01740 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
01741
01742 /**
01743   * @}
01744   */
01745
01746 /** @addtogroup TIM_Exported_Functions_Group9
01747  * @{
01748  */
01749 /* Callback in non blocking modes (Interrupt and DMA) *************************/
01750 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
01751 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
01752 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
01753 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
01754 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
01755 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
01756 /**
01757   * @}
01758   */
01759
01760 /** @addtogroup TIM_Exported_Functions_Group10
01761  * @{
01762  */
01763 /* Peripheral State functions  **************************************************/
01764 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
01765 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
01766 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
01767 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
01768 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
01769 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
01770
01771 /**
01772   * @}
01773   */
01774
01775 /**
01776   * @}
01777   */
01778
01779 /**
01780   * @}
01781   */
01782
01783 /**
01784   * @}
01785   */
01786
01787 #ifdef __cplusplus
01788 }
01789 #endif
01790
01791 #endif /* __STM32F1xx_HAL_TIM_H */
01792
01793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_tim_ex.c Source File

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stm32f1xx_hal_tim_ex.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   TIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer Extended peripheral:
00010   *           + Time Hall Sensor Interface Initialization
00011   *           + Time Hall Sensor Interface Start
00012   *           + Time Complementary signal bread and dead time configuration
00013   *           + Time Master and Slave synchronization configuration
00014   *           + Timer remapping capabilities configuration
00015   @verbatim
00016   ==============================================================================
00017                       ##### TIMER Extended features #####
00018   ==============================================================================
00019   [..]
00020     The Timer Extended features include:
00021     (#) Complementary outputs with programmable dead-time for :
00022         (++) Output Compare
00023         (++) PWM generation (Edge and Center-aligned Mode)
00024         (++) One-pulse mode output
00025     (#) Synchronization circuit to control the timer with external signals and to
00026         interconnect several timers together.
00027     (#) Break input to put the timer output signals in reset state or in a known state.
00028     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00029         positioning purposes
00030
00031             ##### How to use this driver #####
00032   ==============================================================================
00033     [..]
00034      (#) Initialize the TIM low level resources by implementing the following functions
00035          depending from feature used :
00036            (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
00037            (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
00038            (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
00039            (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
00040
00041      (#) Initialize the TIM low level resources :
00042         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00043         (##) TIM pins configuration
00044             (+++) Enable the clock for the TIM GPIOs using the following function:
00045               __HAL_RCC_GPIOx_CLK_ENABLE();
00046             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00047
00048      (#) The external Clock can be configured, if needed (the default clock is the
00049          internal clock from the APBx), using the following function:
00050          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00051          any start function.
00052
00053      (#) Configure the TIM in the desired functioning mode using one of the
00054          initialization function of this driver:
00055           (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
00056               Timer Hall Sensor Interface and the commutation event with the corresponding
00057               Interrupt and DMA request if needed (Note that One Timer is used to interface
00058              with the Hall sensor Interface and another Timer should be used to use
00059              the commutation event).
00060
00061      (#) Activate the TIM peripheral using one of the start functions:
00062            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
00063            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
00064            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
00065            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
00066
00067
00068   @endverbatim
00069   ******************************************************************************
00070   * @attention
00071   *
00072   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00073   *
00074   * Redistribution and use in source and binary forms, with or without modification,
00075   * are permitted provided that the following conditions are met:
00076   *   1. Redistributions of source code must retain the above copyright notice,
00077   *      this list of conditions and the following disclaimer.
00078   *   2. Redistributions in binary form must reproduce the above copyright notice,
00079   *      this list of conditions and the following disclaimer in the documentation
00080   *      and/or other materials provided with the distribution.
00081   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00082   *      may be used to endorse or promote products derived from this software
00083   *      without specific prior written permission.
00084   *
00085   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00086   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00087   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00088   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00089   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00090   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00091   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00092   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00093   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00094   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00095   *
00096   ******************************************************************************
00097 */
00098
00099 /* Includes ------------------------------------------------------------------*/
00100 #include "stm32f1xx_hal.h"
00101
00102 /** @addtogroup STM32F1xx_HAL_Driver
00103   * @{
00104   */
00105
00106 /** @defgroup TIMEx TIMEx
00107   * @brief TIM Extended HAL module driver
00108   * @{
00109   */
00110
00111 #ifdef HAL_TIM_MODULE_ENABLED
00112
00113 /* Private typedef -----------------------------------------------------------*/
00114 /* Private define ------------------------------------------------------------*/
00115 /* Private macro -------------------------------------------------------------*/
00116 /* Private variables ---------------------------------------------------------*/
00117 /* Private function prototypes -----------------------------------------------*/
00118
00119 #if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
00120     defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
00121     defined (STM32F105xC) || defined (STM32F107xC)
00122 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
00123   * @{
00124   */
00125 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
00126 /**
00127   * @}
00128   */
00129 #endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
00130        /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
00131        /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
00132
00133 /* Exported functions ---------------------------------------------------------*/
00134
00135 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
00136   * @{
00137   */
00138
00139
00140 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
00141  *  @brief    Timer Hall Sensor functions
00142  *
00143 @verbatim
00144   ==============================================================================
00145                       ##### Timer Hall Sensor functions #####
00146   ==============================================================================
00147   [..]
00148     This section provides functions allowing to:
00149     (+) Initialize and configure TIM HAL Sensor.
00150     (+) De-initialize TIM HAL Sensor.
00151     (+) Start the Hall Sensor Interface.
00152     (+) Stop the Hall Sensor Interface.
00153     (+) Start the Hall Sensor Interface and enable interrupts.
00154     (+) Stop the Hall Sensor Interface and disable interrupts.
00155     (+) Start the Hall Sensor Interface and enable DMA transfers.
00156     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00157
00158 @endverbatim
00159   * @{
00160   */
00161 /**
00162   * @brief  Initializes the TIM Hall Sensor Interface and create the associated handle.
00163   * @param  htim : TIM Encoder Interface handle
00164   * @param  sConfig : TIM Hall Sensor configuration structure
00165   * @retval HAL status
00166   */
00167 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
00168 {
00169   TIM_OC_InitTypeDef OC_Config;
00170
00171   /* Check the TIM handle allocation */
00172   if(htim == NULL)
00173   {
00174     return HAL_ERROR;
00175   }
00176
00177   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00178   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00179   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00180   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
00181   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00182   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00183   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00184
00185   if(htim->State == HAL_TIM_STATE_RESET)
00186   {
00187     /* Allocate lock resource and initialize it */
00188     htim->Lock = HAL_UNLOCKED;
00189
00190     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00191     HAL_TIMEx_HallSensor_MspInit(htim);
00192   }
00193
00194   /* Set the TIM state */
00195   htim->State= HAL_TIM_STATE_BUSY;
00196
00197   /* Configure the Time base in the Encoder Mode */
00198   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00199
00200   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00201   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00202
00203   /* Reset the IC1PSC Bits */
00204   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00205   /* Set the IC1PSC value */
00206   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00207
00208   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00209   htim->Instance->CR2 |= TIM_CR2_TI1S;
00210
00211   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00212   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00213   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00214
00215   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00216   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00217   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00218
00219   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00220   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00221   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00222   OC_Config.OCMode = TIM_OCMODE_PWM2;
00223   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00224   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00225   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00226   OC_Config.Pulse = sConfig->Commutation_Delay;
00227
00228   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00229
00230   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00231     register to 101 */
00232   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00233   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00234
00235   /* Initialize the TIM state*/
00236   htim->State= HAL_TIM_STATE_READY;
00237
00238   return HAL_OK;
00239 }
00240
00241 /**
00242   * @brief  DeInitializes the TIM Hall Sensor interface
00243   * @param  htim : TIM Hall Sensor handle
00244   * @retval HAL status
00245   */
00246 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00247 {
00248   /* Check the parameters */
00249   assert_param(IS_TIM_INSTANCE(htim->Instance));
00250
00251   htim->State = HAL_TIM_STATE_BUSY;
00252
00253   /* Disable the TIM Peripheral Clock */
00254   __HAL_TIM_DISABLE(htim);
00255
00256   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00257   HAL_TIMEx_HallSensor_MspDeInit(htim);
00258
00259   /* Change TIM state */
00260   htim->State = HAL_TIM_STATE_RESET;
00261
00262   /* Release Lock */
00263   __HAL_UNLOCK(htim);
00264
00265   return HAL_OK;
00266 }
00267
00268 /**
00269   * @brief  Initializes the TIM Hall Sensor MSP.
00270   * @param  htim : TIM handle
00271   * @retval None
00272   */
00273 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00274 {
00275   /* Prevent unused argument(s) compilation warning */
00276   UNUSED(htim);
00277   /* NOTE : This function Should not be modified, when the callback is needed,
00278             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00279    */
00280 }
00281
00282 /**
00283   * @brief  DeInitializes TIM Hall Sensor MSP.
00284   * @param  htim : TIM handle
00285   * @retval None
00286   */
00287 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00288 {
00289   /* Prevent unused argument(s) compilation warning */
00290   UNUSED(htim);
00291   /* NOTE : This function Should not be modified, when the callback is needed,
00292             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00293    */
00294 }
00295
00296 /**
00297   * @brief  Starts the TIM Hall Sensor Interface.
00298   * @param  htim : TIM Hall Sensor handle
00299   * @retval HAL status
00300   */
00301 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00302 {
00303   /* Check the parameters */
00304   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00305
00306   /* Enable the Input Capture channel 1
00307     (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00308   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00309
00310   /* Enable the Peripheral */
00311   __HAL_TIM_ENABLE(htim);
00312
00313   /* Return function status */
00314   return HAL_OK;
00315 }
00316
00317 /**
00318   * @brief  Stops the TIM Hall sensor Interface.
00319   * @param  htim : TIM Hall Sensor handle
00320   * @retval HAL status
00321   */
00322 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00323 {
00324   /* Check the parameters */
00325   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00326
00327   /* Disable the Input Capture channel 1
00328     (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00329   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00330
00331   /* Disable the Peripheral */
00332   __HAL_TIM_DISABLE(htim);
00333
00334   /* Return function status */
00335   return HAL_OK;
00336 }
00337
00338 /**
00339   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00340   * @param  htim : TIM Hall Sensor handle
00341   * @retval HAL status
00342   */
00343 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00344 {
00345   /* Check the parameters */
00346   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00347
00348   /* Enable the capture compare Interrupts 1 event */
00349   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00350
00351   /* Enable the Input Capture channel 1
00352     (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00353   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00354
00355   /* Enable the Peripheral */
00356   __HAL_TIM_ENABLE(htim);
00357
00358   /* Return function status */
00359   return HAL_OK;
00360 }
00361
00362 /**
00363   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00364   * @param  htim : TIM handle
00365   * @retval HAL status
00366   */
00367 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00368 {
00369   /* Check the parameters */
00370   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00371
00372   /* Disable the Input Capture channel 1
00373     (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00374   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00375
00376   /* Disable the capture compare Interrupts event */
00377   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00378
00379   /* Disable the Peripheral */
00380   __HAL_TIM_DISABLE(htim);
00381
00382   /* Return function status */
00383   return HAL_OK;
00384 }
00385
00386 /**
00387   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00388   * @param  htim : TIM Hall Sensor handle
00389   * @param  pData : The destination Buffer address.
00390   * @param  Length : The length of data to be transferred from TIM peripheral to memory.
00391   * @retval HAL status
00392   */
00393 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00394 {
00395   /* Check the parameters */
00396   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00397
00398    if((htim->State == HAL_TIM_STATE_BUSY))
00399   {
00400      return HAL_BUSY;
00401   }
00402   else if((htim->State == HAL_TIM_STATE_READY))
00403   {
00404     if(((uint32_t)pData == 0U) && (Length > 0U))
00405     {
00406       return HAL_ERROR;
00407     }
00408     else
00409     {
00410       htim->State = HAL_TIM_STATE_BUSY;
00411     }
00412   }
00413   /* Enable the Input Capture channel 1
00414     (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00415   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00416
00417   /* Set the DMA Input Capture 1 Callback */
00418   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
00419   /* Set the DMA error callback */
00420   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00421
00422   /* Enable the DMA channel for Capture 1*/
00423   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
00424
00425   /* Enable the capture compare 1 Interrupt */
00426   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00427
00428   /* Enable the Peripheral */
00429   __HAL_TIM_ENABLE(htim);
00430
00431   /* Return function status */
00432   return HAL_OK;
00433 }
00434
00435 /**
00436   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00437   * @param  htim : TIM handle
00438   * @retval HAL status
00439   */
00440 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00441 {
00442   /* Check the parameters */
00443   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00444
00445   /* Disable the Input Capture channel 1
00446     (in the Hall Sensor Interface the 3 possible channels that are used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00447   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00448
00449
00450   /* Disable the capture compare Interrupts 1 event */
00451   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00452
00453   /* Disable the Peripheral */
00454   __HAL_TIM_DISABLE(htim);
00455
00456   /* Return function status */
00457   return HAL_OK;
00458 }
00459
00460 /**
00461   * @}
00462   */
00463
00464 #if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
00465     defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
00466     defined (STM32F105xC) || defined (STM32F107xC)
00467
00468 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
00469  *  @brief    Timer Complementary Output Compare functions
00470  *
00471 @verbatim
00472   ==============================================================================
00473               ##### Timer Complementary Output Compare functions #####
00474   ==============================================================================
00475   [..]
00476     This section provides functions allowing to:
00477     (+) Start the Complementary Output Compare/PWM.
00478     (+) Stop the Complementary Output Compare/PWM.
00479     (+) Start the Complementary Output Compare/PWM and enable interrupts.
00480     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
00481     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
00482     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
00483
00484 @endverbatim
00485   * @{
00486   */
00487
00488 /**
00489   * @brief  Starts the TIM Output Compare signal generation on the complementary
00490   *         output.
00491   * @param  htim : TIM Output Compare handle
00492   * @param  Channel : TIM Channel to be enabled
00493   *          This parameter can be one of the following values:
00494   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00495   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00496   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00497   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00498   * @retval HAL status
00499   */
00500 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00501 {
00502   /* Check the parameters */
00503   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00504
00505   /* Enable the Capture compare channel N */
00506   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00507
00508   /* Enable the Main Ouput */
00509   __HAL_TIM_MOE_ENABLE(htim);
00510
00511   /* Enable the Peripheral */
00512   __HAL_TIM_ENABLE(htim);
00513
00514   /* Return function status */
00515   return HAL_OK;
00516 }
00517
00518 /**
00519   * @brief  Stops the TIM Output Compare signal generation on the complementary
00520   *         output.
00521   * @param  htim : TIM handle
00522   * @param  Channel : TIM Channel to be disabled
00523   *          This parameter can be one of the following values:
00524   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00525   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00526   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00527   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00528   * @retval HAL status
00529   */
00530 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00531 {
00532   /* Check the parameters */
00533   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00534
00535   /* Disable the Capture compare channel N */
00536   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00537
00538   /* Disable the Main Ouput */
00539   __HAL_TIM_MOE_DISABLE(htim);
00540
00541   /* Disable the Peripheral */
00542   __HAL_TIM_DISABLE(htim);
00543
00544   /* Return function status */
00545   return HAL_OK;
00546 }
00547
00548 /**
00549   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00550   *         on the complementary output.
00551   * @param  htim : TIM OC handle
00552   * @param  Channel : TIM Channel to be enabled
00553   *          This parameter can be one of the following values:
00554   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00555   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00556   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00557   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00558   * @retval HAL status
00559   */
00560 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00561 {
00562   /* Check the parameters */
00563   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00564
00565   switch (Channel)
00566   {
00567     case TIM_CHANNEL_1:
00568     {
00569       /* Enable the TIM Output Compare interrupt */
00570       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00571     }
00572     break;
00573
00574     case TIM_CHANNEL_2:
00575     {
00576       /* Enable the TIM Output Compare interrupt */
00577       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00578     }
00579     break;
00580
00581     case TIM_CHANNEL_3:
00582     {
00583       /* Enable the TIM Output Compare interrupt */
00584       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00585     }
00586     break;
00587
00588     case TIM_CHANNEL_4:
00589     {
00590       /* Enable the TIM Output Compare interrupt */
00591       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00592     }
00593     break;
00594
00595     default:
00596     break;
00597   }
00598
00599   /* Enable the TIM Break interrupt */
00600   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00601
00602   /* Enable the Capture compare channel N */
00603   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00604
00605   /* Enable the Main Ouput */
00606   __HAL_TIM_MOE_ENABLE(htim);
00607
00608   /* Enable the Peripheral */
00609   __HAL_TIM_ENABLE(htim);
00610
00611   /* Return function status */
00612   return HAL_OK;
00613 }
00614
00615 /**
00616   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00617   *         on the complementary output.
00618   * @param  htim : TIM Output Compare handle
00619   * @param  Channel : TIM Channel to be disabled
00620   *          This parameter can be one of the following values:
00621   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00622   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00623   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00624   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00625   * @retval HAL status
00626   */
00627 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00628 {
00629   uint32_t tmpccer = 0U;
00630
00631   /* Check the parameters */
00632   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00633
00634   switch (Channel)
00635   {
00636     case TIM_CHANNEL_1:
00637     {
00638       /* Disable the TIM Output Compare interrupt */
00639       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00640     }
00641     break;
00642
00643     case TIM_CHANNEL_2:
00644     {
00645       /* Disable the TIM Output Compare interrupt */
00646       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00647     }
00648     break;
00649
00650     case TIM_CHANNEL_3:
00651     {
00652       /* Disable the TIM Output Compare interrupt */
00653       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00654     }
00655     break;
00656
00657     case TIM_CHANNEL_4:
00658     {
00659       /* Disable the TIM Output Compare interrupt */
00660       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00661     }
00662     break;
00663
00664     default:
00665     break;
00666   }
00667
00668   /* Disable the Capture compare channel N */
00669   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00670
00671   /* Disable the TIM Break interrupt (only if no more channel is active) */
00672   tmpccer = htim->Instance->CCER;
00673   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
00674   {
00675     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00676   }
00677
00678   /* Disable the Main Ouput */
00679   __HAL_TIM_MOE_DISABLE(htim);
00680
00681   /* Disable the Peripheral */
00682   __HAL_TIM_DISABLE(htim);
00683
00684   /* Return function status */
00685   return HAL_OK;
00686 }
00687
00688 /**
00689   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00690   *         on the complementary output.
00691   * @param  htim : TIM Output Compare handle
00692   * @param  Channel : TIM Channel to be enabled
00693   *          This parameter can be one of the following values:
00694   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00695   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00696   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00697   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00698   * @param  pData : The source Buffer address.
00699   * @param  Length : The length of data to be transferred from memory to TIM peripheral
00700   * @retval HAL status
00701   */
00702 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00703 {
00704   /* Check the parameters */
00705   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00706
00707   if((htim->State == HAL_TIM_STATE_BUSY))
00708   {
00709      return HAL_BUSY;
00710   }
00711   else if((htim->State == HAL_TIM_STATE_READY))
00712   {
00713     if(((uint32_t)pData == 0U) && (Length > 0U))
00714     {
00715       return HAL_ERROR;
00716     }
00717     else
00718     {
00719       htim->State = HAL_TIM_STATE_BUSY;
00720     }
00721   }
00722   switch (Channel)
00723   {
00724     case TIM_CHANNEL_1:
00725     {
00726       /* Set the DMA Period elapsed callback */
00727       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00728
00729       /* Set the DMA error callback */
00730       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00731
00732       /* Enable the DMA channel */
00733       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00734
00735       /* Enable the TIM Output Compare DMA request */
00736       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00737     }
00738     break;
00739
00740     case TIM_CHANNEL_2:
00741     {
00742       /* Set the DMA Period elapsed callback */
00743       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00744
00745       /* Set the DMA error callback */
00746       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00747
00748       /* Enable the DMA channel */
00749       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00750
00751       /* Enable the TIM Output Compare DMA request */
00752       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00753     }
00754     break;
00755
00756     case TIM_CHANNEL_3:
00757 {
00758       /* Set the DMA Period elapsed callback */
00759       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00760
00761       /* Set the DMA error callback */
00762       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00763
00764       /* Enable the DMA channel */
00765       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00766
00767       /* Enable the TIM Output Compare DMA request */
00768       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00769     }
00770     break;
00771
00772     case TIM_CHANNEL_4:
00773     {
00774      /* Set the DMA Period elapsed callback */
00775       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
00776
00777       /* Set the DMA error callback */
00778       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
00779
00780       /* Enable the DMA channel */
00781       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00782
00783       /* Enable the TIM Output Compare DMA request */
00784       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00785     }
00786     break;
00787
00788     default:
00789     break;
00790   }
00791
00792   /* Enable the Capture compare channel N */
00793   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00794
00795   /* Enable the Main Ouput */
00796   __HAL_TIM_MOE_ENABLE(htim);
00797
00798   /* Enable the Peripheral */
00799   __HAL_TIM_ENABLE(htim);
00800
00801   /* Return function status */
00802   return HAL_OK;
00803 }
00804
00805 /**
00806   * @brief  Stops the TIM Output Compare signal generation in DMA mode
00807   *         on the complementary output.
00808   * @param  htim : TIM Output Compare handle
00809   * @param  Channel : TIM Channel to be disabled
00810   *          This parameter can be one of the following values:
00811   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00812   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00813   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00814   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00815   * @retval HAL status
00816   */
00817 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00818 {
00819   /* Check the parameters */
00820   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00821
00822   switch (Channel)
00823   {
00824     case TIM_CHANNEL_1:
00825     {
00826       /* Disable the TIM Output Compare DMA request */
00827       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00828     }
00829     break;
00830
00831     case TIM_CHANNEL_2:
00832     {
00833       /* Disable the TIM Output Compare DMA request */
00834       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00835     }
00836     break;
00837
00838     case TIM_CHANNEL_3:
00839     {
00840       /* Disable the TIM Output Compare DMA request */
00841       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00842     }
00843     break;
00844
00845     case TIM_CHANNEL_4:
00846     {
00847       /* Disable the TIM Output Compare interrupt */
00848       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00849     }
00850     break;
00851
00852     default:
00853     break;
00854   }
00855
00856   /* Disable the Capture compare channel N */
00857   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00858
00859   /* Disable the Main Ouput */
00860   __HAL_TIM_MOE_DISABLE(htim);
00861
00862   /* Disable the Peripheral */
00863   __HAL_TIM_DISABLE(htim);
00864
00865   /* Change the htim state */
00866   htim->State = HAL_TIM_STATE_READY;
00867
00868   /* Return function status */
00869   return HAL_OK;
00870 }
00871
00872 /**
00873   * @}
00874   */
00875
00876 /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
00877  *  @brief    Timer Complementary PWM functions
00878  *
00879 @verbatim
00880   ==============================================================================
00881                  ##### Timer Complementary PWM functions #####
00882   ==============================================================================
00883   [..]
00884     This section provides functions allowing to:
00885     (+) Start the Complementary PWM.
00886     (+) Stop the Complementary PWM.
00887     (+) Start the Complementary PWM and enable interrupts.
00888     (+) Stop the Complementary PWM and disable interrupts.
00889     (+) Start the Complementary PWM and enable DMA transfers.
00890     (+) Stop the Complementary PWM and disable DMA transfers.
00891     (+) Start the Complementary Input Capture measurement.
00892     (+) Stop the Complementary Input Capture.
00893     (+) Start the Complementary Input Capture and enable interrupts.
00894     (+) Stop the Complementary Input Capture and disable interrupts.
00895     (+) Start the Complementary Input Capture and enable DMA transfers.
00896     (+) Stop the Complementary Input Capture and disable DMA transfers.
00897     (+) Start the Complementary One Pulse generation.
00898     (+) Stop the Complementary One Pulse.
00899     (+) Start the Complementary One Pulse and enable interrupts.
00900     (+) Stop the Complementary One Pulse and disable interrupts.
00901
00902 @endverbatim
00903   * @{
00904   */
00905
00906 /**
00907   * @brief  Starts the PWM signal generation on the complementary output.
00908   * @param  htim : TIM handle
00909   * @param  Channel : TIM Channel to be enabled
00910   *          This parameter can be one of the following values:
00911   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00912   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00913   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00914   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00915   * @retval HAL status
00916   */
00917 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00918 {
00919   /* Check the parameters */
00920   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00921
00922   /* Enable the complementary PWM output  */
00923   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00924
00925   /* Enable the Main Ouput */
00926   __HAL_TIM_MOE_ENABLE(htim);
00927
00928   /* Enable the Peripheral */
00929   __HAL_TIM_ENABLE(htim);
00930
00931   /* Return function status */
00932   return HAL_OK;
00933 }
00934
00935 /**
00936   * @brief  Stops the PWM signal generation on the complementary output.
00937   * @param  htim : TIM handle
00938   * @param  Channel : TIM Channel to be disabled
00939   *          This parameter can be one of the following values:
00940   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00941   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00942   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00943   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00944   * @retval HAL status
00945   */
00946 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00947 {
00948   /* Check the parameters */
00949   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00950
00951   /* Disable the complementary PWM output  */
00952   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00953
00954   /* Disable the Main Ouput */
00955   __HAL_TIM_MOE_DISABLE(htim);
00956
00957   /* Disable the Peripheral */
00958   __HAL_TIM_DISABLE(htim);
00959
00960   /* Return function status */
00961   return HAL_OK;
00962 }
00963
00964 /**
00965   * @brief  Starts the PWM signal generation in interrupt mode on the
00966   *         complementary output.
00967   * @param  htim : TIM handle
00968   * @param  Channel : TIM Channel to be disabled
00969   *          This parameter can be one of the following values:
00970   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00971   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00972   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00973   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00974   * @retval HAL status
00975   */
00976 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00977 {
00978   /* Check the parameters */
00979   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00980
00981   switch (Channel)
00982   {
00983     case TIM_CHANNEL_1:
00984     {
00985       /* Enable the TIM Capture/Compare 1 interrupt */
00986       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00987     }
00988     break;
00989
00990     case TIM_CHANNEL_2:
00991     {
00992       /* Enable the TIM Capture/Compare 2 interrupt */
00993       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00994     }
00995     break;
00996
00997     case TIM_CHANNEL_3:
00998     {
00999       /* Enable the TIM Capture/Compare 3 interrupt */
01000       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
01001     }
01002     break;
01003
01004     case TIM_CHANNEL_4:
01005     {
01006       /* Enable the TIM Capture/Compare 4 interrupt */
01007       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
01008     }
01009     break;
01010
01011     default:
01012     break;
01013   }
01014
01015   /* Enable the TIM Break interrupt */
01016   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
01017
01018   /* Enable the complementary PWM output  */
01019   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01020
01021   /* Enable the Main Ouput */
01022   __HAL_TIM_MOE_ENABLE(htim);
01023
01024   /* Enable the Peripheral */
01025   __HAL_TIM_ENABLE(htim);
01026
01027   /* Return function status */
01028   return HAL_OK;
01029 }
01030
01031 /**
01032   * @brief  Stops the PWM signal generation in interrupt mode on the
01033   *         complementary output.
01034   * @param  htim : TIM handle
01035   * @param  Channel : TIM Channel to be disabled
01036   *          This parameter can be one of the following values:
01037   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01038   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01039   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01040   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01041   * @retval HAL status
01042   */
01043 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01044 {
01045   uint32_t tmpccer = 0U;
01046
01047   /* Check the parameters */
01048   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01049
01050   switch (Channel)
01051   {
01052     case TIM_CHANNEL_1:
01053     {
01054       /* Disable the TIM Capture/Compare 1 interrupt */
01055       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01056     }
01057     break;
01058
01059     case TIM_CHANNEL_2:
01060     {
01061       /* Disable the TIM Capture/Compare 2 interrupt */
01062       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01063     }
01064     break;
01065
01066     case TIM_CHANNEL_3:
01067     {
01068       /* Disable the TIM Capture/Compare 3 interrupt */
01069       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01070     }
01071     break;
01072
01073     case TIM_CHANNEL_4:
01074     {
01075       /* Disable the TIM Capture/Compare 3 interrupt */
01076       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01077     }
01078     break;
01079
01080     default:
01081     break;
01082   }
01083
01084   /* Disable the complementary PWM output  */
01085   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01086
01087   /* Disable the TIM Break interrupt (only if no more channel is active) */
01088   tmpccer = htim->Instance->CCER;
01089   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
01090   {
01091     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01092   }
01093
01094   /* Disable the Main Ouput */
01095   __HAL_TIM_MOE_DISABLE(htim);
01096
01097   /* Disable the Peripheral */
01098   __HAL_TIM_DISABLE(htim);
01099
01100   /* Return function status */
01101   return HAL_OK;
01102 }
01103
01104 /**
01105   * @brief  Starts the TIM PWM signal generation in DMA mode on the
01106   *         complementary output
01107   * @param  htim : TIM handle
01108   * @param  Channel : TIM Channel to be enabled
01109   *          This parameter can be one of the following values:
01110   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01111   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01112   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01113   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01114   * @param  pData : The source Buffer address.
01115   * @param  Length : The length of data to be transferred from memory to TIM peripheral
01116   * @retval HAL status
01117   */
01118 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01119 {
01120   /* Check the parameters */
01121   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01122
01123   if((htim->State == HAL_TIM_STATE_BUSY))
01124   {
01125      return HAL_BUSY;
01126   }
01127   else if((htim->State == HAL_TIM_STATE_READY))
01128   {
01129     if(((uint32_t)pData == 0U) && (Length > 0U))
01130     {
01131       return HAL_ERROR;
01132     }
01133     else
01134     {
01135       htim->State = HAL_TIM_STATE_BUSY;
01136     }
01137   }
01138   switch (Channel)
01139   {
01140     case TIM_CHANNEL_1:
01141     {
01142       /* Set the DMA Period elapsed callback */
01143       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01144
01145       /* Set the DMA error callback */
01146       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01147
01148       /* Enable the DMA channel */
01149       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01150
01151       /* Enable the TIM Capture/Compare 1 DMA request */
01152       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01153     }
01154     break;
01155
01156     case TIM_CHANNEL_2:
01157     {
01158       /* Set the DMA Period elapsed callback */
01159       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01160
01161       /* Set the DMA error callback */
01162       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01163
01164       /* Enable the DMA channel */
01165       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01166
01167       /* Enable the TIM Capture/Compare 2 DMA request */
01168       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01169     }
01170     break;
01171
01172     case TIM_CHANNEL_3:
01173     {
01174       /* Set the DMA Period elapsed callback */
01175       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01176
01177       /* Set the DMA error callback */
01178       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01179
01180       /* Enable the DMA channel */
01181       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01182
01183       /* Enable the TIM Capture/Compare 3 DMA request */
01184       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01185     }
01186     break;
01187
01188     case TIM_CHANNEL_4:
01189     {
01190      /* Set the DMA Period elapsed callback */
01191       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01192
01193       /* Set the DMA error callback */
01194       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01195
01196       /* Enable the DMA channel */
01197       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01198
01199       /* Enable the TIM Capture/Compare 4 DMA request */
01200       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01201     }
01202     break;
01203
01204     default:
01205     break;
01206   }
01207
01208   /* Enable the complementary PWM output  */
01209      TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01210
01211   /* Enable the Main Ouput */
01212     __HAL_TIM_MOE_ENABLE(htim);
01213
01214   /* Enable the Peripheral */
01215   __HAL_TIM_ENABLE(htim);
01216
01217   /* Return function status */
01218   return HAL_OK;
01219 }
01220
01221 /**
01222   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01223   *         output
01224   * @param  htim : TIM handle
01225   * @param  Channel : TIM Channel to be disabled
01226   *          This parameter can be one of the following values:
01227   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01228   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01229   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01230   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01231   * @retval HAL status
01232   */
01233 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01234 {
01235   /* Check the parameters */
01236   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01237
01238   switch (Channel)
01239   {
01240     case TIM_CHANNEL_1:
01241     {
01242       /* Disable the TIM Capture/Compare 1 DMA request */
01243       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01244     }
01245     break;
01246
01247     case TIM_CHANNEL_2:
01248     {
01249       /* Disable the TIM Capture/Compare 2 DMA request */
01250       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01251     }
01252     break;
01253
01254     case TIM_CHANNEL_3:
01255     {
01256       /* Disable the TIM Capture/Compare 3 DMA request */
01257       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01258     }
01259     break;
01260
01261     case TIM_CHANNEL_4:
01262     {
01263       /* Disable the TIM Capture/Compare 4 DMA request */
01264       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01265     }
01266     break;
01267
01268     default:
01269     break;
01270   }
01271
01272   /* Disable the complementary PWM output */
01273     TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01274
01275   /* Disable the Main Ouput */
01276     __HAL_TIM_MOE_DISABLE(htim);
01277
01278   /* Disable the Peripheral */
01279   __HAL_TIM_DISABLE(htim);
01280
01281   /* Change the htim state */
01282   htim->State = HAL_TIM_STATE_READY;
01283
01284   /* Return function status */
01285   return HAL_OK;
01286 }
01287
01288 /**
01289   * @}
01290   */
01291
01292 /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
01293  *  @brief    Timer Complementary One Pulse functions
01294  *
01295 @verbatim
01296   ==============================================================================
01297                 ##### Timer Complementary One Pulse functions #####
01298   ==============================================================================
01299   [..]
01300     This section provides functions allowing to:
01301     (+) Start the Complementary One Pulse generation.
01302     (+) Stop the Complementary One Pulse.
01303     (+) Start the Complementary One Pulse and enable interrupts.
01304     (+) Stop the Complementary One Pulse and disable interrupts.
01305
01306 @endverbatim
01307   * @{
01308   */
01309
01310 /**
01311   * @brief  Starts the TIM One Pulse signal generation on the complemetary
01312   *         output.
01313   * @param  htim : TIM One Pulse handle
01314   * @param  OutputChannel : TIM Channel to be enabled
01315   *          This parameter can be one of the following values:
01316   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01317   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01318   * @retval HAL status
01319   */
01320 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01321   {
01322   /* Check the parameters */
01323   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01324
01325   /* Enable the complementary One Pulse output */
01326   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01327
01328   /* Enable the Main Ouput */
01329   __HAL_TIM_MOE_ENABLE(htim);
01330
01331   /* Return function status */
01332   return HAL_OK;
01333 }
01334
01335 /**
01336   * @brief  Stops the TIM One Pulse signal generation on the complementary
01337   *         output.
01338   * @param  htim : TIM One Pulse handle
01339   * @param  OutputChannel : TIM Channel to be disabled
01340   *          This parameter can be one of the following values:
01341   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01342   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01343   * @retval HAL status
01344   */
01345 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01346 {
01347
01348   /* Check the parameters */
01349   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01350
01351   /* Disable the complementary One Pulse output */
01352   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01353
01354   /* Disable the Main Ouput */
01355   __HAL_TIM_MOE_DISABLE(htim);
01356
01357   /* Disable the Peripheral */
01358   __HAL_TIM_DISABLE(htim);
01359
01360   /* Return function status */
01361   return HAL_OK;
01362 }
01363
01364 /**
01365   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01366   *         complementary channel.
01367   * @param  htim : TIM One Pulse handle
01368   * @param  OutputChannel : TIM Channel to be enabled
01369   *          This parameter can be one of the following values:
01370   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01371   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01372   * @retval HAL status
01373   */
01374 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01375 {
01376   /* Check the parameters */
01377   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01378
01379   /* Enable the TIM Capture/Compare 1 interrupt */
01380   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01381
01382   /* Enable the TIM Capture/Compare 2 interrupt */
01383   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01384
01385   /* Enable the complementary One Pulse output */
01386   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01387
01388   /* Enable the Main Ouput */
01389   __HAL_TIM_MOE_ENABLE(htim);
01390
01391   /* Return function status */
01392   return HAL_OK;
01393   }
01394
01395 /**
01396   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01397   *         complementary channel.
01398   * @param  htim : TIM One Pulse handle
01399   * @param  OutputChannel : TIM Channel to be disabled
01400   *          This parameter can be one of the following values:
01401   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01402   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01403   * @retval HAL status
01404   */
01405 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01406 {
01407   /* Check the parameters */
01408   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01409
01410   /* Disable the TIM Capture/Compare 1 interrupt */
01411   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01412
01413   /* Disable the TIM Capture/Compare 2 interrupt */
01414   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01415
01416   /* Disable the complementary One Pulse output */
01417   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01418
01419   /* Disable the Main Ouput */
01420   __HAL_TIM_MOE_DISABLE(htim);
01421
01422   /* Disable the Peripheral */
01423    __HAL_TIM_DISABLE(htim);
01424
01425   /* Return function status */
01426   return HAL_OK;
01427 }
01428
01429 /**
01430   * @}
01431   */
01432
01433 #endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
01434        /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
01435        /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
01436
01437 /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
01438  *  @brief      Peripheral Control functions
01439  *
01440 @verbatim
01441   ==============================================================================
01442                     ##### Peripheral Control functions #####
01443   ==============================================================================
01444   [..]
01445     This section provides functions allowing to:
01446     (+) Configure the commutation event in case of use of the Hall sensor interface.
01447       (+) Configure Complementary channels, break features and dead time.
01448       (+) Configure Master synchronization.
01449
01450 @endverbatim
01451   * @{
01452   */
01453
01454 #if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
01455     defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
01456     defined (STM32F105xC) || defined (STM32F107xC)
01457
01458 /**
01459   * @brief  Configure the TIM commutation event sequence.
01460   * @note: this function is mandatory to use the commutation event in order to
01461   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01462   *        the typical use of this feature is with the use of another Timer(interface Timer)
01463   *        configured in Hall sensor interface, this interface Timer will generate the
01464   *        commutation at its TRGO output (connected to Timer used in this function) each time
01465   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01466   * @param  htim : TIM handle
01467   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01468   *          This parameter can be one of the following values:
01469   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01470   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01471   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01472   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01473   *            @arg TIM_TS_NONE: No trigger is needed
01474   * @param  CommutationSource : the Commutation Event source
01475   *          This parameter can be one of the following values:
01476   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01477   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01478   * @retval HAL status
01479   */
01480 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01481 {
01482   /* Check the parameters */
01483   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01484   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01485
01486   __HAL_LOCK(htim);
01487
01488   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01489       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01490   {
01491     /* Select the Input trigger */
01492     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01493     htim->Instance->SMCR |= InputTrigger;
01494   }
01495
01496   /* Select the Capture Compare preload feature */
01497   htim->Instance->CR2 |= TIM_CR2_CCPC;
01498   /* Select the Commutation event source */
01499   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01500   htim->Instance->CR2 |= CommutationSource;
01501
01502   __HAL_UNLOCK(htim);
01503
01504   return HAL_OK;
01505 }
01506
01507 /**
01508   * @brief  Configure the TIM commutation event sequence with interrupt.
01509   * @note: this function is mandatory to use the commutation event in order to
01510   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01511   *        the typical use of this feature is with the use of another Timer(interface Timer)
01512   *        configured in Hall sensor interface, this interface Timer will generate the
01513   *        commutation at its TRGO output (connected to Timer used in this function) each time
01514   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01515   * @param  htim : TIM handle
01516   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01517   *          This parameter can be one of the following values:
01518   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01519   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01520   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01521   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01522   *            @arg TIM_TS_NONE: No trigger is needed
01523   * @param  CommutationSource : the Commutation Event source
01524   *          This parameter can be one of the following values:
01525   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01526   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01527   * @retval HAL status
01528   */
01529 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01530 {
01531   /* Check the parameters */
01532   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01533   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01534
01535   __HAL_LOCK(htim);
01536
01537   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01538       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01539   {
01540     /* Select the Input trigger */
01541     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01542     htim->Instance->SMCR |= InputTrigger;
01543   }
01544
01545   /* Select the Capture Compare preload feature */
01546   htim->Instance->CR2 |= TIM_CR2_CCPC;
01547   /* Select the Commutation event source */
01548   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01549   htim->Instance->CR2 |= CommutationSource;
01550
01551   /* Enable the Commutation Interrupt Request */
01552   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
01553
01554   __HAL_UNLOCK(htim);
01555
01556   return HAL_OK;
01557 }
01558
01559 /**
01560   * @brief  Configure the TIM commutation event sequence with DMA.
01561   * @note: this function is mandatory to use the commutation event in order to
01562   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01563   *        the typical use of this feature is with the use of another Timer(interface Timer)
01564   *        configured in Hall sensor interface, this interface Timer will generate the
01565   *        commutation at its TRGO output (connected to Timer used in this function) each time
01566   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01567   * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
01568   * @param  htim : TIM handle
01569   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01570   *          This parameter can be one of the following values:
01571   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01572   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01573   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01574   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01575   *            @arg TIM_TS_NONE: No trigger is needed
01576   * @param  CommutationSource : the Commutation Event source
01577   *          This parameter can be one of the following values:
01578   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01579   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01580   * @retval HAL status
01581   */
01582 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01583 {
01584   /* Check the parameters */
01585   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01586   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01587
01588   __HAL_LOCK(htim);
01589
01590   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01591       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01592   {
01593     /* Select the Input trigger */
01594     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01595     htim->Instance->SMCR |= InputTrigger;
01596   }
01597
01598   /* Select the Capture Compare preload feature */
01599   htim->Instance->CR2 |= TIM_CR2_CCPC;
01600   /* Select the Commutation event source */
01601   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01602   htim->Instance->CR2 |= CommutationSource;
01603
01604   /* Enable the Commutation DMA Request */
01605   /* Set the DMA Commutation Callback */
01606   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
01607   /* Set the DMA error callback */
01608   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
01609
01610   /* Enable the Commutation DMA Request */
01611   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
01612
01613   __HAL_UNLOCK(htim);
01614
01615   return HAL_OK;
01616 }
01617
01618 /**
01619   * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
01620   *          and the AOE(automatic output enable).
01621   * @param  htim : TIM handle
01622   * @param  sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
01623   *         contains the BDTR Register configuration  information for the TIM peripheral.
01624   * @retval HAL status
01625   */
01626 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
01627                                                 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
01628 {
01629   uint32_t tmpbdtr = 0U;
01630
01631   /* Check the parameters */
01632   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01633   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
01634   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
01635   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
01636   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
01637   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
01638   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
01639   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
01640
01641   /* Process Locked */
01642   __HAL_LOCK(htim);
01643
01644   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
01645      the OSSI State, the dead time value and the Automatic Output Enable Bit */
01646
01647   /* Set the BDTR bits */
01648   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
01649   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
01650   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
01651   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
01652   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
01653   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
01654   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
01655   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
01656
01657   /* Set TIMx_BDTR */
01658   htim->Instance->BDTR = tmpbdtr;
01659
01660   __HAL_UNLOCK(htim);
01661
01662   return HAL_OK;
01663 }
01664
01665 #endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
01666        /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
01667        /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
01668
01669 /**
01670   * @brief  Configures the TIM in master mode.
01671   * @param  htim : TIM handle.
01672   * @param  sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
01673   *         contains the selected trigger output (TRGO) and the Master/Slave
01674   *         mode.
01675   * @retval HAL status
01676   */
01677 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
01678 {
01679   /* Check the parameters */
01680   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
01681   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
01682   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
01683
01684   __HAL_LOCK(htim);
01685
01686   htim->State = HAL_TIM_STATE_BUSY;
01687
01688   /* Reset the MMS Bits */
01689   htim->Instance->CR2 &= ~TIM_CR2_MMS;
01690   /* Select the TRGO source */
01691   htim->Instance->CR2 |=  sMasterConfig->MasterOutputTrigger;
01692
01693   /* Reset the MSM Bit */
01694   htim->Instance->SMCR &= ~TIM_SMCR_MSM;
01695   /* Set or Reset the MSM Bit */
01696   htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
01697
01698   htim->State = HAL_TIM_STATE_READY;
01699
01700   __HAL_UNLOCK(htim);
01701
01702   return HAL_OK;
01703 }
01704
01705 /**
01706   * @}
01707   */
01708
01709 /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
01710  *  @brief   Extension Callbacks functions
01711  *
01712 @verbatim
01713   ==============================================================================
01714                     ##### Extension Callbacks functions #####
01715   ==============================================================================
01716   [..]
01717     This section provides Extension TIM callback functions:
01718     (+) Timer Commutation callback
01719     (+) Timer Break callback
01720
01721 @endverbatim
01722   * @{
01723   */
01724
01725 /**
01726   * @brief  Hall commutation changed callback in non blocking mode
01727   * @param  htim : TIM handle
01728   * @retval None
01729   */
01730 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
01731 {
01732   /* Prevent unused argument(s) compilation warning */
01733   UNUSED(htim);
01734   /* NOTE : This function Should not be modified, when the callback is needed,
01735             the HAL_TIMEx_CommutationCallback could be implemented in the user file
01736    */
01737 }
01738
01739 /**
01740   * @brief  Hall Break detection callback in non blocking mode
01741   * @param  htim : TIM handle
01742   * @retval None
01743   */
01744 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
01745 {
01746   /* Prevent unused argument(s) compilation warning */
01747   UNUSED(htim);
01748   /* NOTE : This function Should not be modified, when the callback is needed,
01749             the HAL_TIMEx_BreakCallback could be implemented in the user file
01750    */
01751 }
01752
01753 /**
01754   * @brief  TIM DMA Commutation callback.
01755   * @param  hdma : pointer to DMA handle.
01756   * @retval None
01757   */
01758 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
01759 {
01760   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01761
01762   htim->State= HAL_TIM_STATE_READY;
01763
01764   HAL_TIMEx_CommutationCallback(htim);
01765 }
01766
01767 /**
01768   * @}
01769   */
01770
01771 #if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
01772     defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
01773     defined (STM32F105xC) || defined (STM32F107xC)
01774
01775 /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
01776  *  @brief   Extension Peripheral State functions
01777  *
01778 @verbatim
01779   ==============================================================================
01780                 ##### Extension Peripheral State functions #####
01781   ==============================================================================
01782   [..]
01783     This subsection permit to get in run-time the status of the peripheral
01784     and the data flow.
01785
01786 @endverbatim
01787   * @{
01788   */
01789
01790 /**
01791   * @brief  Return the TIM Hall Sensor interface state
01792   * @param  htim : TIM Hall Sensor handle
01793   * @retval HAL state
01794   */
01795 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
01796 {
01797   return htim->State;
01798 }
01799
01800 /**
01801   * @}
01802   */
01803 #endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
01804        /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
01805        /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
01806
01807 /**
01808   * @}
01809   */
01810
01811 #if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
01812     defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
01813     defined (STM32F105xC) || defined (STM32F107xC)
01814
01815 /** @addtogroup TIMEx_Private_Functions
01816   * @{
01817   */
01818
01819 /**
01820   * @brief  Enables or disables the TIM Capture Compare Channel xN.
01821   * @param  TIMx  to select the TIM peripheral
01822   * @param  Channel : specifies the TIM Channel
01823   *          This parameter can be one of the following values:
01824   *            @arg TIM_Channel_1: TIM Channel 1
01825   *            @arg TIM_Channel_2: TIM Channel 2
01826   *            @arg TIM_Channel_3: TIM Channel 3
01827   * @param  ChannelNState : specifies the TIM Channel CCxNE bit new state.
01828   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
01829   * @retval None
01830   */
01831 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
01832 {
01833   uint32_t tmp = 0U;
01834
01835   tmp = TIM_CCER_CC1NE << Channel;
01836
01837   /* Reset the CCxNE Bit */
01838   TIMx->CCER &=  ~tmp;
01839
01840   /* Set or reset the CCxNE Bit */
01841   TIMx->CCER |=  (uint32_t)(ChannelNState << Channel);
01842 }
01843
01844 /**
01845   * @}
01846   */
01847
01848 #endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
01849        /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
01850        /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
01851
01852 #endif /* HAL_TIM_MODULE_ENABLED */
01853 /**
01854   * @}
01855   */
01856
01857 /**
01858   * @}
01859   */
01860
01861 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_tim_ex.h Source File

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stm32f1xx_hal_tim_ex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_tim_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of TIM HAL Extension module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_TIM_EX_H
00040 #define __STM32F1xx_HAL_TIM_EX_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup TIMEx
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup TIMEx_Exported_Types TIMEx Exported Types
00059   * @{
00060   */
00061
00062
00063 /**
00064   * @brief  TIM Hall sensor Configuration Structure definition
00065   */
00066
00067 typedef struct
00068 {
00069
00070   uint32_t IC1Polarity;            /*!< Specifies the active edge of the input signal.
00071                                         This parameter can be a value of @ref TIM_Input_Capture_Polarity */
00072
00073   uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
00074                                      This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
00075
00076   uint32_t IC1Filter;           /*!< Specifies the input capture filter.
00077                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
00078   uint32_t Commutation_Delay;  /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
00079                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
00080 } TIM_HallSensor_InitTypeDef;
00081
00082
00083 #if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
00084     defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
00085     defined (STM32F105xC) || defined (STM32F107xC)
00086
00087 /**
00088   * @brief  TIM Break and Dead time configuration Structure definition
00089   */
00090 typedef struct
00091 {
00092   uint32_t OffStateRunMode;       /*!< TIM off state in run mode
00093                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
00094   uint32_t OffStateIDLEMode;      /*!< TIM off state in IDLE mode
00095                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
00096   uint32_t LockLevel;             /*!< TIM Lock level
00097                                      This parameter can be a value of @ref TIM_Lock_level */
00098   uint32_t DeadTime;              /*!< TIM dead Time
00099                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
00100   uint32_t BreakState;            /*!< TIM Break State
00101                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
00102   uint32_t BreakPolarity;         /*!< TIM Break input polarity
00103                                      This parameter can be a value of @ref TIM_Break_Polarity */
00104   uint32_t AutomaticOutput;       /*!< TIM Automatic Output Enable state
00105                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
00106 } TIM_BreakDeadTimeConfigTypeDef;
00107
00108 #endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
00109        /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
00110        /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
00111
00112 /**
00113   * @brief  TIM Master configuration Structure definition
00114   */
00115 typedef struct {
00116   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
00117                                       This parameter can be a value of @ref TIM_Master_Mode_Selection */
00118   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
00119                                       This parameter can be a value of @ref TIM_Master_Slave_Mode */
00120 }TIM_MasterConfigTypeDef;
00121
00122 /**
00123   * @}
00124   */
00125
00126 /* Exported constants --------------------------------------------------------*/
00127 #if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
00128     defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
00129     defined (STM32F105xC) || defined (STM32F107xC)
00130 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
00131   * @{
00132   */
00133
00134 /** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter
00135   * @{
00136   */
00137 #define IS_TIM_DEADTIME(DEADTIME)      ((DEADTIME) <= 0xFFU)          /*!< BreakDead Time */
00138 /**
00139   * @}
00140   */
00141
00142 /**
00143   * @}
00144   */
00145 #endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
00146        /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
00147        /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
00148
00149 /* Exported macro ------------------------------------------------------------*/
00150 /**
00151   * @brief  Sets the TIM Output compare preload.
00152   * @param  __HANDLE__: TIM handle.
00153   * @param  __CHANNEL__: TIM Channels to be configured.
00154   *          This parameter can be one of the following values:
00155   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00156   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00157   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00158   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00159   * @retval None
00160   */
00161 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
00162         (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
00163          ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
00164          ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
00165          ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
00166
00167 /**
00168   * @brief  Resets the TIM Output compare preload.
00169   * @param  __HANDLE__: TIM handle.
00170   * @param  __CHANNEL__: TIM Channels to be configured.
00171   *          This parameter can be one of the following values:
00172   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00173   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00174   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00175   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00176   * @retval None
00177   */
00178 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
00179         (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
00180          ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
00181          ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
00182          ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
00183
00184 /* Exported functions --------------------------------------------------------*/
00185 /** @addtogroup TIMEx_Exported_Functions
00186   * @{
00187   */
00188
00189 /** @addtogroup TIMEx_Exported_Functions_Group1
00190   * @{
00191  */
00192 /* Timer Hall Sensor functions  **********************************************/
00193 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
00194 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
00195
00196 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
00197 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
00198
00199  /* Blocking mode: Polling */
00200 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
00201 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
00202 /* Non-Blocking mode: Interrupt */
00203 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
00204 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
00205 /* Non-Blocking mode: DMA */
00206 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
00207 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
00208 /**
00209   * @}
00210   */
00211
00212 #if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
00213     defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
00214     defined (STM32F105xC) || defined (STM32F107xC)
00215
00216 /** @addtogroup TIMEx_Exported_Functions_Group2
00217  * @{
00218  */
00219 /* Timer Complementary Output Compare functions  *****************************/
00220 /* Blocking mode: Polling */
00221 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00222 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00223
00224 /* Non-Blocking mode: Interrupt */
00225 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00226 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00227
00228 /* Non-Blocking mode: DMA */
00229 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00230 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00231 /**
00232   * @}
00233   */
00234
00235 /** @addtogroup TIMEx_Exported_Functions_Group3
00236  * @{
00237  */
00238 /* Timer Complementary PWM functions  ****************************************/
00239 /* Blocking mode: Polling */
00240 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
00241 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
00242
00243 /* Non-Blocking mode: Interrupt */
00244 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00245 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
00246 /* Non-Blocking mode: DMA */
00247 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
00248 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
00249 /**
00250   * @}
00251   */
00252
00253 /** @addtogroup TIMEx_Exported_Functions_Group4
00254  * @{
00255  */
00256 /* Timer Complementary One Pulse functions  **********************************/
00257 /* Blocking mode: Polling */
00258 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00259 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00260
00261 /* Non-Blocking mode: Interrupt */
00262 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00263 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
00264 /**
00265   * @}
00266   */
00267 #endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
00268        /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
00269        /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
00270
00271 /** @addtogroup TIMEx_Exported_Functions_Group5
00272  * @{
00273  */
00274 /* Extended Control functions  ************************************************/
00275 #if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
00276     defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
00277     defined (STM32F105xC) || defined (STM32F107xC)
00278 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00279 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00280 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
00281 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
00282 #endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
00283        /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
00284        /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
00285 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
00286 /**
00287   * @}
00288   */
00289
00290 /** @addtogroup TIMEx_Exported_Functions_Group6
00291   * @{
00292   */
00293 /* Extension Callback *********************************************************/
00294 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
00295 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
00296 /**
00297   * @}
00298   */
00299
00300 #if defined (STM32F100xB) || defined (STM32F100xE) ||                                                   \
00301     defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
00302     defined (STM32F105xC) || defined (STM32F107xC)
00303 /** @addtogroup TIMEx_Exported_Functions_Group7
00304   * @{
00305   */
00306 /* Extension Peripheral State functions  **************************************/
00307 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
00308 /**
00309   * @}
00310   */
00311 #endif /* defined(STM32F100xB) || defined(STM32F100xE) ||                                                 */
00312        /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
00313        /* defined(STM32F105xC) || defined(STM32F107xC)                                                    */
00314
00315 /**
00316   * @}
00317   */
00318 /* End of exported functions -------------------------------------------------*/
00319
00320 /* Private functions----------------------------------------------------------*/
00321 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
00322 * @{
00323 */
00324 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
00325 /**
00326 * @}
00327 */
00328 /* End of private functions --------------------------------------------------*/
00329
00330 /**
00331   * @}
00332   */
00333
00334 /**
00335   * @}
00336   */
00337
00338 #ifdef __cplusplus
00339 }
00340 #endif
00341
00342
00343 #endif /* __STM32F1xx_HAL_TIM_EX_H */
00344
00345 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_uart.c Source File

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stm32f1xx_hal_uart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_uart.c
00004   * @author  MCD Application Team
00005   * @version V1.5.0
00006   * @date    13-february-2017
00007   * @brief   UART HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   *           + Peripheral State and Errors functions
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018   [..]
00019     The UART HAL driver can be used as follows:
00020
00021     (#) Declare a UART_HandleTypeDef handle structure.
00022     (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
00023         (##) Enable the USARTx interface clock.
00024         (##) UART pins configuration:
00025             (+++) Enable the clock for the UART GPIOs.
00026             (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input).
00027         (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
00028              and HAL_UART_Receive_IT() APIs):
00029             (+++) Configure the USARTx interrupt priority.
00030             (+++) Enable the NVIC USART IRQ handle.
00031         (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
00032              and HAL_UART_Receive_DMA() APIs):
00033             (+++) Declare a DMA handle structure for the Tx/Rx channel.
00034             (+++) Enable the DMAx interface clock.
00035             (+++) Configure the declared DMA handle structure with the required
00036                   Tx/Rx parameters.
00037             (+++) Configure the DMA Tx/Rx channel.
00038             (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
00039             (+++) Configure the priority and enable the NVIC for the transfer complete
00040                   interrupt on the DMA Tx/Rx channel.
00041             (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
00042                   (used for last byte sending completion detection in DMA non circular mode)
00043
00044     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00045         flow control and Mode(Receiver/Transmitter) in the huart Init structure.
00046
00047     (#) For the UART asynchronous mode, initialize the UART registers by calling
00048         the HAL_UART_Init() API.
00049
00050     (#) For the UART Half duplex mode, initialize the UART registers by calling
00051         the HAL_HalfDuplex_Init() API.
00052
00053     (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
00054
00055     (#) For the Multi-Processor mode, initialize the UART registers by calling
00056         the HAL_MultiProcessor_Init() API.
00057
00058      [..]
00059        (@) The specific UART interrupts (Transmission complete interrupt,
00060             RXNE interrupt and Error Interrupts) will be managed using the macros
00061             __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
00062             and receive process.
00063
00064      [..]
00065        (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
00066             low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
00067             HAL_UART_MspInit() API.
00068
00069      [..]
00070         Three operation modes are available within this driver:
00071
00072      *** Polling mode IO operation ***
00073      =================================
00074      [..]
00075        (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
00076        (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
00077
00078      *** Interrupt mode IO operation ***
00079      ===================================
00080      [..]
00081        (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
00082        (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
00083             add his own code by customization of function pointer HAL_UART_TxCpltCallback
00084        (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
00085        (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
00086             add his own code by customization of function pointer HAL_UART_RxCpltCallback
00087        (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
00088             add his own code by customization of function pointer HAL_UART_ErrorCallback
00089
00090      *** DMA mode IO operation ***
00091      ==============================
00092      [..]
00093        (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
00094        (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
00095             add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
00096        (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
00097             add his own code by customization of function pointer HAL_UART_TxCpltCallback
00098        (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
00099        (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
00100             add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
00101        (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
00102             add his own code by customization of function pointer HAL_UART_RxCpltCallback
00103        (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
00104             add his own code by customization of function pointer HAL_UART_ErrorCallback
00105        (+) Pause the DMA Transfer using HAL_UART_DMAPause()
00106        (+) Resume the DMA Transfer using HAL_UART_DMAResume()
00107        (+) Stop the DMA Transfer using HAL_UART_DMAStop()
00108
00109      *** UART HAL driver macros list ***
00110      =============================================
00111      [..]
00112        Below the list of most used macros in UART HAL driver.
00113
00114       (+) __HAL_UART_ENABLE: Enable the UART peripheral
00115       (+) __HAL_UART_DISABLE: Disable the UART peripheral
00116       (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
00117       (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
00118       (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
00119       (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
00120       (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
00121
00122      [..]
00123        (@) You can refer to the UART HAL driver header file for more useful macros
00124   @endverbatim
00125      [..]
00126        (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
00127            in the data register is transmitted but is changed by the parity bit.
00128            Depending on the frame length defined by the M bit (8-bits or 9-bits),
00129            the possible UART frame formats are as listed in the following table:
00130     +-------------------------------------------------------------+
00131     |   M bit |  PCE bit  |            UART frame                 |
00132     |---------------------|---------------------------------------|
00133     |    0    |    0      |    | SB | 8 bit data | STB |          |
00134     |---------|-----------|---------------------------------------|
00135     |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00136     |---------|-----------|---------------------------------------|
00137     |    1    |    0      |    | SB | 9 bit data | STB |          |
00138     |---------|-----------|---------------------------------------|
00139     |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00140     +-------------------------------------------------------------+
00141   ******************************************************************************
00142   * @attention
00143   *
00144   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00145   *
00146   * Redistribution and use in source and binary forms, with or without modification,
00147   * are permitted provided that the following conditions are met:
00148   *   1. Redistributions of source code must retain the above copyright notice,
00149   *      this list of conditions and the following disclaimer.
00150   *   2. Redistributions in binary form must reproduce the above copyright notice,
00151   *      this list of conditions and the following disclaimer in the documentation
00152   *      and/or other materials provided with the distribution.
00153   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00154   *      may be used to endorse or promote products derived from this software
00155   *      without specific prior written permission.
00156   *
00157   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00158   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00159   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00160   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00161   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00162   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00163   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00164   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00165   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00166   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00167   *
00168   ******************************************************************************
00169   */
00170
00171 /* Includes ------------------------------------------------------------------*/
00172 #include "stm32f1xx_hal.h"
00173
00174 /** @addtogroup STM32F1xx_HAL_Driver
00175   * @{
00176   */
00177
00178 /** @defgroup UART UART
00179   * @brief HAL UART module driver
00180   * @{
00181   */
00182 #ifdef HAL_UART_MODULE_ENABLED
00183
00184 /* Private typedef -----------------------------------------------------------*/
00185 /* Private define ------------------------------------------------------------*/
00186 /** @addtogroup UART_Private_Constants
00187   * @{
00188   */
00189 /**
00190   * @}
00191   */
00192 /* Private macro -------------------------------------------------------------*/
00193 /* Private variables ---------------------------------------------------------*/
00194 /* Private function prototypes -----------------------------------------------*/
00195 /** @addtogroup UART_Private_Functions
00196   * @{
00197   */
00198 static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
00199 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
00200 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00201 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00202 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00203 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00204 static void UART_DMAError(DMA_HandleTypeDef *hdma);
00205 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00206 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00207 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00208 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00209 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
00210 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
00211 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
00212 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
00213 static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00214 static void UART_SetConfig (UART_HandleTypeDef *huart);
00215 /**
00216   * @}
00217   */
00218 /* Exported functions ---------------------------------------------------------*/
00219 /** @defgroup UART_Exported_Functions UART Exported Functions
00220   * @{
00221   */
00222
00223 /** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
00224   *  @brief    Initialization and Configuration functions
00225   *
00226 @verbatim
00227   ==============================================================================
00228             ##### Initialization and Configuration functions #####
00229   ==============================================================================
00230     [..]
00231     This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
00232     in asynchronous mode.
00233       (+) For the asynchronous mode only these parameters can be configured:
00234         (++) Baud Rate
00235         (++) Word Length
00236         (++) Stop Bit
00237         (++) Parity: If the parity is enabled, then the MSB bit of the data written
00238              in the data register is transmitted but is changed by the parity bit.
00239              Depending on the frame length defined by the M bit (8-bits or 9-bits),
00240              please refer to Reference manual for possible UART frame formats.
00241         (++) Hardware flow control
00242         (++) Receiver/transmitter modes
00243         (++) Over Sampling Method
00244     [..]
00245     The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
00246     follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
00247     configuration procedures (details for the procedures are available in reference manuals
00248     (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
00249
00250 @endverbatim
00251   * @{
00252   */
00253
00254 /**
00255   * @brief  Initializes the UART mode according to the specified parameters in
00256   *         the UART_InitTypeDef and create the associated handle.
00257   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00258   *                the configuration information for the specified UART module.
00259   * @retval HAL status
00260   */
00261 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
00262 {
00263   /* Check the UART handle allocation */
00264   if(huart == NULL)
00265   {
00266     return HAL_ERROR;
00267   }
00268
00269   /* Check the parameters */
00270   if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
00271   {
00272     /* The hardware flow control is available only for USART1, USART2, USART3 */
00273     assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
00274     assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
00275   }
00276   else
00277   {
00278     assert_param(IS_UART_INSTANCE(huart->Instance));
00279   }
00280   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
00281 #if defined(USART_CR1_OVER8)
00282   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
00283 #endif /* USART_CR1_OVER8 */
00284
00285   if(huart->gState == HAL_UART_STATE_RESET)
00286   {
00287     /* Allocate lock resource and initialize it */
00288     huart->Lock = HAL_UNLOCKED;
00289
00290     /* Init the low level hardware */
00291     HAL_UART_MspInit(huart);
00292   }
00293
00294   huart->gState = HAL_UART_STATE_BUSY;
00295
00296   /* Disable the peripheral */
00297   __HAL_UART_DISABLE(huart);
00298
00299   /* Set the UART Communication parameters */
00300   UART_SetConfig(huart);
00301
00302   /* In asynchronous mode, the following bits must be kept cleared:
00303      - LINEN and CLKEN bits in the USART_CR2 register,
00304      - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
00305   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00306   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00307
00308   /* Enable the peripheral */
00309   __HAL_UART_ENABLE(huart);
00310
00311   /* Initialize the UART state */
00312   huart->ErrorCode = HAL_UART_ERROR_NONE;
00313   huart->gState= HAL_UART_STATE_READY;
00314   huart->RxState= HAL_UART_STATE_READY;
00315
00316   return HAL_OK;
00317 }
00318
00319 /**
00320   * @brief  Initializes the half-duplex mode according to the specified
00321   *         parameters in the UART_InitTypeDef and create the associated handle.
00322   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00323   *                the configuration information for the specified UART module.
00324   * @retval HAL status
00325   */
00326 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
00327 {
00328   /* Check the UART handle allocation */
00329   if(huart == NULL)
00330   {
00331     return HAL_ERROR;
00332   }
00333
00334   /* Check the parameters */
00335   assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
00336   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
00337 #if defined(USART_CR1_OVER8)
00338   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
00339 #endif /* USART_CR1_OVER8 */
00340   if(huart->gState == HAL_UART_STATE_RESET)
00341   {
00342     /* Allocate lock resource and initialize it */
00343     huart->Lock = HAL_UNLOCKED;
00344     /* Init the low level hardware */
00345     HAL_UART_MspInit(huart);
00346   }
00347
00348   huart->gState = HAL_UART_STATE_BUSY;
00349
00350   /* Disable the peripheral */
00351   __HAL_UART_DISABLE(huart);
00352
00353   /* Set the UART Communication parameters */
00354   UART_SetConfig(huart);
00355
00356   /* In half-duplex mode, the following bits must be kept cleared:
00357      - LINEN and CLKEN bits in the USART_CR2 register,
00358      - SCEN and IREN bits in the USART_CR3 register.*/
00359   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00360   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
00361
00362   /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
00363   SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
00364
00365   /* Enable the peripheral */
00366   __HAL_UART_ENABLE(huart);
00367
00368   /* Initialize the UART state*/
00369   huart->ErrorCode = HAL_UART_ERROR_NONE;
00370   huart->gState= HAL_UART_STATE_READY;
00371   huart->RxState= HAL_UART_STATE_READY;
00372
00373   return HAL_OK;
00374 }
00375
00376 /**
00377   * @brief  Initializes the LIN mode according to the specified
00378   *         parameters in the UART_InitTypeDef and create the associated handle.
00379   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00380   *                the configuration information for the specified UART module.
00381   * @param  BreakDetectLength: Specifies the LIN break detection length.
00382   *         This parameter can be one of the following values:
00383   *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
00384   *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
00385   * @retval HAL status
00386   */
00387 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
00388 {
00389   /* Check the UART handle allocation */
00390   if(huart == NULL)
00391   {
00392     return HAL_ERROR;
00393   }
00394
00395   /* Check the LIN UART instance */
00396   assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
00397   /* Check the Break detection length parameter */
00398   assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
00399   assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
00400 #if defined(USART_CR1_OVER8)
00401   assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
00402 #endif /* USART_CR1_OVER8 */
00403
00404   if(huart->gState == HAL_UART_STATE_RESET)
00405   {
00406     /* Allocate lock resource and initialize it */
00407     huart->Lock = HAL_UNLOCKED;
00408     /* Init the low level hardware */
00409     HAL_UART_MspInit(huart);
00410   }
00411
00412   huart->gState = HAL_UART_STATE_BUSY;
00413
00414   /* Disable the peripheral */
00415   __HAL_UART_DISABLE(huart);
00416
00417   /* Set the UART Communication parameters */
00418   UART_SetConfig(huart);
00419
00420   /* In LIN mode, the following bits must be kept cleared:
00421      - CLKEN bits in the USART_CR2 register,
00422      - SCEN and IREN bits in the USART_CR3 register.*/
00423   CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
00424   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
00425
00426   /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
00427   SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
00428
00429   /* Set the USART LIN Break detection length. */
00430   MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
00431
00432   /* Enable the peripheral */
00433   __HAL_UART_ENABLE(huart);
00434
00435   /* Initialize the UART state*/
00436   huart->ErrorCode = HAL_UART_ERROR_NONE;
00437   huart->gState= HAL_UART_STATE_READY;
00438   huart->RxState= HAL_UART_STATE_READY;
00439
00440   return HAL_OK;
00441 }
00442
00443 /**
00444   * @brief  Initializes the Multi-Processor mode according to the specified
00445   *         parameters in the UART_InitTypeDef and create the associated handle.
00446   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00447   *                the configuration information for the specified UART module.
00448   * @param  Address: USART address
00449   * @param  WakeUpMethod: specifies the USART wake-up method.
00450   *         This parameter can be one of the following values:
00451   *            @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
00452   *            @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
00453   * @retval HAL status
00454   */
00455 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
00456 {
00457   /* Check the UART handle allocation */
00458   if(huart == NULL)
00459   {
00460     return HAL_ERROR;
00461   }
00462
00463   /* Check UART instance capabilities */
00464   assert_param(IS_UART_MULTIPROCESSOR_INSTANCE(huart->Instance));
00465
00466   /* Check the Address & wake up method parameters */
00467   assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
00468   assert_param(IS_UART_ADDRESS(Address));
00469   assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
00470 #if defined(USART_CR1_OVER8)
00471   assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
00472 #endif /* USART_CR1_OVER8 */
00473
00474   if(huart->gState == HAL_UART_STATE_RESET)
00475   {
00476     /* Allocate lock resource and initialize it */
00477     huart->Lock = HAL_UNLOCKED;
00478     /* Init the low level hardware */
00479     HAL_UART_MspInit(huart);
00480   }
00481
00482   huart->gState = HAL_UART_STATE_BUSY;
00483
00484   /* Disable the peripheral */
00485   __HAL_UART_DISABLE(huart);
00486
00487   /* Set the UART Communication parameters */
00488   UART_SetConfig(huart);
00489
00490   /* In Multi-Processor mode, the following bits must be kept cleared:
00491      - LINEN and CLKEN bits in the USART_CR2 register,
00492      - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
00493   CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
00494   CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00495
00496   /* Set the USART address node */
00497   MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, Address);
00498
00499   /* Set the wake up method by setting the WAKE bit in the CR1 register */
00500   MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
00501
00502   /* Enable the peripheral */
00503   __HAL_UART_ENABLE(huart);
00504
00505   /* Initialize the UART state */
00506   huart->ErrorCode = HAL_UART_ERROR_NONE;
00507   huart->gState = HAL_UART_STATE_READY;
00508   huart->RxState = HAL_UART_STATE_READY;
00509
00510   return HAL_OK;
00511 }
00512
00513 /**
00514   * @brief  DeInitializes the UART peripheral.
00515   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00516   *                the configuration information for the specified UART module.
00517   * @retval HAL status
00518   */
00519 HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
00520 {
00521   /* Check the UART handle allocation */
00522   if(huart == NULL)
00523   {
00524     return HAL_ERROR;
00525   }
00526
00527   /* Check the parameters */
00528   assert_param(IS_UART_INSTANCE(huart->Instance));
00529
00530   huart->gState = HAL_UART_STATE_BUSY;
00531
00532   /* DeInit the low level hardware */
00533   HAL_UART_MspDeInit(huart);
00534
00535   huart->ErrorCode = HAL_UART_ERROR_NONE;
00536   huart->gState = HAL_UART_STATE_RESET;
00537   huart->RxState = HAL_UART_STATE_RESET;
00538
00539   /* Process Unlock */
00540   __HAL_UNLOCK(huart);
00541
00542   return HAL_OK;
00543 }
00544
00545 /**
00546   * @brief  UART MSP Init.
00547   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00548   *                the configuration information for the specified UART module.
00549   * @retval None
00550   */
00551 __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
00552 {
00553   /* Prevent unused argument(s) compilation warning */
00554   UNUSED(huart);
00555   /* NOTE: This function should not be modified, when the callback is needed,
00556            the HAL_UART_MspInit could be implemented in the user file
00557    */
00558 }
00559
00560 /**
00561   * @brief  UART MSP DeInit.
00562   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00563   *                the configuration information for the specified UART module.
00564   * @retval None
00565   */
00566 __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
00567 {
00568   /* Prevent unused argument(s) compilation warning */
00569   UNUSED(huart);
00570   /* NOTE: This function should not be modified, when the callback is needed,
00571            the HAL_UART_MspDeInit could be implemented in the user file
00572    */
00573 }
00574
00575 /**
00576   * @}
00577   */
00578
00579 /** @defgroup UART_Exported_Functions_Group2 IO operation functions
00580   *  @brief UART Transmit and Receive functions
00581   *
00582 @verbatim
00583   ==============================================================================
00584                       ##### IO operation functions #####
00585   ==============================================================================
00586   [..]
00587     This subsection provides a set of functions allowing to manage the UART asynchronous
00588     and Half duplex data transfers.
00589
00590     (#) There are two modes of transfer:
00591        (++) Blocking mode: The communication is performed in polling mode.
00592             The HAL status of all data processing is returned by the same function
00593             after finishing transfer.
00594        (++) Non blocking mode: The communication is performed using Interrupts
00595             or DMA, these APIs return the HAL status.
00596             The end of the data processing will be indicated through the
00597             dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
00598             using DMA mode.
00599             The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
00600             will be executed respectively at the end of the transmit or receive process.
00601             The HAL_UART_ErrorCallback() user callback will be executed when
00602             a communication error is detected.
00603
00604     (#) Blocking mode APIs are:
00605         (++) HAL_UART_Transmit()
00606         (++) HAL_UART_Receive()
00607
00608     (#) Non Blocking mode APIs with Interrupt are:
00609         (++) HAL_UART_Transmit_IT()
00610         (++) HAL_UART_Receive_IT()
00611         (++) HAL_UART_IRQHandler()
00612
00613     (#) Non Blocking mode functions with DMA are:
00614         (++) HAL_UART_Transmit_DMA()
00615         (++) HAL_UART_Receive_DMA()
00616         (++) HAL_UART_DMAPause()
00617         (++) HAL_UART_DMAResume()
00618         (++) HAL_UART_DMAStop()
00619
00620     (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
00621         (++) HAL_UART_TxHalfCpltCallback()
00622         (++) HAL_UART_TxCpltCallback()
00623         (++) HAL_UART_RxHalfCpltCallback()
00624         (++) HAL_UART_RxCpltCallback()
00625         (++) HAL_UART_ErrorCallback()
00626
00627     [..]
00628       (@) In the Half duplex communication, it is forbidden to run the transmit
00629           and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
00630           can't be useful.
00631
00632 @endverbatim
00633   * @{
00634   */
00635
00636 /**
00637   * @brief  Sends an amount of data in blocking mode.
00638   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00639   *                the configuration information for the specified UART module.
00640   * @param  pData: Pointer to data buffer
00641   * @param  Size: Amount of data to be sent
00642   * @param  Timeout: Timeout duration
00643   * @retval HAL status
00644   */
00645 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00646 {
00647   uint16_t* tmp;
00648   uint32_t tickstart = 0U;
00649
00650   /* Check that a Tx process is not already ongoing */
00651   if(huart->gState == HAL_UART_STATE_READY)
00652   {
00653     if((pData == NULL) || (Size == 0U))
00654     {
00655       return  HAL_ERROR;
00656     }
00657
00658     /* Process Locked */
00659     __HAL_LOCK(huart);
00660
00661     huart->ErrorCode = HAL_UART_ERROR_NONE;
00662     huart->gState = HAL_UART_STATE_BUSY_TX;
00663
00664     /* Init tickstart for timeout managment */
00665     tickstart = HAL_GetTick();
00666
00667     huart->TxXferSize = Size;
00668     huart->TxXferCount = Size;
00669     while(huart->TxXferCount > 0U)
00670     {
00671       huart->TxXferCount--;
00672       if(huart->Init.WordLength == UART_WORDLENGTH_9B)
00673       {
00674         if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00675         {
00676           return HAL_TIMEOUT;
00677         }
00678         tmp = (uint16_t*) pData;
00679         huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
00680         if(huart->Init.Parity == UART_PARITY_NONE)
00681         {
00682           pData +=2U;
00683         }
00684         else
00685         {
00686           pData +=1U;
00687         }
00688       }
00689       else
00690       {
00691         if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00692         {
00693           return HAL_TIMEOUT;
00694         }
00695         huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
00696       }
00697     }
00698
00699     if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00700     {
00701       return HAL_TIMEOUT;
00702     }
00703
00704     /* At end of Tx process, restore huart->gState to Ready */
00705     huart->gState = HAL_UART_STATE_READY;
00706
00707     /* Process Unlocked */
00708     __HAL_UNLOCK(huart);
00709
00710     return HAL_OK;
00711   }
00712   else
00713   {
00714     return HAL_BUSY;
00715   }
00716 }
00717
00718 /**
00719   * @brief  Receive an amount of data in blocking mode.
00720   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00721   *                the configuration information for the specified UART module.
00722   * @param  pData: Pointer to data buffer
00723   * @param  Size: Amount of data to be received
00724   * @param  Timeout: Timeout duration
00725   * @retval HAL status
00726   */
00727 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00728 {
00729   uint16_t* tmp;
00730   uint32_t tickstart = 0U;
00731
00732   /* Check that a Rx process is not already ongoing */
00733   if(huart->RxState == HAL_UART_STATE_READY)
00734   {
00735     if((pData == NULL) || (Size == 0U))
00736     {
00737       return  HAL_ERROR;
00738     }
00739
00740     /* Process Locked */
00741     __HAL_LOCK(huart);
00742
00743     huart->ErrorCode = HAL_UART_ERROR_NONE;
00744     huart->RxState = HAL_UART_STATE_BUSY_RX;
00745
00746     /* Init tickstart for timeout managment */
00747     tickstart = HAL_GetTick();
00748
00749     huart->RxXferSize = Size;
00750     huart->RxXferCount = Size;
00751
00752     /* Check the remain data to be received */
00753     while(huart->RxXferCount > 0U)
00754     {
00755       huart->RxXferCount--;
00756       if(huart->Init.WordLength == UART_WORDLENGTH_9B)
00757       {
00758         if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00759         {
00760           return HAL_TIMEOUT;
00761         }
00762         tmp = (uint16_t*)pData;
00763         if(huart->Init.Parity == UART_PARITY_NONE)
00764         {
00765           *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
00766           pData +=2U;
00767         }
00768         else
00769         {
00770           *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
00771           pData +=1U;
00772         }
00773
00774       }
00775       else
00776       {
00777         if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00778         {
00779           return HAL_TIMEOUT;
00780         }
00781         if(huart->Init.Parity == UART_PARITY_NONE)
00782         {
00783           *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
00784         }
00785         else
00786         {
00787           *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
00788         }
00789
00790       }
00791     }
00792
00793     /* At end of Rx process, restore huart->RxState to Ready */
00794     huart->RxState = HAL_UART_STATE_READY;
00795
00796     /* Process Unlocked */
00797     __HAL_UNLOCK(huart);
00798
00799     return HAL_OK;
00800   }
00801   else
00802   {
00803     return HAL_BUSY;
00804   }
00805 }
00806
00807 /**
00808   * @brief  Sends an amount of data in non blocking mode.
00809   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00810   *                the configuration information for the specified UART module.
00811   * @param  pData: Pointer to data buffer
00812   * @param  Size: Amount of data to be sent
00813   * @retval HAL status
00814   */
00815 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00816 {
00817   /* Check that a Tx process is not already ongoing */
00818   if(huart->gState == HAL_UART_STATE_READY)
00819   {
00820     if((pData == NULL) || (Size == 0U))
00821     {
00822       return HAL_ERROR;
00823     }
00824     /* Process Locked */
00825     __HAL_LOCK(huart);
00826
00827     huart->pTxBuffPtr = pData;
00828     huart->TxXferSize = Size;
00829     huart->TxXferCount = Size;
00830
00831     huart->ErrorCode = HAL_UART_ERROR_NONE;
00832     huart->gState = HAL_UART_STATE_BUSY_TX;
00833
00834     /* Process Unlocked */
00835     __HAL_UNLOCK(huart);
00836
00837     /* Enable the UART Transmit data register empty Interrupt */
00838     __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
00839
00840     return HAL_OK;
00841   }
00842   else
00843   {
00844     return HAL_BUSY;
00845   }
00846 }
00847
00848 /**
00849   * @brief  Receives an amount of data in non blocking mode.
00850   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00851   *                the configuration information for the specified UART module.
00852   * @param  pData: Pointer to data buffer
00853   * @param  Size: Amount of data to be received
00854   * @retval HAL status
00855   */
00856 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00857 {
00858   /* Check that a Rx process is not already ongoing */
00859   if(huart->RxState == HAL_UART_STATE_READY)
00860   {
00861     if((pData == NULL) || (Size == 0U))
00862     {
00863       return HAL_ERROR;
00864     }
00865
00866     /* Process Locked */
00867     __HAL_LOCK(huart);
00868
00869     huart->pRxBuffPtr = pData;
00870     huart->RxXferSize = Size;
00871     huart->RxXferCount = Size;
00872
00873     huart->ErrorCode = HAL_UART_ERROR_NONE;
00874     huart->RxState = HAL_UART_STATE_BUSY_RX;
00875
00876     /* Process Unlocked */
00877     __HAL_UNLOCK(huart);
00878
00879     /* Enable the UART Parity Error Interrupt */
00880     __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
00881
00882     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
00883     __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
00884
00885     /* Enable the UART Data Register not empty Interrupt */
00886     __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
00887
00888     return HAL_OK;
00889   }
00890   else
00891   {
00892     return HAL_BUSY;
00893   }
00894 }
00895
00896 /**
00897   * @brief  Sends an amount of data in non blocking mode.
00898   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00899   *                the configuration information for the specified UART module.
00900   * @param  pData: Pointer to data buffer
00901   * @param  Size: Amount of data to be sent
00902   * @retval HAL status
00903   */
00904 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00905 {
00906   uint32_t *tmp;
00907
00908   /* Check that a Tx process is not already ongoing */
00909   if(huart->gState == HAL_UART_STATE_READY)
00910   {
00911     if((pData == NULL) || (Size == 0U))
00912     {
00913       return HAL_ERROR;
00914     }
00915
00916     /* Process Locked */
00917     __HAL_LOCK(huart);
00918
00919     huart->pTxBuffPtr = pData;
00920     huart->TxXferSize = Size;
00921     huart->TxXferCount = Size;
00922
00923     huart->ErrorCode = HAL_UART_ERROR_NONE;
00924     huart->gState = HAL_UART_STATE_BUSY_TX;
00925
00926     /* Set the UART DMA transfer complete callback */
00927     huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
00928
00929     /* Set the UART DMA Half transfer complete callback */
00930     huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
00931
00932     /* Set the DMA error callback */
00933     huart->hdmatx->XferErrorCallback = UART_DMAError;
00934
00935     /* Set the DMA abort callback */
00936     huart->hdmatx->XferAbortCallback = NULL;
00937
00938     /* Enable the UART transmit DMA channel */
00939     tmp = (uint32_t*)&pData;
00940     HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
00941
00942     /* Clear the TC flag in the SR register by writing 0 to it */
00943     __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
00944
00945     /* Process Unlocked */
00946     __HAL_UNLOCK(huart);
00947
00948     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00949        in the UART CR3 register */
00950     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
00951
00952     return HAL_OK;
00953   }
00954   else
00955   {
00956     return HAL_BUSY;
00957   }
00958 }
00959
00960 /**
00961   * @brief  Receives an amount of data in non blocking mode.
00962   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
00963   *                the configuration information for the specified UART module.
00964   * @param  pData: Pointer to data buffer
00965   * @param  Size: Amount of data to be received
00966   * @note   When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
00967   * @retval HAL status
00968   */
00969 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
00970 {
00971   uint32_t *tmp;
00972
00973   /* Check that a Rx process is not already ongoing */
00974   if(huart->RxState == HAL_UART_STATE_READY)
00975   {
00976     if((pData == NULL) || (Size == 0U))
00977     {
00978       return HAL_ERROR;
00979     }
00980
00981     /* Process Locked */
00982     __HAL_LOCK(huart);
00983
00984     huart->pRxBuffPtr = pData;
00985     huart->RxXferSize = Size;
00986
00987     huart->ErrorCode = HAL_UART_ERROR_NONE;
00988     huart->RxState = HAL_UART_STATE_BUSY_RX;
00989
00990     /* Set the UART DMA transfer complete callback */
00991     huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
00992
00993     /* Set the UART DMA Half transfer complete callback */
00994     huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
00995
00996     /* Set the DMA error callback */
00997     huart->hdmarx->XferErrorCallback = UART_DMAError;
00998
00999     /* Set the DMA abort callback */
01000     huart->hdmarx->XferAbortCallback = NULL;
01001
01002     /* Enable the DMA channel */
01003     tmp = (uint32_t*)&pData;
01004     HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
01005
01006     /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
01007     __HAL_UART_CLEAR_OREFLAG(huart);
01008
01009     /* Process Unlocked */
01010     __HAL_UNLOCK(huart);
01011
01012     /* Enable the UART Parity Error Interrupt */
01013     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01014
01015     /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
01016     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01017
01018     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01019     in the UART CR3 register */
01020     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01021
01022     return HAL_OK;
01023   }
01024   else
01025   {
01026     return HAL_BUSY;
01027   }
01028 }
01029
01030 /**
01031   * @brief Pauses the DMA Transfer.
01032   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01033   *                the configuration information for the specified UART module.
01034   * @retval HAL status
01035   */
01036 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
01037 {
01038   uint32_t dmarequest = 0x00U;
01039
01040   /* Process Locked */
01041   __HAL_LOCK(huart);
01042
01043   dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
01044   if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
01045   {
01046     /* Disable the UART DMA Tx request */
01047     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01048   }
01049
01050   dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
01051   if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
01052   {
01053     /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01054     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01055     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01056
01057     /* Disable the UART DMA Rx request */
01058     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01059   }
01060
01061   /* Process Unlocked */
01062   __HAL_UNLOCK(huart);
01063
01064   return HAL_OK;
01065 }
01066
01067 /**
01068   * @brief Resumes the DMA Transfer.
01069   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01070   *                the configuration information for the specified UART module.
01071   * @retval HAL status
01072   */
01073 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
01074 {
01075   /* Process Locked */
01076   __HAL_LOCK(huart);
01077
01078   if(huart->gState == HAL_UART_STATE_BUSY_TX)
01079   {
01080     /* Enable the UART DMA Tx request */
01081     SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01082   }
01083
01084   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
01085   {
01086     /* Clear the Overrun flag before resuming the Rx transfer*/
01087     __HAL_UART_CLEAR_OREFLAG(huart);
01088
01089     /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
01090     SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
01091     SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
01092
01093     /* Enable the UART DMA Rx request */
01094     SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01095   }
01096
01097   /* Process Unlocked */
01098   __HAL_UNLOCK(huart);
01099
01100   return HAL_OK;
01101 }
01102
01103 /**
01104   * @brief Stops the DMA Transfer.
01105   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01106   *                the configuration information for the specified UART module.
01107   * @retval HAL status
01108   */
01109 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
01110 {
01111   uint32_t dmarequest = 0x00U;
01112   /* The Lock is not implemented on this API to allow the user application
01113      to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
01114      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
01115      and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
01116      */
01117
01118   /* Stop UART DMA Tx request if ongoing */
01119   dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
01120   if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
01121   {
01122     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01123
01124     /* Abort the UART DMA Tx channel */
01125     if(huart->hdmatx != NULL)
01126     {
01127       HAL_DMA_Abort(huart->hdmatx);
01128     }
01129     UART_EndTxTransfer(huart);
01130   }
01131
01132   /* Stop UART DMA Rx request if ongoing */
01133   dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
01134   if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
01135   {
01136     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01137
01138     /* Abort the UART DMA Rx channel */
01139     if(huart->hdmarx != NULL)
01140     {
01141       HAL_DMA_Abort(huart->hdmarx);
01142     }
01143     UART_EndRxTransfer(huart);
01144   }
01145
01146   return HAL_OK;
01147 }
01148
01149 /**
01150   * @brief  Abort ongoing transfers (blocking mode).
01151   * @param  huart UART handle.
01152   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01153   *         This procedure performs following operations :
01154   *           - Disable PPP Interrupts
01155   *           - Disable the DMA transfer in the peripheral register (if enabled)
01156   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01157   *           - Set handle State to READY
01158   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01159   * @retval HAL status
01160 */
01161 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
01162 {
01163   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01164   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01165   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01166
01167   /* Disable the UART DMA Tx request if enabled */
01168   if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01169   {
01170     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01171
01172     /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */
01173     if(huart->hdmatx != NULL)
01174     {
01175       /* Set the UART DMA Abort callback to Null.
01176          No call back execution at end of DMA abort procedure */
01177       huart->hdmatx->XferAbortCallback = NULL;
01178
01179       HAL_DMA_Abort(huart->hdmatx);
01180     }
01181   }
01182
01183   /* Disable the UART DMA Rx request if enabled */
01184   if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01185   {
01186     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01187
01188     /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */
01189     if(huart->hdmarx != NULL)
01190     {
01191       /* Set the UART DMA Abort callback to Null.
01192          No call back execution at end of DMA abort procedure */
01193       huart->hdmarx->XferAbortCallback = NULL;
01194
01195       HAL_DMA_Abort(huart->hdmarx);
01196     }
01197   }
01198
01199   /* Reset Tx and Rx transfer counters */
01200   huart->TxXferCount = 0x00U;
01201   huart->RxXferCount = 0x00U;
01202
01203   /* Reset ErrorCode */
01204   huart->ErrorCode = HAL_UART_ERROR_NONE;
01205
01206   /* Restore huart->RxState and huart->gState to Ready */
01207   huart->RxState = HAL_UART_STATE_READY;
01208   huart->gState = HAL_UART_STATE_READY;
01209
01210   return HAL_OK;
01211 }
01212
01213 /**
01214   * @brief  Abort ongoing Transmit transfer (blocking mode).
01215   * @param  huart UART handle.
01216   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01217   *         This procedure performs following operations :
01218   *           - Disable PPP Interrupts
01219   *           - Disable the DMA transfer in the peripheral register (if enabled)
01220   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01221   *           - Set handle State to READY
01222   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01223   * @retval HAL status
01224 */
01225 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
01226 {
01227   /* Disable TXEIE and TCIE interrupts */
01228   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01229
01230   /* Disable the UART DMA Tx request if enabled */
01231   if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01232   {
01233     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01234
01235     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01236     if(huart->hdmatx != NULL)
01237     {
01238       /* Set the UART DMA Abort callback to Null.
01239          No call back execution at end of DMA abort procedure */
01240       huart->hdmatx->XferAbortCallback = NULL;
01241
01242       HAL_DMA_Abort(huart->hdmatx);
01243     }
01244   }
01245
01246   /* Reset Tx transfer counter */
01247   huart->TxXferCount = 0x00U;
01248
01249   /* Restore huart->gState to Ready */
01250   huart->gState = HAL_UART_STATE_READY;
01251
01252   return HAL_OK;
01253 }
01254
01255 /**
01256   * @brief  Abort ongoing Receive transfer (blocking mode).
01257   * @param  huart UART handle.
01258   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01259   *         This procedure performs following operations :
01260   *           - Disable PPP Interrupts
01261   *           - Disable the DMA transfer in the peripheral register (if enabled)
01262   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01263   *           - Set handle State to READY
01264   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01265   * @retval HAL status
01266 */
01267 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
01268 {
01269   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01270   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01271   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01272
01273   /* Disable the UART DMA Rx request if enabled */
01274   if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01275   {
01276     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01277
01278     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01279     if(huart->hdmarx != NULL)
01280     {
01281       /* Set the UART DMA Abort callback to Null.
01282          No call back execution at end of DMA abort procedure */
01283       huart->hdmarx->XferAbortCallback = NULL;
01284
01285       HAL_DMA_Abort(huart->hdmarx);
01286     }
01287   }
01288
01289   /* Reset Rx transfer counter */
01290   huart->RxXferCount = 0x00U;
01291
01292   /* Restore huart->RxState to Ready */
01293   huart->RxState = HAL_UART_STATE_READY;
01294
01295   return HAL_OK;
01296 }
01297
01298 /**
01299   * @brief  Abort ongoing transfers (Interrupt mode).
01300   * @param  huart UART handle.
01301   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01302   *         This procedure performs following operations :
01303   *           - Disable PPP Interrupts
01304   *           - Disable the DMA transfer in the peripheral register (if enabled)
01305   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01306   *           - Set handle State to READY
01307   *           - At abort completion, call user abort complete callback
01308   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01309   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01310   * @retval HAL status
01311 */
01312 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
01313 {
01314   uint32_t AbortCplt = 0x01U;
01315
01316   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01317   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01318   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01319
01320   /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
01321      before any call to DMA Abort functions */
01322   /* DMA Tx Handle is valid */
01323   if(huart->hdmatx != NULL)
01324   {
01325     /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
01326        Otherwise, set it to NULL */
01327     if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01328     {
01329       huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
01330     }
01331     else
01332     {
01333       huart->hdmatx->XferAbortCallback = NULL;
01334     }
01335   }
01336   /* DMA Rx Handle is valid */
01337   if(huart->hdmarx != NULL)
01338   {
01339     /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
01340        Otherwise, set it to NULL */
01341     if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01342     {
01343       huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
01344     }
01345     else
01346     {
01347       huart->hdmarx->XferAbortCallback = NULL;
01348     }
01349   }
01350
01351   /* Disable the UART DMA Tx request if enabled */
01352   if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01353   {
01354     /* Disable DMA Tx at UART level */
01355     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01356
01357     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
01358     if(huart->hdmatx != NULL)
01359     {
01360       /* UART Tx DMA Abort callback has already been initialised :
01361          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01362
01363       /* Abort DMA TX */
01364       if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
01365       {
01366         huart->hdmatx->XferAbortCallback = NULL;
01367       }
01368       else
01369       {
01370         AbortCplt = 0x00U;
01371       }
01372     }
01373   }
01374
01375   /* Disable the UART DMA Rx request if enabled */
01376   if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01377   {
01378     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01379
01380     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
01381     if(huart->hdmarx != NULL)
01382     {
01383       /* UART Rx DMA Abort callback has already been initialised :
01384          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01385
01386       /* Abort DMA RX */
01387       if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01388       {
01389         huart->hdmarx->XferAbortCallback = NULL;
01390         AbortCplt = 0x01U;
01391       }
01392       else
01393       {
01394         AbortCplt = 0x00U;
01395       }
01396     }
01397   }
01398
01399   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01400   if(AbortCplt == 0x01U)
01401   {
01402     /* Reset Tx and Rx transfer counters */
01403     huart->TxXferCount = 0x00U;
01404     huart->RxXferCount = 0x00U;
01405
01406     /* Reset ErrorCode */
01407     huart->ErrorCode = HAL_UART_ERROR_NONE;
01408
01409     /* Restore huart->gState and huart->RxState to Ready */
01410     huart->gState  = HAL_UART_STATE_READY;
01411     huart->RxState = HAL_UART_STATE_READY;
01412
01413     /* As no DMA to be aborted, call directly user Abort complete callback */
01414     HAL_UART_AbortCpltCallback(huart);
01415   }
01416
01417   return HAL_OK;
01418 }
01419
01420 /**
01421   * @brief  Abort ongoing Transmit transfer (Interrupt mode).
01422   * @param  huart UART handle.
01423   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01424   *         This procedure performs following operations :
01425   *           - Disable PPP Interrupts
01426   *           - Disable the DMA transfer in the peripheral register (if enabled)
01427   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01428   *           - Set handle State to READY
01429   *           - At abort completion, call user abort complete callback
01430   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01431   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01432   * @retval HAL status
01433 */
01434 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
01435 {
01436   /* Disable TXEIE and TCIE interrupts */
01437   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01438
01439   /* Disable the UART DMA Tx request if enabled */
01440   if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
01441   {
01442     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
01443
01444     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
01445     if(huart->hdmatx != NULL)
01446     {
01447       /* Set the UART DMA Abort callback :
01448          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01449       huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
01450
01451       /* Abort DMA TX */
01452       if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
01453       {
01454         /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
01455         huart->hdmatx->XferAbortCallback(huart->hdmatx);
01456       }
01457     }
01458     else
01459     {
01460       /* Reset Tx transfer counter */
01461       huart->TxXferCount = 0x00U;
01462
01463       /* Restore huart->gState to Ready */
01464       huart->gState = HAL_UART_STATE_READY;
01465
01466       /* As no DMA to be aborted, call directly user Abort complete callback */
01467       HAL_UART_AbortTransmitCpltCallback(huart);
01468     }
01469   }
01470   else
01471   {
01472     /* Reset Tx transfer counter */
01473     huart->TxXferCount = 0x00U;
01474
01475     /* Restore huart->gState to Ready */
01476     huart->gState = HAL_UART_STATE_READY;
01477
01478     /* As no DMA to be aborted, call directly user Abort complete callback */
01479     HAL_UART_AbortTransmitCpltCallback(huart);
01480   }
01481
01482   return HAL_OK;
01483 }
01484
01485 /**
01486   * @brief  Abort ongoing Receive transfer (Interrupt mode).
01487   * @param  huart UART handle.
01488   * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
01489   *         This procedure performs following operations :
01490   *           - Disable PPP Interrupts
01491   *           - Disable the DMA transfer in the peripheral register (if enabled)
01492   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01493   *           - Set handle State to READY
01494   *           - At abort completion, call user abort complete callback
01495   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01496   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01497   * @retval HAL status
01498 */
01499 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
01500 {
01501   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01502   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01503   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
01504
01505   /* Disable the UART DMA Rx request if enabled */
01506   if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01507   {
01508     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01509
01510     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
01511     if(huart->hdmarx != NULL)
01512     {
01513       /* Set the UART DMA Abort callback :
01514          will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
01515       huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
01516
01517       /* Abort DMA RX */
01518       if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01519       {
01520         /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
01521         huart->hdmarx->XferAbortCallback(huart->hdmarx);
01522       }
01523     }
01524     else
01525     {
01526       /* Reset Rx transfer counter */
01527       huart->RxXferCount = 0x00U;
01528
01529       /* Restore huart->RxState to Ready */
01530       huart->RxState = HAL_UART_STATE_READY;
01531
01532       /* As no DMA to be aborted, call directly user Abort complete callback */
01533       HAL_UART_AbortReceiveCpltCallback(huart);
01534     }
01535   }
01536   else
01537   {
01538     /* Reset Rx transfer counter */
01539     huart->RxXferCount = 0x00U;
01540
01541     /* Restore huart->RxState to Ready */
01542     huart->RxState = HAL_UART_STATE_READY;
01543
01544     /* As no DMA to be aborted, call directly user Abort complete callback */
01545     HAL_UART_AbortReceiveCpltCallback(huart);
01546   }
01547
01548   return HAL_OK;
01549 }
01550
01551 /**
01552   * @brief  This function handles UART interrupt request.
01553   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01554   *                the configuration information for the specified UART module.
01555   * @retval None
01556   */
01557 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
01558 {
01559    uint32_t isrflags   = READ_REG(huart->Instance->SR);
01560    uint32_t cr1its     = READ_REG(huart->Instance->CR1);
01561    uint32_t cr3its     = READ_REG(huart->Instance->CR3);
01562    uint32_t errorflags = 0x00U;
01563    uint32_t dmarequest = 0x00U;
01564
01565   /* If no error occurs */
01566   errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
01567   if(errorflags == RESET)
01568   {
01569     /* UART in mode Receiver -------------------------------------------------*/
01570     if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01571     {
01572       UART_Receive_IT(huart);
01573       return;
01574     }
01575   }
01576
01577   /* If some errors occur */
01578   if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
01579   {
01580     /* UART parity error interrupt occurred ----------------------------------*/
01581     if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01582     {
01583       huart->ErrorCode |= HAL_UART_ERROR_PE;
01584     }
01585
01586     /* UART noise error interrupt occurred -----------------------------------*/
01587     if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01588     {
01589       huart->ErrorCode |= HAL_UART_ERROR_NE;
01590     }
01591
01592     /* UART frame error interrupt occurred -----------------------------------*/
01593     if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01594     {
01595       huart->ErrorCode |= HAL_UART_ERROR_FE;
01596     }
01597
01598     /* UART Over-Run interrupt occurred --------------------------------------*/
01599     if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01600     {
01601       huart->ErrorCode |= HAL_UART_ERROR_ORE;
01602     }
01603
01604     /* Call UART Error Call back function if need be --------------------------*/
01605     if(huart->ErrorCode != HAL_UART_ERROR_NONE)
01606     {
01607       /* UART in mode Receiver -----------------------------------------------*/
01608       if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01609       {
01610         UART_Receive_IT(huart);
01611       }
01612
01613       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01614          consider error as blocking */
01615       dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
01616       if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
01617       {
01618         /* Blocking error : transfer is aborted
01619            Set the UART state ready to be able to start again the process,
01620            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01621         UART_EndRxTransfer(huart);
01622
01623         /* Disable the UART DMA Rx request if enabled */
01624         if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
01625         {
01626           CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
01627
01628           /* Abort the UART DMA Rx channel */
01629           if(huart->hdmarx != NULL)
01630           {
01631             /* Set the UART DMA Abort callback :
01632                will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
01633             huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
01634             if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
01635             {
01636               /* Call Directly XferAbortCallback function in case of error */
01637               huart->hdmarx->XferAbortCallback(huart->hdmarx);
01638             }
01639           }
01640           else
01641           {
01642             /* Call user error callback */
01643             HAL_UART_ErrorCallback(huart);
01644           }
01645         }
01646         else
01647         {
01648           /* Call user error callback */
01649           HAL_UART_ErrorCallback(huart);
01650         }
01651       }
01652       else
01653       {
01654         /* Non Blocking error : transfer could go on.
01655            Error is notified to user through user error callback */
01656         HAL_UART_ErrorCallback(huart);
01657         huart->ErrorCode = HAL_UART_ERROR_NONE;
01658       }
01659     }
01660     return;
01661   } /* End if some error occurs */
01662
01663   /* UART in mode Transmitter ------------------------------------------------*/
01664   if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01665   {
01666     UART_Transmit_IT(huart);
01667     return;
01668   }
01669
01670   /* UART in mode Transmitter end --------------------------------------------*/
01671   if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01672   {
01673     UART_EndTransmit_IT(huart);
01674     return;
01675   }
01676 }
01677
01678 /**
01679   * @brief  Tx Transfer completed callbacks.
01680   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01681   *                the configuration information for the specified UART module.
01682   * @retval None
01683   */
01684  __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
01685 {
01686   /* Prevent unused argument(s) compilation warning */
01687   UNUSED(huart);
01688   /* NOTE: This function Should not be modified, when the callback is needed,
01689            the HAL_UART_TxCpltCallback could be implemented in the user file
01690    */
01691 }
01692
01693 /**
01694   * @brief  Tx Half Transfer completed callbacks.
01695   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01696   *                the configuration information for the specified UART module.
01697   * @retval None
01698   */
01699  __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
01700 {
01701   /* Prevent unused argument(s) compilation warning */
01702   UNUSED(huart);
01703   /* NOTE: This function Should not be modified, when the callback is needed,
01704            the HAL_UART_TxHalfCpltCallback could be implemented in the user file
01705    */
01706 }
01707
01708 /**
01709   * @brief  Rx Transfer completed callbacks.
01710   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01711   *                the configuration information for the specified UART module.
01712   * @retval None
01713   */
01714 __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
01715 {
01716   /* Prevent unused argument(s) compilation warning */
01717   UNUSED(huart);
01718   /* NOTE: This function Should not be modified, when the callback is needed,
01719            the HAL_UART_RxCpltCallback could be implemented in the user file
01720    */
01721 }
01722
01723 /**
01724   * @brief  Rx Half Transfer completed callbacks.
01725   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01726   *                the configuration information for the specified UART module.
01727   * @retval None
01728   */
01729 __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
01730 {
01731   /* Prevent unused argument(s) compilation warning */
01732   UNUSED(huart);
01733   /* NOTE: This function Should not be modified, when the callback is needed,
01734            the HAL_UART_RxHalfCpltCallback could be implemented in the user file
01735    */
01736 }
01737
01738 /**
01739   * @brief  UART error callbacks.
01740   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01741   *                the configuration information for the specified UART module.
01742   * @retval None
01743   */
01744  __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
01745 {
01746   /* Prevent unused argument(s) compilation warning */
01747   UNUSED(huart);
01748   /* NOTE: This function Should not be modified, when the callback is needed,
01749            the HAL_UART_ErrorCallback could be implemented in the user file
01750    */
01751 }
01752
01753 /**
01754   * @brief  UART Abort Complete callback.
01755   * @param  huart UART handle.
01756   * @retval None
01757   */
01758 __weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
01759 {
01760   /* Prevent unused argument(s) compilation warning */
01761   UNUSED(huart);
01762
01763   /* NOTE : This function should not be modified, when the callback is needed,
01764             the HAL_UART_AbortCpltCallback can be implemented in the user file.
01765    */
01766 }
01767 /**
01768   * @brief  UART Abort Complete callback.
01769   * @param  huart UART handle.
01770   * @retval None
01771   */
01772 __weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
01773 {
01774   /* Prevent unused argument(s) compilation warning */
01775   UNUSED(huart);
01776
01777   /* NOTE : This function should not be modified, when the callback is needed,
01778             the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
01779    */
01780 }
01781
01782 /**
01783   * @brief  UART Abort Receive Complete callback.
01784   * @param  huart UART handle.
01785   * @retval None
01786   */
01787 __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
01788 {
01789   /* Prevent unused argument(s) compilation warning */
01790   UNUSED(huart);
01791
01792   /* NOTE : This function should not be modified, when the callback is needed,
01793             the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
01794    */
01795 }
01796
01797 /**
01798   * @}
01799   */
01800
01801 /** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
01802   *  @brief   UART control functions
01803   *
01804 @verbatim
01805   ==============================================================================
01806                       ##### Peripheral Control functions #####
01807   ==============================================================================
01808   [..]
01809     This subsection provides a set of functions allowing to control the UART:
01810     (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
01811     (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
01812     (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
01813     (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
01814     (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode
01815
01816 @endverbatim
01817   * @{
01818   */
01819
01820 /**
01821   * @brief  Transmits break characters.
01822   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01823   *                the configuration information for the specified UART module.
01824   * @retval HAL status
01825   */
01826 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
01827 {
01828   /* Check the parameters */
01829   assert_param(IS_UART_INSTANCE(huart->Instance));
01830
01831   /* Process Locked */
01832   __HAL_LOCK(huart);
01833
01834   huart->gState = HAL_UART_STATE_BUSY;
01835
01836   /* Send break characters */
01837   SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
01838
01839   huart->gState = HAL_UART_STATE_READY;
01840
01841   /* Process Unlocked */
01842   __HAL_UNLOCK(huart);
01843
01844   return HAL_OK;
01845 }
01846
01847 /**
01848   * @brief  Enters the UART in mute mode.
01849   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01850   *                the configuration information for the specified UART module.
01851   * @retval HAL status
01852   */
01853 HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
01854 {
01855   /* Check the parameters */
01856   assert_param(IS_UART_INSTANCE(huart->Instance));
01857
01858   /* Process Locked */
01859   __HAL_LOCK(huart);
01860
01861   huart->gState = HAL_UART_STATE_BUSY;
01862
01863   /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
01864   SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
01865
01866   huart->gState = HAL_UART_STATE_READY;
01867
01868   /* Process Unlocked */
01869   __HAL_UNLOCK(huart);
01870
01871   return HAL_OK;
01872 }
01873
01874 /**
01875   * @brief  Exits the UART mute mode: wake up software.
01876   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01877   *                the configuration information for the specified UART module.
01878   * @retval HAL status
01879   */
01880 HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
01881 {
01882   /* Check the parameters */
01883   assert_param(IS_UART_INSTANCE(huart->Instance));
01884
01885   /* Process Locked */
01886   __HAL_LOCK(huart);
01887
01888   huart->gState = HAL_UART_STATE_BUSY;
01889
01890   /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
01891   CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
01892
01893   huart->gState = HAL_UART_STATE_READY;
01894
01895   /* Process Unlocked */
01896   __HAL_UNLOCK(huart);
01897
01898   return HAL_OK;
01899 }
01900
01901 /**
01902   * @brief  Enables the UART transmitter and disables the UART receiver.
01903   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01904   *                the configuration information for the specified UART module.
01905   * @retval HAL status
01906   */
01907 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
01908 {
01909   uint32_t tmpreg = 0x00U;
01910
01911   /* Process Locked */
01912   __HAL_LOCK(huart);
01913
01914   huart->gState = HAL_UART_STATE_BUSY;
01915
01916   /*-------------------------- USART CR1 Configuration -----------------------*/
01917   tmpreg = huart->Instance->CR1;
01918
01919   /* Clear TE and RE bits */
01920   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
01921
01922   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
01923   tmpreg |= (uint32_t)USART_CR1_TE;
01924
01925   /* Write to USART CR1 */
01926   WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
01927
01928   huart->gState = HAL_UART_STATE_READY;
01929
01930   /* Process Unlocked */
01931   __HAL_UNLOCK(huart);
01932
01933   return HAL_OK;
01934 }
01935
01936 /**
01937   * @brief  Enables the UART receiver and disables the UART transmitter.
01938   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01939   *                the configuration information for the specified UART module.
01940   * @retval HAL status
01941   */
01942 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
01943 {
01944   uint32_t tmpreg = 0x00U;
01945
01946   /* Process Locked */
01947   __HAL_LOCK(huart);
01948
01949   huart->gState = HAL_UART_STATE_BUSY;
01950
01951   /*-------------------------- USART CR1 Configuration -----------------------*/
01952   tmpreg = huart->Instance->CR1;
01953
01954   /* Clear TE and RE bits */
01955   tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
01956
01957   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
01958   tmpreg |= (uint32_t)USART_CR1_RE;
01959
01960   /* Write to USART CR1 */
01961   WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
01962
01963   huart->gState = HAL_UART_STATE_READY;
01964
01965   /* Process Unlocked */
01966   __HAL_UNLOCK(huart);
01967
01968   return HAL_OK;
01969 }
01970
01971 /**
01972   * @}
01973   */
01974
01975 /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
01976   *  @brief   UART State and Errors functions
01977   *
01978 @verbatim
01979   ==============================================================================
01980                  ##### Peripheral State and Errors functions #####
01981   ==============================================================================
01982  [..]
01983    This subsection provides a set of functions allowing to return the State of
01984    UART communication process, return Peripheral Errors occurred during communication
01985    process
01986    (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
01987    (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
01988
01989 @endverbatim
01990   * @{
01991   */
01992
01993 /**
01994   * @brief  Returns the UART state.
01995   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
01996   *                the configuration information for the specified UART module.
01997   * @retval HAL state
01998   */
01999 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
02000 {
02001   uint32_t temp1= 0x00U, temp2 = 0x00U;
02002   temp1 = huart->gState;
02003   temp2 = huart->RxState;
02004
02005   return (HAL_UART_StateTypeDef)(temp1 | temp2);
02006 }
02007
02008 /**
02009   * @brief  Return the UART error code
02010   * @param  huart : pointer to a UART_HandleTypeDef structure that contains
02011   *              the configuration information for the specified UART.
02012   * @retval UART Error Code
02013   */
02014 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
02015 {
02016   return huart->ErrorCode;
02017 }
02018
02019 /**
02020   * @}
02021   */
02022
02023 /**
02024   * @brief  DMA UART transmit process complete callback.
02025   * @param  hdma: DMA handle
02026   * @retval None
02027   */
02028 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
02029 {
02030   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02031   /* DMA Normal mode*/
02032   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
02033   {
02034     huart->TxXferCount = 0U;
02035
02036     /* Disable the DMA transfer for transmit request by setting the DMAT bit
02037        in the UART CR3 register */
02038     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
02039
02040     /* Enable the UART Transmit Complete Interrupt */
02041     SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
02042
02043   }
02044   /* DMA Circular mode */
02045   else
02046   {
02047     HAL_UART_TxCpltCallback(huart);
02048   }
02049 }
02050
02051 /**
02052   * @brief DMA UART transmit process half complete callback
02053   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02054   *                the configuration information for the specified DMA module.
02055   * @retval None
02056   */
02057 static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
02058 {
02059   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02060
02061   HAL_UART_TxHalfCpltCallback(huart);
02062 }
02063
02064 /**
02065   * @brief  DMA UART receive process complete callback.
02066   * @param  hdma: DMA handle
02067   * @retval None
02068   */
02069 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
02070 {
02071   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02072   /* DMA Normal mode*/
02073   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
02074   {
02075     huart->RxXferCount = 0U;
02076
02077     /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02078     CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
02079     CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02080
02081     /* Disable the DMA transfer for the receiver request by setting the DMAR bit
02082        in the UART CR3 register */
02083     CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
02084
02085     /* At end of Rx process, restore huart->RxState to Ready */
02086     huart->RxState = HAL_UART_STATE_READY;
02087   }
02088   HAL_UART_RxCpltCallback(huart);
02089 }
02090
02091 /**
02092   * @brief DMA UART receive process half complete callback
02093   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
02094   *                the configuration information for the specified DMA module.
02095   * @retval None
02096   */
02097 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
02098 {
02099   UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
02100   HAL_UART_RxHalfCpltCallback(huart);
02101 }
02102
02103 /**
02104   * @brief  DMA UART communication error callback.
02105   * @param  hdma: DMA handle
02106   * @retval None
02107   */
02108 static void UART_DMAError(DMA_HandleTypeDef *hdma)
02109 {
02110   uint32_t dmarequest = 0x00U;
02111   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02112
02113   /* Stop UART DMA Tx request if ongoing */
02114   dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
02115   if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
02116   {
02117     huart->TxXferCount = 0U;
02118     UART_EndTxTransfer(huart);
02119   }
02120
02121   /* Stop UART DMA Rx request if ongoing */
02122   dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
02123   if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
02124   {
02125     huart->RxXferCount = 0U;
02126     UART_EndRxTransfer(huart);
02127   }
02128
02129   huart->ErrorCode |= HAL_UART_ERROR_DMA;
02130   HAL_UART_ErrorCallback(huart);
02131 }
02132
02133 /**
02134   * @brief  This function handles UART Communication Timeout.
02135   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
02136   *                the configuration information for the specified UART module.
02137   * @param  Flag: specifies the UART flag to check.
02138   * @param  Status: The new Flag status (SET or RESET).
02139   * @param  Tickstart Tick start value
02140   * @param  Timeout: Timeout duration
02141   * @retval HAL status
02142   */
02143 static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
02144 {
02145   /* Wait until flag is set */
02146   while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
02147   {
02148     /* Check for the Timeout */
02149     if(Timeout != HAL_MAX_DELAY)
02150     {
02151       if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
02152       {
02153         /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
02154         CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
02155         CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02156
02157         huart->gState  = HAL_UART_STATE_READY;
02158         huart->RxState = HAL_UART_STATE_READY;
02159
02160         /* Process Unlocked */
02161         __HAL_UNLOCK(huart);
02162
02163         return HAL_TIMEOUT;
02164       }
02165     }
02166   }
02167
02168   return HAL_OK;
02169 }
02170
02171 /**
02172   * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
02173   * @param  huart: UART handle.
02174   * @retval None
02175   */
02176 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
02177 {
02178   /* Disable TXEIE and TCIE interrupts */
02179   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
02180
02181   /* At end of Tx process, restore huart->gState to Ready */
02182   huart->gState = HAL_UART_STATE_READY;
02183 }
02184
02185 /**
02186   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
02187   * @param  huart: UART handle.
02188   * @retval None
02189   */
02190 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
02191 {
02192   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
02193   CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
02194   CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
02195
02196   /* At end of Rx process, restore huart->RxState to Ready */
02197   huart->RxState = HAL_UART_STATE_READY;
02198 }
02199
02200 /**
02201   * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
02202   *         (To be called at end of DMA Abort procedure following error occurrence).
02203   * @param  hdma DMA handle.
02204   * @retval None
02205   */
02206 static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
02207 {
02208   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02209   huart->RxXferCount = 0x00U;
02210   huart->TxXferCount = 0x00U;
02211
02212   HAL_UART_ErrorCallback(huart);
02213 }
02214
02215 /**
02216   * @brief  DMA UART Tx communication abort callback, when initiated by user
02217   *         (To be called at end of DMA Tx Abort procedure following user abort request).
02218   * @note   When this callback is executed, User Abort complete call back is called only if no
02219   *         Abort still ongoing for Rx DMA Handle.
02220   * @param  hdma DMA handle.
02221   * @retval None
02222   */
02223 static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
02224 {
02225   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02226
02227   huart->hdmatx->XferAbortCallback = NULL;
02228
02229   /* Check if an Abort process is still ongoing */
02230   if(huart->hdmarx != NULL)
02231   {
02232     if(huart->hdmarx->XferAbortCallback != NULL)
02233     {
02234       return;
02235     }
02236   }
02237
02238   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02239   huart->TxXferCount = 0x00U;
02240   huart->RxXferCount = 0x00U;
02241
02242   /* Reset ErrorCode */
02243   huart->ErrorCode = HAL_UART_ERROR_NONE;
02244
02245   /* Restore huart->gState and huart->RxState to Ready */
02246   huart->gState  = HAL_UART_STATE_READY;
02247   huart->RxState = HAL_UART_STATE_READY;
02248
02249   /* Call user Abort complete callback */
02250   HAL_UART_AbortCpltCallback(huart);
02251 }
02252
02253 /**
02254   * @brief  DMA UART Rx communication abort callback, when initiated by user
02255   *         (To be called at end of DMA Rx Abort procedure following user abort request).
02256   * @note   When this callback is executed, User Abort complete call back is called only if no
02257   *         Abort still ongoing for Tx DMA Handle.
02258   * @param  hdma DMA handle.
02259   * @retval None
02260   */
02261 static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
02262 {
02263   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02264
02265   huart->hdmarx->XferAbortCallback = NULL;
02266
02267   /* Check if an Abort process is still ongoing */
02268   if(huart->hdmatx != NULL)
02269   {
02270     if(huart->hdmatx->XferAbortCallback != NULL)
02271     {
02272       return;
02273     }
02274   }
02275
02276   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
02277   huart->TxXferCount = 0x00U;
02278   huart->RxXferCount = 0x00U;
02279
02280   /* Reset ErrorCode */
02281   huart->ErrorCode = HAL_UART_ERROR_NONE;
02282
02283   /* Restore huart->gState and huart->RxState to Ready */
02284   huart->gState  = HAL_UART_STATE_READY;
02285   huart->RxState = HAL_UART_STATE_READY;
02286
02287   /* Call user Abort complete callback */
02288   HAL_UART_AbortCpltCallback(huart);
02289 }
02290
02291 /**
02292   * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
02293   *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
02294   *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
02295   *         and leads to user Tx Abort Complete callback execution).
02296   * @param  hdma DMA handle.
02297   * @retval None
02298   */
02299 static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02300 {
02301   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02302
02303   huart->TxXferCount = 0x00U;
02304
02305   /* Restore huart->gState to Ready */
02306   huart->gState = HAL_UART_STATE_READY;
02307
02308   /* Call user Abort complete callback */
02309   HAL_UART_AbortTransmitCpltCallback(huart);
02310 }
02311
02312 /**
02313   * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
02314   *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
02315   *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
02316   *         and leads to user Rx Abort Complete callback execution).
02317   * @param  hdma DMA handle.
02318   * @retval None
02319   */
02320 static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
02321 {
02322   UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02323
02324   huart->RxXferCount = 0x00U;
02325
02326   /* Restore huart->RxState to Ready */
02327   huart->RxState = HAL_UART_STATE_READY;
02328
02329   /* Call user Abort complete callback */
02330   HAL_UART_AbortReceiveCpltCallback(huart);
02331 }
02332
02333 /**
02334   * @brief  Sends an amount of data in non blocking mode.
02335   * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
02336   *                the configuration information for the specified UART module.
02337   * @retval HAL status
02338   */
02339 static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
02340 {
02341   uint16_t* tmp;
02342
02343   /* Check that a Tx process is ongoing */
02344   if(huart->gState == HAL_UART_STATE_BUSY_TX)
02345   {
02346     if(huart->Init.WordLength == UART_WORDLENGTH_9B)
02347     {
02348       tmp = (uint16_t*) huart->pTxBuffPtr;
02349       huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
02350       if(huart->Init.Parity == UART_PARITY_NONE)
02351       {
02352         huart->pTxBuffPtr += 2U;
02353       }
02354       else
02355       {
02356         huart->pTxBuffPtr += 1U;
02357       }
02358     }
02359     else
02360     {
02361       huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
02362     }
02363
02364     if(--huart->TxXferCount == 0U)
02365     {
02366       /* Disable the UART Transmit Complete Interrupt */
02367       __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
02368
02369       /* Enable the UART Transmit Complete Interrupt */
02370       __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
02371     }
02372     return HAL_OK;
02373   }
02374   else
02375   {
02376     return HAL_BUSY;
02377   }
02378 }
02379
02380 /**
02381   * @brief  Wraps up transmission in non blocking mode.
02382   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
02383   *                the configuration information for the specified UART module.
02384   * @retval HAL status
02385   */
02386 static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
02387 {
02388   /* Disable the UART Transmit Complete Interrupt */
02389   __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
02390
02391   /* Tx process is ended, restore huart->gState to Ready */
02392   huart->gState = HAL_UART_STATE_READY;
02393   HAL_UART_TxCpltCallback(huart);
02394
02395   return HAL_OK;
02396 }
02397
02398 /**
02399   * @brief  Receives an amount of data in non blocking mode
02400   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
02401   *                the configuration information for the specified UART module.
02402   * @retval HAL status
02403   */
02404 static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
02405 {
02406   uint16_t* tmp;
02407
02408   /* Check that a Rx process is ongoing */
02409   if(huart->RxState == HAL_UART_STATE_BUSY_RX)
02410   {
02411     if(huart->Init.WordLength == UART_WORDLENGTH_9B)
02412     {
02413       tmp = (uint16_t*) huart->pRxBuffPtr;
02414       if(huart->Init.Parity == UART_PARITY_NONE)
02415       {
02416         *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
02417         huart->pRxBuffPtr += 2U;
02418       }
02419       else
02420       {
02421         *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
02422         huart->pRxBuffPtr += 1U;
02423       }
02424     }
02425     else
02426     {
02427       if(huart->Init.Parity == UART_PARITY_NONE)
02428       {
02429         *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
02430       }
02431       else
02432       {
02433         *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
02434       }
02435     }
02436
02437     if(--huart->RxXferCount == 0U)
02438     {
02439       /* Disable the IRDA Data Register not empty Interrupt */
02440       __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
02441
02442       /* Disable the UART Parity Error Interrupt */
02443       __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
02444         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
02445         __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
02446
02447       /* Rx process is completed, restore huart->RxState to Ready */
02448       huart->RxState = HAL_UART_STATE_READY;
02449
02450       HAL_UART_RxCpltCallback(huart);
02451
02452       return HAL_OK;
02453     }
02454     return HAL_OK;
02455   }
02456   else
02457   {
02458     return HAL_BUSY;
02459   }
02460 }
02461
02462 /**
02463   * @brief  Configures the UART peripheral.
02464   * @param  huart: pointer to a UART_HandleTypeDef structure that contains
02465   *                the configuration information for the specified UART module.
02466   * @retval None
02467   */
02468 static void UART_SetConfig(UART_HandleTypeDef *huart)
02469 {
02470   uint32_t tmpreg = 0x00U;
02471
02472   /* Check the parameters */
02473   assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
02474   assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
02475   assert_param(IS_UART_PARITY(huart->Init.Parity));
02476   assert_param(IS_UART_MODE(huart->Init.Mode));
02477
02478   /*------- UART-associated USART registers setting : CR2 Configuration ------*/
02479   /* Configure the UART Stop Bits: Set STOP[13:12] bits according
02480    * to huart->Init.StopBits value */
02481   MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
02482
02483   /*------- UART-associated USART registers setting : CR1 Configuration ------*/
02484   /* Configure the UART Word Length, Parity and mode:
02485      Set the M bits according to huart->Init.WordLength value
02486      Set PCE and PS bits according to huart->Init.Parity value
02487      Set TE and RE bits according to huart->Init.Mode value
02488      Set OVER8 bit according to huart->Init.OverSampling value */
02489
02490 #if defined(USART_CR1_OVER8)
02491   tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
02492   MODIFY_REG(huart->Instance->CR1,
02493              (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
02494              tmpreg);
02495 #else
02496   tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
02497   MODIFY_REG(huart->Instance->CR1,
02498              (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
02499              tmpreg);
02500 #endif /* USART_CR1_OVER8 */
02501
02502   /*------- UART-associated USART registers setting : CR3 Configuration ------*/
02503   /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
02504   MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
02505
02506 #if defined(USART_CR1_OVER8)
02507   /* Check the Over Sampling */
02508   if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
02509   {
02510     /*-------------------------- USART BRR Configuration ---------------------*/
02511     if(huart->Instance == USART1)
02512     {
02513       huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
02514     }
02515     else
02516     {
02517       huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
02518     }
02519   }
02520   else
02521   {
02522     /*-------------------------- USART BRR Configuration ---------------------*/
02523     if(huart->Instance == USART1)
02524     {
02525       huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
02526     }
02527     else
02528     {
02529       huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
02530     }
02531   }
02532 #else
02533   /*-------------------------- USART BRR Configuration ---------------------*/
02534   if(huart->Instance == USART1)
02535   {
02536     huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
02537   }
02538   else
02539   {
02540     huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
02541   }
02542 #endif /* USART_CR1_OVER8 */
02543 }
02544
02545 /**
02546   * @}
02547   */
02548
02549 #endif /* HAL_UART_MODULE_ENABLED */
02550 /**
02551   * @}
02552   */
02553
02554 /**
02555   * @}
02556   */
02557
02558 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_uart.h Source File

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stm32f1xx_hal_uart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_uart.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of UART HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_UART_H
00040 #define __STM32F1xx_HAL_UART_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup UART
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup UART_Exported_Types UART Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief UART Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
00068                                            The baud rate is computed using the following formula:
00069                                            - IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate)))
00070                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
00071
00072   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00073                                            This parameter can be a value of @ref UART_Word_Length */
00074
00075   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00076                                            This parameter can be a value of @ref UART_Stop_Bits */
00077
00078   uint32_t Parity;                    /*!< Specifies the parity mode.
00079                                            This parameter can be a value of @ref UART_Parity
00080                                            @note When parity is enabled, the computed parity is inserted
00081                                                  at the MSB position of the transmitted data (9th bit when
00082                                                  the word length is set to 9 data bits; 8th bit when the
00083                                                  word length is set to 8 data bits). */
00084
00085   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00086                                            This parameter can be a value of @ref UART_Mode */
00087
00088   uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00089                                            This parameter can be a value of @ref UART_Hardware_Flow_Control */
00090
00091   uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
00092                                            This parameter can be a value of @ref UART_Over_Sampling. This feature is only available
00093                                            on STM32F100xx family, so OverSampling parameter should always be set to 16. */
00094 }UART_InitTypeDef;
00095
00096 /**
00097   * @brief HAL UART State structures definition
00098   * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
00099   *        - gState contains UART state information related to global Handle management
00100   *          and also information related to Tx operations.
00101   *          gState value coding follow below described bitmap :
00102   *          b7-b6  Error information
00103   *             00 : No Error
00104   *             01 : (Not Used)
00105   *             10 : Timeout
00106   *             11 : Error
00107   *          b5     IP initilisation status
00108   *             0  : Reset (IP not initialized)
00109   *             1  : Init done (IP not initialized. HAL UART Init function already called)
00110   *          b4-b3  (not used)
00111   *             xx : Should be set to 00
00112   *          b2     Intrinsic process state
00113   *             0  : Ready
00114   *             1  : Busy (IP busy with some configuration or internal operations)
00115   *          b1     (not used)
00116   *             x  : Should be set to 0
00117   *          b0     Tx state
00118   *             0  : Ready (no Tx operation ongoing)
00119   *             1  : Busy (Tx operation ongoing)
00120   *        - RxState contains information related to Rx operations.
00121   *          RxState value coding follow below described bitmap :
00122   *          b7-b6  (not used)
00123   *             xx : Should be set to 00
00124   *          b5     IP initilisation status
00125   *             0  : Reset (IP not initialized)
00126   *             1  : Init done (IP not initialized)
00127   *          b4-b2  (not used)
00128   *            xxx : Should be set to 000
00129   *          b1     Rx state
00130   *             0  : Ready (no Rx operation ongoing)
00131   *             1  : Busy (Rx operation ongoing)
00132   *          b0     (not used)
00133   *             x  : Should be set to 0.
00134   */
00135 typedef enum
00136 {
00137   HAL_UART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
00138                                                    Value is allowed for gState and RxState */
00139   HAL_UART_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
00140                                                    Value is allowed for gState and RxState */
00141   HAL_UART_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
00142                                                    Value is allowed for gState only */
00143   HAL_UART_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
00144                                                    Value is allowed for gState only */
00145   HAL_UART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
00146                                                    Value is allowed for RxState only */
00147   HAL_UART_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
00148                                                    Not to be used for neither gState nor RxState.
00149                                                    Value is result of combination (Or) between gState and RxState values */
00150   HAL_UART_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
00151                                                    Value is allowed for gState only */
00152   HAL_UART_STATE_ERROR             = 0xE0U     /*!< Error
00153                                                    Value is allowed for gState only */
00154 }HAL_UART_StateTypeDef;
00155
00156 /**
00157   * @brief  UART handle Structure definition
00158   */
00159 typedef struct
00160 {
00161   USART_TypeDef                 *Instance;        /*!< UART registers base address        */
00162
00163   UART_InitTypeDef              Init;             /*!< UART communication parameters      */
00164
00165   uint8_t                       *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
00166
00167   uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */
00168
00169   __IO uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
00170
00171   uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
00172
00173   uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */
00174
00175   __IO uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
00176
00177   DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */
00178
00179   DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */
00180
00181   HAL_LockTypeDef               Lock;             /*!< Locking object                     */
00182
00183   __IO HAL_UART_StateTypeDef    gState;           /*!< UART state information related to global Handle management
00184                                                        and also related to Tx operations.
00185                                                        This parameter can be a value of @ref HAL_UART_StateTypeDef */
00186
00187   __IO HAL_UART_StateTypeDef    RxState;          /*!< UART state information related to Rx operations.
00188                                                        This parameter can be a value of @ref HAL_UART_StateTypeDef */
00189
00190   __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */
00191 }UART_HandleTypeDef;
00192
00193 /**
00194   * @}
00195   */
00196
00197 /* Exported constants --------------------------------------------------------*/
00198 /** @defgroup UART_Exported_Constants UART Exported constants
00199   * @{
00200   */
00201
00202 /** @defgroup UART_Error_Code UART Error Code
00203   * @{
00204   */
00205 #define HAL_UART_ERROR_NONE         0x00000000U   /*!< No error            */
00206 #define HAL_UART_ERROR_PE           0x00000001U   /*!< Parity error        */
00207 #define HAL_UART_ERROR_NE           0x00000002U   /*!< Noise error         */
00208 #define HAL_UART_ERROR_FE           0x00000004U   /*!< Frame error         */
00209 #define HAL_UART_ERROR_ORE          0x00000008U   /*!< Overrun error       */
00210 #define HAL_UART_ERROR_DMA          0x00000010U   /*!< DMA transfer error  */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup UART_Word_Length UART Word Length
00216   * @{
00217   */
00218 #define UART_WORDLENGTH_8B                  0x00000000U
00219 #define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup UART_Stop_Bits  UART Number of Stop Bits
00225   * @{
00226   */
00227 #define UART_STOPBITS_1                     0x00000000U
00228 #define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
00229 /**
00230   * @}
00231   */
00232
00233 /** @defgroup UART_Parity  UART Parity
00234   * @{
00235   */
00236 #define UART_PARITY_NONE                    0x00000000U
00237 #define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00238 #define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
00244   * @{
00245   */
00246 #define UART_HWCONTROL_NONE                  0x00000000U
00247 #define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
00248 #define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
00249 #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup UART_Mode UART Transfer Mode
00255   * @{
00256   */
00257 #define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
00258 #define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
00259 #define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00260 /**
00261   * @}
00262   */
00263
00264 /** @defgroup UART_State  UART State
00265   * @{
00266   */
00267 #define UART_STATE_DISABLE                  0x00000000U
00268 #define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
00269 /**
00270   * @}
00271   */
00272
00273
00274 /** @defgroup UART_Over_Sampling UART Over Sampling
00275   * @{
00276   */
00277 #define UART_OVERSAMPLING_16                    0x00000000U
00278 #if defined(USART_CR1_OVER8)
00279 #define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
00280 #endif /* USART_CR1_OVER8 */
00281 /**
00282   * @}
00283   */
00284
00285
00286 /** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
00287   * @{
00288   */
00289 #define UART_LINBREAKDETECTLENGTH_10B      0x00000000U
00290 #define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)
00291 /**
00292   * @}
00293   */
00294 /** @defgroup UART_WakeUp_functions  UART Wakeup Functions
00295   * @{
00296   */
00297 #define UART_WAKEUPMETHOD_IDLELINE                0x00000000U
00298 #define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)USART_CR1_WAKE)
00299 /**
00300   * @}
00301   */
00302
00303 /** @defgroup UART_Flags   UART FLags
00304   *        Elements values convention: 0xXXXX
00305   *           - 0xXXXX  : Flag mask in the SR register
00306   * @{
00307   */
00308 #define UART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)
00309 #define UART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)
00310 #define UART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
00311 #define UART_FLAG_TC                        ((uint32_t)USART_SR_TC)
00312 #define UART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
00313 #define UART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
00314 #define UART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
00315 #define UART_FLAG_NE                        ((uint32_t)USART_SR_NE)
00316 #define UART_FLAG_FE                        ((uint32_t)USART_SR_FE)
00317 #define UART_FLAG_PE                        ((uint32_t)USART_SR_PE)
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup UART_Interrupt_definition  UART Interrupt Definitions
00323   *        Elements values convention: 0xY000XXXX
00324   *           - XXXX  : Interrupt mask (16 bits) in the Y register
00325   *           - Y  : Interrupt source register (2bits)
00326   *                   - 01: CR1 register
00327   *                   - 10: CR2 register
00328   *                   - 11: CR3 register
00329   * @{
00330   */
00331
00332 #define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
00333 #define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
00334 #define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
00335 #define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
00336 #define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
00337
00338 #define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
00339
00340 #define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
00341 #define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
00342 /**
00343   * @}
00344   */
00345
00346 /**
00347   * @}
00348   */
00349
00350 /* Exported macro ------------------------------------------------------------*/
00351 /** @defgroup UART_Exported_Macros UART Exported Macros
00352   * @{
00353   */
00354
00355 /** @brief Reset UART handle gstate & RxState
00356   * @param  __HANDLE__: specifies the UART Handle.
00357   *         UART Handle selects the USARTx or UARTy peripheral
00358   *         (USART,UART availability and x,y values depending on device).
00359   */
00360 #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
00361                                                        (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
00362                                                        (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
00363                                                      } while(0U)
00364
00365 /** @brief  Flushs the UART DR register
00366   * @param  __HANDLE__: specifies the UART Handle.
00367   *         UART Handle selects the USARTx or UARTy peripheral
00368   *         (USART,UART availability and x,y values depending on device).
00369   */
00370 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
00371
00372 /** @brief  Checks whether the specified UART flag is set or not.
00373   * @param  __HANDLE__: specifies the UART Handle.
00374   *         This parameter can be UARTx where x: 1, 2, 3, 4 or 5 to select the USART or
00375   *         UART peripheral.
00376   * @param  __FLAG__: specifies the flag to check.
00377   *        This parameter can be one of the following values:
00378   *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
00379   *            @arg UART_FLAG_LBD:  LIN Break detection flag
00380   *            @arg UART_FLAG_TXE:  Transmit data register empty flag
00381   *            @arg UART_FLAG_TC:   Transmission Complete flag
00382   *            @arg UART_FLAG_RXNE: Receive data register not empty flag
00383   *            @arg UART_FLAG_IDLE: Idle Line detection flag
00384   *            @arg UART_FLAG_ORE:  OverRun Error flag
00385   *            @arg UART_FLAG_NE:   Noise Error flag
00386   *            @arg UART_FLAG_FE:   Framing Error flag
00387   *            @arg UART_FLAG_PE:   Parity Error flag
00388   * @retval The new state of __FLAG__ (TRUE or FALSE).
00389   */
00390 #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00391
00392 /** @brief  Clears the specified UART pending flag.
00393   * @param  __HANDLE__: specifies the UART Handle.
00394   *         UART Handle selects the USARTx or UARTy peripheral
00395   *         (USART,UART availability and x,y values depending on device).
00396   * @param  __FLAG__: specifies the flag to check.
00397   *          This parameter can be any combination of the following values:
00398   *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
00399   *            @arg UART_FLAG_LBD:  LIN Break detection flag.
00400   *            @arg UART_FLAG_TC:   Transmission Complete flag.
00401   *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
00402   *
00403   * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
00404   *          error) and IDLE (Idle line detected) flags are cleared by software
00405   *          sequence: a read operation to USART_SR register followed by a read
00406   *          operation to USART_DR register.
00407   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
00408   * @note   TC flag can be also cleared by software sequence: a read operation to
00409   *          USART_SR register followed by a write operation to USART_DR register.
00410   * @note   TXE flag is cleared only by a write to the USART_DR register.
00411   *
00412   */
00413 #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00414
00415 /** @brief  Clears the UART PE pending flag.
00416   * @param  __HANDLE__: specifies the UART Handle.
00417   *         UART Handle selects the USARTx or UARTy peripheral
00418   *         (USART,UART availability and x,y values depending on device).
00419   */
00420 #define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)     \
00421   do{                                           \
00422     __IO uint32_t tmpreg = 0x00U;               \
00423     tmpreg = (__HANDLE__)->Instance->SR;        \
00424     tmpreg = (__HANDLE__)->Instance->DR;        \
00425     UNUSED(tmpreg);                             \
00426   } while(0U)
00427
00428 /** @brief  Clears the UART FE pending flag.
00429   * @param  __HANDLE__: specifies the UART Handle.
00430   *         UART Handle selects the USARTx or UARTy peripheral
00431   *         (USART,UART availability and x,y values depending on device).
00432   */
00433 #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
00434
00435 /** @brief  Clears the UART NE pending flag.
00436   * @param  __HANDLE__: specifies the UART Handle.
00437   *         UART Handle selects the USARTx or UARTy peripheral
00438   *         (USART,UART availability and x,y values depending on device).
00439   */
00440 #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
00441
00442 /** @brief  Clears the UART ORE pending flag.
00443   * @param  __HANDLE__: specifies the UART Handle.
00444   *         UART Handle selects the USARTx or UARTy peripheral
00445   *         (USART,UART availability and x,y values depending on device).
00446   */
00447 #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
00448
00449 /** @brief  Clears the UART IDLE pending flag.
00450   * @param  __HANDLE__: specifies the UART Handle.
00451   *         UART Handle selects the USARTx or UARTy peripheral
00452   *         (USART,UART availability and x,y values depending on device).
00453   */
00454 #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
00455
00456 /** @brief  Enable the specified UART interrupt.
00457   * @param  __HANDLE__: specifies the UART Handle.
00458   *         UART Handle selects the USARTx or UARTy peripheral
00459   *         (USART,UART availability and x,y values depending on device).
00460   * @param  __INTERRUPT__: specifies the UART interrupt source to enable.
00461   *          This parameter can be one of the following values:
00462   *            @arg UART_IT_CTS:  CTS change interrupt
00463   *            @arg UART_IT_LBD:  LIN Break detection interrupt
00464   *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
00465   *            @arg UART_IT_TC:   Transmission complete interrupt
00466   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00467   *            @arg UART_IT_IDLE: Idle line detection interrupt
00468   *            @arg UART_IT_PE:   Parity Error interrupt
00469   *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00470   */
00471 #define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
00472                                                            (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
00473                                                            ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
00474
00475 /** @brief  Disable the specified UART interrupt.
00476   * @param  __HANDLE__: specifies the UART Handle.
00477   *         UART Handle selects the USARTx or UARTy peripheral
00478   *         (USART,UART availability and x,y values depending on device).
00479   * @param  __INTERRUPT__: specifies the UART interrupt source to disable.
00480   *          This parameter can be one of the following values:
00481   *            @arg UART_IT_CTS:  CTS change interrupt
00482   *            @arg UART_IT_LBD:  LIN Break detection interrupt
00483   *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
00484   *            @arg UART_IT_TC:   Transmission complete interrupt
00485   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00486   *            @arg UART_IT_IDLE: Idle line detection interrupt
00487   *            @arg UART_IT_PE:   Parity Error interrupt
00488   *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00489   */
00490 #define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
00491                                                            (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
00492                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
00493
00494 /** @brief  Checks whether the specified UART interrupt has occurred or not.
00495   * @param  __HANDLE__: specifies the UART Handle.
00496   *         UART Handle selects the USARTx or UARTy peripheral
00497   *         (USART,UART availability and x,y values depending on device).
00498   * @param  __IT__: specifies the UART interrupt source to check.
00499   *          This parameter can be one of the following values:
00500   *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
00501   *            @arg UART_IT_LBD: LIN Break detection interrupt
00502   *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
00503   *            @arg UART_IT_TC:  Transmission complete interrupt
00504   *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
00505   *            @arg UART_IT_IDLE: Idle line detection interrupt
00506   *            @arg UART_IT_ERR: Error interrupt
00507   * @retval The new state of __IT__ (TRUE or FALSE).
00508   */
00509 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
00510                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
00511
00512 /** @brief  Enable CTS flow control
00513   *         This macro allows to enable CTS hardware flow control for a given UART instance,
00514   *         without need to call HAL_UART_Init() function.
00515   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00516   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
00517   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00518   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00519   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00520   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00521   * @param  __HANDLE__: specifies the UART Handle.
00522   *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
00523   *         It is used to select the USART peripheral (USART availability and x value depending on device).
00524   */
00525 #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
00526   do{                                                      \
00527     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
00528     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
00529   } while(0U)
00530
00531 /** @brief  Disable CTS flow control
00532   *         This macro allows to disable CTS hardware flow control for a given UART instance,
00533   *         without need to call HAL_UART_Init() function.
00534   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00535   * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
00536   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00537   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00538   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00539   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00540   * @param  __HANDLE__: specifies the UART Handle.
00541   *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
00542   *         It is used to select the USART peripheral (USART availability and x value depending on device).
00543   */
00544 #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
00545   do{                                                       \
00546     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
00547     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
00548   } while(0U)
00549
00550 /** @brief  Enable RTS flow control
00551   *         This macro allows to enable RTS hardware flow control for a given UART instance,
00552   *         without need to call HAL_UART_Init() function.
00553   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00554   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
00555   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00556   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00557   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00558   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00559   * @param  __HANDLE__: specifies the UART Handle.
00560   *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
00561   *         It is used to select the USART peripheral (USART availability and x value depending on device).
00562   */
00563 #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
00564   do{                                                     \
00565     SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
00566     (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
00567   } while(0U)
00568
00569 /** @brief  Disable RTS flow control
00570   *         This macro allows to disable RTS hardware flow control for a given UART instance,
00571   *         without need to call HAL_UART_Init() function.
00572   *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
00573   * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
00574   *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
00575   *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
00576   *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
00577   *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
00578   * @param  __HANDLE__: specifies the UART Handle.
00579   *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
00580   *         It is used to select the USART peripheral (USART availability and x value depending on device).
00581   */
00582 #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
00583   do{                                                      \
00584     CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
00585     (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
00586   } while(0U)
00587
00588 #if defined(USART_CR3_ONEBIT)
00589 /** @brief  macros to enables the UART's one bit sample method
00590   * @param  __HANDLE__: specifies the UART Handle.
00591   */
00592 #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
00593
00594 /** @brief  macros to disables the UART's one bit sample method
00595   * @param  __HANDLE__: specifies the UART Handle.
00596   * @retval None
00597   */
00598 #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
00599 #endif /* USART_CR3_ONEBIT */
00600
00601 /** @brief  Enable UART
00602   * @param  __HANDLE__: specifies the UART Handle.
00603   */
00604 #define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
00605
00606 /** @brief  Disable UART
00607   * @param  __HANDLE__: specifies the UART Handle.
00608   */
00609 #define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
00610 /**
00611   * @}
00612   */
00613 /* Exported functions --------------------------------------------------------*/
00614 /** @addtogroup UART_Exported_Functions
00615   * @{
00616   */
00617
00618 /** @addtogroup UART_Exported_Functions_Group1
00619   * @{
00620   */
00621 /* Initialization/de-initialization functions  **********************************/
00622 HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
00623 HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
00624 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
00625 HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
00626 HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
00627 void HAL_UART_MspInit(UART_HandleTypeDef *huart);
00628 void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
00629 /**
00630   * @}
00631   */
00632
00633 /** @addtogroup UART_Exported_Functions_Group2
00634   * @{
00635   */
00636 /* IO operation functions *******************************************************/
00637 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00638 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
00639 HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00640 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00641 HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00642 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
00643 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
00644 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
00645 HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
00646 /* Transfer Abort functions */
00647 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
00648 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
00649 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
00650 HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
00651 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
00652 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
00653
00654 void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
00655 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
00656 void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
00657 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
00658 void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
00659 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
00660 void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
00661 void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
00662 void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
00663 /**
00664   * @}
00665   */
00666
00667 /** @addtogroup UART_Exported_Functions_Group3
00668   * @{
00669   */
00670 /* Peripheral Control functions  ************************************************/
00671 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
00672 HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
00673 HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
00674 HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
00675 HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
00676 /**
00677   * @}
00678   */
00679
00680 /** @addtogroup UART_Exported_Functions_Group4
00681   * @{
00682   */
00683 /* Peripheral State functions  **************************************************/
00684 HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
00685 uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
00686 /**
00687   * @}
00688   */
00689
00690 /**
00691   * @}
00692   */
00693 /* Private types -------------------------------------------------------------*/
00694 /* Private variables ---------------------------------------------------------*/
00695 /* Private constants ---------------------------------------------------------*/
00696 /** @defgroup UART_Private_Constants UART Private Constants
00697   * @{
00698   */
00699 /** @brief UART interruptions flag mask
00700   *
00701   */
00702 #define UART_IT_MASK                     0x0000FFFFU
00703
00704 #define UART_CR1_REG_INDEX               1U
00705 #define UART_CR2_REG_INDEX               2U
00706 #define UART_CR3_REG_INDEX               3U
00707 /**
00708   * @}
00709   */
00710
00711 /* Private macros ------------------------------------------------------------*/
00712 /** @defgroup UART_Private_Macros UART Private Macros
00713   * @{
00714   */
00715 #define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
00716                                      ((LENGTH) == UART_WORDLENGTH_9B))
00717 #define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
00718 #define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
00719                                     ((STOPBITS) == UART_STOPBITS_2))
00720 #define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
00721                                 ((PARITY) == UART_PARITY_EVEN) || \
00722                                 ((PARITY) == UART_PARITY_ODD))
00723 #define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
00724                               (((CONTROL) == UART_HWCONTROL_NONE) || \
00725                                ((CONTROL) == UART_HWCONTROL_RTS) || \
00726                                ((CONTROL) == UART_HWCONTROL_CTS) || \
00727                                ((CONTROL) == UART_HWCONTROL_RTS_CTS))
00728 #define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
00729 #define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
00730                               ((STATE) == UART_STATE_ENABLE))
00731 #if defined(USART_CR1_OVER8)
00732 #define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
00733                                         ((SAMPLING) == UART_OVERSAMPLING_8))
00734 #endif /* USART_CR1_OVER8 */
00735 #define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
00736 #define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
00737                                                  ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
00738 #define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
00739                                       ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
00740 #define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
00741 #define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
00742
00743 #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            (((_PCLK_)*25U)/(4U*(_BAUD_)))
00744 #define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
00745 #define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
00746 /* UART BRR = mantissa + overflow + fraction
00747             = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
00748 #define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
00749                                                         (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
00750                                                         (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
00751
00752 #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             (((_PCLK_)*25U)/(2U*(_BAUD_)))
00753 #define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
00754 #define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
00755 /* UART BRR = mantissa + overflow + fraction
00756             = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
00757 #define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
00758                                                         ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
00759                                                         (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
00760 /**
00761   * @}
00762   */
00763
00764 /* Private functions ---------------------------------------------------------*/
00765 /** @defgroup UART_Private_Functions UART Private Functions
00766   * @{
00767   */
00768
00769 /**
00770   * @}
00771   */
00772
00773 /**
00774   * @}
00775   */
00776
00777 /**
00778   * @}
00779   */
00780
00781 #ifdef __cplusplus
00782 }
00783 #endif
00784
00785 #endif /* __STM32F1xx_HAL_UART_H */
00786
00787 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_usart.c Source File

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stm32f1xx_hal_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_usart.c
00004   * @author  MCD Application Team
00005   * @version V1.5.0
00006   * @date    15-February-217
00007   * @brief   USART HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral Control functions
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017   [..]
00018     The USART HAL driver can be used as follows:
00019
00020     (#) Declare a USART_HandleTypeDef handle structure.
00021     (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
00022         (##) Enable the USARTx interface clock.
00023         (##) USART pins configuration:
00024              (+++) Enable the clock for the USART GPIOs.
00025              (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
00026         (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
00027              HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
00028              (+++) Configure the USARTx interrupt priority.
00029              (+++) Enable the NVIC USART IRQ handle.
00030         (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
00031              HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
00032              (+++) Declare a DMA handle structure for the Tx/Rx channel.
00033              (+++) Enable the DMAx interface clock.
00034              (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
00035              (+++) Configure the DMA Tx/Rx channel.
00036              (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
00037              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
00038             (+++) Configure the priority and enable the NVIC for the transfer complete
00039                   interrupt on the DMA Tx/Rx channel.
00040             (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
00041                   (used for last byte sending completion detection in DMA non circular mode)
00042
00043     (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
00044         flow control and Mode(Receiver/Transmitter) in the husart Init structure.
00045
00046     (#) Initialize the USART registers by calling the HAL_USART_Init() API:
00047         (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
00048              by calling the customized HAL_USART_MspInit(&husart) API.
00049
00050         -@@- The specific USART interrupts (Transmission complete interrupt,
00051              RXNE interrupt and Error Interrupts) will be managed using the macros
00052              __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
00053
00054     (#) Three operation modes are available within this driver :
00055
00056      *** Polling mode IO operation ***
00057      =================================
00058      [..]
00059        (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
00060        (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
00061
00062      *** Interrupt mode IO operation ***
00063      ===================================
00064      [..]
00065        (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
00066        (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
00067             add his own code by customization of function pointer HAL_USART_TxCpltCallback
00068        (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
00069        (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
00070             add his own code by customization of function pointer HAL_USART_RxCpltCallback
00071        (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
00072             add his own code by customization of function pointer HAL_USART_ErrorCallback
00073
00074      *** DMA mode IO operation ***
00075      ==============================
00076      [..]
00077        (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
00078        (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
00079             add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
00080        (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
00081             add his own code by customization of function pointer HAL_USART_TxCpltCallback
00082        (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
00083        (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
00084             add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
00085        (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
00086             add his own code by customization of function pointer HAL_USART_RxCpltCallback
00087        (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
00088             add his own code by customization of function pointer HAL_USART_ErrorCallback
00089        (+) Pause the DMA Transfer using HAL_USART_DMAPause()
00090        (+) Resume the DMA Transfer using HAL_USART_DMAResume()
00091        (+) Stop the DMA Transfer using HAL_USART_DMAStop()
00092
00093      *** USART HAL driver macros list ***
00094      =============================================
00095      [..]
00096        Below the list of most used macros in USART HAL driver.
00097
00098        (+) __HAL_USART_ENABLE: Enable the USART peripheral
00099        (+) __HAL_USART_DISABLE: Disable the USART peripheral
00100        (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
00101        (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
00102        (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
00103        (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
00104
00105      [..]
00106        (@) You can refer to the USART HAL driver header file for more useful macros
00107
00108   @endverbatim
00109      [..]
00110        (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
00111            in the data register is transmitted but is changed by the parity bit.
00112            Depending on the frame length defined by the M bit (8-bits or 9-bits),
00113            the possible USART frame formats are as listed in the following table:
00114     +-------------------------------------------------------------+
00115     |   M bit |  PCE bit  |            USART frame                 |
00116     |---------------------|---------------------------------------|
00117     |    0    |    0      |    | SB | 8 bit data | STB |          |
00118     |---------|-----------|---------------------------------------|
00119     |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
00120     |---------|-----------|---------------------------------------|
00121     |    1    |    0      |    | SB | 9 bit data | STB |          |
00122     |---------|-----------|---------------------------------------|
00123     |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
00124     +-------------------------------------------------------------+
00125   ******************************************************************************
00126   * @attention
00127   *
00128   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00129   *
00130   * Redistribution and use in source and binary forms, with or without modification,
00131   * are permitted provided that the following conditions are met:
00132   *   1. Redistributions of source code must retain the above copyright notice,
00133   *      this list of conditions and the following disclaimer.
00134   *   2. Redistributions in binary form must reproduce the above copyright notice,
00135   *      this list of conditions and the following disclaimer in the documentation
00136   *      and/or other materials provided with the distribution.
00137   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00138   *      may be used to endorse or promote products derived from this software
00139   *      without specific prior written permission.
00140   *
00141   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00142   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00143   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00144   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00145   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00146   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00147   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00148   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00149   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00150   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00151   *
00152   ******************************************************************************
00153   */
00154
00155 /* Includes ------------------------------------------------------------------*/
00156 #include "stm32f1xx_hal.h"
00157
00158 /** @addtogroup STM32F1xx_HAL_Driver
00159   * @{
00160   */
00161
00162 /** @defgroup USART USART
00163   * @brief HAL USART Synchronous module driver
00164   * @{
00165   */
00166 #ifdef HAL_USART_MODULE_ENABLED
00167
00168 /* Private typedef -----------------------------------------------------------*/
00169 /* Private define ------------------------------------------------------------*/
00170 /** @addtogroup USART_Private_Constants
00171   * @{
00172   */
00173 #define DUMMY_DATA           0xFFFFU
00174 #define USART_TIMEOUT_VALUE  22000U
00175 /**
00176   * @}
00177   */
00178 /* Private macro -------------------------------------------------------------*/
00179 /* Private variables ---------------------------------------------------------*/
00180 /* Private function prototypes -----------------------------------------------*/
00181 /* Private functions ---------------------------------------------------------*/
00182 /** @addtogroup USART_Private_Functions
00183   * @{
00184   */
00185 static void USART_EndTxTransfer(USART_HandleTypeDef *husart);
00186 static void USART_EndRxTransfer(USART_HandleTypeDef *husart);
00187 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
00188 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
00189 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
00190 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
00191 static void USART_SetConfig (USART_HandleTypeDef *husart);
00192 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
00193 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
00194 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
00195 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
00196 static void USART_DMAError(DMA_HandleTypeDef *hdma);
00197 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
00198 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
00199 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
00200
00201 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
00202 /**
00203   * @}
00204   */
00205
00206 /* Exported functions --------------------------------------------------------*/
00207 /** @defgroup USART_Exported_Functions USART Exported Functions
00208   * @{
00209   */
00210
00211 /** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
00212   *  @brief    Initialization and Configuration functions
00213   *
00214 @verbatim
00215   ==============================================================================
00216             ##### Initialization and Configuration functions #####
00217   ==============================================================================
00218   [..]
00219   This subsection provides a set of functions allowing to initialize the USART
00220   in asynchronous and in synchronous modes.
00221   (+) For the asynchronous mode only these parameters can be configured:
00222       (++) Baud Rate
00223       (++) Word Length
00224       (++) Stop Bit
00225       (++) Parity: If the parity is enabled, then the MSB bit of the data written
00226            in the data register is transmitted but is changed by the parity bit.
00227            Depending on the frame length defined by the M bit (8-bits or 9-bits),
00228            please refer to Reference manual for possible USART frame formats.
00229       (++) USART polarity
00230       (++) USART phase
00231       (++) USART LastBit
00232       (++) Receiver/transmitter modes
00233
00234   [..]
00235     The HAL_USART_Init() function follows the USART  synchronous configuration
00236     procedure (details for the procedure are available in reference manuals
00237     (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
00238
00239 @endverbatim
00240   * @{
00241   */
00242
00243 /**
00244   * @brief  Initializes the USART mode according to the specified
00245   *         parameters in the USART_InitTypeDef and create the associated handle.
00246   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00247   *                 the configuration information for the specified USART module.
00248   * @retval HAL status
00249   */
00250 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
00251 {
00252   /* Check the USART handle allocation */
00253   if(husart == NULL)
00254   {
00255     return HAL_ERROR;
00256   }
00257
00258   /* Check the parameters */
00259   assert_param(IS_USART_INSTANCE(husart->Instance));
00260
00261   if(husart->State == HAL_USART_STATE_RESET)
00262   {
00263     /* Allocate lock resource and initialize it */
00264     husart->Lock = HAL_UNLOCKED;
00265
00266     /* Init the low level hardware */
00267     HAL_USART_MspInit(husart);
00268   }
00269
00270   husart->State = HAL_USART_STATE_BUSY;
00271
00272   /* Set the USART Communication parameters */
00273   USART_SetConfig(husart);
00274
00275   /* In USART mode, the following bits must be kept cleared:
00276      - LINEN bit in the USART_CR2 register
00277      - HDSEL, SCEN and IREN bits in the USART_CR3 register */
00278   CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
00279   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
00280
00281   /* Enable the Peripheral */
00282   __HAL_USART_ENABLE(husart);
00283
00284   /* Initialize the USART state */
00285   husart->ErrorCode = HAL_USART_ERROR_NONE;
00286   husart->State= HAL_USART_STATE_READY;
00287
00288   return HAL_OK;
00289 }
00290
00291 /**
00292   * @brief  DeInitializes the USART peripheral.
00293   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00294   *                 the configuration information for the specified USART module.
00295   * @retval HAL status
00296   */
00297 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
00298 {
00299   /* Check the USART handle allocation */
00300   if(husart == NULL)
00301   {
00302     return HAL_ERROR;
00303   }
00304
00305   /* Check the parameters */
00306   assert_param(IS_USART_INSTANCE(husart->Instance));
00307
00308   husart->State = HAL_USART_STATE_BUSY;
00309
00310   /* DeInit the low level hardware */
00311   HAL_USART_MspDeInit(husart);
00312
00313   husart->ErrorCode = HAL_USART_ERROR_NONE;
00314   husart->State = HAL_USART_STATE_RESET;
00315
00316   /* Release Lock */
00317   __HAL_UNLOCK(husart);
00318
00319   return HAL_OK;
00320 }
00321
00322 /**
00323   * @brief  USART MSP Init.
00324   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00325   *                 the configuration information for the specified USART module.
00326   * @retval None
00327   */
00328 __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
00329 {
00330   /* Prevent unused argument(s) compilation warning */
00331   UNUSED(husart);
00332   /* NOTE: This function should not be modified, when the callback is needed,
00333            the HAL_USART_MspInit could be implemented in the user file
00334    */
00335 }
00336
00337 /**
00338   * @brief  USART MSP DeInit.
00339   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00340   *                 the configuration information for the specified USART module.
00341   * @retval None
00342   */
00343 __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
00344 {
00345   /* Prevent unused argument(s) compilation warning */
00346   UNUSED(husart);
00347   /* NOTE: This function should not be modified, when the callback is needed,
00348            the HAL_USART_MspDeInit could be implemented in the user file
00349    */
00350 }
00351
00352 /**
00353   * @}
00354   */
00355
00356 /** @defgroup USART_Exported_Functions_Group2 IO operation functions
00357   *  @brief   USART Transmit and Receive functions
00358   *
00359 @verbatim
00360   ==============================================================================
00361                       ##### IO operation functions #####
00362   ==============================================================================
00363   [..]
00364     This subsection provides a set of functions allowing to manage the USART synchronous
00365     data transfers.
00366
00367   [..]
00368     The USART supports master mode only: it cannot receive or send data related to an input
00369     clock (SCLK is always an output).
00370
00371     (#) There are two modes of transfer:
00372         (++) Blocking mode: The communication is performed in polling mode.
00373              The HAL status of all data processing is returned by the same function
00374              after finishing transfer.
00375         (++) No-Blocking mode: The communication is performed using Interrupts
00376              or DMA, These API's return the HAL status.
00377              The end of the data processing will be indicated through the
00378              dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
00379              using DMA mode.
00380              The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
00381              user callbacks
00382              will be executed respectively at the end of the transmit or Receive process
00383              The HAL_USART_ErrorCallback() user callback will be executed when a communication
00384              error is detected
00385
00386     (#) Blocking mode APIs are :
00387         (++) HAL_USART_Transmit() in simplex mode
00388         (++) HAL_USART_Receive() in full duplex receive only
00389         (++) HAL_USART_TransmitReceive() in full duplex mode
00390
00391     (#) Non Blocking mode APIs with Interrupt are :
00392         (++) HAL_USART_Transmit_IT()in simplex mode
00393         (++) HAL_USART_Receive_IT() in full duplex receive only
00394         (++) HAL_USART_TransmitReceive_IT() in full duplex mode
00395         (++) HAL_USART_IRQHandler()
00396
00397     (#) Non Blocking mode functions with DMA are :
00398         (++) HAL_USART_Transmit_DMA()in simplex mode
00399         (++) HAL_USART_Receive_DMA() in full duplex receive only
00400         (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
00401         (++) HAL_USART_DMAPause()
00402         (++) HAL_USART_DMAResume()
00403         (++) HAL_USART_DMAStop()
00404
00405     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00406         (++) HAL_USART_TxHalfCpltCallback()
00407         (++) HAL_USART_TxCpltCallback()
00408         (++) HAL_USART_RxHalfCpltCallback()
00409         (++) HAL_USART_RxCpltCallback()
00410         (++) HAL_USART_ErrorCallback()
00411         (++) HAL_USART_TxRxCpltCallback()
00412
00413 @endverbatim
00414   * @{
00415   */
00416
00417 /**
00418   * @brief  Simplex Send an amount of data in blocking mode.
00419   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00420   *                 the configuration information for the specified USART module.
00421   * @param  pTxData: Pointer to data buffer
00422   * @param  Size: Amount of data to be sent
00423   * @param  Timeout: Timeout duration
00424   * @retval HAL status
00425   */
00426 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
00427 {
00428   uint16_t* tmp;
00429   uint32_t tickstart = 0U;
00430
00431   if(husart->State == HAL_USART_STATE_READY)
00432   {
00433     if((pTxData == NULL) || (Size == 0U))
00434     {
00435       return  HAL_ERROR;
00436     }
00437
00438     /* Process Locked */
00439     __HAL_LOCK(husart);
00440
00441     husart->ErrorCode = HAL_USART_ERROR_NONE;
00442     husart->State = HAL_USART_STATE_BUSY_TX;
00443
00444     /* Init tickstart for timeout managment */
00445     tickstart = HAL_GetTick();
00446
00447     husart->TxXferSize = Size;
00448     husart->TxXferCount = Size;
00449     while(husart->TxXferCount > 0U)
00450     {
00451       husart->TxXferCount--;
00452       if(husart->Init.WordLength == USART_WORDLENGTH_9B)
00453       {
00454         /* Wait for TC flag in order to write data in DR */
00455         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00456         {
00457           return HAL_TIMEOUT;
00458         }
00459         tmp = (uint16_t*) pTxData;
00460         WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF));
00461         if(husart->Init.Parity == USART_PARITY_NONE)
00462         {
00463           pTxData += 2U;
00464         }
00465         else
00466         {
00467           pTxData += 1U;
00468         }
00469       }
00470       else
00471       {
00472         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00473         {
00474           return HAL_TIMEOUT;
00475         }
00476         WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0xFF));
00477       }
00478     }
00479
00480     if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
00481     {
00482       return HAL_TIMEOUT;
00483     }
00484
00485     husart->State = HAL_USART_STATE_READY;
00486
00487     /* Process Unlocked */
00488     __HAL_UNLOCK(husart);
00489
00490     return HAL_OK;
00491   }
00492   else
00493   {
00494     return HAL_BUSY;
00495   }
00496 }
00497
00498 /**
00499   * @brief  Full-Duplex Receive an amount of data in blocking mode.
00500   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00501   *                 the configuration information for the specified USART module.
00502   * @param  pRxData: Pointer to data buffer
00503   * @param  Size: Amount of data to be received
00504   * @param  Timeout: Timeout duration
00505   * @retval HAL status
00506   */
00507 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00508 {
00509   uint16_t* tmp;
00510   uint32_t tickstart = 0U;
00511
00512   if(husart->State == HAL_USART_STATE_READY)
00513   {
00514     if((pRxData == NULL) || (Size == 0U))
00515     {
00516       return  HAL_ERROR;
00517     }
00518     /* Process Locked */
00519     __HAL_LOCK(husart);
00520
00521     husart->ErrorCode = HAL_USART_ERROR_NONE;
00522     husart->State = HAL_USART_STATE_BUSY_RX;
00523
00524     /* Init tickstart for timeout managment */
00525     tickstart = HAL_GetTick();
00526
00527     husart->RxXferSize = Size;
00528     husart->RxXferCount = Size;
00529     /* Check the remain data to be received */
00530     while(husart->RxXferCount > 0U)
00531     {
00532       husart->RxXferCount--;
00533       if(husart->Init.WordLength == USART_WORDLENGTH_9B)
00534       {
00535         /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
00536         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00537         {
00538           return HAL_TIMEOUT;
00539         }
00540         /* Send dummy byte in order to generate clock */
00541         WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
00542
00543         /* Wait for RXNE Flag */
00544         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00545         {
00546           return HAL_TIMEOUT;
00547         }
00548         tmp = (uint16_t*) pRxData ;
00549         if(husart->Init.Parity == USART_PARITY_NONE)
00550         {
00551           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
00552           pRxData +=2U;
00553         }
00554         else
00555         {
00556           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
00557           pRxData +=1U;
00558         }
00559       }
00560       else
00561       {
00562         /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
00563         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00564         {
00565           return HAL_TIMEOUT;
00566         }
00567
00568         /* Send Dummy Byte in order to generate clock */
00569         WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF));
00570
00571         /* Wait until RXNE flag is set to receive the byte */
00572         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00573         {
00574           return HAL_TIMEOUT;
00575         }
00576         if(husart->Init.Parity == USART_PARITY_NONE)
00577         {
00578           /* Receive data */
00579           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
00580         }
00581         else
00582         {
00583           /* Receive data */
00584           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
00585         }
00586
00587       }
00588     }
00589
00590     husart->State = HAL_USART_STATE_READY;
00591
00592     /* Process Unlocked */
00593     __HAL_UNLOCK(husart);
00594
00595     return HAL_OK;
00596   }
00597   else
00598   {
00599     return HAL_BUSY;
00600   }
00601 }
00602
00603 /**
00604   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
00605   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00606   *                 the configuration information for the specified USART module.
00607   * @param  pTxData: Pointer to data transmitted buffer
00608   * @param  pRxData: Pointer to data received buffer
00609   * @param  Size: Amount of data to be sent
00610   * @param  Timeout: Timeout duration
00611   * @retval HAL status
00612   */
00613 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
00614 {
00615   uint16_t* tmp;
00616   uint32_t tickstart = 0U;
00617
00618   if(husart->State == HAL_USART_STATE_READY)
00619   {
00620     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00621     {
00622       return  HAL_ERROR;
00623     }
00624     /* Process Locked */
00625     __HAL_LOCK(husart);
00626
00627     husart->ErrorCode = HAL_USART_ERROR_NONE;
00628     husart->State = HAL_USART_STATE_BUSY_RX;
00629
00630     /* Init tickstart for timeout managment */
00631     tickstart = HAL_GetTick();
00632
00633     husart->RxXferSize = Size;
00634     husart->TxXferSize = Size;
00635     husart->TxXferCount = Size;
00636     husart->RxXferCount = Size;
00637
00638     /* Check the remain data to be received */
00639     while(husart->TxXferCount > 0U)
00640     {
00641       husart->TxXferCount--;
00642       husart->RxXferCount--;
00643       if(husart->Init.WordLength == USART_WORDLENGTH_9B)
00644       {
00645         /* Wait for TC flag in order to write data in DR */
00646         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00647         {
00648           return HAL_TIMEOUT;
00649         }
00650         tmp = (uint16_t*) pTxData;
00651         WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF));
00652         if(husart->Init.Parity == USART_PARITY_NONE)
00653         {
00654           pTxData += 2U;
00655         }
00656         else
00657         {
00658           pTxData += 1U;
00659         }
00660
00661         /* Wait for RXNE Flag */
00662         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00663         {
00664           return HAL_TIMEOUT;
00665         }
00666         tmp = (uint16_t*) pRxData ;
00667         if(husart->Init.Parity == USART_PARITY_NONE)
00668         {
00669           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
00670           pRxData += 2U;
00671         }
00672         else
00673         {
00674           *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
00675           pRxData += 1U;
00676         }
00677       }
00678       else
00679       {
00680         /* Wait for TC flag in order to write data in DR */
00681         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
00682         {
00683           return HAL_TIMEOUT;
00684         }
00685         WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0x00FF));
00686
00687         /* Wait for RXNE Flag */
00688         if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
00689         {
00690           return HAL_TIMEOUT;
00691         }
00692         if(husart->Init.Parity == USART_PARITY_NONE)
00693         {
00694           /* Receive data */
00695           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
00696         }
00697         else
00698         {
00699           /* Receive data */
00700           *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
00701         }
00702       }
00703     }
00704
00705     husart->State = HAL_USART_STATE_READY;
00706
00707     /* Process Unlocked */
00708     __HAL_UNLOCK(husart);
00709
00710     return HAL_OK;
00711   }
00712   else
00713   {
00714     return HAL_BUSY;
00715   }
00716 }
00717
00718 /**
00719   * @brief  Simplex Send an amount of data in non-blocking mode.
00720   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00721   *                the configuration information for the specified USART module.
00722   * @param  pTxData: Pointer to data buffer
00723   * @param  Size: Amount of data to be sent
00724   * @retval HAL status
00725   * @note   The USART errors are not managed to avoid the overrun error.
00726   */
00727 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00728 {
00729   /* Check that a Tx process is not already ongoing */
00730   if(husart->State == HAL_USART_STATE_READY)
00731   {
00732     if((pTxData == NULL) || (Size == 0U))
00733     {
00734       return HAL_ERROR;
00735     }
00736     /* Process Locked */
00737     __HAL_LOCK(husart);
00738
00739     husart->pTxBuffPtr = pTxData;
00740     husart->TxXferSize = Size;
00741     husart->TxXferCount = Size;
00742
00743     husart->ErrorCode = HAL_USART_ERROR_NONE;
00744     husart->State = HAL_USART_STATE_BUSY_TX;
00745
00746     /* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
00747        are not managed by the USART transmit process to avoid the overrun interrupt
00748        when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
00749        to benefit for the frame error and noise interrupts the USART mode should be
00750        configured only for transmit "USART_MODE_TX"
00751        The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
00752        Noise error interrupt */
00753
00754     /* Process Unlocked */
00755     __HAL_UNLOCK(husart);
00756
00757     /* Enable the USART Transmit Data Register Empty Interrupt */
00758     __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
00759
00760     return HAL_OK;
00761   }
00762   else
00763   {
00764     return HAL_BUSY;
00765   }
00766 }
00767
00768 /**
00769   * @brief  Simplex Receive an amount of data in non-blocking mode.
00770   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00771   *                the configuration information for the specified USART module.
00772   * @param  pRxData: Pointer to data buffer
00773   * @param  Size: Amount of data to be received
00774   * @retval HAL status
00775   */
00776 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00777 {
00778   if(husart->State == HAL_USART_STATE_READY)
00779   {
00780     if((pRxData == NULL) || (Size == 0U))
00781     {
00782       return HAL_ERROR;
00783     }
00784     /* Process Locked */
00785     __HAL_LOCK(husart);
00786
00787     husart->pRxBuffPtr = pRxData;
00788     husart->RxXferSize = Size;
00789     husart->RxXferCount = Size;
00790
00791     husart->ErrorCode = HAL_USART_ERROR_NONE;
00792     husart->State = HAL_USART_STATE_BUSY_RX;
00793
00794     /* Process Unlocked */
00795     __HAL_UNLOCK(husart);
00796
00797     /* Enable the USART Data Register not empty Interrupt */
00798     __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
00799
00800     /* Enable the USART Parity Error Interrupt */
00801     __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
00802
00803     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00804     __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
00805
00806     /* Send dummy byte in order to generate the clock for the slave to send data */
00807     WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
00808
00809     return HAL_OK;
00810   }
00811   else
00812   {
00813     return HAL_BUSY;
00814   }
00815 }
00816
00817 /**
00818   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
00819   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00820   *                 the configuration information for the specified USART module.
00821   * @param  pTxData: Pointer to data transmitted buffer
00822   * @param  pRxData: Pointer to data received buffer
00823   * @param  Size: Amount of data to be received
00824   * @retval HAL status
00825   */
00826 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
00827 {
00828   if(husart->State == HAL_USART_STATE_READY)
00829   {
00830     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
00831     {
00832       return HAL_ERROR;
00833     }
00834     /* Process Locked */
00835     __HAL_LOCK(husart);
00836
00837     husart->pRxBuffPtr = pRxData;
00838     husart->RxXferSize = Size;
00839     husart->RxXferCount = Size;
00840     husart->pTxBuffPtr = pTxData;
00841     husart->TxXferSize = Size;
00842     husart->TxXferCount = Size;
00843
00844     husart->ErrorCode = HAL_USART_ERROR_NONE;
00845     husart->State = HAL_USART_STATE_BUSY_TX_RX;
00846
00847     /* Process Unlocked */
00848     __HAL_UNLOCK(husart);
00849
00850     /* Enable the USART Data Register not empty Interrupt */
00851     __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE);
00852
00853     /* Enable the USART Parity Error Interrupt */
00854     __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
00855
00856     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
00857     __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
00858
00859     /* Enable the USART Transmit Data Register Empty Interrupt */
00860     __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
00861
00862     return HAL_OK;
00863   }
00864   else
00865   {
00866     return HAL_BUSY;
00867   }
00868 }
00869
00870 /**
00871   * @brief  Simplex Send an amount of data in non-blocking mode.
00872   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00873   *                 the configuration information for the specified USART module.
00874   * @param  pTxData: Pointer to data buffer
00875   * @param  Size: Amount of data to be sent
00876   * @retval HAL status
00877   */
00878 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
00879 {
00880   uint32_t *tmp;
00881
00882   if(husart->State == HAL_USART_STATE_READY)
00883   {
00884     if((pTxData == NULL) || (Size == 0U))
00885     {
00886       return HAL_ERROR;
00887     }
00888     /* Process Locked */
00889     __HAL_LOCK(husart);
00890
00891     husart->pTxBuffPtr = pTxData;
00892     husart->TxXferSize = Size;
00893     husart->TxXferCount = Size;
00894
00895     husart->ErrorCode = HAL_USART_ERROR_NONE;
00896     husart->State = HAL_USART_STATE_BUSY_TX;
00897
00898     /* Set the USART DMA transfer complete callback */
00899     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
00900
00901     /* Set the USART DMA Half transfer complete callback */
00902     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
00903
00904     /* Set the DMA error callback */
00905     husart->hdmatx->XferErrorCallback = USART_DMAError;
00906
00907     /* Set the DMA abort callback */
00908     husart->hdmatx->XferAbortCallback = NULL;
00909
00910     /* Enable the USART transmit DMA channel */
00911     tmp = (uint32_t*)&pTxData;
00912     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
00913
00914     /* Clear the TC flag in the SR register by writing 0 to it */
00915     __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
00916
00917     /* Process Unlocked */
00918     __HAL_UNLOCK(husart);
00919
00920     /* Enable the DMA transfer for transmit request by setting the DMAT bit
00921     in the USART CR3 register */
00922     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
00923
00924     return HAL_OK;
00925   }
00926   else
00927   {
00928     return HAL_BUSY;
00929   }
00930 }
00931
00932 /**
00933   * @brief  Full-Duplex Receive an amount of data in non-blocking mode.
00934   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
00935   *                 the configuration information for the specified USART module.
00936   * @param  pRxData: Pointer to data buffer
00937   * @param  Size: Amount of data to be received
00938   * @retval HAL status
00939   * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
00940   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
00941   */
00942 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
00943 {
00944   uint32_t *tmp;
00945
00946   if(husart->State == HAL_USART_STATE_READY)
00947   {
00948     if((pRxData == NULL) || (Size == 0U))
00949     {
00950       return HAL_ERROR;
00951     }
00952
00953     /* Process Locked */
00954     __HAL_LOCK(husart);
00955
00956     husart->pRxBuffPtr = pRxData;
00957     husart->RxXferSize = Size;
00958     husart->pTxBuffPtr = pRxData;
00959     husart->TxXferSize = Size;
00960
00961     husart->ErrorCode = HAL_USART_ERROR_NONE;
00962     husart->State = HAL_USART_STATE_BUSY_RX;
00963
00964     /* Set the USART DMA Rx transfer complete callback */
00965     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
00966
00967     /* Set the USART DMA Half transfer complete callback */
00968     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
00969
00970     /* Set the USART DMA Rx transfer error callback */
00971     husart->hdmarx->XferErrorCallback = USART_DMAError;
00972
00973     /* Set the DMA abort callback */
00974     husart->hdmarx->XferAbortCallback = NULL;
00975
00976     /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing
00977     is performed in DMA reception complete callback  */
00978     husart->hdmatx->XferHalfCpltCallback = NULL;
00979     husart->hdmatx->XferCpltCallback = NULL;
00980
00981     /* Set the DMA error callback */
00982     husart->hdmatx->XferErrorCallback = USART_DMAError;
00983
00984     /* Set the DMA AbortCpltCallback */
00985     husart->hdmatx->XferAbortCallback = NULL;
00986
00987     /* Enable the USART receive DMA channel */
00988     tmp = (uint32_t*)&pRxData;
00989     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
00990
00991     /* Enable the USART transmit DMA channel: the transmit channel is used in order
00992        to generate in the non-blocking mode the clock to the slave device,
00993        this mode isn't a simplex receive mode but a full-duplex receive one */
00994     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
00995
00996     /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer */
00997     __HAL_USART_CLEAR_OREFLAG(husart);
00998
00999     /* Process Unlocked */
01000     __HAL_UNLOCK(husart);
01001
01002     /* Enable the USART Parity Error Interrupt */
01003     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01004
01005     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01006     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01007
01008     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01009        in the USART CR3 register */
01010     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01011
01012     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01013        in the USART CR3 register */
01014     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01015
01016     return HAL_OK;
01017   }
01018   else
01019   {
01020     return HAL_BUSY;
01021   }
01022 }
01023
01024 /**
01025   * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode.
01026   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01027   *                 the configuration information for the specified USART module.
01028   * @param  pTxData: Pointer to data transmitted buffer
01029   * @param  pRxData: Pointer to data received buffer
01030   * @param  Size: Amount of data to be received
01031   * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
01032   * @retval HAL status
01033   */
01034 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
01035 {
01036   uint32_t *tmp;
01037
01038   if(husart->State == HAL_USART_STATE_READY)
01039   {
01040     if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
01041     {
01042       return HAL_ERROR;
01043     }
01044     /* Process Locked */
01045     __HAL_LOCK(husart);
01046
01047     husart->pRxBuffPtr = pRxData;
01048     husart->RxXferSize = Size;
01049     husart->pTxBuffPtr = pTxData;
01050     husart->TxXferSize = Size;
01051
01052     husart->ErrorCode = HAL_USART_ERROR_NONE;
01053     husart->State = HAL_USART_STATE_BUSY_TX_RX;
01054
01055     /* Set the USART DMA Rx transfer complete callback */
01056     husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
01057
01058     /* Set the USART DMA Half transfer complete callback */
01059     husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
01060
01061     /* Set the USART DMA Tx transfer complete callback */
01062     husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
01063
01064     /* Set the USART DMA Half transfer complete callback */
01065     husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
01066
01067     /* Set the USART DMA Tx transfer error callback */
01068     husart->hdmatx->XferErrorCallback = USART_DMAError;
01069
01070     /* Set the USART DMA Rx transfer error callback */
01071     husart->hdmarx->XferErrorCallback = USART_DMAError;
01072
01073     /* Set the DMA abort callback */
01074     husart->hdmarx->XferAbortCallback = NULL;
01075
01076     /* Enable the USART receive DMA channel */
01077     tmp = (uint32_t*)&pRxData;
01078     HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
01079
01080     /* Enable the USART transmit DMA channel */
01081     tmp = (uint32_t*)&pTxData;
01082     HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
01083
01084     /* Clear the TC flag in the SR register by writing 0 to it */
01085     __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
01086
01087     /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
01088     __HAL_USART_CLEAR_OREFLAG(husart);
01089
01090     /* Process Unlocked */
01091     __HAL_UNLOCK(husart);
01092
01093     /* Enable the USART Parity Error Interrupt */
01094     SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01095
01096     /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
01097     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
01098
01099     /* Enable the DMA transfer for the receiver request by setting the DMAR bit
01100        in the USART CR3 register */
01101     SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01102
01103     /* Enable the DMA transfer for transmit request by setting the DMAT bit
01104        in the USART CR3 register */
01105     SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01106
01107     return HAL_OK;
01108   }
01109   else
01110   {
01111     return HAL_BUSY;
01112   }
01113 }
01114
01115 /**
01116   * @brief Pauses the DMA Transfer.
01117   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01118   *                 the configuration information for the specified USART module.
01119   * @retval HAL status
01120   */
01121 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
01122 {
01123   /* Process Locked */
01124   __HAL_LOCK(husart);
01125
01126   /* Disable the USART DMA Tx request */
01127   CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01128
01129   /* Process Unlocked */
01130   __HAL_UNLOCK(husart);
01131
01132   return HAL_OK;
01133 }
01134
01135 /**
01136   * @brief Resumes the DMA Transfer.
01137   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01138   *                 the configuration information for the specified USART module.
01139   * @retval HAL status
01140   */
01141 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
01142 {
01143   /* Process Locked */
01144   __HAL_LOCK(husart);
01145
01146   /* Enable the USART DMA Tx request */
01147   SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01148
01149   /* Process Unlocked */
01150   __HAL_UNLOCK(husart);
01151
01152   return HAL_OK;
01153 }
01154
01155 /**
01156   * @brief Stops the DMA Transfer.
01157   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01158   *                 the configuration information for the specified USART module.
01159   * @retval HAL status
01160   */
01161 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
01162 {
01163   uint32_t dmarequest = 0x00U;
01164   /* The Lock is not implemented on this API to allow the user application
01165      to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
01166      when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
01167      and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
01168      */
01169
01170   /* Stop USART DMA Tx request if ongoing */
01171   dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
01172   if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
01173   {
01174     USART_EndTxTransfer(husart);
01175
01176     /* Abort the USART DMA Tx channel */
01177     if(husart->hdmatx != NULL)
01178     {
01179       HAL_DMA_Abort(husart->hdmatx);
01180     }
01181
01182     /* Disable the USART Tx DMA request */
01183     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01184   }
01185
01186   /* Stop USART DMA Rx request if ongoing */
01187   dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
01188   if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
01189   {
01190     USART_EndRxTransfer(husart);
01191
01192     /* Abort the USART DMA Rx channel */
01193     if(husart->hdmarx != NULL)
01194     {
01195       HAL_DMA_Abort(husart->hdmarx);
01196     }
01197
01198     /* Disable the USART Rx DMA request */
01199     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01200   }
01201
01202   return HAL_OK;
01203 }
01204
01205 /**
01206   * @brief  Abort ongoing transfer (blocking mode).
01207   * @param  husart USART handle.
01208   * @note   This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
01209   *         as described by TransferType parameter) started in Interrupt or DMA mode.
01210   *         This procedure performs following operations :
01211   *           - Disable PPP Interrupts (depending of transfer direction)
01212   *           - Disable the DMA transfer in the peripheral register (if enabled)
01213   *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
01214   *           - Set handle State to READY
01215   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
01216   * @retval HAL status
01217 */
01218 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
01219 {
01220   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01221   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01222   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01223
01224   /* Disable the USART DMA Tx request if enabled */
01225   if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01226   {
01227     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01228
01229     /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
01230     if(husart->hdmatx != NULL)
01231     {
01232       /* Set the USART DMA Abort callback to Null.
01233          No call back execution at end of DMA abort procedure */
01234       husart->hdmatx->XferAbortCallback = NULL;
01235
01236       HAL_DMA_Abort(husart->hdmatx);
01237     }
01238   }
01239
01240   /* Disable the USART DMA Rx request if enabled */
01241   if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01242   {
01243     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01244
01245     /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
01246     if(husart->hdmarx != NULL)
01247     {
01248       /* Set the USART DMA Abort callback to Null.
01249          No call back execution at end of DMA abort procedure */
01250       husart->hdmarx->XferAbortCallback = NULL;
01251
01252       HAL_DMA_Abort(husart->hdmarx);
01253     }
01254   }
01255
01256   /* Reset Tx and Rx transfer counters */
01257   husart->TxXferCount = 0x00U;
01258   husart->RxXferCount = 0x00U;
01259
01260   /* Restore husart->State to Ready */
01261   husart->State  = HAL_USART_STATE_READY;
01262
01263   /* Reset Handle ErrorCode to No Error */
01264   husart->ErrorCode = HAL_USART_ERROR_NONE;
01265
01266   return HAL_OK;
01267 }
01268
01269 /**
01270   * @brief  Abort ongoing transfer (Interrupt mode).
01271   * @param  husart USART handle.
01272   * @note   This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
01273   *         as described by TransferType parameter) started in Interrupt or DMA mode.
01274   *         This procedure performs following operations :
01275   *           - Disable PPP Interrupts (depending of transfer direction)
01276   *           - Disable the DMA transfer in the peripheral register (if enabled)
01277   *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
01278   *           - Set handle State to READY
01279   *           - At abort completion, call user abort complete callback
01280   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
01281   *         considered as completed only when user abort complete callback is executed (not when exiting function).
01282   * @retval HAL status
01283 */
01284 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
01285 {
01286   uint32_t AbortCplt = 0x01U;
01287
01288   /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01289   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
01290   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01291
01292   /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
01293      before any call to DMA Abort functions */
01294   /* DMA Tx Handle is valid */
01295   if(husart->hdmatx != NULL)
01296   {
01297     /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
01298        Otherwise, set it to NULL */
01299     if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01300     {
01301       husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
01302     }
01303     else
01304     {
01305       husart->hdmatx->XferAbortCallback = NULL;
01306     }
01307   }
01308   /* DMA Rx Handle is valid */
01309   if(husart->hdmarx != NULL)
01310   {
01311     /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
01312        Otherwise, set it to NULL */
01313     if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01314     {
01315       husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
01316     }
01317     else
01318     {
01319       husart->hdmarx->XferAbortCallback = NULL;
01320     }
01321   }
01322
01323   /* Disable the USART DMA Tx request if enabled */
01324   if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
01325   {
01326     /* Disable DMA Tx at USART level */
01327     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01328
01329     /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
01330     if(husart->hdmatx != NULL)
01331     {
01332       /* USART Tx DMA Abort callback has already been initialised :
01333          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
01334
01335       /* Abort DMA TX */
01336       if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
01337       {
01338         husart->hdmatx->XferAbortCallback = NULL;
01339       }
01340       else
01341       {
01342         AbortCplt = 0x00U;
01343       }
01344     }
01345   }
01346
01347   /* Disable the USART DMA Rx request if enabled */
01348   if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01349   {
01350     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01351
01352     /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
01353     if(husart->hdmarx != NULL)
01354     {
01355       /* USART Rx DMA Abort callback has already been initialised :
01356          will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
01357
01358       /* Abort DMA RX */
01359       if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
01360       {
01361         husart->hdmarx->XferAbortCallback = NULL;
01362         AbortCplt = 0x01U;
01363       }
01364       else
01365       {
01366         AbortCplt = 0x00U;
01367       }
01368     }
01369   }
01370
01371   /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
01372   if(AbortCplt  == 0x01U)
01373   {
01374     /* Reset Tx and Rx transfer counters */
01375     husart->TxXferCount = 0x00U;
01376     husart->RxXferCount = 0x00U;
01377
01378     /* Reset errorCode */
01379     husart->ErrorCode = HAL_USART_ERROR_NONE;
01380
01381     /* Restore husart->State to Ready */
01382     husart->State  = HAL_USART_STATE_READY;
01383
01384     /* As no DMA to be aborted, call directly user Abort complete callback */
01385     HAL_USART_AbortCpltCallback(husart);
01386   }
01387
01388   return HAL_OK;
01389 }
01390
01391 /**
01392   * @brief  This function handles USART interrupt request.
01393   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01394   *                the configuration information for the specified USART module.
01395   * @retval None
01396   */
01397 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
01398 {
01399   uint32_t isrflags = READ_REG(husart->Instance->SR);
01400   uint32_t cr1its   = READ_REG(husart->Instance->CR1);
01401   uint32_t cr3its   = READ_REG(husart->Instance->CR3);
01402   uint32_t errorflags = 0x00U;
01403   uint32_t dmarequest = 0x00U;
01404
01405   /* If no error occurs */
01406   errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
01407   if(errorflags == RESET)
01408   {
01409     /* USART in mode Receiver -------------------------------------------------*/
01410     if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01411     {
01412       if(husart->State == HAL_USART_STATE_BUSY_RX)
01413       {
01414         USART_Receive_IT(husart);
01415       }
01416       else
01417       {
01418         USART_TransmitReceive_IT(husart);
01419       }
01420       return;
01421     }
01422   }
01423   /* If some errors occur */
01424   if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
01425   {
01426     /* USART parity error interrupt occurred ----------------------------------*/
01427     if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
01428     {
01429       husart->ErrorCode |= HAL_USART_ERROR_PE;
01430     }
01431
01432     /* USART noise error interrupt occurred --------------------------------*/
01433     if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01434     {
01435       husart->ErrorCode |= HAL_USART_ERROR_NE;
01436     }
01437
01438     /* USART frame error interrupt occurred --------------------------------*/
01439     if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01440     {
01441       husart->ErrorCode |= HAL_USART_ERROR_FE;
01442     }
01443
01444     /* USART Over-Run interrupt occurred -----------------------------------*/
01445     if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
01446     {
01447       husart->ErrorCode |= HAL_USART_ERROR_ORE;
01448     }
01449
01450     if(husart->ErrorCode != HAL_USART_ERROR_NONE)
01451     {
01452       /* USART in mode Receiver -----------------------------------------------*/
01453       if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
01454       {
01455         if(husart->State == HAL_USART_STATE_BUSY_RX)
01456         {
01457           USART_Receive_IT(husart);
01458         }
01459         else
01460         {
01461           USART_TransmitReceive_IT(husart);
01462         }
01463       }
01464       /* If Overrun error occurs, or if any error occurs in DMA mode reception,
01465       consider error as blocking */
01466       dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
01467       if(((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || dmarequest)
01468       {
01469         /* Set the USART state ready to be able to start again the process,
01470         Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
01471         USART_EndRxTransfer(husart);
01472
01473         /* Disable the USART DMA Rx request if enabled */
01474         if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
01475         {
01476           CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01477
01478           /* Abort the USART DMA Rx channel */
01479           if(husart->hdmarx != NULL)
01480           {
01481             /* Set the USART DMA Abort callback :
01482             will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
01483             husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
01484
01485             if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
01486             {
01487               /* Call Directly XferAbortCallback function in case of error */
01488               husart->hdmarx->XferAbortCallback(husart->hdmarx);
01489             }
01490           }
01491           else
01492           {
01493             /* Call user error callback */
01494             HAL_USART_ErrorCallback(husart);
01495           }
01496         }
01497         else
01498         {
01499           /* Call user error callback */
01500           HAL_USART_ErrorCallback(husart);
01501         }
01502       }
01503       else
01504       {
01505         /* Call user error callback */
01506         HAL_USART_ErrorCallback(husart);
01507         husart->ErrorCode = HAL_USART_ERROR_NONE;
01508       }
01509     }
01510     return;
01511   }
01512
01513   /* USART in mode Transmitter -----------------------------------------------*/
01514   if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
01515   {
01516     if(husart->State == HAL_USART_STATE_BUSY_TX)
01517     {
01518       USART_Transmit_IT(husart);
01519     }
01520     else
01521     {
01522       USART_TransmitReceive_IT(husart);
01523     }
01524     return;
01525   }
01526
01527   /* USART in mode Transmitter (transmission end) ----------------------------*/
01528   if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
01529   {
01530     USART_EndTransmit_IT(husart);
01531     return;
01532   }
01533 }
01534
01535 /**
01536   * @brief  Tx Transfer completed callbacks.
01537   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01538   *                 the configuration information for the specified USART module.
01539   * @retval None
01540   */
01541 __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
01542 {
01543   /* Prevent unused argument(s) compilation warning */
01544   UNUSED(husart);
01545   /* NOTE: This function should not be modified, when the callback is needed,
01546            the HAL_USART_TxCpltCallback could be implemented in the user file
01547    */
01548 }
01549
01550 /**
01551   * @brief  Tx Half Transfer completed callbacks.
01552   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01553   *                 the configuration information for the specified USART module.
01554   * @retval None
01555   */
01556 __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
01557 {
01558   /* Prevent unused argument(s) compilation warning */
01559   UNUSED(husart);
01560   /* NOTE: This function should not be modified, when the callback is needed,
01561            the HAL_USART_TxHalfCpltCallback could be implemented in the user file
01562    */
01563 }
01564
01565 /**
01566   * @brief  Rx Transfer completed callbacks.
01567   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01568   *                 the configuration information for the specified USART module.
01569   * @retval None
01570   */
01571 __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
01572 {
01573   /* Prevent unused argument(s) compilation warning */
01574   UNUSED(husart);
01575   /* NOTE: This function should not be modified, when the callback is needed,
01576            the HAL_USART_RxCpltCallback could be implemented in the user file
01577    */
01578 }
01579
01580 /**
01581   * @brief  Rx Half Transfer completed callbacks.
01582   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01583   *                 the configuration information for the specified USART module.
01584   * @retval None
01585   */
01586 __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
01587 {
01588   /* Prevent unused argument(s) compilation warning */
01589   UNUSED(husart);
01590   /* NOTE: This function should not be modified, when the callback is needed,
01591            the HAL_USART_RxHalfCpltCallback could be implemented in the user file
01592    */
01593 }
01594
01595 /**
01596   * @brief  Tx/Rx Transfers completed callback for the non-blocking process.
01597   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01598   *                 the configuration information for the specified USART module.
01599   * @retval None
01600   */
01601 __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
01602 {
01603   /* Prevent unused argument(s) compilation warning */
01604   UNUSED(husart);
01605   /* NOTE: This function should not be modified, when the callback is needed,
01606            the HAL_USART_TxRxCpltCallback could be implemented in the user file
01607    */
01608 }
01609
01610 /**
01611   * @brief  USART error callbacks.
01612   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01613   *                 the configuration information for the specified USART module.
01614   * @retval None
01615   */
01616 __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
01617 {
01618   /* Prevent unused argument(s) compilation warning */
01619   UNUSED(husart);
01620   /* NOTE: This function should not be modified, when the callback is needed,
01621            the HAL_USART_ErrorCallback could be implemented in the user file
01622    */
01623 }
01624
01625 /**
01626   * @brief  USART Abort Complete callback.
01627   * @param  husart USART handle.
01628   * @retval None
01629   */
01630 __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
01631 {
01632   /* Prevent unused argument(s) compilation warning */
01633   UNUSED(husart);
01634
01635   /* NOTE : This function should not be modified, when the callback is needed,
01636             the HAL_USART_AbortCpltCallback can be implemented in the user file.
01637    */
01638 }
01639
01640 /**
01641   * @}
01642   */
01643
01644 /** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
01645   *  @brief   USART State and Errors functions
01646   *
01647 @verbatim
01648   ==============================================================================
01649                   ##### Peripheral State and Errors functions #####
01650   ==============================================================================
01651   [..]
01652     This subsection provides a set of functions allowing to return the State of
01653     USART communication
01654     process, return Peripheral Errors occurred during communication process
01655      (+) HAL_USART_GetState() API can be helpful to check in run-time the state
01656          of the USART peripheral.
01657      (+) HAL_USART_GetError() check in run-time errors that could be occurred during
01658          communication.
01659 @endverbatim
01660   * @{
01661   */
01662
01663 /**
01664   * @brief  Returns the USART state.
01665   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01666   *                 the configuration information for the specified USART module.
01667   * @retval HAL state
01668   */
01669 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
01670 {
01671   return husart->State;
01672 }
01673
01674 /**
01675   * @brief  Return the USART error code
01676   * @param  husart : pointer to a USART_HandleTypeDef structure that contains
01677   *              the configuration information for the specified USART.
01678   * @retval USART Error Code
01679   */
01680 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
01681 {
01682   return husart->ErrorCode;
01683 }
01684
01685 /**
01686   * @}
01687   */
01688
01689 /**
01690   * @}
01691   */
01692
01693 /** @defgroup USART_Private_Functions   USART Private Functions
01694   *  @brief   USART Private functions
01695   * @{
01696   */
01697 /**
01698   * @brief  DMA USART transmit process complete callback.
01699   * @param  hdma: DMA handle
01700   * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
01701   *               the configuration information for the specified DMA module.
01702   * @retval None
01703   */
01704 static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
01705 {
01706   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01707   /* DMA Normal mode */
01708   if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
01709   {
01710     husart->TxXferCount = 0U;
01711     if(husart->State == HAL_USART_STATE_BUSY_TX)
01712     {
01713       /* Disable the DMA transfer for transmit request by resetting the DMAT bit
01714          in the USART CR3 register */
01715       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
01716
01717       /* Enable the USART Transmit Complete Interrupt */
01718       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
01719     }
01720   }
01721   /* DMA Circular mode */
01722   else
01723   {
01724     if(husart->State == HAL_USART_STATE_BUSY_TX)
01725     {
01726       HAL_USART_TxCpltCallback(husart);
01727     }
01728   }
01729 }
01730
01731 /**
01732   * @brief DMA USART transmit process half complete callback
01733   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01734   *               the configuration information for the specified DMA module.
01735   * @retval None
01736   */
01737 static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
01738 {
01739   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01740
01741   HAL_USART_TxHalfCpltCallback(husart);
01742 }
01743
01744 /**
01745   * @brief  DMA USART receive process complete callback.
01746   * @param  hdma: DMA handle
01747   * @retval None
01748   */
01749 static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
01750 {
01751   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01752   /* DMA Normal mode */
01753   if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
01754   {
01755     husart->RxXferCount = 0x00U;
01756
01757     /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
01758     CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
01759     CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01760
01761     if(husart->State == HAL_USART_STATE_BUSY_RX)
01762     {
01763       /* Disable the DMA transfer for the Transmit/Receiver requests by setting the DMAT/DMAR bit
01764          in the USART CR3 register */
01765       CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
01766
01767       husart->State= HAL_USART_STATE_READY;
01768       HAL_USART_RxCpltCallback(husart);
01769     }
01770     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01771     else
01772     {
01773       /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
01774          in the USART CR3 register */
01775       CLEAR_BIT(husart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
01776
01777       husart->State= HAL_USART_STATE_READY;
01778       HAL_USART_TxRxCpltCallback(husart);
01779     }
01780   }
01781   /* DMA circular mode */
01782   else
01783   {
01784     if(husart->State == HAL_USART_STATE_BUSY_RX)
01785     {
01786       HAL_USART_RxCpltCallback(husart);
01787     }
01788     /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
01789     else
01790     {
01791       HAL_USART_TxRxCpltCallback(husart);
01792     }
01793   }
01794 }
01795
01796 /**
01797   * @brief DMA USART receive process half complete callback
01798   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
01799   *               the configuration information for the specified DMA module.
01800   * @retval None
01801   */
01802 static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
01803 {
01804   USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
01805
01806   HAL_USART_RxHalfCpltCallback(husart);
01807 }
01808
01809 /**
01810   * @brief  DMA USART communication error callback.
01811   * @param  hdma: DMA handle
01812   * @retval None
01813   */
01814 static void USART_DMAError(DMA_HandleTypeDef *hdma)
01815 {
01816   uint32_t dmarequest = 0x00U;
01817   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01818   husart->RxXferCount = 0x00U;
01819   husart->TxXferCount = 0x00U;
01820
01821   /* Stop USART DMA Tx request if ongoing */
01822   dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
01823   if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
01824   {
01825     USART_EndTxTransfer(husart);
01826   }
01827
01828   /* Stop USART DMA Rx request if ongoing */
01829   dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
01830   if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
01831   {
01832     USART_EndRxTransfer(husart);
01833   }
01834
01835   husart->ErrorCode |= HAL_USART_ERROR_DMA;
01836   husart->State= HAL_USART_STATE_READY;
01837
01838   HAL_USART_ErrorCallback(husart);
01839 }
01840
01841 /**
01842   * @brief  This function handles USART Communication Timeout.
01843   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
01844   *                 the configuration information for the specified USART module.
01845   * @param  Flag: specifies the USART flag to check.
01846   * @param  Status: The new Flag status (SET or RESET).
01847   * @param  Tickstart: Tick start value.
01848   * @param  Timeout: Timeout duration.
01849   * @retval HAL status
01850   */
01851 static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
01852 {
01853   /* Wait until flag is set */
01854   while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
01855   {
01856     /* Check for the Timeout */
01857     if(Timeout != HAL_MAX_DELAY)
01858     {
01859       if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
01860       {
01861           /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
01862           __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
01863           __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
01864           __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
01865           __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
01866
01867         husart->State= HAL_USART_STATE_READY;
01868
01869         /* Process Unlocked */
01870         __HAL_UNLOCK(husart);
01871
01872         return HAL_TIMEOUT;
01873       }
01874     }
01875   }
01876   return HAL_OK;
01877 }
01878
01879 /**
01880   * @brief  End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
01881   * @param  husart: USART handle.
01882   * @retval None
01883   */
01884 static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
01885 {
01886   /* Disable TXEIE and TCIE interrupts */
01887   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
01888
01889   /* At end of Tx process, restore husart->State to Ready */
01890   husart->State = HAL_USART_STATE_READY;
01891 }
01892
01893 /**
01894   * @brief  End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
01895   * @param  husart: USART handle.
01896   * @retval None
01897   */
01898 static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
01899 {
01900   /* Disable RXNE, PE and ERR interrupts */
01901   CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
01902   CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
01903
01904   /* At end of Rx process, restore husart->State to Ready */
01905   husart->State = HAL_USART_STATE_READY;
01906 }
01907
01908 /**
01909   * @brief  DMA USART communication abort callback, when initiated by HAL services on Error
01910   *         (To be called at end of DMA Abort procedure following error occurrence).
01911   * @param  hdma DMA handle.
01912   * @retval None
01913   */
01914 static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
01915 {
01916   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01917   husart->RxXferCount = 0x00U;
01918   husart->TxXferCount = 0x00U;
01919
01920   HAL_USART_ErrorCallback(husart);
01921 }
01922
01923 /**
01924   * @brief  DMA USART Tx communication abort callback, when initiated by user
01925   *         (To be called at end of DMA Tx Abort procedure following user abort request).
01926   * @note   When this callback is executed, User Abort complete call back is called only if no
01927   *         Abort still ongoing for Rx DMA Handle.
01928   * @param  hdma DMA handle.
01929   * @retval None
01930   */
01931 static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
01932 {
01933   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01934
01935   husart->hdmatx->XferAbortCallback = NULL;
01936
01937   /* Check if an Abort process is still ongoing */
01938   if(husart->hdmarx != NULL)
01939   {
01940     if(husart->hdmarx->XferAbortCallback != NULL)
01941     {
01942       return;
01943     }
01944   }
01945
01946   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
01947   husart->TxXferCount = 0x00U;
01948   husart->RxXferCount = 0x00U;
01949
01950   /* Reset errorCode */
01951   husart->ErrorCode = HAL_USART_ERROR_NONE;
01952
01953   /* Restore husart->State to Ready */
01954   husart->State  = HAL_USART_STATE_READY;
01955
01956   /* Call user Abort complete callback */
01957   HAL_USART_AbortCpltCallback(husart);
01958 }
01959
01960 /**
01961   * @brief  DMA USART Rx communication abort callback, when initiated by user
01962   *         (To be called at end of DMA Rx Abort procedure following user abort request).
01963   * @note   When this callback is executed, User Abort complete call back is called only if no
01964   *         Abort still ongoing for Tx DMA Handle.
01965   * @param  hdma DMA handle.
01966   * @retval None
01967   */
01968 static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
01969 {
01970   USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
01971
01972   husart->hdmarx->XferAbortCallback = NULL;
01973
01974   /* Check if an Abort process is still ongoing */
01975   if(husart->hdmatx != NULL)
01976   {
01977     if(husart->hdmatx->XferAbortCallback != NULL)
01978     {
01979       return;
01980     }
01981   }
01982
01983   /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
01984   husart->TxXferCount = 0x00U;
01985   husart->RxXferCount = 0x00U;
01986
01987   /* Reset errorCode */
01988   husart->ErrorCode = HAL_USART_ERROR_NONE;
01989
01990   /* Restore husart->State to Ready */
01991   husart->State  = HAL_USART_STATE_READY;
01992
01993   /* Call user Abort complete callback */
01994   HAL_USART_AbortCpltCallback(husart);
01995 }
01996
01997 /**
01998   * @brief  Simplex Send an amount of data in non-blocking mode.
01999   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
02000   *                 the configuration information for the specified USART module.
02001   * @retval HAL status
02002   * @note   The USART errors are not managed to avoid the overrun error.
02003   */
02004 static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
02005 {
02006   uint16_t* tmp;
02007
02008   if(husart->State == HAL_USART_STATE_BUSY_TX)
02009   {
02010     if(husart->Init.WordLength == USART_WORDLENGTH_9B)
02011     {
02012       tmp = (uint16_t*) husart->pTxBuffPtr;
02013       WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
02014       if(husart->Init.Parity == USART_PARITY_NONE)
02015       {
02016         husart->pTxBuffPtr += 2U;
02017       }
02018       else
02019       {
02020         husart->pTxBuffPtr += 1U;
02021       }
02022     }
02023     else
02024     {
02025       WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF));
02026     }
02027
02028     if(--husart->TxXferCount == 0U)
02029     {
02030       /* Disable the USART Transmit data register empty Interrupt */
02031       __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
02032
02033       /* Enable the USART Transmit Complete Interrupt */
02034       __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
02035     }
02036     return HAL_OK;
02037   }
02038   else
02039   {
02040     return HAL_BUSY;
02041   }
02042 }
02043
02044 /**
02045   * @brief  Wraps up transmission in non blocking mode.
02046   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
02047   *                the configuration information for the specified USART module.
02048   * @retval HAL status
02049   */
02050 static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
02051 {
02052   /* Disable the USART Transmit Complete Interrupt */
02053   __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
02054
02055   /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
02056   __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
02057
02058   husart->State = HAL_USART_STATE_READY;
02059
02060   HAL_USART_TxCpltCallback(husart);
02061
02062   return HAL_OK;
02063 }
02064
02065 /**
02066   * @brief  Simplex Receive an amount of data in non-blocking mode.
02067   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
02068   *                 the configuration information for the specified USART module.
02069   * @retval HAL status
02070   */
02071 static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
02072 {
02073   uint16_t* tmp;
02074   if(husart->State == HAL_USART_STATE_BUSY_RX)
02075   {
02076     if(husart->Init.WordLength == USART_WORDLENGTH_9B)
02077     {
02078       tmp = (uint16_t*) husart->pRxBuffPtr;
02079       if(husart->Init.Parity == USART_PARITY_NONE)
02080       {
02081         *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
02082         husart->pRxBuffPtr += 2U;
02083       }
02084       else
02085       {
02086         *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
02087         husart->pRxBuffPtr += 1U;
02088       }
02089       if(--husart->RxXferCount != 0x00U)
02090       {
02091         /* Send dummy byte in order to generate the clock for the slave to send the next data */
02092         WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
02093       }
02094     }
02095     else
02096     {
02097       if(husart->Init.Parity == USART_PARITY_NONE)
02098       {
02099         *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
02100       }
02101       else
02102       {
02103         *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
02104       }
02105
02106       if(--husart->RxXferCount != 0x00U)
02107       {
02108         /* Send dummy byte in order to generate the clock for the slave to send the next data */
02109         WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF));
02110       }
02111     }
02112
02113     if(husart->RxXferCount == 0U)
02114     {
02115       /* Disable the USART RXNE Interrupt */
02116       CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
02117
02118       /* Disable the USART Parity Error Interrupt */
02119       CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
02120
02121       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
02122       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02123
02124       husart->State = HAL_USART_STATE_READY;
02125       HAL_USART_RxCpltCallback(husart);
02126
02127       return HAL_OK;
02128     }
02129     return HAL_OK;
02130   }
02131   else
02132   {
02133     return HAL_BUSY;
02134   }
02135 }
02136
02137 /**
02138   * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
02139   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
02140   *                 the configuration information for the specified USART module.
02141   * @retval HAL status
02142   */
02143 static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
02144 {
02145   uint16_t* tmp;
02146
02147   if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
02148   {
02149     if(husart->TxXferCount != 0x00U)
02150     {
02151       if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
02152       {
02153         if(husart->Init.WordLength == USART_WORDLENGTH_9B)
02154         {
02155           tmp = (uint16_t*) husart->pTxBuffPtr;
02156           WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
02157           if(husart->Init.Parity == USART_PARITY_NONE)
02158           {
02159             husart->pTxBuffPtr += 2U;
02160           }
02161           else
02162           {
02163             husart->pTxBuffPtr += 1U;
02164           }
02165         }
02166         else
02167         {
02168           WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF));
02169         }
02170         husart->TxXferCount--;
02171
02172         /* Check the latest data transmitted */
02173         if(husart->TxXferCount == 0U)
02174         {
02175           CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
02176         }
02177       }
02178     }
02179
02180     if(husart->RxXferCount != 0x00U)
02181     {
02182       if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
02183       {
02184         if(husart->Init.WordLength == USART_WORDLENGTH_9B)
02185         {
02186           tmp = (uint16_t*) husart->pRxBuffPtr;
02187           if(husart->Init.Parity == USART_PARITY_NONE)
02188           {
02189             *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
02190             husart->pRxBuffPtr += 2U;
02191           }
02192           else
02193           {
02194             *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
02195             husart->pRxBuffPtr += 1U;
02196           }
02197         }
02198         else
02199         {
02200           if(husart->Init.Parity == USART_PARITY_NONE)
02201           {
02202             *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
02203           }
02204           else
02205           {
02206             *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
02207           }
02208         }
02209         husart->RxXferCount--;
02210       }
02211     }
02212
02213     /* Check the latest data received */
02214     if(husart->RxXferCount == 0U)
02215     {
02216       /* Disable the USART RXNE Interrupt */
02217       CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
02218
02219       /* Disable the USART Parity Error Interrupt */
02220       CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
02221
02222       /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
02223       CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
02224
02225       husart->State = HAL_USART_STATE_READY;
02226
02227       HAL_USART_TxRxCpltCallback(husart);
02228
02229       return HAL_OK;
02230     }
02231
02232     return HAL_OK;
02233   }
02234   else
02235   {
02236     return HAL_BUSY;
02237   }
02238 }
02239
02240 /**
02241   * @brief  Configures the USART pferipheral.
02242   * @param  husart: pointer to a USART_HandleTypeDef structure that contains
02243   *                 the configuration information for the specified USART module.
02244   * @retval None
02245   */
02246 static void USART_SetConfig(USART_HandleTypeDef *husart)
02247 {
02248   /* Check the parameters */
02249   assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
02250   assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
02251   assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
02252   assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));
02253   assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
02254   assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
02255   assert_param(IS_USART_PARITY(husart->Init.Parity));
02256   assert_param(IS_USART_MODE(husart->Init.Mode));
02257
02258   /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
02259      receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
02260   CLEAR_BIT(husart->Instance->CR1, ((uint32_t)(USART_CR1_TE | USART_CR1_RE)));
02261
02262   /*---------------------------- USART CR2 Configuration ---------------------*/
02263   /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/
02264   /* Set CPOL bit according to husart->Init.CLKPolarity value */
02265   /* Set CPHA bit according to husart->Init.CLKPhase value */
02266   /* Set LBCL bit according to husart->Init.CLKLastBit value */
02267   /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
02268   /* Write to USART CR2 */
02269   MODIFY_REG(husart->Instance->CR2,
02270              (uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP),
02271              ((uint32_t)(USART_CLOCK_ENABLE| husart->Init.CLKPolarity | husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits)));
02272
02273   /*-------------------------- USART CR1 Configuration -----------------------*/
02274   /* Configure the USART Word Length, Parity and mode:
02275      Set the M bits according to husart->Init.WordLength value
02276      Set PCE and PS bits according to husart->Init.Parity value
02277      Set TE and RE bits according to husart->Init.Mode value */
02278   MODIFY_REG(husart->Instance->CR1,
02279              (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
02280              (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode);
02281
02282   /*-------------------------- USART CR3 Configuration -----------------------*/
02283   /* Clear CTSE and RTSE bits */
02284   CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
02285
02286   /*-------------------------- USART BRR Configuration -----------------------*/
02287   if((husart->Instance == USART1))
02288   {
02289     husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
02290   }
02291   else
02292   {
02293     husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
02294   }
02295 }
02296
02297 /**
02298   * @}
02299   */
02300
02301 #endif /* HAL_USART_MODULE_ENABLED */
02302 /**
02303   * @}
02304   */
02305
02306 /**
02307   * @}
02308   */
02309
02310 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_usart.h Source File

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stm32f1xx_hal_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_usart.h
00004   * @author  MCD Application Team
00005   * @version V1.0.5
00006   * @date    06-December-2016
00007   * @brief   Header file of USART HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_USART_H
00040 #define __STM32F1xx_HAL_USART_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup USART
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup USART_Exported_Types USART Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief USART Init Structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
00068                                            The baud rate is computed using the following formula:
00069                                            - IntegerDivider = ((PCLKx) / (16 * (husart->Init.BaudRate)))
00070                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
00071
00072   uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
00073                                            This parameter can be a value of @ref USART_Word_Length */
00074
00075   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00076                                            This parameter can be a value of @ref USART_Stop_Bits */
00077
00078   uint32_t Parity;                    /*!< Specifies the parity mode.
00079                                            This parameter can be a value of @ref USART_Parity
00080                                            @note When parity is enabled, the computed parity is inserted
00081                                                  at the MSB position of the transmitted data (9th bit when
00082                                                  the word length is set to 9 data bits; 8th bit when the
00083                                                  word length is set to 8 data bits). */
00084
00085   uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
00086                                            This parameter can be a value of @ref USART_Mode */
00087
00088   uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
00089                                            This parameter can be a value of @ref USART_Clock_Polarity */
00090
00091   uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
00092                                            This parameter can be a value of @ref USART_Clock_Phase */
00093
00094   uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
00095                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00096                                            This parameter can be a value of @ref USART_Last_Bit */
00097 }USART_InitTypeDef;
00098
00099 /**
00100   * @brief HAL State structures definition
00101   */
00102 typedef enum
00103 {
00104   HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet initialized   */
00105   HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */
00106   HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing */
00107   HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing */
00108   HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing */
00109   HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */
00110   HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state */
00111   HAL_USART_STATE_ERROR             = 0x04U     /*!< Error */
00112 }HAL_USART_StateTypeDef;
00113
00114 /**
00115   * @brief  USART handle Structure definition
00116   */
00117 typedef struct
00118 {
00119   USART_TypeDef                 *Instance;        /*!< USART registers base address        */
00120
00121   USART_InitTypeDef             Init;             /*!< Usart communication parameters      */
00122
00123   uint8_t                       *pTxBuffPtr;      /*!< Pointer to Usart Tx transfer Buffer */
00124
00125   uint16_t                      TxXferSize;       /*!< Usart Tx Transfer size              */
00126
00127   __IO uint16_t                 TxXferCount;      /*!< Usart Tx Transfer Counter           */
00128
00129   uint8_t                       *pRxBuffPtr;      /*!< Pointer to Usart Rx transfer Buffer */
00130
00131   uint16_t                      RxXferSize;       /*!< Usart Rx Transfer size              */
00132
00133   __IO uint16_t                 RxXferCount;      /*!< Usart Rx Transfer Counter           */
00134
00135   DMA_HandleTypeDef             *hdmatx;          /*!< Usart Tx DMA Handle parameters      */
00136
00137   DMA_HandleTypeDef             *hdmarx;          /*!< Usart Rx DMA Handle parameters      */
00138
00139   HAL_LockTypeDef               Lock;             /*!< Locking object                      */
00140
00141   __IO HAL_USART_StateTypeDef   State;            /*!< Usart communication state           */
00142
00143   __IO uint32_t                 ErrorCode;        /*!< USART Error code                    */
00144 }USART_HandleTypeDef;
00145 /**
00146   * @}
00147   */
00148
00149 /* Exported constants --------------------------------------------------------*/
00150 /** @defgroup USART_Exported_Constants USART Exported Constants
00151   * @{
00152   */
00153
00154 /** @defgroup USART_Error_Code USART Error Code
00155   * @brief    USART Error Code
00156   * @{
00157   */
00158 #define HAL_USART_ERROR_NONE         0x00000000U   /*!< No error            */
00159 #define HAL_USART_ERROR_PE           0x00000001U   /*!< Parity error        */
00160 #define HAL_USART_ERROR_NE           0x00000002U   /*!< Noise error         */
00161 #define HAL_USART_ERROR_FE           0x00000004U   /*!< Frame error         */
00162 #define HAL_USART_ERROR_ORE          0x00000008U   /*!< Overrun error       */
00163 #define HAL_USART_ERROR_DMA          0x00000010U   /*!< DMA transfer error  */
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup USART_Word_Length USART Word Length
00169   * @{
00170   */
00171 #define USART_WORDLENGTH_8B                  0x00000000U
00172 #define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup USART_Stop_Bits USART Number of Stop Bits
00178   * @{
00179   */
00180 #define USART_STOPBITS_1                     0x00000000U
00181 #define USART_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
00182 #define USART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
00183 #define USART_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup USART_Parity USART Parity
00189   * @{
00190   */
00191 #define USART_PARITY_NONE                    0x00000000U
00192 #define USART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
00193 #define USART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
00194 /**
00195   * @}
00196   */
00197
00198 /** @defgroup USART_Mode USART Mode
00199   * @{
00200   */
00201 #define USART_MODE_RX                        ((uint32_t)USART_CR1_RE)
00202 #define USART_MODE_TX                        ((uint32_t)USART_CR1_TE)
00203 #define USART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup USART_Clock USART Clock
00209   * @{
00210   */
00211 #define USART_CLOCK_DISABLE                 0x00000000U
00212 #define USART_CLOCK_ENABLE                  ((uint32_t)USART_CR2_CLKEN)
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup USART_Clock_Polarity USART Clock Polarity
00218   * @{
00219   */
00220 #define USART_POLARITY_LOW                   0x00000000U
00221 #define USART_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup USART_Clock_Phase USART Clock Phase
00227   * @{
00228   */
00229 #define USART_PHASE_1EDGE                    0x00000000U
00230 #define USART_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
00231 /**
00232   * @}
00233   */
00234
00235 /** @defgroup USART_Last_Bit USART Last Bit
00236   * @{
00237   */
00238 #define USART_LASTBIT_DISABLE                0x00000000U
00239 #define USART_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
00240 /**
00241   * @}
00242   */
00243
00244 /** @defgroup USART_NACK_State USART NACK State
00245   * @{
00246   */
00247 #define USART_NACK_ENABLE           ((uint32_t)USART_CR3_NACK)
00248 #define USART_NACK_DISABLE          0x00000000U
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup USART_Flags USART Flags
00254   *        Elements values convention: 0xXXXX
00255   *           - 0xXXXX  : Flag mask in the SR register
00256   * @{
00257   */
00258 #define USART_FLAG_TXE                  ((uint32_t)USART_SR_TXE)
00259 #define USART_FLAG_TC                   ((uint32_t)USART_SR_TC)
00260 #define USART_FLAG_RXNE                 ((uint32_t)USART_SR_RXNE)
00261 #define USART_FLAG_IDLE                 ((uint32_t)USART_SR_IDLE)
00262 #define USART_FLAG_ORE                  ((uint32_t)USART_SR_ORE)
00263 #define USART_FLAG_NE                   ((uint32_t)USART_SR_NE)
00264 #define USART_FLAG_FE                   ((uint32_t)USART_SR_FE)
00265 #define USART_FLAG_PE                   ((uint32_t)USART_SR_PE)
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
00271   *        Elements values convention: 0xY000XXXX
00272   *           - XXXX  : Interrupt mask in the XX register
00273   *           - Y  : Interrupt source register (2bits)
00274   *                 - 01: CR1 register
00275   *                 - 10: CR2 register
00276   *                 - 11: CR3 register
00277   *
00278   * @{
00279   */
00280
00281 #define USART_IT_PE                     ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
00282 #define USART_IT_TXE                    ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
00283 #define USART_IT_TC                     ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
00284 #define USART_IT_RXNE                   ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
00285 #define USART_IT_IDLE                   ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
00286
00287 #define USART_IT_LBD                    ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
00288
00289 #define USART_IT_CTS                    ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
00290 #define USART_IT_ERR                    ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
00291 /**
00292   * @}
00293   */
00294
00295 /**
00296   * @}
00297   */
00298
00299 /* Exported macro ------------------------------------------------------------*/
00300 /** @defgroup USART_Exported_Macros USART Exported Macros
00301   * @{
00302   */
00303
00304 /** @brief Reset USART handle state
00305   * @param  __HANDLE__: specifies the USART Handle.
00306   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00307   */
00308 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
00309
00310 /** @brief  Checks whether the specified USART flag is set or not.
00311   * @param  __HANDLE__: specifies the USART Handle.
00312   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00313   * @param  __FLAG__: specifies the flag to check.
00314   *        This parameter can be one of the following values:
00315   *            @arg USART_FLAG_TXE:  Transmit data register empty flag
00316   *            @arg USART_FLAG_TC:   Transmission Complete flag
00317   *            @arg USART_FLAG_RXNE: Receive data register not empty flag
00318   *            @arg USART_FLAG_IDLE: Idle Line detection flag
00319   *            @arg USART_FLAG_ORE:  OverRun Error flag
00320   *            @arg USART_FLAG_NE:   Noise Error flag
00321   *            @arg USART_FLAG_FE:   Framing Error flag
00322   *            @arg USART_FLAG_PE:   Parity Error flag
00323   * @retval The new state of __FLAG__ (TRUE or FALSE).
00324   */
00325 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00326
00327 /** @brief  Clears the specified USART pending flags.
00328   * @param  __HANDLE__: specifies the USART Handle.
00329   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00330   * @param  __FLAG__: specifies the flag to check.
00331   *          This parameter can be any combination of the following values:
00332   *            @arg USART_FLAG_TC:   Transmission Complete flag.
00333   *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
00334   *
00335   * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
00336   *          error) and IDLE (Idle line detected) flags are cleared by software
00337   *          sequence: a read operation to USART_SR register followed by a read
00338   *          operation to USART_DR register.
00339   * @note   RXNE flag can be also cleared by a read to the USART_DR register.
00340   * @note   TC flag can be also cleared by software sequence: a read operation to
00341   *          USART_SR register followed by a write operation to USART_DR register
00342   * @note   TXE flag is cleared only by a write to the USART_DR register
00343   *
00344   */
00345 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
00346
00347 /** @brief  Clear the USART PE pending flag.
00348   * @param  __HANDLE__: specifies the USART Handle.
00349   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00350   */
00351 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)    \
00352   do{                                           \
00353     __IO uint32_t tmpreg = 0x00U;               \
00354     tmpreg = (__HANDLE__)->Instance->SR;        \
00355     tmpreg = (__HANDLE__)->Instance->DR;        \
00356     UNUSED(tmpreg);                             \
00357   } while(0U)
00358
00359 /** @brief  Clear the USART FE pending flag.
00360   * @param  __HANDLE__: specifies the USART Handle.
00361   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00362   */
00363 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
00364
00365 /** @brief  Clear the USART NE pending flag.
00366   * @param  __HANDLE__: specifies the USART Handle.
00367   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00368   */
00369 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
00370
00371 /** @brief  Clear the USART ORE pending flag.
00372   * @param  __HANDLE__: specifies the USART Handle.
00373   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00374
00375   */
00376 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
00377
00378 /** @brief  Clear the USART IDLE pending flag.
00379   * @param  __HANDLE__: specifies the USART Handle.
00380   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00381   */
00382 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
00383
00384 /** @brief  Enable the specified USART interrupts.
00385   * @param  __HANDLE__: specifies the USART Handle.
00386   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00387   * @param  __INTERRUPT__: specifies the USART interrupt source to enable.
00388   *          This parameter can be one of the following values:
00389   *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
00390   *            @arg USART_IT_TC:   Transmission complete interrupt
00391   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00392   *            @arg USART_IT_IDLE: Idle line detection interrupt
00393   *            @arg USART_IT_PE:   Parity Error interrupt
00394   *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00395   *          This parameter can be: ENABLE or DISABLE.
00396   */
00397 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
00398                                                             (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & USART_IT_MASK)): \
00399                                                             ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
00400
00401 /** @brief  Disable the specified USART interrupts.
00402   * @param  __HANDLE__: specifies the USART Handle.
00403   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00404   * @param  __INTERRUPT__: specifies the USART interrupt source to disable.
00405   *          This parameter can be one of the following values:
00406   *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
00407   *            @arg USART_IT_TC:   Transmission complete interrupt
00408   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00409   *            @arg USART_IT_IDLE: Idle line detection interrupt
00410   *            @arg USART_IT_PE:   Parity Error interrupt
00411   *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
00412   *          This parameter can be: ENABLE or DISABLE.
00413   */
00414 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
00415                                                             (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
00416                                                              ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
00417
00418 /** @brief  Checks whether the specified USART interrupt has occurred or not.
00419   * @param  __HANDLE__: specifies the USART Handle.
00420   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00421   * @param  __IT__: specifies the USART interrupt source to check.
00422   *          This parameter can be one of the following values:
00423   *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
00424   *            @arg USART_IT_TC:  Transmission complete interrupt
00425   *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
00426   *            @arg USART_IT_IDLE: Idle line detection interrupt
00427   *            @arg USART_IT_ERR: Error interrupt
00428   *            @arg USART_IT_PE: Parity Error interrupt
00429   * @retval The new state of __IT__ (TRUE or FALSE).
00430   */
00431 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
00432                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
00433
00434 /** @brief  Enable USART
00435   * @param  __HANDLE__: specifies the USART Handle.
00436   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00437   */
00438 #define __HAL_USART_ENABLE(__HANDLE__)               SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
00439
00440 /** @brief  Disable USART
00441   * @param  __HANDLE__: specifies the USART Handle.
00442   *         USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
00443   */
00444 #define __HAL_USART_DISABLE(__HANDLE__)              CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
00445 /**
00446   * @}
00447   */
00448 /* Exported functions --------------------------------------------------------*/
00449 /** @addtogroup USART_Exported_Functions
00450   * @{
00451   */
00452
00453 /** @addtogroup USART_Exported_Functions_Group1
00454   * @{
00455   */
00456 /* Initialization/de-initialization functions  **********************************/
00457 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
00458 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
00459 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
00460 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
00461 /**
00462   * @}
00463   */
00464
00465 /** @addtogroup USART_Exported_Functions_Group2
00466   * @{
00467   */
00468 /* IO operation functions *******************************************************/
00469 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
00470 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00471 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
00472 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00473 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00474 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
00475 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
00476 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
00477 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
00478 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
00479 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
00480 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
00481 /* Transfer Abort functions */
00482 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
00483 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
00484
00485 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
00486 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
00487 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
00488 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
00489 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
00490 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
00491 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
00492 void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
00493 /**
00494   * @}
00495   */
00496
00497 /** @addtogroup USART_Exported_Functions_Group3
00498   * @{
00499   */
00500 /* Peripheral State functions  ************************************************/
00501 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
00502 uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
00503 /**
00504   * @}
00505   */
00506
00507 /**
00508   * @}
00509   */
00510 /* Private types -------------------------------------------------------------*/
00511 /* Private variables ---------------------------------------------------------*/
00512 /* Private constants ---------------------------------------------------------*/
00513 /** @defgroup USART_Private_Constants USART Private Constants
00514   * @{
00515   */
00516 /** @brief USART interruptions flag mask
00517   *
00518   */
00519 #define USART_IT_MASK                   0x0000FFFFU
00520
00521 #define USART_CR1_REG_INDEX             1U
00522 #define USART_CR2_REG_INDEX             2U
00523 #define USART_CR3_REG_INDEX             3U
00524 /**
00525   * @}
00526   */
00527
00528 /* Private macros ------------------------------------------------------------*/
00529 /** @defgroup USART_Private_Macros USART Private Macros
00530   * @{
00531   */
00532 #define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
00533                                    ((NACK) == USART_NACK_DISABLE))
00534
00535 #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
00536                                    ((LASTBIT) == USART_LASTBIT_ENABLE))
00537
00538 #define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
00539
00540 #define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
00541
00542 #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
00543                                ((CLOCK) == USART_CLOCK_ENABLE))
00544
00545 #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
00546                                       ((LENGTH) == USART_WORDLENGTH_9B))
00547
00548 #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1)   || \
00549                                      ((STOPBITS) == USART_STOPBITS_0_5) || \
00550                                      ((STOPBITS) == USART_STOPBITS_1_5) || \
00551                                      ((STOPBITS) == USART_STOPBITS_2))
00552
00553 #define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
00554                                  ((PARITY) == USART_PARITY_EVEN) || \
00555                                  ((PARITY) == USART_PARITY_ODD))
00556
00557 #define IS_USART_MODE(MODE) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U))
00558
00559 #define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
00560
00561 #define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
00562
00563 #define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
00564
00565 #define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
00566
00567 #define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
00568 /**
00569   * @}
00570   */
00571
00572 /* Private functions ---------------------------------------------------------*/
00573 /** @defgroup USART_Private_Functions USART Private Functions
00574   * @{
00575   */
00576
00577 /**
00578   * @}
00579   */
00580
00581 /**
00582   * @}
00583   */
00584
00585 /**
00586   * @}
00587   */
00588
00589 #ifdef __cplusplus
00590 }
00591 #endif
00592
00593 #endif /* __STM32F1xx_HAL_USART_H */
00594
00595 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_wwdg.c Source File

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  • Src
stm32f1xx_hal_wwdg.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_wwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.5.0
00006   * @date    06-May-2016
00007   * @brief   WWDG HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Window Watchdog (WWDG) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State functions
00013   @verbatim
00014   ==============================================================================
00015                       ##### WWDG specific features #####
00016   ==============================================================================
00017   [..]
00018     Once enabled the WWDG generates a system reset on expiry of a programmed
00019     time period, unless the program refreshes the counter (downcounter)
00020     before reaching 0x3F value (i.e. a reset is generated when the counter
00021     value rolls over from 0x40 to 0x3F).
00022
00023     (+) An MCU reset is also generated if the counter value is refreshed
00024         before the counter has reached the refresh window value. This
00025         implies that the counter must be refreshed in a limited window.
00026     (+) Once enabled the WWDG cannot be disabled except by a system reset.
00027     (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
00028         reset occurs.
00029     (+) The WWDG counter input clock is derived from the APB clock divided
00030         by a programmable prescaler.
00031     (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
00032     (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
00033     (+) WWDG Counter refresh is allowed between the following limits :
00034         (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
00035         (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock
00036
00037     (+) Min-max timeout value at 36 MHz(PCLK1): 910 us / 58.25 ms
00038
00039     (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
00040         operations or data logging must be performed before the actual reset is
00041         generated. When the downcounter reaches the value 0x40, an EWI interrupt
00042         is generated and the corresponding interrupt service routine (ISR) can
00043         be used to trigger specific actions (such as communications or data
00044         logging), before resetting the device.
00045         In some applications, the EWI interrupt can be used to manage a software
00046         system check and/or system recovery/graceful degradation, without
00047         generating a WWDG reset. In this case, the corresponding interrupt
00048         service routine (ISR) should reload the WWDG counter to avoid the WWDG
00049         reset, then trigger the required actions.
00050         Note:When the EWI interrupt cannot be served, e.g. due to a system lock
00051         in a higher priority task, the WWDG reset will eventually be generated.
00052
00053     (+) Debug mode : When the microcontroller enters debug mode (core halted),
00054         the WWDG counter either continues to work normally or stops, depending
00055         on DBG_WWDG_STOP configuration bit in DBG module, accessible through
00056         __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
00057
00058                      ##### How to use this driver #####
00059   ==============================================================================
00060   [..]
00061     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
00062
00063     (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
00064         Interrupt mode using using HAL_WWDG_Init() function.
00065         This enables WWDG peripheral and the downcounter starts downcounting
00066         from given counter value.
00067         Init function can be called again to modify all watchdog parameters,
00068         however if EWI mode has been set once, it can't be clear until next
00069         reset.
00070
00071     (+) The application program must refresh the WWDG counter at regular
00072         intervals during normal operation to prevent an MCU reset using
00073         HAL_WWDG_Refresh() function. This operation must occur only when
00074         the counter is lower than the window value already programmed.
00075
00076     (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
00077         the counter reaches 0x40. User can add his own code in weak function
00078         HAL_WWDG_EarlyWakeupCallback().
00079
00080      *** WWDG HAL driver macros list ***
00081      ==================================
00082      [..]
00083        Below the list of most used macros in WWDG HAL driver.
00084
00085       (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
00086       (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
00087       (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
00088
00089   @endverbatim
00090   ******************************************************************************
00091   * @attention
00092   *
00093   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00094   *
00095   * Redistribution and use in source and binary forms, with or without modification,
00096   * are permitted provided that the following conditions are met:
00097   *   1. Redistributions of source code must retain the above copyright notice,
00098   *      this list of conditions and the following disclaimer.
00099   *   2. Redistributions in binary form must reproduce the above copyright notice,
00100   *      this list of conditions and the following disclaimer in the documentation
00101   *      and/or other materials provided with the distribution.
00102   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00103   *      may be used to endorse or promote products derived from this software
00104   *      without specific prior written permission.
00105   *
00106   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00107   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00108   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00109   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00110   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00111   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00112   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00113   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00114   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00115   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00116   *
00117   ******************************************************************************
00118   */
00119
00120 /* Includes ------------------------------------------------------------------*/
00121 #include "stm32f1xx_hal.h"
00122
00123 /** @addtogroup STM32F1xx_HAL_Driver
00124   * @{
00125   */
00126
00127 #ifdef HAL_WWDG_MODULE_ENABLED
00128 /** @defgroup WWDG WWDG
00129   * @brief WWDG HAL module driver.
00130   * @{
00131   */
00132
00133 /* Private typedef -----------------------------------------------------------*/
00134 /* Private define ------------------------------------------------------------*/
00135 /* Private macro -------------------------------------------------------------*/
00136 /* Private variables ---------------------------------------------------------*/
00137 /* Private function prototypes -----------------------------------------------*/
00138 /* Exported functions --------------------------------------------------------*/
00139
00140 /** @defgroup WWDG_Exported_Functions WWDG Exported Functions
00141   * @{
00142   */
00143
00144 /** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
00145   *  @brief    Initialization and Configuration functions.
00146   *
00147 @verbatim
00148   ==============================================================================
00149           ##### Initialization and Configuration functions #####
00150   ==============================================================================
00151   [..]
00152     This section provides functions allowing to:
00153       (+) Initialize and start the WWDG according to the specified parameters
00154           in the WWDG_InitTypeDef of associated handle.
00155       (+) Initialize the WWDG MSP.
00156
00157 @endverbatim
00158   * @{
00159   */
00160
00161 /**
00162   * @brief  Initialize the WWDG according to the specified.
00163   *         parameters in the WWDG_InitTypeDef of  associated handle.
00164   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00165   *                the configuration information for the specified WWDG module.
00166   * @retval HAL status
00167   */
00168 HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
00169 {
00170   /* Check the WWDG handle allocation */
00171   if(hwwdg == NULL)
00172   {
00173     return HAL_ERROR;
00174   }
00175
00176   /* Check the parameters */
00177   assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
00178   assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
00179   assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
00180   assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
00181   assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
00182
00183   /* Init the low level hardware */
00184   HAL_WWDG_MspInit(hwwdg);
00185
00186   /* Set WWDG Counter */
00187   WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
00188
00189   /* Set WWDG Prescaler and Window */
00190   WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
00191
00192   /* Return function status */
00193   return HAL_OK;
00194 }
00195
00196 /**
00197   * @brief  Initialize the WWDG MSP.
00198   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00199   *                the configuration information for the specified WWDG module.
00200   * @note   When rewriting this function in user file, mechanism may be added
00201   *         to avoid multiple initialize when HAL_WWDG_Init function is called
00202   *         again to change parameters.
00203   * @retval None
00204   */
00205 __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
00206 {
00207   /* Prevent unused argument(s) compilation warning */
00208   UNUSED(hwwdg);
00209
00210   /* NOTE: This function should not be modified, when the callback is needed,
00211            the HAL_WWDG_MspInit could be implemented in the user file
00212    */
00213 }
00214
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
00220  *  @brief    IO operation functions
00221  *
00222 @verbatim
00223   ==============================================================================
00224                       ##### IO operation functions #####
00225   ==============================================================================
00226   [..]
00227     This section provides functions allowing to:
00228     (+) Refresh the WWDG.
00229     (+) Handle WWDG interrupt request and associated function callback.
00230
00231 @endverbatim
00232   * @{
00233   */
00234
00235 /**
00236   * @brief  Refresh the WWDG.
00237   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00238   *                the configuration information for the specified WWDG module.
00239   * @retval HAL status
00240   */
00241 HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
00242 {
00243   /* Write to WWDG CR the WWDG Counter value to refresh with */
00244   WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
00245
00246   /* Return function status */
00247   return HAL_OK;
00248 }
00249
00250 /**
00251   * @brief  Handle WWDG interrupt request.
00252   * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
00253   *         or data logging must be performed before the actual reset is generated.
00254   *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
00255   *         EWIMode set to WWDG_EWI_ENABLE.
00256   *         When the downcounter reaches the value 0x40, and EWI interrupt is
00257   *         generated and the corresponding Interrupt Service Routine (ISR) can
00258   *         be used to trigger specific actions (such as communications or data
00259   *         logging), before resetting the device.
00260   * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
00261   *                the configuration information for the specified WWDG module.
00262   * @retval None
00263   */
00264 void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
00265 {
00266   /* Check if Early Wakeup Interrupt is enable */
00267   if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
00268   {
00269     /* Check if WWDG Early Wakeup Interrupt occurred */
00270     if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
00271     {
00272       /* Clear the WWDG Early Wakeup flag */
00273       __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
00274
00275       /* Early Wakeup callback */
00276       HAL_WWDG_EarlyWakeupCallback(hwwdg);
00277     }
00278   }
00279 }
00280
00281 /**
00282   * @brief  WWDG Early Wakeup callback.
00283   * @param  hwwdg : pointer to a WWDG_HandleTypeDef structure that contains
00284   *                the configuration information for the specified WWDG module.
00285   * @retval None
00286   */
00287 __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
00288 {
00289   /* Prevent unused argument(s) compilation warning */
00290   UNUSED(hwwdg);
00291
00292   /* NOTE: This function should not be modified, when the callback is needed,
00293            the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
00294    */
00295 }
00296
00297 /**
00298   * @}
00299   */
00300
00301 /**
00302   * @}
00303   */
00304
00305 #endif /* HAL_WWDG_MODULE_ENABLED */
00306 /**
00307   * @}
00308   */
00309
00310 /**
00311   * @}
00312   */
00313
00314 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_hal_wwdg.h Source File

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stm32f1xx_hal_wwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_hal_wwdg.h
00004   * @author  MCD Application Team
00005   * @version V1.5.0
00006   * @date    06-May-2016
00007   * @brief   Header file of WWDG HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_HAL_WWDG_H
00040 #define __STM32F1xx_HAL_WWDG_H
00041
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx_hal_def.h"
00048
00049 /** @addtogroup STM32F1xx_HAL_Driver
00050   * @{
00051   */
00052
00053 /** @addtogroup WWDG
00054   * @{
00055   */
00056
00057 /* Exported types ------------------------------------------------------------*/
00058 /** @defgroup WWDG_Exported_Types WWDG Exported Types
00059   * @{
00060   */
00061
00062 /**
00063   * @brief  WWDG Init structure definition
00064   */
00065 typedef struct
00066 {
00067   uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.
00068                                This parameter can be a value of @ref WWDG_Prescaler */
00069
00070   uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.
00071                                This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
00072
00073   uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.
00074                                This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
00075
00076   uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
00077                                This parameter can be a value of @ref WWDG_EWI_Mode */
00078
00079 }WWDG_InitTypeDef;
00080
00081 /**
00082   * @brief  WWDG handle Structure definition
00083   */
00084 typedef struct
00085 {
00086   WWDG_TypeDef                 *Instance;  /*!< Register base address    */
00087
00088   WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
00089
00090 }WWDG_HandleTypeDef;
00091 /**
00092   * @}
00093   */
00094
00095 /* Exported constants --------------------------------------------------------*/
00096
00097 /** @defgroup WWDG_Exported_Constants WWDG Exported Constants
00098   * @{
00099   */
00100
00101 /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
00102   * @{
00103   */
00104 #define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */
00105 /**
00106   * @}
00107   */
00108
00109 /** @defgroup WWDG_Flag_definition WWDG Flag definition
00110   * @brief WWDG Flag definition
00111   * @{
00112   */
00113 #define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup WWDG_Prescaler WWDG Prescaler
00119   * @{
00120   */
00121 #define WWDG_PRESCALER_1                 0x00000000U  /*!< WWDG counter clock = (PCLK1/4096)/1 */
00122 #define WWDG_PRESCALER_2                  WWDG_CFR_WDGTB0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
00123 #define WWDG_PRESCALER_4                  WWDG_CFR_WDGTB1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
00124 #define WWDG_PRESCALER_8                  WWDG_CFR_WDGTB  /*!< WWDG counter clock = (PCLK1/4096)/8 */
00125 /**
00126   * @}
00127   */
00128
00129 /** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
00130   * @{
00131   */
00132 #define WWDG_EWI_DISABLE                    0x00000000U       /*!< EWI Disable */
00133 #define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */
00134 /**
00135   * @}
00136   */
00137
00138 /**
00139   * @}
00140   */
00141
00142 /* Private macros ------------------------------------------------------------*/
00143
00144 /** @defgroup WWDG_Private_Macros WWDG Private Macros
00145   * @{
00146   */
00147 #define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1) || \
00148                                              ((__PRESCALER__) == WWDG_PRESCALER_2) || \
00149                                              ((__PRESCALER__) == WWDG_PRESCALER_4) || \
00150                                              ((__PRESCALER__) == WWDG_PRESCALER_8))
00151
00152 #define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
00153
00154 #define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
00155
00156 #define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \
00157                                              ((__MODE__) == WWDG_EWI_DISABLE))
00158 /**
00159   * @}
00160   */
00161
00162
00163 /* Exported macros ------------------------------------------------------------*/
00164
00165 /** @defgroup WWDG_Exported_Macros WWDG Exported Macros
00166   * @{
00167   */
00168
00169 /**
00170   * @brief  Enables the WWDG peripheral.
00171   * @param  __HANDLE__: WWDG handle
00172   * @retval None
00173   */
00174 #define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
00175
00176 /**
00177   * @brief  Enables the WWDG early wakeup interrupt.
00178   * @param  __HANDLE__: WWDG handle
00179   * @param  __INTERRUPT__  specifies the interrupt to enable.
00180   *         This parameter can be one of the following values:
00181   *            @arg WWDG_IT_EWI: Early wakeup interrupt
00182   * @note   Once enabled this interrupt cannot be disabled except by a system reset.
00183   * @retval None
00184   */
00185 #define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
00186
00187 /**
00188   * @brief  Checks whether the selected WWDG interrupt has occurred or not.
00189   * @param  __HANDLE__  WWDG handle
00190   * @param  __INTERRUPT__  specifies the it to check.
00191   *        This parameter can be one of the following values:
00192   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
00193   * @retval The new state of WWDG_FLAG (SET or RESET).
00194   */
00195 #define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)       __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
00196
00197 /** @brief  Clear the WWDG's interrupt pending bits
00198   *         bits to clear the selected interrupt pending bits.
00199   * @param  __HANDLE__: WWDG handle
00200   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
00201   *         This parameter can be one of the following values:
00202   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00203   */
00204 #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)     __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
00205
00206 /**
00207   * @brief  Check whether the specified WWDG flag is set or not.
00208   * @param  __HANDLE__  WWDG handle
00209   * @param  __FLAG__  specifies the flag to check.
00210   *         This parameter can be one of the following values:
00211   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00212   * @retval The new state of WWDG_FLAG (SET or RESET).
00213   */
00214 #define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
00215
00216 /**
00217   * @brief  Clears the WWDG's pending flags.
00218   * @param  __HANDLE__: WWDG handle
00219   * @param  __FLAG__: specifies the flag to clear.
00220   *         This parameter can be one of the following values:
00221   *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
00222   * @retval None
00223   */
00224 #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
00225
00226 /** @brief  Checks if the specified WWDG interrupt source is enabled or disabled.
00227   * @param  __HANDLE__: WWDG Handle.
00228   * @param  __INTERRUPT__: specifies the WWDG interrupt source to check.
00229   *          This parameter can be one of the following values:
00230   *            @arg WWDG_IT_EWI: Early Wakeup Interrupt
00231   * @retval state of __INTERRUPT__ (TRUE or FALSE).
00232   */
00233 #define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
00234
00235 /**
00236   * @}
00237   */
00238
00239 /* Exported functions --------------------------------------------------------*/
00240 /** @addtogroup WWDG_Exported_Functions
00241   * @{
00242   */
00243
00244 /** @addtogroup WWDG_Exported_Functions_Group1
00245   * @{
00246   */
00247 /* Initialization/de-initialization functions  **********************************/
00248 HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
00249 void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
00250 /**
00251   * @}
00252   */
00253
00254 /** @addtogroup WWDG_Exported_Functions_Group2
00255   * @{
00256   */
00257 /* I/O operation functions ******************************************************/
00258 HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
00259 void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
00260 void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
00261 /**
00262   * @}
00263   */
00264
00265 /**
00266   * @}
00267   */
00268
00269 /**
00270   * @}
00271   */
00272
00273 /**
00274   * @}
00275   */
00276
00277 #ifdef __cplusplus
00278 }
00279 #endif
00280
00281 #endif /* __STM32F1xx_HAL_WWDG_H */
00282
00283 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_adc.c Source File

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stm32f1xx_ll_adc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_adc.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   ADC LL module driver
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_adc.h"
00041 #include "stm32f1xx_ll_bus.h"
00042
00043 #ifdef  USE_FULL_ASSERT
00044   #include "stm32_assert.h"
00045 #else
00046   #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
00054
00055 /** @addtogroup ADC_LL ADC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063
00064 /** @addtogroup ADC_LL_Private_Macros
00065   * @{
00066   */
00067
00068 /* Check of parameters for configuration of ADC hierarchical scope:           */
00069 /* common to several ADC instances.                                           */
00070 /* Check of parameters for configuration of ADC hierarchical scope:           */
00071 /* ADC instance.                                                              */
00072 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
00073   (   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \
00074    || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
00075   )
00076
00077 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__)                           \
00078   (   ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE)                        \
00079    || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE)                         \
00080   )
00081
00082 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__)                             \
00083   (   ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE)                             \
00084    || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE)                              \
00085   )
00086
00087 /* Check of parameters for configuration of ADC hierarchical scope:           */
00088 /* ADC group regular                                                          */
00089 #if defined(ADC3)
00090 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
00091   ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))              \
00092     ? (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                  \
00093        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)              \
00094        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)              \
00095        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)              \
00096        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)              \
00097        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)             \
00098        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)              \
00099        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)           \
00100        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)             \
00101       )                                                                        \
00102       :                                                                        \
00103       (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                  \
00104        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)              \
00105        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)              \
00106        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)              \
00107        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)              \
00108        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3)        \
00109        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1)              \
00110        || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3)              \
00111       )                                                                        \
00112   )
00113 #else
00114 #if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
00115 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00116   (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
00117    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00118    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
00119    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
00120    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00121    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00122    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
00123    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00124    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
00125   )
00126 #else
00127 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
00128   (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
00129    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
00130    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
00131    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
00132    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
00133    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
00134    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
00135    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
00136   )
00137 #endif
00138 #endif
00139 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
00140   (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
00141    || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
00142   )
00143
00144 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
00145   (   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \
00146    || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
00147   )
00148
00149 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
00150   (   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
00151    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
00152    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
00153    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
00154    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
00155    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
00156    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
00157    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
00158    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
00159    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
00160    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
00161    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
00162    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
00163    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
00164    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
00165    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
00166   )
00167
00168 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
00169   (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
00170    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
00171    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
00172    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
00173    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
00174    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
00175    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
00176    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
00177    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
00178   )
00179
00180 /* Check of parameters for configuration of ADC hierarchical scope:           */
00181 /* ADC group injected                                                         */
00182 #if defined(ADC3)
00183 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
00184   ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))              \
00185     ? (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                  \
00186        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)             \
00187        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)              \
00188        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)             \
00189        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)              \
00190        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)              \
00191        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)             \
00192        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)           \
00193        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)              \
00194       )                                                                        \
00195       :                                                                        \
00196       (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                  \
00197        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)             \
00198        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)              \
00199        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)              \
00200        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)              \
00201        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3)         \
00202        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO)             \
00203        || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4)              \
00204       )                                                                        \
00205   )
00206 #else
00207 #if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
00208 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
00209   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
00210    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00211    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00212    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00213    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
00214    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
00215    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00216    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
00217    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
00218   )
00219 #else
00220 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
00221   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
00222    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
00223    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
00224    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
00225    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
00226    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
00227    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
00228    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
00229   )
00230 #endif
00231 #endif
00232 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
00233   (   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
00234    || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
00235   )
00236
00237 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
00238   (   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
00239    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
00240    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
00241    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
00242   )
00243
00244 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
00245   (   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
00246    || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
00247   )
00248
00249 #if defined(ADC_MULTIMODE_SUPPORT)
00250 /* Check of parameters for configuration of ADC hierarchical scope:           */
00251 /* multimode.                                                                 */
00252 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \
00253   (   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \
00254    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
00255    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST)                  \
00256    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW)                  \
00257    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
00258    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
00259    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
00260    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
00261    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM)              \
00262    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM)              \
00263   )
00264
00265 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \
00266   (   ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                        \
00267    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
00268    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
00269   )
00270
00271 #endif /* ADC_MULTIMODE_SUPPORT */
00272 /**
00273   * @}
00274   */
00275
00276
00277 /* Private function prototypes -----------------------------------------------*/
00278
00279 /* Exported functions --------------------------------------------------------*/
00280 /** @addtogroup ADC_LL_Exported_Functions
00281   * @{
00282   */
00283
00284 /** @addtogroup ADC_LL_EF_Init
00285   * @{
00286   */
00287
00288 /**
00289   * @brief  De-initialize registers of all ADC instances belonging to
00290   *         the same ADC common instance to their default reset values.
00291   * @param  ADCxy_COMMON ADC common instance
00292   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00293   * @retval An ErrorStatus enumeration value:
00294   *          - SUCCESS: ADC common registers are de-initialized
00295   *          - ERROR: not applicable
00296   */
00297 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
00298 {
00299   /* Check the parameters */
00300   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00301
00302   /* Force reset of ADC clock (core clock) */
00303   LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
00304
00305   /* Release reset of ADC clock (core clock) */
00306   LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
00307
00308   return SUCCESS;
00309 }
00310
00311 /**
00312   * @brief  Initialize some features of ADC common parameters
00313   *         (all ADC instances belonging to the same ADC common instance)
00314   *         and multimode (for devices with several ADC instances available).
00315   * @note   The setting of ADC common parameters is conditioned to
00316   *         ADC instances state:
00317   *         All ADC instances belonging to the same ADC common instance
00318   *         must be disabled.
00319   * @param  ADCxy_COMMON ADC common instance
00320   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
00321   * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00322   * @retval An ErrorStatus enumeration value:
00323   *          - SUCCESS: ADC common registers are initialized
00324   *          - ERROR: ADC common registers are not initialized
00325   */
00326 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
00327 {
00328   ErrorStatus status = SUCCESS;
00329
00330   /* Check the parameters */
00331   assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
00332 #if defined(ADC_MULTIMODE_SUPPORT)
00333   assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
00334 #endif /* ADC_MULTIMODE_SUPPORT */
00335
00336   /* Note: Hardware constraint (refer to description of functions             */
00337   /*       "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"):               */
00338   /*       On this STM32 serie, setting of these features is conditioned to   */
00339   /*       ADC state:                                                         */
00340   /*       All ADC instances of the ADC common group must be disabled.        */
00341   if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
00342   {
00343     /* Configuration of ADC hierarchical scope:                               */
00344     /*  - common to several ADC                                               */
00345     /*    (all ADC instances belonging to the same ADC common instance)       */
00346     /*  - multimode (if several ADC instances available on the                */
00347     /*    selected device)                                                    */
00348     /*    - Set ADC multimode configuration                                   */
00349     /*    - Set ADC multimode DMA transfer                                    */
00350     /*    - Set ADC multimode: delay between 2 sampling phases                */
00351 #if defined(ADC_MULTIMODE_SUPPORT)
00352     if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
00353     {
00354       MODIFY_REG(ADCxy_COMMON->CR1,
00355                  ADC_CR1_DUALMOD,
00356                  ADC_CommonInitStruct->Multimode
00357                 );
00358     }
00359     else
00360     {
00361       MODIFY_REG(ADCxy_COMMON->CR1,
00362                  ADC_CR1_DUALMOD,
00363                  LL_ADC_MULTI_INDEPENDENT
00364                 );
00365     }
00366 #endif
00367   }
00368   else
00369   {
00370     /* Initialization error: One or several ADC instances belonging to        */
00371     /* the same ADC common instance are not disabled.                         */
00372     status = ERROR;
00373   }
00374
00375   return status;
00376 }
00377
00378 /**
00379   * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
00380   * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
00381   *                              whose fields will be set to default values.
00382   * @retval None
00383   */
00384 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
00385 {
00386   /* Set ADC_CommonInitStruct fields to default values */
00387   /* Set fields of ADC common */
00388   /* (all ADC instances belonging to the same ADC common instance) */
00389
00390 #if defined(ADC_MULTIMODE_SUPPORT)
00391   /* Set fields of ADC multimode */
00392   ADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;
00393 #endif /* ADC_MULTIMODE_SUPPORT */
00394 }
00395
00396 /**
00397   * @brief  De-initialize registers of the selected ADC instance
00398   *         to their default reset values.
00399   * @note   To reset all ADC instances quickly (perform a hard reset),
00400   *         use function @ref LL_ADC_CommonDeInit().
00401   * @param  ADCx ADC instance
00402   * @retval An ErrorStatus enumeration value:
00403   *          - SUCCESS: ADC registers are de-initialized
00404   *          - ERROR: ADC registers are not de-initialized
00405   */
00406 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
00407 {
00408   ErrorStatus status = SUCCESS;
00409
00410   /* Check the parameters */
00411   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00412
00413   /* Disable ADC instance if not already disabled.                            */
00414   if(LL_ADC_IsEnabled(ADCx) == 1U)
00415   {
00416     /* Set ADC group regular trigger source to SW start to ensure to not      */
00417     /* have an external trigger event occurring during the conversion stop    */
00418     /* ADC disable process.                                                   */
00419     LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
00420
00421     /* Set ADC group injected trigger source to SW start to ensure to not     */
00422     /* have an external trigger event occurring during the conversion stop    */
00423     /* ADC disable process.                                                   */
00424     LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
00425
00426     /* Disable the ADC instance */
00427     LL_ADC_Disable(ADCx);
00428   }
00429
00430   /* Check whether ADC state is compliant with expected state */
00431   /* (hardware requirements of bits state to reset registers below) */
00432   if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
00433   {
00434     /* ========== Reset ADC registers ========== */
00435     /* Reset register SR */
00436     CLEAR_BIT(ADCx->SR,
00437               (  LL_ADC_FLAG_STRT
00438                | LL_ADC_FLAG_JSTRT
00439                | LL_ADC_FLAG_EOS
00440                | LL_ADC_FLAG_JEOS
00441                | LL_ADC_FLAG_AWD1 )
00442              );
00443
00444     /* Reset register CR1 */
00445   #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
00446
00447     CLEAR_BIT(ADCx->CR1,
00448               (  ADC_CR1_AWDEN   | ADC_CR1_JAWDEN  | ADC_CR1_DUALMOD
00449                | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
00450                | ADC_CR1_JAUTO   | ADC_CR1_AWDSGL  | ADC_CR1_SCAN
00451                | ADC_CR1_JEOCIE  | ADC_CR1_AWDIE   | ADC_CR1_EOCIE
00452                | ADC_CR1_AWDCH                                     )
00453              );
00454   #else
00455
00456     CLEAR_BIT(ADCx->CR1,
00457               (  ADC_CR1_AWDEN   | ADC_CR1_JAWDEN  | ADC_CR1_DISCNUM
00458                | ADC_CR1_JDISCEN | ADC_CR1_DISCEN  | ADC_CR1_JAUTO
00459                | ADC_CR1_AWDSGL  | ADC_CR1_SCAN    | ADC_CR1_JEOCIE
00460                | ADC_CR1_AWDIE   | ADC_CR1_EOCIE   | ADC_CR1_AWDCH )
00461              );
00462   #endif
00463
00464     /* Reset register CR2 */
00465     CLEAR_BIT(ADCx->CR2,
00466               (  ADC_CR2_TSVREFE
00467                | ADC_CR2_SWSTART  | ADC_CR2_EXTTRIG  | ADC_CR2_EXTSEL
00468                | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
00469                | ADC_CR2_ALIGN    | ADC_CR2_DMA
00470                | ADC_CR2_RSTCAL   | ADC_CR2_CAL
00471                | ADC_CR2_CONT     | ADC_CR2_ADON                      )
00472              );
00473
00474     /* Reset register SMPR1 */
00475     CLEAR_BIT(ADCx->SMPR1,
00476               (  ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
00477                | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
00478                | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
00479              );
00480
00481     /* Reset register SMPR2 */
00482     CLEAR_BIT(ADCx->SMPR2,
00483               (  ADC_SMPR2_SMP9
00484                | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
00485                | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
00486                | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
00487              );
00488
00489     /* Reset register JOFR1 */
00490     CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
00491     /* Reset register JOFR2 */
00492     CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
00493     /* Reset register JOFR3 */
00494     CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
00495     /* Reset register JOFR4 */
00496     CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
00497
00498     /* Reset register HTR */
00499     SET_BIT(ADCx->HTR, ADC_HTR_HT);
00500     /* Reset register LTR */
00501     CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
00502
00503     /* Reset register SQR1 */
00504     CLEAR_BIT(ADCx->SQR1,
00505               (  ADC_SQR1_L
00506                | ADC_SQR1_SQ16
00507                | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
00508              );
00509
00510     /* Reset register SQR2 */
00511     CLEAR_BIT(ADCx->SQR2,
00512               (  ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
00513                | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
00514              );
00515
00516
00517     /* Reset register JSQR */
00518     CLEAR_BIT(ADCx->JSQR,
00519               (  ADC_JSQR_JL
00520                | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
00521                | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  )
00522              );
00523
00524     /* Reset register DR */
00525     /* bits in access mode read only, no direct reset applicable */
00526
00527     /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00528     /* bits in access mode read only, no direct reset applicable */
00529
00530   }
00531
00532   return status;
00533 }
00534
00535 /**
00536   * @brief  Initialize some features of ADC instance.
00537   * @note   These parameters have an impact on ADC scope: ADC instance.
00538   *         Affects both group regular and group injected (availability
00539   *         of ADC group injected depends on STM32 families).
00540   *         Refer to corresponding unitary functions into
00541   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00542   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00543   *         is conditioned to ADC state:
00544   *         ADC instance must be disabled.
00545   *         This condition is applied to all ADC features, for efficiency
00546   *         and compatibility over all STM32 families. However, the different
00547   *         features can be set under different ADC state conditions
00548   *         (setting possible with ADC enabled without conversion on going,
00549   *         ADC enabled with conversion on going, ...)
00550   *         Each feature can be updated afterwards with a unitary function
00551   *         and potentially with ADC in a different state than disabled,
00552   *         refer to description of each function for setting
00553   *         conditioned to ADC state.
00554   * @note   After using this function, some other features must be configured
00555   *         using LL unitary functions.
00556   *         The minimum configuration remaining to be done is:
00557   *          - Set ADC group regular or group injected sequencer:
00558   *            map channel on the selected sequencer rank.
00559   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
00560   *          - Set ADC channel sampling time
00561   *            Refer to function LL_ADC_SetChannelSamplingTime();
00562   * @param  ADCx ADC instance
00563   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00564   * @retval An ErrorStatus enumeration value:
00565   *          - SUCCESS: ADC registers are initialized
00566   *          - ERROR: ADC registers are not initialized
00567   */
00568 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
00569 {
00570   ErrorStatus status = SUCCESS;
00571
00572   /* Check the parameters */
00573   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00574
00575   assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
00576   assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
00577
00578   /* Note: Hardware constraint (refer to description of this function):       */
00579   /*       ADC instance must be disabled.                                     */
00580   if(LL_ADC_IsEnabled(ADCx) == 0U)
00581   {
00582     /* Configuration of ADC hierarchical scope:                               */
00583     /*  - ADC instance                                                        */
00584     /*    - Set ADC conversion data alignment                                 */
00585     MODIFY_REG(ADCx->CR1,
00586                  ADC_CR1_SCAN
00587               ,
00588                  ADC_InitStruct->SequencersScanMode
00589               );
00590
00591     MODIFY_REG(ADCx->CR2,
00592                  ADC_CR2_ALIGN
00593               ,
00594                  ADC_InitStruct->DataAlignment
00595               );
00596
00597   }
00598   else
00599   {
00600     /* Initialization error: ADC instance is not disabled. */
00601     status = ERROR;
00602   }
00603   return status;
00604 }
00605
00606 /**
00607   * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
00608   * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
00609   *                        whose fields will be set to default values.
00610   * @retval None
00611   */
00612 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
00613 {
00614   /* Set ADC_InitStruct fields to default values */
00615   /* Set fields of ADC instance */
00616   ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
00617
00618   /* Enable scan mode to have a generic behavior with ADC of other            */
00619   /* STM32 families, without this setting available:                          */
00620   /* ADC group regular sequencer and ADC group injected sequencer depend      */
00621   /* only of their own configuration.                                         */
00622   ADC_InitStruct->SequencersScanMode      = LL_ADC_SEQ_SCAN_ENABLE;
00623
00624 }
00625
00626 /**
00627   * @brief  Initialize some features of ADC group regular.
00628   * @note   These parameters have an impact on ADC scope: ADC group regular.
00629   *         Refer to corresponding unitary functions into
00630   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00631   *         (functions with prefix "REG").
00632   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00633   *         is conditioned to ADC state:
00634   *         ADC instance must be disabled.
00635   *         This condition is applied to all ADC features, for efficiency
00636   *         and compatibility over all STM32 families. However, the different
00637   *         features can be set under different ADC state conditions
00638   *         (setting possible with ADC enabled without conversion on going,
00639   *         ADC enabled with conversion on going, ...)
00640   *         Each feature can be updated afterwards with a unitary function
00641   *         and potentially with ADC in a different state than disabled,
00642   *         refer to description of each function for setting
00643   *         conditioned to ADC state.
00644   * @note   After using this function, other features must be configured
00645   *         using LL unitary functions.
00646   *         The minimum configuration remaining to be done is:
00647   *          - Set ADC group regular or group injected sequencer:
00648   *            map channel on the selected sequencer rank.
00649   *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
00650   *          - Set ADC channel sampling time
00651   *            Refer to function LL_ADC_SetChannelSamplingTime();
00652   * @param  ADCx ADC instance
00653   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00654   * @retval An ErrorStatus enumeration value:
00655   *          - SUCCESS: ADC registers are initialized
00656   *          - ERROR: ADC registers are not initialized
00657   */
00658 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
00659 {
00660   ErrorStatus status = SUCCESS;
00661
00662   /* Check the parameters */
00663   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00664 #if defined(ADC3)
00665   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
00666 #else
00667   assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
00668 #endif
00669   assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
00670   if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00671   {
00672     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
00673   }
00674   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
00675   assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
00676
00677   /* Note: Hardware constraint (refer to description of this function):       */
00678   /*       ADC instance must be disabled.                                     */
00679   if(LL_ADC_IsEnabled(ADCx) == 0U)
00680   {
00681     /* Configuration of ADC hierarchical scope:                               */
00682     /*  - ADC group regular                                                   */
00683     /*    - Set ADC group regular trigger source                              */
00684     /*    - Set ADC group regular sequencer length                            */
00685     /*    - Set ADC group regular sequencer discontinuous mode                */
00686     /*    - Set ADC group regular continuous mode                             */
00687     /*    - Set ADC group regular conversion data transfer: no transfer or    */
00688     /*      transfer by DMA, and DMA requests mode                            */
00689     /* Note: On this STM32 serie, ADC trigger edge is set when starting       */
00690     /*       ADC conversion.                                                  */
00691     /*       Refer to function @ref LL_ADC_REG_StartConversionExtTrig().      */
00692     if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00693     {
00694       MODIFY_REG(ADCx->CR1,
00695                    ADC_CR1_DISCEN
00696                  | ADC_CR1_DISCNUM
00697                 ,
00698                    ADC_REG_InitStruct->SequencerLength
00699                  | ADC_REG_InitStruct->SequencerDiscont
00700                 );
00701     }
00702     else
00703     {
00704       MODIFY_REG(ADCx->CR1,
00705                    ADC_CR1_DISCEN
00706                  | ADC_CR1_DISCNUM
00707                 ,
00708                    ADC_REG_InitStruct->SequencerLength
00709                  | LL_ADC_REG_SEQ_DISCONT_DISABLE
00710                 );
00711     }
00712
00713     MODIFY_REG(ADCx->CR2,
00714                  ADC_CR2_EXTSEL
00715                | ADC_CR2_CONT
00716                | ADC_CR2_DMA
00717               ,
00718                  ADC_REG_InitStruct->TriggerSource
00719                | ADC_REG_InitStruct->ContinuousMode
00720                | ADC_REG_InitStruct->DMATransfer
00721               );
00722
00723     /* Set ADC group regular sequencer length and scan direction */
00724     /* Note: Hardware constraint (refer to description of this function):     */
00725     /* Note: If ADC instance feature scan mode is disabled                    */
00726     /*       (refer to  ADC instance initialization structure                 */
00727     /*       parameter @ref SequencersScanMode                                */
00728     /*       or function @ref LL_ADC_SetSequencersScanMode() ),               */
00729     /*       this parameter is discarded.                                     */
00730     LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
00731   }
00732   else
00733   {
00734     /* Initialization error: ADC instance is not disabled. */
00735     status = ERROR;
00736   }
00737   return status;
00738 }
00739
00740 /**
00741   * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
00742   * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
00743   *                            whose fields will be set to default values.
00744   * @retval None
00745   */
00746 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
00747 {
00748   /* Set ADC_REG_InitStruct fields to default values */
00749   /* Set fields of ADC group regular */
00750   /* Note: On this STM32 serie, ADC trigger edge is set when starting         */
00751   /*       ADC conversion.                                                    */
00752   /*       Refer to function @ref LL_ADC_REG_StartConversionExtTrig().        */
00753   ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
00754   ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
00755   ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
00756   ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
00757   ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
00758 }
00759
00760 /**
00761   * @brief  Initialize some features of ADC group injected.
00762   * @note   These parameters have an impact on ADC scope: ADC group injected.
00763   *         Refer to corresponding unitary functions into
00764   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00765   *         (functions with prefix "INJ").
00766   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00767   *         is conditioned to ADC state:
00768   *         ADC instance must be disabled.
00769   *         This condition is applied to all ADC features, for efficiency
00770   *         and compatibility over all STM32 families. However, the different
00771   *         features can be set under different ADC state conditions
00772   *         (setting possible with ADC enabled without conversion on going,
00773   *         ADC enabled with conversion on going, ...)
00774   *         Each feature can be updated afterwards with a unitary function
00775   *         and potentially with ADC in a different state than disabled,
00776   *         refer to description of each function for setting
00777   *         conditioned to ADC state.
00778   * @note   After using this function, other features must be configured
00779   *         using LL unitary functions.
00780   *         The minimum configuration remaining to be done is:
00781   *          - Set ADC group injected sequencer:
00782   *            map channel on the selected sequencer rank.
00783   *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
00784   *          - Set ADC channel sampling time
00785   *            Refer to function LL_ADC_SetChannelSamplingTime();
00786   * @param  ADCx ADC instance
00787   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
00788   * @retval An ErrorStatus enumeration value:
00789   *          - SUCCESS: ADC registers are initialized
00790   *          - ERROR: ADC registers are not initialized
00791   */
00792 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
00793 {
00794   ErrorStatus status = SUCCESS;
00795
00796   /* Check the parameters */
00797   assert_param(IS_ADC_ALL_INSTANCE(ADCx));
00798 #if defined(ADC3)
00799   assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
00800 #else
00801   assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
00802 #endif
00803   assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
00804   if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
00805   {
00806     assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
00807   }
00808   assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
00809
00810   /* Note: Hardware constraint (refer to description of this function):       */
00811   /*       ADC instance must be disabled.                                     */
00812   if(LL_ADC_IsEnabled(ADCx) == 0U)
00813   {
00814     /* Configuration of ADC hierarchical scope:                               */
00815     /*  - ADC group injected                                                  */
00816     /*    - Set ADC group injected trigger source                             */
00817     /*    - Set ADC group injected sequencer length                           */
00818     /*    - Set ADC group injected sequencer discontinuous mode               */
00819     /*    - Set ADC group injected conversion trigger: independent or         */
00820     /*      from ADC group regular                                            */
00821     /* Note: On this STM32 serie, ADC trigger edge is set when starting       */
00822     /*       ADC conversion.                                                  */
00823     /*       Refer to function @ref LL_ADC_INJ_StartConversionExtTrig().      */
00824     if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
00825     {
00826       MODIFY_REG(ADCx->CR1,
00827                    ADC_CR1_JDISCEN
00828                  | ADC_CR1_JAUTO
00829                 ,
00830                    ADC_INJ_InitStruct->SequencerDiscont
00831                  | ADC_INJ_InitStruct->TrigAuto
00832                 );
00833     }
00834     else
00835     {
00836       MODIFY_REG(ADCx->CR1,
00837                    ADC_CR1_JDISCEN
00838                  | ADC_CR1_JAUTO
00839                 ,
00840                    LL_ADC_REG_SEQ_DISCONT_DISABLE
00841                  | ADC_INJ_InitStruct->TrigAuto
00842                 );
00843     }
00844
00845     MODIFY_REG(ADCx->CR2,
00846                ADC_CR2_JEXTSEL
00847               ,
00848                ADC_INJ_InitStruct->TriggerSource
00849               );
00850
00851     /* Note: Hardware constraint (refer to description of this function):     */
00852     /* Note: If ADC instance feature scan mode is disabled                    */
00853     /*       (refer to  ADC instance initialization structure                 */
00854     /*       parameter @ref SequencersScanMode                                */
00855     /*       or function @ref LL_ADC_SetSequencersScanMode() ),               */
00856     /*       this parameter is discarded.                                     */
00857     LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
00858   }
00859   else
00860   {
00861     /* Initialization error: ADC instance is not disabled. */
00862     status = ERROR;
00863   }
00864   return status;
00865 }
00866
00867 /**
00868   * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
00869   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
00870   *                            whose fields will be set to default values.
00871   * @retval None
00872   */
00873 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
00874 {
00875   /* Set ADC_INJ_InitStruct fields to default values */
00876   /* Set fields of ADC group injected */
00877   ADC_INJ_InitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
00878   ADC_INJ_InitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
00879   ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
00880   ADC_INJ_InitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
00881 }
00882
00883 /**
00884   * @}
00885   */
00886
00887 /**
00888   * @}
00889   */
00890
00891 /**
00892   * @}
00893   */
00894
00895 #endif /* ADC1 || ADC2 || ADC3 */
00896
00897 /**
00898   * @}
00899   */
00900
00901 #endif /* USE_FULL_LL_DRIVER */
00902
00903 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_adc.h Source File

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stm32f1xx_ll_adc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_adc.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of ADC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_ADC_H
00040 #define __STM32F1xx_LL_ADC_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
00054
00055 /** @defgroup ADC_LL ADC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
00064   * @{
00065   */
00066
00067 /* Internal mask for ADC group regular sequencer:                             */
00068 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
00069 /* - sequencer register offset                                                */
00070 /* - sequencer rank bits position into the selected register                  */
00071
00072 /* Internal register offset for ADC group regular sequencer configuration */
00073 /* (offset placed into a spare area of literal definition) */
00074 #define ADC_SQR1_REGOFFSET                 0x00000000U
00075 #define ADC_SQR2_REGOFFSET                 0x00000100U
00076 #define ADC_SQR3_REGOFFSET                 0x00000200U
00077 #define ADC_SQR4_REGOFFSET                 0x00000300U
00078
00079 #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
00080 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00081
00082 /* Definition of ADC group regular sequencer bits information to be inserted  */
00083 /* into ADC group regular sequencer ranks literals definition.                */
00084 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
00085 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
00086 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
00087 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
00088 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
00089 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
00090 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
00091 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
00092 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
00093 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
00094 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
00095 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
00096 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
00097 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
00098 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
00099 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
00100
00101 /* Internal mask for ADC group injected sequencer:                            */
00102 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
00103 /* - data register offset                                                     */
00104 /* - offset register offset                                                   */
00105 /* - sequencer rank bits position into the selected register                  */
00106
00107 /* Internal register offset for ADC group injected data register */
00108 /* (offset placed into a spare area of literal definition) */
00109 #define ADC_JDR1_REGOFFSET                 0x00000000U
00110 #define ADC_JDR2_REGOFFSET                 0x00000100U
00111 #define ADC_JDR3_REGOFFSET                 0x00000200U
00112 #define ADC_JDR4_REGOFFSET                 0x00000300U
00113
00114 /* Internal register offset for ADC group injected offset configuration */
00115 /* (offset placed into a spare area of literal definition) */
00116 #define ADC_JOFR1_REGOFFSET                0x00000000U
00117 #define ADC_JOFR2_REGOFFSET                0x00001000U
00118 #define ADC_JOFR3_REGOFFSET                0x00002000U
00119 #define ADC_JOFR4_REGOFFSET                0x00003000U
00120
00121 #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
00122 #define ADC_INJ_JOFRX_REGOFFSET_MASK       (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
00123 #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
00124
00125 /* Internal mask for ADC channel:                                             */
00126 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
00127 /* - channel identifier defined by number                                     */
00128 /* - channel differentiation between external channels (connected to          */
00129 /*   GPIO pins) and internal channels (connected to internal paths)           */
00130 /* - channel sampling time defined by SMPRx register offset                   */
00131 /*   and SMPx bits positions into SMPRx register                              */
00132 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CR1_AWDCH)
00133 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
00134 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
00135 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
00136 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
00137
00138 /* Channel differentiation between external and internal channels */
00139 #define ADC_CHANNEL_ID_INTERNAL_CH         0x80000000U   /* Marker of internal channel */
00140 #define ADC_CHANNEL_ID_INTERNAL_CH_2       0x40000000U   /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
00141 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
00142
00143 /* Internal register offset for ADC channel sampling time configuration */
00144 /* (offset placed into a spare area of literal definition) */
00145 #define ADC_SMPR1_REGOFFSET                0x00000000U
00146 #define ADC_SMPR2_REGOFFSET                0x02000000U
00147 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
00148
00149 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    0x01F00000U
00150 #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
00151
00152 /* Definition of channels ID number information to be inserted into           */
00153 /* channels literals definition.                                              */
00154 #define ADC_CHANNEL_0_NUMBER               0x00000000U
00155 #define ADC_CHANNEL_1_NUMBER               (                                                                        ADC_CR1_AWDCH_0)
00156 #define ADC_CHANNEL_2_NUMBER               (                                                      ADC_CR1_AWDCH_1                  )
00157 #define ADC_CHANNEL_3_NUMBER               (                                                      ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
00158 #define ADC_CHANNEL_4_NUMBER               (                                    ADC_CR1_AWDCH_2                                    )
00159 #define ADC_CHANNEL_5_NUMBER               (                                    ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
00160 #define ADC_CHANNEL_6_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
00161 #define ADC_CHANNEL_7_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
00162 #define ADC_CHANNEL_8_NUMBER               (                  ADC_CR1_AWDCH_3                                                      )
00163 #define ADC_CHANNEL_9_NUMBER               (                  ADC_CR1_AWDCH_3                                     | ADC_CR1_AWDCH_0)
00164 #define ADC_CHANNEL_10_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1                  )
00165 #define ADC_CHANNEL_11_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
00166 #define ADC_CHANNEL_12_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                                    )
00167 #define ADC_CHANNEL_13_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)
00168 #define ADC_CHANNEL_14_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )
00169 #define ADC_CHANNEL_15_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
00170 #define ADC_CHANNEL_16_NUMBER              (ADC_CR1_AWDCH_4                                                                        )
00171 #define ADC_CHANNEL_17_NUMBER              (ADC_CR1_AWDCH_4                                                       | ADC_CR1_AWDCH_0)
00172
00173 /* Definition of channels sampling time information to be inserted into       */
00174 /* channels literals definition.                                              */
00175 #define ADC_CHANNEL_0_SMP                  (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
00176 #define ADC_CHANNEL_1_SMP                  (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
00177 #define ADC_CHANNEL_2_SMP                  (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
00178 #define ADC_CHANNEL_3_SMP                  (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
00179 #define ADC_CHANNEL_4_SMP                  (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
00180 #define ADC_CHANNEL_5_SMP                  (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
00181 #define ADC_CHANNEL_6_SMP                  (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
00182 #define ADC_CHANNEL_7_SMP                  (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
00183 #define ADC_CHANNEL_8_SMP                  (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
00184 #define ADC_CHANNEL_9_SMP                  (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
00185 #define ADC_CHANNEL_10_SMP                 (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
00186 #define ADC_CHANNEL_11_SMP                 (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
00187 #define ADC_CHANNEL_12_SMP                 (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
00188 #define ADC_CHANNEL_13_SMP                 (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
00189 #define ADC_CHANNEL_14_SMP                 (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
00190 #define ADC_CHANNEL_15_SMP                 (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
00191 #define ADC_CHANNEL_16_SMP                 (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
00192 #define ADC_CHANNEL_17_SMP                 (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
00193
00194 /* Internal mask for ADC analog watchdog:                                     */
00195 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
00196 /* (concatenation of multiple bits used in different analog watchdogs,        */
00197 /* (feature of several watchdogs not available on all STM32 families)).       */
00198 /* - analog watchdog 1: monitored channel defined by number,                  */
00199 /*   selection of ADC group (ADC groups regular and-or injected).             */
00200
00201 /* Internal register offset for ADC analog watchdog channel configuration */
00202 #define ADC_AWD_CR1_REGOFFSET              0x00000000U
00203
00204 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)
00205
00206 #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
00207 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)
00208
00209 /* Internal register offset for ADC analog watchdog threshold configuration */
00210 #define ADC_AWD_TR1_HIGH_REGOFFSET         0x00000000U
00211 #define ADC_AWD_TR1_LOW_REGOFFSET          0x00000001U
00212 #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
00213
00214 /* ADC registers bits positions */
00215 #define ADC_CR1_DUALMOD_BITOFFSET_POS      (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
00216
00217 /**
00218   * @}
00219   */
00220
00221
00222 /* Private macros ------------------------------------------------------------*/
00223 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
00224   * @{
00225   */
00226
00227 /**
00228   * @brief  Driver macro reserved for internal use: isolate bits with the
00229   *         selected mask and shift them to the register LSB
00230   *         (shift mask on register position bit 0).
00231   * @param  __BITS__ Bits in register 32 bits
00232   * @param  __MASK__ Mask in register 32 bits
00233   * @retval Bits in register 32 bits
00234   */
00235 #define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \
00236   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
00237
00238 /**
00239   * @brief  Driver macro reserved for internal use: set a pointer to
00240   *         a register from a register basis from which an offset
00241   *         is applied.
00242   * @param  __REG__ Register basis from which the offset is applied.
00243   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00244   * @retval Pointer to register address
00245   */
00246 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00247  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
00248
00249 /**
00250   * @}
00251   */
00252
00253
00254 /* Exported types ------------------------------------------------------------*/
00255 #if defined(USE_FULL_LL_DRIVER)
00256 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
00257   * @{
00258   */
00259
00260 /**
00261   * @brief  Structure definition of some features of ADC common parameters
00262   *         and multimode
00263   *         (all ADC instances belonging to the same ADC common instance).
00264   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
00265   *         is conditioned to ADC instances state (all ADC instances
00266   *         sharing the same ADC common instance):
00267   *         All ADC instances sharing the same ADC common instance must be
00268   *         disabled.
00269   */
00270 typedef struct
00271 {
00272   uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
00273                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
00274
00275                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
00276 } LL_ADC_CommonInitTypeDef;
00277 /**
00278   * @brief  Structure definition of some features of ADC instance.
00279   * @note   These parameters have an impact on ADC scope: ADC instance.
00280   *         Affects both group regular and group injected (availability
00281   *         of ADC group injected depends on STM32 families).
00282   *         Refer to corresponding unitary functions into
00283   *         @ref ADC_LL_EF_Configuration_ADC_Instance .
00284   * @note   The setting of these parameters by function @ref LL_ADC_Init()
00285   *         is conditioned to ADC state:
00286   *         ADC instance must be disabled.
00287   *         This condition is applied to all ADC features, for efficiency
00288   *         and compatibility over all STM32 families. However, the different
00289   *         features can be set under different ADC state conditions
00290   *         (setting possible with ADC enabled without conversion on going,
00291   *         ADC enabled with conversion on going, ...)
00292   *         Each feature can be updated afterwards with a unitary function
00293   *         and potentially with ADC in a different state than disabled,
00294   *         refer to description of each function for setting
00295   *         conditioned to ADC state.
00296   */
00297 typedef struct
00298 {
00299   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
00300                                              This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
00301
00302                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
00303
00304   uint32_t SequencersScanMode;          /*!< Set ADC scan selection.
00305                                              This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
00306
00307                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
00308
00309 } LL_ADC_InitTypeDef;
00310
00311 /**
00312   * @brief  Structure definition of some features of ADC group regular.
00313   * @note   These parameters have an impact on ADC scope: ADC group regular.
00314   *         Refer to corresponding unitary functions into
00315   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00316   *         (functions with prefix "REG").
00317   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
00318   *         is conditioned to ADC state:
00319   *         ADC instance must be disabled.
00320   *         This condition is applied to all ADC features, for efficiency
00321   *         and compatibility over all STM32 families. However, the different
00322   *         features can be set under different ADC state conditions
00323   *         (setting possible with ADC enabled without conversion on going,
00324   *         ADC enabled with conversion on going, ...)
00325   *         Each feature can be updated afterwards with a unitary function
00326   *         and potentially with ADC in a different state than disabled,
00327   *         refer to description of each function for setting
00328   *         conditioned to ADC state.
00329   */
00330 typedef struct
00331 {
00332   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
00333                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
00334                                              @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
00335                                                    (only trigger polarity available on this STM32 serie).
00336
00337                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
00338
00339   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
00340                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
00341                                              @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
00342
00343                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
00344
00345   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00346                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
00347                                              @note This parameter has an effect only if group regular sequencer is enabled
00348                                                    (scan length of 2 ranks or more).
00349
00350                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
00351
00352   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
00353                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
00354                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
00355
00356                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
00357
00358   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
00359                                              This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
00360
00361                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
00362
00363 } LL_ADC_REG_InitTypeDef;
00364
00365 /**
00366   * @brief  Structure definition of some features of ADC group injected.
00367   * @note   These parameters have an impact on ADC scope: ADC group injected.
00368   *         Refer to corresponding unitary functions into
00369   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
00370   *         (functions with prefix "INJ").
00371   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
00372   *         is conditioned to ADC state:
00373   *         ADC instance must be disabled.
00374   *         This condition is applied to all ADC features, for efficiency
00375   *         and compatibility over all STM32 families. However, the different
00376   *         features can be set under different ADC state conditions
00377   *         (setting possible with ADC enabled without conversion on going,
00378   *         ADC enabled with conversion on going, ...)
00379   *         Each feature can be updated afterwards with a unitary function
00380   *         and potentially with ADC in a different state than disabled,
00381   *         refer to description of each function for setting
00382   *         conditioned to ADC state.
00383   */
00384 typedef struct
00385 {
00386   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
00387                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
00388                                              @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
00389                                                    (only trigger polarity available on this STM32 serie).
00390
00391                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
00392
00393   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
00394                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
00395                                              @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
00396
00397                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
00398
00399   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
00400                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
00401                                              @note This parameter has an effect only if group injected sequencer is enabled
00402                                                    (scan length of 2 ranks or more).
00403
00404                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
00405
00406   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
00407                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
00408                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
00409
00410                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
00411
00412 } LL_ADC_INJ_InitTypeDef;
00413
00414 /**
00415   * @}
00416   */
00417 #endif /* USE_FULL_LL_DRIVER */
00418
00419 /* Exported constants --------------------------------------------------------*/
00420 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
00421   * @{
00422   */
00423
00424 /** @defgroup ADC_LL_EC_FLAG ADC flags
00425   * @brief    Flags defines which can be used with LL_ADC_ReadReg function
00426   * @{
00427   */
00428 #define LL_ADC_FLAG_STRT                   ADC_SR_STRT        /*!< ADC flag ADC group regular conversion start */
00429 #define LL_ADC_FLAG_EOS                    ADC_SR_EOC         /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
00430 #define LL_ADC_FLAG_JSTRT                  ADC_SR_JSTRT       /*!< ADC flag ADC group injected conversion start */
00431 #define LL_ADC_FLAG_JEOS                   ADC_SR_JEOC        /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
00432 #define LL_ADC_FLAG_AWD1                   ADC_SR_AWD         /*!< ADC flag ADC analog watchdog 1 */
00433 #if defined(ADC_MULTIMODE_SUPPORT)
00434 #define LL_ADC_FLAG_EOS_MST                ADC_SR_EOC         /*!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
00435 #define LL_ADC_FLAG_EOS_SLV                ADC_SR_EOC         /*!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
00436 #define LL_ADC_FLAG_JEOS_MST               ADC_SR_JEOC        /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
00437 #define LL_ADC_FLAG_JEOS_SLV               ADC_SR_JEOC        /*!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
00438 #define LL_ADC_FLAG_AWD1_MST               ADC_SR_AWD         /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
00439 #define LL_ADC_FLAG_AWD1_SLV               ADC_SR_AWD         /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
00440 #endif
00441 /**
00442   * @}
00443   */
00444
00445 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
00446   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
00447   * @{
00448   */
00449 #define LL_ADC_IT_EOS                      ADC_CR1_EOCIE      /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
00450 #define LL_ADC_IT_JEOS                     ADC_CR1_JEOCIE     /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
00451 #define LL_ADC_IT_AWD1                     ADC_CR1_AWDIE      /*!< ADC interruption ADC analog watchdog 1 */
00452 /**
00453   * @}
00454   */
00455
00456 /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
00457   * @{
00458   */
00459 /* List of ADC registers intended to be used (most commonly) with             */
00460 /* DMA transfer.                                                              */
00461 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
00462 #define LL_ADC_DMA_REG_REGULAR_DATA          0x00000000U   /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
00463 #if defined(ADC_MULTIMODE_SUPPORT)
00464 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    0x00000001U   /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
00465 #endif
00466 /**
00467   * @}
00468   */
00469
00470 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
00471   * @{
00472   */
00473 /* Note: Other measurement paths to internal channels may be available        */
00474 /*       (connections to other peripherals).                                  */
00475 /*       If they are not listed below, they do not require any specific       */
00476 /*       path enable. In this case, Access to measurement path is done        */
00477 /*       only by selecting the corresponding ADC internal channel.            */
00478 #define LL_ADC_PATH_INTERNAL_NONE          0x00000000U            /*!< ADC measurement pathes all disabled */
00479 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CR2_TSVREFE)      /*!< ADC measurement path to internal channel VrefInt */
00480 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CR2_TSVREFE)      /*!< ADC measurement path to internal channel temperature sensor */
00481 /**
00482   * @}
00483   */
00484
00485 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
00486   * @{
00487   */
00488 #define LL_ADC_RESOLUTION_12B              0x00000000U                         /*!< ADC resolution 12 bits */
00489 /**
00490   * @}
00491   */
00492
00493 /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
00494   * @{
00495   */
00496 #define LL_ADC_DATA_ALIGN_RIGHT            0x00000000U            /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
00497 #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CR2_ALIGN)        /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
00498 /**
00499   * @}
00500   */
00501
00502 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
00503   * @{
00504   */
00505 #define LL_ADC_SEQ_SCAN_DISABLE            0x00000000U    /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
00506 #define LL_ADC_SEQ_SCAN_ENABLE             (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
00507 /**
00508   * @}
00509   */
00510
00511 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
00512   * @{
00513   */
00514 #define LL_ADC_GROUP_REGULAR               0x00000001U   /*!< ADC group regular (available on all STM32 devices) */
00515 #define LL_ADC_GROUP_INJECTED              0x00000002U   /*!< ADC group injected (not available on all STM32 devices)*/
00516 #define LL_ADC_GROUP_REGULAR_INJECTED      0x00000003U   /*!< ADC both groups regular and injected */
00517 /**
00518   * @}
00519   */
00520
00521 /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
00522   * @{
00523   */
00524 #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
00525 #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
00526 #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
00527 #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
00528 #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
00529 #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
00530 #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
00531 #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
00532 #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
00533 #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
00534 #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
00535 #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
00536 #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
00537 #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
00538 #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
00539 #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
00540 #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
00541 #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
00542 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. */
00543 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
00544 /**
00545   * @}
00546   */
00547
00548 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
00549   * @{
00550   */
00551 /* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
00552 #define LL_ADC_REG_TRIG_SOFTWARE           (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal: SW start. */
00553 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CR2_EXTSEL_1)                                       /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00554 /* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
00555 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1       0x00000000U                                              /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00556 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CR2_EXTSEL_0)                                       /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00557 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)                    /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00558 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CR2_EXTSEL_2)                                       /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
00559 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)                    /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00560 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)                    /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
00561 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
00562 /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and     */
00563 /*       XL-density devices.                                                  */
00564 /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done    */
00565 /*       A remap of trigger must be done at top level (refer to               */
00566 /*       AFIO peripheral).                                                    */
00567 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)                        /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).*/
00568 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00569 #if defined (STM32F103xE) || defined (STM32F103xG)
00570 /* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
00571 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1       (LL_ADC_REG_TRIG_EXT_TIM1_CH1)                           /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00572 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (LL_ADC_REG_TRIG_EXT_TIM1_CH2)                           /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00573 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)                           /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00574 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                          /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
00575 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1       (LL_ADC_REG_TRIG_EXT_TIM4_CH4)                           /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00576 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3       (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)                        /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00577 #endif
00578 /**
00579   * @}
00580   */
00581
00582 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
00583   * @{
00584   */
00585 #define LL_ADC_REG_TRIG_EXT_RISING         ADC_CR2_EXTTRIG                         /*!< ADC group regular conversion trigger polarity set to rising edge */
00586 /**
00587   * @}
00588   */
00589
00590 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
00591 * @{
00592 */
00593 #define LL_ADC_REG_CONV_SINGLE             0x00000000U             /*!< ADC conversions are performed in single mode: one conversion per trigger */
00594 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CR2_CONT)          /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
00595 /**
00596   * @}
00597   */
00598
00599 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
00600   * @{
00601   */
00602 #define LL_ADC_REG_DMA_TRANSFER_NONE       0x00000000U              /*!< ADC conversions are not transferred by DMA */
00603 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CR2_DMA)                        /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
00604 /**
00605   * @}
00606   */
00607
00608 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
00609   * @{
00610   */
00611 #define LL_ADC_REG_SEQ_SCAN_DISABLE        0x00000000U                                                 /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
00612 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
00613 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
00614 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
00615 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
00616 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
00617 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
00618 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
00619 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
00620 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
00621 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
00622 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
00623 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
00624 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
00625 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
00626 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
00627 /**
00628   * @}
00629   */
00630
00631 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
00632   * @{
00633   */
00634 #define LL_ADC_REG_SEQ_DISCONT_DISABLE     0x00000000U                                                                  /*!< ADC group regular sequencer discontinuous mode disable */
00635 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                            ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
00636 #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                        ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
00637 #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                    ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
00638 #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                    ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
00639 #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CR1_DISCNUM_2                                         | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
00640 #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CR1_DISCNUM_2                     | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
00641 #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
00642 #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
00643 /**
00644   * @}
00645   */
00646
00647 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
00648   * @{
00649   */
00650 #define LL_ADC_REG_RANK_1                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */
00651 #define LL_ADC_REG_RANK_2                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */
00652 #define LL_ADC_REG_RANK_3                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */
00653 #define LL_ADC_REG_RANK_4                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */
00654 #define LL_ADC_REG_RANK_5                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */
00655 #define LL_ADC_REG_RANK_6                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */
00656 #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */
00657 #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */
00658 #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */
00659 #define LL_ADC_REG_RANK_10                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
00660 #define LL_ADC_REG_RANK_11                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
00661 #define LL_ADC_REG_RANK_12                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
00662 #define LL_ADC_REG_RANK_13                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
00663 #define LL_ADC_REG_RANK_14                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
00664 #define LL_ADC_REG_RANK_15                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
00665 #define LL_ADC_REG_RANK_16                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
00666 /**
00667   * @}
00668   */
00669
00670 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
00671   * @{
00672   */
00673 /* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
00674 #define LL_ADC_INJ_TRIG_SOFTWARE           (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal: SW start. */
00675 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      0x00000000U                                                 /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
00676 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_CR2_JEXTSEL_0)                                         /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00677 /* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
00678 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_CR2_JEXTSEL_1)                                         /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
00679 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)                     /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00680 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_CR2_JEXTSEL_2)                                         /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00681 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)                     /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
00682 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)                     /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
00683 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
00684 /* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and      */
00685 /*       XL-density devices.                                                  */
00686 /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done    */
00687 /*       A remap of trigger must be done at top level (refer to               */
00688 /*       AFIO peripheral).                                                    */
00689 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4        (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)                          /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). */
00690 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
00691 #if defined (STM32F103xE) || defined (STM32F103xG)
00692 /* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
00693 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3        (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                            /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00694 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2        (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                             /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00695 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3   (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                             /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00696 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO       (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                            /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
00697 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4        (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)                          /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
00698 #endif
00699 /**
00700   * @}
00701   */
00702
00703 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
00704   * @{
00705   */
00706 #define LL_ADC_INJ_TRIG_EXT_RISING         ADC_CR2_JEXTTRIG                        /*!< ADC group injected conversion trigger polarity set to rising edge */
00707 /**
00708   * @}
00709   */
00710
00711 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
00712 * @{
00713 */
00714 #define LL_ADC_INJ_TRIG_INDEPENDENT        0x00000000U            /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
00715 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CR1_JAUTO)        /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
00716 /**
00717   * @}
00718   */
00719
00720
00721 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
00722   * @{
00723   */
00724 #define LL_ADC_INJ_SEQ_SCAN_DISABLE        0x00000000U                     /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
00725 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
00726 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
00727 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
00728 /**
00729   * @}
00730   */
00731
00732 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
00733   * @{
00734   */
00735 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     0x00000000U            /*!< ADC group injected sequencer discontinuous mode disable */
00736 #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CR1_JDISCEN)      /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
00737 /**
00738   * @}
00739   */
00740
00741 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
00742   * @{
00743   */
00744 #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
00745 #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
00746 #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
00747 #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
00748 /**
00749   * @}
00750   */
00751
00752 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
00753   * @{
00754   */
00755 #define LL_ADC_SAMPLINGTIME_1CYCLE_5       0x00000000U                                              /*!< Sampling time 1.5 ADC clock cycle */
00756 #define LL_ADC_SAMPLINGTIME_7CYCLES_5      (ADC_SMPR2_SMP0_0)                                       /*!< Sampling time 7.5 ADC clock cycles */
00757 #define LL_ADC_SAMPLINGTIME_13CYCLES_5     (ADC_SMPR2_SMP0_1)                                       /*!< Sampling time 13.5 ADC clock cycles */
00758 #define LL_ADC_SAMPLINGTIME_28CYCLES_5     (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)                    /*!< Sampling time 28.5 ADC clock cycles */
00759 #define LL_ADC_SAMPLINGTIME_41CYCLES_5     (ADC_SMPR2_SMP0_2)                                       /*!< Sampling time 41.5 ADC clock cycles */
00760 #define LL_ADC_SAMPLINGTIME_55CYCLES_5     (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)                    /*!< Sampling time 55.5 ADC clock cycles */
00761 #define LL_ADC_SAMPLINGTIME_71CYCLES_5     (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)                    /*!< Sampling time 71.5 ADC clock cycles */
00762 #define LL_ADC_SAMPLINGTIME_239CYCLES_5    (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */
00763 /**
00764   * @}
00765   */
00766
00767 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
00768   * @{
00769   */
00770 #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
00771 /**
00772   * @}
00773   */
00774
00775 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
00776   * @{
00777   */
00778 #define LL_ADC_AWD_DISABLE                 0x00000000U                                                                                   /*!< ADC analog watchdog monitoring disabled */
00779 #define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                             ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
00780 #define LL_ADC_AWD_ALL_CHANNELS_INJ        (                                            ADC_CR1_JAWDEN                                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
00781 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (                                            ADC_CR1_JAWDEN | ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
00782 #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
00783 #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
00784 #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
00785 #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
00786 #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
00787 #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
00788 #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
00789 #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
00790 #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
00791 #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
00792 #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
00793 #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
00794 #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
00795 #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
00796 #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
00797 #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
00798 #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
00799 #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
00800 #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
00801 #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
00802 #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
00803 #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
00804 #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
00805 #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
00806 #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
00807 #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
00808 #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
00809 #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
00810 #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
00811 #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
00812 #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
00813 #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
00814 #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
00815 #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
00816 #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
00817 #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
00818 #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
00819 #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
00820 #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
00821 #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
00822 #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
00823 #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
00824 #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
00825 #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
00826 #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
00827 #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
00828 #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
00829 #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
00830 #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
00831 #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
00832 #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
00833 #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
00834 #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
00835 #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
00836 #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
00837 #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
00838 #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
00839 #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
00840 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
00841 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
00842 /**
00843   * @}
00844   */
00845
00846 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
00847   * @{
00848   */
00849 #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
00850 #define LL_ADC_AWD_THRESHOLD_LOW           (ADC_AWD_TR1_LOW_REGOFFSET)  /*!< ADC analog watchdog threshold low */
00851 /**
00852   * @}
00853   */
00854
00855 #if !defined(ADC_MULTIMODE_SUPPORT)
00856 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
00857   * @{
00858   */
00859 #define LL_ADC_MULTI_INDEPENDENT              0x00000000U                                                         /*!< ADC dual mode disabled (ADC independent mode) */
00860 /**
00861   * @}
00862   */
00863 #endif
00864 #if defined(ADC_MULTIMODE_SUPPORT)
00865 /** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
00866   * @{
00867   */
00868 #define LL_ADC_MULTI_INDEPENDENT              0x00000000U                                                                     /*!< ADC dual mode disabled (ADC independent mode) */
00869 #define LL_ADC_MULTI_DUAL_REG_SIMULT          (                    ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1                    ) /*!< ADC dual mode enabled: group regular simultaneous */
00870 #define LL_ADC_MULTI_DUAL_REG_INTERL_FAST     (                    ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) */
00871 #define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW     (ADC_CR1_DUALMOD_3                                                            ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */
00872 #define LL_ADC_MULTI_DUAL_INJ_SIMULT          (                    ADC_CR1_DUALMOD_2                     | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */
00873 #define LL_ADC_MULTI_DUAL_INJ_ALTERN          (ADC_CR1_DUALMOD_3                                         | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
00874 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM     (                                                            ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
00875 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT     (                                        ADC_CR1_DUALMOD_1                    ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
00876 #define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM (                                        ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous */
00877 #define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM (                    ADC_CR1_DUALMOD_2                                        ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous */
00878
00879 /**
00880   * @}
00881   */
00882
00883 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
00884   * @{
00885   */
00886 #define LL_ADC_MULTI_MASTER                (                  ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: ADC master */
00887 #define LL_ADC_MULTI_SLAVE                 (ADC_DR_ADC2DATA              ) /*!< In multimode, selection among several ADC instances: ADC slave */
00888 #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
00889 /**
00890   * @}
00891   */
00892
00893 #endif /* ADC_MULTIMODE_SUPPORT */
00894
00895
00896 /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
00897   * @note   Only ADC IP HW delays are defined in ADC LL driver driver,
00898   *         not timeout values.
00899   *         For details on delays values, refer to descriptions in source code
00900   *         above each literal definition.
00901   * @{
00902   */
00903
00904 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */
00905 /*       not timeout values.                                                  */
00906 /*       Timeout values for ADC operations are dependent to device clock      */
00907 /*       configuration (system clock versus ADC clock),                       */
00908 /*       and therefore must be defined in user application.                   */
00909 /*       Indications for estimation of ADC timeout delays, for this           */
00910 /*       STM32 serie:                                                         */
00911 /*       - ADC enable time: maximum delay is 1us                              */
00912 /*         (refer to device datasheet, parameter "tSTAB")                     */
00913 /*       - ADC conversion time: duration depending on ADC clock and ADC       */
00914 /*         configuration.                                                     */
00915 /*         (refer to device reference manual, section "Timing")               */
00916
00917 /* Delay for temperature sensor stabilization time.                           */
00918 /* Literal set to maximum value (refer to device datasheet,                   */
00919 /* parameter "tSTART").                                                       */
00920 /* Unit: us                                                                   */
00921 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US       (10U)  /*!< Delay for internal voltage reference stabilization time */
00922
00923 /* Delay required between ADC disable and ADC calibration start.              */
00924 /* Note: On this STM32 serie, before starting a calibration,                  */
00925 /*       ADC must be disabled.                                                */
00926 /*       A minimum number of ADC clock cycles are required                    */
00927 /*       between ADC disable state and calibration start.                     */
00928 /*       Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES.          */
00929 /*       Wait time can be computed in user application by waiting for the     */
00930 /*       equivalent number of CPU cycles, by taking into account              */
00931 /*       ratio of CPU clock versus ADC clock prescalers.                      */
00932 /* Unit: ADC clock cycles.                                                    */
00933 #define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES  (2U)  /*!< Delay required between ADC disable and ADC calibration start */
00934
00935 /* Delay required between end of ADC Enable and the start of ADC calibration. */
00936 /* Note: On this STM32 serie, a minimum number of ADC clock cycles            */
00937 /*       are required between the end of ADC enable and the start of ADC      */
00938 /*       calibration.                                                         */
00939 /*       Wait time can be computed in user application by waiting for the     */
00940 /*       equivalent number of CPU cycles, by taking into account              */
00941 /*       ratio of CPU clock versus ADC clock prescalers.                      */
00942 /* Unit: ADC clock cycles.                                                    */
00943 #define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES  (2U)  /*!< Delay required between end of ADC enable and the start of ADC calibration */
00944
00945 /**
00946   * @}
00947   */
00948
00949 /**
00950   * @}
00951   */
00952
00953
00954 /* Exported macro ------------------------------------------------------------*/
00955 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
00956   * @{
00957   */
00958
00959 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
00960   * @{
00961   */
00962
00963 /**
00964   * @brief  Write a value in ADC register
00965   * @param  __INSTANCE__ ADC Instance
00966   * @param  __REG__ Register to be written
00967   * @param  __VALUE__ Value to be written in the register
00968   * @retval None
00969   */
00970 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00971
00972 /**
00973   * @brief  Read a value in ADC register
00974   * @param  __INSTANCE__ ADC Instance
00975   * @param  __REG__ Register to be read
00976   * @retval Register value
00977   */
00978 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00979 /**
00980   * @}
00981   */
00982
00983 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
00984   * @{
00985   */
00986
00987 /**
00988   * @brief  Helper macro to get ADC channel number in decimal format
00989   *         from literals LL_ADC_CHANNEL_x.
00990   * @note   Example:
00991   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
00992   *           will return decimal number "4".
00993   * @note   The input can be a value from functions where a channel
00994   *         number is returned, either defined with number
00995   *         or with bitfield (only one bit must be set).
00996   * @param  __CHANNEL__ This parameter can be one of the following values:
00997   *         @arg @ref LL_ADC_CHANNEL_0
00998   *         @arg @ref LL_ADC_CHANNEL_1
00999   *         @arg @ref LL_ADC_CHANNEL_2
01000   *         @arg @ref LL_ADC_CHANNEL_3
01001   *         @arg @ref LL_ADC_CHANNEL_4
01002   *         @arg @ref LL_ADC_CHANNEL_5
01003   *         @arg @ref LL_ADC_CHANNEL_6
01004   *         @arg @ref LL_ADC_CHANNEL_7
01005   *         @arg @ref LL_ADC_CHANNEL_8
01006   *         @arg @ref LL_ADC_CHANNEL_9
01007   *         @arg @ref LL_ADC_CHANNEL_10
01008   *         @arg @ref LL_ADC_CHANNEL_11
01009   *         @arg @ref LL_ADC_CHANNEL_12
01010   *         @arg @ref LL_ADC_CHANNEL_13
01011   *         @arg @ref LL_ADC_CHANNEL_14
01012   *         @arg @ref LL_ADC_CHANNEL_15
01013   *         @arg @ref LL_ADC_CHANNEL_16
01014   *         @arg @ref LL_ADC_CHANNEL_17
01015   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01016   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01017   *
01018   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.
01019   * @retval Value between Min_Data=0 and Max_Data=18
01020   */
01021 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
01022   (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
01023
01024 /**
01025   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
01026   *         from number in decimal format.
01027   * @note   Example:
01028   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
01029   *           will return a data equivalent to "LL_ADC_CHANNEL_4".
01030   * @param  __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
01031   * @retval Returned value can be one of the following values:
01032   *         @arg @ref LL_ADC_CHANNEL_0
01033   *         @arg @ref LL_ADC_CHANNEL_1
01034   *         @arg @ref LL_ADC_CHANNEL_2
01035   *         @arg @ref LL_ADC_CHANNEL_3
01036   *         @arg @ref LL_ADC_CHANNEL_4
01037   *         @arg @ref LL_ADC_CHANNEL_5
01038   *         @arg @ref LL_ADC_CHANNEL_6
01039   *         @arg @ref LL_ADC_CHANNEL_7
01040   *         @arg @ref LL_ADC_CHANNEL_8
01041   *         @arg @ref LL_ADC_CHANNEL_9
01042   *         @arg @ref LL_ADC_CHANNEL_10
01043   *         @arg @ref LL_ADC_CHANNEL_11
01044   *         @arg @ref LL_ADC_CHANNEL_12
01045   *         @arg @ref LL_ADC_CHANNEL_13
01046   *         @arg @ref LL_ADC_CHANNEL_14
01047   *         @arg @ref LL_ADC_CHANNEL_15
01048   *         @arg @ref LL_ADC_CHANNEL_16
01049   *         @arg @ref LL_ADC_CHANNEL_17
01050   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01051   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01052   *
01053   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
01054   *         (1) For ADC channel read back from ADC register,
01055   *             comparison with internal channel parameter to be done
01056   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01057   */
01058 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                          \
01059   (((__DECIMAL_NB__) <= 9U)                                                                                     \
01060     ? (                                                                                                         \
01061        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \
01062        (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \
01063       )                                                                                                         \
01064       :                                                                                                         \
01065       (                                                                                                         \
01066        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \
01067        (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
01068       )                                                                                                         \
01069   )
01070
01071 /**
01072   * @brief  Helper macro to determine whether the selected channel
01073   *         corresponds to literal definitions of driver.
01074   * @note   The different literal definitions of ADC channels are:
01075   *         - ADC internal channel:
01076   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
01077   *         - ADC external channel (channel connected to a GPIO pin):
01078   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
01079   * @note   The channel parameter must be a value defined from literal
01080   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01081   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01082   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
01083   *         must not be a value from functions where a channel number is
01084   *         returned from ADC registers,
01085   *         because internal and external channels share the same channel
01086   *         number in ADC registers. The differentiation is made only with
01087   *         parameters definitions of driver.
01088   * @param  __CHANNEL__ This parameter can be one of the following values:
01089   *         @arg @ref LL_ADC_CHANNEL_0
01090   *         @arg @ref LL_ADC_CHANNEL_1
01091   *         @arg @ref LL_ADC_CHANNEL_2
01092   *         @arg @ref LL_ADC_CHANNEL_3
01093   *         @arg @ref LL_ADC_CHANNEL_4
01094   *         @arg @ref LL_ADC_CHANNEL_5
01095   *         @arg @ref LL_ADC_CHANNEL_6
01096   *         @arg @ref LL_ADC_CHANNEL_7
01097   *         @arg @ref LL_ADC_CHANNEL_8
01098   *         @arg @ref LL_ADC_CHANNEL_9
01099   *         @arg @ref LL_ADC_CHANNEL_10
01100   *         @arg @ref LL_ADC_CHANNEL_11
01101   *         @arg @ref LL_ADC_CHANNEL_12
01102   *         @arg @ref LL_ADC_CHANNEL_13
01103   *         @arg @ref LL_ADC_CHANNEL_14
01104   *         @arg @ref LL_ADC_CHANNEL_15
01105   *         @arg @ref LL_ADC_CHANNEL_16
01106   *         @arg @ref LL_ADC_CHANNEL_17
01107   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01108   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01109   *
01110   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.
01111   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
01112   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
01113   */
01114 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
01115   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
01116
01117 /**
01118   * @brief  Helper macro to convert a channel defined from parameter
01119   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01120   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01121   *         to its equivalent parameter definition of a ADC external channel
01122   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
01123   * @note   The channel parameter can be, additionally to a value
01124   *         defined from parameter definition of a ADC internal channel
01125   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
01126   *         a value defined from parameter definition of
01127   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01128   *         or a value from functions where a channel number is returned
01129   *         from ADC registers.
01130   * @param  __CHANNEL__ This parameter can be one of the following values:
01131   *         @arg @ref LL_ADC_CHANNEL_0
01132   *         @arg @ref LL_ADC_CHANNEL_1
01133   *         @arg @ref LL_ADC_CHANNEL_2
01134   *         @arg @ref LL_ADC_CHANNEL_3
01135   *         @arg @ref LL_ADC_CHANNEL_4
01136   *         @arg @ref LL_ADC_CHANNEL_5
01137   *         @arg @ref LL_ADC_CHANNEL_6
01138   *         @arg @ref LL_ADC_CHANNEL_7
01139   *         @arg @ref LL_ADC_CHANNEL_8
01140   *         @arg @ref LL_ADC_CHANNEL_9
01141   *         @arg @ref LL_ADC_CHANNEL_10
01142   *         @arg @ref LL_ADC_CHANNEL_11
01143   *         @arg @ref LL_ADC_CHANNEL_12
01144   *         @arg @ref LL_ADC_CHANNEL_13
01145   *         @arg @ref LL_ADC_CHANNEL_14
01146   *         @arg @ref LL_ADC_CHANNEL_15
01147   *         @arg @ref LL_ADC_CHANNEL_16
01148   *         @arg @ref LL_ADC_CHANNEL_17
01149   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01150   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01151   *
01152   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.
01153   * @retval Returned value can be one of the following values:
01154   *         @arg @ref LL_ADC_CHANNEL_0
01155   *         @arg @ref LL_ADC_CHANNEL_1
01156   *         @arg @ref LL_ADC_CHANNEL_2
01157   *         @arg @ref LL_ADC_CHANNEL_3
01158   *         @arg @ref LL_ADC_CHANNEL_4
01159   *         @arg @ref LL_ADC_CHANNEL_5
01160   *         @arg @ref LL_ADC_CHANNEL_6
01161   *         @arg @ref LL_ADC_CHANNEL_7
01162   *         @arg @ref LL_ADC_CHANNEL_8
01163   *         @arg @ref LL_ADC_CHANNEL_9
01164   *         @arg @ref LL_ADC_CHANNEL_10
01165   *         @arg @ref LL_ADC_CHANNEL_11
01166   *         @arg @ref LL_ADC_CHANNEL_12
01167   *         @arg @ref LL_ADC_CHANNEL_13
01168   *         @arg @ref LL_ADC_CHANNEL_14
01169   *         @arg @ref LL_ADC_CHANNEL_15
01170   *         @arg @ref LL_ADC_CHANNEL_16
01171   *         @arg @ref LL_ADC_CHANNEL_17
01172   */
01173 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
01174   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
01175
01176 /**
01177   * @brief  Helper macro to determine whether the internal channel
01178   *         selected is available on the ADC instance selected.
01179   * @note   The channel parameter must be a value defined from parameter
01180   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
01181   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
01182   *         must not be a value defined from parameter definition of
01183   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
01184   *         or a value from functions where a channel number is
01185   *         returned from ADC registers,
01186   *         because internal and external channels share the same channel
01187   *         number in ADC registers. The differentiation is made only with
01188   *         parameters definitions of driver.
01189   * @param  __ADC_INSTANCE__ ADC instance
01190   * @param  __CHANNEL__ This parameter can be one of the following values:
01191   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01192   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01193   *
01194   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.
01195   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
01196   *         Value "1" if the internal channel selected is available on the ADC instance selected.
01197   */
01198 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
01199   (((__ADC_INSTANCE__) == ADC1)                                                \
01200     ? (                                                                        \
01201        ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \
01202        ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)                            \
01203       )                                                                        \
01204       :                                                                        \
01205       (0U)                                                                     \
01206   )
01207
01208 /**
01209   * @brief  Helper macro to define ADC analog watchdog parameter:
01210   *         define a single channel to monitor with analog watchdog
01211   *         from sequencer channel and groups definition.
01212   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
01213   *         Example:
01214   *           LL_ADC_SetAnalogWDMonitChannels(
01215   *             ADC1, LL_ADC_AWD1,
01216   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
01217   * @param  __CHANNEL__ This parameter can be one of the following values:
01218   *         @arg @ref LL_ADC_CHANNEL_0
01219   *         @arg @ref LL_ADC_CHANNEL_1
01220   *         @arg @ref LL_ADC_CHANNEL_2
01221   *         @arg @ref LL_ADC_CHANNEL_3
01222   *         @arg @ref LL_ADC_CHANNEL_4
01223   *         @arg @ref LL_ADC_CHANNEL_5
01224   *         @arg @ref LL_ADC_CHANNEL_6
01225   *         @arg @ref LL_ADC_CHANNEL_7
01226   *         @arg @ref LL_ADC_CHANNEL_8
01227   *         @arg @ref LL_ADC_CHANNEL_9
01228   *         @arg @ref LL_ADC_CHANNEL_10
01229   *         @arg @ref LL_ADC_CHANNEL_11
01230   *         @arg @ref LL_ADC_CHANNEL_12
01231   *         @arg @ref LL_ADC_CHANNEL_13
01232   *         @arg @ref LL_ADC_CHANNEL_14
01233   *         @arg @ref LL_ADC_CHANNEL_15
01234   *         @arg @ref LL_ADC_CHANNEL_16
01235   *         @arg @ref LL_ADC_CHANNEL_17
01236   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
01237   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
01238   *
01239   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
01240   *         (1) For ADC channel read back from ADC register,
01241   *             comparison with internal channel parameter to be done
01242   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
01243   * @param  __GROUP__ This parameter can be one of the following values:
01244   *         @arg @ref LL_ADC_GROUP_REGULAR
01245   *         @arg @ref LL_ADC_GROUP_INJECTED
01246   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
01247   * @retval Returned value can be one of the following values:
01248   *         @arg @ref LL_ADC_AWD_DISABLE
01249   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
01250   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
01251   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
01252   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
01253   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
01254   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
01255   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
01256   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
01257   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
01258   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
01259   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
01260   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
01261   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
01262   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
01263   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
01264   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
01265   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
01266   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
01267   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
01268   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
01269   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
01270   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
01271   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
01272   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
01273   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
01274   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
01275   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
01276   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
01277   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
01278   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
01279   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
01280   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
01281   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
01282   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
01283   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
01284   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
01285   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
01286   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
01287   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
01288   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
01289   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
01290   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
01291   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
01292   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
01293   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
01294   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
01295   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
01296   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
01297   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
01298   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
01299   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
01300   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
01301   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
01302   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
01303   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
01304   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
01305   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
01306   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (1)
01307   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (1)
01308   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (1)
01309   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (1)
01310   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (1)
01311   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (1)
01312   *
01313   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.
01314   */
01315 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
01316   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
01317     ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)                            \
01318       :                                                                                                   \
01319       ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \
01320        ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)                        \
01321          :                                                                                                \
01322          (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)        \
01323   )
01324
01325 /**
01326   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
01327   *         or low in function of ADC resolution, when ADC resolution is
01328   *         different of 12 bits.
01329   * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().
01330   *         Example, with a ADC resolution of 8 bits, to set the value of
01331   *         analog watchdog threshold high (on 8 bits):
01332   *           LL_ADC_SetAnalogWDThresholds
01333   *            (< ADCx param >,
01334   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
01335   *            );
01336   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01337   *         @arg @ref LL_ADC_RESOLUTION_12B
01338   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
01339   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01340   */
01341 /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits.            */
01342 /*       This macro has been kept anyway for compatibility with other         */
01343 /*       STM32 families featuring different ADC resolutions.                  */
01344 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
01345   ((__AWD_THRESHOLD__) << (0U))
01346
01347 /**
01348   * @brief  Helper macro to get the value of ADC analog watchdog threshold high
01349   *         or low in function of ADC resolution, when ADC resolution is
01350   *         different of 12 bits.
01351   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
01352   *         Example, with a ADC resolution of 8 bits, to get the value of
01353   *         analog watchdog threshold high (on 8 bits):
01354   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
01355   *            (LL_ADC_RESOLUTION_8B,
01356   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
01357   *            );
01358   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01359   *         @arg @ref LL_ADC_RESOLUTION_12B
01360   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
01361   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01362   */
01363 /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits.            */
01364 /*       This macro has been kept anyway for compatibility with other         */
01365 /*       STM32 families featuring different ADC resolutions.                  */
01366 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
01367   (__AWD_THRESHOLD_12_BITS__)
01368
01369 #if defined(ADC_MULTIMODE_SUPPORT)
01370 /**
01371   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
01372   *         or ADC slave from raw value with both ADC conversion data concatenated.
01373   * @note   This macro is intended to be used when multimode transfer by DMA
01374   *         is enabled.
01375   *         In this case the transferred data need to processed with this macro
01376   *         to separate the conversion data of ADC master and ADC slave.
01377   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
01378   *         @arg @ref LL_ADC_MULTI_MASTER
01379   *         @arg @ref LL_ADC_MULTI_SLAVE
01380   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
01381   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01382   */
01383 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
01384   (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA)
01385 #endif
01386
01387 /**
01388   * @brief  Helper macro to select the ADC common instance
01389   *         to which is belonging the selected ADC instance.
01390   * @note   ADC common register instance can be used for:
01391   *         - Set parameters common to several ADC instances
01392   *         - Multimode (for devices with several ADC instances)
01393   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01394   * @note   On STM32F1, there is no common ADC instance.
01395   *         However, ADC instance ADC1 has a role of common ADC instance
01396   *         for ADC1 and ADC2:
01397   *         this instance is used to manage internal channels
01398   *         and multimode (these features are managed in ADC common
01399   *         instances on some other STM32 devices).
01400   *         ADC instance ADC3 (if available on the selected device)
01401   *         has no ADC common instance.
01402   * @param  __ADCx__ ADC instance
01403   * @retval ADC common register instance
01404   */
01405 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
01406 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01407   ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \
01408     ? (                                                                        \
01409        (ADC12_COMMON)                                                          \
01410       )                                                                        \
01411       :                                                                        \
01412       (                                                                        \
01413        (0U)                                                                    \
01414       )                                                                        \
01415   )
01416 #elif defined(ADC1) && defined(ADC2)
01417 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01418   (ADC12_COMMON)
01419 #else
01420 #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
01421   (ADC1_COMMON)
01422 #endif
01423
01424 /**
01425   * @brief  Helper macro to check if all ADC instances sharing the same
01426   *         ADC common instance are disabled.
01427   * @note   This check is required by functions with setting conditioned to
01428   *         ADC state:
01429   *         All ADC instances of the ADC common group must be disabled.
01430   *         Refer to functions having argument "ADCxy_COMMON" as parameter.
01431   * @note   On devices with only 1 ADC common instance, parameter of this macro
01432   *         is useless and can be ignored (parameter kept for compatibility
01433   *         with devices featuring several ADC common instances).
01434   * @note   On STM32F1, there is no common ADC instance.
01435   *         However, ADC instance ADC1 has a role of common ADC instance
01436   *         for ADC1 and ADC2:
01437   *         this instance is used to manage internal channels
01438   *         and multimode (these features are managed in ADC common
01439   *         instances on some other STM32 devices).
01440   *         ADC instance ADC3 (if available on the selected device)
01441   *         has no ADC common instance.
01442   * @param  __ADCXY_COMMON__ ADC common instance
01443   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01444   * @retval Value "0" if all ADC instances sharing the same ADC common instance
01445   *         are disabled.
01446   *         Value "1" if at least one ADC instance sharing the same ADC common instance
01447   *         is enabled.
01448   */
01449 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
01450 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01451   (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
01452     ? (                                                                        \
01453        (LL_ADC_IsEnabled(ADC1) |                                               \
01454         LL_ADC_IsEnabled(ADC2)  )                                              \
01455       )                                                                        \
01456       :                                                                        \
01457       (                                                                        \
01458        LL_ADC_IsEnabled(ADC3)                                                  \
01459       )                                                                        \
01460   )
01461 #elif defined(ADC1) && defined(ADC2)
01462 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01463   (LL_ADC_IsEnabled(ADC1) |                                                    \
01464    LL_ADC_IsEnabled(ADC2)  )
01465 #else
01466 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
01467   LL_ADC_IsEnabled(ADC1)
01468 #endif
01469
01470 /**
01471   * @brief  Helper macro to define the ADC conversion data full-scale digital
01472   *         value corresponding to the selected ADC resolution.
01473   * @note   ADC conversion data full-scale corresponds to voltage range
01474   *         determined by analog voltage references Vref+ and Vref-
01475   *         (refer to reference manual).
01476   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01477   *         @arg @ref LL_ADC_RESOLUTION_12B
01478   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
01479   */
01480 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
01481   (0xFFFU)
01482
01483
01484 /**
01485   * @brief  Helper macro to calculate the voltage (unit: mVolt)
01486   *         corresponding to a ADC conversion data (unit: digital value).
01487   * @note   Analog reference voltage (Vref+) must be known from
01488   *         user board environment or can be calculated using ADC measurement.
01489   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
01490   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
01491   *                       (unit: digital value).
01492   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
01493   *         @arg @ref LL_ADC_RESOLUTION_12B
01494   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
01495   */
01496 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
01497                                       __ADC_DATA__,\
01498                                       __ADC_RESOLUTION__)                      \
01499   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
01500    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
01501   )
01502
01503
01504 /**
01505   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
01506   *         from ADC conversion data of internal temperature sensor.
01507   * @note   Computation is using temperature sensor typical values
01508   *         (refer to device datasheet).
01509   * @note   Calculation formula:
01510   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
01511   *                         / Avg_Slope + CALx_TEMP
01512   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
01513   *                                   (unit: digital value)
01514   *                Avg_Slope        = temperature sensor slope
01515   *                                   (unit: uV/Degree Celsius)
01516   *                TS_TYP_CALx_VOLT = temperature sensor digital value at
01517   *                                   temperature CALx_TEMP (unit: mV)
01518   *         Caution: Calculation relevancy under reserve the temperature sensor
01519   *                  of the current device has characteristics in line with
01520   *                  datasheet typical values.
01521   *                  If temperature sensor calibration values are available on
01522   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
01523   *                  temperature calculation will be more accurate using
01524   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
01525   * @note   As calculation input, the analog reference voltage (Vref+) must be
01526   *         defined as it impacts the ADC LSB equivalent voltage.
01527   * @note   Analog reference voltage (Vref+) must be known from
01528   *         user board environment or can be calculated using ADC measurement.
01529   * @note   ADC measurement data must correspond to a resolution of 12bits
01530   *         (full scale digital value 4095). If not the case, the data must be
01531   *         preliminarily rescaled to an equivalent resolution of 12 bits.
01532   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
01533   *                                       On STM32F1, refer to device datasheet parameter "Avg_Slope".
01534   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
01535   *                                       On STM32F1, refer to device datasheet parameter "V25".
01536   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
01537   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
01538   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
01539   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
01540   *         This parameter can be one of the following values:
01541   *         @arg @ref LL_ADC_RESOLUTION_12B
01542   * @retval Temperature (unit: degree Celsius)
01543   */
01544 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
01545                                              __TEMPSENSOR_TYP_CALX_V__,\
01546                                              __TEMPSENSOR_CALX_TEMP__,\
01547                                              __VREFANALOG_VOLTAGE__,\
01548                                              __TEMPSENSOR_ADC_DATA__,\
01549                                              __ADC_RESOLUTION__)               \
01550   ((( (                                                                        \
01551        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
01552                  * 1000)                                                       \
01553        -                                                                       \
01554        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
01555                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
01556                  * 1000)                                                       \
01557       )                                                                        \
01558     ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \
01559    ) + (__TEMPSENSOR_CALX_TEMP__)                                              \
01560   )
01561
01562 /**
01563   * @}
01564   */
01565
01566 /**
01567   * @}
01568   */
01569
01570
01571 /* Exported functions --------------------------------------------------------*/
01572 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
01573   * @{
01574   */
01575
01576 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
01577   * @{
01578   */
01579 /* Note: LL ADC functions to set DMA transfer are located into sections of    */
01580 /*       configuration of ADC instance, groups and multimode (if available):  */
01581 /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
01582
01583 /**
01584   * @brief  Function to help to configure DMA transfer from ADC: retrieve the
01585   *         ADC register address from ADC instance and a list of ADC registers
01586   *         intended to be used (most commonly) with DMA transfer.
01587   * @note   These ADC registers are data registers:
01588   *         when ADC conversion data is available in ADC data registers,
01589   *         ADC generates a DMA transfer request.
01590   * @note   This macro is intended to be used with LL DMA driver, refer to
01591   *         function "LL_DMA_ConfigAddresses()".
01592   *         Example:
01593   *           LL_DMA_ConfigAddresses(DMA1,
01594   *                                  LL_DMA_CHANNEL_1,
01595   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
01596   *                                  (uint32_t)&< array or variable >,
01597   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
01598   * @note   For devices with several ADC: in multimode, some devices
01599   *         use a different data register outside of ADC instance scope
01600   *         (common data register). This macro manages this register difference,
01601   *         only ADC instance has to be set as parameter.
01602   * @note   On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer
01603   *         capability, not ADC2 (ADC2 and ADC3 instances not available on
01604   *         all devices).
01605   * @note   On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3.
01606   *         Therefore, the corresponding parameter of data transfer
01607   *         for multimode can be used only with ADC1 and ADC2.
01608   *         (ADC2 and ADC3 instances not available on all devices).
01609   * @rmtoll DR       DATA           LL_ADC_DMA_GetRegAddr
01610   * @param  ADCx ADC instance
01611   * @param  Register This parameter can be one of the following values:
01612   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
01613   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
01614   *
01615   *         (1) Available on devices with several ADC instances.
01616   * @retval ADC register address
01617   */
01618 #if defined(ADC_MULTIMODE_SUPPORT)
01619 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
01620 {
01621   register uint32_t data_reg_addr = 0U;
01622
01623   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
01624   {
01625     /* Retrieve address of register DR */
01626     data_reg_addr = (uint32_t)&(ADCx->DR);
01627   }
01628   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
01629   {
01630     /* Retrieve address of register of multimode data */
01631     data_reg_addr = (uint32_t)&(ADC12_COMMON->DR);
01632   }
01633
01634   return data_reg_addr;
01635 }
01636 #else
01637 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
01638 {
01639   /* Retrieve address of register DR */
01640   return (uint32_t)&(ADCx->DR);
01641 }
01642 #endif
01643
01644 /**
01645   * @}
01646   */
01647
01648 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
01649   * @{
01650   */
01651
01652 /**
01653   * @brief  Set parameter common to several ADC: measurement path to internal
01654   *         channels (VrefInt, temperature sensor, ...).
01655   * @note   One or several values can be selected.
01656   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
01657   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
01658   * @note   Stabilization time of measurement path to internal channel:
01659   *         After enabling internal paths, before starting ADC conversion,
01660   *         a delay is required for internal voltage reference and
01661   *         temperature sensor stabilization time.
01662   *         Refer to device datasheet.
01663   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
01664   * @note   ADC internal channel sampling time constraint:
01665   *         For ADC conversion of internal channels,
01666   *         a sampling time minimum value is required.
01667   *         Refer to device datasheet.
01668   * @rmtoll CR2      TSVREFE        LL_ADC_SetCommonPathInternalCh
01669   * @param  ADCxy_COMMON ADC common instance
01670   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01671   * @param  PathInternal This parameter can be a combination of the following values:
01672   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
01673   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
01674   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
01675   * @retval None
01676   */
01677 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
01678 {
01679   MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
01680 }
01681
01682 /**
01683   * @brief  Get parameter common to several ADC: measurement path to internal
01684   *         channels (VrefInt, temperature sensor, ...).
01685   * @note   One or several values can be selected.
01686   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
01687   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
01688   * @rmtoll CR2      TSVREFE        LL_ADC_GetCommonPathInternalCh
01689   * @param  ADCxy_COMMON ADC common instance
01690   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
01691   * @retval Returned value can be a combination of the following values:
01692   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
01693   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
01694   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
01695   */
01696 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
01697 {
01698   return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
01699 }
01700
01701 /**
01702   * @}
01703   */
01704
01705 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
01706   * @{
01707   */
01708
01709 /**
01710   * @brief  Set ADC conversion data alignment.
01711   * @note   Refer to reference manual for alignments formats
01712   *         dependencies to ADC resolutions.
01713   * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment
01714   * @param  ADCx ADC instance
01715   * @param  DataAlignment This parameter can be one of the following values:
01716   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
01717   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
01718   * @retval None
01719   */
01720 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
01721 {
01722   MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
01723 }
01724
01725 /**
01726   * @brief  Get ADC conversion data alignment.
01727   * @note   Refer to reference manual for alignments formats
01728   *         dependencies to ADC resolutions.
01729   * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment
01730   * @param  ADCx ADC instance
01731   * @retval Returned value can be one of the following values:
01732   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
01733   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
01734   */
01735 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
01736 {
01737   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
01738 }
01739
01740 /**
01741   * @brief  Set ADC sequencers scan mode, for all ADC groups
01742   *         (group regular, group injected).
01743   * @note  According to sequencers scan mode :
01744   *         - If disabled: ADC conversion is performed in unitary conversion
01745   *           mode (one channel converted, that defined in rank 1).
01746   *           Configuration of sequencers of all ADC groups
01747   *           (sequencer scan length, ...) is discarded: equivalent to
01748   *           scan length of 1 rank.
01749   *         - If enabled: ADC conversions are performed in sequence conversions
01750   *           mode, according to configuration of sequencers of
01751   *           each ADC group (sequencer scan length, ...).
01752   *           Refer to function @ref LL_ADC_REG_SetSequencerLength()
01753   *           and to function @ref LL_ADC_INJ_SetSequencerLength().
01754   * @rmtoll CR1      SCAN           LL_ADC_SetSequencersScanMode
01755   * @param  ADCx ADC instance
01756   * @param  ScanMode This parameter can be one of the following values:
01757   *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE
01758   *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE
01759   * @retval None
01760   */
01761 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
01762 {
01763   MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
01764 }
01765
01766 /**
01767   * @brief  Get ADC sequencers scan mode, for all ADC groups
01768   *         (group regular, group injected).
01769   * @note  According to sequencers scan mode :
01770   *         - If disabled: ADC conversion is performed in unitary conversion
01771   *           mode (one channel converted, that defined in rank 1).
01772   *           Configuration of sequencers of all ADC groups
01773   *           (sequencer scan length, ...) is discarded: equivalent to
01774   *           scan length of 1 rank.
01775   *         - If enabled: ADC conversions are performed in sequence conversions
01776   *           mode, according to configuration of sequencers of
01777   *           each ADC group (sequencer scan length, ...).
01778   *           Refer to function @ref LL_ADC_REG_SetSequencerLength()
01779   *           and to function @ref LL_ADC_INJ_SetSequencerLength().
01780   * @rmtoll CR1      SCAN           LL_ADC_GetSequencersScanMode
01781   * @param  ADCx ADC instance
01782   * @retval Returned value can be one of the following values:
01783   *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE
01784   *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE
01785   */
01786 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
01787 {
01788   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
01789 }
01790
01791 /**
01792   * @}
01793   */
01794
01795 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
01796   * @{
01797   */
01798
01799 /**
01800   * @brief  Set ADC group regular conversion trigger source:
01801   *         internal (SW start) or from external IP (timer event,
01802   *         external interrupt line).
01803   * @note   On this STM32 serie, external trigger is set with trigger polarity:
01804   *         rising edge (only trigger polarity available on this STM32 serie).
01805   * @note   Availability of parameters of trigger sources from timer
01806   *         depends on timers availability on the selected device.
01807   * @rmtoll CR2      EXTSEL         LL_ADC_REG_SetTriggerSource
01808   * @param  ADCx ADC instance
01809   * @param  TriggerSource This parameter can be one of the following values:
01810   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
01811   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3       (1)
01812   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1       (2)
01813   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2       (2)
01814   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2       (2)
01815   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (2)
01816   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4       (2)
01817   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (2)
01818   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (2)(4)
01819   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
01820   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1       (3)
01821   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3       (3)
01822   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1       (3)
01823   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (3)
01824   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1       (3)
01825   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3       (3)
01826   *
01827   *         (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
01828   *         (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
01829   *         (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
01830   *         (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
01831   * @retval None
01832   */
01833 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
01834 {
01835 /* Note: On this STM32 serie, ADC group regular external trigger edge        */
01836 /*       is used to perform a ADC conversion start.                           */
01837 /*       This function does not set external trigger edge.                    */
01838 /*       This feature is set using function                                   */
01839 /*       @ref LL_ADC_REG_StartConversionExtTrig().                            */
01840   MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
01841 }
01842
01843 /**
01844   * @brief  Get ADC group regular conversion trigger source:
01845   *         internal (SW start) or from external IP (timer event,
01846   *         external interrupt line).
01847   * @note   To determine whether group regular trigger source is
01848   *         internal (SW start) or external, without detail
01849   *         of which peripheral is selected as external trigger,
01850   *         (equivalent to
01851   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
01852   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
01853   * @note   Availability of parameters of trigger sources from timer
01854   *         depends on timers availability on the selected device.
01855   * @rmtoll CR2      EXTSEL         LL_ADC_REG_GetTriggerSource
01856   * @param  ADCx ADC instance
01857   * @retval Returned value can be one of the following values:
01858   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
01859   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3       (1)
01860   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1       (2)
01861   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2       (2)
01862   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2       (2)
01863   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (2)
01864   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4       (2)
01865   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (2)
01866   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (2)(4)
01867   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
01868   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1       (3)
01869   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3       (3)
01870   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1       (3)
01871   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (3)
01872   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1       (3)
01873   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3       (3)
01874   *
01875   *         (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
01876   *         (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
01877   *         (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
01878   *         (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
01879   */
01880 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
01881 {
01882   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
01883 }
01884
01885 /**
01886   * @brief  Get ADC group regular conversion trigger source internal (SW start)
01887             or external.
01888   * @note   In case of group regular trigger source set to external trigger,
01889   *         to determine which peripheral is selected as external trigger,
01890   *         use function @ref LL_ADC_REG_GetTriggerSource().
01891   * @rmtoll CR2      EXTSEL         LL_ADC_REG_IsTriggerSourceSWStart
01892   * @param  ADCx ADC instance
01893   * @retval Value "0" if trigger source external trigger
01894   *         Value "1" if trigger source SW start.
01895   */
01896 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
01897 {
01898   return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
01899 }
01900
01901
01902 /**
01903   * @brief  Set ADC group regular sequencer length and scan direction.
01904   * @note   Description of ADC group regular sequencer features:
01905   *         - For devices with sequencer fully configurable
01906   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
01907   *           sequencer length and each rank affectation to a channel
01908   *           are configurable.
01909   *           This function performs configuration of:
01910   *           - Sequence length: Number of ranks in the scan sequence.
01911   *           - Sequence direction: Unless specified in parameters, sequencer
01912   *             scan direction is forward (from rank 1 to rank n).
01913   *           Sequencer ranks are selected using
01914   *           function "LL_ADC_REG_SetSequencerRanks()".
01915   *         - For devices with sequencer not fully configurable
01916   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
01917   *           sequencer length and each rank affectation to a channel
01918   *           are defined by channel number.
01919   *           This function performs configuration of:
01920   *           - Sequence length: Number of ranks in the scan sequence is
01921   *             defined by number of channels set in the sequence,
01922   *             rank of each channel is fixed by channel HW number.
01923   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
01924   *           - Sequence direction: Unless specified in parameters, sequencer
01925   *             scan direction is forward (from lowest channel number to
01926   *             highest channel number).
01927   *           Sequencer ranks are selected using
01928   *           function "LL_ADC_REG_SetSequencerChannels()".
01929   * @note   On this STM32 serie, group regular sequencer configuration
01930   *         is conditioned to ADC instance sequencer mode.
01931   *         If ADC instance sequencer mode is disabled, sequencers of
01932   *         all groups (group regular, group injected) can be configured
01933   *         but their execution is disabled (limited to rank 1).
01934   *         Refer to function @ref LL_ADC_SetSequencersScanMode().
01935   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
01936   *         ADC conversion on only 1 channel.
01937   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
01938   * @param  ADCx ADC instance
01939   * @param  SequencerNbRanks This parameter can be one of the following values:
01940   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
01941   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
01942   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
01943   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
01944   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
01945   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
01946   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
01947   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
01948   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
01949   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
01950   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
01951   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
01952   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
01953   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
01954   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
01955   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
01956   * @retval None
01957   */
01958 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
01959 {
01960   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
01961 }
01962
01963 /**
01964   * @brief  Get ADC group regular sequencer length and scan direction.
01965   * @note   Description of ADC group regular sequencer features:
01966   *         - For devices with sequencer fully configurable
01967   *           (function "LL_ADC_REG_SetSequencerRanks()" available):
01968   *           sequencer length and each rank affectation to a channel
01969   *           are configurable.
01970   *           This function retrieves:
01971   *           - Sequence length: Number of ranks in the scan sequence.
01972   *           - Sequence direction: Unless specified in parameters, sequencer
01973   *             scan direction is forward (from rank 1 to rank n).
01974   *           Sequencer ranks are selected using
01975   *           function "LL_ADC_REG_SetSequencerRanks()".
01976   *         - For devices with sequencer not fully configurable
01977   *           (function "LL_ADC_REG_SetSequencerChannels()" available):
01978   *           sequencer length and each rank affectation to a channel
01979   *           are defined by channel number.
01980   *           This function retrieves:
01981   *           - Sequence length: Number of ranks in the scan sequence is
01982   *             defined by number of channels set in the sequence,
01983   *             rank of each channel is fixed by channel HW number.
01984   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
01985   *           - Sequence direction: Unless specified in parameters, sequencer
01986   *             scan direction is forward (from lowest channel number to
01987   *             highest channel number).
01988   *           Sequencer ranks are selected using
01989   *           function "LL_ADC_REG_SetSequencerChannels()".
01990   * @note   On this STM32 serie, group regular sequencer configuration
01991   *         is conditioned to ADC instance sequencer mode.
01992   *         If ADC instance sequencer mode is disabled, sequencers of
01993   *         all groups (group regular, group injected) can be configured
01994   *         but their execution is disabled (limited to rank 1).
01995   *         Refer to function @ref LL_ADC_SetSequencersScanMode().
01996   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
01997   *         ADC conversion on only 1 channel.
01998   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
01999   * @param  ADCx ADC instance
02000   * @retval Returned value can be one of the following values:
02001   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
02002   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
02003   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
02004   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
02005   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
02006   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
02007   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
02008   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
02009   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
02010   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
02011   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
02012   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
02013   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
02014   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
02015   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
02016   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
02017   */
02018 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
02019 {
02020   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
02021 }
02022
02023 /**
02024   * @brief  Set ADC group regular sequencer discontinuous mode:
02025   *         sequence subdivided and scan conversions interrupted every selected
02026   *         number of ranks.
02027   * @note   It is not possible to enable both ADC group regular
02028   *         continuous mode and sequencer discontinuous mode.
02029   * @note   It is not possible to enable both ADC auto-injected mode
02030   *         and ADC group regular sequencer discontinuous mode.
02031   * @rmtoll CR1      DISCEN         LL_ADC_REG_SetSequencerDiscont\n
02032   *         CR1      DISCNUM        LL_ADC_REG_SetSequencerDiscont
02033   * @param  ADCx ADC instance
02034   * @param  SeqDiscont This parameter can be one of the following values:
02035   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
02036   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
02037   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
02038   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
02039   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
02040   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
02041   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
02042   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
02043   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
02044   * @retval None
02045   */
02046 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
02047 {
02048   MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
02049 }
02050
02051 /**
02052   * @brief  Get ADC group regular sequencer discontinuous mode:
02053   *         sequence subdivided and scan conversions interrupted every selected
02054   *         number of ranks.
02055   * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont\n
02056   *         CR1      DISCNUM        LL_ADC_REG_GetSequencerDiscont
02057   * @param  ADCx ADC instance
02058   * @retval Returned value can be one of the following values:
02059   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
02060   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
02061   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
02062   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
02063   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
02064   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
02065   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
02066   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
02067   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
02068   */
02069 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
02070 {
02071   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
02072 }
02073
02074 /**
02075   * @brief  Set ADC group regular sequence: channel on the selected
02076   *         scan sequence rank.
02077   * @note   This function performs configuration of:
02078   *         - Channels ordering into each rank of scan sequence:
02079   *           whatever channel can be placed into whatever rank.
02080   * @note   On this STM32 serie, ADC group regular sequencer is
02081   *         fully configurable: sequencer length and each rank
02082   *         affectation to a channel are configurable.
02083   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
02084   * @note   Depending on devices and packages, some channels may not be available.
02085   *         Refer to device datasheet for channels availability.
02086   * @note   On this STM32 serie, to measure internal channels (VrefInt,
02087   *         TempSensor, ...), measurement paths to internal channels must be
02088   *         enabled separately.
02089   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
02090   * @rmtoll SQR3     SQ1            LL_ADC_REG_SetSequencerRanks\n
02091   *         SQR3     SQ2            LL_ADC_REG_SetSequencerRanks\n
02092   *         SQR3     SQ3            LL_ADC_REG_SetSequencerRanks\n
02093   *         SQR3     SQ4            LL_ADC_REG_SetSequencerRanks\n
02094   *         SQR3     SQ5            LL_ADC_REG_SetSequencerRanks\n
02095   *         SQR3     SQ6            LL_ADC_REG_SetSequencerRanks\n
02096   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
02097   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
02098   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
02099   *         SQR2     SQ10           LL_ADC_REG_SetSequencerRanks\n
02100   *         SQR2     SQ11           LL_ADC_REG_SetSequencerRanks\n
02101   *         SQR2     SQ12           LL_ADC_REG_SetSequencerRanks\n
02102   *         SQR1     SQ13           LL_ADC_REG_SetSequencerRanks\n
02103   *         SQR1     SQ14           LL_ADC_REG_SetSequencerRanks\n
02104   *         SQR1     SQ15           LL_ADC_REG_SetSequencerRanks\n
02105   *         SQR1     SQ16           LL_ADC_REG_SetSequencerRanks
02106   * @param  ADCx ADC instance
02107   * @param  Rank This parameter can be one of the following values:
02108   *         @arg @ref LL_ADC_REG_RANK_1
02109   *         @arg @ref LL_ADC_REG_RANK_2
02110   *         @arg @ref LL_ADC_REG_RANK_3
02111   *         @arg @ref LL_ADC_REG_RANK_4
02112   *         @arg @ref LL_ADC_REG_RANK_5
02113   *         @arg @ref LL_ADC_REG_RANK_6
02114   *         @arg @ref LL_ADC_REG_RANK_7
02115   *         @arg @ref LL_ADC_REG_RANK_8
02116   *         @arg @ref LL_ADC_REG_RANK_9
02117   *         @arg @ref LL_ADC_REG_RANK_10
02118   *         @arg @ref LL_ADC_REG_RANK_11
02119   *         @arg @ref LL_ADC_REG_RANK_12
02120   *         @arg @ref LL_ADC_REG_RANK_13
02121   *         @arg @ref LL_ADC_REG_RANK_14
02122   *         @arg @ref LL_ADC_REG_RANK_15
02123   *         @arg @ref LL_ADC_REG_RANK_16
02124   * @param  Channel This parameter can be one of the following values:
02125   *         @arg @ref LL_ADC_CHANNEL_0
02126   *         @arg @ref LL_ADC_CHANNEL_1
02127   *         @arg @ref LL_ADC_CHANNEL_2
02128   *         @arg @ref LL_ADC_CHANNEL_3
02129   *         @arg @ref LL_ADC_CHANNEL_4
02130   *         @arg @ref LL_ADC_CHANNEL_5
02131   *         @arg @ref LL_ADC_CHANNEL_6
02132   *         @arg @ref LL_ADC_CHANNEL_7
02133   *         @arg @ref LL_ADC_CHANNEL_8
02134   *         @arg @ref LL_ADC_CHANNEL_9
02135   *         @arg @ref LL_ADC_CHANNEL_10
02136   *         @arg @ref LL_ADC_CHANNEL_11
02137   *         @arg @ref LL_ADC_CHANNEL_12
02138   *         @arg @ref LL_ADC_CHANNEL_13
02139   *         @arg @ref LL_ADC_CHANNEL_14
02140   *         @arg @ref LL_ADC_CHANNEL_15
02141   *         @arg @ref LL_ADC_CHANNEL_16
02142   *         @arg @ref LL_ADC_CHANNEL_17
02143   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02144   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
02145   *
02146   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.
02147   * @retval None
02148   */
02149 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
02150 {
02151   /* Set bits with content of parameter "Channel" with bits position          */
02152   /* in register and register position depending on parameter "Rank".         */
02153   /* Parameters "Rank" and "Channel" are used with masks because containing   */
02154   /* other bits reserved for other purpose.                                   */
02155   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
02156
02157   MODIFY_REG(*preg,
02158              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
02159              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
02160 }
02161
02162 /**
02163   * @brief  Get ADC group regular sequence: channel on the selected
02164   *         scan sequence rank.
02165   * @note   On this STM32 serie, ADC group regular sequencer is
02166   *         fully configurable: sequencer length and each rank
02167   *         affectation to a channel are configurable.
02168   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
02169   * @note   Depending on devices and packages, some channels may not be available.
02170   *         Refer to device datasheet for channels availability.
02171   * @note   Usage of the returned channel number:
02172   *         - To reinject this channel into another function LL_ADC_xxx:
02173   *           the returned channel number is only partly formatted on definition
02174   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
02175   *           with parts of literals LL_ADC_CHANNEL_x or using
02176   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02177   *           Then the selected literal LL_ADC_CHANNEL_x can be used
02178   *           as parameter for another function.
02179   *         - To get the channel number in decimal format:
02180   *           process the returned value with the helper macro
02181   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02182   * @rmtoll SQR3     SQ1            LL_ADC_REG_GetSequencerRanks\n
02183   *         SQR3     SQ2            LL_ADC_REG_GetSequencerRanks\n
02184   *         SQR3     SQ3            LL_ADC_REG_GetSequencerRanks\n
02185   *         SQR3     SQ4            LL_ADC_REG_GetSequencerRanks\n
02186   *         SQR3     SQ5            LL_ADC_REG_GetSequencerRanks\n
02187   *         SQR3     SQ6            LL_ADC_REG_GetSequencerRanks\n
02188   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
02189   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
02190   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
02191   *         SQR2     SQ10           LL_ADC_REG_GetSequencerRanks\n
02192   *         SQR2     SQ11           LL_ADC_REG_GetSequencerRanks\n
02193   *         SQR2     SQ12           LL_ADC_REG_GetSequencerRanks\n
02194   *         SQR1     SQ13           LL_ADC_REG_GetSequencerRanks\n
02195   *         SQR1     SQ14           LL_ADC_REG_GetSequencerRanks\n
02196   *         SQR1     SQ15           LL_ADC_REG_GetSequencerRanks\n
02197   *         SQR1     SQ16           LL_ADC_REG_GetSequencerRanks
02198   * @param  ADCx ADC instance
02199   * @param  Rank This parameter can be one of the following values:
02200   *         @arg @ref LL_ADC_REG_RANK_1
02201   *         @arg @ref LL_ADC_REG_RANK_2
02202   *         @arg @ref LL_ADC_REG_RANK_3
02203   *         @arg @ref LL_ADC_REG_RANK_4
02204   *         @arg @ref LL_ADC_REG_RANK_5
02205   *         @arg @ref LL_ADC_REG_RANK_6
02206   *         @arg @ref LL_ADC_REG_RANK_7
02207   *         @arg @ref LL_ADC_REG_RANK_8
02208   *         @arg @ref LL_ADC_REG_RANK_9
02209   *         @arg @ref LL_ADC_REG_RANK_10
02210   *         @arg @ref LL_ADC_REG_RANK_11
02211   *         @arg @ref LL_ADC_REG_RANK_12
02212   *         @arg @ref LL_ADC_REG_RANK_13
02213   *         @arg @ref LL_ADC_REG_RANK_14
02214   *         @arg @ref LL_ADC_REG_RANK_15
02215   *         @arg @ref LL_ADC_REG_RANK_16
02216   * @retval Returned value can be one of the following values:
02217   *         @arg @ref LL_ADC_CHANNEL_0
02218   *         @arg @ref LL_ADC_CHANNEL_1
02219   *         @arg @ref LL_ADC_CHANNEL_2
02220   *         @arg @ref LL_ADC_CHANNEL_3
02221   *         @arg @ref LL_ADC_CHANNEL_4
02222   *         @arg @ref LL_ADC_CHANNEL_5
02223   *         @arg @ref LL_ADC_CHANNEL_6
02224   *         @arg @ref LL_ADC_CHANNEL_7
02225   *         @arg @ref LL_ADC_CHANNEL_8
02226   *         @arg @ref LL_ADC_CHANNEL_9
02227   *         @arg @ref LL_ADC_CHANNEL_10
02228   *         @arg @ref LL_ADC_CHANNEL_11
02229   *         @arg @ref LL_ADC_CHANNEL_12
02230   *         @arg @ref LL_ADC_CHANNEL_13
02231   *         @arg @ref LL_ADC_CHANNEL_14
02232   *         @arg @ref LL_ADC_CHANNEL_15
02233   *         @arg @ref LL_ADC_CHANNEL_16
02234   *         @arg @ref LL_ADC_CHANNEL_17
02235   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02236   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
02237   *
02238   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
02239   *         (1) For ADC channel read back from ADC register,
02240   *             comparison with internal channel parameter to be done
02241   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
02242   */
02243 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
02244 {
02245   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
02246
02247   return (uint32_t) (READ_BIT(*preg,
02248                               ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
02249                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
02250                     );
02251 }
02252
02253 /**
02254   * @brief  Set ADC continuous conversion mode on ADC group regular.
02255   * @note   Description of ADC continuous conversion mode:
02256   *         - single mode: one conversion per trigger
02257   *         - continuous mode: after the first trigger, following
02258   *           conversions launched successively automatically.
02259   * @note   It is not possible to enable both ADC group regular
02260   *         continuous mode and sequencer discontinuous mode.
02261   * @rmtoll CR2      CONT           LL_ADC_REG_SetContinuousMode
02262   * @param  ADCx ADC instance
02263   * @param  Continuous This parameter can be one of the following values:
02264   *         @arg @ref LL_ADC_REG_CONV_SINGLE
02265   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
02266   * @retval None
02267   */
02268 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
02269 {
02270   MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
02271 }
02272
02273 /**
02274   * @brief  Get ADC continuous conversion mode on ADC group regular.
02275   * @note   Description of ADC continuous conversion mode:
02276   *         - single mode: one conversion per trigger
02277   *         - continuous mode: after the first trigger, following
02278   *           conversions launched successively automatically.
02279   * @rmtoll CR2      CONT           LL_ADC_REG_GetContinuousMode
02280   * @param  ADCx ADC instance
02281   * @retval Returned value can be one of the following values:
02282   *         @arg @ref LL_ADC_REG_CONV_SINGLE
02283   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
02284   */
02285 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
02286 {
02287   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
02288 }
02289
02290 /**
02291   * @brief  Set ADC group regular conversion data transfer: no transfer or
02292   *         transfer by DMA, and DMA requests mode.
02293   * @note   If transfer by DMA selected, specifies the DMA requests
02294   *         mode:
02295   *         - Limited mode (One shot mode): DMA transfer requests are stopped
02296   *           when number of DMA data transfers (number of
02297   *           ADC conversions) is reached.
02298   *           This ADC mode is intended to be used with DMA mode non-circular.
02299   *         - Unlimited mode: DMA transfer requests are unlimited,
02300   *           whatever number of DMA data transfers (number of
02301   *           ADC conversions).
02302   *           This ADC mode is intended to be used with DMA mode circular.
02303   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
02304   *         mode non-circular:
02305   *         when DMA transfers size will be reached, DMA will stop transfers of
02306   *         ADC conversions data ADC will raise an overrun error
02307   *        (overrun flag and interruption if enabled).
02308   * @note   To configure DMA source address (peripheral address),
02309   *         use function @ref LL_ADC_DMA_GetRegAddr().
02310   * @rmtoll CR2      DMA            LL_ADC_REG_SetDMATransfer
02311   * @param  ADCx ADC instance
02312   * @param  DMATransfer This parameter can be one of the following values:
02313   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
02314   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
02315   * @retval None
02316   */
02317 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
02318 {
02319   MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
02320 }
02321
02322 /**
02323   * @brief  Get ADC group regular conversion data transfer: no transfer or
02324   *         transfer by DMA, and DMA requests mode.
02325   * @note   If transfer by DMA selected, specifies the DMA requests
02326   *         mode:
02327   *         - Limited mode (One shot mode): DMA transfer requests are stopped
02328   *           when number of DMA data transfers (number of
02329   *           ADC conversions) is reached.
02330   *           This ADC mode is intended to be used with DMA mode non-circular.
02331   *         - Unlimited mode: DMA transfer requests are unlimited,
02332   *           whatever number of DMA data transfers (number of
02333   *           ADC conversions).
02334   *           This ADC mode is intended to be used with DMA mode circular.
02335   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
02336   *         mode non-circular:
02337   *         when DMA transfers size will be reached, DMA will stop transfers of
02338   *         ADC conversions data ADC will raise an overrun error
02339   *         (overrun flag and interruption if enabled).
02340   * @note   To configure DMA source address (peripheral address),
02341   *         use function @ref LL_ADC_DMA_GetRegAddr().
02342   * @rmtoll CR2      DMA            LL_ADC_REG_GetDMATransfer
02343   * @param  ADCx ADC instance
02344   * @retval Returned value can be one of the following values:
02345   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
02346   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
02347   */
02348 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
02349 {
02350   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
02351 }
02352
02353 /**
02354   * @}
02355   */
02356
02357 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
02358   * @{
02359   */
02360
02361 /**
02362   * @brief  Set ADC group injected conversion trigger source:
02363   *         internal (SW start) or from external IP (timer event,
02364   *         external interrupt line).
02365   * @note   On this STM32 serie, external trigger is set with trigger polarity:
02366   *         rising edge (only trigger polarity available on this STM32 serie).
02367   * @note   Availability of parameters of trigger sources from timer
02368   *         depends on timers availability on the selected device.
02369   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_SetTriggerSource
02370   * @param  ADCx ADC instance
02371   * @param  TriggerSource This parameter can be one of the following values:
02372   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
02373   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO     (1)
02374   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4      (1)
02375   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO     (2)
02376   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1      (2)
02377   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4      (2)
02378   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO     (2)
02379   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15   (2)
02380   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4      (2)(4)
02381   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
02382   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3      (3)
02383   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2      (3)
02384   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4      (3)
02385   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO     (3)
02386   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4      (3)
02387   *
02388   *         (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
02389   *         (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
02390   *         (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
02391   *         (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
02392   * @retval None
02393   */
02394 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
02395 {
02396 /* Note: On this STM32 serie, ADC group injected external trigger edge       */
02397 /*       is used to perform a ADC conversion start.                           */
02398 /*       This function does not set external trigger edge.                    */
02399 /*       This feature is set using function                                   */
02400 /*       @ref LL_ADC_INJ_StartConversionExtTrig().                            */
02401   MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
02402 }
02403
02404 /**
02405   * @brief  Get ADC group injected conversion trigger source:
02406   *         internal (SW start) or from external IP (timer event,
02407   *         external interrupt line).
02408   * @note   To determine whether group injected trigger source is
02409   *         internal (SW start) or external, without detail
02410   *         of which peripheral is selected as external trigger,
02411   *         (equivalent to
02412   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
02413   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
02414   * @note   Availability of parameters of trigger sources from timer
02415   *         depends on timers availability on the selected device.
02416   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_GetTriggerSource
02417   * @param  ADCx ADC instance
02418   * @retval Returned value can be one of the following values:
02419   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
02420   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO     (1)
02421   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4      (1)
02422   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO     (2)
02423   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1      (2)
02424   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4      (2)
02425   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO     (2)
02426   *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15   (2)
02427   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4      (2)(4)
02428   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
02429   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3      (3)
02430   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2      (3)
02431   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4      (3)
02432   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO     (3)
02433   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4      (3)
02434   *
02435   *         (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
02436   *         (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
02437   *         (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
02438   *         (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
02439   */
02440 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
02441 {
02442   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
02443 }
02444
02445 /**
02446   * @brief  Get ADC group injected conversion trigger source internal (SW start)
02447             or external
02448   * @note   In case of group injected trigger source set to external trigger,
02449   *         to determine which peripheral is selected as external trigger,
02450   *         use function @ref LL_ADC_INJ_GetTriggerSource.
02451   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_IsTriggerSourceSWStart
02452   * @param  ADCx ADC instance
02453   * @retval Value "0" if trigger source external trigger
02454   *         Value "1" if trigger source SW start.
02455   */
02456 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
02457 {
02458   return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
02459 }
02460
02461 /**
02462   * @brief  Set ADC group injected sequencer length and scan direction.
02463   * @note   This function performs configuration of:
02464   *         - Sequence length: Number of ranks in the scan sequence.
02465   *         - Sequence direction: Unless specified in parameters, sequencer
02466   *           scan direction is forward (from rank 1 to rank n).
02467   * @note   On this STM32 serie, group injected sequencer configuration
02468   *         is conditioned to ADC instance sequencer mode.
02469   *         If ADC instance sequencer mode is disabled, sequencers of
02470   *         all groups (group regular, group injected) can be configured
02471   *         but their execution is disabled (limited to rank 1).
02472   *         Refer to function @ref LL_ADC_SetSequencersScanMode().
02473   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
02474   *         ADC conversion on only 1 channel.
02475   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
02476   * @param  ADCx ADC instance
02477   * @param  SequencerNbRanks This parameter can be one of the following values:
02478   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
02479   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
02480   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
02481   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
02482   * @retval None
02483   */
02484 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
02485 {
02486   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
02487 }
02488
02489 /**
02490   * @brief  Get ADC group injected sequencer length and scan direction.
02491   * @note   This function retrieves:
02492   *         - Sequence length: Number of ranks in the scan sequence.
02493   *         - Sequence direction: Unless specified in parameters, sequencer
02494   *           scan direction is forward (from rank 1 to rank n).
02495   * @note   On this STM32 serie, group injected sequencer configuration
02496   *         is conditioned to ADC instance sequencer mode.
02497   *         If ADC instance sequencer mode is disabled, sequencers of
02498   *         all groups (group regular, group injected) can be configured
02499   *         but their execution is disabled (limited to rank 1).
02500   *         Refer to function @ref LL_ADC_SetSequencersScanMode().
02501   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
02502   *         ADC conversion on only 1 channel.
02503   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
02504   * @param  ADCx ADC instance
02505   * @retval Returned value can be one of the following values:
02506   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
02507   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
02508   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
02509   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
02510   */
02511 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
02512 {
02513   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
02514 }
02515
02516 /**
02517   * @brief  Set ADC group injected sequencer discontinuous mode:
02518   *         sequence subdivided and scan conversions interrupted every selected
02519   *         number of ranks.
02520   * @note   It is not possible to enable both ADC group injected
02521   *         auto-injected mode and sequencer discontinuous mode.
02522   * @rmtoll CR1      DISCEN         LL_ADC_INJ_SetSequencerDiscont
02523   * @param  ADCx ADC instance
02524   * @param  SeqDiscont This parameter can be one of the following values:
02525   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
02526   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
02527   * @retval None
02528   */
02529 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
02530 {
02531   MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
02532 }
02533
02534 /**
02535   * @brief  Get ADC group injected sequencer discontinuous mode:
02536   *         sequence subdivided and scan conversions interrupted every selected
02537   *         number of ranks.
02538   * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont
02539   * @param  ADCx ADC instance
02540   * @retval Returned value can be one of the following values:
02541   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
02542   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
02543   */
02544 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
02545 {
02546   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
02547 }
02548
02549 /**
02550   * @brief  Set ADC group injected sequence: channel on the selected
02551   *         sequence rank.
02552   * @note   Depending on devices and packages, some channels may not be available.
02553   *         Refer to device datasheet for channels availability.
02554   * @note   On this STM32 serie, to measure internal channels (VrefInt,
02555   *         TempSensor, ...), measurement paths to internal channels must be
02556   *         enabled separately.
02557   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
02558   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
02559   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
02560   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
02561   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
02562   * @param  ADCx ADC instance
02563   * @param  Rank This parameter can be one of the following values:
02564   *         @arg @ref LL_ADC_INJ_RANK_1
02565   *         @arg @ref LL_ADC_INJ_RANK_2
02566   *         @arg @ref LL_ADC_INJ_RANK_3
02567   *         @arg @ref LL_ADC_INJ_RANK_4
02568   * @param  Channel This parameter can be one of the following values:
02569   *         @arg @ref LL_ADC_CHANNEL_0
02570   *         @arg @ref LL_ADC_CHANNEL_1
02571   *         @arg @ref LL_ADC_CHANNEL_2
02572   *         @arg @ref LL_ADC_CHANNEL_3
02573   *         @arg @ref LL_ADC_CHANNEL_4
02574   *         @arg @ref LL_ADC_CHANNEL_5
02575   *         @arg @ref LL_ADC_CHANNEL_6
02576   *         @arg @ref LL_ADC_CHANNEL_7
02577   *         @arg @ref LL_ADC_CHANNEL_8
02578   *         @arg @ref LL_ADC_CHANNEL_9
02579   *         @arg @ref LL_ADC_CHANNEL_10
02580   *         @arg @ref LL_ADC_CHANNEL_11
02581   *         @arg @ref LL_ADC_CHANNEL_12
02582   *         @arg @ref LL_ADC_CHANNEL_13
02583   *         @arg @ref LL_ADC_CHANNEL_14
02584   *         @arg @ref LL_ADC_CHANNEL_15
02585   *         @arg @ref LL_ADC_CHANNEL_16
02586   *         @arg @ref LL_ADC_CHANNEL_17
02587   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02588   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
02589   *
02590   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.
02591   * @retval None
02592   */
02593 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
02594 {
02595   /* Set bits with content of parameter "Channel" with bits position          */
02596   /* in register depending on parameter "Rank".                               */
02597   /* Parameters "Rank" and "Channel" are used with masks because containing   */
02598   /* other bits reserved for other purpose.                                   */
02599   register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
02600
02601   MODIFY_REG(ADCx->JSQR,
02602              ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
02603              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
02604 }
02605
02606 /**
02607   * @brief  Get ADC group injected sequence: channel on the selected
02608   *         sequence rank.
02609   * @note   Depending on devices and packages, some channels may not be available.
02610   *         Refer to device datasheet for channels availability.
02611   * @note   Usage of the returned channel number:
02612   *         - To reinject this channel into another function LL_ADC_xxx:
02613   *           the returned channel number is only partly formatted on definition
02614   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
02615   *           with parts of literals LL_ADC_CHANNEL_x or using
02616   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02617   *           Then the selected literal LL_ADC_CHANNEL_x can be used
02618   *           as parameter for another function.
02619   *         - To get the channel number in decimal format:
02620   *           process the returned value with the helper macro
02621   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
02622   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
02623   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
02624   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
02625   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
02626   * @param  ADCx ADC instance
02627   * @param  Rank This parameter can be one of the following values:
02628   *         @arg @ref LL_ADC_INJ_RANK_1
02629   *         @arg @ref LL_ADC_INJ_RANK_2
02630   *         @arg @ref LL_ADC_INJ_RANK_3
02631   *         @arg @ref LL_ADC_INJ_RANK_4
02632   * @retval Returned value can be one of the following values:
02633   *         @arg @ref LL_ADC_CHANNEL_0
02634   *         @arg @ref LL_ADC_CHANNEL_1
02635   *         @arg @ref LL_ADC_CHANNEL_2
02636   *         @arg @ref LL_ADC_CHANNEL_3
02637   *         @arg @ref LL_ADC_CHANNEL_4
02638   *         @arg @ref LL_ADC_CHANNEL_5
02639   *         @arg @ref LL_ADC_CHANNEL_6
02640   *         @arg @ref LL_ADC_CHANNEL_7
02641   *         @arg @ref LL_ADC_CHANNEL_8
02642   *         @arg @ref LL_ADC_CHANNEL_9
02643   *         @arg @ref LL_ADC_CHANNEL_10
02644   *         @arg @ref LL_ADC_CHANNEL_11
02645   *         @arg @ref LL_ADC_CHANNEL_12
02646   *         @arg @ref LL_ADC_CHANNEL_13
02647   *         @arg @ref LL_ADC_CHANNEL_14
02648   *         @arg @ref LL_ADC_CHANNEL_15
02649   *         @arg @ref LL_ADC_CHANNEL_16
02650   *         @arg @ref LL_ADC_CHANNEL_17
02651   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02652   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
02653   *
02654   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
02655   *         (1) For ADC channel read back from ADC register,
02656   *             comparison with internal channel parameter to be done
02657   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
02658   */
02659 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
02660 {
02661   register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos)  + 1U;
02662
02663   return (uint32_t)(READ_BIT(ADCx->JSQR,
02664                              ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
02665                     >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
02666                    );
02667 }
02668
02669 /**
02670   * @brief  Set ADC group injected conversion trigger:
02671   *         independent or from ADC group regular.
02672   * @note   This mode can be used to extend number of data registers
02673   *         updated after one ADC conversion trigger and with data
02674   *         permanently kept (not erased by successive conversions of scan of
02675   *         ADC sequencer ranks), up to 5 data registers:
02676   *         1 data register on ADC group regular, 4 data registers
02677   *         on ADC group injected.
02678   * @note   If ADC group injected injected trigger source is set to an
02679   *         external trigger, this feature must be must be set to
02680   *         independent trigger.
02681   *         ADC group injected automatic trigger is compliant only with
02682   *         group injected trigger source set to SW start, without any
02683   *         further action on  ADC group injected conversion start or stop:
02684   *         in this case, ADC group injected is controlled only
02685   *         from ADC group regular.
02686   * @note   It is not possible to enable both ADC group injected
02687   *         auto-injected mode and sequencer discontinuous mode.
02688   * @rmtoll CR1      JAUTO          LL_ADC_INJ_SetTrigAuto
02689   * @param  ADCx ADC instance
02690   * @param  TrigAuto This parameter can be one of the following values:
02691   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
02692   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
02693   * @retval None
02694   */
02695 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
02696 {
02697   MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
02698 }
02699
02700 /**
02701   * @brief  Get ADC group injected conversion trigger:
02702   *         independent or from ADC group regular.
02703   * @rmtoll CR1      JAUTO          LL_ADC_INJ_GetTrigAuto
02704   * @param  ADCx ADC instance
02705   * @retval Returned value can be one of the following values:
02706   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
02707   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
02708   */
02709 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
02710 {
02711   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
02712 }
02713
02714 /**
02715   * @brief  Set ADC group injected offset.
02716   * @note   It sets:
02717   *         - ADC group injected rank to which the offset programmed
02718   *           will be applied
02719   *         - Offset level (offset to be subtracted from the raw
02720   *           converted data).
02721   *         Caution: Offset format is dependent to ADC resolution:
02722   *         offset has to be left-aligned on bit 11, the LSB (right bits)
02723   *         are set to 0.
02724   * @note   Offset cannot be enabled or disabled.
02725   *         To emulate offset disabled, set an offset value equal to 0.
02726   * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_SetOffset\n
02727   *         JOFR2    JOFFSET2       LL_ADC_INJ_SetOffset\n
02728   *         JOFR3    JOFFSET3       LL_ADC_INJ_SetOffset\n
02729   *         JOFR4    JOFFSET4       LL_ADC_INJ_SetOffset
02730   * @param  ADCx ADC instance
02731   * @param  Rank This parameter can be one of the following values:
02732   *         @arg @ref LL_ADC_INJ_RANK_1
02733   *         @arg @ref LL_ADC_INJ_RANK_2
02734   *         @arg @ref LL_ADC_INJ_RANK_3
02735   *         @arg @ref LL_ADC_INJ_RANK_4
02736   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
02737   * @retval None
02738   */
02739 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
02740 {
02741   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
02742
02743   MODIFY_REG(*preg,
02744              ADC_JOFR1_JOFFSET1,
02745              OffsetLevel);
02746 }
02747
02748 /**
02749   * @brief  Get ADC group injected offset.
02750   * @note   It gives offset level (offset to be subtracted from the raw converted data).
02751   *         Caution: Offset format is dependent to ADC resolution:
02752   *         offset has to be left-aligned on bit 11, the LSB (right bits)
02753   *         are set to 0.
02754   * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_GetOffset\n
02755   *         JOFR2    JOFFSET2       LL_ADC_INJ_GetOffset\n
02756   *         JOFR3    JOFFSET3       LL_ADC_INJ_GetOffset\n
02757   *         JOFR4    JOFFSET4       LL_ADC_INJ_GetOffset
02758   * @param  ADCx ADC instance
02759   * @param  Rank This parameter can be one of the following values:
02760   *         @arg @ref LL_ADC_INJ_RANK_1
02761   *         @arg @ref LL_ADC_INJ_RANK_2
02762   *         @arg @ref LL_ADC_INJ_RANK_3
02763   *         @arg @ref LL_ADC_INJ_RANK_4
02764   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
02765   */
02766 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
02767 {
02768   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
02769
02770   return (uint32_t)(READ_BIT(*preg,
02771                              ADC_JOFR1_JOFFSET1)
02772                    );
02773 }
02774
02775 /**
02776   * @}
02777   */
02778
02779 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
02780   * @{
02781   */
02782
02783 /**
02784   * @brief  Set sampling time of the selected ADC channel
02785   *         Unit: ADC clock cycles.
02786   * @note   On this device, sampling time is on channel scope: independently
02787   *         of channel mapped on ADC group regular or injected.
02788   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
02789   *         converted:
02790   *         sampling time constraints must be respected (sampling time can be
02791   *         adjusted in function of ADC clock frequency and sampling time
02792   *         setting).
02793   *         Refer to device datasheet for timings values (parameters TS_vrefint,
02794   *         TS_temp, ...).
02795   * @note   Conversion time is the addition of sampling time and processing time.
02796   *         Refer to reference manual for ADC processing time of
02797   *         this STM32 serie.
02798   * @note   In case of ADC conversion of internal channel (VrefInt,
02799   *         temperature sensor, ...), a sampling time minimum value
02800   *         is required.
02801   *         Refer to device datasheet.
02802   * @rmtoll SMPR1    SMP17          LL_ADC_SetChannelSamplingTime\n
02803   *         SMPR1    SMP16          LL_ADC_SetChannelSamplingTime\n
02804   *         SMPR1    SMP15          LL_ADC_SetChannelSamplingTime\n
02805   *         SMPR1    SMP14          LL_ADC_SetChannelSamplingTime\n
02806   *         SMPR1    SMP13          LL_ADC_SetChannelSamplingTime\n
02807   *         SMPR1    SMP12          LL_ADC_SetChannelSamplingTime\n
02808   *         SMPR1    SMP11          LL_ADC_SetChannelSamplingTime\n
02809   *         SMPR1    SMP10          LL_ADC_SetChannelSamplingTime\n
02810   *         SMPR2    SMP9           LL_ADC_SetChannelSamplingTime\n
02811   *         SMPR2    SMP8           LL_ADC_SetChannelSamplingTime\n
02812   *         SMPR2    SMP7           LL_ADC_SetChannelSamplingTime\n
02813   *         SMPR2    SMP6           LL_ADC_SetChannelSamplingTime\n
02814   *         SMPR2    SMP5           LL_ADC_SetChannelSamplingTime\n
02815   *         SMPR2    SMP4           LL_ADC_SetChannelSamplingTime\n
02816   *         SMPR2    SMP3           LL_ADC_SetChannelSamplingTime\n
02817   *         SMPR2    SMP2           LL_ADC_SetChannelSamplingTime\n
02818   *         SMPR2    SMP1           LL_ADC_SetChannelSamplingTime\n
02819   *         SMPR2    SMP0           LL_ADC_SetChannelSamplingTime
02820   * @param  ADCx ADC instance
02821   * @param  Channel This parameter can be one of the following values:
02822   *         @arg @ref LL_ADC_CHANNEL_0
02823   *         @arg @ref LL_ADC_CHANNEL_1
02824   *         @arg @ref LL_ADC_CHANNEL_2
02825   *         @arg @ref LL_ADC_CHANNEL_3
02826   *         @arg @ref LL_ADC_CHANNEL_4
02827   *         @arg @ref LL_ADC_CHANNEL_5
02828   *         @arg @ref LL_ADC_CHANNEL_6
02829   *         @arg @ref LL_ADC_CHANNEL_7
02830   *         @arg @ref LL_ADC_CHANNEL_8
02831   *         @arg @ref LL_ADC_CHANNEL_9
02832   *         @arg @ref LL_ADC_CHANNEL_10
02833   *         @arg @ref LL_ADC_CHANNEL_11
02834   *         @arg @ref LL_ADC_CHANNEL_12
02835   *         @arg @ref LL_ADC_CHANNEL_13
02836   *         @arg @ref LL_ADC_CHANNEL_14
02837   *         @arg @ref LL_ADC_CHANNEL_15
02838   *         @arg @ref LL_ADC_CHANNEL_16
02839   *         @arg @ref LL_ADC_CHANNEL_17
02840   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02841   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
02842   *
02843   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.
02844   * @param  SamplingTime This parameter can be one of the following values:
02845   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
02846   *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
02847   *         @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
02848   *         @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
02849   *         @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
02850   *         @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
02851   *         @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
02852   *         @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
02853   * @retval None
02854   */
02855 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
02856 {
02857   /* Set bits with content of parameter "SamplingTime" with bits position     */
02858   /* in register and register position depending on parameter "Channel".      */
02859   /* Parameter "Channel" is used with masks because containing                */
02860   /* other bits reserved for other purpose.                                   */
02861   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
02862
02863   MODIFY_REG(*preg,
02864              ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
02865              SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
02866 }
02867
02868 /**
02869   * @brief  Get sampling time of the selected ADC channel
02870   *         Unit: ADC clock cycles.
02871   * @note   On this device, sampling time is on channel scope: independently
02872   *         of channel mapped on ADC group regular or injected.
02873   * @note   Conversion time is the addition of sampling time and processing time.
02874   *         Refer to reference manual for ADC processing time of
02875   *         this STM32 serie.
02876   * @rmtoll SMPR1    SMP17          LL_ADC_GetChannelSamplingTime\n
02877   *         SMPR1    SMP16          LL_ADC_GetChannelSamplingTime\n
02878   *         SMPR1    SMP15          LL_ADC_GetChannelSamplingTime\n
02879   *         SMPR1    SMP14          LL_ADC_GetChannelSamplingTime\n
02880   *         SMPR1    SMP13          LL_ADC_GetChannelSamplingTime\n
02881   *         SMPR1    SMP12          LL_ADC_GetChannelSamplingTime\n
02882   *         SMPR1    SMP11          LL_ADC_GetChannelSamplingTime\n
02883   *         SMPR1    SMP10          LL_ADC_GetChannelSamplingTime\n
02884   *         SMPR2    SMP9           LL_ADC_GetChannelSamplingTime\n
02885   *         SMPR2    SMP8           LL_ADC_GetChannelSamplingTime\n
02886   *         SMPR2    SMP7           LL_ADC_GetChannelSamplingTime\n
02887   *         SMPR2    SMP6           LL_ADC_GetChannelSamplingTime\n
02888   *         SMPR2    SMP5           LL_ADC_GetChannelSamplingTime\n
02889   *         SMPR2    SMP4           LL_ADC_GetChannelSamplingTime\n
02890   *         SMPR2    SMP3           LL_ADC_GetChannelSamplingTime\n
02891   *         SMPR2    SMP2           LL_ADC_GetChannelSamplingTime\n
02892   *         SMPR2    SMP1           LL_ADC_GetChannelSamplingTime\n
02893   *         SMPR2    SMP0           LL_ADC_GetChannelSamplingTime
02894   * @param  ADCx ADC instance
02895   * @param  Channel This parameter can be one of the following values:
02896   *         @arg @ref LL_ADC_CHANNEL_0
02897   *         @arg @ref LL_ADC_CHANNEL_1
02898   *         @arg @ref LL_ADC_CHANNEL_2
02899   *         @arg @ref LL_ADC_CHANNEL_3
02900   *         @arg @ref LL_ADC_CHANNEL_4
02901   *         @arg @ref LL_ADC_CHANNEL_5
02902   *         @arg @ref LL_ADC_CHANNEL_6
02903   *         @arg @ref LL_ADC_CHANNEL_7
02904   *         @arg @ref LL_ADC_CHANNEL_8
02905   *         @arg @ref LL_ADC_CHANNEL_9
02906   *         @arg @ref LL_ADC_CHANNEL_10
02907   *         @arg @ref LL_ADC_CHANNEL_11
02908   *         @arg @ref LL_ADC_CHANNEL_12
02909   *         @arg @ref LL_ADC_CHANNEL_13
02910   *         @arg @ref LL_ADC_CHANNEL_14
02911   *         @arg @ref LL_ADC_CHANNEL_15
02912   *         @arg @ref LL_ADC_CHANNEL_16
02913   *         @arg @ref LL_ADC_CHANNEL_17
02914   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)
02915   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)
02916   *
02917   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.
02918   * @retval Returned value can be one of the following values:
02919   *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
02920   *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
02921   *         @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
02922   *         @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
02923   *         @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
02924   *         @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
02925   *         @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
02926   *         @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
02927   */
02928 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
02929 {
02930   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
02931
02932   return (uint32_t)(READ_BIT(*preg,
02933                              ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
02934                     >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
02935                    );
02936 }
02937
02938 /**
02939   * @}
02940   */
02941
02942 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
02943   * @{
02944   */
02945
02946 /**
02947   * @brief  Set ADC analog watchdog monitored channels:
02948   *         a single channel or all channels,
02949   *         on ADC groups regular and-or injected.
02950   * @note   Once monitored channels are selected, analog watchdog
02951   *         is enabled.
02952   * @note   In case of need to define a single channel to monitor
02953   *         with analog watchdog from sequencer channel definition,
02954   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
02955   * @note   On this STM32 serie, there is only 1 kind of analog watchdog
02956   *         instance:
02957   *         - AWD standard (instance AWD1):
02958   *           - channels monitored: can monitor 1 channel or all channels.
02959   *           - groups monitored: ADC groups regular and-or injected.
02960   *           - resolution: resolution is not limited (corresponds to
02961   *             ADC resolution configured).
02962   * @rmtoll CR1      AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
02963   *         CR1      AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
02964   *         CR1      AWD1EN         LL_ADC_SetAnalogWDMonitChannels
02965   * @param  ADCx ADC instance
02966   * @param  AWDChannelGroup This parameter can be one of the following values:
02967   *         @arg @ref LL_ADC_AWD_DISABLE
02968   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
02969   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
02970   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
02971   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
02972   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
02973   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
02974   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
02975   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
02976   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
02977   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
02978   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
02979   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
02980   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
02981   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
02982   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
02983   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
02984   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
02985   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
02986   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
02987   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
02988   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
02989   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
02990   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
02991   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
02992   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
02993   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
02994   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
02995   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
02996   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
02997   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
02998   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
02999   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
03000   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
03001   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
03002   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
03003   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
03004   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
03005   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
03006   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
03007   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
03008   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
03009   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
03010   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
03011   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
03012   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
03013   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
03014   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
03015   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
03016   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
03017   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
03018   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
03019   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
03020   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
03021   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
03022   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
03023   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
03024   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
03025   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (1)
03026   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (1)
03027   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (1)
03028   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (1)
03029   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (1)
03030   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (1)
03031   *
03032   *         (1) On STM32F1, parameter available only on ADC instance: ADC1.
03033   * @retval None
03034   */
03035 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
03036 {
03037   MODIFY_REG(ADCx->CR1,
03038              (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
03039              AWDChannelGroup);
03040 }
03041
03042 /**
03043   * @brief  Get ADC analog watchdog monitored channel.
03044   * @note   Usage of the returned channel number:
03045   *         - To reinject this channel into another function LL_ADC_xxx:
03046   *           the returned channel number is only partly formatted on definition
03047   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
03048   *           with parts of literals LL_ADC_CHANNEL_x or using
03049   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03050   *           Then the selected literal LL_ADC_CHANNEL_x can be used
03051   *           as parameter for another function.
03052   *         - To get the channel number in decimal format:
03053   *           process the returned value with the helper macro
03054   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
03055   *           Applicable only when the analog watchdog is set to monitor
03056   *           one channel.
03057   * @note   On this STM32 serie, there is only 1 kind of analog watchdog
03058   *         instance:
03059   *         - AWD standard (instance AWD1):
03060   *           - channels monitored: can monitor 1 channel or all channels.
03061   *           - groups monitored: ADC groups regular and-or injected.
03062   *           - resolution: resolution is not limited (corresponds to
03063   *             ADC resolution configured).
03064   * @rmtoll CR1      AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
03065   *         CR1      AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
03066   *         CR1      AWD1EN         LL_ADC_GetAnalogWDMonitChannels
03067   * @param  ADCx ADC instance
03068   * @retval Returned value can be one of the following values:
03069   *         @arg @ref LL_ADC_AWD_DISABLE
03070   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
03071   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
03072   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
03073   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
03074   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
03075   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
03076   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
03077   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
03078   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
03079   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
03080   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
03081   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
03082   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
03083   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
03084   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
03085   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
03086   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
03087   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
03088   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
03089   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
03090   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
03091   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
03092   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
03093   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
03094   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
03095   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
03096   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
03097   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
03098   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
03099   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
03100   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
03101   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
03102   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
03103   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
03104   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
03105   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
03106   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
03107   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
03108   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
03109   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
03110   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
03111   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
03112   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
03113   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
03114   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
03115   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
03116   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
03117   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
03118   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
03119   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
03120   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
03121   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
03122   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
03123   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
03124   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
03125   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
03126   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
03127   */
03128 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
03129 {
03130   return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
03131 }
03132
03133 /**
03134   * @brief  Set ADC analog watchdog threshold value of threshold
03135   *         high or low.
03136   * @note   On this STM32 serie, there is only 1 kind of analog watchdog
03137   *         instance:
03138   *         - AWD standard (instance AWD1):
03139   *           - channels monitored: can monitor 1 channel or all channels.
03140   *           - groups monitored: ADC groups regular and-or injected.
03141   *           - resolution: resolution is not limited (corresponds to
03142   *             ADC resolution configured).
03143   * @rmtoll HTR      HT             LL_ADC_SetAnalogWDThresholds\n
03144   *         LTR      LT             LL_ADC_SetAnalogWDThresholds
03145   * @param  ADCx ADC instance
03146   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
03147   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
03148   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
03149   * @param  AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
03150   * @retval None
03151   */
03152 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
03153 {
03154   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
03155
03156   MODIFY_REG(*preg,
03157              ADC_HTR_HT,
03158              AWDThresholdValue);
03159 }
03160
03161 /**
03162   * @brief  Get ADC analog watchdog threshold value of threshold high or
03163   *         threshold low.
03164   * @note   In case of ADC resolution different of 12 bits,
03165   *         analog watchdog thresholds data require a specific shift.
03166   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
03167   * @rmtoll HTR      HT             LL_ADC_GetAnalogWDThresholds\n
03168   *         LTR      LT             LL_ADC_GetAnalogWDThresholds
03169   * @param  ADCx ADC instance
03170   * @param  AWDThresholdsHighLow This parameter can be one of the following values:
03171   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
03172   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
03173   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
03174 */
03175 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
03176 {
03177   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
03178
03179   return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
03180 }
03181
03182 /**
03183   * @}
03184   */
03185
03186 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
03187   * @{
03188   */
03189
03190 #if defined(ADC_MULTIMODE_SUPPORT)
03191 /**
03192   * @brief  Set ADC multimode configuration to operate in independent mode
03193   *         or multimode (for devices with several ADC instances).
03194   * @note   If multimode configuration: the selected ADC instance is
03195   *         either master or slave depending on hardware.
03196   *         Refer to reference manual.
03197   * @rmtoll CR1      DUALMOD        LL_ADC_SetMultimode
03198   * @param  ADCxy_COMMON ADC common instance
03199   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03200   * @param  Multimode This parameter can be one of the following values:
03201   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
03202   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
03203   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
03204   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
03205   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
03206   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
03207   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
03208   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
03209   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
03210   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
03211   * @retval None
03212   */
03213 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
03214 {
03215   MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode);
03216 }
03217
03218 /**
03219   * @brief  Get ADC multimode configuration to operate in independent mode
03220   *         or multimode (for devices with several ADC instances).
03221   * @note   If multimode configuration: the selected ADC instance is
03222   *         either master or slave depending on hardware.
03223   *         Refer to reference manual.
03224   * @rmtoll CR1      DUALMOD        LL_ADC_GetMultimode
03225   * @param  ADCxy_COMMON ADC common instance
03226   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03227   * @retval Returned value can be one of the following values:
03228   *         @arg @ref LL_ADC_MULTI_INDEPENDENT
03229   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
03230   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
03231   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
03232   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
03233   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
03234   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
03235   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
03236   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
03237   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
03238   */
03239 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
03240 {
03241   return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD));
03242 }
03243
03244 #endif /* ADC_MULTIMODE_SUPPORT */
03245
03246 /**
03247   * @}
03248   */
03249 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
03250   * @{
03251   */
03252
03253 /**
03254   * @brief  Enable the selected ADC instance.
03255   * @note   On this STM32 serie, after ADC enable, a delay for
03256   *         ADC internal analog stabilization is required before performing a
03257   *         ADC conversion start.
03258   *         Refer to device datasheet, parameter tSTAB.
03259   * @rmtoll CR2      ADON           LL_ADC_Enable
03260   * @param  ADCx ADC instance
03261   * @retval None
03262   */
03263 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
03264 {
03265   SET_BIT(ADCx->CR2, ADC_CR2_ADON);
03266 }
03267
03268 /**
03269   * @brief  Disable the selected ADC instance.
03270   * @rmtoll CR2      ADON           LL_ADC_Disable
03271   * @param  ADCx ADC instance
03272   * @retval None
03273   */
03274 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
03275 {
03276   CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
03277 }
03278
03279 /**
03280   * @brief  Get the selected ADC instance enable state.
03281   * @rmtoll CR2      ADON           LL_ADC_IsEnabled
03282   * @param  ADCx ADC instance
03283   * @retval 0: ADC is disabled, 1: ADC is enabled.
03284   */
03285 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
03286 {
03287   return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
03288 }
03289
03290 /**
03291   * @brief  Start ADC calibration in the mode single-ended
03292   *         or differential (for devices with differential mode available).
03293   * @note   On this STM32 serie, before starting a calibration,
03294   *         ADC must be disabled.
03295   *         A minimum number of ADC clock cycles are required
03296   *         between ADC disable state and calibration start.
03297   *         Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
03298   * @note   On this STM32 serie, hardware prerequisite before starting a calibration:
03299             the ADC must have been in power-on state for at least
03300             two ADC clock cycles.
03301   * @rmtoll CR2      CAL            LL_ADC_StartCalibration
03302   * @param  ADCx ADC instance
03303   * @retval None
03304   */
03305 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
03306 {
03307   SET_BIT(ADCx->CR2, ADC_CR2_CAL);
03308 }
03309
03310 /**
03311   * @brief  Get ADC calibration state.
03312   * @rmtoll CR2      CAL            LL_ADC_IsCalibrationOnGoing
03313   * @param  ADCx ADC instance
03314   * @retval 0: calibration complete, 1: calibration in progress.
03315   */
03316 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
03317 {
03318   return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL));
03319 }
03320
03321 /**
03322   * @}
03323   */
03324
03325 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
03326   * @{
03327   */
03328
03329 /**
03330   * @brief  Start ADC group regular conversion.
03331   * @note   On this STM32 serie, this function is relevant only for
03332   *         internal trigger (SW start), not for external trigger:
03333   *         - If ADC trigger has been set to software start, ADC conversion
03334   *           starts immediately.
03335   *         - If ADC trigger has been set to external trigger, ADC conversion
03336   *           start must be performed using function
03337   *           @ref LL_ADC_REG_StartConversionExtTrig().
03338   *           (if external trigger edge would have been set during ADC other
03339   *           settings, ADC conversion would start at trigger event
03340   *           as soon as ADC is enabled).
03341   * @rmtoll CR2      SWSTART        LL_ADC_REG_StartConversionSWStart
03342   * @param  ADCx ADC instance
03343   * @retval None
03344   */
03345 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
03346 {
03347   SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
03348 }
03349
03350 /**
03351   * @brief  Start ADC group regular conversion from external trigger.
03352   * @note   ADC conversion will start at next trigger event (on the selected
03353   *         trigger edge) following the ADC start conversion command.
03354   * @note   On this STM32 serie, this function is relevant for
03355   *         ADC conversion start from external trigger.
03356   *         If internal trigger (SW start) is needed, perform ADC conversion
03357   *         start using function @ref LL_ADC_REG_StartConversionSWStart().
03358   * @rmtoll CR2      EXTEN          LL_ADC_REG_StartConversionExtTrig
03359   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03360   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
03361   * @param  ADCx ADC instance
03362   * @retval None
03363   */
03364 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
03365 {
03366   SET_BIT(ADCx->CR2, ExternalTriggerEdge);
03367 }
03368
03369 /**
03370   * @brief  Stop ADC group regular conversion from external trigger.
03371   * @note   No more ADC conversion will start at next trigger event
03372   *         following the ADC stop conversion command.
03373   *         If a conversion is on-going, it will be completed.
03374   * @note   On this STM32 serie, there is no specific command
03375   *         to stop a conversion on-going or to stop ADC converting
03376   *         in continuous mode. These actions can be performed
03377   *         using function @ref LL_ADC_Disable().
03378   * @rmtoll CR2      EXTSEL         LL_ADC_REG_StopConversionExtTrig
03379   * @param  ADCx ADC instance
03380   * @retval None
03381   */
03382 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
03383 {
03384   CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTSEL);
03385 }
03386
03387 /**
03388   * @brief  Get ADC group regular conversion data, range fit for
03389   *         all ADC configurations: all ADC resolutions and
03390   *         all oversampling increased data width (for devices
03391   *         with feature oversampling).
03392   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
03393   * @param  ADCx ADC instance
03394   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
03395   */
03396 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
03397 {
03398   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
03399 }
03400
03401 /**
03402   * @brief  Get ADC group regular conversion data, range fit for
03403   *         ADC resolution 12 bits.
03404   * @note   For devices with feature oversampling: Oversampling
03405   *         can increase data width, function for extended range
03406   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
03407   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
03408   * @param  ADCx ADC instance
03409   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
03410   */
03411 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
03412 {
03413   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
03414 }
03415
03416 #if defined(ADC_MULTIMODE_SUPPORT)
03417 /**
03418   * @brief  Get ADC multimode conversion data of ADC master, ADC slave
03419   *         or raw data with ADC master and slave concatenated.
03420   * @note   If raw data with ADC master and slave concatenated is retrieved,
03421   *         a macro is available to get the conversion data of
03422   *         ADC master or ADC slave: see helper macro
03423   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
03424   *         (however this macro is mainly intended for multimode
03425   *         transfer by DMA, because this function can do the same
03426   *         by getting multimode conversion data of ADC master or ADC slave
03427   *         separately).
03428   * @rmtoll DR       DATA           LL_ADC_REG_ReadMultiConversionData32\n
03429   *         DR       ADC2DATA       LL_ADC_REG_ReadMultiConversionData32
03430   * @param  ADCx ADC instance
03431   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03432   * @param  ConversionData This parameter can be one of the following values:
03433   *         @arg @ref LL_ADC_MULTI_MASTER
03434   *         @arg @ref LL_ADC_MULTI_SLAVE
03435   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
03436   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
03437   */
03438 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData)
03439 {
03440   return (uint32_t)(READ_BIT(ADCx->DR,
03441                              ADC_DR_ADC2DATA)
03442                     >> POSITION_VAL(ConversionData)
03443                    );
03444 }
03445 #endif /* ADC_MULTIMODE_SUPPORT */
03446
03447 /**
03448   * @}
03449   */
03450
03451 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
03452   * @{
03453   */
03454
03455 /**
03456   * @brief  Start ADC group injected conversion.
03457   * @note   On this STM32 serie, this function is relevant only for
03458   *         internal trigger (SW start), not for external trigger:
03459   *         - If ADC trigger has been set to software start, ADC conversion
03460   *           starts immediately.
03461   *         - If ADC trigger has been set to external trigger, ADC conversion
03462   *           start must be performed using function
03463   *           @ref LL_ADC_INJ_StartConversionExtTrig().
03464   *           (if external trigger edge would have been set during ADC other
03465   *           settings, ADC conversion would start at trigger event
03466   *           as soon as ADC is enabled).
03467   * @rmtoll CR2      JSWSTART       LL_ADC_INJ_StartConversionSWStart
03468   * @param  ADCx ADC instance
03469   * @retval None
03470   */
03471 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
03472 {
03473   SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
03474 }
03475
03476 /**
03477   * @brief  Start ADC group injected conversion from external trigger.
03478   * @note   ADC conversion will start at next trigger event (on the selected
03479   *         trigger edge) following the ADC start conversion command.
03480   * @note   On this STM32 serie, this function is relevant for
03481   *         ADC conversion start from external trigger.
03482   *         If internal trigger (SW start) is needed, perform ADC conversion
03483   *         start using function @ref LL_ADC_INJ_StartConversionSWStart().
03484   * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StartConversionExtTrig
03485   * @param  ExternalTriggerEdge This parameter can be one of the following values:
03486   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
03487   * @param  ADCx ADC instance
03488   * @retval None
03489   */
03490 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
03491 {
03492   SET_BIT(ADCx->CR2, ExternalTriggerEdge);
03493 }
03494
03495 /**
03496   * @brief  Stop ADC group injected conversion from external trigger.
03497   * @note   No more ADC conversion will start at next trigger event
03498   *         following the ADC stop conversion command.
03499   *         If a conversion is on-going, it will be completed.
03500   * @note   On this STM32 serie, there is no specific command
03501   *         to stop a conversion on-going or to stop ADC converting
03502   *         in continuous mode. These actions can be performed
03503   *         using function @ref LL_ADC_Disable().
03504   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_StopConversionExtTrig
03505   * @param  ADCx ADC instance
03506   * @retval None
03507   */
03508 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
03509 {
03510   CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTSEL);
03511 }
03512
03513 /**
03514   * @brief  Get ADC group regular conversion data, range fit for
03515   *         all ADC configurations: all ADC resolutions and
03516   *         all oversampling increased data width (for devices
03517   *         with feature oversampling).
03518   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
03519   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
03520   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
03521   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
03522   * @param  ADCx ADC instance
03523   * @param  Rank This parameter can be one of the following values:
03524   *         @arg @ref LL_ADC_INJ_RANK_1
03525   *         @arg @ref LL_ADC_INJ_RANK_2
03526   *         @arg @ref LL_ADC_INJ_RANK_3
03527   *         @arg @ref LL_ADC_INJ_RANK_4
03528   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
03529   */
03530 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
03531 {
03532   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
03533
03534   return (uint32_t)(READ_BIT(*preg,
03535                              ADC_JDR1_JDATA)
03536                    );
03537 }
03538
03539 /**
03540   * @brief  Get ADC group injected conversion data, range fit for
03541   *         ADC resolution 12 bits.
03542   * @note   For devices with feature oversampling: Oversampling
03543   *         can increase data width, function for extended range
03544   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
03545   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
03546   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
03547   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
03548   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
03549   * @param  ADCx ADC instance
03550   * @param  Rank This parameter can be one of the following values:
03551   *         @arg @ref LL_ADC_INJ_RANK_1
03552   *         @arg @ref LL_ADC_INJ_RANK_2
03553   *         @arg @ref LL_ADC_INJ_RANK_3
03554   *         @arg @ref LL_ADC_INJ_RANK_4
03555   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
03556   */
03557 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
03558 {
03559   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
03560
03561   return (uint16_t)(READ_BIT(*preg,
03562                              ADC_JDR1_JDATA)
03563                    );
03564 }
03565
03566 /**
03567   * @}
03568   */
03569
03570 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
03571   * @{
03572   */
03573
03574 /**
03575   * @brief  Get flag ADC group regular end of sequence conversions.
03576   * @rmtoll SR       EOC            LL_ADC_IsActiveFlag_EOS
03577   * @param  ADCx ADC instance
03578   * @retval State of bit (1 or 0).
03579   */
03580 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
03581 {
03582   /* Note: on this STM32 serie, there is no flag ADC group regular           */
03583   /*       end of unitary conversion.                                         */
03584   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
03585   /*       in other STM32 families).                                          */
03586   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
03587 }
03588
03589
03590 /**
03591   * @brief  Get flag ADC group injected end of sequence conversions.
03592   * @rmtoll SR       JEOC           LL_ADC_IsActiveFlag_JEOS
03593   * @param  ADCx ADC instance
03594   * @retval State of bit (1 or 0).
03595   */
03596 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
03597 {
03598   /* Note: on this STM32 serie, there is no flag ADC group injected          */
03599   /*       end of unitary conversion.                                         */
03600   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
03601   /*       in other STM32 families).                                          */
03602   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
03603 }
03604
03605 /**
03606   * @brief  Get flag ADC analog watchdog 1 flag
03607   * @rmtoll SR       AWD            LL_ADC_IsActiveFlag_AWD1
03608   * @param  ADCx ADC instance
03609   * @retval State of bit (1 or 0).
03610   */
03611 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
03612 {
03613   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
03614 }
03615
03616 /**
03617   * @brief  Clear flag ADC group regular end of sequence conversions.
03618   * @rmtoll SR       EOC            LL_ADC_ClearFlag_EOS
03619   * @param  ADCx ADC instance
03620   * @retval None
03621   */
03622 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
03623 {
03624   /* Note: on this STM32 serie, there is no flag ADC group regular           */
03625   /*       end of unitary conversion.                                         */
03626   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
03627   /*       in other STM32 families).                                          */
03628   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS);
03629 }
03630
03631
03632 /**
03633   * @brief  Clear flag ADC group injected end of sequence conversions.
03634   * @rmtoll SR       JEOC           LL_ADC_ClearFlag_JEOS
03635   * @param  ADCx ADC instance
03636   * @retval None
03637   */
03638 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
03639 {
03640   /* Note: on this STM32 serie, there is no flag ADC group injected          */
03641   /*       end of unitary conversion.                                         */
03642   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
03643   /*       in other STM32 families).                                          */
03644   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
03645 }
03646
03647 /**
03648   * @brief  Clear flag ADC analog watchdog 1.
03649   * @rmtoll SR       AWD            LL_ADC_ClearFlag_AWD1
03650   * @param  ADCx ADC instance
03651   * @retval None
03652   */
03653 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
03654 {
03655   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
03656 }
03657
03658 #if defined(ADC_MULTIMODE_SUPPORT)
03659 /**
03660   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
03661   * @rmtoll SR       EOC            LL_ADC_IsActiveFlag_MST_EOS
03662   * @param  ADCxy_COMMON ADC common instance
03663   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03664   * @retval State of bit (1 or 0).
03665   */
03666 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
03667 {
03668   /* Note: on this STM32 serie, there is no flag ADC group regular           */
03669   /*       end of unitary conversion.                                         */
03670   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
03671   /*       in other STM32 families).                                          */
03672   return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC));
03673 }
03674
03675 /**
03676   * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
03677   * @rmtoll SR       EOC            LL_ADC_IsActiveFlag_SLV_EOS
03678   * @param  ADCxy_COMMON ADC common instance
03679   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03680   * @retval State of bit (1 or 0).
03681   */
03682 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
03683 {
03684   /* Note: on this STM32 serie, there is no flag ADC group regular           */
03685   /*       end of unitary conversion.                                         */
03686   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
03687   /*       in other STM32 families).                                          */
03688
03689   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
03690
03691   return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
03692 }
03693
03694
03695 /**
03696   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
03697   * @rmtoll SR       JEOC           LL_ADC_IsActiveFlag_MST_JEOS
03698   * @param  ADCxy_COMMON ADC common instance
03699   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03700   * @retval State of bit (1 or 0).
03701   */
03702 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
03703 {
03704   /* Note: on this STM32 serie, there is no flag ADC group injected          */
03705   /*       end of unitary conversion.                                         */
03706   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
03707   /*       in other STM32 families).                                          */
03708   return (READ_BIT(ADC1->SR, ADC_SR_JEOC) == (ADC_SR_JEOC));
03709 }
03710
03711 /**
03712   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
03713   * @rmtoll SR       JEOC           LL_ADC_IsActiveFlag_SLV_JEOS
03714   * @param  ADCxy_COMMON ADC common instance
03715   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03716   * @retval State of bit (1 or 0).
03717   */
03718 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
03719 {
03720   /* Note: on this STM32 serie, there is no flag ADC group injected          */
03721   /*       end of unitary conversion.                                         */
03722   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
03723   /*       in other STM32 families).                                          */
03724
03725   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
03726
03727   return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
03728 }
03729
03730 /**
03731   * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
03732   * @rmtoll SR       AWD            LL_ADC_IsActiveFlag_MST_AWD1
03733   * @param  ADCxy_COMMON ADC common instance
03734   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03735   * @retval State of bit (1 or 0).
03736   */
03737 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
03738 {
03739   return (READ_BIT(ADC1->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
03740 }
03741
03742 /**
03743   * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
03744   * @rmtoll SR       AWD            LL_ADC_IsActiveFlag_SLV_AWD1
03745   * @param  ADCxy_COMMON ADC common instance
03746   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
03747   * @retval State of bit (1 or 0).
03748   */
03749 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
03750 {
03751   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
03752
03753   return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
03754 }
03755
03756 #endif /* ADC_MULTIMODE_SUPPORT */
03757
03758 /**
03759   * @}
03760   */
03761
03762 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
03763   * @{
03764   */
03765
03766 /**
03767   * @brief  Enable interruption ADC group regular end of sequence conversions.
03768   * @rmtoll CR1      EOCIE          LL_ADC_EnableIT_EOS
03769   * @param  ADCx ADC instance
03770   * @retval None
03771   */
03772 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
03773 {
03774   /* Note: on this STM32 serie, there is no flag ADC group regular           */
03775   /*       end of unitary conversion.                                         */
03776   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
03777   /*       in other STM32 families).                                          */
03778   SET_BIT(ADCx->CR1, ADC_CR1_EOCIE);
03779 }
03780
03781
03782 /**
03783   * @brief  Enable interruption ADC group injected end of sequence conversions.
03784   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
03785   * @param  ADCx ADC instance
03786   * @retval None
03787   */
03788 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
03789 {
03790   /* Note: on this STM32 serie, there is no flag ADC group injected          */
03791   /*       end of unitary conversion.                                         */
03792   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
03793   /*       in other STM32 families).                                          */
03794   SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
03795 }
03796
03797 /**
03798   * @brief  Enable interruption ADC analog watchdog 1.
03799   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
03800   * @param  ADCx ADC instance
03801   * @retval None
03802   */
03803 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
03804 {
03805   SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
03806 }
03807
03808 /**
03809   * @brief  Disable interruption ADC group regular end of sequence conversions.
03810   * @rmtoll CR1      EOCIE          LL_ADC_DisableIT_EOS
03811   * @param  ADCx ADC instance
03812   * @retval None
03813   */
03814 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
03815 {
03816   /* Note: on this STM32 serie, there is no flag ADC group regular           */
03817   /*       end of unitary conversion.                                         */
03818   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
03819   /*       in other STM32 families).                                          */
03820   CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE);
03821 }
03822
03823
03824 /**
03825   * @brief  Disable interruption ADC group injected end of sequence conversions.
03826   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
03827   * @param  ADCx ADC instance
03828   * @retval None
03829   */
03830 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
03831 {
03832   /* Note: on this STM32 serie, there is no flag ADC group injected          */
03833   /*       end of unitary conversion.                                         */
03834   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
03835   /*       in other STM32 families).                                          */
03836   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
03837 }
03838
03839 /**
03840   * @brief  Disable interruption ADC analog watchdog 1.
03841   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
03842   * @param  ADCx ADC instance
03843   * @retval None
03844   */
03845 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
03846 {
03847   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
03848 }
03849
03850 /**
03851   * @brief  Get state of interruption ADC group regular end of sequence conversions
03852   *         (0: interrupt disabled, 1: interrupt enabled).
03853   * @rmtoll CR1      EOCIE          LL_ADC_IsEnabledIT_EOS
03854   * @param  ADCx ADC instance
03855   * @retval State of bit (1 or 0).
03856   */
03857 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
03858 {
03859   /* Note: on this STM32 serie, there is no flag ADC group regular           */
03860   /*       end of unitary conversion.                                         */
03861   /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
03862   /*       in other STM32 families).                                          */
03863   return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
03864 }
03865
03866
03867 /**
03868   * @brief  Get state of interruption ADC group injected end of sequence conversions
03869   *         (0: interrupt disabled, 1: interrupt enabled).
03870   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS
03871   * @param  ADCx ADC instance
03872   * @retval State of bit (1 or 0).
03873   */
03874 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
03875 {
03876   /* Note: on this STM32 serie, there is no flag ADC group injected          */
03877   /*       end of unitary conversion.                                         */
03878   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
03879   /*       in other STM32 families).                                          */
03880   return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
03881 }
03882
03883 /**
03884   * @brief  Get state of interruption ADC analog watchdog 1
03885   *         (0: interrupt disabled, 1: interrupt enabled).
03886   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1
03887   * @param  ADCx ADC instance
03888   * @retval State of bit (1 or 0).
03889   */
03890 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
03891 {
03892   return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
03893 }
03894
03895 /**
03896   * @}
03897   */
03898
03899 #if defined(USE_FULL_LL_DRIVER)
03900 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
03901   * @{
03902   */
03903
03904 /* Initialization of some features of ADC common parameters and multimode */
03905 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
03906 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
03907 void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
03908
03909 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
03910 /* (availability of ADC group injected depends on STM32 families) */
03911 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
03912
03913 /* Initialization of some features of ADC instance */
03914 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
03915 void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
03916
03917 /* Initialization of some features of ADC instance and ADC group regular */
03918 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
03919 void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
03920
03921 /* Initialization of some features of ADC instance and ADC group injected */
03922 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
03923 void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
03924
03925 /**
03926   * @}
03927   */
03928 #endif /* USE_FULL_LL_DRIVER */
03929
03930 /**
03931   * @}
03932   */
03933
03934 /**
03935   * @}
03936   */
03937
03938 #endif /* ADC1 || ADC2 || ADC3 */
03939
03940 /**
03941   * @}
03942   */
03943
03944 #ifdef __cplusplus
03945 }
03946 #endif
03947
03948 #endif /* __STM32F1xx_LL_ADC_H */
03949
03950 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_bus.h Source File

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stm32f1xx_ll_bus.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_bus.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of BUS LL module.
00008
00009   @verbatim
00010                       ##### RCC Limitations #####
00011   ==============================================================================
00012     [..]
00013       A delay between an RCC peripheral clock enable and the effective peripheral
00014       enabling should be taken into account in order to manage the peripheral read/write
00015       from/to registers.
00016       (+) This delay depends on the peripheral mapping.
00017         (++) AHB & APB peripherals, 1 dummy read is necessary
00018
00019     [..]
00020       Workarounds:
00021       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
00022           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
00023
00024   @endverbatim
00025   ******************************************************************************
00026   * @attention
00027   *
00028   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00029   *
00030   * Redistribution and use in source and binary forms, with or without modification,
00031   * are permitted provided that the following conditions are met:
00032   *   1. Redistributions of source code must retain the above copyright notice,
00033   *      this list of conditions and the following disclaimer.
00034   *   2. Redistributions in binary form must reproduce the above copyright notice,
00035   *      this list of conditions and the following disclaimer in the documentation
00036   *      and/or other materials provided with the distribution.
00037   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00038   *      may be used to endorse or promote products derived from this software
00039   *      without specific prior written permission.
00040   *
00041   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00042   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00043   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00044   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00045   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00046   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00047   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00048   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00049   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00050   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00051   *
00052   ******************************************************************************
00053   */
00054
00055 /* Define to prevent recursive inclusion -------------------------------------*/
00056 #ifndef __STM32F1xx_LL_BUS_H
00057 #define __STM32F1xx_LL_BUS_H
00058
00059 #ifdef __cplusplus
00060 extern "C" {
00061 #endif
00062
00063 /* Includes ------------------------------------------------------------------*/
00064 #include "stm32f1xx.h"
00065
00066 /** @addtogroup STM32F1xx_LL_Driver
00067   * @{
00068   */
00069
00070 #if defined(RCC)
00071
00072 /** @defgroup BUS_LL BUS
00073   * @{
00074   */
00075
00076 /* Private types -------------------------------------------------------------*/
00077 /* Private variables ---------------------------------------------------------*/
00078
00079 /* Private constants ---------------------------------------------------------*/
00080 #if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
00081 #define RCC_AHBRSTR_SUPPORT
00082 #endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
00083
00084 /* Private macros ------------------------------------------------------------*/
00085
00086 /* Exported types ------------------------------------------------------------*/
00087 /* Exported constants --------------------------------------------------------*/
00088 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
00089   * @{
00090   */
00091
00092 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
00093   * @{
00094   */
00095 #define LL_AHB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00096 #define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHBENR_CRCEN
00097 #define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHBENR_DMA1EN
00098 #if defined(DMA2)
00099 #define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHBENR_DMA2EN
00100 #endif /*DMA2*/
00101 #if defined(ETH)
00102 #define LL_AHB1_GRP1_PERIPH_ETHMAC         RCC_AHBENR_ETHMACEN
00103 #define LL_AHB1_GRP1_PERIPH_ETHMACRX       RCC_AHBENR_ETHMACRXEN
00104 #define LL_AHB1_GRP1_PERIPH_ETHMACTX       RCC_AHBENR_ETHMACTXEN
00105 #endif /*ETH*/
00106 #define LL_AHB1_GRP1_PERIPH_FLASH          RCC_AHBENR_FLITFEN
00107 #if defined(FSMC_Bank1)
00108 #define LL_AHB1_GRP1_PERIPH_FSMC           RCC_AHBENR_FSMCEN
00109 #endif /*FSMC_Bank1*/
00110 #if defined(USB_OTG_FS)
00111 #define LL_AHB1_GRP1_PERIPH_OTGFS          RCC_AHBENR_OTGFSEN
00112 #endif /*USB_OTG_FS*/
00113 #if defined(SDIO)
00114 #define LL_AHB1_GRP1_PERIPH_SDIO           RCC_AHBENR_SDIOEN
00115 #endif /*SDIO*/
00116 #define LL_AHB1_GRP1_PERIPH_SRAM           RCC_AHBENR_SRAMEN
00117 /**
00118   * @}
00119   */
00120
00121 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
00122   * @{
00123   */
00124 #define LL_APB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00125 #define LL_APB1_GRP1_PERIPH_BKP            RCC_APB1ENR_BKPEN
00126 #if defined(CAN1)
00127 #define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
00128 #endif /*CAN1*/
00129 #if defined(CAN2)
00130 #define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
00131 #endif /*CAN2*/
00132 #if defined(CEC)
00133 #define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
00134 #endif /*CEC*/
00135 #if defined(DAC)
00136 #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
00137 #endif /*DAC*/
00138 #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
00139 #if defined(I2C2)
00140 #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
00141 #endif /*I2C2*/
00142 #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
00143 #if defined(SPI2)
00144 #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
00145 #endif /*SPI2*/
00146 #if defined(SPI3)
00147 #define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
00148 #endif /*SPI3*/
00149 #if defined(TIM12)
00150 #define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
00151 #endif /*TIM12*/
00152 #if defined(TIM13)
00153 #define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
00154 #endif /*TIM13*/
00155 #if defined(TIM14)
00156 #define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
00157 #endif /*TIM14*/
00158 #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
00159 #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
00160 #if defined(TIM4)
00161 #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
00162 #endif /*TIM4*/
00163 #if defined(TIM5)
00164 #define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
00165 #endif /*TIM5*/
00166 #if defined(TIM6)
00167 #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
00168 #endif /*TIM6*/
00169 #if defined(TIM7)
00170 #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
00171 #endif /*TIM7*/
00172 #if defined(UART4)
00173 #define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
00174 #endif /*UART4*/
00175 #if defined(UART5)
00176 #define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
00177 #endif /*UART5*/
00178 #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
00179 #if defined(USART3)
00180 #define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
00181 #endif /*USART3*/
00182 #if defined(USB)
00183 #define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR_USBEN
00184 #endif /*USB*/
00185 #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
00186 /**
00187   * @}
00188   */
00189
00190 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
00191   * @{
00192   */
00193 #define LL_APB2_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
00194 #define LL_APB2_GRP1_PERIPH_ADC1           RCC_APB2ENR_ADC1EN
00195 #if defined(ADC2)
00196 #define LL_APB2_GRP1_PERIPH_ADC2           RCC_APB2ENR_ADC2EN
00197 #endif /*ADC2*/
00198 #if defined(ADC3)
00199 #define LL_APB2_GRP1_PERIPH_ADC3           RCC_APB2ENR_ADC3EN
00200 #endif /*ADC3*/
00201 #define LL_APB2_GRP1_PERIPH_AFIO           RCC_APB2ENR_AFIOEN
00202 #define LL_APB2_GRP1_PERIPH_GPIOA          RCC_APB2ENR_IOPAEN
00203 #define LL_APB2_GRP1_PERIPH_GPIOB          RCC_APB2ENR_IOPBEN
00204 #define LL_APB2_GRP1_PERIPH_GPIOC          RCC_APB2ENR_IOPCEN
00205 #define LL_APB2_GRP1_PERIPH_GPIOD          RCC_APB2ENR_IOPDEN
00206 #if defined(GPIOE)
00207 #define LL_APB2_GRP1_PERIPH_GPIOE          RCC_APB2ENR_IOPEEN
00208 #endif /*GPIOE*/
00209 #if defined(GPIOF)
00210 #define LL_APB2_GRP1_PERIPH_GPIOF          RCC_APB2ENR_IOPFEN
00211 #endif /*GPIOF*/
00212 #if defined(GPIOG)
00213 #define LL_APB2_GRP1_PERIPH_GPIOG          RCC_APB2ENR_IOPGEN
00214 #endif /*GPIOG*/
00215 #define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN
00216 #if defined(TIM10)
00217 #define LL_APB2_GRP1_PERIPH_TIM10          RCC_APB2ENR_TIM10EN
00218 #endif /*TIM10*/
00219 #if defined(TIM11)
00220 #define LL_APB2_GRP1_PERIPH_TIM11          RCC_APB2ENR_TIM11EN
00221 #endif /*TIM11*/
00222 #if defined(TIM15)
00223 #define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN
00224 #endif /*TIM15*/
00225 #if defined(TIM16)
00226 #define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN
00227 #endif /*TIM16*/
00228 #if defined(TIM17)
00229 #define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN
00230 #endif /*TIM17*/
00231 #define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN
00232 #if defined(TIM8)
00233 #define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN
00234 #endif /*TIM8*/
00235 #if defined(TIM9)
00236 #define LL_APB2_GRP1_PERIPH_TIM9           RCC_APB2ENR_TIM9EN
00237 #endif /*TIM9*/
00238 #define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN
00239 /**
00240   * @}
00241   */
00242
00243 /**
00244   * @}
00245   */
00246
00247 /* Exported macro ------------------------------------------------------------*/
00248
00249 /* Exported functions --------------------------------------------------------*/
00250 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
00251   * @{
00252   */
00253
00254 /** @defgroup BUS_LL_EF_AHB1 AHB1
00255   * @{
00256   */
00257
00258 /**
00259   * @brief  Enable AHB1 peripherals clock.
00260   * @rmtoll AHBENR       CRCEN         LL_AHB1_GRP1_EnableClock\n
00261   *         AHBENR       DMA1EN        LL_AHB1_GRP1_EnableClock\n
00262   *         AHBENR       DMA2EN        LL_AHB1_GRP1_EnableClock\n
00263   *         AHBENR       ETHMACEN      LL_AHB1_GRP1_EnableClock\n
00264   *         AHBENR       ETHMACRXEN    LL_AHB1_GRP1_EnableClock\n
00265   *         AHBENR       ETHMACTXEN    LL_AHB1_GRP1_EnableClock\n
00266   *         AHBENR       FLITFEN       LL_AHB1_GRP1_EnableClock\n
00267   *         AHBENR       FSMCEN        LL_AHB1_GRP1_EnableClock\n
00268   *         AHBENR       OTGFSEN       LL_AHB1_GRP1_EnableClock\n
00269   *         AHBENR       SDIOEN        LL_AHB1_GRP1_EnableClock\n
00270   *         AHBENR       SRAMEN        LL_AHB1_GRP1_EnableClock
00271   * @param  Periphs This parameter can be a combination of the following values:
00272   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00273   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00274   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
00275   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
00276   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
00277   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
00278   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00279   *         @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
00280   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
00281   *         @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
00282   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
00283   *
00284   *         (*) value not defined in all devices.
00285   * @retval None
00286 */
00287 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
00288 {
00289   __IO uint32_t tmpreg;
00290   SET_BIT(RCC->AHBENR, Periphs);
00291   /* Delay after an RCC peripheral clock enabling */
00292   tmpreg = READ_BIT(RCC->AHBENR, Periphs);
00293   (void)tmpreg;
00294 }
00295
00296 /**
00297   * @brief  Check if AHB1 peripheral clock is enabled or not
00298   * @rmtoll AHBENR       CRCEN         LL_AHB1_GRP1_IsEnabledClock\n
00299   *         AHBENR       DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n
00300   *         AHBENR       DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n
00301   *         AHBENR       ETHMACEN      LL_AHB1_GRP1_IsEnabledClock\n
00302   *         AHBENR       ETHMACRXEN    LL_AHB1_GRP1_IsEnabledClock\n
00303   *         AHBENR       ETHMACTXEN    LL_AHB1_GRP1_IsEnabledClock\n
00304   *         AHBENR       FLITFEN       LL_AHB1_GRP1_IsEnabledClock\n
00305   *         AHBENR       FSMCEN        LL_AHB1_GRP1_IsEnabledClock\n
00306   *         AHBENR       OTGFSEN       LL_AHB1_GRP1_IsEnabledClock\n
00307   *         AHBENR       SDIOEN        LL_AHB1_GRP1_IsEnabledClock\n
00308   *         AHBENR       SRAMEN        LL_AHB1_GRP1_IsEnabledClock
00309   * @param  Periphs This parameter can be a combination of the following values:
00310   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00311   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00312   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
00313   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
00314   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
00315   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
00316   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00317   *         @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
00318   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
00319   *         @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
00320   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
00321   *
00322   *         (*) value not defined in all devices.
00323   * @retval State of Periphs (1 or 0).
00324 */
00325 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
00326 {
00327   return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
00328 }
00329
00330 /**
00331   * @brief  Disable AHB1 peripherals clock.
00332   * @rmtoll AHBENR       CRCEN         LL_AHB1_GRP1_DisableClock\n
00333   *         AHBENR       DMA1EN        LL_AHB1_GRP1_DisableClock\n
00334   *         AHBENR       DMA2EN        LL_AHB1_GRP1_DisableClock\n
00335   *         AHBENR       ETHMACEN      LL_AHB1_GRP1_DisableClock\n
00336   *         AHBENR       ETHMACRXEN    LL_AHB1_GRP1_DisableClock\n
00337   *         AHBENR       ETHMACTXEN    LL_AHB1_GRP1_DisableClock\n
00338   *         AHBENR       FLITFEN       LL_AHB1_GRP1_DisableClock\n
00339   *         AHBENR       FSMCEN        LL_AHB1_GRP1_DisableClock\n
00340   *         AHBENR       OTGFSEN       LL_AHB1_GRP1_DisableClock\n
00341   *         AHBENR       SDIOEN        LL_AHB1_GRP1_DisableClock\n
00342   *         AHBENR       SRAMEN        LL_AHB1_GRP1_DisableClock
00343   * @param  Periphs This parameter can be a combination of the following values:
00344   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
00345   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
00346   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
00347   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
00348   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
00349   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
00350   *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
00351   *         @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
00352   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
00353   *         @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
00354   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
00355   *
00356   *         (*) value not defined in all devices.
00357   * @retval None
00358 */
00359 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
00360 {
00361   CLEAR_BIT(RCC->AHBENR, Periphs);
00362 }
00363
00364 #if defined(RCC_AHBRSTR_SUPPORT)
00365 /**
00366   * @brief  Force AHB1 peripherals reset.
00367   * @rmtoll AHBRSTR      ETHMACRST     LL_AHB1_GRP1_ForceReset\n
00368   *         AHBRSTR      OTGFSRST      LL_AHB1_GRP1_ForceReset
00369   * @param  Periphs This parameter can be a combination of the following values:
00370   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00371   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
00372   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
00373   *
00374   *         (*) value not defined in all devices.
00375   * @retval None
00376 */
00377 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
00378 {
00379   SET_BIT(RCC->AHBRSTR, Periphs);
00380 }
00381
00382 /**
00383   * @brief  Release AHB1 peripherals reset.
00384   * @rmtoll AHBRSTR      ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
00385   *         AHBRSTR      OTGFSRST      LL_AHB1_GRP1_ReleaseReset
00386   * @param  Periphs This parameter can be a combination of the following values:
00387   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
00388   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
00389   *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
00390   *
00391   *         (*) value not defined in all devices.
00392   * @retval None
00393 */
00394 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
00395 {
00396   CLEAR_BIT(RCC->AHBRSTR, Periphs);
00397 }
00398 #endif /* RCC_AHBRSTR_SUPPORT */
00399
00400 /**
00401   * @}
00402   */
00403
00404 /** @defgroup BUS_LL_EF_APB1 APB1
00405   * @{
00406   */
00407
00408 /**
00409   * @brief  Enable APB1 peripherals clock.
00410   * @rmtoll APB1ENR      BKPEN         LL_APB1_GRP1_EnableClock\n
00411   *         APB1ENR      CAN1EN        LL_APB1_GRP1_EnableClock\n
00412   *         APB1ENR      CAN2EN        LL_APB1_GRP1_EnableClock\n
00413   *         APB1ENR      CECEN         LL_APB1_GRP1_EnableClock\n
00414   *         APB1ENR      DACEN         LL_APB1_GRP1_EnableClock\n
00415   *         APB1ENR      I2C1EN        LL_APB1_GRP1_EnableClock\n
00416   *         APB1ENR      I2C2EN        LL_APB1_GRP1_EnableClock\n
00417   *         APB1ENR      PWREN         LL_APB1_GRP1_EnableClock\n
00418   *         APB1ENR      SPI2EN        LL_APB1_GRP1_EnableClock\n
00419   *         APB1ENR      SPI3EN        LL_APB1_GRP1_EnableClock\n
00420   *         APB1ENR      TIM12EN       LL_APB1_GRP1_EnableClock\n
00421   *         APB1ENR      TIM13EN       LL_APB1_GRP1_EnableClock\n
00422   *         APB1ENR      TIM14EN       LL_APB1_GRP1_EnableClock\n
00423   *         APB1ENR      TIM2EN        LL_APB1_GRP1_EnableClock\n
00424   *         APB1ENR      TIM3EN        LL_APB1_GRP1_EnableClock\n
00425   *         APB1ENR      TIM4EN        LL_APB1_GRP1_EnableClock\n
00426   *         APB1ENR      TIM5EN        LL_APB1_GRP1_EnableClock\n
00427   *         APB1ENR      TIM6EN        LL_APB1_GRP1_EnableClock\n
00428   *         APB1ENR      TIM7EN        LL_APB1_GRP1_EnableClock\n
00429   *         APB1ENR      UART4EN       LL_APB1_GRP1_EnableClock\n
00430   *         APB1ENR      UART5EN       LL_APB1_GRP1_EnableClock\n
00431   *         APB1ENR      USART2EN      LL_APB1_GRP1_EnableClock\n
00432   *         APB1ENR      USART3EN      LL_APB1_GRP1_EnableClock\n
00433   *         APB1ENR      USBEN         LL_APB1_GRP1_EnableClock\n
00434   *         APB1ENR      WWDGEN        LL_APB1_GRP1_EnableClock
00435   * @param  Periphs This parameter can be a combination of the following values:
00436   *         @arg @ref LL_APB1_GRP1_PERIPH_BKP
00437   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
00438   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
00439   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
00440   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
00441   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00442   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00443   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00444   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00445   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
00446   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
00447   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
00448   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
00449   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00450   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00451   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00452   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00453   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
00454   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
00455   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00456   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00457   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00458   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
00459   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00460   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00461   *
00462   *         (*) value not defined in all devices.
00463   * @retval None
00464 */
00465 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
00466 {
00467   __IO uint32_t tmpreg;
00468   SET_BIT(RCC->APB1ENR, Periphs);
00469   /* Delay after an RCC peripheral clock enabling */
00470   tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
00471   (void)tmpreg;
00472 }
00473
00474 /**
00475   * @brief  Check if APB1 peripheral clock is enabled or not
00476   * @rmtoll APB1ENR      BKPEN         LL_APB1_GRP1_IsEnabledClock\n
00477   *         APB1ENR      CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
00478   *         APB1ENR      CAN2EN        LL_APB1_GRP1_IsEnabledClock\n
00479   *         APB1ENR      CECEN         LL_APB1_GRP1_IsEnabledClock\n
00480   *         APB1ENR      DACEN         LL_APB1_GRP1_IsEnabledClock\n
00481   *         APB1ENR      I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
00482   *         APB1ENR      I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
00483   *         APB1ENR      PWREN         LL_APB1_GRP1_IsEnabledClock\n
00484   *         APB1ENR      SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
00485   *         APB1ENR      SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
00486   *         APB1ENR      TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
00487   *         APB1ENR      TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
00488   *         APB1ENR      TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
00489   *         APB1ENR      TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
00490   *         APB1ENR      TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
00491   *         APB1ENR      TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
00492   *         APB1ENR      TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
00493   *         APB1ENR      TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
00494   *         APB1ENR      TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
00495   *         APB1ENR      UART4EN       LL_APB1_GRP1_IsEnabledClock\n
00496   *         APB1ENR      UART5EN       LL_APB1_GRP1_IsEnabledClock\n
00497   *         APB1ENR      USART2EN      LL_APB1_GRP1_IsEnabledClock\n
00498   *         APB1ENR      USART3EN      LL_APB1_GRP1_IsEnabledClock\n
00499   *         APB1ENR      USBEN         LL_APB1_GRP1_IsEnabledClock\n
00500   *         APB1ENR      WWDGEN        LL_APB1_GRP1_IsEnabledClock
00501   * @param  Periphs This parameter can be a combination of the following values:
00502   *         @arg @ref LL_APB1_GRP1_PERIPH_BKP
00503   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
00504   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
00505   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
00506   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
00507   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00508   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00509   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00510   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00511   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
00512   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
00513   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
00514   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
00515   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00516   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00517   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00518   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00519   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
00520   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
00521   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00522   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00523   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00524   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
00525   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00526   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00527   *
00528   *         (*) value not defined in all devices.
00529   * @retval State of Periphs (1 or 0).
00530 */
00531 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
00532 {
00533   return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
00534 }
00535
00536 /**
00537   * @brief  Disable APB1 peripherals clock.
00538   * @rmtoll APB1ENR      BKPEN         LL_APB1_GRP1_DisableClock\n
00539   *         APB1ENR      CAN1EN        LL_APB1_GRP1_DisableClock\n
00540   *         APB1ENR      CAN2EN        LL_APB1_GRP1_DisableClock\n
00541   *         APB1ENR      CECEN         LL_APB1_GRP1_DisableClock\n
00542   *         APB1ENR      DACEN         LL_APB1_GRP1_DisableClock\n
00543   *         APB1ENR      I2C1EN        LL_APB1_GRP1_DisableClock\n
00544   *         APB1ENR      I2C2EN        LL_APB1_GRP1_DisableClock\n
00545   *         APB1ENR      PWREN         LL_APB1_GRP1_DisableClock\n
00546   *         APB1ENR      SPI2EN        LL_APB1_GRP1_DisableClock\n
00547   *         APB1ENR      SPI3EN        LL_APB1_GRP1_DisableClock\n
00548   *         APB1ENR      TIM12EN       LL_APB1_GRP1_DisableClock\n
00549   *         APB1ENR      TIM13EN       LL_APB1_GRP1_DisableClock\n
00550   *         APB1ENR      TIM14EN       LL_APB1_GRP1_DisableClock\n
00551   *         APB1ENR      TIM2EN        LL_APB1_GRP1_DisableClock\n
00552   *         APB1ENR      TIM3EN        LL_APB1_GRP1_DisableClock\n
00553   *         APB1ENR      TIM4EN        LL_APB1_GRP1_DisableClock\n
00554   *         APB1ENR      TIM5EN        LL_APB1_GRP1_DisableClock\n
00555   *         APB1ENR      TIM6EN        LL_APB1_GRP1_DisableClock\n
00556   *         APB1ENR      TIM7EN        LL_APB1_GRP1_DisableClock\n
00557   *         APB1ENR      UART4EN       LL_APB1_GRP1_DisableClock\n
00558   *         APB1ENR      UART5EN       LL_APB1_GRP1_DisableClock\n
00559   *         APB1ENR      USART2EN      LL_APB1_GRP1_DisableClock\n
00560   *         APB1ENR      USART3EN      LL_APB1_GRP1_DisableClock\n
00561   *         APB1ENR      USBEN         LL_APB1_GRP1_DisableClock\n
00562   *         APB1ENR      WWDGEN        LL_APB1_GRP1_DisableClock
00563   * @param  Periphs This parameter can be a combination of the following values:
00564   *         @arg @ref LL_APB1_GRP1_PERIPH_BKP
00565   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
00566   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
00567   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
00568   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
00569   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00570   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00571   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00572   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00573   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
00574   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
00575   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
00576   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
00577   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00578   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00579   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00580   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00581   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
00582   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
00583   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00584   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00585   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00586   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
00587   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00588   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00589   *
00590   *         (*) value not defined in all devices.
00591   * @retval None
00592 */
00593 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
00594 {
00595   CLEAR_BIT(RCC->APB1ENR, Periphs);
00596 }
00597
00598 /**
00599   * @brief  Force APB1 peripherals reset.
00600   * @rmtoll APB1RSTR     BKPRST        LL_APB1_GRP1_ForceReset\n
00601   *         APB1RSTR     CAN1RST       LL_APB1_GRP1_ForceReset\n
00602   *         APB1RSTR     CAN2RST       LL_APB1_GRP1_ForceReset\n
00603   *         APB1RSTR     CECRST        LL_APB1_GRP1_ForceReset\n
00604   *         APB1RSTR     DACRST        LL_APB1_GRP1_ForceReset\n
00605   *         APB1RSTR     I2C1RST       LL_APB1_GRP1_ForceReset\n
00606   *         APB1RSTR     I2C2RST       LL_APB1_GRP1_ForceReset\n
00607   *         APB1RSTR     PWRRST        LL_APB1_GRP1_ForceReset\n
00608   *         APB1RSTR     SPI2RST       LL_APB1_GRP1_ForceReset\n
00609   *         APB1RSTR     SPI3RST       LL_APB1_GRP1_ForceReset\n
00610   *         APB1RSTR     TIM12RST      LL_APB1_GRP1_ForceReset\n
00611   *         APB1RSTR     TIM13RST      LL_APB1_GRP1_ForceReset\n
00612   *         APB1RSTR     TIM14RST      LL_APB1_GRP1_ForceReset\n
00613   *         APB1RSTR     TIM2RST       LL_APB1_GRP1_ForceReset\n
00614   *         APB1RSTR     TIM3RST       LL_APB1_GRP1_ForceReset\n
00615   *         APB1RSTR     TIM4RST       LL_APB1_GRP1_ForceReset\n
00616   *         APB1RSTR     TIM5RST       LL_APB1_GRP1_ForceReset\n
00617   *         APB1RSTR     TIM6RST       LL_APB1_GRP1_ForceReset\n
00618   *         APB1RSTR     TIM7RST       LL_APB1_GRP1_ForceReset\n
00619   *         APB1RSTR     UART4RST      LL_APB1_GRP1_ForceReset\n
00620   *         APB1RSTR     UART5RST      LL_APB1_GRP1_ForceReset\n
00621   *         APB1RSTR     USART2RST     LL_APB1_GRP1_ForceReset\n
00622   *         APB1RSTR     USART3RST     LL_APB1_GRP1_ForceReset\n
00623   *         APB1RSTR     USBRST        LL_APB1_GRP1_ForceReset\n
00624   *         APB1RSTR     WWDGRST       LL_APB1_GRP1_ForceReset
00625   * @param  Periphs This parameter can be a combination of the following values:
00626   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
00627   *         @arg @ref LL_APB1_GRP1_PERIPH_BKP
00628   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
00629   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
00630   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
00631   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
00632   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00633   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00634   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00635   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00636   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
00637   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
00638   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
00639   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
00640   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00641   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00642   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00643   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00644   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
00645   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
00646   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00647   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00648   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00649   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
00650   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00651   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00652   *
00653   *         (*) value not defined in all devices.
00654   * @retval None
00655 */
00656 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
00657 {
00658   SET_BIT(RCC->APB1RSTR, Periphs);
00659 }
00660
00661 /**
00662   * @brief  Release APB1 peripherals reset.
00663   * @rmtoll APB1RSTR     BKPRST        LL_APB1_GRP1_ReleaseReset\n
00664   *         APB1RSTR     CAN1RST       LL_APB1_GRP1_ReleaseReset\n
00665   *         APB1RSTR     CAN2RST       LL_APB1_GRP1_ReleaseReset\n
00666   *         APB1RSTR     CECRST        LL_APB1_GRP1_ReleaseReset\n
00667   *         APB1RSTR     DACRST        LL_APB1_GRP1_ReleaseReset\n
00668   *         APB1RSTR     I2C1RST       LL_APB1_GRP1_ReleaseReset\n
00669   *         APB1RSTR     I2C2RST       LL_APB1_GRP1_ReleaseReset\n
00670   *         APB1RSTR     PWRRST        LL_APB1_GRP1_ReleaseReset\n
00671   *         APB1RSTR     SPI2RST       LL_APB1_GRP1_ReleaseReset\n
00672   *         APB1RSTR     SPI3RST       LL_APB1_GRP1_ReleaseReset\n
00673   *         APB1RSTR     TIM12RST      LL_APB1_GRP1_ReleaseReset\n
00674   *         APB1RSTR     TIM13RST      LL_APB1_GRP1_ReleaseReset\n
00675   *         APB1RSTR     TIM14RST      LL_APB1_GRP1_ReleaseReset\n
00676   *         APB1RSTR     TIM2RST       LL_APB1_GRP1_ReleaseReset\n
00677   *         APB1RSTR     TIM3RST       LL_APB1_GRP1_ReleaseReset\n
00678   *         APB1RSTR     TIM4RST       LL_APB1_GRP1_ReleaseReset\n
00679   *         APB1RSTR     TIM5RST       LL_APB1_GRP1_ReleaseReset\n
00680   *         APB1RSTR     TIM6RST       LL_APB1_GRP1_ReleaseReset\n
00681   *         APB1RSTR     TIM7RST       LL_APB1_GRP1_ReleaseReset\n
00682   *         APB1RSTR     UART4RST      LL_APB1_GRP1_ReleaseReset\n
00683   *         APB1RSTR     UART5RST      LL_APB1_GRP1_ReleaseReset\n
00684   *         APB1RSTR     USART2RST     LL_APB1_GRP1_ReleaseReset\n
00685   *         APB1RSTR     USART3RST     LL_APB1_GRP1_ReleaseReset\n
00686   *         APB1RSTR     USBRST        LL_APB1_GRP1_ReleaseReset\n
00687   *         APB1RSTR     WWDGRST       LL_APB1_GRP1_ReleaseReset
00688   * @param  Periphs This parameter can be a combination of the following values:
00689   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL
00690   *         @arg @ref LL_APB1_GRP1_PERIPH_BKP
00691   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
00692   *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
00693   *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
00694   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
00695   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
00696   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
00697   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
00698   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
00699   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
00700   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
00701   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
00702   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
00703   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2
00704   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3
00705   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
00706   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
00707   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
00708   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
00709   *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
00710   *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
00711   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
00712   *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
00713   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
00714   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
00715   *
00716   *         (*) value not defined in all devices.
00717   * @retval None
00718 */
00719 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
00720 {
00721   CLEAR_BIT(RCC->APB1RSTR, Periphs);
00722 }
00723
00724 /**
00725   * @}
00726   */
00727
00728 /** @defgroup BUS_LL_EF_APB2 APB2
00729   * @{
00730   */
00731
00732 /**
00733   * @brief  Enable APB2 peripherals clock.
00734   * @rmtoll APB2ENR      ADC1EN        LL_APB2_GRP1_EnableClock\n
00735   *         APB2ENR      ADC2EN        LL_APB2_GRP1_EnableClock\n
00736   *         APB2ENR      ADC3EN        LL_APB2_GRP1_EnableClock\n
00737   *         APB2ENR      AFIOEN        LL_APB2_GRP1_EnableClock\n
00738   *         APB2ENR      IOPAEN        LL_APB2_GRP1_EnableClock\n
00739   *         APB2ENR      IOPBEN        LL_APB2_GRP1_EnableClock\n
00740   *         APB2ENR      IOPCEN        LL_APB2_GRP1_EnableClock\n
00741   *         APB2ENR      IOPDEN        LL_APB2_GRP1_EnableClock\n
00742   *         APB2ENR      IOPEEN        LL_APB2_GRP1_EnableClock\n
00743   *         APB2ENR      IOPFEN        LL_APB2_GRP1_EnableClock\n
00744   *         APB2ENR      IOPGEN        LL_APB2_GRP1_EnableClock\n
00745   *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n
00746   *         APB2ENR      TIM10EN       LL_APB2_GRP1_EnableClock\n
00747   *         APB2ENR      TIM11EN       LL_APB2_GRP1_EnableClock\n
00748   *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n
00749   *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n
00750   *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n
00751   *         APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n
00752   *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n
00753   *         APB2ENR      TIM9EN        LL_APB2_GRP1_EnableClock\n
00754   *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock
00755   * @param  Periphs This parameter can be a combination of the following values:
00756   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
00757   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
00758   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
00759   *         @arg @ref LL_APB2_GRP1_PERIPH_AFIO
00760   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
00761   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
00762   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
00763   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
00764   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
00765   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
00766   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
00767   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
00768   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
00769   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
00770   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
00771   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
00772   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
00773   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
00774   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
00775   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
00776   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00777   *
00778   *         (*) value not defined in all devices.
00779   * @retval None
00780 */
00781 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
00782 {
00783   __IO uint32_t tmpreg;
00784   SET_BIT(RCC->APB2ENR, Periphs);
00785   /* Delay after an RCC peripheral clock enabling */
00786   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
00787   (void)tmpreg;
00788 }
00789
00790 /**
00791   * @brief  Check if APB2 peripheral clock is enabled or not
00792   * @rmtoll APB2ENR      ADC1EN        LL_APB2_GRP1_IsEnabledClock\n
00793   *         APB2ENR      ADC2EN        LL_APB2_GRP1_IsEnabledClock\n
00794   *         APB2ENR      ADC3EN        LL_APB2_GRP1_IsEnabledClock\n
00795   *         APB2ENR      AFIOEN        LL_APB2_GRP1_IsEnabledClock\n
00796   *         APB2ENR      IOPAEN        LL_APB2_GRP1_IsEnabledClock\n
00797   *         APB2ENR      IOPBEN        LL_APB2_GRP1_IsEnabledClock\n
00798   *         APB2ENR      IOPCEN        LL_APB2_GRP1_IsEnabledClock\n
00799   *         APB2ENR      IOPDEN        LL_APB2_GRP1_IsEnabledClock\n
00800   *         APB2ENR      IOPEEN        LL_APB2_GRP1_IsEnabledClock\n
00801   *         APB2ENR      IOPFEN        LL_APB2_GRP1_IsEnabledClock\n
00802   *         APB2ENR      IOPGEN        LL_APB2_GRP1_IsEnabledClock\n
00803   *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
00804   *         APB2ENR      TIM10EN       LL_APB2_GRP1_IsEnabledClock\n
00805   *         APB2ENR      TIM11EN       LL_APB2_GRP1_IsEnabledClock\n
00806   *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n
00807   *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n
00808   *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n
00809   *         APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
00810   *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
00811   *         APB2ENR      TIM9EN        LL_APB2_GRP1_IsEnabledClock\n
00812   *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock
00813   * @param  Periphs This parameter can be a combination of the following values:
00814   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
00815   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
00816   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
00817   *         @arg @ref LL_APB2_GRP1_PERIPH_AFIO
00818   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
00819   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
00820   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
00821   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
00822   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
00823   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
00824   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
00825   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
00826   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
00827   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
00828   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
00829   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
00830   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
00831   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
00832   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
00833   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
00834   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00835   *
00836   *         (*) value not defined in all devices.
00837   * @retval State of Periphs (1 or 0).
00838 */
00839 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
00840 {
00841   return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
00842 }
00843
00844 /**
00845   * @brief  Disable APB2 peripherals clock.
00846   * @rmtoll APB2ENR      ADC1EN        LL_APB2_GRP1_DisableClock\n
00847   *         APB2ENR      ADC2EN        LL_APB2_GRP1_DisableClock\n
00848   *         APB2ENR      ADC3EN        LL_APB2_GRP1_DisableClock\n
00849   *         APB2ENR      AFIOEN        LL_APB2_GRP1_DisableClock\n
00850   *         APB2ENR      IOPAEN        LL_APB2_GRP1_DisableClock\n
00851   *         APB2ENR      IOPBEN        LL_APB2_GRP1_DisableClock\n
00852   *         APB2ENR      IOPCEN        LL_APB2_GRP1_DisableClock\n
00853   *         APB2ENR      IOPDEN        LL_APB2_GRP1_DisableClock\n
00854   *         APB2ENR      IOPEEN        LL_APB2_GRP1_DisableClock\n
00855   *         APB2ENR      IOPFEN        LL_APB2_GRP1_DisableClock\n
00856   *         APB2ENR      IOPGEN        LL_APB2_GRP1_DisableClock\n
00857   *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n
00858   *         APB2ENR      TIM10EN       LL_APB2_GRP1_DisableClock\n
00859   *         APB2ENR      TIM11EN       LL_APB2_GRP1_DisableClock\n
00860   *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n
00861   *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n
00862   *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n
00863   *         APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n
00864   *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n
00865   *         APB2ENR      TIM9EN        LL_APB2_GRP1_DisableClock\n
00866   *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock
00867   * @param  Periphs This parameter can be a combination of the following values:
00868   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
00869   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
00870   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
00871   *         @arg @ref LL_APB2_GRP1_PERIPH_AFIO
00872   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
00873   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
00874   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
00875   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
00876   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
00877   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
00878   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
00879   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
00880   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
00881   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
00882   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
00883   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
00884   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
00885   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
00886   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
00887   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
00888   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00889   *
00890   *         (*) value not defined in all devices.
00891   * @retval None
00892 */
00893 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
00894 {
00895   CLEAR_BIT(RCC->APB2ENR, Periphs);
00896 }
00897
00898 /**
00899   * @brief  Force APB2 peripherals reset.
00900   * @rmtoll APB2RSTR     ADC1RST       LL_APB2_GRP1_ForceReset\n
00901   *         APB2RSTR     ADC2RST       LL_APB2_GRP1_ForceReset\n
00902   *         APB2RSTR     ADC3RST       LL_APB2_GRP1_ForceReset\n
00903   *         APB2RSTR     AFIORST       LL_APB2_GRP1_ForceReset\n
00904   *         APB2RSTR     IOPARST       LL_APB2_GRP1_ForceReset\n
00905   *         APB2RSTR     IOPBRST       LL_APB2_GRP1_ForceReset\n
00906   *         APB2RSTR     IOPCRST       LL_APB2_GRP1_ForceReset\n
00907   *         APB2RSTR     IOPDRST       LL_APB2_GRP1_ForceReset\n
00908   *         APB2RSTR     IOPERST       LL_APB2_GRP1_ForceReset\n
00909   *         APB2RSTR     IOPFRST       LL_APB2_GRP1_ForceReset\n
00910   *         APB2RSTR     IOPGRST       LL_APB2_GRP1_ForceReset\n
00911   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n
00912   *         APB2RSTR     TIM10RST      LL_APB2_GRP1_ForceReset\n
00913   *         APB2RSTR     TIM11RST      LL_APB2_GRP1_ForceReset\n
00914   *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n
00915   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n
00916   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n
00917   *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n
00918   *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n
00919   *         APB2RSTR     TIM9RST       LL_APB2_GRP1_ForceReset\n
00920   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset
00921   * @param  Periphs This parameter can be a combination of the following values:
00922   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
00923   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
00924   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
00925   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
00926   *         @arg @ref LL_APB2_GRP1_PERIPH_AFIO
00927   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
00928   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
00929   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
00930   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
00931   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
00932   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
00933   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
00934   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
00935   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
00936   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
00937   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
00938   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
00939   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
00940   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
00941   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
00942   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
00943   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00944   *
00945   *         (*) value not defined in all devices.
00946   * @retval None
00947 */
00948 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
00949 {
00950   SET_BIT(RCC->APB2RSTR, Periphs);
00951 }
00952
00953 /**
00954   * @brief  Release APB2 peripherals reset.
00955   * @rmtoll APB2RSTR     ADC1RST       LL_APB2_GRP1_ReleaseReset\n
00956   *         APB2RSTR     ADC2RST       LL_APB2_GRP1_ReleaseReset\n
00957   *         APB2RSTR     ADC3RST       LL_APB2_GRP1_ReleaseReset\n
00958   *         APB2RSTR     AFIORST       LL_APB2_GRP1_ReleaseReset\n
00959   *         APB2RSTR     IOPARST       LL_APB2_GRP1_ReleaseReset\n
00960   *         APB2RSTR     IOPBRST       LL_APB2_GRP1_ReleaseReset\n
00961   *         APB2RSTR     IOPCRST       LL_APB2_GRP1_ReleaseReset\n
00962   *         APB2RSTR     IOPDRST       LL_APB2_GRP1_ReleaseReset\n
00963   *         APB2RSTR     IOPERST       LL_APB2_GRP1_ReleaseReset\n
00964   *         APB2RSTR     IOPFRST       LL_APB2_GRP1_ReleaseReset\n
00965   *         APB2RSTR     IOPGRST       LL_APB2_GRP1_ReleaseReset\n
00966   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n
00967   *         APB2RSTR     TIM10RST      LL_APB2_GRP1_ReleaseReset\n
00968   *         APB2RSTR     TIM11RST      LL_APB2_GRP1_ReleaseReset\n
00969   *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n
00970   *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n
00971   *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n
00972   *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n
00973   *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n
00974   *         APB2RSTR     TIM9RST       LL_APB2_GRP1_ReleaseReset\n
00975   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset
00976   * @param  Periphs This parameter can be a combination of the following values:
00977   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
00978   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
00979   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
00980   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
00981   *         @arg @ref LL_APB2_GRP1_PERIPH_AFIO
00982   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
00983   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
00984   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
00985   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
00986   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
00987   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
00988   *         @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
00989   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
00990   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
00991   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
00992   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
00993   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
00994   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
00995   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
00996   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
00997   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
00998   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
00999   *
01000   *         (*) value not defined in all devices.
01001   * @retval None
01002 */
01003 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
01004 {
01005   CLEAR_BIT(RCC->APB2RSTR, Periphs);
01006 }
01007
01008 /**
01009   * @}
01010   */
01011
01012
01013 /**
01014   * @}
01015   */
01016
01017 /**
01018   * @}
01019   */
01020
01021 #endif /* defined(RCC) */
01022
01023 /**
01024   * @}
01025   */
01026
01027 #ifdef __cplusplus
01028 }
01029 #endif
01030
01031 #endif /* __STM32F1xx_LL_BUS_H */
01032
01033 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_cortex.h Source File

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stm32f1xx_ll_cortex.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_cortex.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of CORTEX LL module.
00008   @verbatim
00009   ==============================================================================
00010                      ##### How to use this driver #####
00011   ==============================================================================
00012     [..]
00013     The LL CORTEX driver contains a set of generic APIs that can be
00014     used by user:
00015       (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
00016           functions
00017       (+) Low power mode configuration (SCB register of Cortex-MCU)
00018       (+) MPU API to configure and enable regions
00019           (MPU services provided only on some devices)
00020       (+) API to access to MCU info (CPUID register)
00021       (+) API to enable fault handler (SHCSR accesses)
00022
00023   @endverbatim
00024   ******************************************************************************
00025   * @attention
00026   *
00027   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00028   *
00029   * Redistribution and use in source and binary forms, with or without modification,
00030   * are permitted provided that the following conditions are met:
00031   *   1. Redistributions of source code must retain the above copyright notice,
00032   *      this list of conditions and the following disclaimer.
00033   *   2. Redistributions in binary form must reproduce the above copyright notice,
00034   *      this list of conditions and the following disclaimer in the documentation
00035   *      and/or other materials provided with the distribution.
00036   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00037   *      may be used to endorse or promote products derived from this software
00038   *      without specific prior written permission.
00039   *
00040   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00041   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00042   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00043   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00044   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00045   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00046   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00047   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00048   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00049   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00050   *
00051   ******************************************************************************
00052   */
00053
00054 /* Define to prevent recursive inclusion -------------------------------------*/
00055 #ifndef __STM32F1xx_LL_CORTEX_H
00056 #define __STM32F1xx_LL_CORTEX_H
00057
00058 #ifdef __cplusplus
00059 extern "C" {
00060 #endif
00061
00062 /* Includes ------------------------------------------------------------------*/
00063 #include "stm32f1xx.h"
00064
00065 /** @addtogroup STM32F1xx_LL_Driver
00066   * @{
00067   */
00068
00069 /** @defgroup CORTEX_LL CORTEX
00070   * @{
00071   */
00072
00073 /* Private types -------------------------------------------------------------*/
00074 /* Private variables ---------------------------------------------------------*/
00075
00076 /* Private constants ---------------------------------------------------------*/
00077
00078 /* Private macros ------------------------------------------------------------*/
00079
00080 /* Exported types ------------------------------------------------------------*/
00081 /* Exported constants --------------------------------------------------------*/
00082 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
00083   * @{
00084   */
00085
00086 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
00087   * @{
00088   */
00089 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
00090 #define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
00096   * @{
00097   */
00098 #define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
00099 #define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
00100 #define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
00101 /**
00102   * @}
00103   */
00104
00105 #if __MPU_PRESENT
00106
00107 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
00108   * @{
00109   */
00110 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
00111 #define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
00112 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
00113 #define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
00114 /**
00115   * @}
00116   */
00117
00118 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
00119   * @{
00120   */
00121 #define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
00122 #define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
00123 #define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
00124 #define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
00125 #define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
00126 #define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
00127 #define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
00128 #define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
00129 /**
00130   * @}
00131   */
00132
00133 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
00134   * @{
00135   */
00136 #define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
00137 #define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
00138 #define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
00139 #define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
00140 #define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
00141 #define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
00142 #define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
00143 #define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
00144 #define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
00145 #define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
00146 #define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
00147 #define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
00148 #define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
00149 #define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
00150 #define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
00151 #define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
00152 #define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
00153 #define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
00154 #define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
00155 #define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
00156 #define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
00157 #define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
00158 #define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
00159 #define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
00160 #define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
00161 #define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
00162 #define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
00163 #define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
00169   * @{
00170   */
00171 #define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
00172 #define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
00173 #define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
00174 #define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
00175 #define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
00176 #define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
00177 /**
00178   * @}
00179   */
00180
00181 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
00182   * @{
00183   */
00184 #define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
00185 #define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
00186 #define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
00187 #define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
00188 /**
00189   * @}
00190   */
00191
00192 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
00193   * @{
00194   */
00195 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
00196 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
00202   * @{
00203   */
00204 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
00205 #define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
00206 /**
00207   * @}
00208   */
00209
00210 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
00211   * @{
00212   */
00213 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
00214 #define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
00215 /**
00216   * @}
00217   */
00218
00219 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
00220   * @{
00221   */
00222 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
00223 #define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
00224 /**
00225   * @}
00226   */
00227 #endif /* __MPU_PRESENT */
00228 /**
00229   * @}
00230   */
00231
00232 /* Exported macro ------------------------------------------------------------*/
00233
00234 /* Exported functions --------------------------------------------------------*/
00235 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
00236   * @{
00237   */
00238
00239 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
00240   * @{
00241   */
00242
00243 /**
00244   * @brief  This function checks if the Systick counter flag is active or not.
00245   * @note   It can be used in timeout function on application side.
00246   * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
00247   * @retval State of bit (1 or 0).
00248   */
00249 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
00250 {
00251   return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
00252 }
00253
00254 /**
00255   * @brief  Configures the SysTick clock source
00256   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
00257   * @param  Source This parameter can be one of the following values:
00258   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00259   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00260   * @retval None
00261   */
00262 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
00263 {
00264   if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
00265   {
00266     SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00267   }
00268   else
00269   {
00270     CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00271   }
00272 }
00273
00274 /**
00275   * @brief  Get the SysTick clock source
00276   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
00277   * @retval Returned value can be one of the following values:
00278   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
00279   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
00280   */
00281 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
00282 {
00283   return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
00284 }
00285
00286 /**
00287   * @brief  Enable SysTick exception request
00288   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
00289   * @retval None
00290   */
00291 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
00292 {
00293   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00294 }
00295
00296 /**
00297   * @brief  Disable SysTick exception request
00298   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
00299   * @retval None
00300   */
00301 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
00302 {
00303   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
00304 }
00305
00306 /**
00307   * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
00308   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
00309   * @retval State of bit (1 or 0).
00310   */
00311 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
00312 {
00313   return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
00314 }
00315
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
00321   * @{
00322   */
00323
00324 /**
00325   * @brief  Processor uses sleep as its low power mode
00326   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
00327   * @retval None
00328   */
00329 __STATIC_INLINE void LL_LPM_EnableSleep(void)
00330 {
00331   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00332   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00333 }
00334
00335 /**
00336   * @brief  Processor uses deep sleep as its low power mode
00337   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
00338   * @retval None
00339   */
00340 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
00341 {
00342   /* Set SLEEPDEEP bit of Cortex System Control Register */
00343   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00344 }
00345
00346 /**
00347   * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
00348   * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
00349   *         empty main application.
00350   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
00351   * @retval None
00352   */
00353 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
00354 {
00355   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00356   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00357 }
00358
00359 /**
00360   * @brief  Do not sleep when returning to Thread mode.
00361   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
00362   * @retval None
00363   */
00364 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
00365 {
00366   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00367   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00368 }
00369
00370 /**
00371   * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
00372   *         processor.
00373   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
00374   * @retval None
00375   */
00376 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
00377 {
00378   /* Set SEVEONPEND bit of Cortex System Control Register */
00379   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00380 }
00381
00382 /**
00383   * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
00384   *         excluded
00385   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
00386   * @retval None
00387   */
00388 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
00389 {
00390   /* Clear SEVEONPEND bit of Cortex System Control Register */
00391   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00392 }
00393
00394 /**
00395   * @}
00396   */
00397
00398 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
00399   * @{
00400   */
00401
00402 /**
00403   * @brief  Enable a fault in System handler control register (SHCSR)
00404   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
00405   * @param  Fault This parameter can be a combination of the following values:
00406   *         @arg @ref LL_HANDLER_FAULT_USG
00407   *         @arg @ref LL_HANDLER_FAULT_BUS
00408   *         @arg @ref LL_HANDLER_FAULT_MEM
00409   * @retval None
00410   */
00411 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
00412 {
00413   /* Enable the system handler fault */
00414   SET_BIT(SCB->SHCSR, Fault);
00415 }
00416
00417 /**
00418   * @brief  Disable a fault in System handler control register (SHCSR)
00419   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
00420   * @param  Fault This parameter can be a combination of the following values:
00421   *         @arg @ref LL_HANDLER_FAULT_USG
00422   *         @arg @ref LL_HANDLER_FAULT_BUS
00423   *         @arg @ref LL_HANDLER_FAULT_MEM
00424   * @retval None
00425   */
00426 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
00427 {
00428   /* Disable the system handler fault */
00429   CLEAR_BIT(SCB->SHCSR, Fault);
00430 }
00431
00432 /**
00433   * @}
00434   */
00435
00436 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
00437   * @{
00438   */
00439
00440 /**
00441   * @brief  Get Implementer code
00442   * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
00443   * @retval Value should be equal to 0x41 for ARM
00444   */
00445 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
00446 {
00447   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
00448 }
00449
00450 /**
00451   * @brief  Get Variant number (The r value in the rnpn product revision identifier)
00452   * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
00453   * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
00454   */
00455 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
00456 {
00457   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
00458 }
00459
00460 /**
00461   * @brief  Get Constant number
00462   * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
00463   * @retval Value should be equal to 0xF for Cortex-M3 devices
00464   */
00465 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
00466 {
00467   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
00468 }
00469
00470 /**
00471   * @brief  Get Part number
00472   * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
00473   * @retval Value should be equal to 0xC23 for Cortex-M3
00474   */
00475 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
00476 {
00477   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
00478 }
00479
00480 /**
00481   * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
00482   * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
00483   * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
00484   */
00485 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
00486 {
00487   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
00488 }
00489
00490 /**
00491   * @}
00492   */
00493
00494 #if __MPU_PRESENT
00495 /** @defgroup CORTEX_LL_EF_MPU MPU
00496   * @{
00497   */
00498
00499 /**
00500   * @brief  Enable MPU with input options
00501   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
00502   * @param  Options This parameter can be one of the following values:
00503   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
00504   *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
00505   *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
00506   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
00507   * @retval None
00508   */
00509 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
00510 {
00511   /* Enable the MPU*/
00512   WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
00513   /* Ensure MPU settings take effects */
00514   __DSB();
00515   /* Sequence instruction fetches using update settings */
00516   __ISB();
00517 }
00518
00519 /**
00520   * @brief  Disable MPU
00521   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
00522   * @retval None
00523   */
00524 __STATIC_INLINE void LL_MPU_Disable(void)
00525 {
00526   /* Make sure outstanding transfers are done */
00527   __DMB();
00528   /* Disable MPU*/
00529   WRITE_REG(MPU->CTRL, 0U);
00530 }
00531
00532 /**
00533   * @brief  Check if MPU is enabled or not
00534   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
00535   * @retval State of bit (1 or 0).
00536   */
00537 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
00538 {
00539   return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
00540 }
00541
00542 /**
00543   * @brief  Enable a MPU region
00544   * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
00545   * @param  Region This parameter can be one of the following values:
00546   *         @arg @ref LL_MPU_REGION_NUMBER0
00547   *         @arg @ref LL_MPU_REGION_NUMBER1
00548   *         @arg @ref LL_MPU_REGION_NUMBER2
00549   *         @arg @ref LL_MPU_REGION_NUMBER3
00550   *         @arg @ref LL_MPU_REGION_NUMBER4
00551   *         @arg @ref LL_MPU_REGION_NUMBER5
00552   *         @arg @ref LL_MPU_REGION_NUMBER6
00553   *         @arg @ref LL_MPU_REGION_NUMBER7
00554   * @retval None
00555   */
00556 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
00557 {
00558   /* Set Region number */
00559   WRITE_REG(MPU->RNR, Region);
00560   /* Enable the MPU region */
00561   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00562 }
00563
00564 /**
00565   * @brief  Configure and enable a region
00566   * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
00567   *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
00568   *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
00569   *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
00570   *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
00571   *         MPU_RASR     S             LL_MPU_ConfigRegion\n
00572   *         MPU_RASR     C             LL_MPU_ConfigRegion\n
00573   *         MPU_RASR     B             LL_MPU_ConfigRegion\n
00574   *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
00575   * @param  Region This parameter can be one of the following values:
00576   *         @arg @ref LL_MPU_REGION_NUMBER0
00577   *         @arg @ref LL_MPU_REGION_NUMBER1
00578   *         @arg @ref LL_MPU_REGION_NUMBER2
00579   *         @arg @ref LL_MPU_REGION_NUMBER3
00580   *         @arg @ref LL_MPU_REGION_NUMBER4
00581   *         @arg @ref LL_MPU_REGION_NUMBER5
00582   *         @arg @ref LL_MPU_REGION_NUMBER6
00583   *         @arg @ref LL_MPU_REGION_NUMBER7
00584   * @param  Address Value of region base address
00585   * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
00586   * @param  Attributes This parameter can be a combination of the following values:
00587   *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
00588   *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
00589   *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
00590   *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
00591   *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
00592   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
00593   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
00594   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
00595   *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
00596   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
00597   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
00598   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
00599   *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
00600   * @retval None
00601   */
00602 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
00603 {
00604   /* Set Region number */
00605   WRITE_REG(MPU->RNR, Region);
00606   /* Set base address */
00607   WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
00608   /* Configure MPU */
00609   WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
00610 }
00611
00612 /**
00613   * @brief  Disable a region
00614   * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
00615   *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
00616   * @param  Region This parameter can be one of the following values:
00617   *         @arg @ref LL_MPU_REGION_NUMBER0
00618   *         @arg @ref LL_MPU_REGION_NUMBER1
00619   *         @arg @ref LL_MPU_REGION_NUMBER2
00620   *         @arg @ref LL_MPU_REGION_NUMBER3
00621   *         @arg @ref LL_MPU_REGION_NUMBER4
00622   *         @arg @ref LL_MPU_REGION_NUMBER5
00623   *         @arg @ref LL_MPU_REGION_NUMBER6
00624   *         @arg @ref LL_MPU_REGION_NUMBER7
00625   * @retval None
00626   */
00627 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
00628 {
00629   /* Set Region number */
00630   WRITE_REG(MPU->RNR, Region);
00631   /* Disable the MPU region */
00632   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
00633 }
00634
00635 /**
00636   * @}
00637   */
00638
00639 #endif /* __MPU_PRESENT */
00640 /**
00641   * @}
00642   */
00643
00644 /**
00645   * @}
00646   */
00647
00648 /**
00649   * @}
00650   */
00651
00652 #ifdef __cplusplus
00653 }
00654 #endif
00655
00656 #endif /* __STM32F1xx_LL_CORTEX_H */
00657
00658 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_crc.c Source File

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stm32f1xx_ll_crc.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_crc.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   CRC LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_crc.h"
00041 #include "stm32f1xx_ll_bus.h"
00042
00043 #ifdef  USE_FULL_ASSERT
00044 #include "stm32_assert.h"
00045 #else
00046 #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (CRC)
00054
00055 /** @addtogroup CRC_LL
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064
00065 /* Exported functions --------------------------------------------------------*/
00066 /** @addtogroup CRC_LL_Exported_Functions
00067   * @{
00068   */
00069
00070 /** @addtogroup CRC_LL_EF_Init
00071   * @{
00072   */
00073
00074 /**
00075   * @brief  De-initialize CRC registers (Registers restored to their default values).
00076   * @param  CRCx CRC Instance
00077   * @retval An ErrorStatus enumeration value:
00078   *          - SUCCESS: CRC registers are de-initialized
00079   *          - ERROR: CRC registers are not de-initialized
00080   */
00081 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
00082 {
00083   ErrorStatus status = SUCCESS;
00084
00085   /* Check the parameters */
00086   assert_param(IS_CRC_ALL_INSTANCE(CRCx));
00087
00088   if (CRCx == CRC)
00089   {
00090
00091     /* Reset the CRC calculation unit */
00092     LL_CRC_ResetCRCCalculationUnit(CRCx);
00093
00094     /* Reset IDR register */
00095     LL_CRC_Write_IDR(CRCx, 0x00U);
00096   }
00097   else
00098   {
00099     status = ERROR;
00100   }
00101
00102   return (status);
00103 }
00104
00105 /**
00106   * @}
00107   */
00108
00109 /**
00110   * @}
00111   */
00112
00113 /**
00114   * @}
00115   */
00116
00117 #endif /* defined (CRC) */
00118
00119 /**
00120   * @}
00121   */
00122
00123 #endif /* USE_FULL_LL_DRIVER */
00124
00125 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00126
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_crc.h Source File

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stm32f1xx_ll_crc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_crc.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of CRC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_CRC_H
00040 #define __STM32F1xx_LL_CRC_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(CRC)
00054
00055 /** @defgroup CRC_LL CRC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063
00064 /* Exported types ------------------------------------------------------------*/
00065 /* Exported constants --------------------------------------------------------*/
00066
00067 /* Exported macro ------------------------------------------------------------*/
00068 /** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
00069   * @{
00070   */
00071
00072 /** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
00073   * @{
00074   */
00075
00076 /**
00077   * @brief  Write a value in CRC register
00078   * @param  __INSTANCE__ CRC Instance
00079   * @param  __REG__ Register to be written
00080   * @param  __VALUE__ Value to be written in the register
00081   * @retval None
00082   */
00083 #define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00084
00085 /**
00086   * @brief  Read a value in CRC register
00087   * @param  __INSTANCE__ CRC Instance
00088   * @param  __REG__ Register to be read
00089   * @retval Register value
00090   */
00091 #define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00092 /**
00093   * @}
00094   */
00095
00096 /**
00097   * @}
00098   */
00099
00100
00101 /* Exported functions --------------------------------------------------------*/
00102 /** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
00103   * @{
00104   */
00105
00106 /** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
00107   * @{
00108   */
00109
00110 /**
00111   * @brief  Reset the CRC calculation unit.
00112   * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit
00113   * @param  CRCx CRC Instance
00114   * @retval None
00115   */
00116 __STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
00117 {
00118   WRITE_REG(CRCx->CR, CRC_CR_RESET);
00119 }
00120
00121 /**
00122   * @}
00123   */
00124
00125 /** @defgroup CRC_LL_EF_Data_Management Data_Management
00126   * @{
00127   */
00128
00129 /**
00130   * @brief  Write given 32-bit data to the CRC calculator
00131   * @rmtoll DR           DR            LL_CRC_FeedData32
00132   * @param  CRCx CRC Instance
00133   * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
00134   * @retval None
00135   */
00136 __STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
00137 {
00138   WRITE_REG(CRCx->DR, InData);
00139 }
00140
00141 /**
00142   * @brief  Return current CRC calculation result. 32 bits value is returned.
00143   * @rmtoll DR           DR            LL_CRC_ReadData32
00144   * @param  CRCx CRC Instance
00145   * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
00146   */
00147 __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
00148 {
00149   return (uint32_t)(READ_REG(CRCx->DR));
00150 }
00151
00152 /**
00153   * @brief  Return data stored in the Independent Data(IDR) register.
00154   * @note   This register can be used as a temporary storage location for one byte.
00155   * @rmtoll IDR          IDR           LL_CRC_Read_IDR
00156   * @param  CRCx CRC Instance
00157   * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
00158   */
00159 __STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
00160 {
00161   return (uint32_t)(READ_REG(CRCx->IDR));
00162 }
00163
00164 /**
00165   * @brief  Store data in the Independent Data(IDR) register.
00166   * @note   This register can be used as a temporary storage location for one byte.
00167   * @rmtoll IDR          IDR           LL_CRC_Write_IDR
00168   * @param  CRCx CRC Instance
00169   * @param  InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
00170   * @retval None
00171   */
00172 __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
00173 {
00174   *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
00175 }
00176 /**
00177   * @}
00178   */
00179
00180 #if defined(USE_FULL_LL_DRIVER)
00181 /** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
00182   * @{
00183   */
00184
00185 ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
00186
00187 /**
00188   * @}
00189   */
00190 #endif /* USE_FULL_LL_DRIVER */
00191
00192 /**
00193   * @}
00194   */
00195
00196 /**
00197   * @}
00198   */
00199
00200 #endif /* defined(CRC) */
00201
00202 /**
00203   * @}
00204   */
00205
00206 #ifdef __cplusplus
00207 }
00208 #endif
00209
00210 #endif /* __STM32F1xx_LL_CRC_H */
00211
00212 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_dac.c Source File

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stm32f1xx_ll_dac.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_dac.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   DAC LL module driver
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_dac.h"
00041 #include "stm32f1xx_ll_bus.h"
00042
00043 #ifdef USE_FULL_ASSERT
00044   #include "stm32_assert.h"
00045 #else
00046   #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (DAC)
00054
00055 /** @addtogroup DAC_LL DAC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063
00064 /** @addtogroup DAC_LL_Private_Macros
00065   * @{
00066   */
00067
00068 #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__)                           \
00069   (                                                                            \
00070       ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)                                  \
00071    || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)                                  \
00072   )
00073
00074 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
00075   (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
00076    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
00077    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
00078    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
00079    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
00080    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO)                      \
00081    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
00082    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
00083    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)                      \
00084    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
00085   )
00086 #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)           \
00087   (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)     \
00088    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
00089    || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
00090   )
00091
00092 #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__)      \
00093   (   ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)     \
00094    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)  \
00095    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)  \
00096    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)  \
00097    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)  \
00098    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)  \
00099    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)  \
00100    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)  \
00101    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)  \
00102    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)  \
00103    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
00104    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
00105    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)       \
00106    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)       \
00107    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)       \
00108    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)      \
00109    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)      \
00110    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)      \
00111    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)     \
00112    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)     \
00113    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)     \
00114    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)    \
00115    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)    \
00116    || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)    \
00117   )
00118
00119 #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
00120   (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
00121    || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
00122   )
00123
00124 /**
00125   * @}
00126   */
00127
00128
00129 /* Private function prototypes -----------------------------------------------*/
00130
00131 /* Exported functions --------------------------------------------------------*/
00132 /** @addtogroup DAC_LL_Exported_Functions
00133   * @{
00134   */
00135
00136 /** @addtogroup DAC_LL_EF_Init
00137   * @{
00138   */
00139
00140 /**
00141   * @brief  De-initialize registers of the selected DAC instance
00142   *         to their default reset values.
00143   * @param  DACx DAC instance
00144   * @retval An ErrorStatus enumeration value:
00145   *          - SUCCESS: DAC registers are de-initialized
00146   *          - ERROR: not applicable
00147   */
00148 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
00149 {
00150   /* Check the parameters */
00151   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00152
00153   /* Force reset of DAC1 clock */
00154   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
00155
00156   /* Release reset of DAC1 clock */
00157   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
00158   return SUCCESS;
00159 }
00160
00161 /**
00162   * @brief  Initialize some features of DAC instance.
00163   * @note   The setting of these parameters by function @ref LL_DAC_Init()
00164   *         is conditioned to DAC state:
00165   *         DAC instance must be disabled.
00166   * @param  DACx DAC instance
00167   * @param  DAC_Channel This parameter can be one of the following values:
00168   *         @arg @ref LL_DAC_CHANNEL_1
00169   *         @arg @ref LL_DAC_CHANNEL_2
00170   * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
00171   * @retval An ErrorStatus enumeration value:
00172   *          - SUCCESS: DAC registers are initialized
00173   *          - ERROR: DAC registers are not initialized
00174   */
00175 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
00176 {
00177   ErrorStatus status = SUCCESS;
00178
00179   /* Check the parameters */
00180   assert_param(IS_DAC_ALL_INSTANCE(DACx));
00181   assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
00182   assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
00183   assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
00184   assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
00185   if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00186   {
00187     assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
00188   }
00189
00190   /* Note: Hardware constraint (refer to description of this function)        */
00191   /*       DAC instance must be disabled.                                     */
00192   if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
00193   {
00194     /* Configuration of DAC channel:                                          */
00195     /*  - TriggerSource                                                       */
00196     /*  - WaveAutoGeneration                                                  */
00197     /*  - OutputBuffer                                                        */
00198     if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
00199     {
00200       MODIFY_REG(DACx->CR,
00201                  (  DAC_CR_TSEL1
00202                   | DAC_CR_WAVE1
00203                   | DAC_CR_MAMP1
00204                   | DAC_CR_BOFF1
00205                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00206                 ,
00207                  (  DAC_InitStruct->TriggerSource
00208                   | DAC_InitStruct->WaveAutoGeneration
00209                   | DAC_InitStruct->WaveAutoGenerationConfig
00210                   | DAC_InitStruct->OutputBuffer
00211                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00212                 );
00213     }
00214     else
00215     {
00216       MODIFY_REG(DACx->CR,
00217                  (  DAC_CR_TSEL1
00218                   | DAC_CR_WAVE1
00219                   | DAC_CR_BOFF1
00220                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00221                 ,
00222                  (  DAC_InitStruct->TriggerSource
00223                   | LL_DAC_WAVE_AUTO_GENERATION_NONE
00224                   | DAC_InitStruct->OutputBuffer
00225                  ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00226                 );
00227     }
00228   }
00229   else
00230   {
00231     /* Initialization error: DAC instance is not disabled.                    */
00232     status = ERROR;
00233   }
00234   return status;
00235 }
00236
00237 /**
00238   * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
00239   * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
00240   *                       whose fields will be set to default values.
00241   * @retval None
00242   */
00243 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
00244 {
00245   /* Set DAC_InitStruct fields to default values */
00246   DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
00247   DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
00248   /* Note: Parameter discarded if wave auto generation is disabled,           */
00249   /*       set anyway to its default value.                                   */
00250   DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
00251   DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
00252 }
00253
00254 /**
00255   * @}
00256   */
00257
00258 /**
00259   * @}
00260   */
00261
00262 /**
00263   * @}
00264   */
00265
00266 #endif /* DAC */
00267
00268 /**
00269   * @}
00270   */
00271
00272 #endif /* USE_FULL_LL_DRIVER */
00273
00274 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_dac.h Source File

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stm32f1xx_ll_dac.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_dac.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of DAC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_DAC_H
00040 #define __STM32F1xx_LL_DAC_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (DAC)
00054
00055 /** @defgroup DAC_LL DAC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
00064   * @{
00065   */
00066
00067 /* Internal masks for DAC channels definition */
00068 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
00069 /* - channel bits position into register CR                                   */
00070 /* - channel bits position into register SWTRIG                               */
00071 /* - channel register offset of data holding register DHRx                    */
00072 /* - channel register offset of data output register DORx                     */
00073 #define DAC_CR_CH1_BITOFFSET           0U    /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
00074 #define DAC_CR_CH2_BITOFFSET           16U   /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
00075 #define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
00076
00077 #define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
00078 #define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
00079 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
00080
00081 #define DAC_REG_DHR12R1_REGOFFSET      0x00000000U             /* Register DHR12Rx channel 1 taken as reference */
00082 #define DAC_REG_DHR12L1_REGOFFSET      0x00100000U             /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00083 #define DAC_REG_DHR8R1_REGOFFSET       0x02000000U             /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00084 #define DAC_REG_DHR12R2_REGOFFSET      0x00030000U             /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
00085 #define DAC_REG_DHR12L2_REGOFFSET      0x00400000U             /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
00086 #define DAC_REG_DHR8R2_REGOFFSET       0x05000000U             /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
00087 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
00088 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
00089 #define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000U
00090 #define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
00091
00092 #define DAC_REG_DOR1_REGOFFSET         0x00000000U             /* Register DORx channel 1 taken as reference */
00093 #define DAC_REG_DOR2_REGOFFSET         0x10000000U             /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
00094 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
00095
00096 /* DAC registers bits positions */
00097 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                16U  /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
00098 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                20U  /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
00099 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                  8U  /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
00100
00101 /* Miscellaneous data */
00102 #define DAC_DIGITAL_SCALE_12BITS                        4095U  /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
00103
00104 /**
00105   * @}
00106   */
00107
00108
00109 /* Private macros ------------------------------------------------------------*/
00110 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
00111   * @{
00112   */
00113
00114 /**
00115   * @brief  Driver macro reserved for internal use: isolate bits with the
00116   *         selected mask and shift them to the register LSB
00117   *         (shift mask on register position bit 0).
00118   * @param  __BITS__ Bits in register 32 bits
00119   * @param  __MASK__ Mask in register 32 bits
00120   * @retval Bits in register 32 bits
00121 */
00122 #define __DAC_MASK_SHIFT(__BITS__, __MASK__)                                   \
00123   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
00124
00125 /**
00126   * @brief  Driver macro reserved for internal use: set a pointer to
00127   *         a register from a register basis from which an offset
00128   *         is applied.
00129   * @param  __REG__ Register basis from which the offset is applied.
00130   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
00131   * @retval Pointer to register address
00132 */
00133 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
00134  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
00135
00136 /**
00137   * @}
00138   */
00139
00140
00141 /* Exported types ------------------------------------------------------------*/
00142 #if defined(USE_FULL_LL_DRIVER)
00143 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
00144   * @{
00145   */
00146
00147 /**
00148   * @brief  Structure definition of some features of DAC instance.
00149   */
00150 typedef struct
00151 {
00152   uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
00153                                              This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
00154
00155                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
00156
00157   uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
00158                                              This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
00159
00160                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
00161
00162   uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
00163                                              If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
00164                                              If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
00165                                              @note If waveform automatic generation mode is disabled, this parameter is discarded.
00166
00167                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
00168
00169   uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
00170                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
00171
00172                                              This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
00173
00174 } LL_DAC_InitTypeDef;
00175
00176 /**
00177   * @}
00178   */
00179 #endif /* USE_FULL_LL_DRIVER */
00180
00181 /* Exported constants --------------------------------------------------------*/
00182 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
00183   * @{
00184   */
00185
00186 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
00187   * @brief    Flags defines which can be used with LL_DAC_ReadReg function
00188   * @{
00189   */
00190 /* DAC channel 1 flags */
00191 #if defined(DAC_SR_DMAUDR1)
00192 #define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
00193 #endif /* DAC_SR_DMAUDR1 */
00194
00195 /* DAC channel 2 flags */
00196 #if defined(DAC_SR_DMAUDR2)
00197 #define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
00198 #endif /* DAC_SR_DMAUDR2 */
00199 /**
00200   * @}
00201   */
00202
00203 /** @defgroup DAC_LL_EC_IT DAC interruptions
00204   * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
00205   * @{
00206   */
00207 #if defined(DAC_CR_DMAUDRIE1)
00208 #define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
00209 #endif /* DAC_CR_DMAUDRIE1 */
00210 #if defined(DAC_CR_DMAUDRIE2)
00211 #define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
00212 #endif /* DAC_CR_DMAUDRIE2 */
00213 /**
00214   * @}
00215   */
00216
00217 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
00218   * @{
00219   */
00220 #define LL_DAC_CHANNEL_1                   (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
00221 #define LL_DAC_CHANNEL_2                   (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
00227   * @{
00228   */
00229 #define LL_DAC_TRIG_SOFTWARE               (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
00230 #define LL_DAC_TRIG_EXT_TIM3_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
00231 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
00232 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
00233 #define LL_DAC_TRIG_EXT_TIM8_TRGO          (                                  DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
00234 #define LL_DAC_TRIG_EXT_TIM4_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
00235 #define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
00236 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
00237 #define LL_DAC_TRIG_EXT_TIM5_TRGO          (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
00238 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
00239 /**
00240   * @}
00241   */
00242
00243 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
00244   * @{
00245   */
00246 #define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000U             /*!< DAC channel wave auto generation mode disabled. */
00247 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (DAC_CR_WAVE1_0)        /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
00248 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)        /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
00249 /**
00250   * @}
00251   */
00252
00253 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
00254   * @{
00255   */
00256 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000U                                                         /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
00257 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
00258 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
00259 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
00260 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
00261 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
00262 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
00263 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
00264 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
00265 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
00266 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
00267 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
00268 /**
00269   * @}
00270   */
00271
00272 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
00273   * @{
00274   */
00275 #define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000U                                                         /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
00276 #define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
00277 #define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
00278 #define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
00279 #define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
00280 #define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
00281 #define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
00282 #define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
00283 #define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
00284 #define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
00285 #define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
00286 #define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
00292   * @{
00293   */
00294 #define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000U             /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
00295 #define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_CR_BOFF1)          /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
00296 /**
00297   * @}
00298   */
00299
00300
00301 /** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
00302   * @{
00303   */
00304 #define LL_DAC_RESOLUTION_12B              0x00000000U             /*!< DAC channel resolution 12 bits */
00305 #define LL_DAC_RESOLUTION_8B               0x00000002U             /*!< DAC channel resolution 8 bits */
00306 /**
00307   * @}
00308   */
00309
00310 /** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
00311   * @{
00312   */
00313 /* List of DAC registers intended to be used (most commonly) with             */
00314 /* DMA transfer.                                                              */
00315 /* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
00316 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
00317 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
00318 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_MASK  /*!< DAC channel data holding register 8 bits right aligned */
00319 /**
00320   * @}
00321   */
00322
00323 /** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
00324   * @note   Only DAC IP HW delays are defined in DAC LL driver driver,
00325   *         not timeout values.
00326   *         For details on delays values, refer to descriptions in source code
00327   *         above each literal definition.
00328   * @{
00329   */
00330
00331 /* Delay for DAC channel voltage settling time from DAC channel startup       */
00332 /* (transition from disable to enable).                                       */
00333 /* Note: DAC channel startup time depends on board application environment:   */
00334 /*       impedance connected to DAC channel output.                           */
00335 /*       The delay below is specified under conditions:                       */
00336 /*        - voltage maximum transition (lowest to highest value)              */
00337 /*        - until voltage reaches final value +-1LSB                          */
00338 /*        - DAC channel output buffer enabled                                 */
00339 /*        - load impedance of 5kOhm (min), 50pF (max)                         */
00340 /* Literal set to maximum value (refer to device datasheet,                   */
00341 /* parameter "tWAKEUP").                                                      */
00342 /* Unit: us                                                                   */
00343 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             15U  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
00344
00345 /* Delay for DAC channel voltage settling time.                               */
00346 /* Note: DAC channel startup time depends on board application environment:   */
00347 /*       impedance connected to DAC channel output.                           */
00348 /*       The delay below is specified under conditions:                       */
00349 /*        - voltage maximum transition (lowest to highest value)              */
00350 /*        - until voltage reaches final value +-1LSB                          */
00351 /*        - DAC channel output buffer enabled                                 */
00352 /*        - load impedance of 5kOhm min, 50pF max                             */
00353 /* Literal set to maximum value (refer to device datasheet,                   */
00354 /* parameter "tSETTLING").                                                    */
00355 /* Unit: us                                                                   */
00356 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US                    12U  /*!< Delay for DAC channel voltage settling time */
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 /* Exported macro ------------------------------------------------------------*/
00366 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
00367   * @{
00368   */
00369
00370 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
00371   * @{
00372   */
00373
00374 /**
00375   * @brief  Write a value in DAC register
00376   * @param  __INSTANCE__ DAC Instance
00377   * @param  __REG__ Register to be written
00378   * @param  __VALUE__ Value to be written in the register
00379   * @retval None
00380   */
00381 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00382
00383 /**
00384   * @brief  Read a value in DAC register
00385   * @param  __INSTANCE__ DAC Instance
00386   * @param  __REG__ Register to be read
00387   * @retval Register value
00388   */
00389 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00390
00391 /**
00392   * @}
00393   */
00394
00395 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
00396   * @{
00397   */
00398
00399 /**
00400   * @brief  Helper macro to get DAC channel number in decimal format
00401   *         from literals LL_DAC_CHANNEL_x.
00402   *         Example:
00403   *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
00404   *            will return decimal number "1".
00405   * @note   The input can be a value from functions where a channel
00406   *         number is returned.
00407   * @param  __CHANNEL__ This parameter can be one of the following values:
00408   *         @arg @ref LL_DAC_CHANNEL_1
00409   *         @arg @ref LL_DAC_CHANNEL_2
00410   * @retval 1...2
00411   */
00412 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
00413   ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
00414
00415 /**
00416   * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
00417   *         from number in decimal format.
00418   *         Example:
00419   *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
00420   *           will return a data equivalent to "LL_DAC_CHANNEL_1".
00421   * @note  If the input parameter does not correspond to a DAC channel,
00422   *        this macro returns value '0'.
00423   * @param  __DECIMAL_NB__ 1...2
00424   * @retval Returned value can be one of the following values:
00425   *         @arg @ref LL_DAC_CHANNEL_1
00426   *         @arg @ref LL_DAC_CHANNEL_2
00427   */
00428 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
00429   (((__DECIMAL_NB__) == 1U)                                                     \
00430     ? (                                                                        \
00431        LL_DAC_CHANNEL_1                                                        \
00432       )                                                                        \
00433       :                                                                        \
00434       (((__DECIMAL_NB__) == 2U)                                                 \
00435         ? (                                                                    \
00436            LL_DAC_CHANNEL_2                                                    \
00437           )                                                                    \
00438           :                                                                    \
00439           (                                                                    \
00440            0                                                                   \
00441           )                                                                    \
00442       )                                                                        \
00443   )
00444
00445 /**
00446   * @brief  Helper macro to define the DAC conversion data full-scale digital
00447   *         value corresponding to the selected DAC resolution.
00448   * @note   DAC conversion data full-scale corresponds to voltage range
00449   *         determined by analog voltage references Vref+ and Vref-
00450   *         (refer to reference manual).
00451   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00452   *         @arg @ref LL_DAC_RESOLUTION_12B
00453   *         @arg @ref LL_DAC_RESOLUTION_8B
00454   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
00455   */
00456 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
00457   ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
00458
00459 /**
00460   * @brief  Helper macro to calculate the DAC conversion data (unit: digital
00461   *         value) corresponding to a voltage (unit: mVolt).
00462   * @note   This helper macro is intended to provide input data in voltage
00463   *         rather than digital value,
00464   *         to be used with LL DAC functions such as
00465   *         @ref LL_DAC_ConvertData12RightAligned().
00466   * @note   Analog reference voltage (Vref+) must be either known from
00467   *         user board environment or can be calculated using ADC measurement
00468   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
00469   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
00470   * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
00471   *                         (unit: mVolt).
00472   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
00473   *         @arg @ref LL_DAC_RESOLUTION_12B
00474   *         @arg @ref LL_DAC_RESOLUTION_8B
00475   * @retval DAC conversion data (unit: digital value)
00476   */
00477 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
00478                                       __DAC_VOLTAGE__,\
00479                                       __DAC_RESOLUTION__)                      \
00480   ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
00481    / (__VREFANALOG_VOLTAGE__)                                                  \
00482   )
00483
00484 /**
00485   * @}
00486   */
00487
00488 /**
00489   * @}
00490   */
00491
00492
00493 /* Exported functions --------------------------------------------------------*/
00494 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
00495   * @{
00496   */
00497 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
00498   * @{
00499   */
00500
00501 /**
00502   * @brief  Set the conversion trigger source for the selected DAC channel.
00503   * @note   For conversion trigger source to be effective, DAC trigger
00504   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00505   * @note   To set conversion trigger source, DAC channel must be disabled.
00506   *         Otherwise, the setting is discarded.
00507   * @note   Availability of parameters of trigger sources from timer
00508   *         depends on timers availability on the selected device.
00509   * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
00510   *         CR       TSEL2          LL_DAC_SetTriggerSource
00511   * @param  DACx DAC instance
00512   * @param  DAC_Channel This parameter can be one of the following values:
00513   *         @arg @ref LL_DAC_CHANNEL_1
00514   *         @arg @ref LL_DAC_CHANNEL_2
00515   * @param  TriggerSource This parameter can be one of the following values:
00516   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00517   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
00518   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
00519   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
00520   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00521   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00522   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
00523   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
00524   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00525   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00526   * @retval None
00527   */
00528 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
00529 {
00530   MODIFY_REG(DACx->CR,
00531              DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00532              TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00533 }
00534
00535 /**
00536   * @brief  Get the conversion trigger source for the selected DAC channel.
00537   * @note   For conversion trigger source to be effective, DAC trigger
00538   *         must be enabled using function @ref LL_DAC_EnableTrigger().
00539   * @note   Availability of parameters of trigger sources from timer
00540   *         depends on timers availability on the selected device.
00541   * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
00542   *         CR       TSEL2          LL_DAC_GetTriggerSource
00543   * @param  DACx DAC instance
00544   * @param  DAC_Channel This parameter can be one of the following values:
00545   *         @arg @ref LL_DAC_CHANNEL_1
00546   *         @arg @ref LL_DAC_CHANNEL_2
00547   * @retval Returned value can be one of the following values:
00548   *         @arg @ref LL_DAC_TRIG_SOFTWARE
00549   *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
00550   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
00551   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
00552   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
00553   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
00554   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
00555   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
00556   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
00557   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
00558   */
00559 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00560 {
00561   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00562                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00563                    );
00564 }
00565
00566 /**
00567   * @brief  Set the waveform automatic generation mode
00568   *         for the selected DAC channel.
00569   * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
00570   *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
00571   * @param  DACx DAC instance
00572   * @param  DAC_Channel This parameter can be one of the following values:
00573   *         @arg @ref LL_DAC_CHANNEL_1
00574   *         @arg @ref LL_DAC_CHANNEL_2
00575   * @param  WaveAutoGeneration This parameter can be one of the following values:
00576   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00577   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00578   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00579   * @retval None
00580   */
00581 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
00582 {
00583   MODIFY_REG(DACx->CR,
00584              DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00585              WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00586 }
00587
00588 /**
00589   * @brief  Get the waveform automatic generation mode
00590   *         for the selected DAC channel.
00591   * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
00592   *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
00593   * @param  DACx DAC instance
00594   * @param  DAC_Channel This parameter can be one of the following values:
00595   *         @arg @ref LL_DAC_CHANNEL_1
00596   *         @arg @ref LL_DAC_CHANNEL_2
00597   * @retval Returned value can be one of the following values:
00598   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
00599   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
00600   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
00601   */
00602 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00603 {
00604   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00605                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00606                    );
00607 }
00608
00609 /**
00610   * @brief  Set the noise waveform generation for the selected DAC channel:
00611   *         Noise mode and parameters LFSR (linear feedback shift register).
00612   * @note   For wave generation to be effective, DAC channel
00613   *         wave generation mode must be enabled using
00614   *         function @ref LL_DAC_SetWaveAutoGeneration().
00615   * @note   This setting can be set when the selected DAC channel is disabled
00616   *         (otherwise, the setting operation is ignored).
00617   * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
00618   *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
00619   * @param  DACx DAC instance
00620   * @param  DAC_Channel This parameter can be one of the following values:
00621   *         @arg @ref LL_DAC_CHANNEL_1
00622   *         @arg @ref LL_DAC_CHANNEL_2
00623   * @param  NoiseLFSRMask This parameter can be one of the following values:
00624   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00625   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00626   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00627   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00628   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00629   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00630   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00631   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00632   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00633   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00634   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00635   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00636   * @retval None
00637   */
00638 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
00639 {
00640   MODIFY_REG(DACx->CR,
00641              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00642              NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00643 }
00644
00645 /**
00646   * @brief  Set the noise waveform generation for the selected DAC channel:
00647   *         Noise mode and parameters LFSR (linear feedback shift register).
00648   * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
00649   *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
00650   * @param  DACx DAC instance
00651   * @param  DAC_Channel This parameter can be one of the following values:
00652   *         @arg @ref LL_DAC_CHANNEL_1
00653   *         @arg @ref LL_DAC_CHANNEL_2
00654   * @retval Returned value can be one of the following values:
00655   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
00656   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
00657   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
00658   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
00659   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
00660   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
00661   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
00662   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
00663   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
00664   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
00665   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
00666   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
00667   */
00668 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00669 {
00670   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00671                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00672                    );
00673 }
00674
00675 /**
00676   * @brief  Set the triangle waveform generation for the selected DAC channel:
00677   *         triangle mode and amplitude.
00678   * @note   For wave generation to be effective, DAC channel
00679   *         wave generation mode must be enabled using
00680   *         function @ref LL_DAC_SetWaveAutoGeneration().
00681   * @note   This setting can be set when the selected DAC channel is disabled
00682   *         (otherwise, the setting operation is ignored).
00683   * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
00684   *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
00685   * @param  DACx DAC instance
00686   * @param  DAC_Channel This parameter can be one of the following values:
00687   *         @arg @ref LL_DAC_CHANNEL_1
00688   *         @arg @ref LL_DAC_CHANNEL_2
00689   * @param  TriangleAmplitude This parameter can be one of the following values:
00690   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00691   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00692   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00693   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00694   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00695   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00696   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00697   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00698   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00699   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00700   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00701   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00702   * @retval None
00703   */
00704 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
00705 {
00706   MODIFY_REG(DACx->CR,
00707              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00708              TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00709 }
00710
00711 /**
00712   * @brief  Set the triangle waveform generation for the selected DAC channel:
00713   *         triangle mode and amplitude.
00714   * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
00715   *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
00716   * @param  DACx DAC instance
00717   * @param  DAC_Channel This parameter can be one of the following values:
00718   *         @arg @ref LL_DAC_CHANNEL_1
00719   *         @arg @ref LL_DAC_CHANNEL_2
00720   * @retval Returned value can be one of the following values:
00721   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
00722   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
00723   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
00724   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
00725   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
00726   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
00727   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
00728   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
00729   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
00730   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
00731   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
00732   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
00733   */
00734 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00735 {
00736   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00737                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00738                    );
00739 }
00740
00741 /**
00742   * @brief  Set the output buffer for the selected DAC channel.
00743   * @rmtoll CR       BOFF1          LL_DAC_SetOutputBuffer\n
00744   *         CR       BOFF2          LL_DAC_SetOutputBuffer
00745   * @param  DACx DAC instance
00746   * @param  DAC_Channel This parameter can be one of the following values:
00747   *         @arg @ref LL_DAC_CHANNEL_1
00748   *         @arg @ref LL_DAC_CHANNEL_2
00749   * @param  OutputBuffer This parameter can be one of the following values:
00750   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00751   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00752   * @retval None
00753   */
00754 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
00755 {
00756   MODIFY_REG(DACx->CR,
00757              DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
00758              OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00759 }
00760
00761 /**
00762   * @brief  Get the output buffer state for the selected DAC channel.
00763   * @rmtoll CR       BOFF1          LL_DAC_GetOutputBuffer\n
00764   *         CR       BOFF2          LL_DAC_GetOutputBuffer
00765   * @param  DACx DAC instance
00766   * @param  DAC_Channel This parameter can be one of the following values:
00767   *         @arg @ref LL_DAC_CHANNEL_1
00768   *         @arg @ref LL_DAC_CHANNEL_2
00769   * @retval Returned value can be one of the following values:
00770   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
00771   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
00772   */
00773 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00774 {
00775   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00776                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
00777                    );
00778 }
00779
00780 /**
00781   * @}
00782   */
00783
00784 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
00785   * @{
00786   */
00787
00788 /**
00789   * @brief  Enable DAC DMA transfer request of the selected channel.
00790   * @note   To configure DMA source address (peripheral address),
00791   *         use function @ref LL_DAC_DMA_GetRegAddr().
00792   * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
00793   *         CR       DMAEN2         LL_DAC_EnableDMAReq
00794   * @param  DACx DAC instance
00795   * @param  DAC_Channel This parameter can be one of the following values:
00796   *         @arg @ref LL_DAC_CHANNEL_1
00797   *         @arg @ref LL_DAC_CHANNEL_2
00798   * @retval None
00799   */
00800 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00801 {
00802   SET_BIT(DACx->CR,
00803           DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00804 }
00805
00806 /**
00807   * @brief  Disable DAC DMA transfer request of the selected channel.
00808   * @note   To configure DMA source address (peripheral address),
00809   *         use function @ref LL_DAC_DMA_GetRegAddr().
00810   * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
00811   *         CR       DMAEN2         LL_DAC_DisableDMAReq
00812   * @param  DACx DAC instance
00813   * @param  DAC_Channel This parameter can be one of the following values:
00814   *         @arg @ref LL_DAC_CHANNEL_1
00815   *         @arg @ref LL_DAC_CHANNEL_2
00816   * @retval None
00817   */
00818 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00819 {
00820   CLEAR_BIT(DACx->CR,
00821             DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00822 }
00823
00824 /**
00825   * @brief  Get DAC DMA transfer request state of the selected channel.
00826   *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
00827   * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
00828   *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
00829   * @param  DACx DAC instance
00830   * @param  DAC_Channel This parameter can be one of the following values:
00831   *         @arg @ref LL_DAC_CHANNEL_1
00832   *         @arg @ref LL_DAC_CHANNEL_2
00833   * @retval State of bit (1 or 0).
00834   */
00835 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00836 {
00837   return (READ_BIT(DACx->CR,
00838                    DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00839           == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
00840 }
00841
00842 /**
00843   * @brief  Function to help to configure DMA transfer to DAC: retrieve the
00844   *         DAC register address from DAC instance and a list of DAC registers
00845   *         intended to be used (most commonly) with DMA transfer.
00846   * @note   These DAC registers are data holding registers:
00847   *         when DAC conversion is requested, DAC generates a DMA transfer
00848   *         request to have data available in DAC data holding registers.
00849   * @note   This macro is intended to be used with LL DMA driver, refer to
00850   *         function "LL_DMA_ConfigAddresses()".
00851   *         Example:
00852   *           LL_DMA_ConfigAddresses(DMA1,
00853   *                                  LL_DMA_CHANNEL_1,
00854   *                                  (uint32_t)&< array or variable >,
00855   *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
00856   *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
00857   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
00858   *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
00859   *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
00860   *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
00861   *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
00862   *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
00863   * @param  DACx DAC instance
00864   * @param  DAC_Channel This parameter can be one of the following values:
00865   *         @arg @ref LL_DAC_CHANNEL_1
00866   *         @arg @ref LL_DAC_CHANNEL_2
00867   * @param  Register This parameter can be one of the following values:
00868   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
00869   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
00870   *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
00871   * @retval DAC register address
00872   */
00873 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
00874 {
00875   /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
00876   /* DAC channel selected.                                                    */
00877   return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
00878 }
00879 /**
00880   * @}
00881   */
00882
00883 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
00884   * @{
00885   */
00886
00887 /**
00888   * @brief  Enable DAC selected channel.
00889   * @rmtoll CR       EN1            LL_DAC_Enable\n
00890   *         CR       EN2            LL_DAC_Enable
00891   * @note   After enable from off state, DAC channel requires a delay
00892   *         for output voltage to reach accuracy +/- 1 LSB.
00893   *         Refer to device datasheet, parameter "tWAKEUP".
00894   * @param  DACx DAC instance
00895   * @param  DAC_Channel This parameter can be one of the following values:
00896   *         @arg @ref LL_DAC_CHANNEL_1
00897   *         @arg @ref LL_DAC_CHANNEL_2
00898   * @retval None
00899   */
00900 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00901 {
00902   SET_BIT(DACx->CR,
00903           DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00904 }
00905
00906 /**
00907   * @brief  Disable DAC selected channel.
00908   * @rmtoll CR       EN1            LL_DAC_Disable\n
00909   *         CR       EN2            LL_DAC_Disable
00910   * @param  DACx DAC instance
00911   * @param  DAC_Channel This parameter can be one of the following values:
00912   *         @arg @ref LL_DAC_CHANNEL_1
00913   *         @arg @ref LL_DAC_CHANNEL_2
00914   * @retval None
00915   */
00916 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00917 {
00918   CLEAR_BIT(DACx->CR,
00919             DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00920 }
00921
00922 /**
00923   * @brief  Get DAC enable state of the selected channel.
00924   *         (0: DAC channel is disabled, 1: DAC channel is enabled)
00925   * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
00926   *         CR       EN2            LL_DAC_IsEnabled
00927   * @param  DACx DAC instance
00928   * @param  DAC_Channel This parameter can be one of the following values:
00929   *         @arg @ref LL_DAC_CHANNEL_1
00930   *         @arg @ref LL_DAC_CHANNEL_2
00931   * @retval State of bit (1 or 0).
00932   */
00933 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00934 {
00935   return (READ_BIT(DACx->CR,
00936                    DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00937           == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
00938 }
00939
00940 /**
00941   * @brief  Enable DAC trigger of the selected channel.
00942   * @note   - If DAC trigger is disabled, DAC conversion is performed
00943   *           automatically once the data holding register is updated,
00944   *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
00945   *           @ref LL_DAC_ConvertData12RightAligned(), ...
00946   *         - If DAC trigger is enabled, DAC conversion is performed
00947   *           only when a hardware of software trigger event is occurring.
00948   *           Select trigger source using
00949   *           function @ref LL_DAC_SetTriggerSource().
00950   * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
00951   *         CR       TEN2           LL_DAC_EnableTrigger
00952   * @param  DACx DAC instance
00953   * @param  DAC_Channel This parameter can be one of the following values:
00954   *         @arg @ref LL_DAC_CHANNEL_1
00955   *         @arg @ref LL_DAC_CHANNEL_2
00956   * @retval None
00957   */
00958 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00959 {
00960   SET_BIT(DACx->CR,
00961           DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00962 }
00963
00964 /**
00965   * @brief  Disable DAC trigger of the selected channel.
00966   * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
00967   *         CR       TEN2           LL_DAC_DisableTrigger
00968   * @param  DACx DAC instance
00969   * @param  DAC_Channel This parameter can be one of the following values:
00970   *         @arg @ref LL_DAC_CHANNEL_1
00971   *         @arg @ref LL_DAC_CHANNEL_2
00972   * @retval None
00973   */
00974 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00975 {
00976   CLEAR_BIT(DACx->CR,
00977             DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
00978 }
00979
00980 /**
00981   * @brief  Get DAC trigger state of the selected channel.
00982   *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
00983   * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
00984   *         CR       TEN2           LL_DAC_IsTriggerEnabled
00985   * @param  DACx DAC instance
00986   * @param  DAC_Channel This parameter can be one of the following values:
00987   *         @arg @ref LL_DAC_CHANNEL_1
00988   *         @arg @ref LL_DAC_CHANNEL_2
00989   * @retval State of bit (1 or 0).
00990   */
00991 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
00992 {
00993   return (READ_BIT(DACx->CR,
00994                    DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
00995           == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
00996 }
00997
00998 /**
00999   * @brief  Trig DAC conversion by software for the selected DAC channel.
01000   * @note   Preliminarily, DAC trigger must be set to software trigger
01001   *         using function @ref LL_DAC_SetTriggerSource()
01002   *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
01003   *         and DAC trigger must be enabled using
01004   *         function @ref LL_DAC_EnableTrigger().
01005   * @note   For devices featuring DAC with 2 channels: this function
01006   *         can perform a SW start of both DAC channels simultaneously.
01007   *         Two channels can be selected as parameter.
01008   *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
01009   * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
01010   *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
01011   * @param  DACx DAC instance
01012   * @param  DAC_Channel  This parameter can a combination of the following values:
01013   *         @arg @ref LL_DAC_CHANNEL_1
01014   *         @arg @ref LL_DAC_CHANNEL_2
01015   * @retval None
01016   */
01017 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01018 {
01019   SET_BIT(DACx->SWTRIGR,
01020           (DAC_Channel & DAC_SWTR_CHX_MASK));
01021 }
01022
01023 /**
01024   * @brief  Set the data to be loaded in the data holding register
01025   *         in format 12 bits left alignment (LSB aligned on bit 0),
01026   *         for the selected DAC channel.
01027   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
01028   *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
01029   * @param  DACx DAC instance
01030   * @param  DAC_Channel This parameter can be one of the following values:
01031   *         @arg @ref LL_DAC_CHANNEL_1
01032   *         @arg @ref LL_DAC_CHANNEL_2
01033   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01034   * @retval None
01035   */
01036 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01037 {
01038   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
01039
01040   MODIFY_REG(*preg,
01041              DAC_DHR12R1_DACC1DHR,
01042              Data);
01043 }
01044
01045 /**
01046   * @brief  Set the data to be loaded in the data holding register
01047   *         in format 12 bits left alignment (MSB aligned on bit 15),
01048   *         for the selected DAC channel.
01049   * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
01050   *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
01051   * @param  DACx DAC instance
01052   * @param  DAC_Channel This parameter can be one of the following values:
01053   *         @arg @ref LL_DAC_CHANNEL_1
01054   *         @arg @ref LL_DAC_CHANNEL_2
01055   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
01056   * @retval None
01057   */
01058 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01059 {
01060   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
01061
01062   MODIFY_REG(*preg,
01063              DAC_DHR12L1_DACC1DHR,
01064              Data);
01065 }
01066
01067 /**
01068   * @brief  Set the data to be loaded in the data holding register
01069   *         in format 8 bits left alignment (LSB aligned on bit 0),
01070   *         for the selected DAC channel.
01071   * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
01072   *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
01073   * @param  DACx DAC instance
01074   * @param  DAC_Channel This parameter can be one of the following values:
01075   *         @arg @ref LL_DAC_CHANNEL_1
01076   *         @arg @ref LL_DAC_CHANNEL_2
01077   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
01078   * @retval None
01079   */
01080 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
01081 {
01082   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
01083
01084   MODIFY_REG(*preg,
01085              DAC_DHR8R1_DACC1DHR,
01086              Data);
01087 }
01088
01089 /**
01090   * @brief  Set the data to be loaded in the data holding register
01091   *         in format 12 bits left alignment (LSB aligned on bit 0),
01092   *         for both DAC channels.
01093   * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
01094   *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
01095   * @param  DACx DAC instance
01096   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01097   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01098   * @retval None
01099   */
01100 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01101 {
01102   MODIFY_REG(DACx->DHR12RD,
01103              (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
01104              ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01105 }
01106
01107 /**
01108   * @brief  Set the data to be loaded in the data holding register
01109   *         in format 12 bits left alignment (MSB aligned on bit 15),
01110   *         for both DAC channels.
01111   * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
01112   *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
01113   * @param  DACx DAC instance
01114   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
01115   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
01116   * @retval None
01117   */
01118 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01119 {
01120   /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
01121   /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
01122   /*       the 4 LSB must be taken into account for the shift value.          */
01123   MODIFY_REG(DACx->DHR12LD,
01124              (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
01125              ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
01126 }
01127
01128 /**
01129   * @brief  Set the data to be loaded in the data holding register
01130   *         in format 8 bits left alignment (LSB aligned on bit 0),
01131   *         for both DAC channels.
01132   * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
01133   *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
01134   * @param  DACx DAC instance
01135   * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
01136   * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
01137   * @retval None
01138   */
01139 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
01140 {
01141   MODIFY_REG(DACx->DHR8RD,
01142              (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
01143              ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
01144 }
01145
01146 /**
01147   * @brief  Retrieve output data currently generated for the selected DAC channel.
01148   * @note   Whatever alignment and resolution settings
01149   *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
01150   *         @ref LL_DAC_ConvertData12RightAligned(), ...),
01151   *         output data format is 12 bits right aligned (LSB aligned on bit 0).
01152   * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
01153   *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
01154   * @param  DACx DAC instance
01155   * @param  DAC_Channel This parameter can be one of the following values:
01156   *         @arg @ref LL_DAC_CHANNEL_1
01157   *         @arg @ref LL_DAC_CHANNEL_2
01158   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
01159   */
01160 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
01161 {
01162   register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
01163
01164   return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
01165 }
01166
01167 /**
01168   * @}
01169   */
01170
01171 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
01172   * @{
01173   */
01174 #if defined(DAC_SR_DMAUDR1)
01175 /**
01176   * @brief  Get DAC underrun flag for DAC channel 1
01177   * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
01178   * @param  DACx DAC instance
01179   * @retval State of bit (1 or 0).
01180   */
01181 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
01182 {
01183   return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
01184 }
01185 #endif /* DAC_SR_DMAUDR1 */
01186
01187 #if defined(DAC_SR_DMAUDR2)
01188 /**
01189   * @brief  Get DAC underrun flag for DAC channel 2
01190   * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
01191   * @param  DACx DAC instance
01192   * @retval State of bit (1 or 0).
01193   */
01194 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
01195 {
01196   return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
01197 }
01198 #endif /* DAC_SR_DMAUDR2 */
01199
01200 #if defined(DAC_SR_DMAUDR1)
01201 /**
01202   * @brief  Clear DAC underrun flag for DAC channel 1
01203   * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
01204   * @param  DACx DAC instance
01205   * @retval None
01206   */
01207 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
01208 {
01209   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
01210 }
01211 #endif /* DAC_SR_DMAUDR1 */
01212
01213 #if defined(DAC_SR_DMAUDR2)
01214 /**
01215   * @brief  Clear DAC underrun flag for DAC channel 2
01216   * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
01217   * @param  DACx DAC instance
01218   * @retval None
01219   */
01220 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
01221 {
01222   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
01223 }
01224 #endif /* DAC_SR_DMAUDR2 */
01225
01226 /**
01227   * @}
01228   */
01229 /** @defgroup DAC_LL_EF_IT_Management IT management
01230   * @{
01231   */
01232
01233 #if defined(DAC_CR_DMAUDRIE1)
01234 /**
01235   * @brief  Enable DMA underrun interrupt for DAC channel 1
01236   * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
01237   * @param  DACx DAC instance
01238   * @retval None
01239   */
01240 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
01241 {
01242   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01243 }
01244 #endif /* DAC_CR_DMAUDRIE1 */
01245
01246 #if defined(DAC_CR_DMAUDRIE2)
01247 /**
01248   * @brief  Enable DMA underrun interrupt for DAC channel 2
01249   * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
01250   * @param  DACx DAC instance
01251   * @retval None
01252   */
01253 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
01254 {
01255   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01256 }
01257 #endif /* DAC_CR_DMAUDRIE2 */
01258
01259 #if defined(DAC_CR_DMAUDRIE1)
01260 /**
01261   * @brief  Disable DMA underrun interrupt for DAC channel 1
01262   * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
01263   * @param  DACx DAC instance
01264   * @retval None
01265   */
01266 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
01267 {
01268   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
01269 }
01270 #endif /* DAC_CR_DMAUDRIE1 */
01271
01272 #if defined(DAC_CR_DMAUDRIE2)
01273 /**
01274   * @brief  Disable DMA underrun interrupt for DAC channel 2
01275   * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
01276   * @param  DACx DAC instance
01277   * @retval None
01278   */
01279 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
01280 {
01281   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
01282 }
01283 #endif /* DAC_CR_DMAUDRIE2 */
01284
01285 #if defined(DAC_CR_DMAUDRIE1)
01286 /**
01287   * @brief  Get DMA underrun interrupt for DAC channel 1
01288   * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
01289   * @param  DACx DAC instance
01290   * @retval State of bit (1 or 0).
01291   */
01292 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
01293 {
01294   return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
01295 }
01296 #endif /* DAC_CR_DMAUDRIE1 */
01297
01298 #if defined(DAC_CR_DMAUDRIE2)
01299 /**
01300   * @brief  Get DMA underrun interrupt for DAC channel 2
01301   * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
01302   * @param  DACx DAC instance
01303   * @retval State of bit (1 or 0).
01304   */
01305 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
01306 {
01307   return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
01308 }
01309 #endif /* DAC_CR_DMAUDRIE2 */
01310
01311 /**
01312   * @}
01313   */
01314
01315 #if defined(USE_FULL_LL_DRIVER)
01316 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
01317   * @{
01318   */
01319
01320 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
01321 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
01322 void        LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
01323
01324 /**
01325   * @}
01326   */
01327 #endif /* USE_FULL_LL_DRIVER */
01328
01329 /**
01330   * @}
01331   */
01332
01333 /**
01334   * @}
01335   */
01336
01337 #endif /* DAC */
01338
01339 /**
01340   * @}
01341   */
01342
01343 #ifdef __cplusplus
01344 }
01345 #endif
01346
01347 #endif /* __STM32F1xx_LL_DAC_H */
01348
01349 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_dma.c Source File

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stm32f1xx_ll_dma.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_dma.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   DMA LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_dma.h"
00041 #include "stm32f1xx_ll_bus.h"
00042 #ifdef  USE_FULL_ASSERT
00043 #include "stm32_assert.h"
00044 #else
00045 #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32F1xx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined (DMA1) || defined (DMA2)
00053
00054 /** @defgroup DMA_LL DMA
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062 /** @addtogroup DMA_LL_Private_Macros
00063   * @{
00064   */
00065 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
00066                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
00067                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
00068
00069 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
00070                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
00071
00072 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
00073                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
00074
00075 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
00076                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
00077
00078 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
00079                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
00080                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
00081
00082 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
00083                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
00084                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
00085
00086 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
00087
00088 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
00089                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
00090                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
00091                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
00092
00093 #if defined (DMA2)
00094 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00095                                                             (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00096                                                              ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00097                                                              ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00098                                                              ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00099                                                              ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00100                                                              ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00101                                                              ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
00102                                                             (((INSTANCE) == DMA2) && \
00103                                                             (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00104                                                              ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00105                                                              ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00106                                                              ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00107                                                              ((CHANNEL) == LL_DMA_CHANNEL_5))))
00108 #else
00109 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
00110                                                             (((CHANNEL) == LL_DMA_CHANNEL_1) || \
00111                                                              ((CHANNEL) == LL_DMA_CHANNEL_2) || \
00112                                                              ((CHANNEL) == LL_DMA_CHANNEL_3) || \
00113                                                              ((CHANNEL) == LL_DMA_CHANNEL_4) || \
00114                                                              ((CHANNEL) == LL_DMA_CHANNEL_5) || \
00115                                                              ((CHANNEL) == LL_DMA_CHANNEL_6) || \
00116                                                              ((CHANNEL) == LL_DMA_CHANNEL_7))))
00117 #endif
00118 /**
00119   * @}
00120   */
00121
00122 /* Private function prototypes -----------------------------------------------*/
00123 /* Exported functions --------------------------------------------------------*/
00124 /** @addtogroup DMA_LL_Exported_Functions
00125   * @{
00126   */
00127
00128 /** @addtogroup DMA_LL_EF_Init
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  De-initialize the DMA registers to their default reset values.
00134   * @param  DMAx DMAx Instance
00135   * @param  Channel This parameter can be one of the following values:
00136   *         @arg @ref LL_DMA_CHANNEL_1
00137   *         @arg @ref LL_DMA_CHANNEL_2
00138   *         @arg @ref LL_DMA_CHANNEL_3
00139   *         @arg @ref LL_DMA_CHANNEL_4
00140   *         @arg @ref LL_DMA_CHANNEL_5
00141   *         @arg @ref LL_DMA_CHANNEL_6
00142   *         @arg @ref LL_DMA_CHANNEL_7
00143   * @retval An ErrorStatus enumeration value:
00144   *          - SUCCESS: DMA registers are de-initialized
00145   *          - ERROR: DMA registers are not de-initialized
00146   */
00147 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
00148 {
00149   DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
00150   ErrorStatus status = SUCCESS;
00151
00152   /* Check the DMA Instance DMAx and Channel parameters*/
00153   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
00154
00155   tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
00156
00157   /* Disable the selected DMAx_Channely */
00158   CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
00159
00160   /* Reset DMAx_Channely control register */
00161   LL_DMA_WriteReg(tmp, CCR, 0U);
00162
00163   /* Reset DMAx_Channely remaining bytes register */
00164   LL_DMA_WriteReg(tmp, CNDTR, 0U);
00165
00166   /* Reset DMAx_Channely peripheral address register */
00167   LL_DMA_WriteReg(tmp, CPAR, 0U);
00168
00169   /* Reset DMAx_Channely memory address register */
00170   LL_DMA_WriteReg(tmp, CMAR, 0U);
00171
00172   if (Channel == LL_DMA_CHANNEL_1)
00173   {
00174     /* Reset interrupt pending bits for DMAx Channel1 */
00175     LL_DMA_ClearFlag_GI1(DMAx);
00176   }
00177   else if (Channel == LL_DMA_CHANNEL_2)
00178   {
00179     /* Reset interrupt pending bits for DMAx Channel2 */
00180     LL_DMA_ClearFlag_GI2(DMAx);
00181   }
00182   else if (Channel == LL_DMA_CHANNEL_3)
00183   {
00184     /* Reset interrupt pending bits for DMAx Channel3 */
00185     LL_DMA_ClearFlag_GI3(DMAx);
00186   }
00187   else if (Channel == LL_DMA_CHANNEL_4)
00188   {
00189     /* Reset interrupt pending bits for DMAx Channel4 */
00190     LL_DMA_ClearFlag_GI4(DMAx);
00191   }
00192   else if (Channel == LL_DMA_CHANNEL_5)
00193   {
00194     /* Reset interrupt pending bits for DMAx Channel5 */
00195     LL_DMA_ClearFlag_GI5(DMAx);
00196   }
00197
00198   else if (Channel == LL_DMA_CHANNEL_6)
00199   {
00200     /* Reset interrupt pending bits for DMAx Channel6 */
00201     LL_DMA_ClearFlag_GI6(DMAx);
00202   }
00203   else if (Channel == LL_DMA_CHANNEL_7)
00204   {
00205     /* Reset interrupt pending bits for DMAx Channel7 */
00206     LL_DMA_ClearFlag_GI7(DMAx);
00207   }
00208   else
00209   {
00210     status = ERROR;
00211   }
00212
00213   return status;
00214 }
00215
00216 /**
00217   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
00218   * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
00219   *         @arg @ref __LL_DMA_GET_INSTANCE
00220   *         @arg @ref __LL_DMA_GET_CHANNEL
00221   * @param  DMAx DMAx Instance
00222   * @param  Channel This parameter can be one of the following values:
00223   *         @arg @ref LL_DMA_CHANNEL_1
00224   *         @arg @ref LL_DMA_CHANNEL_2
00225   *         @arg @ref LL_DMA_CHANNEL_3
00226   *         @arg @ref LL_DMA_CHANNEL_4
00227   *         @arg @ref LL_DMA_CHANNEL_5
00228   *         @arg @ref LL_DMA_CHANNEL_6
00229   *         @arg @ref LL_DMA_CHANNEL_7
00230   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
00231   * @retval An ErrorStatus enumeration value:
00232   *          - SUCCESS: DMA registers are initialized
00233   *          - ERROR: Not applicable
00234   */
00235 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
00236 {
00237   /* Check the DMA Instance DMAx and Channel parameters*/
00238   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
00239
00240   /* Check the DMA parameters from DMA_InitStruct */
00241   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
00242   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
00243   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
00244   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
00245   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
00246   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
00247   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
00248   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
00249
00250   /*---------------------------- DMAx CCR Configuration ------------------------
00251    * Configure DMAx_Channely: data transfer direction, data transfer mode,
00252    *                          peripheral and memory increment mode,
00253    *                          data size alignment and  priority level with parameters :
00254    * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
00255    * - Mode:           DMA_CCR_CIRC bit
00256    * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
00257    * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
00258    * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
00259    * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
00260    * - Priority:               DMA_CCR_PL[1:0] bits
00261    */
00262   LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
00263                         DMA_InitStruct->Mode                   | \
00264                         DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
00265                         DMA_InitStruct->MemoryOrM2MDstIncMode  | \
00266                         DMA_InitStruct->PeriphOrM2MSrcDataSize | \
00267                         DMA_InitStruct->MemoryOrM2MDstDataSize | \
00268                         DMA_InitStruct->Priority);
00269
00270   /*-------------------------- DMAx CMAR Configuration -------------------------
00271    * Configure the memory or destination base address with parameter :
00272    * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
00273    */
00274   LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
00275
00276   /*-------------------------- DMAx CPAR Configuration -------------------------
00277    * Configure the peripheral or source base address with parameter :
00278    * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
00279    */
00280   LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
00281
00282   /*--------------------------- DMAx CNDTR Configuration -----------------------
00283    * Configure the peripheral base address with parameter :
00284    * - NbData: DMA_CNDTR_NDT[15:0] bits
00285    */
00286   LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
00287
00288   return SUCCESS;
00289 }
00290
00291 /**
00292   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
00293   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
00294   * @retval None
00295   */
00296 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
00297 {
00298   /* Set DMA_InitStruct fields to default values */
00299   DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
00300   DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
00301   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
00302   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
00303   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
00304   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
00305   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
00306   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
00307   DMA_InitStruct->NbData                 = 0x00000000U;
00308   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
00309 }
00310
00311 /**
00312   * @}
00313   */
00314
00315 /**
00316   * @}
00317   */
00318
00319 /**
00320   * @}
00321   */
00322
00323 #endif /* DMA1 || DMA2 */
00324
00325 /**
00326   * @}
00327   */
00328
00329 #endif /* USE_FULL_LL_DRIVER */
00330
00331 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_dma.h Source File

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stm32f1xx_ll_dma.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_dma.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of DMA LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_DMA_H
00040 #define __STM32F1xx_LL_DMA_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (DMA1) || defined (DMA2)
00054
00055 /** @defgroup DMA_LL DMA
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
00062   * @{
00063   */
00064 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
00065 static const uint8_t CHANNEL_OFFSET_TAB[] =
00066 {
00067   (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
00068   (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
00069   (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
00070   (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
00071   (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
00072   (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
00073   (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
00074 };
00075 /**
00076   * @}
00077   */
00078 /* Private constants ---------------------------------------------------------*/
00079 /* Private macros ------------------------------------------------------------*/
00080 #if defined(USE_FULL_LL_DRIVER)
00081 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
00082   * @{
00083   */
00084 /**
00085   * @}
00086   */
00087 #endif /*USE_FULL_LL_DRIVER*/
00088
00089 /* Exported types ------------------------------------------------------------*/
00090 #if defined(USE_FULL_LL_DRIVER)
00091 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
00092   * @{
00093   */
00094 typedef struct
00095 {
00096   uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
00097                                         or as Source base address in case of memory to memory transfer direction.
00098
00099                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00100
00101   uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
00102                                         or as Destination base address in case of memory to memory transfer direction.
00103
00104                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
00105
00106   uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
00107                                         from memory to memory or from peripheral to memory.
00108                                         This parameter can be a value of @ref DMA_LL_EC_DIRECTION
00109
00110                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
00111
00112   uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
00113                                         This parameter can be a value of @ref DMA_LL_EC_MODE
00114                                         @note: The circular buffer mode cannot be used if the memory to memory
00115                                                data transfer direction is configured on the selected Channel
00116
00117                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
00118
00119   uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
00120                                         is incremented or not.
00121                                         This parameter can be a value of @ref DMA_LL_EC_PERIPH
00122
00123                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
00124
00125   uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
00126                                         is incremented or not.
00127                                         This parameter can be a value of @ref DMA_LL_EC_MEMORY
00128
00129                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
00130
00131   uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
00132                                         in case of memory to memory transfer direction.
00133                                         This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
00134
00135                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
00136
00137   uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
00138                                         in case of memory to memory transfer direction.
00139                                         This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
00140
00141                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
00142
00143   uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
00144                                         The data unit is equal to the source buffer configuration set in PeripheralSize
00145                                         or MemorySize parameters depending in the transfer direction.
00146                                         This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
00147
00148                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
00149
00150   uint32_t Priority;               /*!< Specifies the channel priority level.
00151                                         This parameter can be a value of @ref DMA_LL_EC_PRIORITY
00152
00153                                         This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
00154
00155 } LL_DMA_InitTypeDef;
00156 /**
00157   * @}
00158   */
00159 #endif /*USE_FULL_LL_DRIVER*/
00160
00161 /* Exported constants --------------------------------------------------------*/
00162 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
00163   * @{
00164   */
00165 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
00166   * @brief    Flags defines which can be used with LL_DMA_WriteReg function
00167   * @{
00168   */
00169 #define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */
00170 #define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */
00171 #define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */
00172 #define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */
00173 #define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */
00174 #define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */
00175 #define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */
00176 #define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */
00177 #define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */
00178 #define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */
00179 #define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */
00180 #define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */
00181 #define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */
00182 #define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */
00183 #define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */
00184 #define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */
00185 #define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */
00186 #define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */
00187 #define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */
00188 #define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */
00189 #define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */
00190 #define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */
00191 #define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */
00192 #define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */
00193 #define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */
00194 #define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */
00195 #define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */
00196 #define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
00202   * @brief    Flags defines which can be used with LL_DMA_ReadReg function
00203   * @{
00204   */
00205 #define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */
00206 #define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */
00207 #define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */
00208 #define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */
00209 #define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */
00210 #define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */
00211 #define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */
00212 #define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */
00213 #define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */
00214 #define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */
00215 #define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */
00216 #define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */
00217 #define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */
00218 #define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */
00219 #define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */
00220 #define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */
00221 #define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */
00222 #define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */
00223 #define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */
00224 #define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */
00225 #define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */
00226 #define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */
00227 #define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */
00228 #define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */
00229 #define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */
00230 #define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */
00231 #define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */
00232 #define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */
00233 /**
00234   * @}
00235   */
00236
00237 /** @defgroup DMA_LL_EC_IT IT Defines
00238   * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions
00239   * @{
00240   */
00241 #define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */
00242 #define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */
00243 #define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */
00244 /**
00245   * @}
00246   */
00247
00248 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
00249   * @{
00250   */
00251 #define LL_DMA_CHANNEL_1                  0x00000001U           /*!< DMA Channel 1 */
00252 #define LL_DMA_CHANNEL_2                  0x00000002U           /*!< DMA Channel 2 */
00253 #define LL_DMA_CHANNEL_3                  0x00000003U           /*!< DMA Channel 3 */
00254 #define LL_DMA_CHANNEL_4                  0x00000004U           /*!< DMA Channel 4 */
00255 #define LL_DMA_CHANNEL_5                  0x00000005U           /*!< DMA Channel 5 */
00256 #define LL_DMA_CHANNEL_6                  0x00000006U           /*!< DMA Channel 6 */
00257 #define LL_DMA_CHANNEL_7                  0x00000007U           /*!< DMA Channel 7 */
00258 #if defined(USE_FULL_LL_DRIVER)
00259 #define LL_DMA_CHANNEL_ALL                0xFFFF0000U           /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
00260 #endif /*USE_FULL_LL_DRIVER*/
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
00266   * @{
00267   */
00268 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
00269 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
00270 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
00271 /**
00272   * @}
00273   */
00274
00275 /** @defgroup DMA_LL_EC_MODE Transfer mode
00276   * @{
00277   */
00278 #define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
00279 #define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
00280 /**
00281   * @}
00282   */
00283
00284 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
00285   * @{
00286   */
00287 #define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
00288 #define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
00289 /**
00290   * @}
00291   */
00292
00293 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
00294   * @{
00295   */
00296 #define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
00297 #define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
00298 /**
00299   * @}
00300   */
00301
00302 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
00303   * @{
00304   */
00305 #define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
00306 #define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
00307 #define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
00308 /**
00309   * @}
00310   */
00311
00312 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
00313   * @{
00314   */
00315 #define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
00316 #define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
00317 #define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
00318 /**
00319   * @}
00320   */
00321
00322 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
00323   * @{
00324   */
00325 #define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
00326 #define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
00327 #define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
00328 #define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
00329 /**
00330   * @}
00331   */
00332
00333 /**
00334   * @}
00335   */
00336
00337 /* Exported macro ------------------------------------------------------------*/
00338 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
00339   * @{
00340   */
00341
00342 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
00343   * @{
00344   */
00345 /**
00346   * @brief  Write a value in DMA register
00347   * @param  __INSTANCE__ DMA Instance
00348   * @param  __REG__ Register to be written
00349   * @param  __VALUE__ Value to be written in the register
00350   * @retval None
00351   */
00352 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00353
00354 /**
00355   * @brief  Read a value in DMA register
00356   * @param  __INSTANCE__ DMA Instance
00357   * @param  __REG__ Register to be read
00358   * @retval Register value
00359   */
00360 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00361 /**
00362   * @}
00363   */
00364
00365 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
00366   * @{
00367   */
00368
00369 /**
00370   * @brief  Convert DMAx_Channely into DMAx
00371   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00372   * @retval DMAx
00373   */
00374 #if defined(DMA2)
00375 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \
00376 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ?  DMA2 : DMA1)
00377 #else
00378 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)
00379 #endif
00380
00381 /**
00382   * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y
00383   * @param  __CHANNEL_INSTANCE__ DMAx_Channely
00384   * @retval LL_DMA_CHANNEL_y
00385   */
00386 #if defined (DMA2)
00387 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00388 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00389  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
00390  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00391  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
00392  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00393  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
00394  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00395  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
00396  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00397  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
00398  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00399  LL_DMA_CHANNEL_7)
00400 #else
00401 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \
00402 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
00403  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
00404  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
00405  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
00406  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
00407  ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
00408  LL_DMA_CHANNEL_7)
00409 #endif
00410
00411 /**
00412   * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
00413   * @param  __DMA_INSTANCE__ DMAx
00414   * @param  __CHANNEL__ LL_DMA_CHANNEL_y
00415   * @retval DMAx_Channely
00416   */
00417 #if defined (DMA2)
00418 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00419 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00420  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
00421  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00422  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
00423  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00424  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
00425  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00426  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
00427  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00428  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
00429  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00430  DMA1_Channel7)
00431 #else
00432 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \
00433 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
00434  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
00435  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
00436  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
00437  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
00438  (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
00439  DMA1_Channel7)
00440 #endif
00441
00442 /**
00443   * @}
00444   */
00445
00446 /**
00447   * @}
00448   */
00449
00450 /* Exported functions --------------------------------------------------------*/
00451 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
00452  * @{
00453  */
00454
00455 /** @defgroup DMA_LL_EF_Configuration Configuration
00456   * @{
00457   */
00458 /**
00459   * @brief  Enable DMA channel.
00460   * @rmtoll CCR          EN            LL_DMA_EnableChannel
00461   * @param  DMAx DMAx Instance
00462   * @param  Channel This parameter can be one of the following values:
00463   *         @arg @ref LL_DMA_CHANNEL_1
00464   *         @arg @ref LL_DMA_CHANNEL_2
00465   *         @arg @ref LL_DMA_CHANNEL_3
00466   *         @arg @ref LL_DMA_CHANNEL_4
00467   *         @arg @ref LL_DMA_CHANNEL_5
00468   *         @arg @ref LL_DMA_CHANNEL_6
00469   *         @arg @ref LL_DMA_CHANNEL_7
00470   * @retval None
00471   */
00472 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00473 {
00474   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
00475 }
00476
00477 /**
00478   * @brief  Disable DMA channel.
00479   * @rmtoll CCR          EN            LL_DMA_DisableChannel
00480   * @param  DMAx DMAx Instance
00481   * @param  Channel This parameter can be one of the following values:
00482   *         @arg @ref LL_DMA_CHANNEL_1
00483   *         @arg @ref LL_DMA_CHANNEL_2
00484   *         @arg @ref LL_DMA_CHANNEL_3
00485   *         @arg @ref LL_DMA_CHANNEL_4
00486   *         @arg @ref LL_DMA_CHANNEL_5
00487   *         @arg @ref LL_DMA_CHANNEL_6
00488   *         @arg @ref LL_DMA_CHANNEL_7
00489   * @retval None
00490   */
00491 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00492 {
00493   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
00494 }
00495
00496 /**
00497   * @brief  Check if DMA channel is enabled or disabled.
00498   * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel
00499   * @param  DMAx DMAx Instance
00500   * @param  Channel This parameter can be one of the following values:
00501   *         @arg @ref LL_DMA_CHANNEL_1
00502   *         @arg @ref LL_DMA_CHANNEL_2
00503   *         @arg @ref LL_DMA_CHANNEL_3
00504   *         @arg @ref LL_DMA_CHANNEL_4
00505   *         @arg @ref LL_DMA_CHANNEL_5
00506   *         @arg @ref LL_DMA_CHANNEL_6
00507   *         @arg @ref LL_DMA_CHANNEL_7
00508   * @retval State of bit (1 or 0).
00509   */
00510 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
00511 {
00512   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00513                    DMA_CCR_EN) == (DMA_CCR_EN));
00514 }
00515
00516 /**
00517   * @brief  Configure all parameters link to DMA transfer.
00518   * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\n
00519   *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\n
00520   *         CCR          CIRC          LL_DMA_ConfigTransfer\n
00521   *         CCR          PINC          LL_DMA_ConfigTransfer\n
00522   *         CCR          MINC          LL_DMA_ConfigTransfer\n
00523   *         CCR          PSIZE         LL_DMA_ConfigTransfer\n
00524   *         CCR          MSIZE         LL_DMA_ConfigTransfer\n
00525   *         CCR          PL            LL_DMA_ConfigTransfer
00526   * @param  DMAx DMAx Instance
00527   * @param  Channel This parameter can be one of the following values:
00528   *         @arg @ref LL_DMA_CHANNEL_1
00529   *         @arg @ref LL_DMA_CHANNEL_2
00530   *         @arg @ref LL_DMA_CHANNEL_3
00531   *         @arg @ref LL_DMA_CHANNEL_4
00532   *         @arg @ref LL_DMA_CHANNEL_5
00533   *         @arg @ref LL_DMA_CHANNEL_6
00534   *         @arg @ref LL_DMA_CHANNEL_7
00535   * @param  Configuration This parameter must be a combination of all the following values:
00536   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00537   *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
00538   *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
00539   *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
00540   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
00541   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
00542   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
00543   * @retval None
00544   */
00545 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
00546 {
00547   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00548              DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
00549              Configuration);
00550 }
00551
00552 /**
00553   * @brief  Set Data transfer direction (read from peripheral or from memory).
00554   * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\n
00555   *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection
00556   * @param  DMAx DMAx Instance
00557   * @param  Channel This parameter can be one of the following values:
00558   *         @arg @ref LL_DMA_CHANNEL_1
00559   *         @arg @ref LL_DMA_CHANNEL_2
00560   *         @arg @ref LL_DMA_CHANNEL_3
00561   *         @arg @ref LL_DMA_CHANNEL_4
00562   *         @arg @ref LL_DMA_CHANNEL_5
00563   *         @arg @ref LL_DMA_CHANNEL_6
00564   *         @arg @ref LL_DMA_CHANNEL_7
00565   * @param  Direction This parameter can be one of the following values:
00566   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00567   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00568   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00569   * @retval None
00570   */
00571 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
00572 {
00573   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00574              DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
00575 }
00576
00577 /**
00578   * @brief  Get Data transfer direction (read from peripheral or from memory).
00579   * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\n
00580   *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection
00581   * @param  DMAx DMAx Instance
00582   * @param  Channel This parameter can be one of the following values:
00583   *         @arg @ref LL_DMA_CHANNEL_1
00584   *         @arg @ref LL_DMA_CHANNEL_2
00585   *         @arg @ref LL_DMA_CHANNEL_3
00586   *         @arg @ref LL_DMA_CHANNEL_4
00587   *         @arg @ref LL_DMA_CHANNEL_5
00588   *         @arg @ref LL_DMA_CHANNEL_6
00589   *         @arg @ref LL_DMA_CHANNEL_7
00590   * @retval Returned value can be one of the following values:
00591   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00592   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00593   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00594   */
00595 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
00596 {
00597   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00598                    DMA_CCR_DIR | DMA_CCR_MEM2MEM));
00599 }
00600
00601 /**
00602   * @brief  Set DMA mode circular or normal.
00603   * @note The circular buffer mode cannot be used if the memory-to-memory
00604   * data transfer is configured on the selected Channel.
00605   * @rmtoll CCR          CIRC          LL_DMA_SetMode
00606   * @param  DMAx DMAx Instance
00607   * @param  Channel This parameter can be one of the following values:
00608   *         @arg @ref LL_DMA_CHANNEL_1
00609   *         @arg @ref LL_DMA_CHANNEL_2
00610   *         @arg @ref LL_DMA_CHANNEL_3
00611   *         @arg @ref LL_DMA_CHANNEL_4
00612   *         @arg @ref LL_DMA_CHANNEL_5
00613   *         @arg @ref LL_DMA_CHANNEL_6
00614   *         @arg @ref LL_DMA_CHANNEL_7
00615   * @param  Mode This parameter can be one of the following values:
00616   *         @arg @ref LL_DMA_MODE_NORMAL
00617   *         @arg @ref LL_DMA_MODE_CIRCULAR
00618   * @retval None
00619   */
00620 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
00621 {
00622   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
00623              Mode);
00624 }
00625
00626 /**
00627   * @brief  Get DMA mode circular or normal.
00628   * @rmtoll CCR          CIRC          LL_DMA_GetMode
00629   * @param  DMAx DMAx Instance
00630   * @param  Channel This parameter can be one of the following values:
00631   *         @arg @ref LL_DMA_CHANNEL_1
00632   *         @arg @ref LL_DMA_CHANNEL_2
00633   *         @arg @ref LL_DMA_CHANNEL_3
00634   *         @arg @ref LL_DMA_CHANNEL_4
00635   *         @arg @ref LL_DMA_CHANNEL_5
00636   *         @arg @ref LL_DMA_CHANNEL_6
00637   *         @arg @ref LL_DMA_CHANNEL_7
00638   * @retval Returned value can be one of the following values:
00639   *         @arg @ref LL_DMA_MODE_NORMAL
00640   *         @arg @ref LL_DMA_MODE_CIRCULAR
00641   */
00642 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
00643 {
00644   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00645                    DMA_CCR_CIRC));
00646 }
00647
00648 /**
00649   * @brief  Set Peripheral increment mode.
00650   * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode
00651   * @param  DMAx DMAx Instance
00652   * @param  Channel This parameter can be one of the following values:
00653   *         @arg @ref LL_DMA_CHANNEL_1
00654   *         @arg @ref LL_DMA_CHANNEL_2
00655   *         @arg @ref LL_DMA_CHANNEL_3
00656   *         @arg @ref LL_DMA_CHANNEL_4
00657   *         @arg @ref LL_DMA_CHANNEL_5
00658   *         @arg @ref LL_DMA_CHANNEL_6
00659   *         @arg @ref LL_DMA_CHANNEL_7
00660   * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:
00661   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00662   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00663   * @retval None
00664   */
00665 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
00666 {
00667   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
00668              PeriphOrM2MSrcIncMode);
00669 }
00670
00671 /**
00672   * @brief  Get Peripheral increment mode.
00673   * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode
00674   * @param  DMAx DMAx Instance
00675   * @param  Channel This parameter can be one of the following values:
00676   *         @arg @ref LL_DMA_CHANNEL_1
00677   *         @arg @ref LL_DMA_CHANNEL_2
00678   *         @arg @ref LL_DMA_CHANNEL_3
00679   *         @arg @ref LL_DMA_CHANNEL_4
00680   *         @arg @ref LL_DMA_CHANNEL_5
00681   *         @arg @ref LL_DMA_CHANNEL_6
00682   *         @arg @ref LL_DMA_CHANNEL_7
00683   * @retval Returned value can be one of the following values:
00684   *         @arg @ref LL_DMA_PERIPH_INCREMENT
00685   *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
00686   */
00687 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00688 {
00689   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00690                    DMA_CCR_PINC));
00691 }
00692
00693 /**
00694   * @brief  Set Memory increment mode.
00695   * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode
00696   * @param  DMAx DMAx Instance
00697   * @param  Channel This parameter can be one of the following values:
00698   *         @arg @ref LL_DMA_CHANNEL_1
00699   *         @arg @ref LL_DMA_CHANNEL_2
00700   *         @arg @ref LL_DMA_CHANNEL_3
00701   *         @arg @ref LL_DMA_CHANNEL_4
00702   *         @arg @ref LL_DMA_CHANNEL_5
00703   *         @arg @ref LL_DMA_CHANNEL_6
00704   *         @arg @ref LL_DMA_CHANNEL_7
00705   * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:
00706   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00707   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00708   * @retval None
00709   */
00710 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
00711 {
00712   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
00713              MemoryOrM2MDstIncMode);
00714 }
00715
00716 /**
00717   * @brief  Get Memory increment mode.
00718   * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode
00719   * @param  DMAx DMAx Instance
00720   * @param  Channel This parameter can be one of the following values:
00721   *         @arg @ref LL_DMA_CHANNEL_1
00722   *         @arg @ref LL_DMA_CHANNEL_2
00723   *         @arg @ref LL_DMA_CHANNEL_3
00724   *         @arg @ref LL_DMA_CHANNEL_4
00725   *         @arg @ref LL_DMA_CHANNEL_5
00726   *         @arg @ref LL_DMA_CHANNEL_6
00727   *         @arg @ref LL_DMA_CHANNEL_7
00728   * @retval Returned value can be one of the following values:
00729   *         @arg @ref LL_DMA_MEMORY_INCREMENT
00730   *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
00731   */
00732 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
00733 {
00734   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00735                    DMA_CCR_MINC));
00736 }
00737
00738 /**
00739   * @brief  Set Peripheral size.
00740   * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize
00741   * @param  DMAx DMAx Instance
00742   * @param  Channel This parameter can be one of the following values:
00743   *         @arg @ref LL_DMA_CHANNEL_1
00744   *         @arg @ref LL_DMA_CHANNEL_2
00745   *         @arg @ref LL_DMA_CHANNEL_3
00746   *         @arg @ref LL_DMA_CHANNEL_4
00747   *         @arg @ref LL_DMA_CHANNEL_5
00748   *         @arg @ref LL_DMA_CHANNEL_6
00749   *         @arg @ref LL_DMA_CHANNEL_7
00750   * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:
00751   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00752   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00753   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00754   * @retval None
00755   */
00756 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
00757 {
00758   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
00759              PeriphOrM2MSrcDataSize);
00760 }
00761
00762 /**
00763   * @brief  Get Peripheral size.
00764   * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize
00765   * @param  DMAx DMAx Instance
00766   * @param  Channel This parameter can be one of the following values:
00767   *         @arg @ref LL_DMA_CHANNEL_1
00768   *         @arg @ref LL_DMA_CHANNEL_2
00769   *         @arg @ref LL_DMA_CHANNEL_3
00770   *         @arg @ref LL_DMA_CHANNEL_4
00771   *         @arg @ref LL_DMA_CHANNEL_5
00772   *         @arg @ref LL_DMA_CHANNEL_6
00773   *         @arg @ref LL_DMA_CHANNEL_7
00774   * @retval Returned value can be one of the following values:
00775   *         @arg @ref LL_DMA_PDATAALIGN_BYTE
00776   *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
00777   *         @arg @ref LL_DMA_PDATAALIGN_WORD
00778   */
00779 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
00780 {
00781   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00782                    DMA_CCR_PSIZE));
00783 }
00784
00785 /**
00786   * @brief  Set Memory size.
00787   * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize
00788   * @param  DMAx DMAx Instance
00789   * @param  Channel This parameter can be one of the following values:
00790   *         @arg @ref LL_DMA_CHANNEL_1
00791   *         @arg @ref LL_DMA_CHANNEL_2
00792   *         @arg @ref LL_DMA_CHANNEL_3
00793   *         @arg @ref LL_DMA_CHANNEL_4
00794   *         @arg @ref LL_DMA_CHANNEL_5
00795   *         @arg @ref LL_DMA_CHANNEL_6
00796   *         @arg @ref LL_DMA_CHANNEL_7
00797   * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:
00798   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00799   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00800   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00801   * @retval None
00802   */
00803 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
00804 {
00805   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
00806              MemoryOrM2MDstDataSize);
00807 }
00808
00809 /**
00810   * @brief  Get Memory size.
00811   * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize
00812   * @param  DMAx DMAx Instance
00813   * @param  Channel This parameter can be one of the following values:
00814   *         @arg @ref LL_DMA_CHANNEL_1
00815   *         @arg @ref LL_DMA_CHANNEL_2
00816   *         @arg @ref LL_DMA_CHANNEL_3
00817   *         @arg @ref LL_DMA_CHANNEL_4
00818   *         @arg @ref LL_DMA_CHANNEL_5
00819   *         @arg @ref LL_DMA_CHANNEL_6
00820   *         @arg @ref LL_DMA_CHANNEL_7
00821   * @retval Returned value can be one of the following values:
00822   *         @arg @ref LL_DMA_MDATAALIGN_BYTE
00823   *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
00824   *         @arg @ref LL_DMA_MDATAALIGN_WORD
00825   */
00826 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
00827 {
00828   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00829                    DMA_CCR_MSIZE));
00830 }
00831
00832 /**
00833   * @brief  Set Channel priority level.
00834   * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel
00835   * @param  DMAx DMAx Instance
00836   * @param  Channel This parameter can be one of the following values:
00837   *         @arg @ref LL_DMA_CHANNEL_1
00838   *         @arg @ref LL_DMA_CHANNEL_2
00839   *         @arg @ref LL_DMA_CHANNEL_3
00840   *         @arg @ref LL_DMA_CHANNEL_4
00841   *         @arg @ref LL_DMA_CHANNEL_5
00842   *         @arg @ref LL_DMA_CHANNEL_6
00843   *         @arg @ref LL_DMA_CHANNEL_7
00844   * @param  Priority This parameter can be one of the following values:
00845   *         @arg @ref LL_DMA_PRIORITY_LOW
00846   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00847   *         @arg @ref LL_DMA_PRIORITY_HIGH
00848   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00849   * @retval None
00850   */
00851 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
00852 {
00853   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
00854              Priority);
00855 }
00856
00857 /**
00858   * @brief  Get Channel priority level.
00859   * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel
00860   * @param  DMAx DMAx Instance
00861   * @param  Channel This parameter can be one of the following values:
00862   *         @arg @ref LL_DMA_CHANNEL_1
00863   *         @arg @ref LL_DMA_CHANNEL_2
00864   *         @arg @ref LL_DMA_CHANNEL_3
00865   *         @arg @ref LL_DMA_CHANNEL_4
00866   *         @arg @ref LL_DMA_CHANNEL_5
00867   *         @arg @ref LL_DMA_CHANNEL_6
00868   *         @arg @ref LL_DMA_CHANNEL_7
00869   * @retval Returned value can be one of the following values:
00870   *         @arg @ref LL_DMA_PRIORITY_LOW
00871   *         @arg @ref LL_DMA_PRIORITY_MEDIUM
00872   *         @arg @ref LL_DMA_PRIORITY_HIGH
00873   *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
00874   */
00875 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
00876 {
00877   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
00878                    DMA_CCR_PL));
00879 }
00880
00881 /**
00882   * @brief  Set Number of data to transfer.
00883   * @note   This action has no effect if
00884   *         channel is enabled.
00885   * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength
00886   * @param  DMAx DMAx Instance
00887   * @param  Channel This parameter can be one of the following values:
00888   *         @arg @ref LL_DMA_CHANNEL_1
00889   *         @arg @ref LL_DMA_CHANNEL_2
00890   *         @arg @ref LL_DMA_CHANNEL_3
00891   *         @arg @ref LL_DMA_CHANNEL_4
00892   *         @arg @ref LL_DMA_CHANNEL_5
00893   *         @arg @ref LL_DMA_CHANNEL_6
00894   *         @arg @ref LL_DMA_CHANNEL_7
00895   * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
00896   * @retval None
00897   */
00898 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
00899 {
00900   MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
00901              DMA_CNDTR_NDT, NbData);
00902 }
00903
00904 /**
00905   * @brief  Get Number of data to transfer.
00906   * @note   Once the channel is enabled, the return value indicate the
00907   *         remaining bytes to be transmitted.
00908   * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength
00909   * @param  DMAx DMAx Instance
00910   * @param  Channel This parameter can be one of the following values:
00911   *         @arg @ref LL_DMA_CHANNEL_1
00912   *         @arg @ref LL_DMA_CHANNEL_2
00913   *         @arg @ref LL_DMA_CHANNEL_3
00914   *         @arg @ref LL_DMA_CHANNEL_4
00915   *         @arg @ref LL_DMA_CHANNEL_5
00916   *         @arg @ref LL_DMA_CHANNEL_6
00917   *         @arg @ref LL_DMA_CHANNEL_7
00918   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00919   */
00920 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
00921 {
00922   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
00923                    DMA_CNDTR_NDT));
00924 }
00925
00926 /**
00927   * @brief  Configure the Source and Destination addresses.
00928   * @note   This API must not be called when the DMA channel is enabled.
00929   * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
00930   * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
00931   *         CMAR         MA            LL_DMA_ConfigAddresses
00932   * @param  DMAx DMAx Instance
00933   * @param  Channel This parameter can be one of the following values:
00934   *         @arg @ref LL_DMA_CHANNEL_1
00935   *         @arg @ref LL_DMA_CHANNEL_2
00936   *         @arg @ref LL_DMA_CHANNEL_3
00937   *         @arg @ref LL_DMA_CHANNEL_4
00938   *         @arg @ref LL_DMA_CHANNEL_5
00939   *         @arg @ref LL_DMA_CHANNEL_6
00940   *         @arg @ref LL_DMA_CHANNEL_7
00941   * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00942   * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00943   * @param  Direction This parameter can be one of the following values:
00944   *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
00945   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
00946   *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
00947   * @retval None
00948   */
00949 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
00950                                             uint32_t DstAddress, uint32_t Direction)
00951 {
00952   /* Direction Memory to Periph */
00953   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
00954   {
00955     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
00956     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
00957   }
00958   /* Direction Periph to Memory and Memory to Memory */
00959   else
00960   {
00961     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
00962     WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
00963   }
00964 }
00965
00966 /**
00967   * @brief  Set the Memory address.
00968   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
00969   * @note   This API must not be called when the DMA channel is enabled.
00970   * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
00971   * @param  DMAx DMAx Instance
00972   * @param  Channel This parameter can be one of the following values:
00973   *         @arg @ref LL_DMA_CHANNEL_1
00974   *         @arg @ref LL_DMA_CHANNEL_2
00975   *         @arg @ref LL_DMA_CHANNEL_3
00976   *         @arg @ref LL_DMA_CHANNEL_4
00977   *         @arg @ref LL_DMA_CHANNEL_5
00978   *         @arg @ref LL_DMA_CHANNEL_6
00979   *         @arg @ref LL_DMA_CHANNEL_7
00980   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
00981   * @retval None
00982   */
00983 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
00984 {
00985   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
00986 }
00987
00988 /**
00989   * @brief  Set the Peripheral address.
00990   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
00991   * @note   This API must not be called when the DMA channel is enabled.
00992   * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
00993   * @param  DMAx DMAx Instance
00994   * @param  Channel This parameter can be one of the following values:
00995   *         @arg @ref LL_DMA_CHANNEL_1
00996   *         @arg @ref LL_DMA_CHANNEL_2
00997   *         @arg @ref LL_DMA_CHANNEL_3
00998   *         @arg @ref LL_DMA_CHANNEL_4
00999   *         @arg @ref LL_DMA_CHANNEL_5
01000   *         @arg @ref LL_DMA_CHANNEL_6
01001   *         @arg @ref LL_DMA_CHANNEL_7
01002   * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01003   * @retval None
01004   */
01005 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
01006 {
01007   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
01008 }
01009
01010 /**
01011   * @brief  Get Memory address.
01012   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01013   * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress
01014   * @param  DMAx DMAx Instance
01015   * @param  Channel This parameter can be one of the following values:
01016   *         @arg @ref LL_DMA_CHANNEL_1
01017   *         @arg @ref LL_DMA_CHANNEL_2
01018   *         @arg @ref LL_DMA_CHANNEL_3
01019   *         @arg @ref LL_DMA_CHANNEL_4
01020   *         @arg @ref LL_DMA_CHANNEL_5
01021   *         @arg @ref LL_DMA_CHANNEL_6
01022   *         @arg @ref LL_DMA_CHANNEL_7
01023   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01024   */
01025 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01026 {
01027   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
01028 }
01029
01030 /**
01031   * @brief  Get Peripheral address.
01032   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
01033   * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress
01034   * @param  DMAx DMAx Instance
01035   * @param  Channel This parameter can be one of the following values:
01036   *         @arg @ref LL_DMA_CHANNEL_1
01037   *         @arg @ref LL_DMA_CHANNEL_2
01038   *         @arg @ref LL_DMA_CHANNEL_3
01039   *         @arg @ref LL_DMA_CHANNEL_4
01040   *         @arg @ref LL_DMA_CHANNEL_5
01041   *         @arg @ref LL_DMA_CHANNEL_6
01042   *         @arg @ref LL_DMA_CHANNEL_7
01043   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01044   */
01045 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01046 {
01047   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
01048 }
01049
01050 /**
01051   * @brief  Set the Memory to Memory Source address.
01052   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01053   * @note   This API must not be called when the DMA channel is enabled.
01054   * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
01055   * @param  DMAx DMAx Instance
01056   * @param  Channel This parameter can be one of the following values:
01057   *         @arg @ref LL_DMA_CHANNEL_1
01058   *         @arg @ref LL_DMA_CHANNEL_2
01059   *         @arg @ref LL_DMA_CHANNEL_3
01060   *         @arg @ref LL_DMA_CHANNEL_4
01061   *         @arg @ref LL_DMA_CHANNEL_5
01062   *         @arg @ref LL_DMA_CHANNEL_6
01063   *         @arg @ref LL_DMA_CHANNEL_7
01064   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01065   * @retval None
01066   */
01067 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01068 {
01069   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
01070 }
01071
01072 /**
01073   * @brief  Set the Memory to Memory Destination address.
01074   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01075   * @note   This API must not be called when the DMA channel is enabled.
01076   * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
01077   * @param  DMAx DMAx Instance
01078   * @param  Channel This parameter can be one of the following values:
01079   *         @arg @ref LL_DMA_CHANNEL_1
01080   *         @arg @ref LL_DMA_CHANNEL_2
01081   *         @arg @ref LL_DMA_CHANNEL_3
01082   *         @arg @ref LL_DMA_CHANNEL_4
01083   *         @arg @ref LL_DMA_CHANNEL_5
01084   *         @arg @ref LL_DMA_CHANNEL_6
01085   *         @arg @ref LL_DMA_CHANNEL_7
01086   * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01087   * @retval None
01088   */
01089 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
01090 {
01091   WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
01092 }
01093
01094 /**
01095   * @brief  Get the Memory to Memory Source address.
01096   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01097   * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress
01098   * @param  DMAx DMAx Instance
01099   * @param  Channel This parameter can be one of the following values:
01100   *         @arg @ref LL_DMA_CHANNEL_1
01101   *         @arg @ref LL_DMA_CHANNEL_2
01102   *         @arg @ref LL_DMA_CHANNEL_3
01103   *         @arg @ref LL_DMA_CHANNEL_4
01104   *         @arg @ref LL_DMA_CHANNEL_5
01105   *         @arg @ref LL_DMA_CHANNEL_6
01106   *         @arg @ref LL_DMA_CHANNEL_7
01107   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01108   */
01109 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01110 {
01111   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
01112 }
01113
01114 /**
01115   * @brief  Get the Memory to Memory Destination address.
01116   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
01117   * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress
01118   * @param  DMAx DMAx Instance
01119   * @param  Channel This parameter can be one of the following values:
01120   *         @arg @ref LL_DMA_CHANNEL_1
01121   *         @arg @ref LL_DMA_CHANNEL_2
01122   *         @arg @ref LL_DMA_CHANNEL_3
01123   *         @arg @ref LL_DMA_CHANNEL_4
01124   *         @arg @ref LL_DMA_CHANNEL_5
01125   *         @arg @ref LL_DMA_CHANNEL_6
01126   *         @arg @ref LL_DMA_CHANNEL_7
01127   * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
01128   */
01129 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
01130 {
01131   return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
01132 }
01133
01134 /**
01135   * @}
01136   */
01137
01138 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
01139   * @{
01140   */
01141
01142 /**
01143   * @brief  Get Channel 1 global interrupt flag.
01144   * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1
01145   * @param  DMAx DMAx Instance
01146   * @retval State of bit (1 or 0).
01147   */
01148 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
01149 {
01150   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
01151 }
01152
01153 /**
01154   * @brief  Get Channel 2 global interrupt flag.
01155   * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2
01156   * @param  DMAx DMAx Instance
01157   * @retval State of bit (1 or 0).
01158   */
01159 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
01160 {
01161   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
01162 }
01163
01164 /**
01165   * @brief  Get Channel 3 global interrupt flag.
01166   * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3
01167   * @param  DMAx DMAx Instance
01168   * @retval State of bit (1 or 0).
01169   */
01170 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
01171 {
01172   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
01173 }
01174
01175 /**
01176   * @brief  Get Channel 4 global interrupt flag.
01177   * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4
01178   * @param  DMAx DMAx Instance
01179   * @retval State of bit (1 or 0).
01180   */
01181 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
01182 {
01183   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
01184 }
01185
01186 /**
01187   * @brief  Get Channel 5 global interrupt flag.
01188   * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5
01189   * @param  DMAx DMAx Instance
01190   * @retval State of bit (1 or 0).
01191   */
01192 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
01193 {
01194   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
01195 }
01196
01197 /**
01198   * @brief  Get Channel 6 global interrupt flag.
01199   * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6
01200   * @param  DMAx DMAx Instance
01201   * @retval State of bit (1 or 0).
01202   */
01203 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
01204 {
01205   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
01206 }
01207
01208 /**
01209   * @brief  Get Channel 7 global interrupt flag.
01210   * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7
01211   * @param  DMAx DMAx Instance
01212   * @retval State of bit (1 or 0).
01213   */
01214 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
01215 {
01216   return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
01217 }
01218
01219 /**
01220   * @brief  Get Channel 1 transfer complete flag.
01221   * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1
01222   * @param  DMAx DMAx Instance
01223   * @retval State of bit (1 or 0).
01224   */
01225 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
01226 {
01227   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
01228 }
01229
01230 /**
01231   * @brief  Get Channel 2 transfer complete flag.
01232   * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2
01233   * @param  DMAx DMAx Instance
01234   * @retval State of bit (1 or 0).
01235   */
01236 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
01237 {
01238   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
01239 }
01240
01241 /**
01242   * @brief  Get Channel 3 transfer complete flag.
01243   * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3
01244   * @param  DMAx DMAx Instance
01245   * @retval State of bit (1 or 0).
01246   */
01247 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
01248 {
01249   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
01250 }
01251
01252 /**
01253   * @brief  Get Channel 4 transfer complete flag.
01254   * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4
01255   * @param  DMAx DMAx Instance
01256   * @retval State of bit (1 or 0).
01257   */
01258 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
01259 {
01260   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
01261 }
01262
01263 /**
01264   * @brief  Get Channel 5 transfer complete flag.
01265   * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5
01266   * @param  DMAx DMAx Instance
01267   * @retval State of bit (1 or 0).
01268   */
01269 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
01270 {
01271   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
01272 }
01273
01274 /**
01275   * @brief  Get Channel 6 transfer complete flag.
01276   * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6
01277   * @param  DMAx DMAx Instance
01278   * @retval State of bit (1 or 0).
01279   */
01280 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
01281 {
01282   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
01283 }
01284
01285 /**
01286   * @brief  Get Channel 7 transfer complete flag.
01287   * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7
01288   * @param  DMAx DMAx Instance
01289   * @retval State of bit (1 or 0).
01290   */
01291 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
01292 {
01293   return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
01294 }
01295
01296 /**
01297   * @brief  Get Channel 1 half transfer flag.
01298   * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1
01299   * @param  DMAx DMAx Instance
01300   * @retval State of bit (1 or 0).
01301   */
01302 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
01303 {
01304   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
01305 }
01306
01307 /**
01308   * @brief  Get Channel 2 half transfer flag.
01309   * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2
01310   * @param  DMAx DMAx Instance
01311   * @retval State of bit (1 or 0).
01312   */
01313 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
01314 {
01315   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
01316 }
01317
01318 /**
01319   * @brief  Get Channel 3 half transfer flag.
01320   * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3
01321   * @param  DMAx DMAx Instance
01322   * @retval State of bit (1 or 0).
01323   */
01324 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
01325 {
01326   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
01327 }
01328
01329 /**
01330   * @brief  Get Channel 4 half transfer flag.
01331   * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4
01332   * @param  DMAx DMAx Instance
01333   * @retval State of bit (1 or 0).
01334   */
01335 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
01336 {
01337   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
01338 }
01339
01340 /**
01341   * @brief  Get Channel 5 half transfer flag.
01342   * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5
01343   * @param  DMAx DMAx Instance
01344   * @retval State of bit (1 or 0).
01345   */
01346 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
01347 {
01348   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
01349 }
01350
01351 /**
01352   * @brief  Get Channel 6 half transfer flag.
01353   * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6
01354   * @param  DMAx DMAx Instance
01355   * @retval State of bit (1 or 0).
01356   */
01357 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
01358 {
01359   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
01360 }
01361
01362 /**
01363   * @brief  Get Channel 7 half transfer flag.
01364   * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7
01365   * @param  DMAx DMAx Instance
01366   * @retval State of bit (1 or 0).
01367   */
01368 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
01369 {
01370   return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
01371 }
01372
01373 /**
01374   * @brief  Get Channel 1 transfer error flag.
01375   * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1
01376   * @param  DMAx DMAx Instance
01377   * @retval State of bit (1 or 0).
01378   */
01379 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
01380 {
01381   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
01382 }
01383
01384 /**
01385   * @brief  Get Channel 2 transfer error flag.
01386   * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2
01387   * @param  DMAx DMAx Instance
01388   * @retval State of bit (1 or 0).
01389   */
01390 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
01391 {
01392   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
01393 }
01394
01395 /**
01396   * @brief  Get Channel 3 transfer error flag.
01397   * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3
01398   * @param  DMAx DMAx Instance
01399   * @retval State of bit (1 or 0).
01400   */
01401 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
01402 {
01403   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
01404 }
01405
01406 /**
01407   * @brief  Get Channel 4 transfer error flag.
01408   * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4
01409   * @param  DMAx DMAx Instance
01410   * @retval State of bit (1 or 0).
01411   */
01412 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
01413 {
01414   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
01415 }
01416
01417 /**
01418   * @brief  Get Channel 5 transfer error flag.
01419   * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5
01420   * @param  DMAx DMAx Instance
01421   * @retval State of bit (1 or 0).
01422   */
01423 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
01424 {
01425   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
01426 }
01427
01428 /**
01429   * @brief  Get Channel 6 transfer error flag.
01430   * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6
01431   * @param  DMAx DMAx Instance
01432   * @retval State of bit (1 or 0).
01433   */
01434 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
01435 {
01436   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
01437 }
01438
01439 /**
01440   * @brief  Get Channel 7 transfer error flag.
01441   * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7
01442   * @param  DMAx DMAx Instance
01443   * @retval State of bit (1 or 0).
01444   */
01445 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
01446 {
01447   return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
01448 }
01449
01450 /**
01451   * @brief  Clear Channel 1 global interrupt flag.
01452   * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1
01453   * @param  DMAx DMAx Instance
01454   * @retval None
01455   */
01456 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
01457 {
01458   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF1);
01459 }
01460
01461 /**
01462   * @brief  Clear Channel 2 global interrupt flag.
01463   * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2
01464   * @param  DMAx DMAx Instance
01465   * @retval None
01466   */
01467 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
01468 {
01469   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF2);
01470 }
01471
01472 /**
01473   * @brief  Clear Channel 3 global interrupt flag.
01474   * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3
01475   * @param  DMAx DMAx Instance
01476   * @retval None
01477   */
01478 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
01479 {
01480   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF3);
01481 }
01482
01483 /**
01484   * @brief  Clear Channel 4 global interrupt flag.
01485   * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4
01486   * @param  DMAx DMAx Instance
01487   * @retval None
01488   */
01489 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
01490 {
01491   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF4);
01492 }
01493
01494 /**
01495   * @brief  Clear Channel 5 global interrupt flag.
01496   * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5
01497   * @param  DMAx DMAx Instance
01498   * @retval None
01499   */
01500 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
01501 {
01502   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF5);
01503 }
01504
01505 /**
01506   * @brief  Clear Channel 6 global interrupt flag.
01507   * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6
01508   * @param  DMAx DMAx Instance
01509   * @retval None
01510   */
01511 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
01512 {
01513   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF6);
01514 }
01515
01516 /**
01517   * @brief  Clear Channel 7 global interrupt flag.
01518   * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7
01519   * @param  DMAx DMAx Instance
01520   * @retval None
01521   */
01522 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
01523 {
01524   SET_BIT(DMAx->IFCR, DMA_IFCR_CGIF7);
01525 }
01526
01527 /**
01528   * @brief  Clear Channel 1  transfer complete flag.
01529   * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1
01530   * @param  DMAx DMAx Instance
01531   * @retval None
01532   */
01533 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
01534 {
01535   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF1);
01536 }
01537
01538 /**
01539   * @brief  Clear Channel 2  transfer complete flag.
01540   * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2
01541   * @param  DMAx DMAx Instance
01542   * @retval None
01543   */
01544 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
01545 {
01546   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF2);
01547 }
01548
01549 /**
01550   * @brief  Clear Channel 3  transfer complete flag.
01551   * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3
01552   * @param  DMAx DMAx Instance
01553   * @retval None
01554   */
01555 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
01556 {
01557   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF3);
01558 }
01559
01560 /**
01561   * @brief  Clear Channel 4  transfer complete flag.
01562   * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4
01563   * @param  DMAx DMAx Instance
01564   * @retval None
01565   */
01566 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
01567 {
01568   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF4);
01569 }
01570
01571 /**
01572   * @brief  Clear Channel 5  transfer complete flag.
01573   * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5
01574   * @param  DMAx DMAx Instance
01575   * @retval None
01576   */
01577 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
01578 {
01579   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF5);
01580 }
01581
01582 /**
01583   * @brief  Clear Channel 6  transfer complete flag.
01584   * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6
01585   * @param  DMAx DMAx Instance
01586   * @retval None
01587   */
01588 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
01589 {
01590   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF6);
01591 }
01592
01593 /**
01594   * @brief  Clear Channel 7  transfer complete flag.
01595   * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7
01596   * @param  DMAx DMAx Instance
01597   * @retval None
01598   */
01599 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
01600 {
01601   SET_BIT(DMAx->IFCR, DMA_IFCR_CTCIF7);
01602 }
01603
01604 /**
01605   * @brief  Clear Channel 1  half transfer flag.
01606   * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1
01607   * @param  DMAx DMAx Instance
01608   * @retval None
01609   */
01610 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
01611 {
01612   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF1);
01613 }
01614
01615 /**
01616   * @brief  Clear Channel 2  half transfer flag.
01617   * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2
01618   * @param  DMAx DMAx Instance
01619   * @retval None
01620   */
01621 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
01622 {
01623   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF2);
01624 }
01625
01626 /**
01627   * @brief  Clear Channel 3  half transfer flag.
01628   * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3
01629   * @param  DMAx DMAx Instance
01630   * @retval None
01631   */
01632 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
01633 {
01634   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF3);
01635 }
01636
01637 /**
01638   * @brief  Clear Channel 4  half transfer flag.
01639   * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4
01640   * @param  DMAx DMAx Instance
01641   * @retval None
01642   */
01643 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
01644 {
01645   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF4);
01646 }
01647
01648 /**
01649   * @brief  Clear Channel 5  half transfer flag.
01650   * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5
01651   * @param  DMAx DMAx Instance
01652   * @retval None
01653   */
01654 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
01655 {
01656   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF5);
01657 }
01658
01659 /**
01660   * @brief  Clear Channel 6  half transfer flag.
01661   * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6
01662   * @param  DMAx DMAx Instance
01663   * @retval None
01664   */
01665 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
01666 {
01667   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF6);
01668 }
01669
01670 /**
01671   * @brief  Clear Channel 7  half transfer flag.
01672   * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7
01673   * @param  DMAx DMAx Instance
01674   * @retval None
01675   */
01676 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
01677 {
01678   SET_BIT(DMAx->IFCR, DMA_IFCR_CHTIF7);
01679 }
01680
01681 /**
01682   * @brief  Clear Channel 1 transfer error flag.
01683   * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1
01684   * @param  DMAx DMAx Instance
01685   * @retval None
01686   */
01687 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
01688 {
01689   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF1);
01690 }
01691
01692 /**
01693   * @brief  Clear Channel 2 transfer error flag.
01694   * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2
01695   * @param  DMAx DMAx Instance
01696   * @retval None
01697   */
01698 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
01699 {
01700   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF2);
01701 }
01702
01703 /**
01704   * @brief  Clear Channel 3 transfer error flag.
01705   * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3
01706   * @param  DMAx DMAx Instance
01707   * @retval None
01708   */
01709 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
01710 {
01711   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF3);
01712 }
01713
01714 /**
01715   * @brief  Clear Channel 4 transfer error flag.
01716   * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4
01717   * @param  DMAx DMAx Instance
01718   * @retval None
01719   */
01720 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
01721 {
01722   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF4);
01723 }
01724
01725 /**
01726   * @brief  Clear Channel 5 transfer error flag.
01727   * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5
01728   * @param  DMAx DMAx Instance
01729   * @retval None
01730   */
01731 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
01732 {
01733   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF5);
01734 }
01735
01736 /**
01737   * @brief  Clear Channel 6 transfer error flag.
01738   * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6
01739   * @param  DMAx DMAx Instance
01740   * @retval None
01741   */
01742 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
01743 {
01744   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF6);
01745 }
01746
01747 /**
01748   * @brief  Clear Channel 7 transfer error flag.
01749   * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7
01750   * @param  DMAx DMAx Instance
01751   * @retval None
01752   */
01753 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
01754 {
01755   SET_BIT(DMAx->IFCR, DMA_IFCR_CTEIF7);
01756 }
01757
01758 /**
01759   * @}
01760   */
01761
01762 /** @defgroup DMA_LL_EF_IT_Management IT_Management
01763   * @{
01764   */
01765
01766 /**
01767   * @brief  Enable Transfer complete interrupt.
01768   * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC
01769   * @param  DMAx DMAx Instance
01770   * @param  Channel This parameter can be one of the following values:
01771   *         @arg @ref LL_DMA_CHANNEL_1
01772   *         @arg @ref LL_DMA_CHANNEL_2
01773   *         @arg @ref LL_DMA_CHANNEL_3
01774   *         @arg @ref LL_DMA_CHANNEL_4
01775   *         @arg @ref LL_DMA_CHANNEL_5
01776   *         @arg @ref LL_DMA_CHANNEL_6
01777   *         @arg @ref LL_DMA_CHANNEL_7
01778   * @retval None
01779   */
01780 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
01781 {
01782   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
01783 }
01784
01785 /**
01786   * @brief  Enable Half transfer interrupt.
01787   * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT
01788   * @param  DMAx DMAx Instance
01789   * @param  Channel This parameter can be one of the following values:
01790   *         @arg @ref LL_DMA_CHANNEL_1
01791   *         @arg @ref LL_DMA_CHANNEL_2
01792   *         @arg @ref LL_DMA_CHANNEL_3
01793   *         @arg @ref LL_DMA_CHANNEL_4
01794   *         @arg @ref LL_DMA_CHANNEL_5
01795   *         @arg @ref LL_DMA_CHANNEL_6
01796   *         @arg @ref LL_DMA_CHANNEL_7
01797   * @retval None
01798   */
01799 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
01800 {
01801   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
01802 }
01803
01804 /**
01805   * @brief  Enable Transfer error interrupt.
01806   * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE
01807   * @param  DMAx DMAx Instance
01808   * @param  Channel This parameter can be one of the following values:
01809   *         @arg @ref LL_DMA_CHANNEL_1
01810   *         @arg @ref LL_DMA_CHANNEL_2
01811   *         @arg @ref LL_DMA_CHANNEL_3
01812   *         @arg @ref LL_DMA_CHANNEL_4
01813   *         @arg @ref LL_DMA_CHANNEL_5
01814   *         @arg @ref LL_DMA_CHANNEL_6
01815   *         @arg @ref LL_DMA_CHANNEL_7
01816   * @retval None
01817   */
01818 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
01819 {
01820   SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
01821 }
01822
01823 /**
01824   * @brief  Disable Transfer complete interrupt.
01825   * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC
01826   * @param  DMAx DMAx Instance
01827   * @param  Channel This parameter can be one of the following values:
01828   *         @arg @ref LL_DMA_CHANNEL_1
01829   *         @arg @ref LL_DMA_CHANNEL_2
01830   *         @arg @ref LL_DMA_CHANNEL_3
01831   *         @arg @ref LL_DMA_CHANNEL_4
01832   *         @arg @ref LL_DMA_CHANNEL_5
01833   *         @arg @ref LL_DMA_CHANNEL_6
01834   *         @arg @ref LL_DMA_CHANNEL_7
01835   * @retval None
01836   */
01837 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
01838 {
01839   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
01840 }
01841
01842 /**
01843   * @brief  Disable Half transfer interrupt.
01844   * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT
01845   * @param  DMAx DMAx Instance
01846   * @param  Channel This parameter can be one of the following values:
01847   *         @arg @ref LL_DMA_CHANNEL_1
01848   *         @arg @ref LL_DMA_CHANNEL_2
01849   *         @arg @ref LL_DMA_CHANNEL_3
01850   *         @arg @ref LL_DMA_CHANNEL_4
01851   *         @arg @ref LL_DMA_CHANNEL_5
01852   *         @arg @ref LL_DMA_CHANNEL_6
01853   *         @arg @ref LL_DMA_CHANNEL_7
01854   * @retval None
01855   */
01856 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
01857 {
01858   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
01859 }
01860
01861 /**
01862   * @brief  Disable Transfer error interrupt.
01863   * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE
01864   * @param  DMAx DMAx Instance
01865   * @param  Channel This parameter can be one of the following values:
01866   *         @arg @ref LL_DMA_CHANNEL_1
01867   *         @arg @ref LL_DMA_CHANNEL_2
01868   *         @arg @ref LL_DMA_CHANNEL_3
01869   *         @arg @ref LL_DMA_CHANNEL_4
01870   *         @arg @ref LL_DMA_CHANNEL_5
01871   *         @arg @ref LL_DMA_CHANNEL_6
01872   *         @arg @ref LL_DMA_CHANNEL_7
01873   * @retval None
01874   */
01875 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
01876 {
01877   CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
01878 }
01879
01880 /**
01881   * @brief  Check if Transfer complete Interrupt is enabled.
01882   * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC
01883   * @param  DMAx DMAx Instance
01884   * @param  Channel This parameter can be one of the following values:
01885   *         @arg @ref LL_DMA_CHANNEL_1
01886   *         @arg @ref LL_DMA_CHANNEL_2
01887   *         @arg @ref LL_DMA_CHANNEL_3
01888   *         @arg @ref LL_DMA_CHANNEL_4
01889   *         @arg @ref LL_DMA_CHANNEL_5
01890   *         @arg @ref LL_DMA_CHANNEL_6
01891   *         @arg @ref LL_DMA_CHANNEL_7
01892   * @retval State of bit (1 or 0).
01893   */
01894 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
01895 {
01896   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
01897                    DMA_CCR_TCIE) == (DMA_CCR_TCIE));
01898 }
01899
01900 /**
01901   * @brief  Check if Half transfer Interrupt is enabled.
01902   * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT
01903   * @param  DMAx DMAx Instance
01904   * @param  Channel This parameter can be one of the following values:
01905   *         @arg @ref LL_DMA_CHANNEL_1
01906   *         @arg @ref LL_DMA_CHANNEL_2
01907   *         @arg @ref LL_DMA_CHANNEL_3
01908   *         @arg @ref LL_DMA_CHANNEL_4
01909   *         @arg @ref LL_DMA_CHANNEL_5
01910   *         @arg @ref LL_DMA_CHANNEL_6
01911   *         @arg @ref LL_DMA_CHANNEL_7
01912   * @retval State of bit (1 or 0).
01913   */
01914 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
01915 {
01916   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
01917                    DMA_CCR_HTIE) == (DMA_CCR_HTIE));
01918 }
01919
01920 /**
01921   * @brief  Check if Transfer error Interrupt is enabled.
01922   * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE
01923   * @param  DMAx DMAx Instance
01924   * @param  Channel This parameter can be one of the following values:
01925   *         @arg @ref LL_DMA_CHANNEL_1
01926   *         @arg @ref LL_DMA_CHANNEL_2
01927   *         @arg @ref LL_DMA_CHANNEL_3
01928   *         @arg @ref LL_DMA_CHANNEL_4
01929   *         @arg @ref LL_DMA_CHANNEL_5
01930   *         @arg @ref LL_DMA_CHANNEL_6
01931   *         @arg @ref LL_DMA_CHANNEL_7
01932   * @retval State of bit (1 or 0).
01933   */
01934 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
01935 {
01936   return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
01937                    DMA_CCR_TEIE) == (DMA_CCR_TEIE));
01938 }
01939
01940 /**
01941   * @}
01942   */
01943
01944 #if defined(USE_FULL_LL_DRIVER)
01945 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
01946   * @{
01947   */
01948
01949 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
01950 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
01951 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
01952
01953 /**
01954   * @}
01955   */
01956 #endif /* USE_FULL_LL_DRIVER */
01957
01958 /**
01959   * @}
01960   */
01961
01962 /**
01963   * @}
01964   */
01965
01966 #endif /* DMA1 || DMA2 */
01967
01968 /**
01969   * @}
01970   */
01971
01972 #ifdef __cplusplus
01973 }
01974 #endif
01975
01976 #endif /* __STM32F1xx_LL_DMA_H */
01977
01978 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_exti.c Source File

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stm32f1xx_ll_exti.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_exti.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   EXTI LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_exti.h"
00041 #ifdef  USE_FULL_ASSERT
00042 #include "stm32_assert.h"
00043 #else
00044 #define assert_param(expr) ((void)0U)
00045 #endif
00046
00047 /** @addtogroup STM32F1xx_LL_Driver
00048   * @{
00049   */
00050
00051 #if defined (EXTI)
00052
00053 /** @defgroup EXTI_LL EXTI
00054   * @{
00055   */
00056
00057 /* Private types -------------------------------------------------------------*/
00058 /* Private variables ---------------------------------------------------------*/
00059 /* Private constants ---------------------------------------------------------*/
00060 /* Private macros ------------------------------------------------------------*/
00061 /** @addtogroup EXTI_LL_Private_Macros
00062   * @{
00063   */
00064
00065 #define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
00066
00067 #define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
00068                                                    || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
00069                                                    || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
00070
00071
00072 #define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
00073                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
00074                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
00075                                                    || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
00076
00077 /**
00078   * @}
00079   */
00080
00081 /* Private function prototypes -----------------------------------------------*/
00082
00083 /* Exported functions --------------------------------------------------------*/
00084 /** @addtogroup EXTI_LL_Exported_Functions
00085   * @{
00086   */
00087
00088 /** @addtogroup EXTI_LL_EF_Init
00089   * @{
00090   */
00091
00092 /**
00093   * @brief  De-initialize the EXTI registers to their default reset values.
00094   * @retval An ErrorStatus enumeration value:
00095   *          - SUCCESS: EXTI registers are de-initialized
00096   *          - ERROR: not applicable
00097   */
00098 uint32_t LL_EXTI_DeInit(void)
00099 {
00100   /* Interrupt mask register set to default reset values */
00101   LL_EXTI_WriteReg(IMR,   0x00000000U);
00102   /* Event mask register set to default reset values */
00103   LL_EXTI_WriteReg(EMR,   0x00000000U);
00104   /* Rising Trigger selection register set to default reset values */
00105   LL_EXTI_WriteReg(RTSR,  0x00000000U);
00106   /* Falling Trigger selection register set to default reset values */
00107   LL_EXTI_WriteReg(FTSR,  0x00000000U);
00108   /* Software interrupt event register set to default reset values */
00109   LL_EXTI_WriteReg(SWIER, 0x00000000U);
00110   /* Pending register set to default reset values */
00111   LL_EXTI_WriteReg(PR,    0x000FFFFFU);
00112
00113   return SUCCESS;
00114 }
00115
00116 /**
00117   * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
00118   * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
00119   * @retval An ErrorStatus enumeration value:
00120   *          - SUCCESS: EXTI registers are initialized
00121   *          - ERROR: not applicable
00122   */
00123 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00124 {
00125   ErrorStatus status = SUCCESS;
00126   /* Check the parameters */
00127   assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
00128   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
00129   assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
00130
00131   /* ENABLE LineCommand */
00132   if (EXTI_InitStruct->LineCommand != DISABLE)
00133   {
00134     assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
00135
00136     /* Configure EXTI Lines in range from 0 to 31 */
00137     if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
00138     {
00139       switch (EXTI_InitStruct->Mode)
00140       {
00141         case LL_EXTI_MODE_IT:
00142           /* First Disable Event on provided Lines */
00143           LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00144           /* Then Enable IT on provided Lines */
00145           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00146           break;
00147         case LL_EXTI_MODE_EVENT:
00148           /* First Disable IT on provided Lines */
00149           LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00150           /* Then Enable Event on provided Lines */
00151           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00152           break;
00153         case LL_EXTI_MODE_IT_EVENT:
00154           /* Directly Enable IT & Event on provided Lines */
00155           LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
00156           LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
00157           break;
00158         default:
00159           status = ERROR;
00160           break;
00161       }
00162       if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
00163       {
00164         switch (EXTI_InitStruct->Trigger)
00165         {
00166           case LL_EXTI_TRIGGER_RISING:
00167             /* First Disable Falling Trigger on provided Lines */
00168             LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00169             /* Then Enable Rising Trigger on provided Lines */
00170             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00171             break;
00172           case LL_EXTI_TRIGGER_FALLING:
00173             /* First Disable Rising Trigger on provided Lines */
00174             LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00175             /* Then Enable Falling Trigger on provided Lines */
00176             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00177             break;
00178           case LL_EXTI_TRIGGER_RISING_FALLING:
00179             LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
00180             LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
00181             break;
00182           default:
00183             status = ERROR;
00184             break;
00185         }
00186       }
00187     }
00188   }
00189   /* DISABLE LineCommand */
00190   else
00191   {
00192     /* De-configure EXTI Lines in range from 0 to 31 */
00193     LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
00194     LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
00195   }
00196   return status;
00197 }
00198
00199 /**
00200   * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
00201   * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
00202   * @retval None
00203   */
00204 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
00205 {
00206   EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
00207   EXTI_InitStruct->LineCommand    = DISABLE;
00208   EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
00209   EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
00210 }
00211
00212 /**
00213   * @}
00214   */
00215
00216 /**
00217   * @}
00218   */
00219
00220 /**
00221   * @}
00222   */
00223
00224 #endif /* defined (EXTI) */
00225
00226 /**
00227   * @}
00228   */
00229
00230 #endif /* USE_FULL_LL_DRIVER */
00231
00232 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_exti.h Source File

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  • Inc
stm32f1xx_ll_exti.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_exti.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of EXTI LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_EXTI_H
00040 #define __STM32F1xx_LL_EXTI_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (EXTI)
00054
00055 /** @defgroup EXTI_LL EXTI
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private Macros ------------------------------------------------------------*/
00063 #if defined(USE_FULL_LL_DRIVER)
00064 /** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
00065   * @{
00066   */
00067 /**
00068   * @}
00069   */
00070 #endif /*USE_FULL_LL_DRIVER*/
00071 /* Exported types ------------------------------------------------------------*/
00072 #if defined(USE_FULL_LL_DRIVER)
00073 /** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
00074   * @{
00075   */
00076 typedef struct
00077 {
00078
00079   uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
00080                                      This parameter can be any combination of @ref EXTI_LL_EC_LINE */
00081
00082   FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
00083                                      This parameter can be set either to ENABLE or DISABLE */
00084
00085   uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
00086                                      This parameter can be a value of @ref EXTI_LL_EC_MODE. */
00087
00088   uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
00089                                      This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
00090 } LL_EXTI_InitTypeDef;
00091
00092 /**
00093   * @}
00094   */
00095 #endif /*USE_FULL_LL_DRIVER*/
00096
00097 /* Exported constants --------------------------------------------------------*/
00098 /** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
00099   * @{
00100   */
00101
00102 /** @defgroup EXTI_LL_EC_LINE LINE
00103   * @{
00104   */
00105 #define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
00106 #define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
00107 #define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
00108 #define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
00109 #define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
00110 #define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
00111 #define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
00112 #define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
00113 #define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
00114 #define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
00115 #define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
00116 #define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
00117 #define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
00118 #define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
00119 #define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
00120 #define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
00121 #if defined(EXTI_IMR_IM16)
00122 #define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
00123 #endif
00124 #define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
00125 #if defined(EXTI_IMR_IM18)
00126 #define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
00127 #endif
00128 #if defined(EXTI_IMR_IM19)
00129 #define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
00130 #endif
00131 #if defined(EXTI_IMR_IM20)
00132 #define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
00133 #endif
00134 #if defined(EXTI_IMR_IM21)
00135 #define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
00136 #endif
00137 #if defined(EXTI_IMR_IM22)
00138 #define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
00139 #endif
00140 #if defined(EXTI_IMR_IM23)
00141 #define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
00142 #endif
00143 #if defined(EXTI_IMR_IM24)
00144 #define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
00145 #endif
00146 #if defined(EXTI_IMR_IM25)
00147 #define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
00148 #endif
00149 #if defined(EXTI_IMR_IM26)
00150 #define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
00151 #endif
00152 #if defined(EXTI_IMR_IM27)
00153 #define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
00154 #endif
00155 #if defined(EXTI_IMR_IM28)
00156 #define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
00157 #endif
00158 #if defined(EXTI_IMR_IM29)
00159 #define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
00160 #endif
00161 #if defined(EXTI_IMR_IM30)
00162 #define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
00163 #endif
00164 #if defined(EXTI_IMR_IM31)
00165 #define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
00166 #endif
00167 #define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
00168
00169
00170 #define LL_EXTI_LINE_ALL               ((uint32_t)0xFFFFFFFFU)  /*!< All Extended line */
00171
00172 #if defined(USE_FULL_LL_DRIVER)
00173 #define LL_EXTI_LINE_NONE              ((uint32_t)0x00000000U)  /*!< None Extended line */
00174 #endif /*USE_FULL_LL_DRIVER*/
00175
00176 /**
00177   * @}
00178   */
00179 #if defined(USE_FULL_LL_DRIVER)
00180
00181 /** @defgroup EXTI_LL_EC_MODE Mode
00182   * @{
00183   */
00184 #define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
00185 #define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
00186 #define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
00192   * @{
00193   */
00194 #define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
00195 #define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
00196 #define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
00197 #define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
00198
00199 /**
00200   * @}
00201   */
00202
00203
00204 #endif /*USE_FULL_LL_DRIVER*/
00205
00206
00207 /**
00208   * @}
00209   */
00210
00211 /* Exported macro ------------------------------------------------------------*/
00212 /** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
00213   * @{
00214   */
00215
00216 /** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
00217   * @{
00218   */
00219
00220 /**
00221   * @brief  Write a value in EXTI register
00222   * @param  __REG__ Register to be written
00223   * @param  __VALUE__ Value to be written in the register
00224   * @retval None
00225   */
00226 #define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
00227
00228 /**
00229   * @brief  Read a value in EXTI register
00230   * @param  __REG__ Register to be read
00231   * @retval Register value
00232   */
00233 #define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
00234 /**
00235   * @}
00236   */
00237
00238
00239 /**
00240   * @}
00241   */
00242
00243
00244
00245 /* Exported functions --------------------------------------------------------*/
00246 /** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
00247  * @{
00248  */
00249 /** @defgroup EXTI_LL_EF_IT_Management IT_Management
00250   * @{
00251   */
00252
00253 /**
00254   * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
00255   * @note The reset value for the direct or internal lines (see RM)
00256   *       is set to 1 in order to enable the interrupt by default.
00257   *       Bits are set automatically at Power on.
00258   * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
00259   * @param  ExtiLine This parameter can be one of the following values:
00260   *         @arg @ref LL_EXTI_LINE_0
00261   *         @arg @ref LL_EXTI_LINE_1
00262   *         @arg @ref LL_EXTI_LINE_2
00263   *         @arg @ref LL_EXTI_LINE_3
00264   *         @arg @ref LL_EXTI_LINE_4
00265   *         @arg @ref LL_EXTI_LINE_5
00266   *         @arg @ref LL_EXTI_LINE_6
00267   *         @arg @ref LL_EXTI_LINE_7
00268   *         @arg @ref LL_EXTI_LINE_8
00269   *         @arg @ref LL_EXTI_LINE_9
00270   *         @arg @ref LL_EXTI_LINE_10
00271   *         @arg @ref LL_EXTI_LINE_11
00272   *         @arg @ref LL_EXTI_LINE_12
00273   *         @arg @ref LL_EXTI_LINE_13
00274   *         @arg @ref LL_EXTI_LINE_14
00275   *         @arg @ref LL_EXTI_LINE_15
00276   *         @arg @ref LL_EXTI_LINE_16
00277   *         @arg @ref LL_EXTI_LINE_17
00278   *         @arg @ref LL_EXTI_LINE_18
00279   *         @arg @ref LL_EXTI_LINE_19
00280   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00281   * @note   Please check each device line mapping for EXTI Line availability
00282   * @retval None
00283   */
00284 __STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
00285 {
00286   SET_BIT(EXTI->IMR, ExtiLine);
00287 }
00288
00289 /**
00290   * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
00291   * @note The reset value for the direct or internal lines (see RM)
00292   *       is set to 1 in order to enable the interrupt by default.
00293   *       Bits are set automatically at Power on.
00294   * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
00295   * @param  ExtiLine This parameter can be one of the following values:
00296   *         @arg @ref LL_EXTI_LINE_0
00297   *         @arg @ref LL_EXTI_LINE_1
00298   *         @arg @ref LL_EXTI_LINE_2
00299   *         @arg @ref LL_EXTI_LINE_3
00300   *         @arg @ref LL_EXTI_LINE_4
00301   *         @arg @ref LL_EXTI_LINE_5
00302   *         @arg @ref LL_EXTI_LINE_6
00303   *         @arg @ref LL_EXTI_LINE_7
00304   *         @arg @ref LL_EXTI_LINE_8
00305   *         @arg @ref LL_EXTI_LINE_9
00306   *         @arg @ref LL_EXTI_LINE_10
00307   *         @arg @ref LL_EXTI_LINE_11
00308   *         @arg @ref LL_EXTI_LINE_12
00309   *         @arg @ref LL_EXTI_LINE_13
00310   *         @arg @ref LL_EXTI_LINE_14
00311   *         @arg @ref LL_EXTI_LINE_15
00312   *         @arg @ref LL_EXTI_LINE_16
00313   *         @arg @ref LL_EXTI_LINE_17
00314   *         @arg @ref LL_EXTI_LINE_18
00315   *         @arg @ref LL_EXTI_LINE_19
00316   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00317   * @note   Please check each device line mapping for EXTI Line availability
00318   * @retval None
00319   */
00320 __STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
00321 {
00322   CLEAR_BIT(EXTI->IMR, ExtiLine);
00323 }
00324
00325
00326 /**
00327   * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
00328   * @note The reset value for the direct or internal lines (see RM)
00329   *       is set to 1 in order to enable the interrupt by default.
00330   *       Bits are set automatically at Power on.
00331   * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
00332   * @param  ExtiLine This parameter can be one of the following values:
00333   *         @arg @ref LL_EXTI_LINE_0
00334   *         @arg @ref LL_EXTI_LINE_1
00335   *         @arg @ref LL_EXTI_LINE_2
00336   *         @arg @ref LL_EXTI_LINE_3
00337   *         @arg @ref LL_EXTI_LINE_4
00338   *         @arg @ref LL_EXTI_LINE_5
00339   *         @arg @ref LL_EXTI_LINE_6
00340   *         @arg @ref LL_EXTI_LINE_7
00341   *         @arg @ref LL_EXTI_LINE_8
00342   *         @arg @ref LL_EXTI_LINE_9
00343   *         @arg @ref LL_EXTI_LINE_10
00344   *         @arg @ref LL_EXTI_LINE_11
00345   *         @arg @ref LL_EXTI_LINE_12
00346   *         @arg @ref LL_EXTI_LINE_13
00347   *         @arg @ref LL_EXTI_LINE_14
00348   *         @arg @ref LL_EXTI_LINE_15
00349   *         @arg @ref LL_EXTI_LINE_16
00350   *         @arg @ref LL_EXTI_LINE_17
00351   *         @arg @ref LL_EXTI_LINE_18
00352   *         @arg @ref LL_EXTI_LINE_19
00353   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00354   * @note   Please check each device line mapping for EXTI Line availability
00355   * @retval State of bit (1 or 0).
00356   */
00357 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
00358 {
00359   return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
00360 }
00361
00362
00363 /**
00364   * @}
00365   */
00366
00367 /** @defgroup EXTI_LL_EF_Event_Management Event_Management
00368   * @{
00369   */
00370
00371 /**
00372   * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
00373   * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
00374   * @param  ExtiLine This parameter can be one of the following values:
00375   *         @arg @ref LL_EXTI_LINE_0
00376   *         @arg @ref LL_EXTI_LINE_1
00377   *         @arg @ref LL_EXTI_LINE_2
00378   *         @arg @ref LL_EXTI_LINE_3
00379   *         @arg @ref LL_EXTI_LINE_4
00380   *         @arg @ref LL_EXTI_LINE_5
00381   *         @arg @ref LL_EXTI_LINE_6
00382   *         @arg @ref LL_EXTI_LINE_7
00383   *         @arg @ref LL_EXTI_LINE_8
00384   *         @arg @ref LL_EXTI_LINE_9
00385   *         @arg @ref LL_EXTI_LINE_10
00386   *         @arg @ref LL_EXTI_LINE_11
00387   *         @arg @ref LL_EXTI_LINE_12
00388   *         @arg @ref LL_EXTI_LINE_13
00389   *         @arg @ref LL_EXTI_LINE_14
00390   *         @arg @ref LL_EXTI_LINE_15
00391   *         @arg @ref LL_EXTI_LINE_16
00392   *         @arg @ref LL_EXTI_LINE_17
00393   *         @arg @ref LL_EXTI_LINE_18
00394   *         @arg @ref LL_EXTI_LINE_19
00395   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00396   * @note   Please check each device line mapping for EXTI Line availability
00397   * @retval None
00398   */
00399 __STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
00400 {
00401   SET_BIT(EXTI->EMR, ExtiLine);
00402
00403 }
00404
00405
00406 /**
00407   * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
00408   * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
00409   * @param  ExtiLine This parameter can be one of the following values:
00410   *         @arg @ref LL_EXTI_LINE_0
00411   *         @arg @ref LL_EXTI_LINE_1
00412   *         @arg @ref LL_EXTI_LINE_2
00413   *         @arg @ref LL_EXTI_LINE_3
00414   *         @arg @ref LL_EXTI_LINE_4
00415   *         @arg @ref LL_EXTI_LINE_5
00416   *         @arg @ref LL_EXTI_LINE_6
00417   *         @arg @ref LL_EXTI_LINE_7
00418   *         @arg @ref LL_EXTI_LINE_8
00419   *         @arg @ref LL_EXTI_LINE_9
00420   *         @arg @ref LL_EXTI_LINE_10
00421   *         @arg @ref LL_EXTI_LINE_11
00422   *         @arg @ref LL_EXTI_LINE_12
00423   *         @arg @ref LL_EXTI_LINE_13
00424   *         @arg @ref LL_EXTI_LINE_14
00425   *         @arg @ref LL_EXTI_LINE_15
00426   *         @arg @ref LL_EXTI_LINE_16
00427   *         @arg @ref LL_EXTI_LINE_17
00428   *         @arg @ref LL_EXTI_LINE_18
00429   *         @arg @ref LL_EXTI_LINE_19
00430   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00431   * @note   Please check each device line mapping for EXTI Line availability
00432   * @retval None
00433   */
00434 __STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
00435 {
00436   CLEAR_BIT(EXTI->EMR, ExtiLine);
00437 }
00438
00439
00440 /**
00441   * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
00442   * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
00443   * @param  ExtiLine This parameter can be one of the following values:
00444   *         @arg @ref LL_EXTI_LINE_0
00445   *         @arg @ref LL_EXTI_LINE_1
00446   *         @arg @ref LL_EXTI_LINE_2
00447   *         @arg @ref LL_EXTI_LINE_3
00448   *         @arg @ref LL_EXTI_LINE_4
00449   *         @arg @ref LL_EXTI_LINE_5
00450   *         @arg @ref LL_EXTI_LINE_6
00451   *         @arg @ref LL_EXTI_LINE_7
00452   *         @arg @ref LL_EXTI_LINE_8
00453   *         @arg @ref LL_EXTI_LINE_9
00454   *         @arg @ref LL_EXTI_LINE_10
00455   *         @arg @ref LL_EXTI_LINE_11
00456   *         @arg @ref LL_EXTI_LINE_12
00457   *         @arg @ref LL_EXTI_LINE_13
00458   *         @arg @ref LL_EXTI_LINE_14
00459   *         @arg @ref LL_EXTI_LINE_15
00460   *         @arg @ref LL_EXTI_LINE_16
00461   *         @arg @ref LL_EXTI_LINE_17
00462   *         @arg @ref LL_EXTI_LINE_18
00463   *         @arg @ref LL_EXTI_LINE_19
00464   *         @arg @ref LL_EXTI_LINE_ALL_0_31
00465   * @note   Please check each device line mapping for EXTI Line availability
00466   * @retval State of bit (1 or 0).
00467   */
00468 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
00469 {
00470   return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
00471
00472 }
00473
00474
00475 /**
00476   * @}
00477   */
00478
00479 /** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
00480   * @{
00481   */
00482
00483 /**
00484   * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00485   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00486   *       generated on these lines. If a rising edge on a configurable interrupt
00487   *       line occurs during a write operation in the EXTI_RTSR register, the
00488   *       pending bit is not set.
00489   *       Rising and falling edge triggers can be set for
00490   *       the same interrupt line. In this case, both generate a trigger
00491   *       condition.
00492   * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
00493   * @param  ExtiLine This parameter can be a combination of the following values:
00494   *         @arg @ref LL_EXTI_LINE_0
00495   *         @arg @ref LL_EXTI_LINE_1
00496   *         @arg @ref LL_EXTI_LINE_2
00497   *         @arg @ref LL_EXTI_LINE_3
00498   *         @arg @ref LL_EXTI_LINE_4
00499   *         @arg @ref LL_EXTI_LINE_5
00500   *         @arg @ref LL_EXTI_LINE_6
00501   *         @arg @ref LL_EXTI_LINE_7
00502   *         @arg @ref LL_EXTI_LINE_8
00503   *         @arg @ref LL_EXTI_LINE_9
00504   *         @arg @ref LL_EXTI_LINE_10
00505   *         @arg @ref LL_EXTI_LINE_11
00506   *         @arg @ref LL_EXTI_LINE_12
00507   *         @arg @ref LL_EXTI_LINE_13
00508   *         @arg @ref LL_EXTI_LINE_14
00509   *         @arg @ref LL_EXTI_LINE_15
00510   *         @arg @ref LL_EXTI_LINE_16
00511   *         @arg @ref LL_EXTI_LINE_18
00512   *         @arg @ref LL_EXTI_LINE_19
00513   * @note   Please check each device line mapping for EXTI Line availability
00514   * @retval None
00515   */
00516 __STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
00517 {
00518   SET_BIT(EXTI->RTSR, ExtiLine);
00519
00520 }
00521
00522
00523 /**
00524   * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
00525   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00526   *       generated on these lines. If a rising edge on a configurable interrupt
00527   *       line occurs during a write operation in the EXTI_RTSR register, the
00528   *       pending bit is not set.
00529   *       Rising and falling edge triggers can be set for
00530   *       the same interrupt line. In this case, both generate a trigger
00531   *       condition.
00532   * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
00533   * @param  ExtiLine This parameter can be a combination of the following values:
00534   *         @arg @ref LL_EXTI_LINE_0
00535   *         @arg @ref LL_EXTI_LINE_1
00536   *         @arg @ref LL_EXTI_LINE_2
00537   *         @arg @ref LL_EXTI_LINE_3
00538   *         @arg @ref LL_EXTI_LINE_4
00539   *         @arg @ref LL_EXTI_LINE_5
00540   *         @arg @ref LL_EXTI_LINE_6
00541   *         @arg @ref LL_EXTI_LINE_7
00542   *         @arg @ref LL_EXTI_LINE_8
00543   *         @arg @ref LL_EXTI_LINE_9
00544   *         @arg @ref LL_EXTI_LINE_10
00545   *         @arg @ref LL_EXTI_LINE_11
00546   *         @arg @ref LL_EXTI_LINE_12
00547   *         @arg @ref LL_EXTI_LINE_13
00548   *         @arg @ref LL_EXTI_LINE_14
00549   *         @arg @ref LL_EXTI_LINE_15
00550   *         @arg @ref LL_EXTI_LINE_16
00551   *         @arg @ref LL_EXTI_LINE_18
00552   *         @arg @ref LL_EXTI_LINE_19
00553   * @note   Please check each device line mapping for EXTI Line availability
00554   * @retval None
00555   */
00556 __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
00557 {
00558   CLEAR_BIT(EXTI->RTSR, ExtiLine);
00559
00560 }
00561
00562
00563 /**
00564   * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
00565   * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
00566   * @param  ExtiLine This parameter can be a combination of the following values:
00567   *         @arg @ref LL_EXTI_LINE_0
00568   *         @arg @ref LL_EXTI_LINE_1
00569   *         @arg @ref LL_EXTI_LINE_2
00570   *         @arg @ref LL_EXTI_LINE_3
00571   *         @arg @ref LL_EXTI_LINE_4
00572   *         @arg @ref LL_EXTI_LINE_5
00573   *         @arg @ref LL_EXTI_LINE_6
00574   *         @arg @ref LL_EXTI_LINE_7
00575   *         @arg @ref LL_EXTI_LINE_8
00576   *         @arg @ref LL_EXTI_LINE_9
00577   *         @arg @ref LL_EXTI_LINE_10
00578   *         @arg @ref LL_EXTI_LINE_11
00579   *         @arg @ref LL_EXTI_LINE_12
00580   *         @arg @ref LL_EXTI_LINE_13
00581   *         @arg @ref LL_EXTI_LINE_14
00582   *         @arg @ref LL_EXTI_LINE_15
00583   *         @arg @ref LL_EXTI_LINE_16
00584   *         @arg @ref LL_EXTI_LINE_18
00585   *         @arg @ref LL_EXTI_LINE_19
00586   * @note   Please check each device line mapping for EXTI Line availability
00587   * @retval State of bit (1 or 0).
00588   */
00589 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
00590 {
00591   return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
00592 }
00593
00594
00595 /**
00596   * @}
00597   */
00598
00599 /** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
00600   * @{
00601   */
00602
00603 /**
00604   * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
00605   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00606   *       generated on these lines. If a falling edge on a configurable interrupt
00607   *       line occurs during a write operation in the EXTI_FTSR register, the
00608   *       pending bit is not set.
00609   *       Rising and falling edge triggers can be set for
00610   *       the same interrupt line. In this case, both generate a trigger
00611   *       condition.
00612   * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
00613   * @param  ExtiLine This parameter can be a combination of the following values:
00614   *         @arg @ref LL_EXTI_LINE_0
00615   *         @arg @ref LL_EXTI_LINE_1
00616   *         @arg @ref LL_EXTI_LINE_2
00617   *         @arg @ref LL_EXTI_LINE_3
00618   *         @arg @ref LL_EXTI_LINE_4
00619   *         @arg @ref LL_EXTI_LINE_5
00620   *         @arg @ref LL_EXTI_LINE_6
00621   *         @arg @ref LL_EXTI_LINE_7
00622   *         @arg @ref LL_EXTI_LINE_8
00623   *         @arg @ref LL_EXTI_LINE_9
00624   *         @arg @ref LL_EXTI_LINE_10
00625   *         @arg @ref LL_EXTI_LINE_11
00626   *         @arg @ref LL_EXTI_LINE_12
00627   *         @arg @ref LL_EXTI_LINE_13
00628   *         @arg @ref LL_EXTI_LINE_14
00629   *         @arg @ref LL_EXTI_LINE_15
00630   *         @arg @ref LL_EXTI_LINE_16
00631   *         @arg @ref LL_EXTI_LINE_18
00632   *         @arg @ref LL_EXTI_LINE_19
00633   * @note   Please check each device line mapping for EXTI Line availability
00634   * @retval None
00635   */
00636 __STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
00637 {
00638   SET_BIT(EXTI->FTSR, ExtiLine);
00639 }
00640
00641
00642 /**
00643   * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
00644   * @note The configurable wakeup lines are edge-triggered. No glitch must be
00645   *       generated on these lines. If a Falling edge on a configurable interrupt
00646   *       line occurs during a write operation in the EXTI_FTSR register, the
00647   *       pending bit is not set.
00648   *       Rising and falling edge triggers can be set for the same interrupt line.
00649   *       In this case, both generate a trigger condition.
00650   * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
00651   * @param  ExtiLine This parameter can be a combination of the following values:
00652   *         @arg @ref LL_EXTI_LINE_0
00653   *         @arg @ref LL_EXTI_LINE_1
00654   *         @arg @ref LL_EXTI_LINE_2
00655   *         @arg @ref LL_EXTI_LINE_3
00656   *         @arg @ref LL_EXTI_LINE_4
00657   *         @arg @ref LL_EXTI_LINE_5
00658   *         @arg @ref LL_EXTI_LINE_6
00659   *         @arg @ref LL_EXTI_LINE_7
00660   *         @arg @ref LL_EXTI_LINE_8
00661   *         @arg @ref LL_EXTI_LINE_9
00662   *         @arg @ref LL_EXTI_LINE_10
00663   *         @arg @ref LL_EXTI_LINE_11
00664   *         @arg @ref LL_EXTI_LINE_12
00665   *         @arg @ref LL_EXTI_LINE_13
00666   *         @arg @ref LL_EXTI_LINE_14
00667   *         @arg @ref LL_EXTI_LINE_15
00668   *         @arg @ref LL_EXTI_LINE_16
00669   *         @arg @ref LL_EXTI_LINE_18
00670   *         @arg @ref LL_EXTI_LINE_19
00671   * @note   Please check each device line mapping for EXTI Line availability
00672   * @retval None
00673   */
00674 __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
00675 {
00676   CLEAR_BIT(EXTI->FTSR, ExtiLine);
00677 }
00678
00679
00680 /**
00681   * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
00682   * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
00683   * @param  ExtiLine This parameter can be a combination of the following values:
00684   *         @arg @ref LL_EXTI_LINE_0
00685   *         @arg @ref LL_EXTI_LINE_1
00686   *         @arg @ref LL_EXTI_LINE_2
00687   *         @arg @ref LL_EXTI_LINE_3
00688   *         @arg @ref LL_EXTI_LINE_4
00689   *         @arg @ref LL_EXTI_LINE_5
00690   *         @arg @ref LL_EXTI_LINE_6
00691   *         @arg @ref LL_EXTI_LINE_7
00692   *         @arg @ref LL_EXTI_LINE_8
00693   *         @arg @ref LL_EXTI_LINE_9
00694   *         @arg @ref LL_EXTI_LINE_10
00695   *         @arg @ref LL_EXTI_LINE_11
00696   *         @arg @ref LL_EXTI_LINE_12
00697   *         @arg @ref LL_EXTI_LINE_13
00698   *         @arg @ref LL_EXTI_LINE_14
00699   *         @arg @ref LL_EXTI_LINE_15
00700   *         @arg @ref LL_EXTI_LINE_16
00701   *         @arg @ref LL_EXTI_LINE_18
00702   *         @arg @ref LL_EXTI_LINE_19
00703   * @note   Please check each device line mapping for EXTI Line availability
00704   * @retval State of bit (1 or 0).
00705   */
00706 __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
00707 {
00708   return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
00709 }
00710
00711
00712 /**
00713   * @}
00714   */
00715
00716 /** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
00717   * @{
00718   */
00719
00720 /**
00721   * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
00722   * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
00723   *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
00724   *       resulting in an interrupt request generation.
00725   *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
00726   *       register (by writing a 1 into the bit)
00727   * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31
00728   * @param  ExtiLine This parameter can be a combination of the following values:
00729   *         @arg @ref LL_EXTI_LINE_0
00730   *         @arg @ref LL_EXTI_LINE_1
00731   *         @arg @ref LL_EXTI_LINE_2
00732   *         @arg @ref LL_EXTI_LINE_3
00733   *         @arg @ref LL_EXTI_LINE_4
00734   *         @arg @ref LL_EXTI_LINE_5
00735   *         @arg @ref LL_EXTI_LINE_6
00736   *         @arg @ref LL_EXTI_LINE_7
00737   *         @arg @ref LL_EXTI_LINE_8
00738   *         @arg @ref LL_EXTI_LINE_9
00739   *         @arg @ref LL_EXTI_LINE_10
00740   *         @arg @ref LL_EXTI_LINE_11
00741   *         @arg @ref LL_EXTI_LINE_12
00742   *         @arg @ref LL_EXTI_LINE_13
00743   *         @arg @ref LL_EXTI_LINE_14
00744   *         @arg @ref LL_EXTI_LINE_15
00745   *         @arg @ref LL_EXTI_LINE_16
00746   *         @arg @ref LL_EXTI_LINE_18
00747   *         @arg @ref LL_EXTI_LINE_19
00748   * @note   Please check each device line mapping for EXTI Line availability
00749   * @retval None
00750   */
00751 __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
00752 {
00753   SET_BIT(EXTI->SWIER, ExtiLine);
00754 }
00755
00756
00757 /**
00758   * @}
00759   */
00760
00761 /** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
00762   * @{
00763   */
00764
00765 /**
00766   * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
00767   * @note This bit is set when the selected edge event arrives on the interrupt
00768   *       line. This bit is cleared by writing a 1 to the bit.
00769   * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31
00770   * @param  ExtiLine This parameter can be a combination of the following values:
00771   *         @arg @ref LL_EXTI_LINE_0
00772   *         @arg @ref LL_EXTI_LINE_1
00773   *         @arg @ref LL_EXTI_LINE_2
00774   *         @arg @ref LL_EXTI_LINE_3
00775   *         @arg @ref LL_EXTI_LINE_4
00776   *         @arg @ref LL_EXTI_LINE_5
00777   *         @arg @ref LL_EXTI_LINE_6
00778   *         @arg @ref LL_EXTI_LINE_7
00779   *         @arg @ref LL_EXTI_LINE_8
00780   *         @arg @ref LL_EXTI_LINE_9
00781   *         @arg @ref LL_EXTI_LINE_10
00782   *         @arg @ref LL_EXTI_LINE_11
00783   *         @arg @ref LL_EXTI_LINE_12
00784   *         @arg @ref LL_EXTI_LINE_13
00785   *         @arg @ref LL_EXTI_LINE_14
00786   *         @arg @ref LL_EXTI_LINE_15
00787   *         @arg @ref LL_EXTI_LINE_16
00788   *         @arg @ref LL_EXTI_LINE_18
00789   *         @arg @ref LL_EXTI_LINE_19
00790   * @note   Please check each device line mapping for EXTI Line availability
00791   * @retval State of bit (1 or 0).
00792   */
00793 __STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
00794 {
00795   return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
00796 }
00797
00798
00799 /**
00800   * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
00801   * @note This bit is set when the selected edge event arrives on the interrupt
00802   *       line. This bit is cleared by writing a 1 to the bit.
00803   * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31
00804   * @param  ExtiLine This parameter can be a combination of the following values:
00805   *         @arg @ref LL_EXTI_LINE_0
00806   *         @arg @ref LL_EXTI_LINE_1
00807   *         @arg @ref LL_EXTI_LINE_2
00808   *         @arg @ref LL_EXTI_LINE_3
00809   *         @arg @ref LL_EXTI_LINE_4
00810   *         @arg @ref LL_EXTI_LINE_5
00811   *         @arg @ref LL_EXTI_LINE_6
00812   *         @arg @ref LL_EXTI_LINE_7
00813   *         @arg @ref LL_EXTI_LINE_8
00814   *         @arg @ref LL_EXTI_LINE_9
00815   *         @arg @ref LL_EXTI_LINE_10
00816   *         @arg @ref LL_EXTI_LINE_11
00817   *         @arg @ref LL_EXTI_LINE_12
00818   *         @arg @ref LL_EXTI_LINE_13
00819   *         @arg @ref LL_EXTI_LINE_14
00820   *         @arg @ref LL_EXTI_LINE_15
00821   *         @arg @ref LL_EXTI_LINE_16
00822   *         @arg @ref LL_EXTI_LINE_18
00823   *         @arg @ref LL_EXTI_LINE_19
00824   * @note   Please check each device line mapping for EXTI Line availability
00825   * @retval @note This bit is set when the selected edge event arrives on the interrupt
00826   */
00827 __STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
00828 {
00829   return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
00830 }
00831
00832
00833 /**
00834   * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
00835   * @note This bit is set when the selected edge event arrives on the interrupt
00836   *       line. This bit is cleared by writing a 1 to the bit.
00837   * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31
00838   * @param  ExtiLine This parameter can be a combination of the following values:
00839   *         @arg @ref LL_EXTI_LINE_0
00840   *         @arg @ref LL_EXTI_LINE_1
00841   *         @arg @ref LL_EXTI_LINE_2
00842   *         @arg @ref LL_EXTI_LINE_3
00843   *         @arg @ref LL_EXTI_LINE_4
00844   *         @arg @ref LL_EXTI_LINE_5
00845   *         @arg @ref LL_EXTI_LINE_6
00846   *         @arg @ref LL_EXTI_LINE_7
00847   *         @arg @ref LL_EXTI_LINE_8
00848   *         @arg @ref LL_EXTI_LINE_9
00849   *         @arg @ref LL_EXTI_LINE_10
00850   *         @arg @ref LL_EXTI_LINE_11
00851   *         @arg @ref LL_EXTI_LINE_12
00852   *         @arg @ref LL_EXTI_LINE_13
00853   *         @arg @ref LL_EXTI_LINE_14
00854   *         @arg @ref LL_EXTI_LINE_15
00855   *         @arg @ref LL_EXTI_LINE_16
00856   *         @arg @ref LL_EXTI_LINE_18
00857   *         @arg @ref LL_EXTI_LINE_19
00858   * @note   Please check each device line mapping for EXTI Line availability
00859   * @retval None
00860   */
00861 __STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
00862 {
00863   WRITE_REG(EXTI->PR, ExtiLine);
00864 }
00865
00866
00867 /**
00868   * @}
00869   */
00870
00871 #if defined(USE_FULL_LL_DRIVER)
00872 /** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
00873   * @{
00874   */
00875
00876 uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
00877 uint32_t LL_EXTI_DeInit(void);
00878 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
00879
00880
00881 /**
00882   * @}
00883   */
00884 #endif /* USE_FULL_LL_DRIVER */
00885
00886 /**
00887   * @}
00888   */
00889
00890 /**
00891   * @}
00892   */
00893
00894 #endif /* EXTI */
00895
00896 /**
00897   * @}
00898   */
00899
00900 #ifdef __cplusplus
00901 }
00902 #endif
00903
00904 #endif /* __STM32F1xx_LL_EXTI_H */
00905
00906 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_gpio.c Source File

  • File List
  • Globals
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  • STM32F1xx_HAL_Driver
  • Src
stm32f1xx_ll_gpio.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_gpio.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   GPIO LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_gpio.h"
00041 #include "stm32f1xx_ll_bus.h"
00042 #ifdef  USE_FULL_ASSERT
00043 #include "stm32_assert.h"
00044 #else
00045 #define assert_param(expr) ((void)0U)
00046 #endif
00047
00048 /** @addtogroup STM32F1xx_LL_Driver
00049   * @{
00050   */
00051
00052 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
00053
00054 /** @addtogroup GPIO_LL
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062 /** @addtogroup GPIO_LL_Private_Macros
00063   * @{
00064   */
00065 #define IS_LL_GPIO_PIN(__VALUE__)          ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
00066
00067 #define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_ANALOG)       ||\
00068                                             ((__VALUE__) == LL_GPIO_MODE_FLOATING)     ||\
00069                                             ((__VALUE__) == LL_GPIO_MODE_INPUT)        ||\
00070                                             ((__VALUE__) == LL_GPIO_MODE_OUTPUT)       ||\
00071                                             ((__VALUE__) == LL_GPIO_MODE_ALTERNATE))
00072
00073 #define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
00074                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
00075                                             ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
00076
00077 #define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
00078                                             ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
00079
00080 #define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_DOWN)   ||\
00081                                             ((__VALUE__) == LL_GPIO_PULL_UP))
00082
00083 /**
00084   * @}
00085   */
00086
00087 /* Private function prototypes -----------------------------------------------*/
00088
00089 /* Exported functions --------------------------------------------------------*/
00090 /** @addtogroup GPIO_LL_Exported_Functions
00091   * @{
00092   */
00093
00094 /** @addtogroup GPIO_LL_EF_Init
00095   * @{
00096   */
00097
00098 /**
00099   * @brief  De-initialize GPIO registers (Registers restored to their default values).
00100   * @param  GPIOx GPIO Port
00101   * @retval An ErrorStatus enumeration value:
00102   *          - SUCCESS: GPIO registers are de-initialized
00103   *          - ERROR:   Wrong GPIO Port
00104   */
00105 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
00106 {
00107   ErrorStatus status = SUCCESS;
00108
00109   /* Check the parameters */
00110   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00111
00112   /* Force and Release reset on clock of GPIOx Port */
00113   if (GPIOx == GPIOA)
00114   {
00115     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOA);
00116     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOA);
00117   }
00118   else if (GPIOx == GPIOB)
00119   {
00120     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOB);
00121     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOB);
00122   }
00123   else if (GPIOx == GPIOC)
00124   {
00125     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOC);
00126     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOC);
00127   }
00128   else if (GPIOx == GPIOD)
00129   {
00130     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOD);
00131     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOD);
00132   }
00133 #if defined(GPIOE)
00134   else if (GPIOx == GPIOE)
00135   {
00136     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOE);
00137     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOE);
00138   }
00139 #endif
00140 #if defined(GPIOF)
00141   else if (GPIOx == GPIOF)
00142   {
00143     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOF);
00144     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOF);
00145   }
00146 #endif
00147 #if defined(GPIOG)
00148   else if (GPIOx == GPIOG)
00149   {
00150     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOG);
00151     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOG);
00152   }
00153 #endif
00154   else
00155   {
00156     status = ERROR;
00157   }
00158
00159   return (status);
00160 }
00161
00162 /**
00163   * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
00164   * @param  GPIOx GPIO Port
00165   * @param  GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
00166   *         that contains the configuration information for the specified GPIO peripheral.
00167   * @retval An ErrorStatus enumeration value:
00168   *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
00169   *          - ERROR:   Not applicable
00170   */
00171 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
00172 {
00173   uint32_t pinpos     = 0x00000000U;
00174   uint32_t currentpin = 0x00000000U;
00175
00176   /* Check the parameters */
00177   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
00178   assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
00179   assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
00180   assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
00181
00182   /* ------------------------- Configure the port pins ---------------- */
00183   /* Initialize  pinpos on first pin set */
00184   pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
00185
00186   /* Configure the port pins */
00187   while ((((GPIO_InitStruct->Pin) & 0x0000FFFFU) >> pinpos) != 0x00000000U)
00188   {
00189     /* Get current io position */
00190     if(pinpos <8 )
00191     {
00192       currentpin = (GPIO_InitStruct->Pin) & (0x00000101U << pinpos);
00193     }
00194     else
00195     {
00196       currentpin = (GPIO_InitStruct->Pin) & ((0x00010001U << (pinpos-8)) | 0x04000000U);
00197     }
00198
00199     if (currentpin)
00200     {
00201       /* Pin Mode configuration */
00202       LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
00203
00204       /* Pull-up Pull down resistor configuration*/
00205       LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
00206
00207       if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_FLOATING))
00208       {
00209         /* Speed mode configuration */
00210         LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
00211       }
00212     }
00213     pinpos++;
00214   }
00215
00216   if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_FLOATING))
00217   {
00218     /* Check Output mode parameters */
00219     assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
00220
00221     /* Output mode configuration*/
00222     LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
00223   }
00224   return (SUCCESS);
00225 }
00226
00227 /**
00228   * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
00229   * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
00230   *                          whose fields will be set to default values.
00231   * @retval None
00232   */
00233
00234 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
00235 {
00236   /* Reset GPIO init structure parameters values */
00237   GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
00238   GPIO_InitStruct->Mode       = LL_GPIO_MODE_FLOATING;
00239   GPIO_InitStruct->Speed      = 0x00000000U;
00240   GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
00241   GPIO_InitStruct->Pull       = LL_GPIO_PULL_DOWN;
00242 }
00243
00244 /**
00245   * @}
00246   */
00247
00248 /**
00249   * @}
00250   */
00251
00252 /**
00253   * @}
00254   */
00255
00256 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
00257
00258 /**
00259   * @}
00260   */
00261
00262 #endif /* USE_FULL_LL_DRIVER */
00263
00264 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00265
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_gpio.h Source File

  • File List
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  • STM32F1xx_HAL_Driver
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stm32f1xx_ll_gpio.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_gpio.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of GPIO LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_GPIO_H
00040 #define __STM32F1xx_LL_GPIO_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
00054
00055 /** @defgroup GPIO_LL GPIO
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
00064   * @{
00065   */
00066 /**
00067   * @}
00068   */
00069
00070
00071 /* Private macros ------------------------------------------------------------*/
00072 #if defined(USE_FULL_LL_DRIVER)
00073 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
00074   * @{
00075   */
00076
00077 /**
00078   * @}
00079   */
00080 #endif /*USE_FULL_LL_DRIVER*/
00081
00082 /* Exported types ------------------------------------------------------------*/
00083 #if defined(USE_FULL_LL_DRIVER)
00084 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
00085   * @{
00086   */
00087
00088 /**
00089   * @brief LL GPIO Init Structure definition
00090   */
00091 typedef struct
00092 {
00093   uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
00094                               This parameter can be any value of @ref GPIO_LL_EC_PIN */
00095
00096   uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
00097                               This parameter can be a value of @ref GPIO_LL_EC_MODE.
00098
00099                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
00100
00101   uint32_t Speed;        /*!< Specifies the speed for the selected pins.
00102                               This parameter can be a value of @ref GPIO_LL_EC_SPEED.
00103
00104                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
00105
00106   uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
00107                               This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
00108
00109                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
00110
00111   uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
00112                               This parameter can be a value of @ref GPIO_LL_EC_PULL.
00113
00114                               GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
00115 }LL_GPIO_InitTypeDef;
00116
00117 /**
00118   * @}
00119   */
00120 #endif /* USE_FULL_LL_DRIVER */
00121
00122 /* Exported constants --------------------------------------------------------*/
00123 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
00124   * @{
00125   */
00126
00127 /** @defgroup GPIO_LL_EC_PIN PIN
00128   * @{
00129   */
00130 #define LL_GPIO_PIN_0                    (GPIO_BSRR_BS0 << 8)  | 0x00000001U  /*!< Select pin 0 */
00131 #define LL_GPIO_PIN_1                    (GPIO_BSRR_BS1 << 8)  | 0x00000002U  /*!< Select pin 1 */
00132 #define LL_GPIO_PIN_2                    (GPIO_BSRR_BS2 << 8)  | 0x00000004U  /*!< Select pin 2 */
00133 #define LL_GPIO_PIN_3                    (GPIO_BSRR_BS3 << 8)  | 0x00000008U  /*!< Select pin 3 */
00134 #define LL_GPIO_PIN_4                    (GPIO_BSRR_BS4 << 8)  | 0x00000010U  /*!< Select pin 4 */
00135 #define LL_GPIO_PIN_5                    (GPIO_BSRR_BS5 << 8)  | 0x00000020U  /*!< Select pin 5 */
00136 #define LL_GPIO_PIN_6                    (GPIO_BSRR_BS6 << 8)  | 0x00000040U  /*!< Select pin 6 */
00137 #define LL_GPIO_PIN_7                    (GPIO_BSRR_BS7 << 8)  | 0x00000080U  /*!< Select pin 7 */
00138 #define LL_GPIO_PIN_8                    (GPIO_BSRR_BS8 << 8)  | 0x04000001U  /*!< Select pin 8 */
00139 #define LL_GPIO_PIN_9                    (GPIO_BSRR_BS9 << 8)  | 0x04000002U  /*!< Select pin 9 */
00140 #define LL_GPIO_PIN_10                   (GPIO_BSRR_BS10 << 8) | 0x04000004U  /*!< Select pin 10 */
00141 #define LL_GPIO_PIN_11                   (GPIO_BSRR_BS11 << 8) | 0x04000008U  /*!< Select pin 11 */
00142 #define LL_GPIO_PIN_12                   (GPIO_BSRR_BS12 << 8) | 0x04000010U  /*!< Select pin 12 */
00143 #define LL_GPIO_PIN_13                   (GPIO_BSRR_BS13 << 8) | 0x04000020U  /*!< Select pin 13 */
00144 #define LL_GPIO_PIN_14                   (GPIO_BSRR_BS14 << 8) | 0x04000040U  /*!< Select pin 14 */
00145 #define LL_GPIO_PIN_15                   (GPIO_BSRR_BS15 << 8) | 0x04000080U  /*!< Select pin 15 */
00146 #define LL_GPIO_PIN_ALL                  (LL_GPIO_PIN_0  | LL_GPIO_PIN_1  | LL_GPIO_PIN_2  | \
00147                                           LL_GPIO_PIN_3  | LL_GPIO_PIN_4  | LL_GPIO_PIN_5  | \
00148                                           LL_GPIO_PIN_6  | LL_GPIO_PIN_7  | LL_GPIO_PIN_8  | \
00149                                           LL_GPIO_PIN_9  | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
00150                                           LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
00151                                           LL_GPIO_PIN_15) /*!< Select all pins */
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup GPIO_LL_EC_MODE Mode
00157   * @{
00158   */
00159 #define LL_GPIO_MODE_ANALOG                0x00000000U   /*!< Select analog mode */
00160 #define LL_GPIO_MODE_FLOATING              GPIO_CRL_CNF0_0   /*!< Select floating mode */
00161 #define LL_GPIO_MODE_INPUT                 GPIO_CRL_CNF0_1   /*!< Select input mode */
00162 #define LL_GPIO_MODE_OUTPUT                GPIO_CRL_MODE0_0   /*!< Select general purpose output mode */
00163 #define LL_GPIO_MODE_ALTERNATE             (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */
00164 /**
00165   * @}
00166   */
00167
00168 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
00169   * @{
00170   */
00171 #define LL_GPIO_OUTPUT_PUSHPULL            0x00000000U /*!< Select push-pull as output type */
00172 #define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup GPIO_LL_EC_SPEED Output Speed
00178   * @{
00179   */
00180 #define LL_GPIO_MODE_OUTPUT_10MHz      GPIO_CRL_MODE0_0            /*!< Select Output mode, max speed 10 MHz */
00181 #define LL_GPIO_MODE_OUTPUT_2MHz       GPIO_CRL_MODE0_1            /*!< Select Output mode, max speed 20 MHz */
00182 #define LL_GPIO_MODE_OUTPUT_50MHz      GPIO_CRL_MODE0              /*!< Select Output mode, max speed 50 MHz */
00183 /**
00184   * @}
00185   */
00186
00187 #define LL_GPIO_SPEED_FREQ_LOW           LL_GPIO_MODE_OUTPUT_2MHz    /*!< Select I/O low output speed    */
00188 #define LL_GPIO_SPEED_FREQ_MEDIUM        LL_GPIO_MODE_OUTPUT_10MHz   /*!< Select I/O medium output speed */
00189 #define LL_GPIO_SPEED_FREQ_HIGH          LL_GPIO_MODE_OUTPUT_50MHz   /*!< Select I/O high output speed   */
00190
00191 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
00192   * @{
00193   */
00194 #define LL_GPIO_PULL_DOWN                  0x00000000U    /*!< Select I/O pull down */
00195 #define LL_GPIO_PULL_UP                    GPIO_ODR_ODR0  /*!< Select I/O pull up */
00196
00197 /**
00198   * @}
00199   */
00200
00201 /** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
00202   * @{
00203   */
00204
00205 #define LL_GPIO_AF_EVENTOUT_PIN_0        AFIO_EVCR_PIN_PX0   /*!< EVENTOUT on pin 0 */
00206 #define LL_GPIO_AF_EVENTOUT_PIN_1        AFIO_EVCR_PIN_PX1   /*!< EVENTOUT on pin 1 */
00207 #define LL_GPIO_AF_EVENTOUT_PIN_2        AFIO_EVCR_PIN_PX2   /*!< EVENTOUT on pin 2 */
00208 #define LL_GPIO_AF_EVENTOUT_PIN_3        AFIO_EVCR_PIN_PX3   /*!< EVENTOUT on pin 3 */
00209 #define LL_GPIO_AF_EVENTOUT_PIN_4        AFIO_EVCR_PIN_PX4   /*!< EVENTOUT on pin 4 */
00210 #define LL_GPIO_AF_EVENTOUT_PIN_5        AFIO_EVCR_PIN_PX5   /*!< EVENTOUT on pin 5 */
00211 #define LL_GPIO_AF_EVENTOUT_PIN_6        AFIO_EVCR_PIN_PX6   /*!< EVENTOUT on pin 6 */
00212 #define LL_GPIO_AF_EVENTOUT_PIN_7        AFIO_EVCR_PIN_PX7   /*!< EVENTOUT on pin 7 */
00213 #define LL_GPIO_AF_EVENTOUT_PIN_8        AFIO_EVCR_PIN_PX8   /*!< EVENTOUT on pin 8 */
00214 #define LL_GPIO_AF_EVENTOUT_PIN_9        AFIO_EVCR_PIN_PX9   /*!< EVENTOUT on pin 9 */
00215 #define LL_GPIO_AF_EVENTOUT_PIN_10       AFIO_EVCR_PIN_PX10  /*!< EVENTOUT on pin 10 */
00216 #define LL_GPIO_AF_EVENTOUT_PIN_11       AFIO_EVCR_PIN_PX11  /*!< EVENTOUT on pin 11 */
00217 #define LL_GPIO_AF_EVENTOUT_PIN_12       AFIO_EVCR_PIN_PX12  /*!< EVENTOUT on pin 12 */
00218 #define LL_GPIO_AF_EVENTOUT_PIN_13       AFIO_EVCR_PIN_PX13  /*!< EVENTOUT on pin 13 */
00219 #define LL_GPIO_AF_EVENTOUT_PIN_14       AFIO_EVCR_PIN_PX14  /*!< EVENTOUT on pin 14 */
00220 #define LL_GPIO_AF_EVENTOUT_PIN_15       AFIO_EVCR_PIN_PX15  /*!< EVENTOUT on pin 15 */
00221
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
00227   * @{
00228   */
00229
00230 #define LL_GPIO_AF_EVENTOUT_PORT_A       AFIO_EVCR_PORT_PA  /*!< EVENTOUT on port A */
00231 #define LL_GPIO_AF_EVENTOUT_PORT_B       AFIO_EVCR_PORT_PB  /*!< EVENTOUT on port B */
00232 #define LL_GPIO_AF_EVENTOUT_PORT_C       AFIO_EVCR_PORT_PC  /*!< EVENTOUT on port C */
00233 #define LL_GPIO_AF_EVENTOUT_PORT_D       AFIO_EVCR_PORT_PD  /*!< EVENTOUT on port D */
00234 #define LL_GPIO_AF_EVENTOUT_PORT_E       AFIO_EVCR_PORT_PE  /*!< EVENTOUT on port E */
00235
00236 /**
00237   * @}
00238   */
00239
00240 /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
00241   * @{
00242   */
00243 #define LL_GPIO_AF_EXTI_PORTA            (uint32_t)0   /*!< EXTI PORT A */
00244 #define LL_GPIO_AF_EXTI_PORTB            (uint32_t)1   /*!< EXTI PORT B */
00245 #define LL_GPIO_AF_EXTI_PORTC            (uint32_t)2   /*!< EXTI PORT C */
00246 #define LL_GPIO_AF_EXTI_PORTD            (uint32_t)3   /*!< EXTI PORT D */
00247 #define LL_GPIO_AF_EXTI_PORTE            (uint32_t)4   /*!< EXTI PORT E */
00248 #define LL_GPIO_AF_EXTI_PORTF            (uint32_t)5   /*!< EXTI PORT F */
00249 #define LL_GPIO_AF_EXTI_PORTG            (uint32_t)6   /*!< EXTI PORT G */
00250 /**
00251   * @}
00252   */
00253
00254 /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
00255   * @{
00256   */
00257 #define LL_GPIO_AF_EXTI_LINE0            (uint32_t)(0x000FU << 16 | 0)  /*!< EXTI_POSITION_0  | EXTICR[0] */
00258 #define LL_GPIO_AF_EXTI_LINE1            (uint32_t)(0x00F0U << 16 | 0)  /*!< EXTI_POSITION_4  | EXTICR[0] */
00259 #define LL_GPIO_AF_EXTI_LINE2            (uint32_t)(0x0F00U << 16 | 0)  /*!< EXTI_POSITION_8  | EXTICR[0] */
00260 #define LL_GPIO_AF_EXTI_LINE3            (uint32_t)(0xF000U << 16 | 0)  /*!< EXTI_POSITION_12 | EXTICR[0] */
00261 #define LL_GPIO_AF_EXTI_LINE4            (uint32_t)(0x000FU << 16 | 1)  /*!< EXTI_POSITION_0  | EXTICR[1] */
00262 #define LL_GPIO_AF_EXTI_LINE5            (uint32_t)(0x00F0U << 16 | 1)  /*!< EXTI_POSITION_4  | EXTICR[1] */
00263 #define LL_GPIO_AF_EXTI_LINE6            (uint32_t)(0x0F00U << 16 | 1)  /*!< EXTI_POSITION_8  | EXTICR[1] */
00264 #define LL_GPIO_AF_EXTI_LINE7            (uint32_t)(0xF000U << 16 | 1)  /*!< EXTI_POSITION_12 | EXTICR[1] */
00265 #define LL_GPIO_AF_EXTI_LINE8            (uint32_t)(0x000FU << 16 | 2)  /*!< EXTI_POSITION_0  | EXTICR[2] */
00266 #define LL_GPIO_AF_EXTI_LINE9            (uint32_t)(0x00F0U << 16 | 2)  /*!< EXTI_POSITION_4  | EXTICR[2] */
00267 #define LL_GPIO_AF_EXTI_LINE10           (uint32_t)(0x0F00U << 16 | 2)  /*!< EXTI_POSITION_8  | EXTICR[2] */
00268 #define LL_GPIO_AF_EXTI_LINE11           (uint32_t)(0xF000U << 16 | 2)  /*!< EXTI_POSITION_12 | EXTICR[2] */
00269 #define LL_GPIO_AF_EXTI_LINE12           (uint32_t)(0x000FU << 16 | 3)  /*!< EXTI_POSITION_0  | EXTICR[3] */
00270 #define LL_GPIO_AF_EXTI_LINE13           (uint32_t)(0x00F0U << 16 | 3)  /*!< EXTI_POSITION_4  | EXTICR[3] */
00271 #define LL_GPIO_AF_EXTI_LINE14           (uint32_t)(0x0F00U << 16 | 3)  /*!< EXTI_POSITION_8  | EXTICR[3] */
00272 #define LL_GPIO_AF_EXTI_LINE15           (uint32_t)(0xF000U << 16 | 3)  /*!< EXTI_POSITION_12 | EXTICR[3] */
00273 /**
00274   * @}
00275   */
00276
00277 /**
00278   * @}
00279   */
00280
00281 /* Exported macro ------------------------------------------------------------*/
00282 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
00283   * @{
00284   */
00285
00286 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
00287   * @{
00288   */
00289
00290 /**
00291   * @brief  Write a value in GPIO register
00292   * @param  __INSTANCE__ GPIO Instance
00293   * @param  __REG__ Register to be written
00294   * @param  __VALUE__ Value to be written in the register
00295   * @retval None
00296   */
00297 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00298
00299 /**
00300   * @brief  Read a value in GPIO register
00301   * @param  __INSTANCE__ GPIO Instance
00302   * @param  __REG__ Register to be read
00303   * @retval Register value
00304   */
00305 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00306 /**
00307   * @}
00308   */
00309
00310 /**
00311   * @}
00312   */
00313
00314 /* Exported functions --------------------------------------------------------*/
00315 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
00316   * @{
00317   */
00318
00319 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
00320   * @{
00321   */
00322
00323 /**
00324   * @brief  Configure gpio mode for a dedicated pin on dedicated port.
00325   * @note   I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
00326   *         Alternate function Output.
00327   * @note   Warning: only one pin can be passed as parameter.
00328   * @rmtoll CRL        CNFy         LL_GPIO_SetPinMode
00329   * @rmtoll CRL        MODEy        LL_GPIO_SetPinMode
00330   * @rmtoll CRH        CNFy         LL_GPIO_SetPinMode
00331   * @rmtoll CRH        MODEy        LL_GPIO_SetPinMode
00332   * @param  GPIOx GPIO Port
00333   * @param  Pin This parameter can be one of the following values:
00334   *         @arg @ref LL_GPIO_PIN_0
00335   *         @arg @ref LL_GPIO_PIN_1
00336   *         @arg @ref LL_GPIO_PIN_2
00337   *         @arg @ref LL_GPIO_PIN_3
00338   *         @arg @ref LL_GPIO_PIN_4
00339   *         @arg @ref LL_GPIO_PIN_5
00340   *         @arg @ref LL_GPIO_PIN_6
00341   *         @arg @ref LL_GPIO_PIN_7
00342   *         @arg @ref LL_GPIO_PIN_8
00343   *         @arg @ref LL_GPIO_PIN_9
00344   *         @arg @ref LL_GPIO_PIN_10
00345   *         @arg @ref LL_GPIO_PIN_11
00346   *         @arg @ref LL_GPIO_PIN_12
00347   *         @arg @ref LL_GPIO_PIN_13
00348   *         @arg @ref LL_GPIO_PIN_14
00349   *         @arg @ref LL_GPIO_PIN_15
00350   * @param  Mode This parameter can be one of the following values:
00351   *         @arg @ref LL_GPIO_MODE_ANALOG
00352   *         @arg @ref LL_GPIO_MODE_FLOATING
00353   *         @arg @ref LL_GPIO_MODE_INPUT
00354   *         @arg @ref LL_GPIO_MODE_OUTPUT
00355   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00356   * @retval None
00357   */
00358 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
00359 {
00360   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
00361   MODIFY_REG(*pReg, ((GPIO_CRL_CNF0|GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
00362 }
00363
00364 /**
00365   * @brief  Return gpio mode for a dedicated pin on dedicated port.
00366   * @note   I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
00367   *         Alternate function Output.
00368   * @note   Warning: only one pin can be passed as parameter.
00369   * @rmtoll CRL        CNFy         LL_GPIO_GetPinMode
00370   * @rmtoll CRL        MODEy        LL_GPIO_GetPinMode
00371   * @rmtoll CRH        CNFy         LL_GPIO_GetPinMode
00372   * @rmtoll CRH        MODEy        LL_GPIO_GetPinMode
00373   * @param  GPIOx GPIO Port
00374   * @param  Pin This parameter can be one of the following values:
00375   *         @arg @ref LL_GPIO_PIN_0
00376   *         @arg @ref LL_GPIO_PIN_1
00377   *         @arg @ref LL_GPIO_PIN_2
00378   *         @arg @ref LL_GPIO_PIN_3
00379   *         @arg @ref LL_GPIO_PIN_4
00380   *         @arg @ref LL_GPIO_PIN_5
00381   *         @arg @ref LL_GPIO_PIN_6
00382   *         @arg @ref LL_GPIO_PIN_7
00383   *         @arg @ref LL_GPIO_PIN_8
00384   *         @arg @ref LL_GPIO_PIN_9
00385   *         @arg @ref LL_GPIO_PIN_10
00386   *         @arg @ref LL_GPIO_PIN_11
00387   *         @arg @ref LL_GPIO_PIN_12
00388   *         @arg @ref LL_GPIO_PIN_13
00389   *         @arg @ref LL_GPIO_PIN_14
00390   *         @arg @ref LL_GPIO_PIN_15
00391   * @retval Returned value can be one of the following values:
00392   *         @arg @ref LL_GPIO_MODE_ANALOG
00393   *         @arg @ref LL_GPIO_MODE_FLOATING
00394   *         @arg @ref LL_GPIO_MODE_INPUT
00395   *         @arg @ref LL_GPIO_MODE_OUTPUT
00396   *         @arg @ref LL_GPIO_MODE_ALTERNATE
00397   */
00398 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
00399 {
00400   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
00401   return (uint32_t)(READ_BIT(*pReg,
00402                              ((GPIO_CRL_CNF0|GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
00403 }
00404
00405 /**
00406   * @brief  Configure gpio speed for a dedicated pin on dedicated port.
00407   * @note   I/O speed can be Low, Medium or Fast speed.
00408   * @note   Warning: only one pin can be passed as parameter.
00409   * @note   Refer to datasheet for frequency specifications and the power
00410   *         supply and load conditions for each speed.
00411   * @rmtoll CRL      MODEy       LL_GPIO_SetPinSpeed
00412   * @rmtoll CRH      MODEy       LL_GPIO_SetPinSpeed
00413   * @param  GPIOx GPIO Port
00414   * @param  Pin This parameter can be one of the following values:
00415   *         @arg @ref LL_GPIO_PIN_0
00416   *         @arg @ref LL_GPIO_PIN_1
00417   *         @arg @ref LL_GPIO_PIN_2
00418   *         @arg @ref LL_GPIO_PIN_3
00419   *         @arg @ref LL_GPIO_PIN_4
00420   *         @arg @ref LL_GPIO_PIN_5
00421   *         @arg @ref LL_GPIO_PIN_6
00422   *         @arg @ref LL_GPIO_PIN_7
00423   *         @arg @ref LL_GPIO_PIN_8
00424   *         @arg @ref LL_GPIO_PIN_9
00425   *         @arg @ref LL_GPIO_PIN_10
00426   *         @arg @ref LL_GPIO_PIN_11
00427   *         @arg @ref LL_GPIO_PIN_12
00428   *         @arg @ref LL_GPIO_PIN_13
00429   *         @arg @ref LL_GPIO_PIN_14
00430   *         @arg @ref LL_GPIO_PIN_15
00431   * @param  Speed This parameter can be one of the following values:
00432   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00433   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00434   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00435   * @retval None
00436   */
00437 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
00438 {
00439   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
00440   MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
00441              (Speed << (POSITION_VAL(Pin) * 4U)));
00442 }
00443
00444 /**
00445   * @brief  Return gpio speed for a dedicated pin on dedicated port.
00446   * @note   I/O speed can be Low, Medium, Fast or High speed.
00447   * @note   Warning: only one pin can be passed as parameter.
00448   * @note   Refer to datasheet for frequency specifications and the power
00449   *         supply and load conditions for each speed.
00450   * @rmtoll CRL      MODEy       LL_GPIO_GetPinSpeed
00451   * @rmtoll CRH      MODEy       LL_GPIO_GetPinSpeed
00452   * @param  GPIOx GPIO Port
00453   * @param  Pin This parameter can be one of the following values:
00454   *         @arg @ref LL_GPIO_PIN_0
00455   *         @arg @ref LL_GPIO_PIN_1
00456   *         @arg @ref LL_GPIO_PIN_2
00457   *         @arg @ref LL_GPIO_PIN_3
00458   *         @arg @ref LL_GPIO_PIN_4
00459   *         @arg @ref LL_GPIO_PIN_5
00460   *         @arg @ref LL_GPIO_PIN_6
00461   *         @arg @ref LL_GPIO_PIN_7
00462   *         @arg @ref LL_GPIO_PIN_8
00463   *         @arg @ref LL_GPIO_PIN_9
00464   *         @arg @ref LL_GPIO_PIN_10
00465   *         @arg @ref LL_GPIO_PIN_11
00466   *         @arg @ref LL_GPIO_PIN_12
00467   *         @arg @ref LL_GPIO_PIN_13
00468   *         @arg @ref LL_GPIO_PIN_14
00469   *         @arg @ref LL_GPIO_PIN_15
00470   * @retval Returned value can be one of the following values:
00471   *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
00472   *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
00473   *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
00474   */
00475 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
00476 {
00477   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
00478   return (uint32_t)(READ_BIT(*pReg,
00479                              (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
00480 }
00481
00482 /**
00483   * @brief  Configure gpio output type for several pins on dedicated port.
00484   * @note   Output type as to be set when gpio pin is in output or
00485   *         alternate modes. Possible type are Push-pull or Open-drain.
00486   * @rmtoll CRL       MODEy           LL_GPIO_SetPinOutputType
00487   * @rmtoll CRH       MODEy           LL_GPIO_SetPinOutputType
00488   * @param  GPIOx GPIO Port
00489   * @param  Pin This parameter can be a combination of the following values:
00490   *         @arg @ref LL_GPIO_PIN_0
00491   *         @arg @ref LL_GPIO_PIN_1
00492   *         @arg @ref LL_GPIO_PIN_2
00493   *         @arg @ref LL_GPIO_PIN_3
00494   *         @arg @ref LL_GPIO_PIN_4
00495   *         @arg @ref LL_GPIO_PIN_5
00496   *         @arg @ref LL_GPIO_PIN_6
00497   *         @arg @ref LL_GPIO_PIN_7
00498   *         @arg @ref LL_GPIO_PIN_8
00499   *         @arg @ref LL_GPIO_PIN_9
00500   *         @arg @ref LL_GPIO_PIN_10
00501   *         @arg @ref LL_GPIO_PIN_11
00502   *         @arg @ref LL_GPIO_PIN_12
00503   *         @arg @ref LL_GPIO_PIN_13
00504   *         @arg @ref LL_GPIO_PIN_14
00505   *         @arg @ref LL_GPIO_PIN_15
00506   *         @arg @ref LL_GPIO_PIN_ALL
00507   * @param  OutputType This parameter can be one of the following values:
00508   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00509   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00510   * @retval None
00511   */
00512 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
00513 {
00514   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
00515   MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
00516              (OutputType << (POSITION_VAL(Pin) * 4U)));
00517 }
00518
00519 /**
00520   * @brief  Return gpio output type for several pins on dedicated port.
00521   * @note   Output type as to be set when gpio pin is in output or
00522   *         alternate modes. Possible type are Push-pull or Open-drain.
00523   * @note   Warning: only one pin can be passed as parameter.
00524   * @rmtoll CRL       MODEy       LL_GPIO_GetPinOutputType
00525   * @rmtoll CRH       MODEy       LL_GPIO_GetPinOutputType
00526   * @param  GPIOx GPIO Port
00527   * @param  Pin This parameter can be one of the following values:
00528   *         @arg @ref LL_GPIO_PIN_0
00529   *         @arg @ref LL_GPIO_PIN_1
00530   *         @arg @ref LL_GPIO_PIN_2
00531   *         @arg @ref LL_GPIO_PIN_3
00532   *         @arg @ref LL_GPIO_PIN_4
00533   *         @arg @ref LL_GPIO_PIN_5
00534   *         @arg @ref LL_GPIO_PIN_6
00535   *         @arg @ref LL_GPIO_PIN_7
00536   *         @arg @ref LL_GPIO_PIN_8
00537   *         @arg @ref LL_GPIO_PIN_9
00538   *         @arg @ref LL_GPIO_PIN_10
00539   *         @arg @ref LL_GPIO_PIN_11
00540   *         @arg @ref LL_GPIO_PIN_12
00541   *         @arg @ref LL_GPIO_PIN_13
00542   *         @arg @ref LL_GPIO_PIN_14
00543   *         @arg @ref LL_GPIO_PIN_15
00544   *         @arg @ref LL_GPIO_PIN_ALL
00545   * @retval Returned value can be one of the following values:
00546   *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
00547   *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
00548   */
00549 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
00550 {
00551   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
00552   return (uint32_t)(READ_BIT(*pReg,
00553                             (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
00554
00555 }
00556
00557 /**
00558   * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
00559   * @note   Warning: only one pin can be passed as parameter.
00560   * @rmtoll ODR        ODR         LL_GPIO_SetPinPull
00561   * @param  GPIOx GPIO Port
00562   * @param  Pin This parameter can be one of the following values:
00563   *         @arg @ref LL_GPIO_PIN_0
00564   *         @arg @ref LL_GPIO_PIN_1
00565   *         @arg @ref LL_GPIO_PIN_2
00566   *         @arg @ref LL_GPIO_PIN_3
00567   *         @arg @ref LL_GPIO_PIN_4
00568   *         @arg @ref LL_GPIO_PIN_5
00569   *         @arg @ref LL_GPIO_PIN_6
00570   *         @arg @ref LL_GPIO_PIN_7
00571   *         @arg @ref LL_GPIO_PIN_8
00572   *         @arg @ref LL_GPIO_PIN_9
00573   *         @arg @ref LL_GPIO_PIN_10
00574   *         @arg @ref LL_GPIO_PIN_11
00575   *         @arg @ref LL_GPIO_PIN_12
00576   *         @arg @ref LL_GPIO_PIN_13
00577   *         @arg @ref LL_GPIO_PIN_14
00578   *         @arg @ref LL_GPIO_PIN_15
00579   * @param  Pull This parameter can be one of the following values:
00580   *         @arg @ref LL_GPIO_PULL_DOWN
00581   *         @arg @ref LL_GPIO_PULL_UP
00582   * @retval None
00583   */
00584 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
00585 {
00586   MODIFY_REG(GPIOx->ODR, (Pin>>8) , Pull << (POSITION_VAL(Pin>>8)));
00587 }
00588
00589 /**
00590   * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
00591   * @note   Warning: only one pin can be passed as parameter.
00592   * @rmtoll ODR        ODR         LL_GPIO_GetPinPull
00593   * @param  GPIOx GPIO Port
00594   * @param  Pin This parameter can be one of the following values:
00595   *         @arg @ref LL_GPIO_PIN_0
00596   *         @arg @ref LL_GPIO_PIN_1
00597   *         @arg @ref LL_GPIO_PIN_2
00598   *         @arg @ref LL_GPIO_PIN_3
00599   *         @arg @ref LL_GPIO_PIN_4
00600   *         @arg @ref LL_GPIO_PIN_5
00601   *         @arg @ref LL_GPIO_PIN_6
00602   *         @arg @ref LL_GPIO_PIN_7
00603   *         @arg @ref LL_GPIO_PIN_8
00604   *         @arg @ref LL_GPIO_PIN_9
00605   *         @arg @ref LL_GPIO_PIN_10
00606   *         @arg @ref LL_GPIO_PIN_11
00607   *         @arg @ref LL_GPIO_PIN_12
00608   *         @arg @ref LL_GPIO_PIN_13
00609   *         @arg @ref LL_GPIO_PIN_14
00610   *         @arg @ref LL_GPIO_PIN_15
00611   * @retval Returned value can be one of the following values:
00612   *         @arg @ref LL_GPIO_PULL_DOWN
00613   *         @arg @ref LL_GPIO_PULL_UP
00614   */
00615 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
00616 {
00617   return (uint32_t)(READ_BIT(GPIOx->ODR,
00618                              (GPIO_ODR_ODR0 << (POSITION_VAL(Pin>>8)))) >> (POSITION_VAL(Pin>>8)));
00619 }
00620
00621 /**
00622   * @brief  Lock configuration of several pins for a dedicated port.
00623   * @note   When the lock sequence has been applied on a port bit, the
00624   *         value of this port bit can no longer be modified until the
00625   *         next reset.
00626   * @note   Each lock bit freezes a specific configuration register
00627   *         (control and alternate function registers).
00628   * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
00629   * @param  GPIOx GPIO Port
00630   * @param  PinMask This parameter can be a combination of the following values:
00631   *         @arg @ref LL_GPIO_PIN_0
00632   *         @arg @ref LL_GPIO_PIN_1
00633   *         @arg @ref LL_GPIO_PIN_2
00634   *         @arg @ref LL_GPIO_PIN_3
00635   *         @arg @ref LL_GPIO_PIN_4
00636   *         @arg @ref LL_GPIO_PIN_5
00637   *         @arg @ref LL_GPIO_PIN_6
00638   *         @arg @ref LL_GPIO_PIN_7
00639   *         @arg @ref LL_GPIO_PIN_8
00640   *         @arg @ref LL_GPIO_PIN_9
00641   *         @arg @ref LL_GPIO_PIN_10
00642   *         @arg @ref LL_GPIO_PIN_11
00643   *         @arg @ref LL_GPIO_PIN_12
00644   *         @arg @ref LL_GPIO_PIN_13
00645   *         @arg @ref LL_GPIO_PIN_14
00646   *         @arg @ref LL_GPIO_PIN_15
00647   *         @arg @ref LL_GPIO_PIN_ALL
00648   * @retval None
00649   */
00650 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00651 {
00652   __IO uint32_t temp;
00653   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> 8) & 0x0000FFFFU));
00654   WRITE_REG(GPIOx->LCKR, ((PinMask >>8 ) & 0x0000FFFFU));
00655   WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask>>8) & 0x0000FFFFU));
00656   temp = READ_REG(GPIOx->LCKR);
00657   (void) temp;
00658 }
00659
00660 /**
00661   * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
00662   * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
00663   * @param  GPIOx GPIO Port
00664   * @param  PinMask This parameter can be a combination of the following values:
00665   *         @arg @ref LL_GPIO_PIN_0
00666   *         @arg @ref LL_GPIO_PIN_1
00667   *         @arg @ref LL_GPIO_PIN_2
00668   *         @arg @ref LL_GPIO_PIN_3
00669   *         @arg @ref LL_GPIO_PIN_4
00670   *         @arg @ref LL_GPIO_PIN_5
00671   *         @arg @ref LL_GPIO_PIN_6
00672   *         @arg @ref LL_GPIO_PIN_7
00673   *         @arg @ref LL_GPIO_PIN_8
00674   *         @arg @ref LL_GPIO_PIN_9
00675   *         @arg @ref LL_GPIO_PIN_10
00676   *         @arg @ref LL_GPIO_PIN_11
00677   *         @arg @ref LL_GPIO_PIN_12
00678   *         @arg @ref LL_GPIO_PIN_13
00679   *         @arg @ref LL_GPIO_PIN_14
00680   *         @arg @ref LL_GPIO_PIN_15
00681   *         @arg @ref LL_GPIO_PIN_ALL
00682   * @retval State of bit (1 or 0).
00683   */
00684 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00685 {
00686   return (READ_BIT(GPIOx->LCKR, ((PinMask >> 8 ) & 0x0000FFFFU)) == ((PinMask >>8 ) & 0x0000FFFFU));
00687 }
00688
00689 /**
00690   * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
00691   * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
00692   * @param  GPIOx GPIO Port
00693   * @retval State of bit (1 or 0).
00694   */
00695 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
00696 {
00697   return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
00698 }
00699
00700 /**
00701   * @}
00702   */
00703
00704 /** @defgroup GPIO_LL_EF_Data_Access Data Access
00705   * @{
00706   */
00707
00708 /**
00709   * @brief  Return full input data register value for a dedicated port.
00710   * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
00711   * @param  GPIOx GPIO Port
00712   * @retval Input data register value of port
00713   */
00714 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
00715 {
00716   return (uint32_t)(READ_REG(GPIOx->IDR));
00717 }
00718
00719 /**
00720   * @brief  Return if input data level for several pins of dedicated port is high or low.
00721   * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
00722   * @param  GPIOx GPIO Port
00723   * @param  PinMask This parameter can be a combination of the following values:
00724   *         @arg @ref LL_GPIO_PIN_0
00725   *         @arg @ref LL_GPIO_PIN_1
00726   *         @arg @ref LL_GPIO_PIN_2
00727   *         @arg @ref LL_GPIO_PIN_3
00728   *         @arg @ref LL_GPIO_PIN_4
00729   *         @arg @ref LL_GPIO_PIN_5
00730   *         @arg @ref LL_GPIO_PIN_6
00731   *         @arg @ref LL_GPIO_PIN_7
00732   *         @arg @ref LL_GPIO_PIN_8
00733   *         @arg @ref LL_GPIO_PIN_9
00734   *         @arg @ref LL_GPIO_PIN_10
00735   *         @arg @ref LL_GPIO_PIN_11
00736   *         @arg @ref LL_GPIO_PIN_12
00737   *         @arg @ref LL_GPIO_PIN_13
00738   *         @arg @ref LL_GPIO_PIN_14
00739   *         @arg @ref LL_GPIO_PIN_15
00740   *         @arg @ref LL_GPIO_PIN_ALL
00741   * @retval State of bit (1 or 0).
00742   */
00743 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00744 {
00745   return (READ_BIT(GPIOx->IDR, (PinMask >> 8 ) & 0x0000FFFFU) == ((PinMask >> 8 ) & 0x0000FFFFU));
00746 }
00747
00748 /**
00749   * @brief  Write output data register for the port.
00750   * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
00751   * @param  GPIOx GPIO Port
00752   * @param  PortValue Level value for each pin of the port
00753   * @retval None
00754   */
00755 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
00756 {
00757   WRITE_REG(GPIOx->ODR, PortValue);
00758 }
00759
00760 /**
00761   * @brief  Return full output data register value for a dedicated port.
00762   * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
00763   * @param  GPIOx GPIO Port
00764   * @retval Output data register value of port
00765   */
00766 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
00767 {
00768   return (uint32_t)(READ_REG(GPIOx->ODR));
00769 }
00770
00771 /**
00772   * @brief  Return if input data level for several pins of dedicated port is high or low.
00773   * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
00774   * @param  GPIOx GPIO Port
00775   * @param  PinMask This parameter can be a combination of the following values:
00776   *         @arg @ref LL_GPIO_PIN_0
00777   *         @arg @ref LL_GPIO_PIN_1
00778   *         @arg @ref LL_GPIO_PIN_2
00779   *         @arg @ref LL_GPIO_PIN_3
00780   *         @arg @ref LL_GPIO_PIN_4
00781   *         @arg @ref LL_GPIO_PIN_5
00782   *         @arg @ref LL_GPIO_PIN_6
00783   *         @arg @ref LL_GPIO_PIN_7
00784   *         @arg @ref LL_GPIO_PIN_8
00785   *         @arg @ref LL_GPIO_PIN_9
00786   *         @arg @ref LL_GPIO_PIN_10
00787   *         @arg @ref LL_GPIO_PIN_11
00788   *         @arg @ref LL_GPIO_PIN_12
00789   *         @arg @ref LL_GPIO_PIN_13
00790   *         @arg @ref LL_GPIO_PIN_14
00791   *         @arg @ref LL_GPIO_PIN_15
00792   *         @arg @ref LL_GPIO_PIN_ALL
00793   * @retval State of bit (1 or 0).
00794   */
00795 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00796 {
00797   return (READ_BIT(GPIOx->ODR, (PinMask >> 8 ) & 0x0000FFFFU) == ((PinMask >> 8 ) & 0x0000FFFFU));
00798 }
00799
00800 /**
00801   * @brief  Set several pins to high level on dedicated gpio port.
00802   * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
00803   * @param  GPIOx GPIO Port
00804   * @param  PinMask This parameter can be a combination of the following values:
00805   *         @arg @ref LL_GPIO_PIN_0
00806   *         @arg @ref LL_GPIO_PIN_1
00807   *         @arg @ref LL_GPIO_PIN_2
00808   *         @arg @ref LL_GPIO_PIN_3
00809   *         @arg @ref LL_GPIO_PIN_4
00810   *         @arg @ref LL_GPIO_PIN_5
00811   *         @arg @ref LL_GPIO_PIN_6
00812   *         @arg @ref LL_GPIO_PIN_7
00813   *         @arg @ref LL_GPIO_PIN_8
00814   *         @arg @ref LL_GPIO_PIN_9
00815   *         @arg @ref LL_GPIO_PIN_10
00816   *         @arg @ref LL_GPIO_PIN_11
00817   *         @arg @ref LL_GPIO_PIN_12
00818   *         @arg @ref LL_GPIO_PIN_13
00819   *         @arg @ref LL_GPIO_PIN_14
00820   *         @arg @ref LL_GPIO_PIN_15
00821   *         @arg @ref LL_GPIO_PIN_ALL
00822   * @retval None
00823   */
00824 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00825 {
00826   WRITE_REG(GPIOx->BSRR, (PinMask >> 8) & 0x0000FFFFU);
00827 }
00828
00829 /**
00830   * @brief  Set several pins to low level on dedicated gpio port.
00831   * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin
00832   * @param  GPIOx GPIO Port
00833   * @param  PinMask This parameter can be a combination of the following values:
00834   *         @arg @ref LL_GPIO_PIN_0
00835   *         @arg @ref LL_GPIO_PIN_1
00836   *         @arg @ref LL_GPIO_PIN_2
00837   *         @arg @ref LL_GPIO_PIN_3
00838   *         @arg @ref LL_GPIO_PIN_4
00839   *         @arg @ref LL_GPIO_PIN_5
00840   *         @arg @ref LL_GPIO_PIN_6
00841   *         @arg @ref LL_GPIO_PIN_7
00842   *         @arg @ref LL_GPIO_PIN_8
00843   *         @arg @ref LL_GPIO_PIN_9
00844   *         @arg @ref LL_GPIO_PIN_10
00845   *         @arg @ref LL_GPIO_PIN_11
00846   *         @arg @ref LL_GPIO_PIN_12
00847   *         @arg @ref LL_GPIO_PIN_13
00848   *         @arg @ref LL_GPIO_PIN_14
00849   *         @arg @ref LL_GPIO_PIN_15
00850   *         @arg @ref LL_GPIO_PIN_ALL
00851   * @retval None
00852   */
00853 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00854 {
00855   WRITE_REG(GPIOx->BRR, (PinMask >> 8 ) & 0x0000FFFFU);
00856 }
00857
00858 /**
00859   * @brief  Toggle data value for several pin of dedicated port.
00860   * @rmtoll ODR          ODy           LL_GPIO_TogglePin
00861   * @param  GPIOx GPIO Port
00862   * @param  PinMask This parameter can be a combination of the following values:
00863   *         @arg @ref LL_GPIO_PIN_0
00864   *         @arg @ref LL_GPIO_PIN_1
00865   *         @arg @ref LL_GPIO_PIN_2
00866   *         @arg @ref LL_GPIO_PIN_3
00867   *         @arg @ref LL_GPIO_PIN_4
00868   *         @arg @ref LL_GPIO_PIN_5
00869   *         @arg @ref LL_GPIO_PIN_6
00870   *         @arg @ref LL_GPIO_PIN_7
00871   *         @arg @ref LL_GPIO_PIN_8
00872   *         @arg @ref LL_GPIO_PIN_9
00873   *         @arg @ref LL_GPIO_PIN_10
00874   *         @arg @ref LL_GPIO_PIN_11
00875   *         @arg @ref LL_GPIO_PIN_12
00876   *         @arg @ref LL_GPIO_PIN_13
00877   *         @arg @ref LL_GPIO_PIN_14
00878   *         @arg @ref LL_GPIO_PIN_15
00879   *         @arg @ref LL_GPIO_PIN_ALL
00880   * @retval None
00881   */
00882 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
00883 {
00884   WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> 8 ) & 0x0000FFFFU));
00885 }
00886
00887 /**
00888   * @}
00889   */
00890
00891 /** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
00892   * @brief This section propose definition to remap the alternate function to some other port/pins.
00893   * @{
00894   */
00895
00896 /**
00897   * @brief  Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
00898   * @rmtoll MAPR          SPI1_REMAP           LL_GPIO_AF_EnableRemap_SPI1
00899   * @note   ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
00900   * @retval None
00901   */
00902 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
00903 {
00904   SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
00905 }
00906
00907 /**
00908   * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
00909   * @rmtoll MAPR          SPI1_REMAP           LL_GPIO_AF_DisableRemap_SPI1
00910   * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
00911   * @retval None
00912   */
00913 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
00914 {
00915   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
00916 }
00917
00918 /**
00919   * @brief  Check if SPI1 has been remaped or not
00920   * @rmtoll MAPR         SPI1_REMAP         LL_GPIO_AF_IsEnabledRemap_SPI1
00921   * @retval State of bit (1 or 0).
00922   */
00923 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
00924 {
00925   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
00926 }
00927
00928 /**
00929   * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
00930   * @rmtoll MAPR          I2C1_REMAP           LL_GPIO_AF_EnableRemap_I2C1
00931   * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
00932   * @retval None
00933   */
00934 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
00935 {
00936   SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
00937 }
00938
00939 /**
00940   * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
00941   * @rmtoll MAPR          I2C1_REMAP           LL_GPIO_AF_DisableRemap_I2C1
00942   * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
00943   * @retval None
00944   */
00945 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
00946 {
00947   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
00948 }
00949
00950 /**
00951   * @brief  Check if I2C1 has been remaped or not
00952   * @rmtoll MAPR         I2C1_REMAP         LL_GPIO_AF_IsEnabledRemap_I2C1
00953   * @retval State of bit (1 or 0).
00954   */
00955 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
00956 {
00957   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
00958 }
00959
00960 /**
00961   * @brief Enable the remapping of USART1 alternate function TX and RX.
00962   * @rmtoll MAPR          USART1_REMAP           LL_GPIO_AF_EnableRemap_USART1
00963   * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
00964   * @retval None
00965   */
00966 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
00967 {
00968   SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
00969 }
00970
00971 /**
00972   * @brief Disable the remapping of USART1 alternate function TX and RX.
00973   * @rmtoll MAPR          USART1_REMAP           LL_GPIO_AF_DisableRemap_USART1
00974   * @note  DISABLE: No remap (TX/PA9, RX/PA10)
00975   * @retval None
00976   */
00977 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
00978 {
00979   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
00980 }
00981
00982 /**
00983   * @brief  Check if USART1 has been remaped or not
00984   * @rmtoll MAPR         USART1_REMAP         LL_GPIO_AF_IsEnabledRemap_USART1
00985   * @retval State of bit (1 or 0).
00986   */
00987 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
00988 {
00989   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
00990 }
00991
00992 /**
00993   * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
00994   * @rmtoll MAPR          USART2_REMAP           LL_GPIO_AF_EnableRemap_USART2
00995   * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
00996   * @retval None
00997   */
00998 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
00999 {
01000   SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
01001 }
01002
01003 /**
01004   * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
01005   * @rmtoll MAPR          USART2_REMAP           LL_GPIO_AF_DisableRemap_USART2
01006   * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
01007   * @retval None
01008   */
01009 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
01010 {
01011   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
01012 }
01013
01014 /**
01015   * @brief  Check if USART2 has been remaped or not
01016   * @rmtoll MAPR         USART2_REMAP         LL_GPIO_AF_IsEnabledRemap_USART2
01017   * @retval State of bit (1 or 0).
01018   */
01019 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
01020 {
01021   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
01022 }
01023
01024 #if defined (AFIO_MAPR_USART3_REMAP)
01025 /**
01026   * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
01027   * @rmtoll MAPR          USART3_REMAP           LL_GPIO_AF_EnableRemap_USART3
01028   * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
01029   * @retval None
01030   */
01031 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
01032 {
01033   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
01034   SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);
01035 }
01036
01037 /**
01038   * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
01039   * @rmtoll MAPR          USART3_REMAP           LL_GPIO_AF_RemapPartial_USART3
01040   * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
01041   * @retval None
01042   */
01043 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
01044 {
01045   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
01046   SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP);
01047 }
01048
01049 /**
01050   * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
01051   * @rmtoll MAPR          USART3_REMAP           LL_GPIO_AF_DisableRemap_USART3
01052   * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
01053   * @retval None
01054   */
01055 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
01056 {
01057   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
01058   SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP);
01059 }
01060 #endif
01061
01062 /**
01063   * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
01064   * @rmtoll MAPR          TIM1_REMAP           LL_GPIO_AF_EnableRemap_TIM1
01065   * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
01066   * @retval None
01067   */
01068 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
01069 {
01070   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
01071   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP);
01072 }
01073
01074 /**
01075   * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
01076   * @rmtoll MAPR          TIM1_REMAP           LL_GPIO_AF_RemapPartial_TIM1
01077   * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
01078   * @retval None
01079   */
01080 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
01081 {
01082   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
01083   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP);
01084 }
01085
01086 /**
01087   * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
01088   * @rmtoll MAPR          TIM1_REMAP           LL_GPIO_AF_DisableRemap_TIM1
01089   * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
01090   * @retval None
01091   */
01092 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
01093 {
01094   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
01095   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP);
01096 }
01097
01098 /**
01099   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
01100   * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_EnableRemap_TIM2
01101   * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
01102   * @retval None
01103   */
01104 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
01105 {
01106   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
01107   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP);
01108 }
01109
01110 /**
01111   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
01112   * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_RemapPartial2_TIM2
01113   * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
01114   * @retval None
01115   */
01116 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
01117 {
01118   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
01119   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2);
01120 }
01121
01122 /**
01123   * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
01124   * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_RemapPartial1_TIM2
01125   * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
01126   * @retval None
01127   */
01128 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
01129 {
01130   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
01131   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1);
01132 }
01133
01134 /**
01135   * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
01136   * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_DisableRemap_TIM2
01137   * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
01138   * @retval None
01139   */
01140 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
01141 {
01142   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
01143   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);
01144 }
01145
01146 /**
01147   * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
01148   * @rmtoll MAPR          TIM3_REMAP           LL_GPIO_AF_EnableRemap_TIM3
01149   * @note  ENABLE: Full remap     (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
01150   * @note  TIM3_ETR on PE0 is not re-mapped.
01151   * @retval None
01152   */
01153 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
01154 {
01155   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
01156   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP);
01157 }
01158
01159 /**
01160   * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
01161   * @rmtoll MAPR          TIM3_REMAP           LL_GPIO_AF_RemapPartial_TIM3
01162   * @note  PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
01163   * @note  TIM3_ETR on PE0 is not re-mapped.
01164   * @retval None
01165   */
01166 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
01167 {
01168   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
01169   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP);
01170 }
01171
01172 /**
01173   * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
01174   * @rmtoll MAPR          TIM3_REMAP           LL_GPIO_AF_DisableRemap_TIM3
01175   * @note  DISABLE: No remap      (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
01176   * @note  TIM3_ETR on PE0 is not re-mapped.
01177   * @retval None
01178   */
01179 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
01180 {
01181   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
01182   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);
01183 }
01184
01185 #if defined(AFIO_MAPR_TIM4_REMAP)
01186 /**
01187   * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
01188   * @rmtoll MAPR          TIM4_REMAP           LL_GPIO_AF_EnableRemap_TIM4
01189   * @note  ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
01190   * @note  TIM4_ETR on PE0 is not re-mapped.
01191   * @retval None
01192   */
01193 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
01194 {
01195   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
01196 }
01197 /**
01198   * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
01199   * @rmtoll MAPR          TIM4_REMAP           LL_GPIO_AF_DisableRemap_TIM4
01200   * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
01201   * @note  TIM4_ETR on PE0 is not re-mapped.
01202   * @retval None
01203   */
01204 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
01205 {
01206   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
01207 }
01208
01209 /**
01210   * @brief  Check if TIM4 has been remaped or not
01211   * @rmtoll MAPR         TIM4_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM4
01212   * @retval State of bit (1 or 0).
01213   */
01214 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
01215 {
01216   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
01217 }
01218 #endif
01219
01220 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
01221
01222 /**
01223   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
01224   * @rmtoll MAPR          CAN_REMAP           LL_GPIO_AF_RemapPartial1_CAN1
01225   * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
01226   * @retval None
01227   */
01228 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
01229 {
01230   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
01231   SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);
01232 }
01233
01234 /**
01235   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
01236   * @rmtoll MAPR          CAN_REMAP           LL_GPIO_AF_RemapPartial2_CAN1
01237   * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
01238   * @retval None
01239   */
01240 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
01241 {
01242   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
01243   SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);
01244 }
01245
01246 /**
01247   * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
01248   * @rmtoll MAPR          CAN_REMAP           LL_GPIO_AF_RemapPartial3_CAN1
01249   * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
01250   * @retval None
01251   */
01252 __STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
01253 {
01254   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
01255   SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);
01256 }
01257 #endif
01258
01259 /**
01260   * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
01261   *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
01262   *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
01263   *        on 100-pin and 144-pin packages, no need for remapping).
01264   * @rmtoll MAPR          PD01_REMAP           LL_GPIO_AF_EnableRemap_PD01
01265   * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
01266   * @retval None
01267   */
01268 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
01269 {
01270   SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
01271 }
01272
01273 /**
01274   * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
01275   *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
01276   *        OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
01277   *        on 100-pin and 144-pin packages, no need for remapping).
01278   * @rmtoll MAPR          PD01_REMAP           LL_GPIO_AF_DisableRemap_PD01
01279   * @note  DISABLE: No remapping of PD0 and PD1
01280   * @retval None
01281   */
01282 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
01283 {
01284   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
01285 }
01286
01287 /**
01288   * @brief  Check if PD01 has been remaped or not
01289   * @rmtoll MAPR         PD01_REMAP         LL_GPIO_AF_IsEnabledRemap_PD01
01290   * @retval State of bit (1 or 0).
01291   */
01292 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
01293 {
01294   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
01295 }
01296
01297 #if defined(AFIO_MAPR_TIM5CH4_IREMAP)
01298 /**
01299   * @brief Enable the remapping of TIM5CH4.
01300   * @rmtoll MAPR          TIM5CH4_IREMAP           LL_GPIO_AF_EnableRemap_TIM5CH4
01301   * @note  ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
01302   * @note  This function is available only in high density value line devices.
01303   * @retval None
01304   */
01305 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
01306 {
01307   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
01308 }
01309
01310 /**
01311   * @brief Disable the remapping of TIM5CH4.
01312   * @rmtoll MAPR          TIM5CH4_IREMAP           LL_GPIO_AF_DisableRemap_TIM5CH4
01313   * @note  DISABLE: TIM5_CH4 is connected to PA3
01314   * @note  This function is available only in high density value line devices.
01315   * @retval None
01316   */
01317 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
01318 {
01319   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
01320 }
01321
01322 /**
01323   * @brief  Check if TIM5CH4 has been remaped or not
01324   * @rmtoll MAPR         TIM5CH4_IREMAP         LL_GPIO_AF_IsEnabledRemap_TIM5CH4
01325   * @retval State of bit (1 or 0).
01326   */
01327 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
01328 {
01329   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
01330 }
01331 #endif
01332
01333 #if defined(AFIO_MAPR_ETH_REMAP)
01334 /**
01335   * @brief Enable the remapping of Ethernet MAC connections with the PHY.
01336   * @rmtoll MAPR          ETH_REMAP           LL_GPIO_AF_EnableRemap_ETH
01337   * @note  ENABLE: Remap     (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
01338   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01339   * @retval None
01340   */
01341 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
01342 {
01343   SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
01344 }
01345
01346 /**
01347   * @brief Disable the remapping of Ethernet MAC connections with the PHY.
01348   * @rmtoll MAPR          ETH_REMAP           LL_GPIO_AF_DisableRemap_ETH
01349   * @note  DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5,  RXD2/PB0,  RXD3/PB1)
01350   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01351   * @retval None
01352   */
01353 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
01354 {
01355   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
01356 }
01357
01358 /**
01359   * @brief  Check if ETH has been remaped or not
01360   * @rmtoll MAPR         ETH_REMAP         LL_GPIO_AF_IsEnabledRemap_ETH
01361   * @retval State of bit (1 or 0).
01362   */
01363 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
01364 {
01365   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
01366 }
01367 #endif
01368
01369 #if defined(AFIO_MAPR_CAN2_REMAP)
01370
01371 /**
01372   * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
01373   * @rmtoll MAPR          CAN2_REMAP           LL_GPIO_AF_EnableRemap_CAN2
01374   * @note  ENABLE: Remap     (CAN2_RX/PB5,  CAN2_TX/PB6)
01375   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01376   * @retval None
01377   */
01378 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
01379 {
01380   SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
01381 }
01382 /**
01383   * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
01384   * @rmtoll MAPR          CAN2_REMAP           LL_GPIO_AF_DisableRemap_CAN2
01385   * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
01386   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01387   * @retval None
01388   */
01389 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
01390 {
01391   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
01392 }
01393
01394 /**
01395   * @brief  Check if CAN2 has been remaped or not
01396   * @rmtoll MAPR         CAN2_REMAP         LL_GPIO_AF_IsEnabledRemap_CAN2
01397   * @retval State of bit (1 or 0).
01398   */
01399 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
01400 {
01401   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
01402 }
01403 #endif
01404
01405 #if defined(AFIO_MAPR_MII_RMII_SEL)
01406 /**
01407   * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
01408   * @rmtoll MAPR          MII_RMII_SEL           LL_GPIO_AF_Select_ETH_RMII
01409   * @note  ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
01410   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01411   * @retval None
01412   */
01413 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
01414 {
01415   SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
01416 }
01417
01418 /**
01419   * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
01420   * @rmtoll MAPR          MII_RMII_SEL           LL_GPIO_AF_Select_ETH_MII
01421   * @note  ETH_MII: Configure Ethernet MAC for connection with an MII PHY
01422   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01423   * @retval None
01424   */
01425 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
01426 {
01427   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
01428 }
01429 #endif
01430
01431 #if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
01432 /**
01433   * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
01434   * @rmtoll MAPR          ADC1_ETRGINJ_REMAP           LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
01435   * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
01436   * @retval None
01437   */
01438 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
01439 {
01440   SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
01441 }
01442
01443 /**
01444   * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
01445   * @rmtoll MAPR          ADC1_ETRGINJ_REMAP           LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
01446   * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
01447   * @retval None
01448   */
01449 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
01450 {
01451   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
01452 }
01453
01454 /**
01455   * @brief  Check if ADC1_ETRGINJ has been remaped or not
01456   * @rmtoll MAPR         ADC1_ETRGINJ_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
01457   * @retval State of bit (1 or 0).
01458   */
01459 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
01460 {
01461   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
01462 }
01463 #endif
01464
01465 #if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
01466 /**
01467   * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
01468   * @rmtoll MAPR          ADC1_ETRGREG_REMAP           LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
01469   * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
01470   * @retval None
01471   */
01472 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
01473 {
01474   SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
01475 }
01476
01477 /**
01478   * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
01479   * @rmtoll MAPR          ADC1_ETRGREG_REMAP           LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
01480   * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
01481   * @retval None
01482   */
01483 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
01484 {
01485   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
01486 }
01487
01488 /**
01489   * @brief  Check if ADC1_ETRGREG has been remaped or not
01490   * @rmtoll MAPR         ADC1_ETRGREG_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
01491   * @retval State of bit (1 or 0).
01492   */
01493 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
01494 {
01495   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
01496 }
01497 #endif
01498
01499 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
01500
01501 /**
01502   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
01503   * @rmtoll MAPR          ADC2_ETRGINJ_REMAP           LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
01504   * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
01505   * @retval None
01506   */
01507 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
01508 {
01509   SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
01510 }
01511
01512 /**
01513   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
01514   * @rmtoll MAPR          ADC2_ETRGINJ_REMAP           LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
01515   * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
01516   * @retval None
01517   */
01518 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
01519 {
01520   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
01521 }
01522
01523 /**
01524   * @brief  Check if ADC2_ETRGINJ has been remaped or not
01525   * @rmtoll MAPR         ADC2_ETRGINJ_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
01526   * @retval State of bit (1 or 0).
01527   */
01528 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
01529 {
01530   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
01531 }
01532 #endif
01533
01534 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
01535
01536 /**
01537   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
01538   * @rmtoll MAPR          ADC2_ETRGREG_REMAP           LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
01539   * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
01540   * @retval None
01541   */
01542 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
01543 {
01544   SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
01545 }
01546
01547 /**
01548   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
01549   * @rmtoll MAPR          ADC2_ETRGREG_REMAP           LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
01550   * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
01551   * @retval None
01552   */
01553 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
01554 {
01555   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
01556 }
01557
01558 /**
01559   * @brief  Check if ADC2_ETRGREG has been remaped or not
01560   * @rmtoll MAPR         ADC2_ETRGREG_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
01561   * @retval State of bit (1 or 0).
01562   */
01563 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
01564 {
01565   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
01566 }
01567 #endif
01568
01569 /**
01570   * @brief Enable the Serial wire JTAG configuration
01571   * @rmtoll MAPR          SWJ_CFG           LL_GPIO_AF_EnableRemap_SWJ
01572   * @note  ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
01573   * @retval None
01574   */
01575 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
01576 {
01577   CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
01578   SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);
01579 }
01580
01581 /**
01582   * @brief Enable the Serial wire JTAG configuration
01583   * @rmtoll MAPR          SWJ_CFG           LL_GPIO_AF_Remap_SWJ_NONJTRST
01584   * @note  NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
01585   * @retval None
01586   */
01587 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
01588 {
01589   CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
01590   SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);
01591 }
01592
01593 /**
01594   * @brief Enable the Serial wire JTAG configuration
01595   * @rmtoll MAPR          SWJ_CFG           LL_GPIO_AF_Remap_SWJ_NOJTAG
01596   * @note  NOJTAG: JTAG-DP Disabled and SW-DP Enabled
01597   * @retval None
01598   */
01599 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
01600 {
01601   CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
01602   SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
01603 }
01604
01605 /**
01606   * @brief Disable the Serial wire JTAG configuration
01607   * @rmtoll MAPR          SWJ_CFG           LL_GPIO_AF_DisableRemap_SWJ
01608   * @note  DISABLE: JTAG-DP Disabled and SW-DP Disabled
01609   * @retval None
01610   */
01611 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
01612 {
01613   CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
01614   SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);
01615 }
01616
01617 #if defined(AFIO_MAPR_SPI3_REMAP)
01618
01619 /**
01620   * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
01621   * @rmtoll MAPR          SPI3_REMAP           LL_GPIO_AF_EnableRemap_SPI3
01622   * @note  ENABLE: Remap     (SPI3_NSS-I2S3_WS/PA4,  SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
01623   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01624   * @retval None
01625   */
01626 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
01627 {
01628   SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
01629 }
01630
01631 /**
01632   * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
01633   * @rmtoll MAPR          SPI3_REMAP           LL_GPIO_AF_DisableRemap_SPI3
01634   * @note  DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3,  SPI3_MISO/PB4,  SPI3_MOSI-I2S3_SD/PB5).
01635   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01636   * @retval None
01637   */
01638 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
01639 {
01640   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
01641 }
01642
01643 /**
01644   * @brief  Check if SPI3 has been remaped or not
01645   * @rmtoll MAPR         SPI3_REMAP         LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
01646   * @retval State of bit (1 or 0).
01647   */
01648 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
01649 {
01650   return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
01651 }
01652 #endif
01653
01654 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
01655
01656 /**
01657   * @brief Control of TIM2_ITR1 internal mapping.
01658   * @rmtoll MAPR          TIM2ITR1_IREMAP           LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
01659   * @note  TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
01660   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01661   * @retval None
01662   */
01663 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
01664 {
01665   SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
01666 }
01667
01668 /**
01669   * @brief Control of TIM2_ITR1 internal mapping.
01670   * @rmtoll MAPR          TIM2ITR1_IREMAP           LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
01671   * @note  TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
01672   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01673   * @retval None
01674   */
01675 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
01676 {
01677   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
01678 }
01679 #endif
01680
01681 #if defined(AFIO_MAPR_PTP_PPS_REMAP)
01682
01683 /**
01684   * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
01685   * @rmtoll MAPR          PTP_PPS_REMAP           LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
01686   * @note  ENABLE: PTP_PPS is output on PB5 pin.
01687   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01688   * @retval None
01689   */
01690 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
01691 {
01692   SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
01693 }
01694
01695 /**
01696   * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
01697   * @rmtoll MAPR          PTP_PPS_REMAP           LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
01698   * @note  DISABLE: PTP_PPS not output on PB5 pin.
01699   * @note  This bit is available only in connectivity line devices and is reserved otherwise.
01700   * @retval None
01701   */
01702 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
01703 {
01704   CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
01705 }
01706 #endif
01707
01708 #if defined(AFIO_MAPR2_TIM9_REMAP)
01709
01710 /**
01711   * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
01712   * @rmtoll MAPR2          TIM9_REMAP           LL_GPIO_AF_EnableRemap_TIM9
01713   * @note  ENABLE: Remap     (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
01714   * @retval None
01715   */
01716 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
01717 {
01718   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
01719 }
01720
01721 /**
01722   * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
01723   * @rmtoll MAPR2          TIM9_REMAP           LL_GPIO_AF_DisableRemap_TIM9
01724   * @note  DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
01725   * @retval None
01726   */
01727 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
01728 {
01729   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
01730 }
01731
01732 /**
01733   * @brief  Check if TIM9_CH1 and TIM9_CH2 have been remaped or not
01734   * @rmtoll MAPR2         TIM9_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM9
01735   * @retval State of bit (1 or 0).
01736   */
01737 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
01738 {
01739   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
01740 }
01741 #endif
01742
01743 #if defined(AFIO_MAPR2_TIM10_REMAP)
01744
01745 /**
01746   * @brief Enable the remapping of TIM10_CH1.
01747   * @rmtoll MAPR2          TIM10_REMAP           LL_GPIO_AF_EnableRemap_TIM10
01748   * @note  ENABLE: Remap     (TIM10_CH1 on PF6).
01749   * @retval None
01750   */
01751 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
01752 {
01753   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
01754 }
01755
01756 /**
01757   * @brief Disable the remapping of TIM10_CH1.
01758   * @rmtoll MAPR2          TIM10_REMAP           LL_GPIO_AF_DisableRemap_TIM10
01759   * @note  DISABLE: No remap (TIM10_CH1 on PB8).
01760   * @retval None
01761   */
01762 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
01763 {
01764   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
01765 }
01766
01767 /**
01768   * @brief  Check if TIM10_CH1 has been remaped or not
01769   * @rmtoll MAPR2         TIM10_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM10
01770   * @retval State of bit (1 or 0).
01771   */
01772 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
01773 {
01774   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
01775 }
01776 #endif
01777
01778 #if defined(AFIO_MAPR2_TIM11_REMAP)
01779 /**
01780   * @brief Enable the remapping of TIM11_CH1.
01781   * @rmtoll MAPR2          TIM11_REMAP           LL_GPIO_AF_EnableRemap_TIM11
01782   * @note  ENABLE: Remap     (TIM11_CH1 on PF7).
01783   * @retval None
01784   */
01785 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
01786 {
01787   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
01788 }
01789
01790 /**
01791   * @brief Disable the remapping of TIM11_CH1.
01792   * @rmtoll MAPR2          TIM11_REMAP           LL_GPIO_AF_DisableRemap_TIM11
01793   * @note  DISABLE: No remap (TIM11_CH1 on PB9).
01794   * @retval None
01795   */
01796 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
01797 {
01798   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
01799 }
01800
01801 /**
01802   * @brief  Check if TIM11_CH1 has been remaped or not
01803   * @rmtoll MAPR2         TIM11_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM11
01804   * @retval State of bit (1 or 0).
01805   */
01806 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
01807 {
01808   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
01809 }
01810 #endif
01811
01812 #if defined(AFIO_MAPR2_TIM13_REMAP)
01813
01814 /**
01815   * @brief Enable the remapping of TIM13_CH1.
01816   * @rmtoll MAPR2          TIM13_REMAP           LL_GPIO_AF_EnableRemap_TIM13
01817   * @note  ENABLE: Remap     STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
01818   * @retval None
01819   */
01820 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
01821 {
01822   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
01823 }
01824
01825 /**
01826   * @brief Disable the remapping of TIM13_CH1.
01827   * @rmtoll MAPR2          TIM13_REMAP           LL_GPIO_AF_DisableRemap_TIM13
01828   * @note  DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
01829   * @retval None
01830   */
01831 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
01832 {
01833   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
01834 }
01835
01836 /**
01837   * @brief  Check if TIM13_CH1 has been remaped or not
01838   * @rmtoll MAPR2         TIM13_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM13
01839   * @retval State of bit (1 or 0).
01840   */
01841 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
01842 {
01843   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
01844 }
01845 #endif
01846
01847 #if defined(AFIO_MAPR2_TIM14_REMAP)
01848
01849 /**
01850   * @brief Enable the remapping of TIM14_CH1.
01851   * @rmtoll MAPR2          TIM14_REMAP           LL_GPIO_AF_EnableRemap_TIM14
01852   * @note  ENABLE: Remap     STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
01853   * @retval None
01854   */
01855 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
01856 {
01857   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
01858 }
01859
01860 /**
01861   * @brief Disable the remapping of TIM14_CH1.
01862   * @rmtoll MAPR2          TIM14_REMAP           LL_GPIO_AF_DisableRemap_TIM14
01863   * @note  DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
01864   * @retval None
01865   */
01866 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
01867 {
01868   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
01869 }
01870
01871 /**
01872   * @brief  Check if TIM14_CH1 has been remaped or not
01873   * @rmtoll MAPR2         TIM14_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM14
01874   * @retval State of bit (1 or 0).
01875   */
01876 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
01877 {
01878   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
01879 }
01880 #endif
01881
01882 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
01883
01884 /**
01885   * @brief Controls the use of the optional FSMC_NADV signal.
01886   * @rmtoll MAPR2          FSMC_NADV           LL_GPIO_AF_Disconnect_FSMCNADV
01887   * @note  DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
01888   * @retval None
01889   */
01890 __STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
01891 {
01892   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
01893 }
01894
01895 /**
01896   * @brief Controls the use of the optional FSMC_NADV signal.
01897   * @rmtoll MAPR2          FSMC_NADV           LL_GPIO_AF_Connect_FSMCNADV
01898   * @note  CONNECTED: The NADV signal is connected to the output (default).
01899   * @retval None
01900   */
01901 __STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
01902 {
01903   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
01904 }
01905 #endif
01906
01907 #if defined(AFIO_MAPR2_TIM15_REMAP)
01908
01909 /**
01910   * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
01911   * @rmtoll MAPR2          TIM15_REMAP           LL_GPIO_AF_EnableRemap_TIM15
01912   * @note  ENABLE: Remap     (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
01913   * @retval None
01914   */
01915 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
01916 {
01917   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
01918 }
01919 /**
01920   * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
01921   * @rmtoll MAPR2          TIM15_REMAP           LL_GPIO_AF_DisableRemap_TIM15
01922   * @note  DISABLE: No remap (TIM15_CH1 on PA2  and TIM15_CH2 on PA3).
01923   * @retval None
01924   */
01925 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
01926 {
01927   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
01928 }
01929
01930 /**
01931   * @brief  Check if TIM15_CH1 has been remaped or not
01932   * @rmtoll MAPR2         TIM15_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM15
01933   * @retval State of bit (1 or 0).
01934   */
01935 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
01936 {
01937   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
01938 }
01939 #endif
01940
01941 #if defined(AFIO_MAPR2_TIM16_REMAP)
01942
01943 /**
01944   * @brief Enable the remapping of TIM16_CH1.
01945   * @rmtoll MAPR2          TIM16_REMAP           LL_GPIO_AF_EnableRemap_TIM16
01946   * @note  ENABLE: Remap     (TIM16_CH1 on PA6).
01947   * @retval None
01948   */
01949 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
01950 {
01951   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
01952 }
01953
01954 /**
01955   * @brief Disable the remapping of TIM16_CH1.
01956   * @rmtoll MAPR2          TIM16_REMAP           LL_GPIO_AF_DisableRemap_TIM16
01957   * @note  DISABLE: No remap (TIM16_CH1 on PB8).
01958   * @retval None
01959   */
01960 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
01961 {
01962   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
01963 }
01964
01965 /**
01966   * @brief  Check if TIM16_CH1 has been remaped or not
01967   * @rmtoll MAPR2         TIM16_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM16
01968   * @retval State of bit (1 or 0).
01969   */
01970 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
01971 {
01972   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
01973 }
01974 #endif
01975
01976 #if defined(AFIO_MAPR2_TIM17_REMAP)
01977
01978 /**
01979   * @brief Enable the remapping of TIM17_CH1.
01980   * @rmtoll MAPR2          TIM17_REMAP           LL_GPIO_AF_EnableRemap_TIM17
01981   * @note  ENABLE: Remap     (TIM17_CH1 on PA7).
01982   * @retval None
01983   */
01984 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
01985 {
01986   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
01987 }
01988
01989 /**
01990   * @brief Disable the remapping of TIM17_CH1.
01991   * @rmtoll MAPR2          TIM17_REMAP           LL_GPIO_AF_DisableRemap_TIM17
01992   * @note  DISABLE: No remap (TIM17_CH1 on PB9).
01993   * @retval None
01994   */
01995 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
01996 {
01997   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
01998 }
01999
02000 /**
02001   * @brief  Check if TIM17_CH1 has been remaped or not
02002   * @rmtoll MAPR2         TIM17_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM17
02003   * @retval State of bit (1 or 0).
02004   */
02005 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
02006 {
02007   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
02008 }
02009 #endif
02010
02011 #if defined(AFIO_MAPR2_CEC_REMAP)
02012
02013 /**
02014   * @brief Enable the remapping of CEC.
02015   * @rmtoll MAPR2          CEC_REMAP           LL_GPIO_AF_EnableRemap_CEC
02016   * @note  ENABLE: Remap     (CEC on PB10).
02017   * @retval None
02018   */
02019 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
02020 {
02021   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
02022 }
02023
02024 /**
02025   * @brief Disable the remapping of CEC.
02026   * @rmtoll MAPR2          CEC_REMAP           LL_GPIO_AF_DisableRemap_CEC
02027   * @note  DISABLE: No remap (CEC on PB8).
02028   * @retval None
02029   */
02030 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
02031 {
02032   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
02033 }
02034
02035 /**
02036   * @brief  Check if CEC has been remaped or not
02037   * @rmtoll MAPR2         CEC_REMAP         LL_GPIO_AF_IsEnabledRemap_CEC
02038   * @retval State of bit (1 or 0).
02039   */
02040 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
02041 {
02042   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
02043 }
02044 #endif
02045
02046 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
02047
02048 /**
02049   * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
02050   * @rmtoll MAPR2          TIM1_DMA_REMAP           LL_GPIO_AF_EnableRemap_TIM1DMA
02051   * @note  ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
02052   * @retval None
02053   */
02054 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
02055 {
02056   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
02057 }
02058
02059 /**
02060   * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
02061   * @rmtoll MAPR2          TIM1_DMA_REMAP           LL_GPIO_AF_DisableRemap_TIM1DMA
02062   * @note  DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
02063   * @retval None
02064   */
02065 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
02066 {
02067   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
02068 }
02069
02070 /**
02071   * @brief  Check if TIM1DMA has been remaped or not
02072   * @rmtoll MAPR2         TIM1_DMA_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM1DMA
02073   * @retval State of bit (1 or 0).
02074   */
02075 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
02076 {
02077   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
02078 }
02079 #endif
02080
02081 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
02082
02083 /**
02084   * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
02085   * @rmtoll MAPR2          TIM76_DAC_DMA_REMAP           LL_GPIO_AF_EnableRemap_TIM67DACDMA
02086   * @note  ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
02087   * @retval None
02088   */
02089 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
02090 {
02091   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
02092 }
02093
02094 /**
02095   * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
02096   * @rmtoll MAPR2          TIM76_DAC_DMA_REMAP           LL_GPIO_AF_DisableRemap_TIM67DACDMA
02097   * @note  DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
02098   * @retval None
02099   */
02100 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
02101 {
02102   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
02103 }
02104
02105 /**
02106   * @brief  Check if TIM67DACDMA has been remaped or not
02107   * @rmtoll MAPR2         TIM76_DAC_DMA_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
02108   * @retval State of bit (1 or 0).
02109   */
02110 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
02111 {
02112   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
02113 }
02114 #endif
02115
02116 #if defined(AFIO_MAPR2_TIM12_REMAP)
02117
02118 /**
02119   * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
02120   * @rmtoll MAPR2          TIM12_REMAP           LL_GPIO_AF_EnableRemap_TIM12
02121   * @note  ENABLE: Remap     (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
02122   * @note  This bit is available only in high density value line devices.
02123   * @retval None
02124   */
02125 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
02126 {
02127   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
02128 }
02129
02130 /**
02131   * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
02132   * @rmtoll MAPR2          TIM12_REMAP           LL_GPIO_AF_DisableRemap_TIM12
02133   * @note  DISABLE: No remap (TIM12_CH1 on PC4  and TIM12_CH2 on PC5).
02134   * @note  This bit is available only in high density value line devices.
02135   * @retval None
02136   */
02137 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
02138 {
02139   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
02140 }
02141
02142 /**
02143   * @brief  Check if TIM12_CH1 has been remaped or not
02144   * @rmtoll MAPR2         TIM12_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM12
02145   * @retval State of bit (1 or 0).
02146   */
02147 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
02148 {
02149   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
02150 }
02151 #endif
02152
02153 #if defined(AFIO_MAPR2_MISC_REMAP)
02154
02155 /**
02156   * @brief Miscellaneous features remapping.
02157   *        This bit is set and cleared by software. It controls miscellaneous features.
02158   *        The DMA2 channel 5 interrupt position in the vector table.
02159   *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
02160   * @rmtoll MAPR2          MISC_REMAP           LL_GPIO_AF_EnableRemap_MISC
02161   * @note  ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
02162   *        selected as DAC Trigger 3, TIM15 triggers TIM1/3.
02163   * @note  This bit is available only in high density value line devices.
02164   * @retval None
02165   */
02166 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
02167 {
02168   SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
02169 }
02170
02171 /**
02172   * @brief Miscellaneous features remapping.
02173   *        This bit is set and cleared by software. It controls miscellaneous features.
02174   *        The DMA2 channel 5 interrupt position in the vector table.
02175   *        The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
02176   * @rmtoll MAPR2          MISC_REMAP           LL_GPIO_AF_DisableRemap_MISC
02177   * @note  DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
02178   *        event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
02179   * @note  This bit is available only in high density value line devices.
02180   * @retval None
02181   */
02182 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
02183 {
02184   CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
02185 }
02186
02187 /**
02188   * @brief  Check if MISC has been remaped or not
02189   * @rmtoll MAPR2         MISC_REMAP         LL_GPIO_AF_IsEnabledRemap_MISC
02190   * @retval State of bit (1 or 0).
02191   */
02192 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
02193 {
02194   return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
02195 }
02196 #endif
02197
02198 /**
02199   * @}
02200   */
02201
02202 /** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
02203   * @brief This section propose definition to Configure EVENTOUT Cortex feature .
02204   * @{
02205   */
02206
02207 /**
02208   * @brief  Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
02209   * @rmtoll EVCR          PORT           LL_GPIO_AF_ConfigEventout\n
02210   *         EVCR          PIN            LL_GPIO_AF_ConfigEventout
02211   * @param  LL_GPIO_PortSource This parameter can be one of the following values:
02212   *      @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
02213   *      @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
02214   *      @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
02215   *      @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
02216   *      @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
02217   * @param  LL_GPIO_PinSource This parameter can be one of the following values:
02218   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
02219   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
02220   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
02221   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
02222   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
02223   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
02224   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
02225   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
02226   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
02227   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
02228   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
02229   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
02230   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
02231   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
02232   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
02233   *      @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
02234   * @retval None
02235 */
02236 __STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
02237 {
02238   MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource));
02239 }
02240
02241 /**
02242   * @brief  Enables the Event Output.
02243   * @rmtoll EVCR          EVOE           LL_GPIO_AF_EnableEventout
02244   * @retval None
02245   */
02246 __STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
02247 {
02248   SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
02249 }
02250
02251 /**
02252   * @brief  Disables the Event Output.
02253   * @rmtoll EVCR          EVOE           LL_GPIO_AF_DisableEventout
02254   * @retval None
02255   */
02256 __STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
02257 {
02258   CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
02259 }
02260
02261 /**
02262   * @}
02263   */
02264 /** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
02265   * @brief This section Configure source input for the EXTI external interrupt .
02266   * @{
02267   */
02268
02269 /**
02270   * @brief  Configure source input for the EXTI external interrupt.
02271   * @rmtoll AFIO_EXTICR1      EXTIx         LL_GPIO_AF_SetEXTISource\n
02272   *         AFIO_EXTICR2      EXTIx         LL_GPIO_AF_SetEXTISource\n
02273   *         AFIO_EXTICR3      EXTIx         LL_GPIO_AF_SetEXTISource\n
02274   *         AFIO_EXTICR4      EXTIx         LL_GPIO_AF_SetEXTISource
02275   * @param  Port This parameter can be one of the following values:
02276   *         @arg @ref LL_GPIO_AF_EXTI_PORTA
02277   *         @arg @ref LL_GPIO_AF_EXTI_PORTB
02278   *         @arg @ref LL_GPIO_AF_EXTI_PORTC
02279   *         @arg @ref LL_GPIO_AF_EXTI_PORTD
02280   *         @arg @ref LL_GPIO_AF_EXTI_PORTE
02281   *         @arg @ref LL_GPIO_AF_EXTI_PORTF
02282   *         @arg @ref LL_GPIO_AF_EXTI_PORTG
02283   * @param  Line This parameter can be one of the following values:
02284   *         @arg @ref LL_GPIO_AF_EXTI_LINE0
02285   *         @arg @ref LL_GPIO_AF_EXTI_LINE1
02286   *         @arg @ref LL_GPIO_AF_EXTI_LINE2
02287   *         @arg @ref LL_GPIO_AF_EXTI_LINE3
02288   *         @arg @ref LL_GPIO_AF_EXTI_LINE4
02289   *         @arg @ref LL_GPIO_AF_EXTI_LINE5
02290   *         @arg @ref LL_GPIO_AF_EXTI_LINE6
02291   *         @arg @ref LL_GPIO_AF_EXTI_LINE7
02292   *         @arg @ref LL_GPIO_AF_EXTI_LINE8
02293   *         @arg @ref LL_GPIO_AF_EXTI_LINE9
02294   *         @arg @ref LL_GPIO_AF_EXTI_LINE10
02295   *         @arg @ref LL_GPIO_AF_EXTI_LINE11
02296   *         @arg @ref LL_GPIO_AF_EXTI_LINE12
02297   *         @arg @ref LL_GPIO_AF_EXTI_LINE13
02298   *         @arg @ref LL_GPIO_AF_EXTI_LINE14
02299   *         @arg @ref LL_GPIO_AF_EXTI_LINE15
02300   * @retval None
02301   */
02302 __STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
02303 {
02304   MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
02305 }
02306
02307 /**
02308   * @brief  Get the configured defined for specific EXTI Line
02309   * @rmtoll AFIO_EXTICR1      EXTIx         LL_GPIO_AF_GetEXTISource\n
02310   *         AFIO_EXTICR2      EXTIx         LL_GPIO_AF_GetEXTISource\n
02311   *         AFIO_EXTICR3      EXTIx         LL_GPIO_AF_GetEXTISource\n
02312   *         AFIO_EXTICR4      EXTIx         LL_GPIO_AF_GetEXTISource
02313   * @param  Line This parameter can be one of the following values:
02314   *         @arg @ref LL_GPIO_AF_EXTI_LINE0
02315   *         @arg @ref LL_GPIO_AF_EXTI_LINE1
02316   *         @arg @ref LL_GPIO_AF_EXTI_LINE2
02317   *         @arg @ref LL_GPIO_AF_EXTI_LINE3
02318   *         @arg @ref LL_GPIO_AF_EXTI_LINE4
02319   *         @arg @ref LL_GPIO_AF_EXTI_LINE5
02320   *         @arg @ref LL_GPIO_AF_EXTI_LINE6
02321   *         @arg @ref LL_GPIO_AF_EXTI_LINE7
02322   *         @arg @ref LL_GPIO_AF_EXTI_LINE8
02323   *         @arg @ref LL_GPIO_AF_EXTI_LINE9
02324   *         @arg @ref LL_GPIO_AF_EXTI_LINE10
02325   *         @arg @ref LL_GPIO_AF_EXTI_LINE11
02326   *         @arg @ref LL_GPIO_AF_EXTI_LINE12
02327   *         @arg @ref LL_GPIO_AF_EXTI_LINE13
02328   *         @arg @ref LL_GPIO_AF_EXTI_LINE14
02329   *         @arg @ref LL_GPIO_AF_EXTI_LINE15
02330   * @retval Returned value can be one of the following values:
02331   *         @arg @ref LL_GPIO_AF_EXTI_PORTA
02332   *         @arg @ref LL_GPIO_AF_EXTI_PORTB
02333   *         @arg @ref LL_GPIO_AF_EXTI_PORTC
02334   *         @arg @ref LL_GPIO_AF_EXTI_PORTD
02335   *         @arg @ref LL_GPIO_AF_EXTI_PORTE
02336   *         @arg @ref LL_GPIO_AF_EXTI_PORTF
02337   *         @arg @ref LL_GPIO_AF_EXTI_PORTG
02338   */
02339 __STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
02340 {
02341   return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
02342 }
02343
02344 /**
02345   * @}
02346   */
02347
02348 #if defined(USE_FULL_LL_DRIVER)
02349 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
02350   * @{
02351   */
02352
02353 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
02354 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
02355 void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
02356
02357 /**
02358   * @}
02359   */
02360 #endif /* USE_FULL_LL_DRIVER */
02361
02362 /**
02363   * @}
02364   */
02365
02366 /**
02367   * @}
02368   */
02369
02370 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
02371 /**
02372   * @}
02373   */
02374
02375 #ifdef __cplusplus
02376 }
02377 #endif
02378
02379 #endif /* __STM32F1xx_LL_GPIO_H */
02380
02381 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_i2c.c Source File

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stm32f1xx_ll_i2c.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_i2c.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   I2C LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_i2c.h"
00041 #include "stm32f1xx_ll_bus.h"
00042 #include "stm32f1xx_ll_rcc.h"
00043 #ifdef  USE_FULL_ASSERT
00044 #include "stm32_assert.h"
00045 #else
00046 #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (I2C1) || defined (I2C2)
00054
00055 /** @defgroup I2C_LL I2C
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 /** @addtogroup I2C_LL_Private_Macros
00064   * @{
00065   */
00066
00067 #define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
00068                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
00069                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
00070                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
00071
00072 #define IS_I2C_CLOCK_SPEED(__VALUE__)           (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
00073
00074 #define IS_I2C_DUTY_CYCLE(__VALUE__)            (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
00075                                                  ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
00076
00077 #define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
00078
00079 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
00080                                                  ((__VALUE__) == LL_I2C_NACK))
00081
00082 #define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
00083                                                  ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
00084 /**
00085   * @}
00086   */
00087
00088 /* Private function prototypes -----------------------------------------------*/
00089
00090 /* Exported functions --------------------------------------------------------*/
00091 /** @addtogroup I2C_LL_Exported_Functions
00092   * @{
00093   */
00094
00095 /** @addtogroup I2C_LL_EF_Init
00096   * @{
00097   */
00098
00099 /**
00100   * @brief  De-initialize the I2C registers to their default reset values.
00101   * @param  I2Cx I2C Instance.
00102   * @retval An ErrorStatus enumeration value:
00103   *          - SUCCESS: I2C registers are de-initialized
00104   *          - ERROR: I2C registers are not de-initialized
00105   */
00106 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
00107 {
00108   ErrorStatus status = SUCCESS;
00109
00110   /* Check the I2C Instance I2Cx */
00111   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00112
00113   if (I2Cx == I2C1)
00114   {
00115     /* Force reset of I2C clock */
00116     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
00117
00118     /* Release reset of I2C clock */
00119     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
00120   }
00121   else if (I2Cx == I2C2)
00122   {
00123     /* Force reset of I2C clock */
00124     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
00125
00126     /* Release reset of I2C clock */
00127     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
00128
00129   }
00130   else
00131   {
00132     status = ERROR;
00133   }
00134
00135   return status;
00136 }
00137
00138 /**
00139   * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
00140   * @param  I2Cx I2C Instance.
00141   * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
00142   * @retval An ErrorStatus enumeration value:
00143   *          - SUCCESS: I2C registers are initialized
00144   *          - ERROR: Not applicable
00145   */
00146 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
00147 {
00148   LL_RCC_ClocksTypeDef rcc_clocks;
00149
00150   /* Check the I2C Instance I2Cx */
00151   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
00152
00153   /* Check the I2C parameters from I2C_InitStruct */
00154   assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
00155   assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed));
00156   assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle));
00157   assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
00158   assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
00159   assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
00160
00161   /* Disable the selected I2Cx Peripheral */
00162   LL_I2C_Disable(I2Cx);
00163
00164   /* Retrieve Clock frequencies */
00165   LL_RCC_GetSystemClocksFreq(&rcc_clocks);
00166
00167   /*---------------------------- I2Cx SCL Clock Speed Configuration ------------
00168    * Configure the SCL speed :
00169    * - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS,
00170    *           and I2C_CCR_CCR[11:0] bits
00171    * - DutyCycle: I2C_CCR_DUTY[7:0] bits
00172    */
00173   LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle);
00174
00175   /*---------------------------- I2Cx OAR1 Configuration -----------------------
00176    * Disable, Configure and Enable I2Cx device own address 1 with parameters :
00177    * - OwnAddress1:  I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits
00178    * - OwnAddrSize:  I2C_OAR1_ADDMODE bit
00179    */
00180   LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
00181
00182   /*---------------------------- I2Cx MODE Configuration -----------------------
00183   * Configure I2Cx peripheral mode with parameter :
00184    * - PeripheralMode: I2C_CR1_SMBUS, I2C_CR1_SMBTYPE and I2C_CR1_ENARP bits
00185    */
00186   LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
00187
00188   /* Enable the selected I2Cx Peripheral */
00189   LL_I2C_Enable(I2Cx);
00190
00191   /*---------------------------- I2Cx CR2 Configuration ------------------------
00192    * Configure the ACKnowledge or Non ACKnowledge condition
00193    * after the address receive match code or next received byte with parameter :
00194    * - TypeAcknowledge: I2C_CR2_NACK bit
00195    */
00196   LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
00197
00198   return SUCCESS;
00199 }
00200
00201 /**
00202   * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
00203   * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
00204   * @retval None
00205   */
00206 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
00207 {
00208   /* Set I2C_InitStruct fields to default values */
00209   I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
00210   I2C_InitStruct->ClockSpeed      = 5000U;
00211   I2C_InitStruct->DutyCycle       = LL_I2C_DUTYCYCLE_2;
00212   I2C_InitStruct->OwnAddress1     = 0U;
00213   I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
00214   I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
00215 }
00216
00217 /**
00218   * @}
00219   */
00220
00221 /**
00222   * @}
00223   */
00224
00225 /**
00226   * @}
00227   */
00228
00229 #endif /* I2C1 || I2C2 */
00230
00231 /**
00232   * @}
00233   */
00234
00235 #endif /* USE_FULL_LL_DRIVER */
00236
00237 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_i2c.h Source File

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stm32f1xx_ll_i2c.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_i2c.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of I2C LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_I2C_H
00040 #define __STM32F1xx_LL_I2C_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (I2C1) || defined (I2C2)
00054
00055 /** @defgroup I2C_LL I2C
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
00064   * @{
00065   */
00066
00067 /* Defines used to perform compute and check in the macros */
00068 #define LL_I2C_MAX_SPEED_STANDARD           100000U
00069 #define LL_I2C_MAX_SPEED_FAST               400000U
00070 /**
00071   * @}
00072   */
00073
00074 /* Private macros ------------------------------------------------------------*/
00075 #if defined(USE_FULL_LL_DRIVER)
00076 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
00077   * @{
00078   */
00079 /**
00080   * @}
00081   */
00082 #endif /*USE_FULL_LL_DRIVER*/
00083
00084 /* Exported types ------------------------------------------------------------*/
00085 #if defined(USE_FULL_LL_DRIVER)
00086 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
00087   * @{
00088   */
00089 typedef struct
00090 {
00091   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
00092                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
00093
00094                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
00095
00096   uint32_t ClockSpeed;          /*!< Specifies the clock frequency.
00097                                      This parameter must be set to a value lower than 400kHz (in Hz)
00098
00099                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
00100                                      or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
00101
00102   uint32_t DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
00103                                      This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
00104
00105                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
00106
00107   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
00108                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
00109
00110                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00111
00112   uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
00113                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
00114
00115                                      This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
00116
00117   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
00118                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
00119
00120                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00121 } LL_I2C_InitTypeDef;
00122 /**
00123   * @}
00124   */
00125 #endif /*USE_FULL_LL_DRIVER*/
00126
00127 /* Exported constants --------------------------------------------------------*/
00128 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
00129   * @{
00130   */
00131
00132 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
00133   * @brief    Flags defines which can be used with LL_I2C_ReadReg function
00134   * @{
00135   */
00136 #define LL_I2C_SR1_SB                       I2C_SR1_SB              /*!< Start Bit (master mode)                   */
00137 #define LL_I2C_SR1_ADDR                     I2C_SR1_ADDR            /*!< Address sent (master mode) or
00138                                                                          Address matched flag (slave mode)         */
00139 #define LL_I2C_SR1_BTF                      I2C_SR1_BTF             /*!< Byte Transfer Finished flag               */
00140 #define LL_I2C_SR1_ADD10                    I2C_SR1_ADD10           /*!< 10-bit header sent (master mode)          */
00141 #define LL_I2C_SR1_STOPF                    I2C_SR1_STOPF           /*!< Stop detection flag (slave mode)          */
00142 #define LL_I2C_SR1_RXNE                     I2C_SR1_RXNE            /*!< Data register not empty (receivers)       */
00143 #define LL_I2C_SR1_TXE                      I2C_SR1_TXE             /*!< Data register empty (transmitters)        */
00144 #define LL_I2C_SR1_BERR                     I2C_SR1_BERR            /*!< Bus error                                 */
00145 #define LL_I2C_SR1_ARLO                     I2C_SR1_ARLO            /*!< Arbitration lost                          */
00146 #define LL_I2C_SR1_AF                       I2C_SR1_AF              /*!< Acknowledge failure flag                  */
00147 #define LL_I2C_SR1_OVR                      I2C_SR1_OVR             /*!< Overrun/Underrun                          */
00148 #define LL_I2C_SR1_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode)       */
00149 #define LL_I2C_SR1_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode)       */
00150 #define LL_I2C_SR1_SMALERT                  I2C_ISR_SMALERT         /*!< SMBus alert (SMBus mode)                  */
00151 #define LL_I2C_SR2_MSL                      I2C_SR2_MSL             /*!< Master/Slave flag                         */
00152 #define LL_I2C_SR2_BUSY                     I2C_SR2_BUSY            /*!< Bus busy flag                             */
00153 #define LL_I2C_SR2_TRA                      I2C_SR2_TRA             /*!< Transmitter/receiver direction            */
00154 #define LL_I2C_SR2_GENCALL                  I2C_SR2_GENCALL         /*!< General call address (Slave mode)         */
00155 #define LL_I2C_SR2_SMBDEFAULT               I2C_SR2_SMBDEFAULT      /*!< SMBus Device default address (Slave mode) */
00156 #define LL_I2C_SR2_SMBHOST                  I2C_SR2_SMBHOST         /*!< SMBus Host address (Slave mode)           */
00157 #define LL_I2C_SR2_DUALF                    I2C_SR2_DUALF           /*!< Dual flag  (Slave mode)                   */
00158 /**
00159   * @}
00160   */
00161
00162 /** @defgroup I2C_LL_EC_IT IT Defines
00163   * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
00164   * @{
00165   */
00166 #define LL_I2C_CR2_ITEVTEN                  I2C_CR2_ITEVTEN         /*!< Events interrupts enable */
00167 #define LL_I2C_CR2_ITBUFEN                  I2C_CR2_ITBUFEN         /*!< Buffer interrupts enable */
00168 #define LL_I2C_CR2_ITERREN                  I2C_CR2_ITERREN         /*!< Error interrupts enable  */
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
00174   * @{
00175   */
00176 #define LL_I2C_OWNADDRESS1_7BIT             0x00004000U                                /*!< Own address 1 is a 7-bit address.   */
00177 #define LL_I2C_OWNADDRESS1_10BIT            (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address.  */
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
00183   * @{
00184   */
00185 #define LL_I2C_DUTYCYCLE_2                  0x00000000U             /*!< I2C fast mode Tlow/Thigh = 2        */
00186 #define LL_I2C_DUTYCYCLE_16_9               I2C_CCR_DUTY            /*!< I2C fast mode Tlow/Thigh = 16/9     */
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
00192   * @{
00193   */
00194 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE    0x00000000U             /*!< Master clock speed range is standard mode */
00195 #define LL_I2C_CLOCK_SPEED_FAST_MODE        I2C_CCR_FS              /*!< Master clock speed range is fast mode     */
00196 /**
00197   * @}
00198   */
00199
00200 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
00201   * @{
00202   */
00203 #define LL_I2C_MODE_I2C                     0x00000000U                                                 /*!< I2C Master or Slave mode                                    */
00204 #define LL_I2C_MODE_SMBUS_HOST              (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge                              */
00205 #define LL_I2C_MODE_SMBUS_DEVICE            I2C_CR1_SMBUS                                               /*!< SMBus Device default mode (Default address not acknowledge) */
00206 #define LL_I2C_MODE_SMBUS_DEVICE_ARP        (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP)                   /*!< SMBus Device Default address acknowledge                    */
00207 /**
00208   * @}
00209   */
00210
00211 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
00212   * @{
00213   */
00214 #define LL_I2C_ACK                          I2C_CR1_ACK             /*!< ACK is sent after current received byte. */
00215 #define LL_I2C_NACK                         0x00000000U             /*!< NACK is sent after current received byte.*/
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
00221   * @{
00222   */
00223 #define LL_I2C_DIRECTION_WRITE              I2C_SR2_TRA             /*!< Bus is in write transfer */
00224 #define LL_I2C_DIRECTION_READ               0x00000000U             /*!< Bus is in read transfer  */
00225 /**
00226   * @}
00227   */
00228
00229 /**
00230   * @}
00231   */
00232
00233 /* Exported macro ------------------------------------------------------------*/
00234 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
00235   * @{
00236   */
00237
00238 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
00239   * @{
00240   */
00241
00242 /**
00243   * @brief  Write a value in I2C register
00244   * @param  __INSTANCE__ I2C Instance
00245   * @param  __REG__ Register to be written
00246   * @param  __VALUE__ Value to be written in the register
00247   * @retval None
00248   */
00249 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00250
00251 /**
00252   * @brief  Read a value in I2C register
00253   * @param  __INSTANCE__ I2C Instance
00254   * @param  __REG__ Register to be read
00255   * @retval Register value
00256   */
00257 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00258 /**
00259   * @}
00260   */
00261
00262 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
00263   * @{
00264   */
00265
00266 /**
00267   * @brief  Convert Peripheral Clock Frequency in Mhz.
00268   * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
00269   * @retval Value of peripheral clock (in Mhz)
00270   */
00271 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__)                               (uint32_t)((__PCLK__)/1000000U)
00272
00273 /**
00274   * @brief  Convert Peripheral Clock Frequency in Hz.
00275   * @param  __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
00276   * @retval Value of peripheral clock (in Hz)
00277   */
00278 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__)                               (uint32_t)((__PCLK__)*1000000U)
00279
00280 /**
00281   * @brief  Compute I2C Clock rising time.
00282   * @param  __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
00283   * @param  __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
00284   * @retval Value between Min_Data=0x02 and Max_Data=0x3F
00285   */
00286 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__)                    (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
00287
00288 /**
00289   * @brief  Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
00290   * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
00291   * @param  __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
00292   * @param  __DUTYCYCLE__ This parameter can be one of the following values:
00293   *         @arg @ref LL_I2C_DUTYCYCLE_2
00294   *         @arg @ref LL_I2C_DUTYCYCLE_16_9
00295   * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
00296   */
00297 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__)       (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
00298                                                                                   (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
00299                                                                                   (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
00300
00301 /**
00302   * @brief  Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
00303   * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
00304   * @param  __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
00305   * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
00306   */
00307 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__)             (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
00308
00309 /**
00310   * @brief  Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
00311   * @param  __PCLK__ This parameter must be a value of peripheral clock (in Hz).
00312   * @param  __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
00313   * @param  __DUTYCYCLE__ This parameter can be one of the following values:
00314   *         @arg @ref LL_I2C_DUTYCYCLE_2
00315   *         @arg @ref LL_I2C_DUTYCYCLE_16_9
00316   * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
00317   */
00318 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__)  (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
00319                                                                             (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
00320                                                                             (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
00321
00322 /**
00323   * @brief  Get the Least significant bits of a 10-Bits address.
00324   * @param  __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
00325   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00326   */
00327 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__)                             ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
00328
00329 /**
00330   * @brief  Convert a 10-Bits address to a 10-Bits header with Write direction.
00331   * @param  __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
00332   * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
00333   */
00334 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__)                        ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
00335
00336 /**
00337   * @brief  Convert a 10-Bits address to a 10-Bits header with Read direction.
00338   * @param  __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
00339   * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
00340   */
00341 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__)                         ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
00342
00343 /**
00344   * @}
00345   */
00346
00347 /**
00348   * @}
00349   */
00350
00351 /* Exported functions --------------------------------------------------------*/
00352
00353 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
00354   * @{
00355   */
00356
00357 /** @defgroup I2C_LL_EF_Configuration Configuration
00358   * @{
00359   */
00360
00361 /**
00362   * @brief  Enable I2C peripheral (PE = 1).
00363   * @rmtoll CR1          PE            LL_I2C_Enable
00364   * @param  I2Cx I2C Instance.
00365   * @retval None
00366   */
00367 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
00368 {
00369   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
00370 }
00371
00372 /**
00373   * @brief  Disable I2C peripheral (PE = 0).
00374   * @rmtoll CR1          PE            LL_I2C_Disable
00375   * @param  I2Cx I2C Instance.
00376   * @retval None
00377   */
00378 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
00379 {
00380   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
00381 }
00382
00383 /**
00384   * @brief  Check if the I2C peripheral is enabled or disabled.
00385   * @rmtoll CR1          PE            LL_I2C_IsEnabled
00386   * @param  I2Cx I2C Instance.
00387   * @retval State of bit (1 or 0).
00388   */
00389 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
00390 {
00391   return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
00392 }
00393
00394
00395 /**
00396   * @brief  Enable DMA transmission requests.
00397   * @rmtoll CR2          DMAEN         LL_I2C_EnableDMAReq_TX
00398   * @param  I2Cx I2C Instance.
00399   * @retval None
00400   */
00401 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
00402 {
00403   SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
00404 }
00405
00406 /**
00407   * @brief  Disable DMA transmission requests.
00408   * @rmtoll CR2          DMAEN         LL_I2C_DisableDMAReq_TX
00409   * @param  I2Cx I2C Instance.
00410   * @retval None
00411   */
00412 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
00413 {
00414   CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
00415 }
00416
00417 /**
00418   * @brief  Check if DMA transmission requests are enabled or disabled.
00419   * @rmtoll CR2          DMAEN         LL_I2C_IsEnabledDMAReq_TX
00420   * @param  I2Cx I2C Instance.
00421   * @retval State of bit (1 or 0).
00422   */
00423 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
00424 {
00425   return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
00426 }
00427
00428 /**
00429   * @brief  Enable DMA reception requests.
00430   * @rmtoll CR2          DMAEN         LL_I2C_EnableDMAReq_RX
00431   * @param  I2Cx I2C Instance.
00432   * @retval None
00433   */
00434 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
00435 {
00436   SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
00437 }
00438
00439 /**
00440   * @brief  Disable DMA reception requests.
00441   * @rmtoll CR2          DMAEN         LL_I2C_DisableDMAReq_RX
00442   * @param  I2Cx I2C Instance.
00443   * @retval None
00444   */
00445 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
00446 {
00447   CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
00448 }
00449
00450 /**
00451   * @brief  Check if DMA reception requests are enabled or disabled.
00452   * @rmtoll CR2          DMAEN         LL_I2C_IsEnabledDMAReq_RX
00453   * @param  I2Cx I2C Instance.
00454   * @retval State of bit (1 or 0).
00455   */
00456 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
00457 {
00458   return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
00459 }
00460
00461 /**
00462   * @brief  Get the data register address used for DMA transfer.
00463   * @rmtoll DR           DR            LL_I2C_DMA_GetRegAddr
00464   * @param  I2Cx I2C Instance.
00465   * @retval Address of data register
00466   */
00467 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
00468 {
00469   return (uint32_t) & (I2Cx->DR);
00470 }
00471
00472 /**
00473   * @brief  Enable Clock stretching.
00474   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00475   * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
00476   * @param  I2Cx I2C Instance.
00477   * @retval None
00478   */
00479 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
00480 {
00481   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00482 }
00483
00484 /**
00485   * @brief  Disable Clock stretching.
00486   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00487   * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
00488   * @param  I2Cx I2C Instance.
00489   * @retval None
00490   */
00491 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
00492 {
00493   SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00494 }
00495
00496 /**
00497   * @brief  Check if Clock stretching is enabled or disabled.
00498   * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
00499   * @param  I2Cx I2C Instance.
00500   * @retval State of bit (1 or 0).
00501   */
00502 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
00503 {
00504   return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
00505 }
00506
00507 /**
00508   * @brief  Enable General Call.
00509   * @note   When enabled the Address 0x00 is ACKed.
00510   * @rmtoll CR1          ENGC          LL_I2C_EnableGeneralCall
00511   * @param  I2Cx I2C Instance.
00512   * @retval None
00513   */
00514 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
00515 {
00516   SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
00517 }
00518
00519 /**
00520   * @brief  Disable General Call.
00521   * @note   When disabled the Address 0x00 is NACKed.
00522   * @rmtoll CR1          ENGC          LL_I2C_DisableGeneralCall
00523   * @param  I2Cx I2C Instance.
00524   * @retval None
00525   */
00526 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
00527 {
00528   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
00529 }
00530
00531 /**
00532   * @brief  Check if General Call is enabled or disabled.
00533   * @rmtoll CR1          ENGC          LL_I2C_IsEnabledGeneralCall
00534   * @param  I2Cx I2C Instance.
00535   * @retval State of bit (1 or 0).
00536   */
00537 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
00538 {
00539   return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
00540 }
00541
00542 /**
00543   * @brief  Set the Own Address1.
00544   * @rmtoll OAR1         ADD0          LL_I2C_SetOwnAddress1\n
00545   *         OAR1         ADD1_7        LL_I2C_SetOwnAddress1\n
00546   *         OAR1         ADD8_9        LL_I2C_SetOwnAddress1\n
00547   *         OAR1         ADDMODE       LL_I2C_SetOwnAddress1
00548   * @param  I2Cx I2C Instance.
00549   * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
00550   * @param  OwnAddrSize This parameter can be one of the following values:
00551   *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
00552   *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
00553   * @retval None
00554   */
00555 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
00556 {
00557   MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
00558 }
00559
00560 /**
00561   * @brief  Set the 7bits Own Address2.
00562   * @note   This action has no effect if own address2 is enabled.
00563   * @rmtoll OAR2         ADD2          LL_I2C_SetOwnAddress2
00564   * @param  I2Cx I2C Instance.
00565   * @param  OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
00566   * @retval None
00567   */
00568 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
00569 {
00570   MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
00571 }
00572
00573 /**
00574   * @brief  Enable acknowledge on Own Address2 match address.
00575   * @rmtoll OAR2         ENDUAL        LL_I2C_EnableOwnAddress2
00576   * @param  I2Cx I2C Instance.
00577   * @retval None
00578   */
00579 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
00580 {
00581   SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
00582 }
00583
00584 /**
00585   * @brief  Disable  acknowledge on Own Address2 match address.
00586   * @rmtoll OAR2         ENDUAL        LL_I2C_DisableOwnAddress2
00587   * @param  I2Cx I2C Instance.
00588   * @retval None
00589   */
00590 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
00591 {
00592   CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
00593 }
00594
00595 /**
00596   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00597   * @rmtoll OAR2         ENDUAL        LL_I2C_IsEnabledOwnAddress2
00598   * @param  I2Cx I2C Instance.
00599   * @retval State of bit (1 or 0).
00600   */
00601 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
00602 {
00603   return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
00604 }
00605
00606 /**
00607   * @brief  Configure the Peripheral clock frequency.
00608   * @rmtoll CR2          FREQ          LL_I2C_SetPeriphClock
00609   * @param  I2Cx I2C Instance.
00610   * @param  PeriphClock Peripheral Clock (in Hz)
00611   * @retval None
00612   */
00613 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
00614 {
00615   MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
00616 }
00617
00618 /**
00619   * @brief  Get the Peripheral clock frequency.
00620   * @rmtoll CR2          FREQ          LL_I2C_GetPeriphClock
00621   * @param  I2Cx I2C Instance.
00622   * @retval Value of Peripheral Clock (in Hz)
00623   */
00624 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
00625 {
00626   return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
00627 }
00628
00629 /**
00630   * @brief  Configure the Duty cycle (Fast mode only).
00631   * @rmtoll CCR          DUTY          LL_I2C_SetDutyCycle
00632   * @param  I2Cx I2C Instance.
00633   * @param  DutyCycle This parameter can be one of the following values:
00634   *         @arg @ref LL_I2C_DUTYCYCLE_2
00635   *         @arg @ref LL_I2C_DUTYCYCLE_16_9
00636   * @retval None
00637   */
00638 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
00639 {
00640   MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
00641 }
00642
00643 /**
00644   * @brief  Get the Duty cycle (Fast mode only).
00645   * @rmtoll CCR          DUTY          LL_I2C_GetDutyCycle
00646   * @param  I2Cx I2C Instance.
00647   * @retval Returned value can be one of the following values:
00648   *         @arg @ref LL_I2C_DUTYCYCLE_2
00649   *         @arg @ref LL_I2C_DUTYCYCLE_16_9
00650   */
00651 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
00652 {
00653   return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
00654 }
00655
00656 /**
00657   * @brief  Configure the I2C master clock speed mode.
00658   * @rmtoll CCR          FS            LL_I2C_SetClockSpeedMode
00659   * @param  I2Cx I2C Instance.
00660   * @param  ClockSpeedMode This parameter can be one of the following values:
00661   *         @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
00662   *         @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
00663   * @retval None
00664   */
00665 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
00666 {
00667   MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
00668 }
00669
00670 /**
00671   * @brief  Get the the I2C master speed mode.
00672   * @rmtoll CCR          FS            LL_I2C_GetClockSpeedMode
00673   * @param  I2Cx I2C Instance.
00674   * @retval Returned value can be one of the following values:
00675   *         @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
00676   *         @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
00677   */
00678 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
00679 {
00680   return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
00681 }
00682
00683 /**
00684   * @brief  Configure the SCL, SDA rising time.
00685   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00686   * @rmtoll TRISE        TRISE         LL_I2C_SetRiseTime
00687   * @param  I2Cx I2C Instance.
00688   * @param  RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
00689   * @retval None
00690   */
00691 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
00692 {
00693   MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
00694 }
00695
00696 /**
00697   * @brief  Get the SCL, SDA rising time.
00698   * @rmtoll TRISE        TRISE         LL_I2C_GetRiseTime
00699   * @param  I2Cx I2C Instance.
00700   * @retval Value between Min_Data=0x02 and Max_Data=0x3F
00701   */
00702 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
00703 {
00704   return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
00705 }
00706
00707 /**
00708   * @brief  Configure the SCL high and low period.
00709   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00710   * @rmtoll CCR          CCR           LL_I2C_SetClockPeriod
00711   * @param  I2Cx I2C Instance.
00712   * @param  ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
00713   * @retval None
00714   */
00715 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
00716 {
00717   MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
00718 }
00719
00720 /**
00721   * @brief  Get the SCL high and low period.
00722   * @rmtoll CCR          CCR           LL_I2C_GetClockPeriod
00723   * @param  I2Cx I2C Instance.
00724   * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
00725   */
00726 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
00727 {
00728   return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
00729 }
00730
00731 /**
00732   * @brief  Configure the SCL speed.
00733   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00734   * @rmtoll CR2          FREQ          LL_I2C_ConfigSpeed\n
00735   *         TRISE        TRISE         LL_I2C_ConfigSpeed\n
00736   *         CCR          FS            LL_I2C_ConfigSpeed\n
00737   *         CCR          DUTY          LL_I2C_ConfigSpeed\n
00738   *         CCR          CCR           LL_I2C_ConfigSpeed
00739   * @param  I2Cx I2C Instance.
00740   * @param  PeriphClock Peripheral Clock (in Hz)
00741   * @param  ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
00742   * @param  DutyCycle This parameter can be one of the following values:
00743   *         @arg @ref LL_I2C_DUTYCYCLE_2
00744   *         @arg @ref LL_I2C_DUTYCYCLE_16_9
00745   * @retval None
00746   */
00747 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
00748                                         uint32_t DutyCycle)
00749 {
00750   register uint32_t freqrange = 0x0U;
00751   register uint32_t clockconfig = 0x0U;
00752
00753   /* Compute frequency range */
00754   freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
00755
00756   /* Configure I2Cx: Frequency range register */
00757   MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
00758
00759   /* Configure I2Cx: Rise Time register */
00760   MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
00761
00762   /* Configure Speed mode, Duty Cycle and Clock control register value */
00763   if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
00764   {
00765     /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
00766     clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE                                          | \
00767                   __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle)        | \
00768                   DutyCycle;
00769   }
00770   else
00771   {
00772     /* Set Speed mode at standard for Clock Speed request in standard clock range */
00773     clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE                                      | \
00774                   __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
00775   }
00776
00777   /* Configure I2Cx: Clock control register */
00778   MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
00779 }
00780
00781 /**
00782   * @brief  Configure peripheral mode.
00783   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00784   *         SMBus feature is supported by the I2Cx Instance.
00785   * @rmtoll CR1          SMBUS         LL_I2C_SetMode\n
00786   *         CR1          SMBTYPE       LL_I2C_SetMode\n
00787   *         CR1          ENARP         LL_I2C_SetMode
00788   * @param  I2Cx I2C Instance.
00789   * @param  PeripheralMode This parameter can be one of the following values:
00790   *         @arg @ref LL_I2C_MODE_I2C
00791   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00792   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00793   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00794   * @retval None
00795   */
00796 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
00797 {
00798   MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
00799 }
00800
00801 /**
00802   * @brief  Get peripheral mode.
00803   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00804   *         SMBus feature is supported by the I2Cx Instance.
00805   * @rmtoll CR1          SMBUS         LL_I2C_GetMode\n
00806   *         CR1          SMBTYPE       LL_I2C_GetMode\n
00807   *         CR1          ENARP         LL_I2C_GetMode
00808   * @param  I2Cx I2C Instance.
00809   * @retval Returned value can be one of the following values:
00810   *         @arg @ref LL_I2C_MODE_I2C
00811   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00812   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00813   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00814   */
00815 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
00816 {
00817   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
00818 }
00819
00820 /**
00821   * @brief  Enable SMBus alert (Host or Device mode)
00822   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00823   *         SMBus feature is supported by the I2Cx Instance.
00824   * @note   SMBus Device mode:
00825   *         - SMBus Alert pin is drived low and
00826   *           Alert Response Address Header acknowledge is enabled.
00827   *         SMBus Host mode:
00828   *         - SMBus Alert pin management is supported.
00829   * @rmtoll CR1          ALERT         LL_I2C_EnableSMBusAlert
00830   * @param  I2Cx I2C Instance.
00831   * @retval None
00832   */
00833 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
00834 {
00835   SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
00836 }
00837
00838 /**
00839   * @brief  Disable SMBus alert (Host or Device mode)
00840   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00841   *         SMBus feature is supported by the I2Cx Instance.
00842   * @note   SMBus Device mode:
00843   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
00844   *           Alert Response Address Header acknowledge is disabled.
00845   *         SMBus Host mode:
00846   *         - SMBus Alert pin management is not supported.
00847   * @rmtoll CR1          ALERT         LL_I2C_DisableSMBusAlert
00848   * @param  I2Cx I2C Instance.
00849   * @retval None
00850   */
00851 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
00852 {
00853   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
00854 }
00855
00856 /**
00857   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
00858   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00859   *         SMBus feature is supported by the I2Cx Instance.
00860   * @rmtoll CR1          ALERT         LL_I2C_IsEnabledSMBusAlert
00861   * @param  I2Cx I2C Instance.
00862   * @retval State of bit (1 or 0).
00863   */
00864 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
00865 {
00866   return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
00867 }
00868
00869 /**
00870   * @brief  Enable SMBus Packet Error Calculation (PEC).
00871   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00872   *         SMBus feature is supported by the I2Cx Instance.
00873   * @rmtoll CR1          ENPEC         LL_I2C_EnableSMBusPEC
00874   * @param  I2Cx I2C Instance.
00875   * @retval None
00876   */
00877 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
00878 {
00879   SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
00880 }
00881
00882 /**
00883   * @brief  Disable SMBus Packet Error Calculation (PEC).
00884   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00885   *         SMBus feature is supported by the I2Cx Instance.
00886   * @rmtoll CR1          ENPEC         LL_I2C_DisableSMBusPEC
00887   * @param  I2Cx I2C Instance.
00888   * @retval None
00889   */
00890 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
00891 {
00892   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
00893 }
00894
00895 /**
00896   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
00897   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00898   *         SMBus feature is supported by the I2Cx Instance.
00899   * @rmtoll CR1          ENPEC         LL_I2C_IsEnabledSMBusPEC
00900   * @param  I2Cx I2C Instance.
00901   * @retval State of bit (1 or 0).
00902   */
00903 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
00904 {
00905   return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
00906 }
00907
00908 /**
00909   * @}
00910   */
00911
00912 /** @defgroup I2C_LL_EF_IT_Management IT_Management
00913   * @{
00914   */
00915
00916 /**
00917   * @brief  Enable TXE interrupt.
00918   * @rmtoll CR2          ITEVTEN       LL_I2C_EnableIT_TX\n
00919   *         CR2          ITBUFEN       LL_I2C_EnableIT_TX
00920   * @param  I2Cx I2C Instance.
00921   * @retval None
00922   */
00923 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
00924 {
00925   SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
00926 }
00927
00928 /**
00929   * @brief  Disable TXE interrupt.
00930   * @rmtoll CR2          ITEVTEN       LL_I2C_DisableIT_TX\n
00931   *         CR2          ITBUFEN       LL_I2C_DisableIT_TX
00932   * @param  I2Cx I2C Instance.
00933   * @retval None
00934   */
00935 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
00936 {
00937   CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
00938 }
00939
00940 /**
00941   * @brief  Check if the TXE Interrupt is enabled or disabled.
00942   * @rmtoll CR2          ITEVTEN       LL_I2C_IsEnabledIT_TX\n
00943   *         CR2          ITBUFEN       LL_I2C_IsEnabledIT_TX
00944   * @param  I2Cx I2C Instance.
00945   * @retval State of bit (1 or 0).
00946   */
00947 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
00948 {
00949   return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
00950 }
00951
00952 /**
00953   * @brief  Enable RXNE interrupt.
00954   * @rmtoll CR2          ITEVTEN       LL_I2C_EnableIT_RX\n
00955   *         CR2          ITBUFEN       LL_I2C_EnableIT_RX
00956   * @param  I2Cx I2C Instance.
00957   * @retval None
00958   */
00959 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
00960 {
00961   SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
00962 }
00963
00964 /**
00965   * @brief  Disable RXNE interrupt.
00966   * @rmtoll CR2          ITEVTEN       LL_I2C_DisableIT_RX\n
00967   *         CR2          ITBUFEN       LL_I2C_DisableIT_RX
00968   * @param  I2Cx I2C Instance.
00969   * @retval None
00970   */
00971 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
00972 {
00973   CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
00974 }
00975
00976 /**
00977   * @brief  Check if the RXNE Interrupt is enabled or disabled.
00978   * @rmtoll CR2          ITEVTEN       LL_I2C_IsEnabledIT_RX\n
00979   *         CR2          ITBUFEN       LL_I2C_IsEnabledIT_RX
00980   * @param  I2Cx I2C Instance.
00981   * @retval State of bit (1 or 0).
00982   */
00983 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
00984 {
00985   return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
00986 }
00987
00988 /**
00989   * @brief  Enable Events interrupts.
00990   * @note   Any of these events will generate interrupt :
00991   *         Start Bit (SB)
00992   *         Address sent, Address matched (ADDR)
00993   *         10-bit header sent (ADD10)
00994   *         Stop detection  (STOPF)
00995   *         Byte transfer finished (BTF)
00996   *
00997   * @note   Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
00998   *         Receive buffer not empty (RXNE)
00999   *         Transmit buffer empty (TXE)
01000   * @rmtoll CR2          ITEVTEN       LL_I2C_EnableIT_EVT
01001   * @param  I2Cx I2C Instance.
01002   * @retval None
01003   */
01004 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
01005 {
01006   SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
01007 }
01008
01009 /**
01010   * @brief  Disable Events interrupts.
01011   * @note   Any of these events will generate interrupt :
01012   *         Start Bit (SB)
01013   *         Address sent, Address matched (ADDR)
01014   *         10-bit header sent (ADD10)
01015   *         Stop detection  (STOPF)
01016   *         Byte transfer finished (BTF)
01017   *         Receive buffer not empty (RXNE)
01018   *         Transmit buffer empty (TXE)
01019   * @rmtoll CR2          ITEVTEN       LL_I2C_DisableIT_EVT
01020   * @param  I2Cx I2C Instance.
01021   * @retval None
01022   */
01023 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
01024 {
01025   CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
01026 }
01027
01028 /**
01029   * @brief  Check if Events interrupts are enabled or disabled.
01030   * @rmtoll CR2          ITEVTEN       LL_I2C_IsEnabledIT_EVT
01031   * @param  I2Cx I2C Instance.
01032   * @retval State of bit (1 or 0).
01033   */
01034 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
01035 {
01036   return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
01037 }
01038
01039 /**
01040   * @brief  Enable Buffer interrupts.
01041   * @note   Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
01042   *         Receive buffer not empty (RXNE)
01043   *         Transmit buffer empty (TXE)
01044   * @rmtoll CR2          ITBUFEN       LL_I2C_EnableIT_BUF
01045   * @param  I2Cx I2C Instance.
01046   * @retval None
01047   */
01048 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
01049 {
01050   SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
01051 }
01052
01053 /**
01054   * @brief  Disable Buffer interrupts.
01055   * @note   Any of these Buffer events will generate interrupt :
01056   *         Receive buffer not empty (RXNE)
01057   *         Transmit buffer empty (TXE)
01058   * @rmtoll CR2          ITBUFEN       LL_I2C_DisableIT_BUF
01059   * @param  I2Cx I2C Instance.
01060   * @retval None
01061   */
01062 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
01063 {
01064   CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
01065 }
01066
01067 /**
01068   * @brief  Check if Buffer interrupts are enabled or disabled.
01069   * @rmtoll CR2          ITBUFEN       LL_I2C_IsEnabledIT_BUF
01070   * @param  I2Cx I2C Instance.
01071   * @retval State of bit (1 or 0).
01072   */
01073 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
01074 {
01075   return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
01076 }
01077
01078 /**
01079   * @brief  Enable Error interrupts.
01080   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01081   *         SMBus feature is supported by the I2Cx Instance.
01082   * @note   Any of these errors will generate interrupt :
01083   *         Bus Error detection (BERR)
01084   *         Arbitration Loss (ARLO)
01085   *         Acknowledge Failure(AF)
01086   *         Overrun/Underrun (OVR)
01087   *         SMBus Timeout detection (TIMEOUT)
01088   *         SMBus PEC error detection (PECERR)
01089   *         SMBus Alert pin event detection (SMBALERT)
01090   * @rmtoll CR2          ITERREN       LL_I2C_EnableIT_ERR
01091   * @param  I2Cx I2C Instance.
01092   * @retval None
01093   */
01094 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
01095 {
01096   SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
01097 }
01098
01099 /**
01100   * @brief  Disable Error interrupts.
01101   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01102   *         SMBus feature is supported by the I2Cx Instance.
01103   * @note   Any of these errors will generate interrupt :
01104   *         Bus Error detection (BERR)
01105   *         Arbitration Loss (ARLO)
01106   *         Acknowledge Failure(AF)
01107   *         Overrun/Underrun (OVR)
01108   *         SMBus Timeout detection (TIMEOUT)
01109   *         SMBus PEC error detection (PECERR)
01110   *         SMBus Alert pin event detection (SMBALERT)
01111   * @rmtoll CR2          ITERREN       LL_I2C_DisableIT_ERR
01112   * @param  I2Cx I2C Instance.
01113   * @retval None
01114   */
01115 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
01116 {
01117   CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
01118 }
01119
01120 /**
01121   * @brief  Check if Error interrupts are enabled or disabled.
01122   * @rmtoll CR2          ITERREN       LL_I2C_IsEnabledIT_ERR
01123   * @param  I2Cx I2C Instance.
01124   * @retval State of bit (1 or 0).
01125   */
01126 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
01127 {
01128   return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
01129 }
01130
01131 /**
01132   * @}
01133   */
01134
01135 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
01136   * @{
01137   */
01138
01139 /**
01140   * @brief  Indicate the status of Transmit data register empty flag.
01141   * @note   RESET: When next data is written in Transmit data register.
01142   *         SET: When Transmit data register is empty.
01143   * @rmtoll SR1          TXE           LL_I2C_IsActiveFlag_TXE
01144   * @param  I2Cx I2C Instance.
01145   * @retval State of bit (1 or 0).
01146   */
01147 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
01148 {
01149   return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
01150 }
01151
01152 /**
01153   * @brief  Indicate the status of Byte Transfer Finished flag.
01154   *         RESET: When Data byte transfer not done.
01155   *         SET: When Data byte transfer succeeded.
01156   * @rmtoll SR1          BTF           LL_I2C_IsActiveFlag_BTF
01157   * @param  I2Cx I2C Instance.
01158   * @retval State of bit (1 or 0).
01159   */
01160 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
01161 {
01162   return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
01163 }
01164
01165 /**
01166   * @brief  Indicate the status of Receive data register not empty flag.
01167   * @note   RESET: When Receive data register is read.
01168   *         SET: When the received data is copied in Receive data register.
01169   * @rmtoll SR1          RXNE          LL_I2C_IsActiveFlag_RXNE
01170   * @param  I2Cx I2C Instance.
01171   * @retval State of bit (1 or 0).
01172   */
01173 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
01174 {
01175   return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
01176 }
01177
01178 /**
01179   * @brief  Indicate the status of Start Bit (master mode).
01180   * @note   RESET: When No Start condition.
01181   *         SET: When Start condition is generated.
01182   * @rmtoll SR1          SB            LL_I2C_IsActiveFlag_SB
01183   * @param  I2Cx I2C Instance.
01184   * @retval State of bit (1 or 0).
01185   */
01186 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
01187 {
01188   return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
01189 }
01190
01191 /**
01192   * @brief  Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
01193   * @note   RESET: Clear default value.
01194   *         SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
01195   * @rmtoll SR1          ADDR          LL_I2C_IsActiveFlag_ADDR
01196   * @param  I2Cx I2C Instance.
01197   * @retval State of bit (1 or 0).
01198   */
01199 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
01200 {
01201   return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
01202 }
01203
01204 /**
01205   * @brief  Indicate the status of 10-bit header sent (master mode).
01206   * @note   RESET: When no ADD10 event occured.
01207   *         SET: When the master has sent the first address byte (header).
01208   * @rmtoll SR1          ADD10         LL_I2C_IsActiveFlag_ADD10
01209   * @param  I2Cx I2C Instance.
01210   * @retval State of bit (1 or 0).
01211   */
01212 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
01213 {
01214   return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
01215 }
01216
01217 /**
01218   * @brief  Indicate the status of Acknowledge failure flag.
01219   * @note   RESET: No acknowledge failure.
01220   *         SET: When an acknowledge failure is received after a byte transmission.
01221   * @rmtoll SR1          AF            LL_I2C_IsActiveFlag_AF
01222   * @param  I2Cx I2C Instance.
01223   * @retval State of bit (1 or 0).
01224   */
01225 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
01226 {
01227   return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
01228 }
01229
01230 /**
01231   * @brief  Indicate the status of Stop detection flag (slave mode).
01232   * @note   RESET: Clear default value.
01233   *         SET: When a Stop condition is detected.
01234   * @rmtoll SR1          STOPF         LL_I2C_IsActiveFlag_STOP
01235   * @param  I2Cx I2C Instance.
01236   * @retval State of bit (1 or 0).
01237   */
01238 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
01239 {
01240   return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
01241 }
01242
01243 /**
01244   * @brief  Indicate the status of Bus error flag.
01245   * @note   RESET: Clear default value.
01246   *         SET: When a misplaced Start or Stop condition is detected.
01247   * @rmtoll SR1          BERR          LL_I2C_IsActiveFlag_BERR
01248   * @param  I2Cx I2C Instance.
01249   * @retval State of bit (1 or 0).
01250   */
01251 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
01252 {
01253   return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
01254 }
01255
01256 /**
01257   * @brief  Indicate the status of Arbitration lost flag.
01258   * @note   RESET: Clear default value.
01259   *         SET: When arbitration lost.
01260   * @rmtoll SR1          ARLO          LL_I2C_IsActiveFlag_ARLO
01261   * @param  I2Cx I2C Instance.
01262   * @retval State of bit (1 or 0).
01263   */
01264 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
01265 {
01266   return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
01267 }
01268
01269 /**
01270   * @brief  Indicate the status of Overrun/Underrun flag.
01271   * @note   RESET: Clear default value.
01272   *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
01273   * @rmtoll SR1          OVR           LL_I2C_IsActiveFlag_OVR
01274   * @param  I2Cx I2C Instance.
01275   * @retval State of bit (1 or 0).
01276   */
01277 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
01278 {
01279   return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
01280 }
01281
01282 /**
01283   * @brief  Indicate the status of SMBus PEC error flag in reception.
01284   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01285   *         SMBus feature is supported by the I2Cx Instance.
01286   * @rmtoll SR1          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
01287   * @param  I2Cx I2C Instance.
01288   * @retval State of bit (1 or 0).
01289   */
01290 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01291 {
01292   return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
01293 }
01294
01295 /**
01296   * @brief  Indicate the status of SMBus Timeout detection flag.
01297   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01298   *         SMBus feature is supported by the I2Cx Instance.
01299   * @rmtoll SR1          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
01300   * @param  I2Cx I2C Instance.
01301   * @retval State of bit (1 or 0).
01302   */
01303 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01304 {
01305   return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
01306 }
01307
01308 /**
01309   * @brief  Indicate the status of SMBus alert flag.
01310   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01311   *         SMBus feature is supported by the I2Cx Instance.
01312   * @rmtoll SR1          SMBALERT      LL_I2C_IsActiveSMBusFlag_ALERT
01313   * @param  I2Cx I2C Instance.
01314   * @retval State of bit (1 or 0).
01315   */
01316 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01317 {
01318   return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
01319 }
01320
01321 /**
01322   * @brief  Indicate the status of Bus Busy flag.
01323   * @note   RESET: Clear default value.
01324   *         SET: When a Start condition is detected.
01325   * @rmtoll SR2          BUSY          LL_I2C_IsActiveFlag_BUSY
01326   * @param  I2Cx I2C Instance.
01327   * @retval State of bit (1 or 0).
01328   */
01329 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
01330 {
01331   return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
01332 }
01333
01334 /**
01335   * @brief  Indicate the status of Dual flag.
01336   * @note   RESET: Received address matched with OAR1.
01337   *         SET: Received address matched with OAR2.
01338   * @rmtoll SR2          DUALF         LL_I2C_IsActiveFlag_DUAL
01339   * @param  I2Cx I2C Instance.
01340   * @retval State of bit (1 or 0).
01341   */
01342 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
01343 {
01344   return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
01345 }
01346
01347 /**
01348   * @brief  Indicate the status of SMBus Host address reception (Slave mode).
01349   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01350   *         SMBus feature is supported by the I2Cx Instance.
01351   * @note   RESET: No SMBus Host address
01352   *         SET: SMBus Host address received.
01353   * @note   This status is cleared by hardware after a STOP condition or repeated START condition.
01354   * @rmtoll SR2          SMBHOST       LL_I2C_IsActiveSMBusFlag_SMBHOST
01355   * @param  I2Cx I2C Instance.
01356   * @retval State of bit (1 or 0).
01357   */
01358 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
01359 {
01360   return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
01361 }
01362
01363 /**
01364   * @brief  Indicate the status of SMBus Device default address reception (Slave mode).
01365   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01366   *         SMBus feature is supported by the I2Cx Instance.
01367   * @note   RESET: No SMBus Device default address
01368   *         SET: SMBus Device default address received.
01369   * @note   This status is cleared by hardware after a STOP condition or repeated START condition.
01370   * @rmtoll SR2          SMBDEFAULT    LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
01371   * @param  I2Cx I2C Instance.
01372   * @retval State of bit (1 or 0).
01373   */
01374 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
01375 {
01376   return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
01377 }
01378
01379 /**
01380   * @brief  Indicate the status of General call address reception (Slave mode).
01381   * @note   RESET: No Generall call address
01382   *         SET: General call address received.
01383   * @note   This status is cleared by hardware after a STOP condition or repeated START condition.
01384   * @rmtoll SR2          GENCALL       LL_I2C_IsActiveFlag_GENCALL
01385   * @param  I2Cx I2C Instance.
01386   * @retval State of bit (1 or 0).
01387   */
01388 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
01389 {
01390   return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
01391 }
01392
01393 /**
01394   * @brief  Indicate the status of Master/Slave flag.
01395   * @note   RESET: Slave Mode.
01396   *         SET: Master Mode.
01397   * @rmtoll SR2          MSL           LL_I2C_IsActiveFlag_MSL
01398   * @param  I2Cx I2C Instance.
01399   * @retval State of bit (1 or 0).
01400   */
01401 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
01402 {
01403   return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
01404 }
01405
01406 /**
01407   * @brief  Clear Address Matched flag.
01408   * @note   Clearing this flag is done by a read access to the I2Cx_SR1
01409   *         register followed by a read access to the I2Cx_SR2 register.
01410   * @rmtoll SR1          ADDR          LL_I2C_ClearFlag_ADDR
01411   * @param  I2Cx I2C Instance.
01412   * @retval None
01413   */
01414 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
01415 {
01416   __IO uint32_t tmpreg;
01417   tmpreg = I2Cx->SR1;
01418   (void) tmpreg;
01419   tmpreg = I2Cx->SR2;
01420   (void) tmpreg;
01421 }
01422
01423 /**
01424   * @brief  Clear Acknowledge failure flag.
01425   * @rmtoll SR1          AF            LL_I2C_ClearFlag_AF
01426   * @param  I2Cx I2C Instance.
01427   * @retval None
01428   */
01429 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
01430 {
01431   CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
01432 }
01433
01434 /**
01435   * @brief  Clear Stop detection flag.
01436   * @note   Clearing this flag is done by a read access to the I2Cx_SR1
01437   *         register followed by a write access to I2Cx_CR1 register.
01438   * @rmtoll SR1          STOPF         LL_I2C_ClearFlag_STOP\n
01439   *         CR1          PE            LL_I2C_ClearFlag_STOP
01440   * @param  I2Cx I2C Instance.
01441   * @retval None
01442   */
01443 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
01444 {
01445   __IO uint32_t tmpreg;
01446   tmpreg = I2Cx->SR1;
01447   (void) tmpreg;
01448   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
01449 }
01450
01451 /**
01452   * @brief  Clear Bus error flag.
01453   * @rmtoll SR1          BERR          LL_I2C_ClearFlag_BERR
01454   * @param  I2Cx I2C Instance.
01455   * @retval None
01456   */
01457 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
01458 {
01459   CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
01460 }
01461
01462 /**
01463   * @brief  Clear Arbitration lost flag.
01464   * @rmtoll SR1          ARLO          LL_I2C_ClearFlag_ARLO
01465   * @param  I2Cx I2C Instance.
01466   * @retval None
01467   */
01468 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
01469 {
01470   CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
01471 }
01472
01473 /**
01474   * @brief  Clear Overrun/Underrun flag.
01475   * @rmtoll SR1          OVR           LL_I2C_ClearFlag_OVR
01476   * @param  I2Cx I2C Instance.
01477   * @retval None
01478   */
01479 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
01480 {
01481   CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
01482 }
01483
01484 /**
01485   * @brief  Clear SMBus PEC error flag.
01486   * @rmtoll SR1          PECERR        LL_I2C_ClearSMBusFlag_PECERR
01487   * @param  I2Cx I2C Instance.
01488   * @retval None
01489   */
01490 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01491 {
01492   CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
01493 }
01494
01495 /**
01496   * @brief  Clear SMBus Timeout detection flag.
01497   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01498   *         SMBus feature is supported by the I2Cx Instance.
01499   * @rmtoll SR1          TIMEOUT       LL_I2C_ClearSMBusFlag_TIMEOUT
01500   * @param  I2Cx I2C Instance.
01501   * @retval None
01502   */
01503 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01504 {
01505   CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
01506 }
01507
01508 /**
01509   * @brief  Clear SMBus Alert flag.
01510   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01511   *         SMBus feature is supported by the I2Cx Instance.
01512   * @rmtoll SR1          SMBALERT      LL_I2C_ClearSMBusFlag_ALERT
01513   * @param  I2Cx I2C Instance.
01514   * @retval None
01515   */
01516 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01517 {
01518   CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
01519 }
01520
01521 /**
01522   * @}
01523   */
01524
01525 /** @defgroup I2C_LL_EF_Data_Management Data_Management
01526   * @{
01527   */
01528
01529 /**
01530   * @brief  Enable Reset of I2C peripheral.
01531   * @rmtoll CR1          SWRST         LL_I2C_EnableReset
01532   * @param  I2Cx I2C Instance.
01533   * @retval None
01534   */
01535 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
01536 {
01537   SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
01538 }
01539
01540 /**
01541   * @brief  Disable Reset of I2C peripheral.
01542   * @rmtoll CR1          SWRST         LL_I2C_DisableReset
01543   * @param  I2Cx I2C Instance.
01544   * @retval None
01545   */
01546 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
01547 {
01548   CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
01549 }
01550
01551 /**
01552   * @brief  Check if the I2C peripheral is under reset state or not.
01553   * @rmtoll CR1          SWRST         LL_I2C_IsResetEnabled
01554   * @param  I2Cx I2C Instance.
01555   * @retval State of bit (1 or 0).
01556   */
01557 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
01558 {
01559   return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
01560 }
01561
01562 /**
01563   * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
01564   * @note   Usage in Slave or Master mode.
01565   * @rmtoll CR1          ACK           LL_I2C_AcknowledgeNextData
01566   * @param  I2Cx I2C Instance.
01567   * @param  TypeAcknowledge This parameter can be one of the following values:
01568   *         @arg @ref LL_I2C_ACK
01569   *         @arg @ref LL_I2C_NACK
01570   * @retval None
01571   */
01572 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
01573 {
01574   MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
01575 }
01576
01577 /**
01578   * @brief  Generate a START or RESTART condition
01579   * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
01580   *         This action has no effect when RELOAD is set.
01581   * @rmtoll CR1          START         LL_I2C_GenerateStartCondition
01582   * @param  I2Cx I2C Instance.
01583   * @retval None
01584   */
01585 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
01586 {
01587   SET_BIT(I2Cx->CR1, I2C_CR1_START);
01588 }
01589
01590 /**
01591   * @brief  Generate a STOP condition after the current byte transfer (master mode).
01592   * @rmtoll CR1          STOP          LL_I2C_GenerateStopCondition
01593   * @param  I2Cx I2C Instance.
01594   * @retval None
01595   */
01596 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
01597 {
01598   SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
01599 }
01600
01601 /**
01602   * @brief  Enable bit POS (master/host mode).
01603   * @note   In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
01604   * @rmtoll CR1          POS           LL_I2C_EnableBitPOS
01605   * @param  I2Cx I2C Instance.
01606   * @retval None
01607   */
01608 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
01609 {
01610   SET_BIT(I2Cx->CR1, I2C_CR1_POS);
01611 }
01612
01613 /**
01614   * @brief  Disable bit POS (master/host mode).
01615   * @note   In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
01616   * @rmtoll CR1          POS           LL_I2C_DisableBitPOS
01617   * @param  I2Cx I2C Instance.
01618   * @retval None
01619   */
01620 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
01621 {
01622   CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
01623 }
01624
01625 /**
01626   * @brief  Check if bit POS  is enabled or disabled.
01627   * @rmtoll CR1          POS           LL_I2C_IsEnabledBitPOS
01628   * @param  I2Cx I2C Instance.
01629   * @retval State of bit (1 or 0).
01630   */
01631 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
01632 {
01633   return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
01634 }
01635
01636 /**
01637   * @brief  Indicate the value of transfer direction.
01638   * @note   RESET: Bus is in read transfer (peripheral point of view).
01639   *         SET: Bus is in write transfer (peripheral point of view).
01640   * @rmtoll SR2          TRA           LL_I2C_GetTransferDirection
01641   * @param  I2Cx I2C Instance.
01642   * @retval Returned value can be one of the following values:
01643   *         @arg @ref LL_I2C_DIRECTION_WRITE
01644   *         @arg @ref LL_I2C_DIRECTION_READ
01645   */
01646 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
01647 {
01648   return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
01649 }
01650
01651 /**
01652   * @brief  Enable DMA last transfer.
01653   * @note   This action mean that next DMA EOT is the last transfer.
01654   * @rmtoll CR2          LAST          LL_I2C_EnableLastDMA
01655   * @param  I2Cx I2C Instance.
01656   * @retval None
01657   */
01658 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
01659 {
01660   SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
01661 }
01662
01663 /**
01664   * @brief  Disable DMA last transfer.
01665   * @note   This action mean that next DMA EOT is not the last transfer.
01666   * @rmtoll CR2          LAST          LL_I2C_DisableLastDMA
01667   * @param  I2Cx I2C Instance.
01668   * @retval None
01669   */
01670 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
01671 {
01672   CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
01673 }
01674
01675 /**
01676   * @brief  Check if DMA last transfer is enabled or disabled.
01677   * @rmtoll CR2          LAST          LL_I2C_IsEnabledLastDMA
01678   * @param  I2Cx I2C Instance.
01679   * @retval State of bit (1 or 0).
01680   */
01681 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
01682 {
01683   return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
01684 }
01685
01686 /**
01687   * @brief  Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
01688   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01689   *         SMBus feature is supported by the I2Cx Instance.
01690   * @note   This feature is cleared by hardware when the PEC byte is transferred or compared,
01691   *         or by a START or STOP condition, it is also cleared by software.
01692   * @rmtoll CR1          PEC           LL_I2C_EnableSMBusPECCompare
01693   * @param  I2Cx I2C Instance.
01694   * @retval None
01695   */
01696 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
01697 {
01698   SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
01699 }
01700
01701 /**
01702   * @brief  Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
01703   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01704   *         SMBus feature is supported by the I2Cx Instance.
01705   * @rmtoll CR1          PEC           LL_I2C_DisableSMBusPECCompare
01706   * @param  I2Cx I2C Instance.
01707   * @retval None
01708   */
01709 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
01710 {
01711   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
01712 }
01713
01714 /**
01715   * @brief  Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
01716   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01717   *         SMBus feature is supported by the I2Cx Instance.
01718   * @rmtoll CR1          PEC           LL_I2C_IsEnabledSMBusPECCompare
01719   * @param  I2Cx I2C Instance.
01720   * @retval State of bit (1 or 0).
01721   */
01722 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
01723 {
01724   return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
01725 }
01726
01727 /**
01728   * @brief  Get the SMBus Packet Error byte calculated.
01729   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01730   *         SMBus feature is supported by the I2Cx Instance.
01731   * @rmtoll SR2          PEC           LL_I2C_GetSMBusPEC
01732   * @param  I2Cx I2C Instance.
01733   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
01734   */
01735 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
01736 {
01737   return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
01738 }
01739
01740 /**
01741   * @brief  Read Receive Data register.
01742   * @rmtoll DR           DR            LL_I2C_ReceiveData8
01743   * @param  I2Cx I2C Instance.
01744   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
01745   */
01746 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
01747 {
01748   return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
01749 }
01750
01751 /**
01752   * @brief  Write in Transmit Data Register .
01753   * @rmtoll DR           DR            LL_I2C_TransmitData8
01754   * @param  I2Cx I2C Instance.
01755   * @param  Data Value between Min_Data=0x0 and Max_Data=0xFF
01756   * @retval None
01757   */
01758 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
01759 {
01760   MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
01761 }
01762
01763 /**
01764   * @}
01765   */
01766
01767 #if defined(USE_FULL_LL_DRIVER)
01768 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
01769   * @{
01770   */
01771
01772 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
01773 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
01774 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
01775
01776
01777 /**
01778   * @}
01779   */
01780 #endif /* USE_FULL_LL_DRIVER */
01781
01782 /**
01783   * @}
01784   */
01785
01786 /**
01787   * @}
01788   */
01789
01790 #endif /* I2C1 || I2C2 */
01791
01792 /**
01793   * @}
01794   */
01795
01796 #ifdef __cplusplus
01797 }
01798 #endif
01799
01800 #endif /* __STM32F1xx_LL_I2C_H */
01801
01802 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_i2s.c Source File

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stm32f1xx_ll_i2s.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_spi.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   SPI LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_spi.h"
00041 #include "stm32f1xx_ll_bus.h"
00042 #include "stm32f1xx_ll_rcc.h"
00043
00044 #ifdef  USE_FULL_ASSERT
00045 #include "stm32_assert.h"
00046 #else
00047 #define assert_param(expr) ((void)0U)
00048 #endif
00049
00050 /** @addtogroup STM32F1xx_LL_Driver
00051   * @{
00052   */
00053
00054 /** @addtogroup I2S_LL
00055   * @{
00056   */
00057
00058 /* Private types -------------------------------------------------------------*/
00059 /* Private variables ---------------------------------------------------------*/
00060 /* Private constants ---------------------------------------------------------*/
00061 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
00062   * @{
00063   */
00064 /* I2S registers Masks */
00065 #define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
00066                                             SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
00067                                             SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
00068
00069 #define I2S_I2SPR_CLEAR_MASK               0x0002U
00070 /**
00071   * @}
00072   */
00073 /* Private macros ------------------------------------------------------------*/
00074 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
00075   * @{
00076   */
00077
00078 #define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)          \
00079                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
00080                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
00081                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
00082
00083 #define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
00084                                        || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
00085
00086 #define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)   \
00087                                        || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
00088                                        || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
00089                                        || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
00090                                        || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
00091
00092 #define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)  \
00093                                        || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
00094                                        || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
00095                                        || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
00096
00097 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
00098                                        || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
00099
00100 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)    \
00101                                        && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
00102                                        || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
00103
00104 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
00105
00106 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
00107                                            || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
00108 /**
00109   * @}
00110   */
00111
00112 /* Private function prototypes -----------------------------------------------*/
00113
00114 /* Exported functions --------------------------------------------------------*/
00115 /** @addtogroup I2S_LL_Exported_Functions
00116   * @{
00117   */
00118
00119 /** @addtogroup I2S_LL_EF_Init
00120   * @{
00121   */
00122
00123 /**
00124   * @brief  De-initialize the SPI/I2S registers to their default reset values.
00125   * @param  SPIx SPI Instance
00126   * @retval An ErrorStatus enumeration value:
00127   *          - SUCCESS: SPI registers are de-initialized
00128   *          - ERROR: SPI registers are not de-initialized
00129   */
00130 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
00131 {
00132   return LL_SPI_DeInit(SPIx);
00133 }
00134
00135 /**
00136   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
00137   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00138   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00139   * @param  SPIx SPI Instance
00140   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00141   * @retval An ErrorStatus enumeration value:
00142   *          - SUCCESS: SPI registers are Initialized
00143   *          - ERROR: SPI registers are not Initialized
00144   */
00145 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
00146 {
00147   uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
00148   uint32_t tmp = 0U;
00149   uint32_t sourceclock = 0U;
00150   ErrorStatus status = ERROR;
00151
00152   /* Check the I2S parameters */
00153   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
00154   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
00155   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
00156   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
00157   assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
00158   assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
00159   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
00160
00161   if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
00162   {
00163     /*---------------------------- SPIx I2SCFGR Configuration --------------------
00164      * Configure SPIx I2SCFGR with parameters:
00165      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
00166      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
00167      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
00168      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
00169      */
00170
00171     /* Write to SPIx I2SCFGR */
00172     MODIFY_REG(SPIx->I2SCFGR,
00173                I2S_I2SCFGR_CLEAR_MASK,
00174                I2S_InitStruct->Mode | I2S_InitStruct->Standard |
00175                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
00176                SPI_I2SCFGR_I2SMOD);
00177
00178     /*---------------------------- SPIx I2SPR Configuration ----------------------
00179      * Configure SPIx I2SPR with parameters:
00180      * - MCLKOutput:    SPI_I2SPR_MCKOE bit
00181      * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
00182      */
00183
00184     /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
00185      * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
00186      */
00187     if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
00188     {
00189       /* Check the frame length (For the Prescaler computing)
00190        * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
00191        */
00192       if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
00193       {
00194         /* Packet length is 32 bits */
00195         packetlength = 2U;
00196       }
00197
00198       /* If an external I2S clock has to be used, the specific define should be set
00199       in the project configuration or in the stm32f1xx_ll_rcc.h file */
00200       /* Get the I2S source clock value */
00201       sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
00202
00203       /* Compute the Real divider depending on the MCLK output state with a floating point */
00204       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
00205       {
00206         /* MCLK output is enabled */
00207         tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
00208       }
00209       else
00210       {
00211         /* MCLK output is disabled */
00212         tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
00213       }
00214
00215       /* Remove the floating point */
00216       tmp = tmp / 10U;
00217
00218       /* Check the parity of the divider */
00219       i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
00220
00221       /* Compute the i2sdiv prescaler */
00222       i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
00223
00224       /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
00225       i2sodd = (uint16_t)(i2sodd << 8U);
00226     }
00227
00228     /* Test if the divider is 1 or 0 or greater than 0xFF */
00229     if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
00230     {
00231       /* Set the default values */
00232       i2sdiv = 2U;
00233       i2sodd = 0U;
00234     }
00235
00236     /* Write to SPIx I2SPR register the computed value */
00237     WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
00238
00239     status = SUCCESS;
00240   }
00241   return status;
00242 }
00243
00244 /**
00245   * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
00246   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
00247   *         whose fields will be set to default values.
00248   * @retval None
00249   */
00250 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
00251 {
00252   /*--------------- Reset I2S init structure parameters values -----------------*/
00253   I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
00254   I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
00255   I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
00256   I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
00257   I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
00258   I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
00259 }
00260
00261 /**
00262   * @brief  Set linear and parity prescaler.
00263   * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
00264   *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
00265   * @param  SPIx SPI Instance
00266   * @param  PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
00267   * @param  PrescalerParity This parameter can be one of the following values:
00268   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
00269   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
00270   * @retval None
00271   */
00272 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
00273 {
00274   /* Check the I2S parameters */
00275   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
00276   assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
00277   assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
00278
00279   /* Write to SPIx I2SPR */
00280   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
00281 }
00282
00283 /**
00284   * @}
00285   */
00286
00287 /**
00288   * @}
00289   */
00290
00291 /**
00292   * @}
00293   */
00294
00295 /**
00296   * @}
00297   */
00298
00299 #endif /* USE_FULL_LL_DRIVER */
00300
00301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_i2s.h Source File

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stm32f1xx_ll_i2s.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_spi.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of SPI LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_SPI_H
00040 #define __STM32F1xx_LL_SPI_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 /** @defgroup I2S_LL I2S
00054   * @{
00055   */
00056
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private constants ---------------------------------------------------------*/
00059 /* Private macros ------------------------------------------------------------*/
00060
00061 /* Exported types ------------------------------------------------------------*/
00062 #if defined(USE_FULL_LL_DRIVER)
00063 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
00064   * @{
00065   */
00066
00067 /**
00068   * @brief  I2S Init structure definition
00069   */
00070
00071 typedef struct
00072 {
00073   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
00074                                          This parameter can be a value of @ref I2S_LL_EC_MODE
00075
00076                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
00077
00078   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
00079                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
00080
00081                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
00082
00083
00084   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
00085                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
00086
00087                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
00088
00089
00090   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
00091                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
00092
00093                                          This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
00094
00095
00096   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
00097                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
00098
00099                                          Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
00100                                          and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
00101
00102
00103   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
00104                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
00105
00106                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
00107
00108 } LL_I2S_InitTypeDef;
00109
00110 /**
00111   * @}
00112   */
00113 #endif /*USE_FULL_LL_DRIVER*/
00114
00115 /* Exported constants --------------------------------------------------------*/
00116 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
00117   * @{
00118   */
00119
00120 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
00121   * @brief    Flags defines which can be used with LL_I2S_ReadReg function
00122   * @{
00123   */
00124 #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
00125 #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
00126 #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
00127 #define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
00128 #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
00129 #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
00130 /**
00131   * @}
00132   */
00133
00134 /** @defgroup SPI_LL_EC_IT IT Defines
00135   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
00136   * @{
00137   */
00138 #define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
00139 #define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
00140 #define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
00141 /**
00142   * @}
00143   */
00144
00145 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
00146   * @{
00147   */
00148 #define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel lenght 16bit */
00149 #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel lenght 32bit */
00150 #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel lenght 32bit */
00151 #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel lenght 32bit */
00152 /**
00153   * @}
00154   */
00155
00156 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
00157   * @{
00158   */
00159 #define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
00160 #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
00161 /**
00162   * @}
00163   */
00164
00165 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
00166   * @{
00167   */
00168 #define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
00169 #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
00170 #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
00171 #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
00172 #define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
00173 /**
00174   * @}
00175   */
00176
00177 /** @defgroup I2S_LL_EC_MODE Operation Mode
00178   * @{
00179   */
00180 #define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
00181 #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
00182 #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
00183 #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
00184 /**
00185   * @}
00186   */
00187
00188 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
00189   * @{
00190   */
00191 #define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
00192 #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
00193 /**
00194   * @}
00195   */
00196
00197 #if defined(USE_FULL_LL_DRIVER)
00198
00199 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
00200   * @{
00201   */
00202 #define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
00203 #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
00204 /**
00205   * @}
00206   */
00207
00208 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
00209   * @{
00210   */
00211
00212 #define LL_I2S_AUDIOFREQ_192K              192000U      /*!< Audio Frequency configuration 192000 Hz       */
00213 #define LL_I2S_AUDIOFREQ_96K               96000U       /*!< Audio Frequency configuration  96000 Hz       */
00214 #define LL_I2S_AUDIOFREQ_48K               48000U       /*!< Audio Frequency configuration  48000 Hz       */
00215 #define LL_I2S_AUDIOFREQ_44K               44100U       /*!< Audio Frequency configuration  44100 Hz       */
00216 #define LL_I2S_AUDIOFREQ_32K               32000U       /*!< Audio Frequency configuration  32000 Hz       */
00217 #define LL_I2S_AUDIOFREQ_22K               22050U       /*!< Audio Frequency configuration  22050 Hz       */
00218 #define LL_I2S_AUDIOFREQ_16K               16000U       /*!< Audio Frequency configuration  16000 Hz       */
00219 #define LL_I2S_AUDIOFREQ_11K               11025U       /*!< Audio Frequency configuration  11025 Hz       */
00220 #define LL_I2S_AUDIOFREQ_8K                8000U        /*!< Audio Frequency configuration   8000 Hz       */
00221 #define LL_I2S_AUDIOFREQ_DEFAULT           2U           /*!< Audio Freq not specified. Register I2SDIV = 2 */
00222 /**
00223   * @}
00224   */
00225 #endif /* USE_FULL_LL_DRIVER */
00226
00227 /**
00228   * @}
00229   */
00230
00231 /* Exported macro ------------------------------------------------------------*/
00232 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
00233   * @{
00234   */
00235
00236 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
00237   * @{
00238   */
00239
00240 /**
00241   * @brief  Write a value in I2S register
00242   * @param  __INSTANCE__ I2S Instance
00243   * @param  __REG__ Register to be written
00244   * @param  __VALUE__ Value to be written in the register
00245   * @retval None
00246   */
00247 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00248
00249 /**
00250   * @brief  Read a value in I2S register
00251   * @param  __INSTANCE__ I2S Instance
00252   * @param  __REG__ Register to be read
00253   * @retval Register value
00254   */
00255 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00256 /**
00257   * @}
00258   */
00259
00260 /**
00261   * @}
00262   */
00263
00264
00265 /* Exported functions --------------------------------------------------------*/
00266
00267 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
00268   * @{
00269   */
00270
00271 /** @defgroup I2S_LL_EF_Configuration Configuration
00272   * @{
00273   */
00274
00275 /**
00276   * @brief  Select I2S mode and Enable I2S peripheral
00277   * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
00278   *         I2SCFGR      I2SE          LL_I2S_Enable
00279   * @param  SPIx SPI Instance
00280   * @retval None
00281   */
00282 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
00283 {
00284   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
00285 }
00286
00287 /**
00288   * @brief  Disable I2S peripheral
00289   * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
00290   * @param  SPIx SPI Instance
00291   * @retval None
00292   */
00293 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
00294 {
00295   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
00296 }
00297
00298 /**
00299   * @brief  Check if I2S peripheral is enabled
00300   * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
00301   * @param  SPIx SPI Instance
00302   * @retval State of bit (1 or 0).
00303   */
00304 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
00305 {
00306   return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
00307 }
00308
00309 /**
00310   * @brief  Set I2S data frame length
00311   * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
00312   *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
00313   * @param  SPIx SPI Instance
00314   * @param  DataFormat This parameter can be one of the following values:
00315   *         @arg @ref LL_I2S_DATAFORMAT_16B
00316   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
00317   *         @arg @ref LL_I2S_DATAFORMAT_24B
00318   *         @arg @ref LL_I2S_DATAFORMAT_32B
00319   * @retval None
00320   */
00321 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
00322 {
00323   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
00324 }
00325
00326 /**
00327   * @brief  Get I2S data frame length
00328   * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
00329   *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
00330   * @param  SPIx SPI Instance
00331   * @retval Returned value can be one of the following values:
00332   *         @arg @ref LL_I2S_DATAFORMAT_16B
00333   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
00334   *         @arg @ref LL_I2S_DATAFORMAT_24B
00335   *         @arg @ref LL_I2S_DATAFORMAT_32B
00336   */
00337 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
00338 {
00339   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
00340 }
00341
00342 /**
00343   * @brief  Set I2S clock polarity
00344   * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
00345   * @param  SPIx SPI Instance
00346   * @param  ClockPolarity This parameter can be one of the following values:
00347   *         @arg @ref LL_I2S_POLARITY_LOW
00348   *         @arg @ref LL_I2S_POLARITY_HIGH
00349   * @retval None
00350   */
00351 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
00352 {
00353   SET_BIT(SPIx->I2SCFGR, ClockPolarity);
00354 }
00355
00356 /**
00357   * @brief  Get I2S clock polarity
00358   * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
00359   * @param  SPIx SPI Instance
00360   * @retval Returned value can be one of the following values:
00361   *         @arg @ref LL_I2S_POLARITY_LOW
00362   *         @arg @ref LL_I2S_POLARITY_HIGH
00363   */
00364 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
00365 {
00366   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
00367 }
00368
00369 /**
00370   * @brief  Set I2S standard protocol
00371   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
00372   *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
00373   * @param  SPIx SPI Instance
00374   * @param  Standard This parameter can be one of the following values:
00375   *         @arg @ref LL_I2S_STANDARD_PHILIPS
00376   *         @arg @ref LL_I2S_STANDARD_MSB
00377   *         @arg @ref LL_I2S_STANDARD_LSB
00378   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
00379   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
00380   * @retval None
00381   */
00382 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
00383 {
00384   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
00385 }
00386
00387 /**
00388   * @brief  Get I2S standard protocol
00389   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
00390   *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
00391   * @param  SPIx SPI Instance
00392   * @retval Returned value can be one of the following values:
00393   *         @arg @ref LL_I2S_STANDARD_PHILIPS
00394   *         @arg @ref LL_I2S_STANDARD_MSB
00395   *         @arg @ref LL_I2S_STANDARD_LSB
00396   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
00397   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
00398   */
00399 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
00400 {
00401   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
00402 }
00403
00404 /**
00405   * @brief  Set I2S transfer mode
00406   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
00407   * @param  SPIx SPI Instance
00408   * @param  Mode This parameter can be one of the following values:
00409   *         @arg @ref LL_I2S_MODE_SLAVE_TX
00410   *         @arg @ref LL_I2S_MODE_SLAVE_RX
00411   *         @arg @ref LL_I2S_MODE_MASTER_TX
00412   *         @arg @ref LL_I2S_MODE_MASTER_RX
00413   * @retval None
00414   */
00415 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
00416 {
00417   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
00418 }
00419
00420 /**
00421   * @brief  Get I2S transfer mode
00422   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
00423   * @param  SPIx SPI Instance
00424   * @retval Returned value can be one of the following values:
00425   *         @arg @ref LL_I2S_MODE_SLAVE_TX
00426   *         @arg @ref LL_I2S_MODE_SLAVE_RX
00427   *         @arg @ref LL_I2S_MODE_MASTER_TX
00428   *         @arg @ref LL_I2S_MODE_MASTER_RX
00429   */
00430 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
00431 {
00432   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
00433 }
00434
00435 /**
00436   * @brief  Set I2S linear prescaler
00437   * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
00438   * @param  SPIx SPI Instance
00439   * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
00440   * @retval None
00441   */
00442 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
00443 {
00444   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
00445 }
00446
00447 /**
00448   * @brief  Get I2S linear prescaler
00449   * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
00450   * @param  SPIx SPI Instance
00451   * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
00452   */
00453 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
00454 {
00455   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
00456 }
00457
00458 /**
00459   * @brief  Set I2S parity prescaler
00460   * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
00461   * @param  SPIx SPI Instance
00462   * @param  PrescalerParity This parameter can be one of the following values:
00463   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
00464   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
00465   * @retval None
00466   */
00467 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
00468 {
00469   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
00470 }
00471
00472 /**
00473   * @brief  Get I2S parity prescaler
00474   * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
00475   * @param  SPIx SPI Instance
00476   * @retval Returned value can be one of the following values:
00477   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
00478   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
00479   */
00480 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
00481 {
00482   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
00483 }
00484
00485 /**
00486   * @brief  Enable the master clock ouput (Pin MCK)
00487   * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
00488   * @param  SPIx SPI Instance
00489   * @retval None
00490   */
00491 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
00492 {
00493   SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
00494 }
00495
00496 /**
00497   * @brief  Disable the master clock ouput (Pin MCK)
00498   * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
00499   * @param  SPIx SPI Instance
00500   * @retval None
00501   */
00502 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
00503 {
00504   CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
00505 }
00506
00507 /**
00508   * @brief  Check if the master clock ouput (Pin MCK) is enabled
00509   * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
00510   * @param  SPIx SPI Instance
00511   * @retval State of bit (1 or 0).
00512   */
00513 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
00514 {
00515   return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
00516 }
00517
00518 /**
00519   * @}
00520   */
00521
00522 /** @defgroup I2S_LL_EF_FLAG FLAG Management
00523   * @{
00524   */
00525
00526 /**
00527   * @brief  Check if Rx buffer is not empty
00528   * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
00529   * @param  SPIx SPI Instance
00530   * @retval State of bit (1 or 0).
00531   */
00532 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
00533 {
00534   return LL_SPI_IsActiveFlag_RXNE(SPIx);
00535 }
00536
00537 /**
00538   * @brief  Check if Tx buffer is empty
00539   * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
00540   * @param  SPIx SPI Instance
00541   * @retval State of bit (1 or 0).
00542   */
00543 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
00544 {
00545   return LL_SPI_IsActiveFlag_TXE(SPIx);
00546 }
00547
00548 /**
00549   * @brief  Get busy flag
00550   * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
00551   * @param  SPIx SPI Instance
00552   * @retval State of bit (1 or 0).
00553   */
00554 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
00555 {
00556   return LL_SPI_IsActiveFlag_BSY(SPIx);
00557 }
00558
00559 /**
00560   * @brief  Get overrun error flag
00561   * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
00562   * @param  SPIx SPI Instance
00563   * @retval State of bit (1 or 0).
00564   */
00565 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
00566 {
00567   return LL_SPI_IsActiveFlag_OVR(SPIx);
00568 }
00569
00570 /**
00571   * @brief  Get underrun error flag
00572   * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
00573   * @param  SPIx SPI Instance
00574   * @retval State of bit (1 or 0).
00575   */
00576 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
00577 {
00578   return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
00579 }
00580
00581 /**
00582   * @brief  Get frame format error flag
00583   * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
00584   * @param  SPIx SPI Instance
00585   * @retval State of bit (1 or 0).
00586   */
00587 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
00588 {
00589   return LL_SPI_IsActiveFlag_FRE(SPIx);
00590 }
00591
00592 /**
00593   * @brief  Get channel side flag.
00594   * @note   0: Channel Left has to be transmitted or has been received\n
00595   *         1: Channel Right has to be transmitted or has been received\n
00596   *         It has no significance in PCM mode.
00597   * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
00598   * @param  SPIx SPI Instance
00599   * @retval State of bit (1 or 0).
00600   */
00601 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
00602 {
00603   return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
00604 }
00605
00606 /**
00607   * @brief  Clear overrun error flag
00608   * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
00609   * @param  SPIx SPI Instance
00610   * @retval None
00611   */
00612 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
00613 {
00614   LL_SPI_ClearFlag_OVR(SPIx);
00615 }
00616
00617 /**
00618   * @brief  Clear underrun error flag
00619   * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
00620   * @param  SPIx SPI Instance
00621   * @retval None
00622   */
00623 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
00624 {
00625   __IO uint32_t tmpreg;
00626   tmpreg = SPIx->SR;
00627   (void)tmpreg;
00628 }
00629
00630 /**
00631   * @brief  Clear frame format error flag
00632   * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
00633   * @param  SPIx SPI Instance
00634   * @retval None
00635   */
00636 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
00637 {
00638   LL_SPI_ClearFlag_FRE(SPIx);
00639 }
00640
00641 /**
00642   * @}
00643   */
00644
00645 /** @defgroup I2S_LL_EF_IT Interrupt Management
00646   * @{
00647   */
00648
00649 /**
00650   * @brief  Enable error IT
00651   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
00652   * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
00653   * @param  SPIx SPI Instance
00654   * @retval None
00655   */
00656 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
00657 {
00658   LL_SPI_EnableIT_ERR(SPIx);
00659 }
00660
00661 /**
00662   * @brief  Enable Rx buffer not empty IT
00663   * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
00664   * @param  SPIx SPI Instance
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
00668 {
00669   LL_SPI_EnableIT_RXNE(SPIx);
00670 }
00671
00672 /**
00673   * @brief  Enable Tx buffer empty IT
00674   * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
00675   * @param  SPIx SPI Instance
00676   * @retval None
00677   */
00678 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
00679 {
00680   LL_SPI_EnableIT_TXE(SPIx);
00681 }
00682
00683 /**
00684   * @brief  Disable error IT
00685   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
00686   * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
00687   * @param  SPIx SPI Instance
00688   * @retval None
00689   */
00690 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
00691 {
00692   LL_SPI_DisableIT_ERR(SPIx);
00693 }
00694
00695 /**
00696   * @brief  Disable Rx buffer not empty IT
00697   * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
00698   * @param  SPIx SPI Instance
00699   * @retval None
00700   */
00701 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
00702 {
00703   LL_SPI_DisableIT_RXNE(SPIx);
00704 }
00705
00706 /**
00707   * @brief  Disable Tx buffer empty IT
00708   * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
00709   * @param  SPIx SPI Instance
00710   * @retval None
00711   */
00712 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
00713 {
00714   LL_SPI_DisableIT_TXE(SPIx);
00715 }
00716
00717 /**
00718   * @brief  Check if ERR IT is enabled
00719   * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
00720   * @param  SPIx SPI Instance
00721   * @retval State of bit (1 or 0).
00722   */
00723 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
00724 {
00725   return LL_SPI_IsEnabledIT_ERR(SPIx);
00726 }
00727
00728 /**
00729   * @brief  Check if RXNE IT is enabled
00730   * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
00731   * @param  SPIx SPI Instance
00732   * @retval State of bit (1 or 0).
00733   */
00734 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
00735 {
00736   return LL_SPI_IsEnabledIT_RXNE(SPIx);
00737 }
00738
00739 /**
00740   * @brief  Check if TXE IT is enabled
00741   * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
00742   * @param  SPIx SPI Instance
00743   * @retval State of bit (1 or 0).
00744   */
00745 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
00746 {
00747   return LL_SPI_IsEnabledIT_TXE(SPIx);
00748 }
00749
00750 /**
00751   * @}
00752   */
00753
00754 /** @defgroup I2S_LL_EF_DMA DMA Management
00755   * @{
00756   */
00757
00758 /**
00759   * @brief  Enable DMA Rx
00760   * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
00761   * @param  SPIx SPI Instance
00762   * @retval None
00763   */
00764 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
00765 {
00766   LL_SPI_EnableDMAReq_RX(SPIx);
00767 }
00768
00769 /**
00770   * @brief  Disable DMA Rx
00771   * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
00772   * @param  SPIx SPI Instance
00773   * @retval None
00774   */
00775 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
00776 {
00777   LL_SPI_DisableDMAReq_RX(SPIx);
00778 }
00779
00780 /**
00781   * @brief  Check if DMA Rx is enabled
00782   * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
00783   * @param  SPIx SPI Instance
00784   * @retval State of bit (1 or 0).
00785   */
00786 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
00787 {
00788   return LL_SPI_IsEnabledDMAReq_RX(SPIx);
00789 }
00790
00791 /**
00792   * @brief  Enable DMA Tx
00793   * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
00794   * @param  SPIx SPI Instance
00795   * @retval None
00796   */
00797 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
00798 {
00799   LL_SPI_EnableDMAReq_TX(SPIx);
00800 }
00801
00802 /**
00803   * @brief  Disable DMA Tx
00804   * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
00805   * @param  SPIx SPI Instance
00806   * @retval None
00807   */
00808 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
00809 {
00810   LL_SPI_DisableDMAReq_TX(SPIx);
00811 }
00812
00813 /**
00814   * @brief  Check if DMA Tx is enabled
00815   * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
00816   * @param  SPIx SPI Instance
00817   * @retval State of bit (1 or 0).
00818   */
00819 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
00820 {
00821   return LL_SPI_IsEnabledDMAReq_TX(SPIx);
00822 }
00823
00824 /**
00825   * @}
00826   */
00827
00828 /** @defgroup I2S_LL_EF_DATA DATA Management
00829   * @{
00830   */
00831
00832 /**
00833   * @brief  Read 16-Bits in data register
00834   * @rmtoll DR           DR            LL_I2S_ReceiveData16
00835   * @param  SPIx SPI Instance
00836   * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
00837   */
00838 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
00839 {
00840   return LL_SPI_ReceiveData16(SPIx);
00841 }
00842
00843 /**
00844   * @brief  Write 16-Bits in data register
00845   * @rmtoll DR           DR            LL_I2S_TransmitData16
00846   * @param  SPIx SPI Instance
00847   * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
00848   * @retval None
00849   */
00850 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
00851 {
00852   LL_SPI_TransmitData16(SPIx, TxData);
00853 }
00854
00855 /**
00856   * @}
00857   */
00858
00859 #if defined(USE_FULL_LL_DRIVER)
00860 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
00861   * @{
00862   */
00863
00864 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
00865 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
00866 void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
00867 void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
00868
00869 /**
00870   * @}
00871   */
00872 #endif /* USE_FULL_LL_DRIVER */
00873
00874 /**
00875   * @}
00876   */
00877
00878 /**
00879   * @}
00880   */
00881
00882 /**
00883   * @}
00884   */
00885
00886 #ifdef __cplusplus
00887 }
00888 #endif
00889
00890 #endif /* __STM32F1xx_LL_SPI_H */
00891
00892 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_iwdg.h Source File

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  • Inc
stm32f1xx_ll_iwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_iwdg.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of IWDG LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_IWDG_H
00040 #define __STM32F1xx_LL_IWDG_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(IWDG)
00054
00055 /** @defgroup IWDG_LL IWDG
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
00064   * @{
00065   */
00066
00067 #define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
00068 #define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
00069 #define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
00070 #define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
00071
00072 /**
00073   * @}
00074   */
00075
00076 /* Private macros ------------------------------------------------------------*/
00077
00078 /* Exported types ------------------------------------------------------------*/
00079 /* Exported constants --------------------------------------------------------*/
00080 /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
00081   * @{
00082   */
00083
00084 /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
00085   * @brief    Flags defines which can be used with LL_IWDG_ReadReg function
00086   * @{
00087   */
00088 #define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */
00089 #define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */
00090
00091 /**
00092   * @}
00093   */
00094
00095 /** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
00096   * @{
00097   */
00098 #define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
00099 #define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
00100 #define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
00101 #define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */
00102 #define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */
00103 #define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */
00104 #define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */
00105 /**
00106   * @}
00107   */
00108
00109 /**
00110   * @}
00111   */
00112
00113 /* Exported macro ------------------------------------------------------------*/
00114 /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
00115   * @{
00116   */
00117
00118 /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
00119   * @{
00120   */
00121
00122 /**
00123   * @brief  Write a value in IWDG register
00124   * @param  __INSTANCE__ IWDG Instance
00125   * @param  __REG__ Register to be written
00126   * @param  __VALUE__ Value to be written in the register
00127   * @retval None
00128   */
00129 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00130
00131 /**
00132   * @brief  Read a value in IWDG register
00133   * @param  __INSTANCE__ IWDG Instance
00134   * @param  __REG__ Register to be read
00135   * @retval Register value
00136   */
00137 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00138 /**
00139   * @}
00140   */
00141
00142 /**
00143   * @}
00144   */
00145
00146
00147 /* Exported functions --------------------------------------------------------*/
00148 /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
00149   * @{
00150   */
00151 /** @defgroup IWDG_LL_EF_Configuration Configuration
00152   * @{
00153   */
00154
00155 /**
00156   * @brief  Start the Independent Watchdog
00157   * @note   Except if the hardware watchdog option is selected
00158   * @rmtoll KR           KEY           LL_IWDG_Enable
00159   * @param  IWDGx IWDG Instance
00160   * @retval None
00161   */
00162 __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
00163 {
00164   WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
00165 }
00166
00167 /**
00168   * @brief  Reloads IWDG counter with value defined in the reload register
00169   * @rmtoll KR           KEY           LL_IWDG_ReloadCounter
00170   * @param  IWDGx IWDG Instance
00171   * @retval None
00172   */
00173 __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
00174 {
00175   WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
00176 }
00177
00178 /**
00179   * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00180   * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess
00181   * @param  IWDGx IWDG Instance
00182   * @retval None
00183   */
00184 __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
00185 {
00186   WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
00187 }
00188
00189 /**
00190   * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
00191   * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess
00192   * @param  IWDGx IWDG Instance
00193   * @retval None
00194   */
00195 __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
00196 {
00197   WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
00198 }
00199
00200 /**
00201   * @brief  Select the prescaler of the IWDG
00202   * @rmtoll PR           PR            LL_IWDG_SetPrescaler
00203   * @param  IWDGx IWDG Instance
00204   * @param  Prescaler This parameter can be one of the following values:
00205   *         @arg @ref LL_IWDG_PRESCALER_4
00206   *         @arg @ref LL_IWDG_PRESCALER_8
00207   *         @arg @ref LL_IWDG_PRESCALER_16
00208   *         @arg @ref LL_IWDG_PRESCALER_32
00209   *         @arg @ref LL_IWDG_PRESCALER_64
00210   *         @arg @ref LL_IWDG_PRESCALER_128
00211   *         @arg @ref LL_IWDG_PRESCALER_256
00212   * @retval None
00213   */
00214 __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
00215 {
00216   WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
00217 }
00218
00219 /**
00220   * @brief  Get the selected prescaler of the IWDG
00221   * @rmtoll PR           PR            LL_IWDG_GetPrescaler
00222   * @param  IWDGx IWDG Instance
00223   * @retval Returned value can be one of the following values:
00224   *         @arg @ref LL_IWDG_PRESCALER_4
00225   *         @arg @ref LL_IWDG_PRESCALER_8
00226   *         @arg @ref LL_IWDG_PRESCALER_16
00227   *         @arg @ref LL_IWDG_PRESCALER_32
00228   *         @arg @ref LL_IWDG_PRESCALER_64
00229   *         @arg @ref LL_IWDG_PRESCALER_128
00230   *         @arg @ref LL_IWDG_PRESCALER_256
00231   */
00232 __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
00233 {
00234   return (uint32_t)(READ_REG(IWDGx->PR));
00235 }
00236
00237 /**
00238   * @brief  Specify the IWDG down-counter reload value
00239   * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter
00240   * @param  IWDGx IWDG Instance
00241   * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF
00242   * @retval None
00243   */
00244 __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
00245 {
00246   WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
00247 }
00248
00249 /**
00250   * @brief  Get the specified IWDG down-counter reload value
00251   * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter
00252   * @param  IWDGx IWDG Instance
00253   * @retval Value between Min_Data=0 and Max_Data=0x0FFF
00254   */
00255 __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
00256 {
00257   return (uint32_t)(READ_REG(IWDGx->RLR));
00258 }
00259
00260
00261 /**
00262   * @}
00263   */
00264
00265 /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
00266   * @{
00267   */
00268
00269 /**
00270   * @brief  Check if flag Prescaler Value Update is set or not
00271   * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU
00272   * @param  IWDGx IWDG Instance
00273   * @retval State of bit (1 or 0).
00274   */
00275 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
00276 {
00277   return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
00278 }
00279
00280 /**
00281   * @brief  Check if flag Reload Value Update is set or not
00282   * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU
00283   * @param  IWDGx IWDG Instance
00284   * @retval State of bit (1 or 0).
00285   */
00286 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
00287 {
00288   return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
00289 }
00290
00291
00292 /**
00293   * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not
00294   * @rmtoll SR           PVU           LL_IWDG_IsReady\n
00295   *         SR           RVU           LL_IWDG_IsReady
00296   * @param  IWDGx IWDG Instance
00297   * @retval State of bits (1 or 0).
00298   */
00299 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
00300 {
00301   return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U);
00302 }
00303
00304 /**
00305   * @}
00306   */
00307
00308
00309 /**
00310   * @}
00311   */
00312
00313 /**
00314   * @}
00315   */
00316
00317 #endif /* IWDG) */
00318
00319 /**
00320   * @}
00321   */
00322
00323 #ifdef __cplusplus
00324 }
00325 #endif
00326
00327 #endif /* __STM32F1xx_LL_IWDG_H */
00328
00329 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_pwr.c Source File

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  • Src
stm32f1xx_ll_pwr.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_pwr.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   PWR LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_pwr.h"
00041 #include "stm32f1xx_ll_bus.h"
00042
00043 /** @addtogroup STM32F1xx_LL_Driver
00044   * @{
00045   */
00046
00047 #if defined(PWR)
00048
00049 /** @defgroup PWR_LL PWR
00050   * @{
00051   */
00052
00053 /* Private types -------------------------------------------------------------*/
00054 /* Private variables ---------------------------------------------------------*/
00055 /* Private constants ---------------------------------------------------------*/
00056 /* Private macros ------------------------------------------------------------*/
00057 /* Private function prototypes -----------------------------------------------*/
00058
00059 /* Exported functions --------------------------------------------------------*/
00060 /** @addtogroup PWR_LL_Exported_Functions
00061   * @{
00062   */
00063
00064 /** @addtogroup PWR_LL_EF_Init
00065   * @{
00066   */
00067
00068 /**
00069   * @brief  De-initialize the PWR registers to their default reset values.
00070   * @retval An ErrorStatus enumeration value:
00071   *          - SUCCESS: PWR registers are de-initialized
00072   *          - ERROR: not applicable
00073   */
00074 ErrorStatus LL_PWR_DeInit(void)
00075 {
00076   /* Force reset of PWR clock */
00077   LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
00078
00079   /* Release reset of PWR clock */
00080   LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
00081
00082   return SUCCESS;
00083 }
00084
00085 /**
00086   * @}
00087   */
00088
00089 /**
00090   * @}
00091   */
00092
00093 /**
00094   * @}
00095   */
00096 #endif /* defined(PWR) */
00097 /**
00098   * @}
00099   */
00100
00101 #endif /* USE_FULL_LL_DRIVER */
00102
00103 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_pwr.h Source File

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  • Drivers
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  • Inc
stm32f1xx_ll_pwr.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_pwr.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of PWR LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_PWR_H
00040 #define __STM32F1xx_LL_PWR_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(PWR)
00054
00055 /** @defgroup PWR_LL PWR
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 /* Exported types ------------------------------------------------------------*/
00064 /* Exported constants --------------------------------------------------------*/
00065 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
00066   * @{
00067   */
00068
00069 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
00070   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
00071   * @{
00072   */
00073 #define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */
00074 #define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */
00075 /**
00076   * @}
00077   */
00078
00079 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
00080   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
00081   * @{
00082   */
00083 #define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
00084 #define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
00085 #define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
00086 #define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP           /*!< Enable WKUP pin 1 */
00087 /**
00088   * @}
00089   */
00090
00091
00092 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
00093   * @{
00094   */
00095 #define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
00096 #define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
00097 #define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
00098 /**
00099   * @}
00100   */
00101
00102 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
00103  * @{
00104  */
00105 #define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
00106 #define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
00107 /**
00108   * @}
00109   */
00110
00111 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
00112   * @{
00113   */
00114 #define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 2.2 V */
00115 #define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.3 V */
00116 #define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.4 V */
00117 #define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */
00118 #define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.6 V */
00119 #define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.7 V */
00120 #define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 2.8 V */
00121 #define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< Voltage threshold detected by PVD 2.9 V */
00122 /**
00123   * @}
00124   */
00125 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
00126   * @{
00127   */
00128 #define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP)         /*!< WKUP pin 1 : PA0 */
00129 /**
00130   * @}
00131   */
00132
00133 /**
00134   * @}
00135   */
00136
00137
00138 /* Exported macro ------------------------------------------------------------*/
00139 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
00140   * @{
00141   */
00142
00143 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
00144   * @{
00145   */
00146
00147 /**
00148   * @brief  Write a value in PWR register
00149   * @param  __REG__ Register to be written
00150   * @param  __VALUE__ Value to be written in the register
00151   * @retval None
00152   */
00153 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
00154
00155 /**
00156   * @brief  Read a value in PWR register
00157   * @param  __REG__ Register to be read
00158   * @retval Register value
00159   */
00160 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
00161 /**
00162   * @}
00163   */
00164
00165 /**
00166   * @}
00167   */
00168
00169 /* Exported functions --------------------------------------------------------*/
00170 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
00171   * @{
00172   */
00173
00174 /** @defgroup PWR_LL_EF_Configuration Configuration
00175   * @{
00176   */
00177
00178 /**
00179   * @brief  Enable access to the backup domain
00180   * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
00181   * @retval None
00182   */
00183 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
00184 {
00185   SET_BIT(PWR->CR, PWR_CR_DBP);
00186 }
00187
00188 /**
00189   * @brief  Disable access to the backup domain
00190   * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess
00191   * @retval None
00192   */
00193 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
00194 {
00195   CLEAR_BIT(PWR->CR, PWR_CR_DBP);
00196 }
00197
00198 /**
00199   * @brief  Check if the backup domain is enabled
00200   * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess
00201   * @retval State of bit (1 or 0).
00202   */
00203 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
00204 {
00205   return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
00206 }
00207
00208 /**
00209   * @brief  Set voltage Regulator mode during deep sleep mode
00210   * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
00211   * @param  RegulMode This parameter can be one of the following values:
00212   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
00213   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
00214   * @retval None
00215   */
00216 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
00217 {
00218   MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
00219 }
00220
00221 /**
00222   * @brief  Get voltage Regulator mode during deep sleep mode
00223   * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
00224   * @retval Returned value can be one of the following values:
00225   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
00226   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
00227   */
00228 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
00229 {
00230   return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
00231 }
00232
00233 /**
00234   * @brief  Set Power Down mode when CPU enters deepsleep
00235   * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\n
00236   * @rmtoll CR    LPDS         LL_PWR_SetPowerMode
00237   * @param  PDMode This parameter can be one of the following values:
00238   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
00239   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
00240   *         @arg @ref LL_PWR_MODE_STANDBY
00241   * @retval None
00242   */
00243 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
00244 {
00245   MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
00246 }
00247
00248 /**
00249   * @brief  Get Power Down mode when CPU enters deepsleep
00250   * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\n
00251   * @rmtoll CR    LPDS         LL_PWR_GetPowerMode
00252   * @retval Returned value can be one of the following values:
00253   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
00254   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
00255   *         @arg @ref LL_PWR_MODE_STANDBY
00256   */
00257 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
00258 {
00259   return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
00260 }
00261
00262 /**
00263   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
00264   * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
00265   * @param  PVDLevel This parameter can be one of the following values:
00266   *         @arg @ref LL_PWR_PVDLEVEL_0
00267   *         @arg @ref LL_PWR_PVDLEVEL_1
00268   *         @arg @ref LL_PWR_PVDLEVEL_2
00269   *         @arg @ref LL_PWR_PVDLEVEL_3
00270   *         @arg @ref LL_PWR_PVDLEVEL_4
00271   *         @arg @ref LL_PWR_PVDLEVEL_5
00272   *         @arg @ref LL_PWR_PVDLEVEL_6
00273   *         @arg @ref LL_PWR_PVDLEVEL_7
00274   * @retval None
00275   */
00276 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
00277 {
00278   MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
00279 }
00280
00281 /**
00282   * @brief  Get the voltage threshold detection
00283   * @rmtoll CR    PLS       LL_PWR_GetPVDLevel
00284   * @retval Returned value can be one of the following values:
00285   *         @arg @ref LL_PWR_PVDLEVEL_0
00286   *         @arg @ref LL_PWR_PVDLEVEL_1
00287   *         @arg @ref LL_PWR_PVDLEVEL_2
00288   *         @arg @ref LL_PWR_PVDLEVEL_3
00289   *         @arg @ref LL_PWR_PVDLEVEL_4
00290   *         @arg @ref LL_PWR_PVDLEVEL_5
00291   *         @arg @ref LL_PWR_PVDLEVEL_6
00292   *         @arg @ref LL_PWR_PVDLEVEL_7
00293   */
00294 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
00295 {
00296   return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
00297 }
00298
00299 /**
00300   * @brief  Enable Power Voltage Detector
00301   * @rmtoll CR    PVDE       LL_PWR_EnablePVD
00302   * @retval None
00303   */
00304 __STATIC_INLINE void LL_PWR_EnablePVD(void)
00305 {
00306   SET_BIT(PWR->CR, PWR_CR_PVDE);
00307 }
00308
00309 /**
00310   * @brief  Disable Power Voltage Detector
00311   * @rmtoll CR    PVDE       LL_PWR_DisablePVD
00312   * @retval None
00313   */
00314 __STATIC_INLINE void LL_PWR_DisablePVD(void)
00315 {
00316   CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
00317 }
00318
00319 /**
00320   * @brief  Check if Power Voltage Detector is enabled
00321   * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD
00322   * @retval State of bit (1 or 0).
00323   */
00324 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
00325 {
00326   return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
00327 }
00328
00329 /**
00330   * @brief  Enable the WakeUp PINx functionality
00331   * @rmtoll CSR   EWUP       LL_PWR_EnableWakeUpPin
00332   * @param  WakeUpPin This parameter can be one of the following values:
00333   *         @arg @ref LL_PWR_WAKEUP_PIN1
00334   * @retval None
00335   */
00336 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
00337 {
00338   SET_BIT(PWR->CSR, WakeUpPin);
00339 }
00340
00341 /**
00342   * @brief  Disable the WakeUp PINx functionality
00343   * @rmtoll CSR   EWUP       LL_PWR_DisableWakeUpPin
00344   * @param  WakeUpPin This parameter can be one of the following values:
00345   *         @arg @ref LL_PWR_WAKEUP_PIN1
00346   * @retval None
00347   */
00348 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
00349 {
00350   CLEAR_BIT(PWR->CSR, WakeUpPin);
00351 }
00352
00353 /**
00354   * @brief  Check if the WakeUp PINx functionality is enabled
00355   * @rmtoll CSR   EWUP       LL_PWR_IsEnabledWakeUpPin
00356   * @param  WakeUpPin This parameter can be one of the following values:
00357   *         @arg @ref LL_PWR_WAKEUP_PIN1
00358   * @retval State of bit (1 or 0).
00359   */
00360 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
00361 {
00362   return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
00363 }
00364
00365
00366 /**
00367   * @}
00368   */
00369
00370 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
00371   * @{
00372   */
00373
00374 /**
00375   * @brief  Get Wake-up Flag
00376   * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU
00377   * @retval State of bit (1 or 0).
00378   */
00379 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
00380 {
00381   return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
00382 }
00383
00384 /**
00385   * @brief  Get Standby Flag
00386   * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB
00387   * @retval State of bit (1 or 0).
00388   */
00389 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
00390 {
00391   return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
00392 }
00393
00394 /**
00395   * @brief  Indicate whether VDD voltage is below the selected PVD threshold
00396   * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
00397   * @retval State of bit (1 or 0).
00398   */
00399 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
00400 {
00401   return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
00402 }
00403
00404 /**
00405   * @brief  Clear Standby Flag
00406   * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
00407   * @retval None
00408   */
00409 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
00410 {
00411   SET_BIT(PWR->CR, PWR_CR_CSBF);
00412 }
00413
00414 /**
00415   * @brief  Clear Wake-up Flags
00416   * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU
00417   * @retval None
00418   */
00419 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
00420 {
00421   SET_BIT(PWR->CR, PWR_CR_CWUF);
00422 }
00423
00424 /**
00425   * @}
00426   */
00427
00428 #if defined(USE_FULL_LL_DRIVER)
00429 /** @defgroup PWR_LL_EF_Init De-initialization function
00430   * @{
00431   */
00432 ErrorStatus LL_PWR_DeInit(void);
00433 /**
00434   * @}
00435   */
00436 #endif /* USE_FULL_LL_DRIVER */
00437
00438 /**
00439   * @}
00440   */
00441
00442 /**
00443   * @}
00444   */
00445
00446 #endif /* defined(PWR) */
00447
00448 /**
00449   * @}
00450   */
00451
00452 #ifdef __cplusplus
00453 }
00454 #endif
00455
00456 #endif /* __STM32F1xx_LL_PWR_H */
00457
00458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_rcc.c Source File

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  • Src
stm32f1xx_ll_rcc.c
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_rcc.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   RCC LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_rcc.h"
00041 #ifdef  USE_FULL_ASSERT
00042   #include "stm32_assert.h"
00043 #else
00044   #define assert_param(expr) ((void)0U)
00045 #endif /* USE_FULL_ASSERT */
00046 /** @addtogroup STM32F1xx_LL_Driver
00047   * @{
00048   */
00049
00050 #if defined(RCC)
00051
00052 /** @defgroup RCC_LL RCC
00053   * @{
00054   */
00055
00056 /* Private types -------------------------------------------------------------*/
00057 /* Private variables ---------------------------------------------------------*/
00058 /* Private constants ---------------------------------------------------------*/
00059 /* Private macros ------------------------------------------------------------*/
00060 /** @addtogroup RCC_LL_Private_Macros
00061   * @{
00062   */
00063 #if defined(RCC_PLLI2S_SUPPORT)
00064 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)     (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
00065                                              || ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
00066 #endif /* RCC_PLLI2S_SUPPORT */
00067
00068 #if defined(USB) || defined(USB_OTG_FS)
00069 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
00070 #endif /* USB */
00071
00072 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
00073 /**
00074   * @}
00075   */
00076
00077 /* Private function prototypes -----------------------------------------------*/
00078 /** @defgroup RCC_LL_Private_Functions RCC Private functions
00079   * @{
00080   */
00081 uint32_t RCC_GetSystemClockFreq(void);
00082 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
00083 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
00084 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
00085 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
00086 #if defined(RCC_PLLI2S_SUPPORT)
00087 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
00088 #endif /* RCC_PLLI2S_SUPPORT */
00089 #if defined(RCC_PLL2_SUPPORT)
00090 uint32_t RCC_PLL2_GetFreqClockFreq(void);
00091 #endif /* RCC_PLL2_SUPPORT */
00092 /**
00093   * @}
00094   */
00095
00096 /* Exported functions --------------------------------------------------------*/
00097 /** @addtogroup RCC_LL_Exported_Functions
00098   * @{
00099   */
00100
00101 /** @addtogroup RCC_LL_EF_Init
00102   * @{
00103   */
00104
00105 /**
00106   * @brief  Reset the RCC clock configuration to the default reset state.
00107   * @note   The default reset state of the clock configuration is given below:
00108   *         - HSI ON and used as system clock source
00109   *         - HSE PLL, PLL2, PLL3 OFF
00110   *         - AHB, APB1 and APB2 prescaler set to 1.
00111   *         - CSS, MCO OFF
00112   *         - All interrupts disabled
00113   * @note   This function doesn't modify the configuration of the
00114   *         - Peripheral clocks
00115   *         - LSI, LSE and RTC clocks
00116   * @retval An ErrorStatus enumeration value:
00117   *          - SUCCESS: RCC registers are de-initialized
00118   *          - ERROR: not applicable
00119   */
00120 ErrorStatus LL_RCC_DeInit(void)
00121 {
00122   uint32_t vl_mask = 0U;
00123
00124   /* Set HSION bit */
00125   LL_RCC_HSI_Enable();
00126
00127   /* Reset SW, HPRE, PPRE, MCOSEL, PLLXTPRE, PLLSRC and ADCPRE bits */
00128   vl_mask = 0xFFFFFFFFU;
00129   CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL |\
00130             RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_ADCPRE));
00131
00132 #if defined(USB)
00133   /* Reset USBPRE bit */
00134   CLEAR_BIT(vl_mask, RCC_CFGR_USBPRE);
00135 #elif defined(USB_OTG_FS)
00136   /* Reset OTGFSPRE bit */
00137   CLEAR_BIT(vl_mask, RCC_CFGR_OTGFSPRE);
00138 #endif /* USB */
00139
00140 #if defined(RCC_CFGR_PLLMULL2)
00141   /* Set PLL multiplication factor to 2 */
00142   vl_mask |= RCC_CFGR_PLLMULL2;
00143 #else
00144   /* Set PLL multiplication factor to 4 */
00145   vl_mask |= RCC_CFGR_PLLMULL4;
00146 #endif /* RCC_CFGR_PLLMULL2 */
00147
00148   LL_RCC_WriteReg(CFGR, vl_mask);
00149
00150   /* Reset HSEON, HSEBYP, CSSON, PLLON bits */
00151   vl_mask = 0xFFFFFFFFU;
00152   CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
00153
00154 #if defined(RCC_CR_PLL2ON)
00155   /* Reset PLL2ON bit */
00156   CLEAR_BIT(vl_mask, RCC_CR_PLL2ON);
00157 #endif /* RCC_CR_PLL2ON */
00158
00159 #if defined(RCC_CR_PLL3ON)
00160   /* Reset PLL3ON bit */
00161   CLEAR_BIT(vl_mask, RCC_CR_PLL3ON);
00162 #endif /* RCC_CR_PLL3ON */
00163
00164   LL_RCC_WriteReg(CR, vl_mask);
00165
00166   /* Set HSITRIM bits to the reset value */
00167   LL_RCC_HSI_SetCalibTrimming(0x10U);
00168
00169 #if defined(RCC_CFGR2_PREDIV1)
00170   /* Reset CFGR2 register */
00171   vl_mask = 0x00000000U;
00172
00173 #if defined(RCC_PLL2_SUPPORT)
00174   /* Set PLL2 multiplication factor to 8 */
00175   vl_mask |= RCC_CFGR2_PLL2MUL8;
00176 #endif /* RCC_PLL2_SUPPORT */
00177
00178 #if defined(RCC_PLLI2S_SUPPORT)
00179   /* Set PLL3 multiplication factor to 8 */
00180   vl_mask |= RCC_CFGR2_PLL3MUL8;
00181 #endif /* RCC_PLLI2S_SUPPORT */
00182
00183   LL_RCC_WriteReg(CFGR2, vl_mask);
00184 #endif /* RCC_CFGR2_PREDIV1 */
00185
00186   /* Disable all interrupts */
00187   LL_RCC_WriteReg(CIR, 0x00000000U);
00188
00189   return SUCCESS;
00190 }
00191
00192 /**
00193   * @}
00194   */
00195
00196 /** @addtogroup RCC_LL_EF_Get_Freq
00197   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
00198   *         and different peripheral clocks available on the device.
00199   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
00200   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
00201   * @note   If SYSCLK source is PLL, function returns values based on
00202   *         HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
00203   * @note   (**) HSI_VALUE is a defined constant but the real value may vary
00204   *              depending on the variations in voltage and temperature.
00205   * @note   (***) HSE_VALUE is a defined constant, user has to ensure that
00206   *               HSE_VALUE is same as the real frequency of the crystal used.
00207   *               Otherwise, this function may have wrong result.
00208   * @note   The result of this function could be incorrect when using fractional
00209   *         value for HSE crystal.
00210   * @note   This function can be used by the user application to compute the
00211   *         baud-rate for the communication peripherals or configure other parameters.
00212   * @{
00213   */
00214
00215 /**
00216   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
00217   * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
00218   *         must be called to update structure fields. Otherwise, any
00219   *         configuration based on this function will be incorrect.
00220   * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
00221   * @retval None
00222   */
00223 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
00224 {
00225   /* Get SYSCLK frequency */
00226   RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
00227
00228   /* HCLK clock frequency */
00229   RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
00230
00231   /* PCLK1 clock frequency */
00232   RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
00233
00234   /* PCLK2 clock frequency */
00235   RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
00236 }
00237
00238 #if defined(RCC_CFGR2_I2S2SRC)
00239 /**
00240   * @brief  Return I2Sx clock frequency
00241   * @param  I2SxSource This parameter can be one of the following values:
00242   *         @arg @ref LL_RCC_I2S2_CLKSOURCE
00243   *         @arg @ref LL_RCC_I2S3_CLKSOURCE
00244   * @retval I2S clock frequency (in Hz)
00245   */
00246 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
00247 {
00248   uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00249
00250   /* Check parameter */
00251   assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
00252
00253   /* I2S1CLK clock frequency */
00254   switch (LL_RCC_GetI2SClockSource(I2SxSource))
00255   {
00256     case LL_RCC_I2S2_CLKSOURCE_SYSCLK:        /*!< System clock selected as I2S clock source */
00257     case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
00258       i2s_frequency = RCC_GetSystemClockFreq();
00259       break;
00260
00261     case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO:    /*!< PLLI2S oscillator clock selected as I2S clock source */
00262     case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
00263     default:
00264       i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
00265       break;
00266   }
00267
00268   return i2s_frequency;
00269 }
00270 #endif /* RCC_CFGR2_I2S2SRC */
00271
00272 #if defined(USB) || defined(USB_OTG_FS)
00273 /**
00274   * @brief  Return USBx clock frequency
00275   * @param  USBxSource This parameter can be one of the following values:
00276   *         @arg @ref LL_RCC_USB_CLKSOURCE
00277   * @retval USB clock frequency (in Hz)
00278   *         @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
00279   */
00280 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
00281 {
00282   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
00283
00284   /* Check parameter */
00285   assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
00286
00287   /* USBCLK clock frequency */
00288   switch (LL_RCC_GetUSBClockSource(USBxSource))
00289   {
00290 #if defined(RCC_CFGR_USBPRE)
00291     case LL_RCC_USB_CLKSOURCE_PLL:        /* PLL clock used as USB clock source */
00292       if (LL_RCC_PLL_IsReady())
00293       {
00294         usb_frequency = RCC_PLL_GetFreqDomain_SYS();
00295       }
00296       break;
00297
00298     case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5:        /* PLL clock divided by 1.5 used as USB clock source */
00299     default:
00300       if (LL_RCC_PLL_IsReady())
00301       {
00302         usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
00303       }
00304       break;
00305 #endif /* RCC_CFGR_USBPRE */
00306 #if defined(RCC_CFGR_OTGFSPRE)
00307     /* USBCLK = PLLVCO/2
00308               = (2 x PLLCLK) / 2
00309               = PLLCLK */
00310     case LL_RCC_USB_CLKSOURCE_PLL_DIV_2:        /* PLL clock used as USB clock source */
00311       if (LL_RCC_PLL_IsReady())
00312       {
00313         usb_frequency = RCC_PLL_GetFreqDomain_SYS();
00314       }
00315       break;
00316
00317     /* USBCLK = PLLVCO/3
00318               = (2 x PLLCLK) / 3 */
00319     case LL_RCC_USB_CLKSOURCE_PLL_DIV_3:        /* PLL clock divided by 3 used as USB clock source */
00320     default:
00321       if (LL_RCC_PLL_IsReady())
00322       {
00323         usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
00324       }
00325       break;
00326 #endif /* RCC_CFGR_OTGFSPRE */
00327   }
00328
00329   return usb_frequency;
00330 }
00331 #endif /* USB */
00332
00333 /**
00334   * @brief  Return ADCx clock frequency
00335   * @param  ADCxSource This parameter can be one of the following values:
00336   *         @arg @ref LL_RCC_ADC_CLKSOURCE
00337   * @retval ADC clock frequency (in Hz)
00338   */
00339 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
00340 {
00341   uint32_t adc_prescaler = 0U;
00342   uint32_t adc_frequency = 0U;
00343
00344   /* Check parameter */
00345   assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
00346
00347   /* Get ADC prescaler */
00348   adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
00349
00350   /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
00351   adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
00352                   / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
00353
00354   return adc_frequency;
00355 }
00356
00357 /**
00358   * @}
00359   */
00360
00361 /**
00362   * @}
00363   */
00364
00365 /** @addtogroup RCC_LL_Private_Functions
00366   * @{
00367   */
00368
00369 /**
00370   * @brief  Return SYSTEM clock frequency
00371   * @retval SYSTEM clock frequency (in Hz)
00372   */
00373 uint32_t RCC_GetSystemClockFreq(void)
00374 {
00375   uint32_t frequency = 0U;
00376
00377   /* Get SYSCLK source -------------------------------------------------------*/
00378   switch (LL_RCC_GetSysClkSource())
00379   {
00380     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
00381       frequency = HSI_VALUE;
00382       break;
00383
00384     case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
00385       frequency = HSE_VALUE;
00386       break;
00387
00388     case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
00389       frequency = RCC_PLL_GetFreqDomain_SYS();
00390       break;
00391
00392     default:
00393       frequency = HSI_VALUE;
00394       break;
00395   }
00396
00397   return frequency;
00398 }
00399
00400 /**
00401   * @brief  Return HCLK clock frequency
00402   * @param  SYSCLK_Frequency SYSCLK clock frequency
00403   * @retval HCLK clock frequency (in Hz)
00404   */
00405 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
00406 {
00407   /* HCLK clock frequency */
00408   return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
00409 }
00410
00411 /**
00412   * @brief  Return PCLK1 clock frequency
00413   * @param  HCLK_Frequency HCLK clock frequency
00414   * @retval PCLK1 clock frequency (in Hz)
00415   */
00416 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
00417 {
00418   /* PCLK1 clock frequency */
00419   return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
00420 }
00421
00422 /**
00423   * @brief  Return PCLK2 clock frequency
00424   * @param  HCLK_Frequency HCLK clock frequency
00425   * @retval PCLK2 clock frequency (in Hz)
00426   */
00427 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
00428 {
00429   /* PCLK2 clock frequency */
00430   return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
00431 }
00432
00433 /**
00434   * @brief  Return PLL clock frequency used for system domain
00435   * @retval PLL clock frequency (in Hz)
00436   */
00437 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
00438 {
00439   uint32_t pllinputfreq = 0U, pllsource = 0U;
00440
00441   /* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
00442
00443   /* Get PLL source */
00444   pllsource = LL_RCC_PLL_GetMainSource();
00445
00446   switch (pllsource)
00447   {
00448     case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
00449       pllinputfreq = HSI_VALUE / 2U;
00450       break;
00451
00452     case LL_RCC_PLLSOURCE_HSE:       /* HSE used as PLL clock source */
00453       pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
00454       break;
00455
00456 #if defined(RCC_PLL2_SUPPORT)
00457     case LL_RCC_PLLSOURCE_PLL2:       /* PLL2 used as PLL clock source */
00458       pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
00459       break;
00460 #endif /* RCC_PLL2_SUPPORT */
00461
00462     default:
00463       pllinputfreq = HSI_VALUE / 2U;
00464       break;
00465   }
00466   return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
00467 }
00468
00469 #if defined(RCC_PLL2_SUPPORT)
00470 /**
00471   * @brief  Return PLL clock frequency used for system domain
00472   * @retval PLL clock frequency (in Hz)
00473   */
00474 uint32_t RCC_PLL2_GetFreqClockFreq(void)
00475 {
00476   return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
00477 }
00478 #endif /* RCC_PLL2_SUPPORT */
00479
00480 #if defined(RCC_PLLI2S_SUPPORT)
00481 /**
00482   * @brief  Return PLL clock frequency used for system domain
00483   * @retval PLL clock frequency (in Hz)
00484   */
00485 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
00486 {
00487   return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
00488 }
00489 #endif /* RCC_PLLI2S_SUPPORT */
00490
00491 /**
00492   * @}
00493   */
00494
00495 /**
00496   * @}
00497   */
00498
00499 #endif /* defined(RCC) */
00500
00501 /**
00502   * @}
00503   */
00504
00505 #endif /* USE_FULL_LL_DRIVER */
00506
00507 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_rcc.h Source File

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stm32f1xx_ll_rcc.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_rcc.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of RCC LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_RCC_H
00040 #define __STM32F1xx_LL_RCC_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined(RCC)
00054
00055 /** @defgroup RCC_LL RCC
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 #if defined(USE_FULL_LL_DRIVER)
00064 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
00065   * @{
00066   */
00067 /**
00068   * @}
00069   */
00070 #endif /*USE_FULL_LL_DRIVER*/
00071 /* Exported types ------------------------------------------------------------*/
00072 #if defined(USE_FULL_LL_DRIVER)
00073 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
00074   * @{
00075   */
00076
00077 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
00078   * @{
00079   */
00080
00081 /**
00082   * @brief  RCC Clocks Frequency Structure
00083   */
00084 typedef struct
00085 {
00086   uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
00087   uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
00088   uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
00089   uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
00090 } LL_RCC_ClocksTypeDef;
00091
00092 /**
00093   * @}
00094   */
00095
00096 /**
00097   * @}
00098   */
00099 #endif /* USE_FULL_LL_DRIVER */
00100
00101 /* Exported constants --------------------------------------------------------*/
00102 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
00103   * @{
00104   */
00105
00106 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
00107   * @brief    Defines used to adapt values of different oscillators
00108   * @note     These values could be modified in the user environment according to
00109   *           HW set-up.
00110   * @{
00111   */
00112 #if !defined  (HSE_VALUE)
00113 #define HSE_VALUE    8000000U  /*!< Value of the HSE oscillator in Hz */
00114 #endif /* HSE_VALUE */
00115
00116 #if !defined  (HSI_VALUE)
00117 #define HSI_VALUE    8000000U  /*!< Value of the HSI oscillator in Hz */
00118 #endif /* HSI_VALUE */
00119
00120 #if !defined  (LSE_VALUE)
00121 #define LSE_VALUE    32768U    /*!< Value of the LSE oscillator in Hz */
00122 #endif /* LSE_VALUE */
00123
00124 #if !defined  (LSI_VALUE)
00125 #define LSI_VALUE    32000U    /*!< Value of the LSI oscillator in Hz */
00126 #endif /* LSI_VALUE */
00127 /**
00128   * @}
00129   */
00130
00131 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
00132   * @brief    Flags defines which can be used with LL_RCC_WriteReg function
00133   * @{
00134   */
00135 #define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
00136 #define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
00137 #define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
00138 #define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
00139 #define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
00140 #define LL_RCC_CIR_PLL3RDYC               RCC_CIR_PLL3RDYC    /*!< PLL3(PLLI2S) Ready Interrupt Clear */
00141 #define LL_RCC_CIR_PLL2RDYC               RCC_CIR_PLL2RDYC    /*!< PLL2 Ready Interrupt Clear */
00142 #define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */
00143 /**
00144   * @}
00145   */
00146
00147 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
00148   * @brief    Flags defines which can be used with LL_RCC_ReadReg function
00149   * @{
00150   */
00151 #define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
00152 #define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
00153 #define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
00154 #define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
00155 #define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
00156 #define LL_RCC_CIR_PLL3RDYF               RCC_CIR_PLL3RDYF    /*!< PLL3(PLLI2S) Ready Interrupt flag */
00157 #define LL_RCC_CIR_PLL2RDYF               RCC_CIR_PLL2RDYF    /*!< PLL2 Ready Interrupt flag */
00158 #define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF        /*!< Clock Security System Interrupt flag */
00159 #define LL_RCC_CSR_PINRSTF                RCC_CSR_PINRSTF     /*!< PIN reset flag */
00160 #define LL_RCC_CSR_PORRSTF                RCC_CSR_PORRSTF     /*!< POR/PDR reset flag */
00161 #define LL_RCC_CSR_SFTRSTF                RCC_CSR_SFTRSTF     /*!< Software Reset flag */
00162 #define LL_RCC_CSR_IWDGRSTF               RCC_CSR_IWDGRSTF    /*!< Independent Watchdog reset flag */
00163 #define LL_RCC_CSR_WWDGRSTF               RCC_CSR_WWDGRSTF    /*!< Window watchdog reset flag */
00164 #define LL_RCC_CSR_LPWRRSTF               RCC_CSR_LPWRRSTF    /*!< Low-Power reset flag */
00165 /**
00166   * @}
00167   */
00168
00169 /** @defgroup RCC_LL_EC_IT IT Defines
00170   * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
00171   * @{
00172   */
00173 #define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
00174 #define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
00175 #define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
00176 #define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
00177 #define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
00178 #define LL_RCC_CIR_PLL3RDYIE              RCC_CIR_PLL3RDYIE     /*!< PLL3(PLLI2S) Ready Interrupt Enable */
00179 #define LL_RCC_CIR_PLL2RDYIE              RCC_CIR_PLL2RDYIE     /*!< PLL2 Ready Interrupt Enable */
00180 /**
00181   * @}
00182   */
00183
00184 #if defined(RCC_CFGR2_PREDIV2)
00185 /** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor
00186   * @{
00187   */
00188 #define LL_RCC_HSE_PREDIV2_DIV_1           RCC_CFGR2_PREDIV2_DIV1   /*!< PREDIV2 input clock not divided */
00189 #define LL_RCC_HSE_PREDIV2_DIV_2           RCC_CFGR2_PREDIV2_DIV2   /*!< PREDIV2 input clock divided by 2 */
00190 #define LL_RCC_HSE_PREDIV2_DIV_3           RCC_CFGR2_PREDIV2_DIV3   /*!< PREDIV2 input clock divided by 3 */
00191 #define LL_RCC_HSE_PREDIV2_DIV_4           RCC_CFGR2_PREDIV2_DIV4   /*!< PREDIV2 input clock divided by 4 */
00192 #define LL_RCC_HSE_PREDIV2_DIV_5           RCC_CFGR2_PREDIV2_DIV5   /*!< PREDIV2 input clock divided by 5 */
00193 #define LL_RCC_HSE_PREDIV2_DIV_6           RCC_CFGR2_PREDIV2_DIV6   /*!< PREDIV2 input clock divided by 6 */
00194 #define LL_RCC_HSE_PREDIV2_DIV_7           RCC_CFGR2_PREDIV2_DIV7   /*!< PREDIV2 input clock divided by 7 */
00195 #define LL_RCC_HSE_PREDIV2_DIV_8           RCC_CFGR2_PREDIV2_DIV8   /*!< PREDIV2 input clock divided by 8 */
00196 #define LL_RCC_HSE_PREDIV2_DIV_9           RCC_CFGR2_PREDIV2_DIV9   /*!< PREDIV2 input clock divided by 9 */
00197 #define LL_RCC_HSE_PREDIV2_DIV_10          RCC_CFGR2_PREDIV2_DIV10  /*!< PREDIV2 input clock divided by 10 */
00198 #define LL_RCC_HSE_PREDIV2_DIV_11          RCC_CFGR2_PREDIV2_DIV11  /*!< PREDIV2 input clock divided by 11 */
00199 #define LL_RCC_HSE_PREDIV2_DIV_12          RCC_CFGR2_PREDIV2_DIV12  /*!< PREDIV2 input clock divided by 12 */
00200 #define LL_RCC_HSE_PREDIV2_DIV_13          RCC_CFGR2_PREDIV2_DIV13  /*!< PREDIV2 input clock divided by 13 */
00201 #define LL_RCC_HSE_PREDIV2_DIV_14          RCC_CFGR2_PREDIV2_DIV14  /*!< PREDIV2 input clock divided by 14 */
00202 #define LL_RCC_HSE_PREDIV2_DIV_15          RCC_CFGR2_PREDIV2_DIV15  /*!< PREDIV2 input clock divided by 15 */
00203 #define LL_RCC_HSE_PREDIV2_DIV_16          RCC_CFGR2_PREDIV2_DIV16  /*!< PREDIV2 input clock divided by 16 */
00204 /**
00205   * @}
00206   */
00207
00208 #endif /* RCC_CFGR2_PREDIV2 */
00209
00210 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
00211   * @{
00212   */
00213 #define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
00214 #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
00215 #define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
00221   * @{
00222   */
00223 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
00224 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
00225 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
00231   * @{
00232   */
00233 #define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
00234 #define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
00235 #define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
00236 #define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
00237 #define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
00238 #define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
00239 #define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
00240 #define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
00241 #define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
00242 /**
00243   * @}
00244   */
00245
00246 /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
00247   * @{
00248   */
00249 #define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
00250 #define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
00251 #define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
00252 #define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
00253 #define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
00254 /**
00255   * @}
00256   */
00257
00258 /** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
00259   * @{
00260   */
00261 #define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
00262 #define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
00263 #define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
00264 #define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
00265 #define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
00266 /**
00267   * @}
00268   */
00269
00270 /** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection
00271   * @{
00272   */
00273 #define LL_RCC_MCO1SOURCE_NOCLOCK          RCC_CFGR_MCOSEL_NOCLOCK      /*!< MCO output disabled, no clock on MCO */
00274 #define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_SYSCLK       /*!< SYSCLK selection as MCO source */
00275 #define LL_RCC_MCO1SOURCE_HSI              RCC_CFGR_MCOSEL_HSI          /*!< HSI selection as MCO source */
00276 #define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_HSE          /*!< HSE selection as MCO source */
00277 #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2     RCC_CFGR_MCOSEL_PLL_DIV2     /*!< PLL clock divided by 2*/
00278 #if defined(RCC_CFGR_MCOSEL_PLL2CLK)
00279 #define LL_RCC_MCO1SOURCE_PLL2CLK          RCC_CFGR_MCOSEL_PLL2         /*!< PLL2 clock selected as MCO source*/
00280 #endif /* RCC_CFGR_MCOSEL_PLL2CLK */
00281 #if defined(RCC_CFGR_MCOSEL_PLL3CLK_DIV2)
00282 #define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2   RCC_CFGR_MCOSEL_PLL3_DIV2    /*!< PLLI2S clock divided by 2 selected as MCO source*/
00283 #endif /* RCC_CFGR_MCOSEL_PLL3CLK_DIV2 */
00284 #if defined(RCC_CFGR_MCOSEL_EXT_HSE)
00285 #define LL_RCC_MCO1SOURCE_EXT_HSE          RCC_CFGR_MCOSEL_EXT_HSE      /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
00286 #endif /* RCC_CFGR_MCOSEL_EXT_HSE */
00287 #if defined(RCC_CFGR_MCOSEL_PLL3CLK)
00288 #define LL_RCC_MCO1SOURCE_PLLI2SCLK        RCC_CFGR_MCOSEL_PLL3CLK      /*!< PLLI2S clock selected as MCO source */
00289 #endif /* RCC_CFGR_MCOSEL_PLL3CLK */
00290 /**
00291   * @}
00292   */
00293
00294 #if defined(USE_FULL_LL_DRIVER)
00295 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
00296   * @{
00297   */
00298 #define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U      /*!< No clock enabled for the peripheral            */
00299 #define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
00300 /**
00301   * @}
00302   */
00303 #endif /* USE_FULL_LL_DRIVER */
00304
00305 #if defined(RCC_CFGR2_I2S2SRC)
00306 /** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection
00307   * @{
00308   */
00309 #define LL_RCC_I2S2_CLKSOURCE_SYSCLK        RCC_CFGR2_I2S2SRC                                          /*!< System clock (SYSCLK) selected as I2S2 clock entry */
00310 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO    (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */
00311 #define LL_RCC_I2S3_CLKSOURCE_SYSCLK        RCC_CFGR2_I2S3SRC                                          /*!< System clock (SYSCLK) selected as I2S3 clock entry */
00312 #define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO    (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */
00313 /**
00314   * @}
00315   */
00316 #endif /* RCC_CFGR2_I2S2SRC */
00317
00318 #if defined(USB_OTG_FS) || defined(USB)
00319 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
00320   * @{
00321   */
00322 #if defined(RCC_CFGR_USBPRE)
00323 #define LL_RCC_USB_CLKSOURCE_PLL             RCC_CFGR_USBPRE        /*!< PLL clock is not divided */
00324 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5     0x00000000U            /*!< PLL clock is divided by 1.5 */
00325 #endif /*RCC_CFGR_USBPRE*/
00326 #if defined(RCC_CFGR_OTGFSPRE)
00327 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_2       RCC_CFGR_OTGFSPRE      /*!< PLL clock is divided by 2 */
00328 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_3       0x00000000U            /*!< PLL clock is divided by 3 */
00329 #endif /*RCC_CFGR_OTGFSPRE*/
00330 /**
00331   * @}
00332   */
00333 #endif /* USB_OTG_FS || USB */
00334
00335 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection
00336   * @{
00337   */
00338 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2    RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/
00339 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4    RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/
00340 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6    RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/
00341 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8    RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/
00342 /**
00343   * @}
00344   */
00345
00346 #if defined(RCC_CFGR2_I2S2SRC)
00347 /** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
00348   * @{
00349   */
00350 #define LL_RCC_I2S2_CLKSOURCE              RCC_CFGR2_I2S2SRC       /*!< I2S2 Clock source selection */
00351 #define LL_RCC_I2S3_CLKSOURCE              RCC_CFGR2_I2S3SRC       /*!< I2S3 Clock source selection */
00352 /**
00353   * @}
00354   */
00355
00356 #endif /* RCC_CFGR2_I2S2SRC */
00357
00358 #if defined(USB_OTG_FS) || defined(USB)
00359 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
00360   * @{
00361   */
00362 #define LL_RCC_USB_CLKSOURCE               0x00400000U     /*!< USB Clock source selection */
00363 /**
00364   * @}
00365   */
00366
00367 #endif /* USB_OTG_FS || USB */
00368
00369 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
00370   * @{
00371   */
00372 #define LL_RCC_ADC_CLKSOURCE               RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
00373 /**
00374   * @}
00375   */
00376
00377 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
00378   * @{
00379   */
00380 #define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U             /*!< No clock used as RTC clock */
00381 #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
00382 #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
00383 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV128    RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 128 used as RTC clock */
00384 /**
00385   * @}
00386   */
00387
00388 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
00389   * @{
00390   */
00391 #if defined(RCC_CFGR_PLLMULL2)
00392 #define LL_RCC_PLL_MUL_2                   RCC_CFGR_PLLMULL2  /*!< PLL input clock*2 */
00393 #endif /*RCC_CFGR_PLLMULL2*/
00394 #if defined(RCC_CFGR_PLLMULL3)
00395 #define LL_RCC_PLL_MUL_3                   RCC_CFGR_PLLMULL3  /*!< PLL input clock*3 */
00396 #endif /*RCC_CFGR_PLLMULL3*/
00397 #define LL_RCC_PLL_MUL_4                   RCC_CFGR_PLLMULL4  /*!< PLL input clock*4 */
00398 #define LL_RCC_PLL_MUL_5                   RCC_CFGR_PLLMULL5  /*!< PLL input clock*5 */
00399 #define LL_RCC_PLL_MUL_6                   RCC_CFGR_PLLMULL6  /*!< PLL input clock*6 */
00400 #define LL_RCC_PLL_MUL_7                   RCC_CFGR_PLLMULL7  /*!< PLL input clock*7 */
00401 #define LL_RCC_PLL_MUL_8                   RCC_CFGR_PLLMULL8  /*!< PLL input clock*8 */
00402 #define LL_RCC_PLL_MUL_9                   RCC_CFGR_PLLMULL9  /*!< PLL input clock*9 */
00403 #if defined(RCC_CFGR_PLLMULL6_5)
00404 #define LL_RCC_PLL_MUL_6_5                 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */
00405 #else
00406 #define LL_RCC_PLL_MUL_10                  RCC_CFGR_PLLMULL10  /*!< PLL input clock*10 */
00407 #define LL_RCC_PLL_MUL_11                  RCC_CFGR_PLLMULL11  /*!< PLL input clock*11 */
00408 #define LL_RCC_PLL_MUL_12                  RCC_CFGR_PLLMULL12  /*!< PLL input clock*12 */
00409 #define LL_RCC_PLL_MUL_13                  RCC_CFGR_PLLMULL13  /*!< PLL input clock*13 */
00410 #define LL_RCC_PLL_MUL_14                  RCC_CFGR_PLLMULL14  /*!< PLL input clock*14 */
00411 #define LL_RCC_PLL_MUL_15                  RCC_CFGR_PLLMULL15  /*!< PLL input clock*15 */
00412 #define LL_RCC_PLL_MUL_16                  RCC_CFGR_PLLMULL16  /*!< PLL input clock*16 */
00413 #endif /*RCC_CFGR_PLLMULL6_5*/
00414 /**
00415   * @}
00416   */
00417
00418 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
00419   * @{
00420   */
00421 #define LL_RCC_PLLSOURCE_HSI_DIV_2         0x00000000U                                    /*!< HSI clock divided by 2 selected as PLL entry clock source */
00422 #define LL_RCC_PLLSOURCE_HSE               RCC_CFGR_PLLSRC                                /*!< HSE/PREDIV1 clock selected as PLL entry clock source */
00423 #if defined(RCC_CFGR2_PREDIV1SRC)
00424 #define LL_RCC_PLLSOURCE_PLL2              (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */
00425 #endif /*RCC_CFGR2_PREDIV1SRC*/
00426
00427 #define LL_RCC_PLLSOURCE_HSE_DIV_1         RCC_CFGR_PLLSRC                                /*!< HSE clock selected as PLL entry clock source */
00428 #if defined(RCC_CFGR2_PREDIV1)
00429 #define LL_RCC_PLLSOURCE_HSE_DIV_2         (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2)    /*!< HSE/2 clock selected as PLL entry clock source */
00430 #define LL_RCC_PLLSOURCE_HSE_DIV_3         (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3)    /*!< HSE/3 clock selected as PLL entry clock source */
00431 #define LL_RCC_PLLSOURCE_HSE_DIV_4         (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4)    /*!< HSE/4 clock selected as PLL entry clock source */
00432 #define LL_RCC_PLLSOURCE_HSE_DIV_5         (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5)    /*!< HSE/5 clock selected as PLL entry clock source */
00433 #define LL_RCC_PLLSOURCE_HSE_DIV_6         (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6)    /*!< HSE/6 clock selected as PLL entry clock source */
00434 #define LL_RCC_PLLSOURCE_HSE_DIV_7         (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7)    /*!< HSE/7 clock selected as PLL entry clock source */
00435 #define LL_RCC_PLLSOURCE_HSE_DIV_8         (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8)    /*!< HSE/8 clock selected as PLL entry clock source */
00436 #define LL_RCC_PLLSOURCE_HSE_DIV_9         (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9)    /*!< HSE/9 clock selected as PLL entry clock source */
00437 #define LL_RCC_PLLSOURCE_HSE_DIV_10        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10)   /*!< HSE/10 clock selected as PLL entry clock source */
00438 #define LL_RCC_PLLSOURCE_HSE_DIV_11        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11)   /*!< HSE/11 clock selected as PLL entry clock source */
00439 #define LL_RCC_PLLSOURCE_HSE_DIV_12        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12)   /*!< HSE/12 clock selected as PLL entry clock source */
00440 #define LL_RCC_PLLSOURCE_HSE_DIV_13        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13)   /*!< HSE/13 clock selected as PLL entry clock source */
00441 #define LL_RCC_PLLSOURCE_HSE_DIV_14        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14)   /*!< HSE/14 clock selected as PLL entry clock source */
00442 #define LL_RCC_PLLSOURCE_HSE_DIV_15        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15)   /*!< HSE/15 clock selected as PLL entry clock source */
00443 #define LL_RCC_PLLSOURCE_HSE_DIV_16        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16)   /*!< HSE/16 clock selected as PLL entry clock source */
00444 #if defined(RCC_CFGR2_PREDIV1SRC)
00445 #define LL_RCC_PLLSOURCE_PLL2_DIV_2        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U)    /*!< PLL2/2 clock selected as PLL entry clock source */
00446 #define LL_RCC_PLLSOURCE_PLL2_DIV_3        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U)    /*!< PLL2/3 clock selected as PLL entry clock source */
00447 #define LL_RCC_PLLSOURCE_PLL2_DIV_4        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U)    /*!< PLL2/4 clock selected as PLL entry clock source */
00448 #define LL_RCC_PLLSOURCE_PLL2_DIV_5        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U)    /*!< PLL2/5 clock selected as PLL entry clock source */
00449 #define LL_RCC_PLLSOURCE_PLL2_DIV_6        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U)    /*!< PLL2/6 clock selected as PLL entry clock source */
00450 #define LL_RCC_PLLSOURCE_PLL2_DIV_7        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U)    /*!< PLL2/7 clock selected as PLL entry clock source */
00451 #define LL_RCC_PLLSOURCE_PLL2_DIV_8        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U)    /*!< PLL2/8 clock selected as PLL entry clock source */
00452 #define LL_RCC_PLLSOURCE_PLL2_DIV_9        (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U)    /*!< PLL2/9 clock selected as PLL entry clock source */
00453 #define LL_RCC_PLLSOURCE_PLL2_DIV_10       (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U)   /*!< PLL2/10 clock selected as PLL entry clock source */
00454 #define LL_RCC_PLLSOURCE_PLL2_DIV_11       (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U)   /*!< PLL2/11 clock selected as PLL entry clock source */
00455 #define LL_RCC_PLLSOURCE_PLL2_DIV_12       (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U)   /*!< PLL2/12 clock selected as PLL entry clock source */
00456 #define LL_RCC_PLLSOURCE_PLL2_DIV_13       (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U)   /*!< PLL2/13 clock selected as PLL entry clock source */
00457 #define LL_RCC_PLLSOURCE_PLL2_DIV_14       (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U)   /*!< PLL2/14 clock selected as PLL entry clock source */
00458 #define LL_RCC_PLLSOURCE_PLL2_DIV_15       (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U)   /*!< PLL2/15 clock selected as PLL entry clock source */
00459 #define LL_RCC_PLLSOURCE_PLL2_DIV_16       (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U)   /*!< PLL2/16 clock selected as PLL entry clock source */
00460 #endif /*RCC_CFGR2_PREDIV1SRC*/
00461 #else
00462 #define LL_RCC_PLLSOURCE_HSE_DIV_2         (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)         /*!< HSE/2 clock selected as PLL entry clock source */
00463 #endif /*RCC_CFGR2_PREDIV1*/
00464 /**
00465   * @}
00466   */
00467
00468 /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
00469   * @{
00470   */
00471 #if defined(RCC_CFGR2_PREDIV1)
00472 #define LL_RCC_PREDIV_DIV_1                RCC_CFGR2_PREDIV1_DIV1   /*!< PREDIV1 input clock not divided */
00473 #define LL_RCC_PREDIV_DIV_2                RCC_CFGR2_PREDIV1_DIV2   /*!< PREDIV1 input clock divided by 2 */
00474 #define LL_RCC_PREDIV_DIV_3                RCC_CFGR2_PREDIV1_DIV3   /*!< PREDIV1 input clock divided by 3 */
00475 #define LL_RCC_PREDIV_DIV_4                RCC_CFGR2_PREDIV1_DIV4   /*!< PREDIV1 input clock divided by 4 */
00476 #define LL_RCC_PREDIV_DIV_5                RCC_CFGR2_PREDIV1_DIV5   /*!< PREDIV1 input clock divided by 5 */
00477 #define LL_RCC_PREDIV_DIV_6                RCC_CFGR2_PREDIV1_DIV6   /*!< PREDIV1 input clock divided by 6 */
00478 #define LL_RCC_PREDIV_DIV_7                RCC_CFGR2_PREDIV1_DIV7   /*!< PREDIV1 input clock divided by 7 */
00479 #define LL_RCC_PREDIV_DIV_8                RCC_CFGR2_PREDIV1_DIV8   /*!< PREDIV1 input clock divided by 8 */
00480 #define LL_RCC_PREDIV_DIV_9                RCC_CFGR2_PREDIV1_DIV9   /*!< PREDIV1 input clock divided by 9 */
00481 #define LL_RCC_PREDIV_DIV_10               RCC_CFGR2_PREDIV1_DIV10  /*!< PREDIV1 input clock divided by 10 */
00482 #define LL_RCC_PREDIV_DIV_11               RCC_CFGR2_PREDIV1_DIV11  /*!< PREDIV1 input clock divided by 11 */
00483 #define LL_RCC_PREDIV_DIV_12               RCC_CFGR2_PREDIV1_DIV12  /*!< PREDIV1 input clock divided by 12 */
00484 #define LL_RCC_PREDIV_DIV_13               RCC_CFGR2_PREDIV1_DIV13  /*!< PREDIV1 input clock divided by 13 */
00485 #define LL_RCC_PREDIV_DIV_14               RCC_CFGR2_PREDIV1_DIV14  /*!< PREDIV1 input clock divided by 14 */
00486 #define LL_RCC_PREDIV_DIV_15               RCC_CFGR2_PREDIV1_DIV15  /*!< PREDIV1 input clock divided by 15 */
00487 #define LL_RCC_PREDIV_DIV_16               RCC_CFGR2_PREDIV1_DIV16  /*!< PREDIV1 input clock divided by 16 */
00488 #else
00489 #define LL_RCC_PREDIV_DIV_1                0x00000000U              /*!< HSE divider clock clock not divided */
00490 #define LL_RCC_PREDIV_DIV_2                RCC_CFGR_PLLXTPRE        /*!< HSE divider clock divided by 2 for PLL entry */
00491 #endif /*RCC_CFGR2_PREDIV1*/
00492 /**
00493   * @}
00494   */
00495
00496 #if defined(RCC_PLLI2S_SUPPORT)
00497 /** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL
00498   * @{
00499   */
00500 #define LL_RCC_PLLI2S_MUL_8                RCC_CFGR2_PLL3MUL8   /*!< PLLI2S input clock * 8 */
00501 #define LL_RCC_PLLI2S_MUL_9                RCC_CFGR2_PLL3MUL9   /*!< PLLI2S input clock * 9 */
00502 #define LL_RCC_PLLI2S_MUL_10               RCC_CFGR2_PLL3MUL10  /*!< PLLI2S input clock * 10 */
00503 #define LL_RCC_PLLI2S_MUL_11               RCC_CFGR2_PLL3MUL11  /*!< PLLI2S input clock * 11 */
00504 #define LL_RCC_PLLI2S_MUL_12               RCC_CFGR2_PLL3MUL12  /*!< PLLI2S input clock * 12 */
00505 #define LL_RCC_PLLI2S_MUL_13               RCC_CFGR2_PLL3MUL13  /*!< PLLI2S input clock * 13 */
00506 #define LL_RCC_PLLI2S_MUL_14               RCC_CFGR2_PLL3MUL14  /*!< PLLI2S input clock * 14 */
00507 #define LL_RCC_PLLI2S_MUL_16               RCC_CFGR2_PLL3MUL16  /*!< PLLI2S input clock * 16 */
00508 #define LL_RCC_PLLI2S_MUL_20               RCC_CFGR2_PLL3MUL20  /*!< PLLI2S input clock * 20 */
00509 /**
00510   * @}
00511   */
00512
00513 #endif /* RCC_PLLI2S_SUPPORT */
00514
00515 #if defined(RCC_PLL2_SUPPORT)
00516 /** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL
00517   * @{
00518   */
00519 #define LL_RCC_PLL2_MUL_8                  RCC_CFGR2_PLL2MUL8   /*!< PLL2 input clock * 8 */
00520 #define LL_RCC_PLL2_MUL_9                  RCC_CFGR2_PLL2MUL9   /*!< PLL2 input clock * 9 */
00521 #define LL_RCC_PLL2_MUL_10                 RCC_CFGR2_PLL2MUL10  /*!< PLL2 input clock * 10 */
00522 #define LL_RCC_PLL2_MUL_11                 RCC_CFGR2_PLL2MUL11  /*!< PLL2 input clock * 11 */
00523 #define LL_RCC_PLL2_MUL_12                 RCC_CFGR2_PLL2MUL12  /*!< PLL2 input clock * 12 */
00524 #define LL_RCC_PLL2_MUL_13                 RCC_CFGR2_PLL2MUL13  /*!< PLL2 input clock * 13 */
00525 #define LL_RCC_PLL2_MUL_14                 RCC_CFGR2_PLL2MUL14  /*!< PLL2 input clock * 14 */
00526 #define LL_RCC_PLL2_MUL_16                 RCC_CFGR2_PLL2MUL16  /*!< PLL2 input clock * 16 */
00527 #define LL_RCC_PLL2_MUL_20                 RCC_CFGR2_PLL2MUL20  /*!< PLL2 input clock * 20 */
00528 /**
00529   * @}
00530   */
00531
00532 #endif /* RCC_PLL2_SUPPORT */
00533
00534 /**
00535   * @}
00536   */
00537
00538 /* Exported macro ------------------------------------------------------------*/
00539 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
00540   * @{
00541   */
00542
00543 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
00544   * @{
00545   */
00546
00547 /**
00548   * @brief  Write a value in RCC register
00549   * @param  __REG__ Register to be written
00550   * @param  __VALUE__ Value to be written in the register
00551   * @retval None
00552   */
00553 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
00554
00555 /**
00556   * @brief  Read a value in RCC register
00557   * @param  __REG__ Register to be read
00558   * @retval Register value
00559   */
00560 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
00561 /**
00562   * @}
00563   */
00564
00565 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
00566   * @{
00567   */
00568
00569 #if defined(RCC_CFGR_PLLMULL6_5)
00570 /**
00571   * @brief  Helper macro to calculate the PLLCLK frequency
00572   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
00573   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1)
00574   * @param  __PLLMUL__: This parameter can be one of the following values:
00575   *         @arg @ref LL_RCC_PLL_MUL_4
00576   *         @arg @ref LL_RCC_PLL_MUL_5
00577   *         @arg @ref LL_RCC_PLL_MUL_6
00578   *         @arg @ref LL_RCC_PLL_MUL_7
00579   *         @arg @ref LL_RCC_PLL_MUL_8
00580   *         @arg @ref LL_RCC_PLL_MUL_9
00581   *         @arg @ref LL_RCC_PLL_MUL_6_5
00582   * @retval PLL clock frequency (in Hz)
00583   */
00584 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
00585           (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \
00586               ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\
00587               (((__INPUTFREQ__) * 13U) / 2U))
00588
00589 #else
00590 /**
00591   * @brief  Helper macro to calculate the PLLCLK frequency
00592   * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ());
00593   * @param  __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
00594   * @param  __PLLMUL__: This parameter can be one of the following values:
00595   *         @arg @ref LL_RCC_PLL_MUL_2
00596   *         @arg @ref LL_RCC_PLL_MUL_3
00597   *         @arg @ref LL_RCC_PLL_MUL_4
00598   *         @arg @ref LL_RCC_PLL_MUL_5
00599   *         @arg @ref LL_RCC_PLL_MUL_6
00600   *         @arg @ref LL_RCC_PLL_MUL_7
00601   *         @arg @ref LL_RCC_PLL_MUL_8
00602   *         @arg @ref LL_RCC_PLL_MUL_9
00603   *         @arg @ref LL_RCC_PLL_MUL_10
00604   *         @arg @ref LL_RCC_PLL_MUL_11
00605   *         @arg @ref LL_RCC_PLL_MUL_12
00606   *         @arg @ref LL_RCC_PLL_MUL_13
00607   *         @arg @ref LL_RCC_PLL_MUL_14
00608   *         @arg @ref LL_RCC_PLL_MUL_15
00609   *         @arg @ref LL_RCC_PLL_MUL_16
00610   * @retval PLL clock frequency (in Hz)
00611   */
00612 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))
00613 #endif /* RCC_CFGR_PLLMULL6_5 */
00614
00615 #if defined(RCC_PLLI2S_SUPPORT)
00616 /**
00617   * @brief  Helper macro to calculate the PLLI2S frequency
00618   * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
00619   * @param  __INPUTFREQ__ PLLI2S Input frequency (based on HSE value)
00620   * @param  __PLLI2SMUL__: This parameter can be one of the following values:
00621   *         @arg @ref LL_RCC_PLLI2S_MUL_8
00622   *         @arg @ref LL_RCC_PLLI2S_MUL_9
00623   *         @arg @ref LL_RCC_PLLI2S_MUL_10
00624   *         @arg @ref LL_RCC_PLLI2S_MUL_11
00625   *         @arg @ref LL_RCC_PLLI2S_MUL_12
00626   *         @arg @ref LL_RCC_PLLI2S_MUL_13
00627   *         @arg @ref LL_RCC_PLLI2S_MUL_14
00628   *         @arg @ref LL_RCC_PLLI2S_MUL_16
00629   *         @arg @ref LL_RCC_PLLI2S_MUL_20
00630   * @param  __PLLI2SDIV__: This parameter can be one of the following values:
00631   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
00632   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
00633   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
00634   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
00635   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
00636   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
00637   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
00638   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
00639   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
00640   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
00641   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
00642   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
00643   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
00644   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
00645   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
00646   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
00647   * @retval PLLI2S clock frequency (in Hz)
00648   */
00649 #define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
00650 #endif /* RCC_PLLI2S_SUPPORT */
00651
00652 #if defined(RCC_PLL2_SUPPORT)
00653 /**
00654   * @brief  Helper macro to calculate the PLL2 frequency
00655   * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
00656   * @param  __INPUTFREQ__ PLL2 Input frequency (based on HSE value)
00657   * @param  __PLL2MUL__: This parameter can be one of the following values:
00658   *         @arg @ref LL_RCC_PLL2_MUL_8
00659   *         @arg @ref LL_RCC_PLL2_MUL_9
00660   *         @arg @ref LL_RCC_PLL2_MUL_10
00661   *         @arg @ref LL_RCC_PLL2_MUL_11
00662   *         @arg @ref LL_RCC_PLL2_MUL_12
00663   *         @arg @ref LL_RCC_PLL2_MUL_13
00664   *         @arg @ref LL_RCC_PLL2_MUL_14
00665   *         @arg @ref LL_RCC_PLL2_MUL_16
00666   *         @arg @ref LL_RCC_PLL2_MUL_20
00667   * @param  __PLL2DIV__: This parameter can be one of the following values:
00668   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
00669   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
00670   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
00671   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
00672   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
00673   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
00674   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
00675   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
00676   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
00677   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
00678   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
00679   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
00680   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
00681   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
00682   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
00683   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
00684   * @retval PLL2 clock frequency (in Hz)
00685   */
00686 #define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
00687 #endif /* RCC_PLL2_SUPPORT */
00688
00689 /**
00690   * @brief  Helper macro to calculate the HCLK frequency
00691   * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
00692   *        ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
00693   * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
00694   * @param  __AHBPRESCALER__: This parameter can be one of the following values:
00695   *         @arg @ref LL_RCC_SYSCLK_DIV_1
00696   *         @arg @ref LL_RCC_SYSCLK_DIV_2
00697   *         @arg @ref LL_RCC_SYSCLK_DIV_4
00698   *         @arg @ref LL_RCC_SYSCLK_DIV_8
00699   *         @arg @ref LL_RCC_SYSCLK_DIV_16
00700   *         @arg @ref LL_RCC_SYSCLK_DIV_64
00701   *         @arg @ref LL_RCC_SYSCLK_DIV_128
00702   *         @arg @ref LL_RCC_SYSCLK_DIV_256
00703   *         @arg @ref LL_RCC_SYSCLK_DIV_512
00704   * @retval HCLK clock frequency (in Hz)
00705   */
00706 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
00707
00708 /**
00709   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
00710   * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
00711   *        ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
00712   * @param  __HCLKFREQ__ HCLK frequency
00713   * @param  __APB1PRESCALER__: This parameter can be one of the following values:
00714   *         @arg @ref LL_RCC_APB1_DIV_1
00715   *         @arg @ref LL_RCC_APB1_DIV_2
00716   *         @arg @ref LL_RCC_APB1_DIV_4
00717   *         @arg @ref LL_RCC_APB1_DIV_8
00718   *         @arg @ref LL_RCC_APB1_DIV_16
00719   * @retval PCLK1 clock frequency (in Hz)
00720   */
00721 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
00722
00723 /**
00724   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
00725   * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
00726   *        ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
00727   * @param  __HCLKFREQ__ HCLK frequency
00728   * @param  __APB2PRESCALER__: This parameter can be one of the following values:
00729   *         @arg @ref LL_RCC_APB2_DIV_1
00730   *         @arg @ref LL_RCC_APB2_DIV_2
00731   *         @arg @ref LL_RCC_APB2_DIV_4
00732   *         @arg @ref LL_RCC_APB2_DIV_8
00733   *         @arg @ref LL_RCC_APB2_DIV_16
00734   * @retval PCLK2 clock frequency (in Hz)
00735   */
00736 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
00737
00738 /**
00739   * @}
00740   */
00741
00742 /**
00743   * @}
00744   */
00745
00746 /* Exported functions --------------------------------------------------------*/
00747 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
00748   * @{
00749   */
00750
00751 /** @defgroup RCC_LL_EF_HSE HSE
00752   * @{
00753   */
00754
00755 /**
00756   * @brief  Enable the Clock Security System.
00757   * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
00758   * @retval None
00759   */
00760 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
00761 {
00762   SET_BIT(RCC->CR, RCC_CR_CSSON);
00763 }
00764
00765 /**
00766   * @brief  Enable HSE external oscillator (HSE Bypass)
00767   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
00768   * @retval None
00769   */
00770 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
00771 {
00772   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
00773 }
00774
00775 /**
00776   * @brief  Disable HSE external oscillator (HSE Bypass)
00777   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
00778   * @retval None
00779   */
00780 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
00781 {
00782   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
00783 }
00784
00785 /**
00786   * @brief  Enable HSE crystal oscillator (HSE ON)
00787   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
00788   * @retval None
00789   */
00790 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
00791 {
00792   SET_BIT(RCC->CR, RCC_CR_HSEON);
00793 }
00794
00795 /**
00796   * @brief  Disable HSE crystal oscillator (HSE ON)
00797   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
00798   * @retval None
00799   */
00800 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
00801 {
00802   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
00803 }
00804
00805 /**
00806   * @brief  Check if HSE oscillator Ready
00807   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
00808   * @retval State of bit (1 or 0).
00809   */
00810 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
00811 {
00812   return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
00813 }
00814
00815 #if defined(RCC_CFGR2_PREDIV2)
00816 /**
00817   * @brief  Get PREDIV2 division factor
00818   * @rmtoll CFGR2        PREDIV2       LL_RCC_HSE_GetPrediv2
00819   * @retval Returned value can be one of the following values:
00820   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
00821   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
00822   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
00823   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
00824   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
00825   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
00826   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
00827   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
00828   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
00829   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
00830   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
00831   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
00832   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
00833   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
00834   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
00835   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
00836   */
00837 __STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void)
00838 {
00839   return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2));
00840 }
00841 #endif /* RCC_CFGR2_PREDIV2 */
00842
00843 /**
00844   * @}
00845   */
00846
00847 /** @defgroup RCC_LL_EF_HSI HSI
00848   * @{
00849   */
00850
00851 /**
00852   * @brief  Enable HSI oscillator
00853   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
00854   * @retval None
00855   */
00856 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
00857 {
00858   SET_BIT(RCC->CR, RCC_CR_HSION);
00859 }
00860
00861 /**
00862   * @brief  Disable HSI oscillator
00863   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
00864   * @retval None
00865   */
00866 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
00867 {
00868   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
00869 }
00870
00871 /**
00872   * @brief  Check if HSI clock is ready
00873   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
00874   * @retval State of bit (1 or 0).
00875   */
00876 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
00877 {
00878   return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
00879 }
00880
00881 /**
00882   * @brief  Get HSI Calibration value
00883   * @note When HSITRIM is written, HSICAL is updated with the sum of
00884   *       HSITRIM and the factory trim value
00885   * @rmtoll CR        HSICAL        LL_RCC_HSI_GetCalibration
00886   * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
00887   */
00888 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
00889 {
00890   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
00891 }
00892
00893 /**
00894   * @brief  Set HSI Calibration trimming
00895   * @note user-programmable trimming value that is added to the HSICAL
00896   * @note Default value is 16, which, when added to the HSICAL value,
00897   *       should trim the HSI to 16 MHz +/- 1 %
00898   * @rmtoll CR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
00899   * @param  Value between Min_Data = 0x00 and Max_Data = 0x1F
00900   * @retval None
00901   */
00902 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
00903 {
00904   MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
00905 }
00906
00907 /**
00908   * @brief  Get HSI Calibration trimming
00909   * @rmtoll CR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
00910   * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
00911   */
00912 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
00913 {
00914   return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
00915 }
00916
00917 /**
00918   * @}
00919   */
00920
00921 /** @defgroup RCC_LL_EF_LSE LSE
00922   * @{
00923   */
00924
00925 /**
00926   * @brief  Enable  Low Speed External (LSE) crystal.
00927   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
00928   * @retval None
00929   */
00930 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
00931 {
00932   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
00933 }
00934
00935 /**
00936   * @brief  Disable  Low Speed External (LSE) crystal.
00937   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
00938   * @retval None
00939   */
00940 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
00941 {
00942   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
00943 }
00944
00945 /**
00946   * @brief  Enable external clock source (LSE bypass).
00947   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
00948   * @retval None
00949   */
00950 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
00951 {
00952   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
00953 }
00954
00955 /**
00956   * @brief  Disable external clock source (LSE bypass).
00957   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
00958   * @retval None
00959   */
00960 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
00961 {
00962   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
00963 }
00964
00965 /**
00966   * @brief  Check if LSE oscillator Ready
00967   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
00968   * @retval State of bit (1 or 0).
00969   */
00970 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
00971 {
00972   return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
00973 }
00974
00975 /**
00976   * @}
00977   */
00978
00979 /** @defgroup RCC_LL_EF_LSI LSI
00980   * @{
00981   */
00982
00983 /**
00984   * @brief  Enable LSI Oscillator
00985   * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
00986   * @retval None
00987   */
00988 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
00989 {
00990   SET_BIT(RCC->CSR, RCC_CSR_LSION);
00991 }
00992
00993 /**
00994   * @brief  Disable LSI Oscillator
00995   * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
00996   * @retval None
00997   */
00998 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
00999 {
01000   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
01001 }
01002
01003 /**
01004   * @brief  Check if LSI is Ready
01005   * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
01006   * @retval State of bit (1 or 0).
01007   */
01008 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
01009 {
01010   return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
01011 }
01012
01013 /**
01014   * @}
01015   */
01016
01017 /** @defgroup RCC_LL_EF_System System
01018   * @{
01019   */
01020
01021 /**
01022   * @brief  Configure the system clock source
01023   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
01024   * @param  Source This parameter can be one of the following values:
01025   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
01026   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
01027   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
01028   * @retval None
01029   */
01030 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
01031 {
01032   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
01033 }
01034
01035 /**
01036   * @brief  Get the system clock source
01037   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
01038   * @retval Returned value can be one of the following values:
01039   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
01040   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
01041   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
01042   */
01043 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
01044 {
01045   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
01046 }
01047
01048 /**
01049   * @brief  Set AHB prescaler
01050   * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
01051   * @param  Prescaler This parameter can be one of the following values:
01052   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01053   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01054   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01055   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01056   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01057   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01058   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01059   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01060   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01061   * @retval None
01062   */
01063 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
01064 {
01065   MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
01066 }
01067
01068 /**
01069   * @brief  Set APB1 prescaler
01070   * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
01071   * @param  Prescaler This parameter can be one of the following values:
01072   *         @arg @ref LL_RCC_APB1_DIV_1
01073   *         @arg @ref LL_RCC_APB1_DIV_2
01074   *         @arg @ref LL_RCC_APB1_DIV_4
01075   *         @arg @ref LL_RCC_APB1_DIV_8
01076   *         @arg @ref LL_RCC_APB1_DIV_16
01077   * @retval None
01078   */
01079 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
01080 {
01081   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
01082 }
01083
01084 /**
01085   * @brief  Set APB2 prescaler
01086   * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
01087   * @param  Prescaler This parameter can be one of the following values:
01088   *         @arg @ref LL_RCC_APB2_DIV_1
01089   *         @arg @ref LL_RCC_APB2_DIV_2
01090   *         @arg @ref LL_RCC_APB2_DIV_4
01091   *         @arg @ref LL_RCC_APB2_DIV_8
01092   *         @arg @ref LL_RCC_APB2_DIV_16
01093   * @retval None
01094   */
01095 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
01096 {
01097   MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
01098 }
01099
01100 /**
01101   * @brief  Get AHB prescaler
01102   * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
01103   * @retval Returned value can be one of the following values:
01104   *         @arg @ref LL_RCC_SYSCLK_DIV_1
01105   *         @arg @ref LL_RCC_SYSCLK_DIV_2
01106   *         @arg @ref LL_RCC_SYSCLK_DIV_4
01107   *         @arg @ref LL_RCC_SYSCLK_DIV_8
01108   *         @arg @ref LL_RCC_SYSCLK_DIV_16
01109   *         @arg @ref LL_RCC_SYSCLK_DIV_64
01110   *         @arg @ref LL_RCC_SYSCLK_DIV_128
01111   *         @arg @ref LL_RCC_SYSCLK_DIV_256
01112   *         @arg @ref LL_RCC_SYSCLK_DIV_512
01113   */
01114 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
01115 {
01116   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
01117 }
01118
01119 /**
01120   * @brief  Get APB1 prescaler
01121   * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
01122   * @retval Returned value can be one of the following values:
01123   *         @arg @ref LL_RCC_APB1_DIV_1
01124   *         @arg @ref LL_RCC_APB1_DIV_2
01125   *         @arg @ref LL_RCC_APB1_DIV_4
01126   *         @arg @ref LL_RCC_APB1_DIV_8
01127   *         @arg @ref LL_RCC_APB1_DIV_16
01128   */
01129 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
01130 {
01131   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
01132 }
01133
01134 /**
01135   * @brief  Get APB2 prescaler
01136   * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
01137   * @retval Returned value can be one of the following values:
01138   *         @arg @ref LL_RCC_APB2_DIV_1
01139   *         @arg @ref LL_RCC_APB2_DIV_2
01140   *         @arg @ref LL_RCC_APB2_DIV_4
01141   *         @arg @ref LL_RCC_APB2_DIV_8
01142   *         @arg @ref LL_RCC_APB2_DIV_16
01143   */
01144 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
01145 {
01146   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
01147 }
01148
01149 /**
01150   * @}
01151   */
01152
01153 /** @defgroup RCC_LL_EF_MCO MCO
01154   * @{
01155   */
01156
01157 /**
01158   * @brief  Configure MCOx
01159   * @rmtoll CFGR         MCO           LL_RCC_ConfigMCO
01160   * @param  MCOxSource This parameter can be one of the following values:
01161   *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
01162   *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
01163   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
01164   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
01165   *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
01166   *         @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*)
01167   *         @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
01168   *         @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*)
01169   *         @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
01170   *
01171   *         (*) value not defined in all devices
01172   * @retval None
01173   */
01174 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource)
01175 {
01176   MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
01177 }
01178
01179 /**
01180   * @}
01181   */
01182
01183 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
01184   * @{
01185   */
01186
01187 #if defined(RCC_CFGR2_I2S2SRC)
01188 /**
01189   * @brief  Configure I2Sx clock source
01190   * @rmtoll CFGR2        I2S2SRC       LL_RCC_SetI2SClockSource\n
01191   *         CFGR2        I2S3SRC       LL_RCC_SetI2SClockSource
01192   * @param  I2SxSource This parameter can be one of the following values:
01193   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
01194   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
01195   *         @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
01196   *         @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
01197   * @retval None
01198   */
01199 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
01200 {
01201   MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U));
01202 }
01203 #endif /* RCC_CFGR2_I2S2SRC */
01204
01205 #if defined(USB_OTG_FS) || defined(USB)
01206 /**
01207   * @brief  Configure USB clock source
01208   * @rmtoll CFGR         OTGFSPRE      LL_RCC_SetUSBClockSource\n
01209   *         CFGR         USBPRE        LL_RCC_SetUSBClockSource
01210   * @param  USBxSource This parameter can be one of the following values:
01211   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
01212   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
01213   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
01214   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
01215   *
01216   *         (*) value not defined in all devices
01217   * @retval None
01218   */
01219 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
01220 {
01221 #if defined(RCC_CFGR_USBPRE)
01222   MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
01223 #else /*RCC_CFGR_OTGFSPRE*/
01224   MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource);
01225 #endif /*RCC_CFGR_USBPRE*/
01226 }
01227 #endif /* USB_OTG_FS || USB */
01228
01229 /**
01230   * @brief  Configure ADC clock source
01231   * @rmtoll CFGR         ADCPRE        LL_RCC_SetADCClockSource
01232   * @param  ADCxSource This parameter can be one of the following values:
01233   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
01234   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
01235   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
01236   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
01237   * @retval None
01238   */
01239 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
01240 {
01241   MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
01242 }
01243
01244 #if defined(RCC_CFGR2_I2S2SRC)
01245 /**
01246   * @brief  Get I2Sx clock source
01247   * @rmtoll CFGR2        I2S2SRC       LL_RCC_GetI2SClockSource\n
01248   *         CFGR2        I2S3SRC       LL_RCC_GetI2SClockSource
01249   * @param  I2Sx This parameter can be one of the following values:
01250   *         @arg @ref LL_RCC_I2S2_CLKSOURCE
01251   *         @arg @ref LL_RCC_I2S3_CLKSOURCE
01252   * @retval Returned value can be one of the following values:
01253   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
01254   *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
01255   *         @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
01256   *         @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
01257   */
01258 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
01259 {
01260   return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx);
01261 }
01262 #endif /* RCC_CFGR2_I2S2SRC */
01263
01264 #if defined(USB_OTG_FS) || defined(USB)
01265 /**
01266   * @brief  Get USBx clock source
01267   * @rmtoll CFGR         OTGFSPRE      LL_RCC_GetUSBClockSource\n
01268   *         CFGR         USBPRE        LL_RCC_GetUSBClockSource
01269   * @param  USBx This parameter can be one of the following values:
01270   *         @arg @ref LL_RCC_USB_CLKSOURCE
01271   * @retval Returned value can be one of the following values:
01272   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
01273   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
01274   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
01275   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
01276   *
01277   *         (*) value not defined in all devices
01278   */
01279 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
01280 {
01281   return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
01282 }
01283 #endif /* USB_OTG_FS || USB */
01284
01285 /**
01286   * @brief  Get ADCx clock source
01287   * @rmtoll CFGR         ADCPRE        LL_RCC_GetADCClockSource
01288   * @param  ADCx This parameter can be one of the following values:
01289   *         @arg @ref LL_RCC_ADC_CLKSOURCE
01290   * @retval Returned value can be one of the following values:
01291   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
01292   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
01293   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
01294   *         @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
01295   */
01296 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
01297 {
01298   return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
01299 }
01300
01301 /**
01302   * @}
01303   */
01304
01305 /** @defgroup RCC_LL_EF_RTC RTC
01306   * @{
01307   */
01308
01309 /**
01310   * @brief  Set RTC Clock Source
01311   * @note Once the RTC clock source has been selected, it cannot be changed any more unless
01312   *       the Backup domain is reset. The BDRST bit can be used to reset them.
01313   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
01314   * @param  Source This parameter can be one of the following values:
01315   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
01316   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
01317   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
01318   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
01319   * @retval None
01320   */
01321 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
01322 {
01323   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
01324 }
01325
01326 /**
01327   * @brief  Get RTC Clock Source
01328   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
01329   * @retval Returned value can be one of the following values:
01330   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
01331   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
01332   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
01333   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
01334   */
01335 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
01336 {
01337   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
01338 }
01339
01340 /**
01341   * @brief  Enable RTC
01342   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
01343   * @retval None
01344   */
01345 __STATIC_INLINE void LL_RCC_EnableRTC(void)
01346 {
01347   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
01348 }
01349
01350 /**
01351   * @brief  Disable RTC
01352   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
01353   * @retval None
01354   */
01355 __STATIC_INLINE void LL_RCC_DisableRTC(void)
01356 {
01357   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
01358 }
01359
01360 /**
01361   * @brief  Check if RTC has been enabled or not
01362   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
01363   * @retval State of bit (1 or 0).
01364   */
01365 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
01366 {
01367   return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
01368 }
01369
01370 /**
01371   * @brief  Force the Backup domain reset
01372   * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
01373   * @retval None
01374   */
01375 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
01376 {
01377   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
01378 }
01379
01380 /**
01381   * @brief  Release the Backup domain reset
01382   * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
01383   * @retval None
01384   */
01385 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
01386 {
01387   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
01388 }
01389
01390 /**
01391   * @}
01392   */
01393
01394 /** @defgroup RCC_LL_EF_PLL PLL
01395   * @{
01396   */
01397
01398 /**
01399   * @brief  Enable PLL
01400   * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
01401   * @retval None
01402   */
01403 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
01404 {
01405   SET_BIT(RCC->CR, RCC_CR_PLLON);
01406 }
01407
01408 /**
01409   * @brief  Disable PLL
01410   * @note Cannot be disabled if the PLL clock is used as the system clock
01411   * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
01412   * @retval None
01413   */
01414 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
01415 {
01416   CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
01417 }
01418
01419 /**
01420   * @brief  Check if PLL Ready
01421   * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
01422   * @retval State of bit (1 or 0).
01423   */
01424 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
01425 {
01426   return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
01427 }
01428
01429 /**
01430   * @brief  Configure PLL used for SYSCLK Domain
01431   * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
01432   *         CFGR         PLLXTPRE      LL_RCC_PLL_ConfigDomain_SYS\n
01433   *         CFGR         PLLMULL       LL_RCC_PLL_ConfigDomain_SYS\n
01434   *         CFGR2        PREDIV1       LL_RCC_PLL_ConfigDomain_SYS\n
01435   *         CFGR2        PREDIV1SRC    LL_RCC_PLL_ConfigDomain_SYS
01436   * @param  Source This parameter can be one of the following values:
01437   *         @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
01438   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
01439   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
01440   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
01441   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
01442   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
01443   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
01444   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
01445   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
01446   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
01447   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
01448   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
01449   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
01450   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
01451   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
01452   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
01453   *         @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
01454   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
01455   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
01456   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
01457   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
01458   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
01459   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
01460   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
01461   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
01462   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
01463   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
01464   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
01465   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
01466   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
01467   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
01468   *         @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
01469   *
01470   *         (*) value not defined in all devices
01471   * @param  PLLMul This parameter can be one of the following values:
01472   *         @arg @ref LL_RCC_PLL_MUL_2 (*)
01473   *         @arg @ref LL_RCC_PLL_MUL_3 (*)
01474   *         @arg @ref LL_RCC_PLL_MUL_4
01475   *         @arg @ref LL_RCC_PLL_MUL_5
01476   *         @arg @ref LL_RCC_PLL_MUL_6
01477   *         @arg @ref LL_RCC_PLL_MUL_7
01478   *         @arg @ref LL_RCC_PLL_MUL_8
01479   *         @arg @ref LL_RCC_PLL_MUL_9
01480   *         @arg @ref LL_RCC_PLL_MUL_6_5 (*)
01481   *         @arg @ref LL_RCC_PLL_MUL_10 (*)
01482   *         @arg @ref LL_RCC_PLL_MUL_11 (*)
01483   *         @arg @ref LL_RCC_PLL_MUL_12 (*)
01484   *         @arg @ref LL_RCC_PLL_MUL_13 (*)
01485   *         @arg @ref LL_RCC_PLL_MUL_14 (*)
01486   *         @arg @ref LL_RCC_PLL_MUL_15 (*)
01487   *         @arg @ref LL_RCC_PLL_MUL_16 (*)
01488   *
01489   *         (*) value not defined in all devices
01490   * @retval None
01491   */
01492 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
01493 {
01494   MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL,
01495              (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul);
01496 #if defined(RCC_CFGR2_PREDIV1)
01497 #if defined(RCC_CFGR2_PREDIV1SRC)
01498   MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC),
01499              (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
01500 #else
01501   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1));
01502 #endif /*RCC_CFGR2_PREDIV1SRC*/
01503 #endif /*RCC_CFGR2_PREDIV1*/
01504 }
01505
01506 /**
01507   * @brief  Get the oscillator used as PLL clock source.
01508   * @rmtoll CFGR         PLLSRC        LL_RCC_PLL_GetMainSource\n
01509   *         CFGR2        PREDIV1SRC    LL_RCC_PLL_GetMainSource
01510   * @retval Returned value can be one of the following values:
01511   *         @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
01512   *         @arg @ref LL_RCC_PLLSOURCE_HSE
01513   *         @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
01514   *
01515   *         (*) value not defined in all devices
01516   */
01517 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
01518 {
01519 #if defined(RCC_CFGR2_PREDIV1SRC)
01520   register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC);
01521   register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U);
01522   return (uint32_t)(pllsrc | predivsrc);
01523 #else
01524   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
01525 #endif /*RCC_CFGR2_PREDIV1SRC*/
01526 }
01527
01528 /**
01529   * @brief  Get PLL multiplication Factor
01530   * @rmtoll CFGR         PLLMULL       LL_RCC_PLL_GetMultiplicator
01531   * @retval Returned value can be one of the following values:
01532   *         @arg @ref LL_RCC_PLL_MUL_2 (*)
01533   *         @arg @ref LL_RCC_PLL_MUL_3 (*)
01534   *         @arg @ref LL_RCC_PLL_MUL_4
01535   *         @arg @ref LL_RCC_PLL_MUL_5
01536   *         @arg @ref LL_RCC_PLL_MUL_6
01537   *         @arg @ref LL_RCC_PLL_MUL_7
01538   *         @arg @ref LL_RCC_PLL_MUL_8
01539   *         @arg @ref LL_RCC_PLL_MUL_9
01540   *         @arg @ref LL_RCC_PLL_MUL_6_5 (*)
01541   *         @arg @ref LL_RCC_PLL_MUL_10 (*)
01542   *         @arg @ref LL_RCC_PLL_MUL_11 (*)
01543   *         @arg @ref LL_RCC_PLL_MUL_12 (*)
01544   *         @arg @ref LL_RCC_PLL_MUL_13 (*)
01545   *         @arg @ref LL_RCC_PLL_MUL_14 (*)
01546   *         @arg @ref LL_RCC_PLL_MUL_15 (*)
01547   *         @arg @ref LL_RCC_PLL_MUL_16 (*)
01548   *
01549   *         (*) value not defined in all devices
01550   */
01551 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
01552 {
01553   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL));
01554 }
01555
01556 /**
01557   * @brief  Get PREDIV1 division factor for the main PLL
01558   * @note They can be written only when the PLL is disabled
01559   * @rmtoll CFGR2        PREDIV1       LL_RCC_PLL_GetPrediv\n
01560   *         CFGR2        PLLXTPRE      LL_RCC_PLL_GetPrediv
01561   * @retval Returned value can be one of the following values:
01562   *         @arg @ref LL_RCC_PREDIV_DIV_1
01563   *         @arg @ref LL_RCC_PREDIV_DIV_2
01564   *         @arg @ref LL_RCC_PREDIV_DIV_3 (*)
01565   *         @arg @ref LL_RCC_PREDIV_DIV_4 (*)
01566   *         @arg @ref LL_RCC_PREDIV_DIV_5 (*)
01567   *         @arg @ref LL_RCC_PREDIV_DIV_6 (*)
01568   *         @arg @ref LL_RCC_PREDIV_DIV_7 (*)
01569   *         @arg @ref LL_RCC_PREDIV_DIV_8 (*)
01570   *         @arg @ref LL_RCC_PREDIV_DIV_9 (*)
01571   *         @arg @ref LL_RCC_PREDIV_DIV_10 (*)
01572   *         @arg @ref LL_RCC_PREDIV_DIV_11 (*)
01573   *         @arg @ref LL_RCC_PREDIV_DIV_12 (*)
01574   *         @arg @ref LL_RCC_PREDIV_DIV_13 (*)
01575   *         @arg @ref LL_RCC_PREDIV_DIV_14 (*)
01576   *         @arg @ref LL_RCC_PREDIV_DIV_15 (*)
01577   *         @arg @ref LL_RCC_PREDIV_DIV_16 (*)
01578   *
01579   *         (*) value not defined in all devices
01580   */
01581 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
01582 {
01583 #if defined(RCC_CFGR2_PREDIV1)
01584   return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));
01585 #else
01586   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE));
01587 #endif /*RCC_CFGR2_PREDIV1*/
01588 }
01589
01590 /**
01591   * @}
01592   */
01593
01594 #if defined(RCC_PLLI2S_SUPPORT)
01595 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
01596   * @{
01597   */
01598
01599 /**
01600   * @brief  Enable PLLI2S
01601   * @rmtoll CR           PLL3ON        LL_RCC_PLLI2S_Enable
01602   * @retval None
01603   */
01604 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
01605 {
01606   SET_BIT(RCC->CR, RCC_CR_PLL3ON);
01607 }
01608
01609 /**
01610   * @brief  Disable PLLI2S
01611   * @rmtoll CR           PLL3ON        LL_RCC_PLLI2S_Disable
01612   * @retval None
01613   */
01614 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
01615 {
01616   CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
01617 }
01618
01619 /**
01620   * @brief  Check if PLLI2S Ready
01621   * @rmtoll CR           PLL3RDY       LL_RCC_PLLI2S_IsReady
01622   * @retval State of bit (1 or 0).
01623   */
01624 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
01625 {
01626   return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY));
01627 }
01628
01629 /**
01630   * @brief  Configure PLLI2S used for I2S Domain
01631   * @rmtoll CFGR2        PREDIV2       LL_RCC_PLL_ConfigDomain_PLLI2S\n
01632   *         CFGR2        PLL3MUL       LL_RCC_PLL_ConfigDomain_PLLI2S
01633   * @param  Divider This parameter can be one of the following values:
01634   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
01635   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
01636   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
01637   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
01638   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
01639   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
01640   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
01641   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
01642   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
01643   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
01644   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
01645   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
01646   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
01647   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
01648   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
01649   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
01650   * @param  Multiplicator This parameter can be one of the following values:
01651   *         @arg @ref LL_RCC_PLLI2S_MUL_8
01652   *         @arg @ref LL_RCC_PLLI2S_MUL_9
01653   *         @arg @ref LL_RCC_PLLI2S_MUL_10
01654   *         @arg @ref LL_RCC_PLLI2S_MUL_11
01655   *         @arg @ref LL_RCC_PLLI2S_MUL_12
01656   *         @arg @ref LL_RCC_PLLI2S_MUL_13
01657   *         @arg @ref LL_RCC_PLLI2S_MUL_14
01658   *         @arg @ref LL_RCC_PLLI2S_MUL_16
01659   *         @arg @ref LL_RCC_PLLI2S_MUL_20
01660   * @retval None
01661   */
01662 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator)
01663 {
01664   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator);
01665 }
01666
01667 /**
01668   * @brief  Get PLLI2S Multiplication Factor
01669   * @rmtoll CFGR2        PLL3MUL       LL_RCC_PLLI2S_GetMultiplicator
01670   * @retval Returned value can be one of the following values:
01671   *         @arg @ref LL_RCC_PLLI2S_MUL_8
01672   *         @arg @ref LL_RCC_PLLI2S_MUL_9
01673   *         @arg @ref LL_RCC_PLLI2S_MUL_10
01674   *         @arg @ref LL_RCC_PLLI2S_MUL_11
01675   *         @arg @ref LL_RCC_PLLI2S_MUL_12
01676   *         @arg @ref LL_RCC_PLLI2S_MUL_13
01677   *         @arg @ref LL_RCC_PLLI2S_MUL_14
01678   *         @arg @ref LL_RCC_PLLI2S_MUL_16
01679   *         @arg @ref LL_RCC_PLLI2S_MUL_20
01680   */
01681 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void)
01682 {
01683   return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL));
01684 }
01685
01686 /**
01687   * @}
01688   */
01689 #endif /* RCC_PLLI2S_SUPPORT */
01690
01691 #if defined(RCC_PLL2_SUPPORT)
01692 /** @defgroup RCC_LL_EF_PLL2 PLL2
01693   * @{
01694   */
01695
01696 /**
01697   * @brief  Enable PLL2
01698   * @rmtoll CR           PLL2ON        LL_RCC_PLL2_Enable
01699   * @retval None
01700   */
01701 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
01702 {
01703   SET_BIT(RCC->CR, RCC_CR_PLL2ON);
01704 }
01705
01706 /**
01707   * @brief  Disable PLL2
01708   * @rmtoll CR           PLL2ON        LL_RCC_PLL2_Disable
01709   * @retval None
01710   */
01711 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
01712 {
01713   CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
01714 }
01715
01716 /**
01717   * @brief  Check if PLL2 Ready
01718   * @rmtoll CR           PLL2RDY       LL_RCC_PLL2_IsReady
01719   * @retval State of bit (1 or 0).
01720   */
01721 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
01722 {
01723   return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY));
01724 }
01725
01726 /**
01727   * @brief  Configure PLL2 used for PLL2 Domain
01728   * @rmtoll CFGR2        PREDIV2       LL_RCC_PLL_ConfigDomain_PLL2\n
01729   *         CFGR2        PLL2MUL       LL_RCC_PLL_ConfigDomain_PLL2
01730   * @param  Divider This parameter can be one of the following values:
01731   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
01732   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
01733   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
01734   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
01735   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
01736   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
01737   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
01738   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
01739   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
01740   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
01741   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
01742   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
01743   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
01744   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
01745   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
01746   *         @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
01747   * @param  Multiplicator This parameter can be one of the following values:
01748   *         @arg @ref LL_RCC_PLL2_MUL_8
01749   *         @arg @ref LL_RCC_PLL2_MUL_9
01750   *         @arg @ref LL_RCC_PLL2_MUL_10
01751   *         @arg @ref LL_RCC_PLL2_MUL_11
01752   *         @arg @ref LL_RCC_PLL2_MUL_12
01753   *         @arg @ref LL_RCC_PLL2_MUL_13
01754   *         @arg @ref LL_RCC_PLL2_MUL_14
01755   *         @arg @ref LL_RCC_PLL2_MUL_16
01756   *         @arg @ref LL_RCC_PLL2_MUL_20
01757   * @retval None
01758   */
01759 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator)
01760 {
01761   MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator);
01762 }
01763
01764 /**
01765   * @brief  Get PLL2 Multiplication Factor
01766   * @rmtoll CFGR2        PLL2MUL       LL_RCC_PLL2_GetMultiplicator
01767   * @retval Returned value can be one of the following values:
01768   *         @arg @ref LL_RCC_PLL2_MUL_8
01769   *         @arg @ref LL_RCC_PLL2_MUL_9
01770   *         @arg @ref LL_RCC_PLL2_MUL_10
01771   *         @arg @ref LL_RCC_PLL2_MUL_11
01772   *         @arg @ref LL_RCC_PLL2_MUL_12
01773   *         @arg @ref LL_RCC_PLL2_MUL_13
01774   *         @arg @ref LL_RCC_PLL2_MUL_14
01775   *         @arg @ref LL_RCC_PLL2_MUL_16
01776   *         @arg @ref LL_RCC_PLL2_MUL_20
01777   */
01778 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void)
01779 {
01780   return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL));
01781 }
01782
01783 /**
01784   * @}
01785   */
01786 #endif /* RCC_PLL2_SUPPORT */
01787
01788 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
01789   * @{
01790   */
01791
01792 /**
01793   * @brief  Clear LSI ready interrupt flag
01794   * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
01795   * @retval None
01796   */
01797 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
01798 {
01799   SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
01800 }
01801
01802 /**
01803   * @brief  Clear LSE ready interrupt flag
01804   * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY
01805   * @retval None
01806   */
01807 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
01808 {
01809   SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
01810 }
01811
01812 /**
01813   * @brief  Clear HSI ready interrupt flag
01814   * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
01815   * @retval None
01816   */
01817 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
01818 {
01819   SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
01820 }
01821
01822 /**
01823   * @brief  Clear HSE ready interrupt flag
01824   * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY
01825   * @retval None
01826   */
01827 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
01828 {
01829   SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
01830 }
01831
01832 /**
01833   * @brief  Clear PLL ready interrupt flag
01834   * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
01835   * @retval None
01836   */
01837 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
01838 {
01839   SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
01840 }
01841
01842 #if defined(RCC_PLLI2S_SUPPORT)
01843 /**
01844   * @brief  Clear PLLI2S ready interrupt flag
01845   * @rmtoll CIR          PLL3RDYC      LL_RCC_ClearFlag_PLLI2SRDY
01846   * @retval None
01847   */
01848 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
01849 {
01850   SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC);
01851 }
01852 #endif /* RCC_PLLI2S_SUPPORT */
01853
01854 #if defined(RCC_PLL2_SUPPORT)
01855 /**
01856   * @brief  Clear PLL2 ready interrupt flag
01857   * @rmtoll CIR          PLL2RDYC      LL_RCC_ClearFlag_PLL2RDY
01858   * @retval None
01859   */
01860 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
01861 {
01862   SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC);
01863 }
01864 #endif /* RCC_PLL2_SUPPORT */
01865
01866 /**
01867   * @brief  Clear Clock security system interrupt flag
01868   * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS
01869   * @retval None
01870   */
01871 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
01872 {
01873   SET_BIT(RCC->CIR, RCC_CIR_CSSC);
01874 }
01875
01876 /**
01877   * @brief  Check if LSI ready interrupt occurred or not
01878   * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
01879   * @retval State of bit (1 or 0).
01880   */
01881 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
01882 {
01883   return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
01884 }
01885
01886 /**
01887   * @brief  Check if LSE ready interrupt occurred or not
01888   * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
01889   * @retval State of bit (1 or 0).
01890   */
01891 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
01892 {
01893   return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
01894 }
01895
01896 /**
01897   * @brief  Check if HSI ready interrupt occurred or not
01898   * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
01899   * @retval State of bit (1 or 0).
01900   */
01901 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
01902 {
01903   return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
01904 }
01905
01906 /**
01907   * @brief  Check if HSE ready interrupt occurred or not
01908   * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
01909   * @retval State of bit (1 or 0).
01910   */
01911 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
01912 {
01913   return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
01914 }
01915
01916 /**
01917   * @brief  Check if PLL ready interrupt occurred or not
01918   * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
01919   * @retval State of bit (1 or 0).
01920   */
01921 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
01922 {
01923   return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
01924 }
01925
01926 #if defined(RCC_PLLI2S_SUPPORT)
01927 /**
01928   * @brief  Check if PLLI2S ready interrupt occurred or not
01929   * @rmtoll CIR          PLL3RDYF      LL_RCC_IsActiveFlag_PLLI2SRDY
01930   * @retval State of bit (1 or 0).
01931   */
01932 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
01933 {
01934   return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF));
01935 }
01936 #endif /* RCC_PLLI2S_SUPPORT */
01937
01938 #if defined(RCC_PLL2_SUPPORT)
01939 /**
01940   * @brief  Check if PLL2 ready interrupt occurred or not
01941   * @rmtoll CIR          PLL2RDYF      LL_RCC_IsActiveFlag_PLL2RDY
01942   * @retval State of bit (1 or 0).
01943   */
01944 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
01945 {
01946   return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF));
01947 }
01948 #endif /* RCC_PLL2_SUPPORT */
01949
01950 /**
01951   * @brief  Check if Clock security system interrupt occurred or not
01952   * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS
01953   * @retval State of bit (1 or 0).
01954   */
01955 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
01956 {
01957   return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
01958 }
01959
01960 /**
01961   * @brief  Check if RCC flag Independent Watchdog reset is set or not.
01962   * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
01963   * @retval State of bit (1 or 0).
01964   */
01965 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
01966 {
01967   return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
01968 }
01969
01970 /**
01971   * @brief  Check if RCC flag Low Power reset is set or not.
01972   * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
01973   * @retval State of bit (1 or 0).
01974   */
01975 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
01976 {
01977   return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
01978 }
01979
01980 /**
01981   * @brief  Check if RCC flag Pin reset is set or not.
01982   * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
01983   * @retval State of bit (1 or 0).
01984   */
01985 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
01986 {
01987   return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
01988 }
01989
01990 /**
01991   * @brief  Check if RCC flag POR/PDR reset is set or not.
01992   * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
01993   * @retval State of bit (1 or 0).
01994   */
01995 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
01996 {
01997   return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
01998 }
01999
02000 /**
02001   * @brief  Check if RCC flag Software reset is set or not.
02002   * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
02003   * @retval State of bit (1 or 0).
02004   */
02005 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
02006 {
02007   return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
02008 }
02009
02010 /**
02011   * @brief  Check if RCC flag Window Watchdog reset is set or not.
02012   * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
02013   * @retval State of bit (1 or 0).
02014   */
02015 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
02016 {
02017   return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
02018 }
02019
02020 /**
02021   * @brief  Set RMVF bit to clear the reset flags.
02022   * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
02023   * @retval None
02024   */
02025 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
02026 {
02027   SET_BIT(RCC->CSR, RCC_CSR_RMVF);
02028 }
02029
02030 /**
02031   * @}
02032   */
02033
02034 /** @defgroup RCC_LL_EF_IT_Management IT Management
02035   * @{
02036   */
02037
02038 /**
02039   * @brief  Enable LSI ready interrupt
02040   * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
02041   * @retval None
02042   */
02043 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
02044 {
02045   SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
02046 }
02047
02048 /**
02049   * @brief  Enable LSE ready interrupt
02050   * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY
02051   * @retval None
02052   */
02053 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
02054 {
02055   SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
02056 }
02057
02058 /**
02059   * @brief  Enable HSI ready interrupt
02060   * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
02061   * @retval None
02062   */
02063 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
02064 {
02065   SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
02066 }
02067
02068 /**
02069   * @brief  Enable HSE ready interrupt
02070   * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY
02071   * @retval None
02072   */
02073 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
02074 {
02075   SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
02076 }
02077
02078 /**
02079   * @brief  Enable PLL ready interrupt
02080   * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
02081   * @retval None
02082   */
02083 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
02084 {
02085   SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
02086 }
02087
02088 #if defined(RCC_PLLI2S_SUPPORT)
02089 /**
02090   * @brief  Enable PLLI2S ready interrupt
02091   * @rmtoll CIR          PLL3RDYIE     LL_RCC_EnableIT_PLLI2SRDY
02092   * @retval None
02093   */
02094 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
02095 {
02096   SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
02097 }
02098 #endif /* RCC_PLLI2S_SUPPORT */
02099
02100 #if defined(RCC_PLL2_SUPPORT)
02101 /**
02102   * @brief  Enable PLL2 ready interrupt
02103   * @rmtoll CIR          PLL2RDYIE     LL_RCC_EnableIT_PLL2RDY
02104   * @retval None
02105   */
02106 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
02107 {
02108   SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
02109 }
02110 #endif /* RCC_PLL2_SUPPORT */
02111
02112 /**
02113   * @brief  Disable LSI ready interrupt
02114   * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
02115   * @retval None
02116   */
02117 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
02118 {
02119   CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
02120 }
02121
02122 /**
02123   * @brief  Disable LSE ready interrupt
02124   * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY
02125   * @retval None
02126   */
02127 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
02128 {
02129   CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
02130 }
02131
02132 /**
02133   * @brief  Disable HSI ready interrupt
02134   * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
02135   * @retval None
02136   */
02137 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
02138 {
02139   CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
02140 }
02141
02142 /**
02143   * @brief  Disable HSE ready interrupt
02144   * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY
02145   * @retval None
02146   */
02147 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
02148 {
02149   CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
02150 }
02151
02152 /**
02153   * @brief  Disable PLL ready interrupt
02154   * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
02155   * @retval None
02156   */
02157 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
02158 {
02159   CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
02160 }
02161
02162 #if defined(RCC_PLLI2S_SUPPORT)
02163 /**
02164   * @brief  Disable PLLI2S ready interrupt
02165   * @rmtoll CIR          PLL3RDYIE     LL_RCC_DisableIT_PLLI2SRDY
02166   * @retval None
02167   */
02168 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
02169 {
02170   CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
02171 }
02172 #endif /* RCC_PLLI2S_SUPPORT */
02173
02174 #if defined(RCC_PLL2_SUPPORT)
02175 /**
02176   * @brief  Disable PLL2 ready interrupt
02177   * @rmtoll CIR          PLL2RDYIE     LL_RCC_DisableIT_PLL2RDY
02178   * @retval None
02179   */
02180 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
02181 {
02182   CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
02183 }
02184 #endif /* RCC_PLL2_SUPPORT */
02185
02186 /**
02187   * @brief  Checks if LSI ready interrupt source is enabled or disabled.
02188   * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
02189   * @retval State of bit (1 or 0).
02190   */
02191 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
02192 {
02193   return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
02194 }
02195
02196 /**
02197   * @brief  Checks if LSE ready interrupt source is enabled or disabled.
02198   * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
02199   * @retval State of bit (1 or 0).
02200   */
02201 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
02202 {
02203   return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
02204 }
02205
02206 /**
02207   * @brief  Checks if HSI ready interrupt source is enabled or disabled.
02208   * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
02209   * @retval State of bit (1 or 0).
02210   */
02211 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
02212 {
02213   return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
02214 }
02215
02216 /**
02217   * @brief  Checks if HSE ready interrupt source is enabled or disabled.
02218   * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
02219   * @retval State of bit (1 or 0).
02220   */
02221 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
02222 {
02223   return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
02224 }
02225
02226 /**
02227   * @brief  Checks if PLL ready interrupt source is enabled or disabled.
02228   * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
02229   * @retval State of bit (1 or 0).
02230   */
02231 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
02232 {
02233   return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
02234 }
02235
02236 #if defined(RCC_PLLI2S_SUPPORT)
02237 /**
02238   * @brief  Checks if PLLI2S ready interrupt source is enabled or disabled.
02239   * @rmtoll CIR          PLL3RDYIE     LL_RCC_IsEnabledIT_PLLI2SRDY
02240   * @retval State of bit (1 or 0).
02241   */
02242 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
02243 {
02244   return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE));
02245 }
02246 #endif /* RCC_PLLI2S_SUPPORT */
02247
02248 #if defined(RCC_PLL2_SUPPORT)
02249 /**
02250   * @brief  Checks if PLL2 ready interrupt source is enabled or disabled.
02251   * @rmtoll CIR          PLL2RDYIE     LL_RCC_IsEnabledIT_PLL2RDY
02252   * @retval State of bit (1 or 0).
02253   */
02254 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
02255 {
02256   return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE));
02257 }
02258 #endif /* RCC_PLL2_SUPPORT */
02259
02260 /**
02261   * @}
02262   */
02263
02264 #if defined(USE_FULL_LL_DRIVER)
02265 /** @defgroup RCC_LL_EF_Init De-initialization function
02266   * @{
02267   */
02268 ErrorStatus LL_RCC_DeInit(void);
02269 /**
02270   * @}
02271   */
02272
02273 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
02274   * @{
02275   */
02276 void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
02277 #if defined(RCC_CFGR2_I2S2SRC)
02278 uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
02279 #endif /* RCC_CFGR2_I2S2SRC */
02280 #if defined(USB_OTG_FS) || defined(USB)
02281 uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
02282 #endif /* USB_OTG_FS || USB */
02283 uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
02284 /**
02285   * @}
02286   */
02287 #endif /* USE_FULL_LL_DRIVER */
02288
02289 /**
02290   * @}
02291   */
02292
02293 /**
02294   * @}
02295   */
02296
02297 #endif /* RCC */
02298
02299 /**
02300   * @}
02301   */
02302
02303 #ifdef __cplusplus
02304 }
02305 #endif
02306
02307 #endif /* __STM32F1xx_LL_RCC_H */
02308
02309 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_spi.c Source File

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stm32f1xx_ll_spi.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_spi.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   SPI LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_spi.h"
00041 #include "stm32f1xx_ll_bus.h"
00042 #include "stm32f1xx_ll_rcc.h"
00043
00044 #ifdef  USE_FULL_ASSERT
00045 #include "stm32_assert.h"
00046 #else
00047 #define assert_param(expr) ((void)0U)
00048 #endif
00049
00050 /** @addtogroup STM32F1xx_LL_Driver
00051   * @{
00052   */
00053
00054 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
00055
00056 /** @addtogroup SPI_LL
00057   * @{
00058   */
00059
00060 /* Private types -------------------------------------------------------------*/
00061 /* Private variables ---------------------------------------------------------*/
00062
00063 /* Private constants ---------------------------------------------------------*/
00064 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
00065   * @{
00066   */
00067 /* SPI registers Masks */
00068 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
00069                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
00070                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_DFF    | \
00071                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
00072                                             SPI_CR1_BIDIMODE)
00073 /**
00074   * @}
00075   */
00076
00077 /* Private macros ------------------------------------------------------------*/
00078 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
00079   * @{
00080   */
00081 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
00082                                               || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
00083                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
00084                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
00085
00086 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
00087                                 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
00088
00089 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
00090                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
00091
00092 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
00093                                     || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
00094
00095 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
00096                                  || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
00097
00098 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
00099                                || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
00100                                || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
00101
00102 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
00103                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
00104                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
00105                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
00106                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
00107                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
00108                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
00109                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
00110
00111 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
00112                                     || ((__VALUE__) == LL_SPI_MSB_FIRST))
00113
00114 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
00115                                           || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
00116
00117 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
00118
00119 /**
00120   * @}
00121   */
00122
00123 /* Private function prototypes -----------------------------------------------*/
00124
00125 /* Exported functions --------------------------------------------------------*/
00126 /** @addtogroup SPI_LL_Exported_Functions
00127   * @{
00128   */
00129
00130 /** @addtogroup SPI_LL_EF_Init
00131   * @{
00132   */
00133
00134 /**
00135   * @brief  De-initialize the SPI registers to their default reset values.
00136   * @param  SPIx SPI Instance
00137   * @retval An ErrorStatus enumeration value:
00138   *          - SUCCESS: SPI registers are de-initialized
00139   *          - ERROR: SPI registers are not de-initialized
00140   */
00141 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
00142 {
00143   ErrorStatus status = ERROR;
00144
00145   /* Check the parameters */
00146   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00147
00148 #if defined(SPI1)
00149   if (SPIx == SPI1)
00150   {
00151     /* Force reset of SPI clock */
00152     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
00153
00154     /* Release reset of SPI clock */
00155     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
00156
00157     status = SUCCESS;
00158   }
00159 #endif /* SPI1 */
00160 #if defined(SPI2)
00161   if (SPIx == SPI2)
00162   {
00163     /* Force reset of SPI clock */
00164     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
00165
00166     /* Release reset of SPI clock */
00167     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
00168
00169     status = SUCCESS;
00170   }
00171 #endif /* SPI2 */
00172 #if defined(SPI3)
00173   if (SPIx == SPI3)
00174   {
00175     /* Force reset of SPI clock */
00176     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
00177
00178     /* Release reset of SPI clock */
00179     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
00180
00181     status = SUCCESS;
00182   }
00183 #endif /* SPI3 */
00184
00185   return status;
00186 }
00187
00188 /**
00189   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
00190   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
00191   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00192   * @param  SPIx SPI Instance
00193   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00194   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
00195   */
00196 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
00197 {
00198   ErrorStatus status = ERROR;
00199
00200   /* Check the SPI Instance SPIx*/
00201   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
00202
00203   /* Check the SPI parameters from SPI_InitStruct*/
00204   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
00205   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
00206   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
00207   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
00208   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
00209   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
00210   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
00211   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
00212   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
00213
00214   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
00215   {
00216     /*---------------------------- SPIx CR1 Configuration ------------------------
00217      * Configure SPIx CR1 with parameters:
00218      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
00219      * - Master/Slave Mode:  SPI_CR1_MSTR bit
00220      * - DataWidth:          SPI_CR1_DFF bit
00221      * - ClockPolarity:      SPI_CR1_CPOL bit
00222      * - ClockPhase:         SPI_CR1_CPHA bit
00223      * - NSS management:     SPI_CR1_SSM bit
00224      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
00225      * - BitOrder:           SPI_CR1_LSBFIRST bit
00226      * - CRCCalculation:     SPI_CR1_CRCEN bit
00227      */
00228     MODIFY_REG(SPIx->CR1,
00229                SPI_CR1_CLEAR_MASK,
00230                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
00231                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
00232                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
00233                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
00234
00235     /*---------------------------- SPIx CR2 Configuration ------------------------
00236      * Configure SPIx CR2 with parameters:
00237      * - NSS management:     SSOE bit
00238      */
00239     MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
00240
00241     /*---------------------------- SPIx CRCPR Configuration ----------------------
00242      * Configure SPIx CRCPR with parameters:
00243      * - CRCPoly:            CRCPOLY[15:0] bits
00244      */
00245     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
00246     {
00247       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
00248       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
00249     }
00250     status = SUCCESS;
00251   }
00252
00253 #if defined (SPI_I2S_SUPPORT)
00254   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
00255   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
00256 #endif /* SPI_I2S_SUPPORT */
00257   return status;
00258 }
00259
00260 /**
00261   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
00262   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
00263   * whose fields will be set to default values.
00264   * @retval None
00265   */
00266 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
00267 {
00268   /* Set SPI_InitStruct fields to default values */
00269   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
00270   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
00271   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
00272   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
00273   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
00274   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
00275   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
00276   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
00277   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
00278   SPI_InitStruct->CRCPoly           = 7U;
00279 }
00280
00281 /**
00282   * @}
00283   */
00284
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
00294
00295 /**
00296   * @}
00297   */
00298
00299 #endif /* USE_FULL_LL_DRIVER */
00300
00301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_spi.h Source File

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stm32f1xx_ll_spi.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_spi.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of SPI LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_SPI_H
00040 #define __STM32F1xx_LL_SPI_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
00054
00055 /** @defgroup SPI_LL SPI
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private macros ------------------------------------------------------------*/
00062
00063 /* Exported types ------------------------------------------------------------*/
00064 #if defined(USE_FULL_LL_DRIVER)
00065 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
00066   * @{
00067   */
00068
00069 /**
00070   * @brief  SPI Init structures definition
00071   */
00072 typedef struct
00073 {
00074   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
00075                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
00076
00077                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
00078
00079   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
00080                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
00081
00082                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
00083
00084   uint32_t DataWidth;               /*!< Specifies the SPI data width.
00085                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
00086
00087                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
00088
00089   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
00090                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
00091
00092                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
00093
00094   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
00095                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
00096
00097                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
00098
00099   uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
00100                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
00101
00102                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
00103
00104   uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
00105                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
00106                                          @note The communication clock is derived from the master clock. The slave clock does not need to be set.
00107
00108                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
00109
00110   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
00111                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
00112
00113                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
00114
00115   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
00116                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
00117
00118                                          This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
00119
00120   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
00121                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
00122
00123                                          This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
00124
00125 } LL_SPI_InitTypeDef;
00126
00127 /**
00128   * @}
00129   */
00130 #endif /* USE_FULL_LL_DRIVER */
00131
00132 /* Exported constants --------------------------------------------------------*/
00133 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
00134   * @{
00135   */
00136
00137 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
00138   * @brief    Flags defines which can be used with LL_SPI_ReadReg function
00139   * @{
00140   */
00141 #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
00142 #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
00143 #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
00144 #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
00145 #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
00146 #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
00147 #define LL_SPI_SR_FRE                      SPI_SR_FRE                /*!< TI mode frame format error flag  */
00148 /**
00149   * @}
00150   */
00151
00152 /** @defgroup SPI_LL_EC_IT IT Defines
00153   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
00154   * @{
00155   */
00156 #define LL_SPI_CR2_RXNEIE                  SPI_CR2_RXNEIE            /*!< Rx buffer not empty interrupt enable */
00157 #define LL_SPI_CR2_TXEIE                   SPI_CR2_TXEIE             /*!< Tx buffer empty interrupt enable     */
00158 #define LL_SPI_CR2_ERRIE                   SPI_CR2_ERRIE             /*!< Error interrupt enable               */
00159 /**
00160   * @}
00161   */
00162
00163 /** @defgroup SPI_LL_EC_MODE Operation Mode
00164   * @{
00165   */
00166 #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
00167 #define LL_SPI_MODE_SLAVE                  0x00000000U                    /*!< Slave configuration   */
00168 /**
00169   * @}
00170   */
00171
00172
00173 /** @defgroup SPI_LL_EC_PHASE Clock Phase
00174   * @{
00175   */
00176 #define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
00177 #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
00178 /**
00179   * @}
00180   */
00181
00182 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
00183   * @{
00184   */
00185 #define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
00186 #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
00187 /**
00188   * @}
00189   */
00190
00191 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
00192   * @{
00193   */
00194 #define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
00195 #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
00196 #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
00197 #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
00198 #define LL_SPI_BAUDRATEPRESCALER_DIV32     (SPI_CR1_BR_2)                                 /*!< BaudRate control equal to fPCLK/32  */
00199 #define LL_SPI_BAUDRATEPRESCALER_DIV64     (SPI_CR1_BR_2 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/64  */
00200 #define LL_SPI_BAUDRATEPRESCALER_DIV128    (SPI_CR1_BR_2 | SPI_CR1_BR_1)                  /*!< BaudRate control equal to fPCLK/128 */
00201 #define LL_SPI_BAUDRATEPRESCALER_DIV256    (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)   /*!< BaudRate control equal to fPCLK/256 */
00202 /**
00203   * @}
00204   */
00205
00206 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
00207   * @{
00208   */
00209 #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
00210 #define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
00211 /**
00212   * @}
00213   */
00214
00215 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
00216   * @{
00217   */
00218 #define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
00219 #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
00220 #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
00221 #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
00222 /**
00223   * @}
00224   */
00225
00226 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
00227   * @{
00228   */
00229 #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
00230 #define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
00231 #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
00232 /**
00233   * @}
00234   */
00235
00236 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
00237   * @{
00238   */
00239 #define LL_SPI_DATAWIDTH_8BIT              0x00000000U                       /*!< Data length for SPI transfer:  8 bits */
00240 #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR1_DFF)                     /*!< Data length for SPI transfer:  16 bits */
00241 /**
00242   * @}
00243   */
00244 #if defined(USE_FULL_LL_DRIVER)
00245
00246 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
00247   * @{
00248   */
00249 #define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U                       /*!< CRC calculation disabled */
00250 #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)                   /*!< CRC calculation enabled  */
00251 /**
00252   * @}
00253   */
00254 #endif /* USE_FULL_LL_DRIVER */
00255
00256 /**
00257   * @}
00258   */
00259
00260 /* Exported macro ------------------------------------------------------------*/
00261 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
00262   * @{
00263   */
00264
00265 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
00266   * @{
00267   */
00268
00269 /**
00270   * @brief  Write a value in SPI register
00271   * @param  __INSTANCE__ SPI Instance
00272   * @param  __REG__ Register to be written
00273   * @param  __VALUE__ Value to be written in the register
00274   * @retval None
00275   */
00276 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00277
00278 /**
00279   * @brief  Read a value in SPI register
00280   * @param  __INSTANCE__ SPI Instance
00281   * @param  __REG__ Register to be read
00282   * @retval Register value
00283   */
00284 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00285 /**
00286   * @}
00287   */
00288
00289 /**
00290   * @}
00291   */
00292
00293 /* Exported functions --------------------------------------------------------*/
00294 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
00295   * @{
00296   */
00297
00298 /** @defgroup SPI_LL_EF_Configuration Configuration
00299   * @{
00300   */
00301
00302 /**
00303   * @brief  Enable SPI peripheral
00304   * @rmtoll CR1          SPE           LL_SPI_Enable
00305   * @param  SPIx SPI Instance
00306   * @retval None
00307   */
00308 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
00309 {
00310   SET_BIT(SPIx->CR1, SPI_CR1_SPE);
00311 }
00312
00313 /**
00314   * @brief  Disable SPI peripheral
00315   * @note   When disabling the SPI, follow the procedure described in the Reference Manual.
00316   * @rmtoll CR1          SPE           LL_SPI_Disable
00317   * @param  SPIx SPI Instance
00318   * @retval None
00319   */
00320 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
00321 {
00322   CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
00323 }
00324
00325 /**
00326   * @brief  Check if SPI peripheral is enabled
00327   * @rmtoll CR1          SPE           LL_SPI_IsEnabled
00328   * @param  SPIx SPI Instance
00329   * @retval State of bit (1 or 0).
00330   */
00331 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
00332 {
00333   return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
00334 }
00335
00336 /**
00337   * @brief  Set SPI operation mode to Master or Slave
00338   * @note   This bit should not be changed when communication is ongoing.
00339   * @rmtoll CR1          MSTR          LL_SPI_SetMode\n
00340   *         CR1          SSI           LL_SPI_SetMode
00341   * @param  SPIx SPI Instance
00342   * @param  Mode This parameter can be one of the following values:
00343   *         @arg @ref LL_SPI_MODE_MASTER
00344   *         @arg @ref LL_SPI_MODE_SLAVE
00345   * @retval None
00346   */
00347 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
00348 {
00349   MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
00350 }
00351
00352 /**
00353   * @brief  Get SPI operation mode (Master or Slave)
00354   * @rmtoll CR1          MSTR          LL_SPI_GetMode\n
00355   *         CR1          SSI           LL_SPI_GetMode
00356   * @param  SPIx SPI Instance
00357   * @retval Returned value can be one of the following values:
00358   *         @arg @ref LL_SPI_MODE_MASTER
00359   *         @arg @ref LL_SPI_MODE_SLAVE
00360   */
00361 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
00362 {
00363   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
00364 }
00365
00366
00367 /**
00368   * @brief  Set clock phase
00369   * @note   This bit should not be changed when communication is ongoing.
00370   *         This bit is not used in SPI TI mode.
00371   * @rmtoll CR1          CPHA          LL_SPI_SetClockPhase
00372   * @param  SPIx SPI Instance
00373   * @param  ClockPhase This parameter can be one of the following values:
00374   *         @arg @ref LL_SPI_PHASE_1EDGE
00375   *         @arg @ref LL_SPI_PHASE_2EDGE
00376   * @retval None
00377   */
00378 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
00379 {
00380   MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
00381 }
00382
00383 /**
00384   * @brief  Get clock phase
00385   * @rmtoll CR1          CPHA          LL_SPI_GetClockPhase
00386   * @param  SPIx SPI Instance
00387   * @retval Returned value can be one of the following values:
00388   *         @arg @ref LL_SPI_PHASE_1EDGE
00389   *         @arg @ref LL_SPI_PHASE_2EDGE
00390   */
00391 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
00392 {
00393   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
00394 }
00395
00396 /**
00397   * @brief  Set clock polarity
00398   * @note   This bit should not be changed when communication is ongoing.
00399   *         This bit is not used in SPI TI mode.
00400   * @rmtoll CR1          CPOL          LL_SPI_SetClockPolarity
00401   * @param  SPIx SPI Instance
00402   * @param  ClockPolarity This parameter can be one of the following values:
00403   *         @arg @ref LL_SPI_POLARITY_LOW
00404   *         @arg @ref LL_SPI_POLARITY_HIGH
00405   * @retval None
00406   */
00407 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
00408 {
00409   MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
00410 }
00411
00412 /**
00413   * @brief  Get clock polarity
00414   * @rmtoll CR1          CPOL          LL_SPI_GetClockPolarity
00415   * @param  SPIx SPI Instance
00416   * @retval Returned value can be one of the following values:
00417   *         @arg @ref LL_SPI_POLARITY_LOW
00418   *         @arg @ref LL_SPI_POLARITY_HIGH
00419   */
00420 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
00421 {
00422   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
00423 }
00424
00425 /**
00426   * @brief  Set baud rate prescaler
00427   * @note   These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
00428   * @rmtoll CR1          BR            LL_SPI_SetBaudRatePrescaler
00429   * @param  SPIx SPI Instance
00430   * @param  BaudRate This parameter can be one of the following values:
00431   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00432   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00433   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00434   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00435   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00436   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00437   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00438   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00439   * @retval None
00440   */
00441 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
00442 {
00443   MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
00444 }
00445
00446 /**
00447   * @brief  Get baud rate prescaler
00448   * @rmtoll CR1          BR            LL_SPI_GetBaudRatePrescaler
00449   * @param  SPIx SPI Instance
00450   * @retval Returned value can be one of the following values:
00451   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
00452   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
00453   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
00454   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
00455   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
00456   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
00457   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
00458   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
00459   */
00460 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
00461 {
00462   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
00463 }
00464
00465 /**
00466   * @brief  Set transfer bit order
00467   * @note   This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
00468   * @rmtoll CR1          LSBFIRST      LL_SPI_SetTransferBitOrder
00469   * @param  SPIx SPI Instance
00470   * @param  BitOrder This parameter can be one of the following values:
00471   *         @arg @ref LL_SPI_LSB_FIRST
00472   *         @arg @ref LL_SPI_MSB_FIRST
00473   * @retval None
00474   */
00475 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
00476 {
00477   MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
00478 }
00479
00480 /**
00481   * @brief  Get transfer bit order
00482   * @rmtoll CR1          LSBFIRST      LL_SPI_GetTransferBitOrder
00483   * @param  SPIx SPI Instance
00484   * @retval Returned value can be one of the following values:
00485   *         @arg @ref LL_SPI_LSB_FIRST
00486   *         @arg @ref LL_SPI_MSB_FIRST
00487   */
00488 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
00489 {
00490   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
00491 }
00492
00493 /**
00494   * @brief  Set transfer direction mode
00495   * @note   For Half-Duplex mode, Rx Direction is set by default.
00496   *         In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
00497   * @rmtoll CR1          RXONLY        LL_SPI_SetTransferDirection\n
00498   *         CR1          BIDIMODE      LL_SPI_SetTransferDirection\n
00499   *         CR1          BIDIOE        LL_SPI_SetTransferDirection
00500   * @param  SPIx SPI Instance
00501   * @param  TransferDirection This parameter can be one of the following values:
00502   *         @arg @ref LL_SPI_FULL_DUPLEX
00503   *         @arg @ref LL_SPI_SIMPLEX_RX
00504   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00505   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00506   * @retval None
00507   */
00508 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
00509 {
00510   MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
00511 }
00512
00513 /**
00514   * @brief  Get transfer direction mode
00515   * @rmtoll CR1          RXONLY        LL_SPI_GetTransferDirection\n
00516   *         CR1          BIDIMODE      LL_SPI_GetTransferDirection\n
00517   *         CR1          BIDIOE        LL_SPI_GetTransferDirection
00518   * @param  SPIx SPI Instance
00519   * @retval Returned value can be one of the following values:
00520   *         @arg @ref LL_SPI_FULL_DUPLEX
00521   *         @arg @ref LL_SPI_SIMPLEX_RX
00522   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
00523   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
00524   */
00525 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
00526 {
00527   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
00528 }
00529
00530 /**
00531   * @brief  Set frame data width
00532   * @rmtoll CR1          DFF           LL_SPI_SetDataWidth
00533   * @param  SPIx SPI Instance
00534   * @param  DataWidth This parameter can be one of the following values:
00535   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00536   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00537   * @retval None
00538   */
00539 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
00540 {
00541   MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
00542 }
00543
00544 /**
00545   * @brief  Get frame data width
00546   * @rmtoll CR1          DFF           LL_SPI_GetDataWidth
00547   * @param  SPIx SPI Instance
00548   * @retval Returned value can be one of the following values:
00549   *         @arg @ref LL_SPI_DATAWIDTH_8BIT
00550   *         @arg @ref LL_SPI_DATAWIDTH_16BIT
00551   */
00552 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
00553 {
00554   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
00555 }
00556
00557 /**
00558   * @}
00559   */
00560
00561 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
00562   * @{
00563   */
00564
00565 /**
00566   * @brief  Enable CRC
00567   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00568   * @rmtoll CR1          CRCEN         LL_SPI_EnableCRC
00569   * @param  SPIx SPI Instance
00570   * @retval None
00571   */
00572 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
00573 {
00574   SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00575 }
00576
00577 /**
00578   * @brief  Disable CRC
00579   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00580   * @rmtoll CR1          CRCEN         LL_SPI_DisableCRC
00581   * @param  SPIx SPI Instance
00582   * @retval None
00583   */
00584 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
00585 {
00586   CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
00587 }
00588
00589 /**
00590   * @brief  Check if CRC is enabled
00591   * @note   This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
00592   * @rmtoll CR1          CRCEN         LL_SPI_IsEnabledCRC
00593   * @param  SPIx SPI Instance
00594   * @retval State of bit (1 or 0).
00595   */
00596 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
00597 {
00598   return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
00599 }
00600
00601 /**
00602   * @brief  Set CRCNext to transfer CRC on the line
00603   * @note   This bit has to be written as soon as the last data is written in the SPIx_DR register.
00604   * @rmtoll CR1          CRCNEXT       LL_SPI_SetCRCNext
00605   * @param  SPIx SPI Instance
00606   * @retval None
00607   */
00608 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
00609 {
00610   SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
00611 }
00612
00613 /**
00614   * @brief  Set polynomial for CRC calculation
00615   * @rmtoll CRCPR        CRCPOLY       LL_SPI_SetCRCPolynomial
00616   * @param  SPIx SPI Instance
00617   * @param  CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00618   * @retval None
00619   */
00620 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
00621 {
00622   WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
00623 }
00624
00625 /**
00626   * @brief  Get polynomial for CRC calculation
00627   * @rmtoll CRCPR        CRCPOLY       LL_SPI_GetCRCPolynomial
00628   * @param  SPIx SPI Instance
00629   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00630   */
00631 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
00632 {
00633   return (uint32_t)(READ_REG(SPIx->CRCPR));
00634 }
00635
00636 /**
00637   * @brief  Get Rx CRC
00638   * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC
00639   * @param  SPIx SPI Instance
00640   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00641   */
00642 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
00643 {
00644   return (uint32_t)(READ_REG(SPIx->RXCRCR));
00645 }
00646
00647 /**
00648   * @brief  Get Tx CRC
00649   * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC
00650   * @param  SPIx SPI Instance
00651   * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
00652   */
00653 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
00654 {
00655   return (uint32_t)(READ_REG(SPIx->TXCRCR));
00656 }
00657
00658 /**
00659   * @}
00660   */
00661
00662 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
00663   * @{
00664   */
00665
00666 /**
00667   * @brief  Set NSS mode
00668   * @note   LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
00669   * @rmtoll CR1          SSM           LL_SPI_SetNSSMode\n
00670   * @rmtoll CR2          SSOE          LL_SPI_SetNSSMode
00671   * @param  SPIx SPI Instance
00672   * @param  NSS This parameter can be one of the following values:
00673   *         @arg @ref LL_SPI_NSS_SOFT
00674   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00675   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00676   * @retval None
00677   */
00678 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
00679 {
00680   MODIFY_REG(SPIx->CR1, SPI_CR1_SSM,  NSS);
00681   MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
00682 }
00683
00684 /**
00685   * @brief  Get NSS mode
00686   * @rmtoll CR1          SSM           LL_SPI_GetNSSMode\n
00687   * @rmtoll CR2          SSOE          LL_SPI_GetNSSMode
00688   * @param  SPIx SPI Instance
00689   * @retval Returned value can be one of the following values:
00690   *         @arg @ref LL_SPI_NSS_SOFT
00691   *         @arg @ref LL_SPI_NSS_HARD_INPUT
00692   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
00693   */
00694 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
00695 {
00696   register uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
00697   register uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
00698   return (Ssm | Ssoe);
00699 }
00700
00701 /**
00702   * @}
00703   */
00704
00705 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
00706   * @{
00707   */
00708
00709 /**
00710   * @brief  Check if Rx buffer is not empty
00711   * @rmtoll SR           RXNE          LL_SPI_IsActiveFlag_RXNE
00712   * @param  SPIx SPI Instance
00713   * @retval State of bit (1 or 0).
00714   */
00715 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
00716 {
00717   return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
00718 }
00719
00720 /**
00721   * @brief  Check if Tx buffer is empty
00722   * @rmtoll SR           TXE           LL_SPI_IsActiveFlag_TXE
00723   * @param  SPIx SPI Instance
00724   * @retval State of bit (1 or 0).
00725   */
00726 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
00727 {
00728   return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
00729 }
00730
00731 /**
00732   * @brief  Get CRC error flag
00733   * @rmtoll SR           CRCERR        LL_SPI_IsActiveFlag_CRCERR
00734   * @param  SPIx SPI Instance
00735   * @retval State of bit (1 or 0).
00736   */
00737 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
00738 {
00739   return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
00740 }
00741
00742 /**
00743   * @brief  Get mode fault error flag
00744   * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF
00745   * @param  SPIx SPI Instance
00746   * @retval State of bit (1 or 0).
00747   */
00748 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
00749 {
00750   return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
00751 }
00752
00753 /**
00754   * @brief  Get overrun error flag
00755   * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR
00756   * @param  SPIx SPI Instance
00757   * @retval State of bit (1 or 0).
00758   */
00759 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
00760 {
00761   return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
00762 }
00763
00764 /**
00765   * @brief  Get busy flag
00766   * @note   The BSY flag is cleared under any one of the following conditions:
00767   * -When the SPI is correctly disabled
00768   * -When a fault is detected in Master mode (MODF bit set to 1)
00769   * -In Master mode, when it finishes a data transmission and no new data is ready to be
00770   * sent
00771   * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
00772   * each data transfer.
00773   * @rmtoll SR           BSY           LL_SPI_IsActiveFlag_BSY
00774   * @param  SPIx SPI Instance
00775   * @retval State of bit (1 or 0).
00776   */
00777 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
00778 {
00779   return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
00780 }
00781
00782
00783 /**
00784   * @brief  Clear CRC error flag
00785   * @rmtoll SR           CRCERR        LL_SPI_ClearFlag_CRCERR
00786   * @param  SPIx SPI Instance
00787   * @retval None
00788   */
00789 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
00790 {
00791   CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
00792 }
00793
00794 /**
00795   * @brief  Clear mode fault error flag
00796   * @note   Clearing this flag is done by a read access to the SPIx_SR
00797   *         register followed by a write access to the SPIx_CR1 register
00798   * @rmtoll SR           MODF          LL_SPI_ClearFlag_MODF
00799   * @param  SPIx SPI Instance
00800   * @retval None
00801   */
00802 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
00803 {
00804   __IO uint32_t tmpreg;
00805   tmpreg = SPIx->SR;
00806   (void) tmpreg;
00807   tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
00808   (void) tmpreg;
00809 }
00810
00811 /**
00812   * @brief  Clear overrun error flag
00813   * @note   Clearing this flag is done by a read access to the SPIx_DR
00814   *         register followed by a read access to the SPIx_SR register
00815   * @rmtoll SR           OVR           LL_SPI_ClearFlag_OVR
00816   * @param  SPIx SPI Instance
00817   * @retval None
00818   */
00819 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
00820 {
00821   __IO uint32_t tmpreg;
00822   tmpreg = SPIx->DR;
00823   (void) tmpreg;
00824   tmpreg = SPIx->SR;
00825   (void) tmpreg;
00826 }
00827
00828
00829 /**
00830   * @}
00831   */
00832
00833 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
00834   * @{
00835   */
00836
00837 /**
00838   * @brief  Enable error interrupt
00839   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
00840   * @rmtoll CR2          ERRIE         LL_SPI_EnableIT_ERR
00841   * @param  SPIx SPI Instance
00842   * @retval None
00843   */
00844 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
00845 {
00846   SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
00847 }
00848
00849 /**
00850   * @brief  Enable Rx buffer not empty interrupt
00851   * @rmtoll CR2          RXNEIE        LL_SPI_EnableIT_RXNE
00852   * @param  SPIx SPI Instance
00853   * @retval None
00854   */
00855 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
00856 {
00857   SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
00858 }
00859
00860 /**
00861   * @brief  Enable Tx buffer empty interrupt
00862   * @rmtoll CR2          TXEIE         LL_SPI_EnableIT_TXE
00863   * @param  SPIx SPI Instance
00864   * @retval None
00865   */
00866 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
00867 {
00868   SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
00869 }
00870
00871 /**
00872   * @brief  Disable error interrupt
00873   * @note   This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
00874   * @rmtoll CR2          ERRIE         LL_SPI_DisableIT_ERR
00875   * @param  SPIx SPI Instance
00876   * @retval None
00877   */
00878 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
00879 {
00880   CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
00881 }
00882
00883 /**
00884   * @brief  Disable Rx buffer not empty interrupt
00885   * @rmtoll CR2          RXNEIE        LL_SPI_DisableIT_RXNE
00886   * @param  SPIx SPI Instance
00887   * @retval None
00888   */
00889 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
00890 {
00891   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
00892 }
00893
00894 /**
00895   * @brief  Disable Tx buffer empty interrupt
00896   * @rmtoll CR2          TXEIE         LL_SPI_DisableIT_TXE
00897   * @param  SPIx SPI Instance
00898   * @retval None
00899   */
00900 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
00901 {
00902   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
00903 }
00904
00905 /**
00906   * @brief  Check if error interrupt is enabled
00907   * @rmtoll CR2          ERRIE         LL_SPI_IsEnabledIT_ERR
00908   * @param  SPIx SPI Instance
00909   * @retval State of bit (1 or 0).
00910   */
00911 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
00912 {
00913   return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
00914 }
00915
00916 /**
00917   * @brief  Check if Rx buffer not empty interrupt is enabled
00918   * @rmtoll CR2          RXNEIE        LL_SPI_IsEnabledIT_RXNE
00919   * @param  SPIx SPI Instance
00920   * @retval State of bit (1 or 0).
00921   */
00922 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
00923 {
00924   return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
00925 }
00926
00927 /**
00928   * @brief  Check if Tx buffer empty interrupt
00929   * @rmtoll CR2          TXEIE         LL_SPI_IsEnabledIT_TXE
00930   * @param  SPIx SPI Instance
00931   * @retval State of bit (1 or 0).
00932   */
00933 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
00934 {
00935   return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
00936 }
00937
00938 /**
00939   * @}
00940   */
00941
00942 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
00943   * @{
00944   */
00945
00946 /**
00947   * @brief  Enable DMA Rx
00948   * @rmtoll CR2          RXDMAEN       LL_SPI_EnableDMAReq_RX
00949   * @param  SPIx SPI Instance
00950   * @retval None
00951   */
00952 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
00953 {
00954   SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
00955 }
00956
00957 /**
00958   * @brief  Disable DMA Rx
00959   * @rmtoll CR2          RXDMAEN       LL_SPI_DisableDMAReq_RX
00960   * @param  SPIx SPI Instance
00961   * @retval None
00962   */
00963 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
00964 {
00965   CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
00966 }
00967
00968 /**
00969   * @brief  Check if DMA Rx is enabled
00970   * @rmtoll CR2          RXDMAEN       LL_SPI_IsEnabledDMAReq_RX
00971   * @param  SPIx SPI Instance
00972   * @retval State of bit (1 or 0).
00973   */
00974 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
00975 {
00976   return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
00977 }
00978
00979 /**
00980   * @brief  Enable DMA Tx
00981   * @rmtoll CR2          TXDMAEN       LL_SPI_EnableDMAReq_TX
00982   * @param  SPIx SPI Instance
00983   * @retval None
00984   */
00985 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
00986 {
00987   SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
00988 }
00989
00990 /**
00991   * @brief  Disable DMA Tx
00992   * @rmtoll CR2          TXDMAEN       LL_SPI_DisableDMAReq_TX
00993   * @param  SPIx SPI Instance
00994   * @retval None
00995   */
00996 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
00997 {
00998   CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
00999 }
01000
01001 /**
01002   * @brief  Check if DMA Tx is enabled
01003   * @rmtoll CR2          TXDMAEN       LL_SPI_IsEnabledDMAReq_TX
01004   * @param  SPIx SPI Instance
01005   * @retval State of bit (1 or 0).
01006   */
01007 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
01008 {
01009   return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
01010 }
01011
01012 /**
01013   * @brief  Get the data register address used for DMA transfer
01014   * @rmtoll DR           DR            LL_SPI_DMA_GetRegAddr
01015   * @param  SPIx SPI Instance
01016   * @retval Address of data register
01017   */
01018 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
01019 {
01020   return (uint32_t) & (SPIx->DR);
01021 }
01022
01023 /**
01024   * @}
01025   */
01026
01027 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
01028   * @{
01029   */
01030
01031 /**
01032   * @brief  Read 8-Bits in the data register
01033   * @rmtoll DR           DR            LL_SPI_ReceiveData8
01034   * @param  SPIx SPI Instance
01035   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
01036   */
01037 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
01038 {
01039   return (uint8_t)(READ_REG(SPIx->DR));
01040 }
01041
01042 /**
01043   * @brief  Read 16-Bits in the data register
01044   * @rmtoll DR           DR            LL_SPI_ReceiveData16
01045   * @param  SPIx SPI Instance
01046   * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01047   */
01048 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
01049 {
01050   return (uint16_t)(READ_REG(SPIx->DR));
01051 }
01052
01053 /**
01054   * @brief  Write 8-Bits in the data register
01055   * @rmtoll DR           DR            LL_SPI_TransmitData8
01056   * @param  SPIx SPI Instance
01057   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFF
01058   * @retval None
01059   */
01060 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
01061 {
01062   SPIx->DR = TxData;
01063 }
01064
01065 /**
01066   * @brief  Write 16-Bits in the data register
01067   * @rmtoll DR           DR            LL_SPI_TransmitData16
01068   * @param  SPIx SPI Instance
01069   * @param  TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
01070   * @retval None
01071   */
01072 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
01073 {
01074   SPIx->DR = TxData;
01075 }
01076
01077 /**
01078   * @}
01079   */
01080 #if defined(USE_FULL_LL_DRIVER)
01081 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
01082   * @{
01083   */
01084
01085 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
01086 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
01087 void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
01088
01089 /**
01090   * @}
01091   */
01092 #endif /* USE_FULL_LL_DRIVER */
01093 /**
01094   * @}
01095   */
01096
01097 /**
01098   * @}
01099   */
01100
01101 #if defined(SPI_I2S_SUPPORT)
01102 /** @defgroup I2S_LL I2S
01103   * @{
01104   */
01105
01106 /* Private variables ---------------------------------------------------------*/
01107 /* Private constants ---------------------------------------------------------*/
01108 /* Private macros ------------------------------------------------------------*/
01109
01110 /* Exported types ------------------------------------------------------------*/
01111 #if defined(USE_FULL_LL_DRIVER)
01112 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
01113   * @{
01114   */
01115
01116 /**
01117   * @brief  I2S Init structure definition
01118   */
01119
01120 typedef struct
01121 {
01122   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
01123                                          This parameter can be a value of @ref I2S_LL_EC_MODE
01124
01125                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
01126
01127   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
01128                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
01129
01130                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
01131
01132
01133   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
01134                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
01135
01136                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
01137
01138
01139   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
01140                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
01141
01142                                          This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
01143
01144
01145   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
01146                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
01147
01148                                          Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
01149                                          and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
01150
01151
01152   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
01153                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
01154
01155                                          This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
01156
01157 } LL_I2S_InitTypeDef;
01158
01159 /**
01160   * @}
01161   */
01162 #endif /*USE_FULL_LL_DRIVER*/
01163
01164 /* Exported constants --------------------------------------------------------*/
01165 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
01166   * @{
01167   */
01168
01169 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
01170   * @brief    Flags defines which can be used with LL_I2S_ReadReg function
01171   * @{
01172   */
01173 #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
01174 #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
01175 #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
01176 #define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
01177 #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
01178 #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
01179 /**
01180   * @}
01181   */
01182
01183 /** @defgroup SPI_LL_EC_IT IT Defines
01184   * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions
01185   * @{
01186   */
01187 #define LL_I2S_CR2_RXNEIE                  LL_SPI_CR2_RXNEIE         /*!< Rx buffer not empty interrupt enable */
01188 #define LL_I2S_CR2_TXEIE                   LL_SPI_CR2_TXEIE          /*!< Tx buffer empty interrupt enable     */
01189 #define LL_I2S_CR2_ERRIE                   LL_SPI_CR2_ERRIE          /*!< Error interrupt enable               */
01190 /**
01191   * @}
01192   */
01193
01194 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
01195   * @{
01196   */
01197 #define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel lenght 16bit */
01198 #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel lenght 32bit */
01199 #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel lenght 32bit */
01200 #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel lenght 32bit */
01201 /**
01202   * @}
01203   */
01204
01205 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
01206   * @{
01207   */
01208 #define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
01209 #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
01210 /**
01211   * @}
01212   */
01213
01214 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
01215   * @{
01216   */
01217 #define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
01218 #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
01219 #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
01220 #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
01221 #define LL_I2S_STANDARD_PCM_LONG           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization  */
01222 /**
01223   * @}
01224   */
01225
01226 /** @defgroup I2S_LL_EC_MODE Operation Mode
01227   * @{
01228   */
01229 #define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
01230 #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
01231 #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
01232 #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
01233 /**
01234   * @}
01235   */
01236
01237 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
01238   * @{
01239   */
01240 #define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
01241 #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
01242 /**
01243   * @}
01244   */
01245
01246 #if defined(USE_FULL_LL_DRIVER)
01247
01248 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
01249   * @{
01250   */
01251 #define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
01252 #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
01253 /**
01254   * @}
01255   */
01256
01257 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
01258   * @{
01259   */
01260
01261 #define LL_I2S_AUDIOFREQ_192K              192000U      /*!< Audio Frequency configuration 192000 Hz       */
01262 #define LL_I2S_AUDIOFREQ_96K               96000U       /*!< Audio Frequency configuration  96000 Hz       */
01263 #define LL_I2S_AUDIOFREQ_48K               48000U       /*!< Audio Frequency configuration  48000 Hz       */
01264 #define LL_I2S_AUDIOFREQ_44K               44100U       /*!< Audio Frequency configuration  44100 Hz       */
01265 #define LL_I2S_AUDIOFREQ_32K               32000U       /*!< Audio Frequency configuration  32000 Hz       */
01266 #define LL_I2S_AUDIOFREQ_22K               22050U       /*!< Audio Frequency configuration  22050 Hz       */
01267 #define LL_I2S_AUDIOFREQ_16K               16000U       /*!< Audio Frequency configuration  16000 Hz       */
01268 #define LL_I2S_AUDIOFREQ_11K               11025U       /*!< Audio Frequency configuration  11025 Hz       */
01269 #define LL_I2S_AUDIOFREQ_8K                8000U        /*!< Audio Frequency configuration   8000 Hz       */
01270 #define LL_I2S_AUDIOFREQ_DEFAULT           2U           /*!< Audio Freq not specified. Register I2SDIV = 2 */
01271 /**
01272   * @}
01273   */
01274 #endif /* USE_FULL_LL_DRIVER */
01275
01276 /**
01277   * @}
01278   */
01279
01280 /* Exported macro ------------------------------------------------------------*/
01281 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
01282   * @{
01283   */
01284
01285 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
01286   * @{
01287   */
01288
01289 /**
01290   * @brief  Write a value in I2S register
01291   * @param  __INSTANCE__ I2S Instance
01292   * @param  __REG__ Register to be written
01293   * @param  __VALUE__ Value to be written in the register
01294   * @retval None
01295   */
01296 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
01297
01298 /**
01299   * @brief  Read a value in I2S register
01300   * @param  __INSTANCE__ I2S Instance
01301   * @param  __REG__ Register to be read
01302   * @retval Register value
01303   */
01304 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
01305 /**
01306   * @}
01307   */
01308
01309 /**
01310   * @}
01311   */
01312
01313
01314 /* Exported functions --------------------------------------------------------*/
01315
01316 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
01317   * @{
01318   */
01319
01320 /** @defgroup I2S_LL_EF_Configuration Configuration
01321   * @{
01322   */
01323
01324 /**
01325   * @brief  Select I2S mode and Enable I2S peripheral
01326   * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n
01327   *         I2SCFGR      I2SE          LL_I2S_Enable
01328   * @param  SPIx SPI Instance
01329   * @retval None
01330   */
01331 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
01332 {
01333   SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
01334 }
01335
01336 /**
01337   * @brief  Disable I2S peripheral
01338   * @rmtoll I2SCFGR      I2SE          LL_I2S_Disable
01339   * @param  SPIx SPI Instance
01340   * @retval None
01341   */
01342 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
01343 {
01344   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
01345 }
01346
01347 /**
01348   * @brief  Check if I2S peripheral is enabled
01349   * @rmtoll I2SCFGR      I2SE          LL_I2S_IsEnabled
01350   * @param  SPIx SPI Instance
01351   * @retval State of bit (1 or 0).
01352   */
01353 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
01354 {
01355   return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
01356 }
01357
01358 /**
01359   * @brief  Set I2S data frame length
01360   * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
01361   *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
01362   * @param  SPIx SPI Instance
01363   * @param  DataFormat This parameter can be one of the following values:
01364   *         @arg @ref LL_I2S_DATAFORMAT_16B
01365   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
01366   *         @arg @ref LL_I2S_DATAFORMAT_24B
01367   *         @arg @ref LL_I2S_DATAFORMAT_32B
01368   * @retval None
01369   */
01370 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
01371 {
01372   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
01373 }
01374
01375 /**
01376   * @brief  Get I2S data frame length
01377   * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
01378   *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
01379   * @param  SPIx SPI Instance
01380   * @retval Returned value can be one of the following values:
01381   *         @arg @ref LL_I2S_DATAFORMAT_16B
01382   *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
01383   *         @arg @ref LL_I2S_DATAFORMAT_24B
01384   *         @arg @ref LL_I2S_DATAFORMAT_32B
01385   */
01386 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
01387 {
01388   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
01389 }
01390
01391 /**
01392   * @brief  Set I2S clock polarity
01393   * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity
01394   * @param  SPIx SPI Instance
01395   * @param  ClockPolarity This parameter can be one of the following values:
01396   *         @arg @ref LL_I2S_POLARITY_LOW
01397   *         @arg @ref LL_I2S_POLARITY_HIGH
01398   * @retval None
01399   */
01400 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
01401 {
01402   SET_BIT(SPIx->I2SCFGR, ClockPolarity);
01403 }
01404
01405 /**
01406   * @brief  Get I2S clock polarity
01407   * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity
01408   * @param  SPIx SPI Instance
01409   * @retval Returned value can be one of the following values:
01410   *         @arg @ref LL_I2S_POLARITY_LOW
01411   *         @arg @ref LL_I2S_POLARITY_HIGH
01412   */
01413 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
01414 {
01415   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
01416 }
01417
01418 /**
01419   * @brief  Set I2S standard protocol
01420   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
01421   *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
01422   * @param  SPIx SPI Instance
01423   * @param  Standard This parameter can be one of the following values:
01424   *         @arg @ref LL_I2S_STANDARD_PHILIPS
01425   *         @arg @ref LL_I2S_STANDARD_MSB
01426   *         @arg @ref LL_I2S_STANDARD_LSB
01427   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
01428   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
01429   * @retval None
01430   */
01431 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
01432 {
01433   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
01434 }
01435
01436 /**
01437   * @brief  Get I2S standard protocol
01438   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
01439   *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
01440   * @param  SPIx SPI Instance
01441   * @retval Returned value can be one of the following values:
01442   *         @arg @ref LL_I2S_STANDARD_PHILIPS
01443   *         @arg @ref LL_I2S_STANDARD_MSB
01444   *         @arg @ref LL_I2S_STANDARD_LSB
01445   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
01446   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
01447   */
01448 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
01449 {
01450   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
01451 }
01452
01453 /**
01454   * @brief  Set I2S transfer mode
01455   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
01456   * @param  SPIx SPI Instance
01457   * @param  Mode This parameter can be one of the following values:
01458   *         @arg @ref LL_I2S_MODE_SLAVE_TX
01459   *         @arg @ref LL_I2S_MODE_SLAVE_RX
01460   *         @arg @ref LL_I2S_MODE_MASTER_TX
01461   *         @arg @ref LL_I2S_MODE_MASTER_RX
01462   * @retval None
01463   */
01464 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
01465 {
01466   MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
01467 }
01468
01469 /**
01470   * @brief  Get I2S transfer mode
01471   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
01472   * @param  SPIx SPI Instance
01473   * @retval Returned value can be one of the following values:
01474   *         @arg @ref LL_I2S_MODE_SLAVE_TX
01475   *         @arg @ref LL_I2S_MODE_SLAVE_RX
01476   *         @arg @ref LL_I2S_MODE_MASTER_TX
01477   *         @arg @ref LL_I2S_MODE_MASTER_RX
01478   */
01479 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
01480 {
01481   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
01482 }
01483
01484 /**
01485   * @brief  Set I2S linear prescaler
01486   * @rmtoll I2SPR        I2SDIV        LL_I2S_SetPrescalerLinear
01487   * @param  SPIx SPI Instance
01488   * @param  PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
01489   * @retval None
01490   */
01491 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
01492 {
01493   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
01494 }
01495
01496 /**
01497   * @brief  Get I2S linear prescaler
01498   * @rmtoll I2SPR        I2SDIV        LL_I2S_GetPrescalerLinear
01499   * @param  SPIx SPI Instance
01500   * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
01501   */
01502 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
01503 {
01504   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
01505 }
01506
01507 /**
01508   * @brief  Set I2S parity prescaler
01509   * @rmtoll I2SPR        ODD           LL_I2S_SetPrescalerParity
01510   * @param  SPIx SPI Instance
01511   * @param  PrescalerParity This parameter can be one of the following values:
01512   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
01513   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
01514   * @retval None
01515   */
01516 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
01517 {
01518   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
01519 }
01520
01521 /**
01522   * @brief  Get I2S parity prescaler
01523   * @rmtoll I2SPR        ODD           LL_I2S_GetPrescalerParity
01524   * @param  SPIx SPI Instance
01525   * @retval Returned value can be one of the following values:
01526   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
01527   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
01528   */
01529 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
01530 {
01531   return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
01532 }
01533
01534 /**
01535   * @brief  Enable the master clock ouput (Pin MCK)
01536   * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
01537   * @param  SPIx SPI Instance
01538   * @retval None
01539   */
01540 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
01541 {
01542   SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
01543 }
01544
01545 /**
01546   * @brief  Disable the master clock ouput (Pin MCK)
01547   * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
01548   * @param  SPIx SPI Instance
01549   * @retval None
01550   */
01551 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
01552 {
01553   CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
01554 }
01555
01556 /**
01557   * @brief  Check if the master clock ouput (Pin MCK) is enabled
01558   * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
01559   * @param  SPIx SPI Instance
01560   * @retval State of bit (1 or 0).
01561   */
01562 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
01563 {
01564   return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
01565 }
01566
01567 /**
01568   * @}
01569   */
01570
01571 /** @defgroup I2S_LL_EF_FLAG FLAG Management
01572   * @{
01573   */
01574
01575 /**
01576   * @brief  Check if Rx buffer is not empty
01577   * @rmtoll SR           RXNE          LL_I2S_IsActiveFlag_RXNE
01578   * @param  SPIx SPI Instance
01579   * @retval State of bit (1 or 0).
01580   */
01581 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
01582 {
01583   return LL_SPI_IsActiveFlag_RXNE(SPIx);
01584 }
01585
01586 /**
01587   * @brief  Check if Tx buffer is empty
01588   * @rmtoll SR           TXE           LL_I2S_IsActiveFlag_TXE
01589   * @param  SPIx SPI Instance
01590   * @retval State of bit (1 or 0).
01591   */
01592 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
01593 {
01594   return LL_SPI_IsActiveFlag_TXE(SPIx);
01595 }
01596
01597 /**
01598   * @brief  Get busy flag
01599   * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
01600   * @param  SPIx SPI Instance
01601   * @retval State of bit (1 or 0).
01602   */
01603 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
01604 {
01605   return LL_SPI_IsActiveFlag_BSY(SPIx);
01606 }
01607
01608 /**
01609   * @brief  Get overrun error flag
01610   * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
01611   * @param  SPIx SPI Instance
01612   * @retval State of bit (1 or 0).
01613   */
01614 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
01615 {
01616   return LL_SPI_IsActiveFlag_OVR(SPIx);
01617 }
01618
01619 /**
01620   * @brief  Get underrun error flag
01621   * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
01622   * @param  SPIx SPI Instance
01623   * @retval State of bit (1 or 0).
01624   */
01625 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
01626 {
01627   return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
01628 }
01629
01630 /**
01631   * @brief  Get frame format error flag
01632   * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
01633   * @param  SPIx SPI Instance
01634   * @retval State of bit (1 or 0).
01635   */
01636 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
01637 {
01638   return LL_SPI_IsActiveFlag_FRE(SPIx);
01639 }
01640
01641 /**
01642   * @brief  Get channel side flag.
01643   * @note   0: Channel Left has to be transmitted or has been received\n
01644   *         1: Channel Right has to be transmitted or has been received\n
01645   *         It has no significance in PCM mode.
01646   * @rmtoll SR           CHSIDE        LL_I2S_IsActiveFlag_CHSIDE
01647   * @param  SPIx SPI Instance
01648   * @retval State of bit (1 or 0).
01649   */
01650 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
01651 {
01652   return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
01653 }
01654
01655 /**
01656   * @brief  Clear overrun error flag
01657   * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
01658   * @param  SPIx SPI Instance
01659   * @retval None
01660   */
01661 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
01662 {
01663   LL_SPI_ClearFlag_OVR(SPIx);
01664 }
01665
01666 /**
01667   * @brief  Clear underrun error flag
01668   * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
01669   * @param  SPIx SPI Instance
01670   * @retval None
01671   */
01672 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
01673 {
01674   __IO uint32_t tmpreg;
01675   tmpreg = SPIx->SR;
01676   (void)tmpreg;
01677 }
01678
01679 /**
01680   * @brief  Clear frame format error flag
01681   * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
01682   * @param  SPIx SPI Instance
01683   * @retval None
01684   */
01685 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
01686 {
01687   LL_SPI_ClearFlag_FRE(SPIx);
01688 }
01689
01690 /**
01691   * @}
01692   */
01693
01694 /** @defgroup I2S_LL_EF_IT Interrupt Management
01695   * @{
01696   */
01697
01698 /**
01699   * @brief  Enable error IT
01700   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
01701   * @rmtoll CR2          ERRIE         LL_I2S_EnableIT_ERR
01702   * @param  SPIx SPI Instance
01703   * @retval None
01704   */
01705 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
01706 {
01707   LL_SPI_EnableIT_ERR(SPIx);
01708 }
01709
01710 /**
01711   * @brief  Enable Rx buffer not empty IT
01712   * @rmtoll CR2          RXNEIE        LL_I2S_EnableIT_RXNE
01713   * @param  SPIx SPI Instance
01714   * @retval None
01715   */
01716 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
01717 {
01718   LL_SPI_EnableIT_RXNE(SPIx);
01719 }
01720
01721 /**
01722   * @brief  Enable Tx buffer empty IT
01723   * @rmtoll CR2          TXEIE         LL_I2S_EnableIT_TXE
01724   * @param  SPIx SPI Instance
01725   * @retval None
01726   */
01727 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
01728 {
01729   LL_SPI_EnableIT_TXE(SPIx);
01730 }
01731
01732 /**
01733   * @brief  Disable error IT
01734   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
01735   * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
01736   * @param  SPIx SPI Instance
01737   * @retval None
01738   */
01739 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
01740 {
01741   LL_SPI_DisableIT_ERR(SPIx);
01742 }
01743
01744 /**
01745   * @brief  Disable Rx buffer not empty IT
01746   * @rmtoll CR2          RXNEIE        LL_I2S_DisableIT_RXNE
01747   * @param  SPIx SPI Instance
01748   * @retval None
01749   */
01750 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
01751 {
01752   LL_SPI_DisableIT_RXNE(SPIx);
01753 }
01754
01755 /**
01756   * @brief  Disable Tx buffer empty IT
01757   * @rmtoll CR2          TXEIE         LL_I2S_DisableIT_TXE
01758   * @param  SPIx SPI Instance
01759   * @retval None
01760   */
01761 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
01762 {
01763   LL_SPI_DisableIT_TXE(SPIx);
01764 }
01765
01766 /**
01767   * @brief  Check if ERR IT is enabled
01768   * @rmtoll CR2          ERRIE         LL_I2S_IsEnabledIT_ERR
01769   * @param  SPIx SPI Instance
01770   * @retval State of bit (1 or 0).
01771   */
01772 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
01773 {
01774   return LL_SPI_IsEnabledIT_ERR(SPIx);
01775 }
01776
01777 /**
01778   * @brief  Check if RXNE IT is enabled
01779   * @rmtoll CR2          RXNEIE        LL_I2S_IsEnabledIT_RXNE
01780   * @param  SPIx SPI Instance
01781   * @retval State of bit (1 or 0).
01782   */
01783 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
01784 {
01785   return LL_SPI_IsEnabledIT_RXNE(SPIx);
01786 }
01787
01788 /**
01789   * @brief  Check if TXE IT is enabled
01790   * @rmtoll CR2          TXEIE         LL_I2S_IsEnabledIT_TXE
01791   * @param  SPIx SPI Instance
01792   * @retval State of bit (1 or 0).
01793   */
01794 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
01795 {
01796   return LL_SPI_IsEnabledIT_TXE(SPIx);
01797 }
01798
01799 /**
01800   * @}
01801   */
01802
01803 /** @defgroup I2S_LL_EF_DMA DMA Management
01804   * @{
01805   */
01806
01807 /**
01808   * @brief  Enable DMA Rx
01809   * @rmtoll CR2          RXDMAEN       LL_I2S_EnableDMAReq_RX
01810   * @param  SPIx SPI Instance
01811   * @retval None
01812   */
01813 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
01814 {
01815   LL_SPI_EnableDMAReq_RX(SPIx);
01816 }
01817
01818 /**
01819   * @brief  Disable DMA Rx
01820   * @rmtoll CR2          RXDMAEN       LL_I2S_DisableDMAReq_RX
01821   * @param  SPIx SPI Instance
01822   * @retval None
01823   */
01824 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
01825 {
01826   LL_SPI_DisableDMAReq_RX(SPIx);
01827 }
01828
01829 /**
01830   * @brief  Check if DMA Rx is enabled
01831   * @rmtoll CR2          RXDMAEN       LL_I2S_IsEnabledDMAReq_RX
01832   * @param  SPIx SPI Instance
01833   * @retval State of bit (1 or 0).
01834   */
01835 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
01836 {
01837   return LL_SPI_IsEnabledDMAReq_RX(SPIx);
01838 }
01839
01840 /**
01841   * @brief  Enable DMA Tx
01842   * @rmtoll CR2          TXDMAEN       LL_I2S_EnableDMAReq_TX
01843   * @param  SPIx SPI Instance
01844   * @retval None
01845   */
01846 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
01847 {
01848   LL_SPI_EnableDMAReq_TX(SPIx);
01849 }
01850
01851 /**
01852   * @brief  Disable DMA Tx
01853   * @rmtoll CR2          TXDMAEN       LL_I2S_DisableDMAReq_TX
01854   * @param  SPIx SPI Instance
01855   * @retval None
01856   */
01857 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
01858 {
01859   LL_SPI_DisableDMAReq_TX(SPIx);
01860 }
01861
01862 /**
01863   * @brief  Check if DMA Tx is enabled
01864   * @rmtoll CR2          TXDMAEN       LL_I2S_IsEnabledDMAReq_TX
01865   * @param  SPIx SPI Instance
01866   * @retval State of bit (1 or 0).
01867   */
01868 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
01869 {
01870   return LL_SPI_IsEnabledDMAReq_TX(SPIx);
01871 }
01872
01873 /**
01874   * @}
01875   */
01876
01877 /** @defgroup I2S_LL_EF_DATA DATA Management
01878   * @{
01879   */
01880
01881 /**
01882   * @brief  Read 16-Bits in data register
01883   * @rmtoll DR           DR            LL_I2S_ReceiveData16
01884   * @param  SPIx SPI Instance
01885   * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
01886   */
01887 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
01888 {
01889   return LL_SPI_ReceiveData16(SPIx);
01890 }
01891
01892 /**
01893   * @brief  Write 16-Bits in data register
01894   * @rmtoll DR           DR            LL_I2S_TransmitData16
01895   * @param  SPIx SPI Instance
01896   * @param  TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
01897   * @retval None
01898   */
01899 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
01900 {
01901   LL_SPI_TransmitData16(SPIx, TxData);
01902 }
01903
01904 /**
01905   * @}
01906   */
01907
01908 #if defined(USE_FULL_LL_DRIVER)
01909 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
01910   * @{
01911   */
01912
01913 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
01914 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
01915 void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
01916 void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
01917
01918 /**
01919   * @}
01920   */
01921 #endif /* USE_FULL_LL_DRIVER */
01922
01923 /**
01924   * @}
01925   */
01926
01927 /**
01928   * @}
01929   */
01930 #endif /* SPI_I2S_SUPPORT */
01931
01932 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
01933
01934 /**
01935   * @}
01936   */
01937
01938 #ifdef __cplusplus
01939 }
01940 #endif
01941
01942 #endif /* __STM32F1xx_LL_SPI_H */
01943
01944 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_system.h Source File

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stm32f1xx_ll_system.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_system.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of SYSTEM LL module.
00008   @verbatim
00009   ==============================================================================
00010                      ##### How to use this driver #####
00011   ==============================================================================
00012     [..]
00013     The LL SYSTEM driver contains a set of generic APIs that can be
00014     used by user:
00015       (+) Some of the FLASH features need to be handled in the SYSTEM file.
00016       (+) Access to DBGCMU registers
00017       (+) Access to SYSCFG registers
00018
00019   @endverbatim
00020   ******************************************************************************
00021   * @attention
00022   *
00023   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00024   *
00025   * Redistribution and use in source and binary forms, with or without modification,
00026   * are permitted provided that the following conditions are met:
00027   *   1. Redistributions of source code must retain the above copyright notice,
00028   *      this list of conditions and the following disclaimer.
00029   *   2. Redistributions in binary form must reproduce the above copyright notice,
00030   *      this list of conditions and the following disclaimer in the documentation
00031   *      and/or other materials provided with the distribution.
00032   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00033   *      may be used to endorse or promote products derived from this software
00034   *      without specific prior written permission.
00035   *
00036   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00037   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00038   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00039   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00040   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00041   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00042   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00043   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00044   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00045   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00046   *
00047   ******************************************************************************
00048   */
00049
00050 /* Define to prevent recursive inclusion -------------------------------------*/
00051 #ifndef __STM32F1xx_LL_SYSTEM_H
00052 #define __STM32F1xx_LL_SYSTEM_H
00053
00054 #ifdef __cplusplus
00055 extern "C" {
00056 #endif
00057
00058 /* Includes ------------------------------------------------------------------*/
00059 #include "stm32f1xx.h"
00060
00061 /** @addtogroup STM32F1xx_LL_Driver
00062   * @{
00063   */
00064
00065 #if defined (FLASH) || defined (DBGMCU)
00066
00067 /** @defgroup SYSTEM_LL SYSTEM
00068   * @{
00069   */
00070
00071 /* Private types -------------------------------------------------------------*/
00072 /* Private variables ---------------------------------------------------------*/
00073
00074 /* Private constants ---------------------------------------------------------*/
00075 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
00076   * @{
00077   */
00078
00079 /**
00080   * @}
00081   */
00082
00083 /* Private macros ------------------------------------------------------------*/
00084
00085 /* Exported types ------------------------------------------------------------*/
00086 /* Exported constants --------------------------------------------------------*/
00087 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
00088   * @{
00089   */
00090
00091
00092
00093 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
00094   * @{
00095   */
00096 #define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
00097 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
00098 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
00099 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
00100 #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
00101 /**
00102   * @}
00103   */
00104
00105 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
00106   * @{
00107   */
00108 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_CR_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */
00109 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_CR_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */
00110 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_CR_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */
00111 #if defined(DBGMCU_CR_DBG_TIM5_STOP)
00112 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_CR_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */
00113 #endif /* DBGMCU_CR_DBG_TIM5_STOP */
00114 #if defined(DBGMCU_CR_DBG_TIM6_STOP)
00115 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_CR_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */
00116 #endif /* DBGMCU_CR_DBG_TIM6_STOP */
00117 #if defined(DBGMCU_CR_DBG_TIM7_STOP)
00118 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_CR_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */
00119 #endif /* DBGMCU_CR_DBG_TIM7_STOP */
00120 #if defined(DBGMCU_CR_DBG_TIM12_STOP)
00121 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_CR_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */
00122 #endif /* DBGMCU_CR_DBG_TIM12_STOP */
00123 #if defined(DBGMCU_CR_DBG_TIM13_STOP)
00124 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_CR_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */
00125 #endif /* DBGMCU_CR_DBG_TIM13_STOP */
00126 #if defined(DBGMCU_CR_DBG_TIM14_STOP)
00127 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_CR_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */
00128 #endif /* DBGMCU_CR_DBG_TIM14_STOP */
00129 #define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_CR_DBG_RTC_STOP           /*!< RTC counter stopped when core is halted */
00130 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_CR_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */
00131 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_CR_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */
00132 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_CR_DBG_I2C1_STOP          /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
00133 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_CR_DBG_I2C2_STOP          /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
00134 #if defined(DBGMCU_CR_DBG_CAN1_STOP)
00135 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP      DBGMCU_CR_DBG_CAN1_STOP          /*!< CAN1 debug stopped when Core is halted  */
00136 #endif /* DBGMCU_CR_DBG_CAN1_STOP */
00137 #if defined(DBGMCU_CR_DBG_CAN2_STOP)
00138 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_CR_DBG_CAN2_STOP          /*!< CAN2 debug stopped when Core is halted  */
00139 #endif /* DBGMCU_CR_DBG_CAN2_STOP */
00140 /**
00141   * @}
00142   */
00143
00144 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
00145   * @{
00146   */
00147 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_CR_DBG_TIM1_STOP   /*!< TIM1 counter stopped when core is halted */
00148 #if defined(DBGMCU_CR_DBG_TIM8_STOP)
00149 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_CR_DBG_TIM8_STOP   /*!< TIM8 counter stopped when core is halted */
00150 #endif /* DBGMCU_CR_DBG_CAN1_STOP */
00151 #if defined(DBGMCU_CR_DBG_TIM9_STOP)
00152 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_CR_DBG_TIM9_STOP   /*!< TIM9 counter stopped when core is halted */
00153 #endif /* DBGMCU_CR_DBG_TIM9_STOP */
00154 #if defined(DBGMCU_CR_DBG_TIM10_STOP)
00155 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_CR_DBG_TIM10_STOP   /*!< TIM10 counter stopped when core is halted */
00156 #endif /* DBGMCU_CR_DBG_TIM10_STOP */
00157 #if defined(DBGMCU_CR_DBG_TIM11_STOP)
00158 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_CR_DBG_TIM11_STOP   /*!< TIM11 counter stopped when core is halted */
00159 #endif /* DBGMCU_CR_DBG_TIM11_STOP */
00160 #if defined(DBGMCU_CR_DBG_TIM15_STOP)
00161 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_CR_DBG_TIM15_STOP   /*!< TIM15 counter stopped when core is halted */
00162 #endif /* DBGMCU_CR_DBG_TIM15_STOP */
00163 #if defined(DBGMCU_CR_DBG_TIM16_STOP)
00164 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_CR_DBG_TIM16_STOP   /*!< TIM16 counter stopped when core is halted */
00165 #endif /* DBGMCU_CR_DBG_TIM16_STOP */
00166 #if defined(DBGMCU_CR_DBG_TIM17_STOP)
00167 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_CR_DBG_TIM17_STOP   /*!< TIM17 counter stopped when core is halted */
00168 #endif /* DBGMCU_CR_DBG_TIM17_STOP */
00169 /**
00170   * @}
00171   */
00172
00173 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
00174   * @{
00175   */
00176 #if defined(FLASH_ACR_LATENCY)
00177 #define LL_FLASH_LATENCY_0                 0x00000000U             /*!< FLASH Zero Latency cycle */
00178 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_0     /*!< FLASH One Latency cycle */
00179 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_1     /*!< FLASH Two wait states */
00180 #else
00181 #endif /* FLASH_ACR_LATENCY */
00182 /**
00183   * @}
00184   */
00185
00186 /**
00187   * @}
00188   */
00189
00190 /* Exported macro ------------------------------------------------------------*/
00191
00192 /* Exported functions --------------------------------------------------------*/
00193 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
00194   * @{
00195   */
00196
00197
00198
00199 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
00200   * @{
00201   */
00202
00203 /**
00204   * @brief  Return the device identifier
00205   * @note For Low Density devices, the device ID is 0x412
00206   * @note For Medium Density devices, the device ID is 0x410
00207   * @note For High Density devices, the device ID is 0x414
00208   * @note For XL Density devices, the device ID is 0x430
00209   * @note For Connectivity Line devices, the device ID is 0x418
00210   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
00211   * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
00212   */
00213 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
00214 {
00215   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
00216 }
00217
00218 /**
00219   * @brief  Return the device revision identifier
00220   * @note This field indicates the revision of the device.
00221           For example, it is read as revA -> 0x1000,for Low Density devices
00222           For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
00223           For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
00224           For example, it is read as revA or 1 -> 0x1003,for XL Density devices
00225           For example, it is read as revA -> 0x1000, revZ -> 0x1001 for  Connectivity line devices
00226   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
00227   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
00228   */
00229 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
00230 {
00231   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
00232 }
00233
00234 /**
00235   * @brief  Enable the Debug Module during SLEEP mode
00236   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
00237   * @retval None
00238   */
00239 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
00240 {
00241   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00242 }
00243
00244 /**
00245   * @brief  Disable the Debug Module during SLEEP mode
00246   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
00247   * @retval None
00248   */
00249 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
00250 {
00251   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00252 }
00253
00254 /**
00255   * @brief  Enable the Debug Module during STOP mode
00256   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
00257   * @retval None
00258   */
00259 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
00260 {
00261   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00262 }
00263
00264 /**
00265   * @brief  Disable the Debug Module during STOP mode
00266   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
00267   * @retval None
00268   */
00269 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
00270 {
00271   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00272 }
00273
00274 /**
00275   * @brief  Enable the Debug Module during STANDBY mode
00276   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
00277   * @retval None
00278   */
00279 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
00280 {
00281   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00282 }
00283
00284 /**
00285   * @brief  Disable the Debug Module during STANDBY mode
00286   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
00287   * @retval None
00288   */
00289 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
00290 {
00291   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
00292 }
00293
00294 /**
00295   * @brief  Set Trace pin assignment control
00296   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
00297   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
00298   * @param  PinAssignment This parameter can be one of the following values:
00299   *         @arg @ref LL_DBGMCU_TRACE_NONE
00300   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
00301   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
00302   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
00303   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
00304   * @retval None
00305   */
00306 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
00307 {
00308   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
00309 }
00310
00311 /**
00312   * @brief  Get Trace pin assignment control
00313   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
00314   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
00315   * @retval Returned value can be one of the following values:
00316   *         @arg @ref LL_DBGMCU_TRACE_NONE
00317   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
00318   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
00319   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
00320   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
00321   */
00322 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
00323 {
00324   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
00325 }
00326
00327 /**
00328   * @brief  Freeze APB1 peripherals (group1 peripherals)
00329   * @rmtoll DBGMCU_CR_APB1      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00330   *         DBGMCU_CR_APB1      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00331   *         DBGMCU_CR_APB1      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00332   *         DBGMCU_CR_APB1      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00333   *         DBGMCU_CR_APB1      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00334   *         DBGMCU_CR_APB1      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00335   *         DBGMCU_CR_APB1      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00336   *         DBGMCU_CR_APB1      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00337   *         DBGMCU_CR_APB1      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00338   *         DBGMCU_CR_APB1      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00339   *         DBGMCU_CR_APB1      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00340   *         DBGMCU_CR_APB1      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00341   *         DBGMCU_CR_APB1      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00342   *         DBGMCU_CR_APB1      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00343   *         DBGMCU_CR_APB1      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
00344   *         DBGMCU_CR_APB1      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph
00345   * @param  Periphs This parameter can be a combination of the following values:
00346   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
00347   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
00348   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
00349   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
00350   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
00351   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
00352   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
00353   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
00354   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
00355   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
00356   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
00357   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
00358   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
00359   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
00360   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
00361   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
00362   *
00363   *         (*) value not defined in all devices.
00364   * @retval None
00365   */
00366 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
00367 {
00368   SET_BIT(DBGMCU->CR, Periphs);
00369 }
00370
00371 /**
00372   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
00373   * @rmtoll DBGMCU_CR_APB1      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00374   *         DBGMCU_CR_APB1      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00375   *         DBGMCU_CR_APB1      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00376   *         DBGMCU_CR_APB1      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00377   *         DBGMCU_CR_APB1      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00378   *         DBGMCU_CR_APB1      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00379   *         DBGMCU_CR_APB1      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00380   *         DBGMCU_CR_APB1      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00381   *         DBGMCU_CR_APB1      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00382   *         DBGMCU_CR_APB1      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00383   *         DBGMCU_CR_APB1      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00384   *         DBGMCU_CR_APB1      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00385   *         DBGMCU_CR_APB1      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00386   *         DBGMCU_CR_APB1      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00387   *         DBGMCU_CR_APB1      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
00388   *         DBGMCU_CR_APB1      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph
00389   * @param  Periphs This parameter can be a combination of the following values:
00390   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
00391   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
00392   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
00393   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
00394   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
00395   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
00396   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
00397   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
00398   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
00399   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
00400   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
00401   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
00402   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
00403   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
00404   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
00405   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
00406   *
00407   *         (*) value not defined in all devices.
00408   * @retval None
00409   */
00410 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
00411 {
00412   CLEAR_BIT(DBGMCU->CR, Periphs);
00413 }
00414
00415 /**
00416   * @brief  Freeze APB2 peripherals
00417   * @rmtoll DBGMCU_CR_APB2      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00418   *         DBGMCU_CR_APB2      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00419   *         DBGMCU_CR_APB2      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00420   *         DBGMCU_CR_APB2      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00421   *         DBGMCU_CR_APB2      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00422   *         DBGMCU_CR_APB2      DBG_TIM15_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00423   *         DBGMCU_CR_APB2      DBG_TIM16_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00424   *         DBGMCU_CR_APB2      DBG_TIM17_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
00425   * @param  Periphs This parameter can be a combination of the following values:
00426   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
00427   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
00428   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
00429   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
00430   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
00431   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
00432   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
00433   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
00434   *
00435   *         (*) value not defined in all devices.
00436   * @retval None
00437   */
00438 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
00439 {
00440   SET_BIT(DBGMCU->CR, Periphs);
00441 }
00442
00443 /**
00444   * @brief  Unfreeze APB2 peripherals
00445   * @rmtoll DBGMCU_CR_APB2      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00446   *         DBGMCU_CR_APB2      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00447   *         DBGMCU_CR_APB2      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00448   *         DBGMCU_CR_APB2      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00449   *         DBGMCU_CR_APB2      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00450   *         DBGMCU_CR_APB2      DBG_TIM15_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00451   *         DBGMCU_CR_APB2      DBG_TIM16_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
00452   *         DBGMCU_CR_APB2      DBG_TIM17_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
00453   * @param  Periphs This parameter can be a combination of the following values:
00454   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
00455   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
00456   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
00457   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
00458   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
00459   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
00460   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
00461   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
00462   *
00463   *         (*) value not defined in all devices.
00464   * @retval None
00465   */
00466 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
00467 {
00468   CLEAR_BIT(DBGMCU->CR, Periphs);
00469 }
00470 /**
00471   * @}
00472   */
00473
00474 #if defined(FLASH_ACR_LATENCY)
00475 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
00476   * @{
00477   */
00478
00479 /**
00480   * @brief  Set FLASH Latency
00481   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
00482   * @param  Latency This parameter can be one of the following values:
00483   *         @arg @ref LL_FLASH_LATENCY_0
00484   *         @arg @ref LL_FLASH_LATENCY_1
00485   *         @arg @ref LL_FLASH_LATENCY_2
00486   * @retval None
00487   */
00488 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
00489 {
00490   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
00491 }
00492
00493 /**
00494   * @brief  Get FLASH Latency
00495   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
00496   * @retval Returned value can be one of the following values:
00497   *         @arg @ref LL_FLASH_LATENCY_0
00498   *         @arg @ref LL_FLASH_LATENCY_1
00499   *         @arg @ref LL_FLASH_LATENCY_2
00500   */
00501 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
00502 {
00503   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
00504 }
00505
00506 /**
00507   * @brief  Enable Prefetch
00508   * @rmtoll FLASH_ACR    PRFTBE        LL_FLASH_EnablePrefetch
00509   * @retval None
00510   */
00511 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
00512 {
00513   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
00514 }
00515
00516 /**
00517   * @brief  Disable Prefetch
00518   * @rmtoll FLASH_ACR    PRFTBE        LL_FLASH_DisablePrefetch
00519   * @retval None
00520   */
00521 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
00522 {
00523   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
00524 }
00525
00526 /**
00527   * @brief  Check if Prefetch buffer is enabled
00528   * @rmtoll FLASH_ACR    PRFTBS        LL_FLASH_IsPrefetchEnabled
00529   * @retval State of bit (1 or 0).
00530   */
00531 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
00532 {
00533   return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
00534 }
00535
00536 #endif /* FLASH_ACR_LATENCY */
00537 /**
00538   * @brief  Enable Flash Half Cycle Access
00539   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_EnableHalfCycleAccess
00540   * @retval None
00541   */
00542 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
00543 {
00544   SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
00545 }
00546
00547 /**
00548   * @brief  Disable Flash Half Cycle Access
00549   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_DisableHalfCycleAccess
00550   * @retval None
00551   */
00552 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
00553 {
00554   CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
00555 }
00556
00557 /**
00558   * @brief  Check if  Flash Half Cycle Access is enabled or not
00559   * @rmtoll FLASH_ACR    HLFCYA        LL_FLASH_IsHalfCycleAccessEnabled
00560   * @retval State of bit (1 or 0).
00561   */
00562 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
00563 {
00564   return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
00565 }
00566
00567
00568 /**
00569   * @}
00570   */
00571
00572 /**
00573   * @}
00574   */
00575
00576 /**
00577   * @}
00578   */
00579
00580 #endif /* defined (FLASH) || defined (DBGMCU) */
00581
00582 /**
00583   * @}
00584   */
00585
00586 #ifdef __cplusplus
00587 }
00588 #endif
00589
00590 #endif /* __STM32F1xx_LL_SYSTEM_H */
00591
00592 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_tim.c Source File

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stm32f1xx_ll_tim.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_tim.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   TIM LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_tim.h"
00041 #include "stm32f1xx_ll_bus.h"
00042
00043 #ifdef  USE_FULL_ASSERT
00044 #include "stm32_assert.h"
00045 #else
00046 #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
00054
00055 /** @addtogroup TIM_LL
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 /** @addtogroup TIM_LL_Private_Macros
00064   * @{
00065   */
00066 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
00067                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
00068                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
00069                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
00070                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
00071
00072 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
00073                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
00074                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
00075
00076 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
00077                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
00078                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
00079                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
00080                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
00081                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
00082                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
00083                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
00084
00085 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
00086                                    || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
00087
00088 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
00089                                       || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
00090
00091 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
00092                                        || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
00093
00094 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
00095                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
00096                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
00097
00098 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
00099                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
00100                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
00101                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
00102
00103 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
00104                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
00105                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
00106                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
00107                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
00108                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
00109                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
00110                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
00111                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
00112                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
00113                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
00114                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
00115                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
00116                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
00117                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
00118                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
00119
00120 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00121                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
00122
00123 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
00124                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
00125                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
00126
00127 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
00128                                                || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
00129
00130 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
00131                                      || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
00132
00133 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
00134                                       || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
00135
00136 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
00137                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
00138                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
00139                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
00140
00141 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
00142                                        || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
00143
00144 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
00145                                           || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
00146
00147 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
00148                                                   || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
00149 /**
00150   * @}
00151   */
00152
00153
00154 /* Private function prototypes -----------------------------------------------*/
00155 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
00156   * @{
00157   */
00158 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00159 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00160 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00161 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
00162 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00163 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00164 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00165 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
00166 /**
00167   * @}
00168   */
00169
00170 /* Exported functions --------------------------------------------------------*/
00171 /** @addtogroup TIM_LL_Exported_Functions
00172   * @{
00173   */
00174
00175 /** @addtogroup TIM_LL_EF_Init
00176   * @{
00177   */
00178
00179 /**
00180   * @brief  Set TIMx registers to their reset values.
00181   * @param  TIMx Timer instance
00182   * @retval An ErrorStatus enumeration value:
00183   *          - SUCCESS: TIMx registers are de-initialized
00184   *          - ERROR: invalid TIMx instance
00185   */
00186 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
00187 {
00188   ErrorStatus result = SUCCESS;
00189
00190   /* Check the parameters */
00191   assert_param(IS_TIM_INSTANCE(TIMx));
00192
00193   if (TIMx == TIM2)
00194   {
00195     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
00196     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
00197   }
00198 #if defined(TIM1)
00199   else if (TIMx == TIM1)
00200   {
00201     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
00202     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
00203   }
00204 #endif
00205 #if defined(TIM3)
00206   else if (TIMx == TIM3)
00207   {
00208     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
00209     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
00210   }
00211 #endif
00212 #if defined(TIM4)
00213   else if (TIMx == TIM4)
00214   {
00215     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
00216     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
00217   }
00218 #endif
00219 #if defined(TIM5)
00220   else if (TIMx == TIM5)
00221   {
00222     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
00223     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
00224   }
00225 #endif
00226 #if defined(TIM6)
00227   else if (TIMx == TIM6)
00228   {
00229     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
00230     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
00231   }
00232 #endif
00233 #if defined (TIM7)
00234   else if (TIMx == TIM7)
00235   {
00236     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
00237     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
00238   }
00239 #endif
00240 #if defined(TIM8)
00241   else if (TIMx == TIM8)
00242   {
00243     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
00244     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
00245   }
00246 #endif
00247 #if defined(TIM9)
00248   else if (TIMx == TIM9)
00249   {
00250     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
00251     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
00252   }
00253 #endif
00254 #if defined(TIM10)
00255   else if (TIMx == TIM10)
00256   {
00257     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
00258     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
00259   }
00260 #endif
00261 #if defined(TIM11)
00262   else if (TIMx == TIM11)
00263   {
00264     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
00265     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
00266   }
00267 #endif
00268 #if defined(TIM12)
00269   else if (TIMx == TIM12)
00270   {
00271     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
00272     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
00273   }
00274 #endif
00275 #if defined(TIM13)
00276   else if (TIMx == TIM13)
00277   {
00278     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
00279     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
00280   }
00281 #endif
00282 #if defined(TIM14)
00283   else if (TIMx == TIM14)
00284   {
00285     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
00286     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
00287   }
00288 #endif
00289 #if defined(TIM15)
00290   else if (TIMx == TIM15)
00291   {
00292     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
00293     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
00294   }
00295 #endif
00296 #if defined(TIM16)
00297   else if (TIMx == TIM16)
00298   {
00299     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
00300     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
00301   }
00302 #endif
00303 #if defined(TIM17)
00304   else if (TIMx == TIM17)
00305   {
00306     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
00307     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
00308   }
00309 #endif
00310   else
00311   {
00312     result = ERROR;
00313   }
00314
00315   return result;
00316 }
00317
00318 /**
00319   * @brief  Set the fields of the time base unit configuration data structure
00320   *         to their default values.
00321   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
00322   * @retval None
00323   */
00324 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
00325 {
00326   /* Set the default configuration */
00327   TIM_InitStruct->Prescaler         = (uint16_t)0x0000U;
00328   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
00329   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
00330   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
00331   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
00332 }
00333
00334 /**
00335   * @brief  Configure the TIMx time base unit.
00336   * @param  TIMx Timer Instance
00337   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
00338   * @retval An ErrorStatus enumeration value:
00339   *          - SUCCESS: TIMx registers are de-initialized
00340   *          - ERROR: not applicable
00341   */
00342 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
00343 {
00344   uint32_t tmpcr1 = 0U;
00345
00346   /* Check the parameters */
00347   assert_param(IS_TIM_INSTANCE(TIMx));
00348   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
00349   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
00350
00351   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
00352
00353   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
00354   {
00355     /* Select the Counter Mode */
00356     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
00357   }
00358
00359   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
00360   {
00361     /* Set the clock division */
00362     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
00363   }
00364
00365   /* Write to TIMx CR1 */
00366   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
00367
00368   /* Set the Autoreload value */
00369   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
00370
00371   /* Set the Prescaler value */
00372   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
00373
00374   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
00375   {
00376     /* Set the Repetition Counter value */
00377     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
00378   }
00379
00380   /* Generate an update event to reload the Prescaler
00381      and the repetition counter value (if applicable) immediately */
00382   LL_TIM_GenerateEvent_UPDATE(TIMx);
00383
00384   return SUCCESS;
00385 }
00386
00387 /**
00388   * @brief  Set the fields of the TIMx output channel configuration data
00389   *         structure to their default values.
00390   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
00391   * @retval None
00392   */
00393 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00394 {
00395   /* Set the default configuration */
00396   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
00397   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
00398   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
00399   TIM_OC_InitStruct->CompareValue = 0x00000000U;
00400   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
00401   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
00402   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
00403   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
00404 }
00405
00406 /**
00407   * @brief  Configure the TIMx output channel.
00408   * @param  TIMx Timer Instance
00409   * @param  Channel This parameter can be one of the following values:
00410   *         @arg @ref LL_TIM_CHANNEL_CH1
00411   *         @arg @ref LL_TIM_CHANNEL_CH2
00412   *         @arg @ref LL_TIM_CHANNEL_CH3
00413   *         @arg @ref LL_TIM_CHANNEL_CH4
00414   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
00415   * @retval An ErrorStatus enumeration value:
00416   *          - SUCCESS: TIMx output channel is initialized
00417   *          - ERROR: TIMx output channel is not initialized
00418   */
00419 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
00420 {
00421   ErrorStatus result = ERROR;
00422
00423   switch (Channel)
00424   {
00425     case LL_TIM_CHANNEL_CH1:
00426       result = OC1Config(TIMx, TIM_OC_InitStruct);
00427       break;
00428     case LL_TIM_CHANNEL_CH2:
00429       result = OC2Config(TIMx, TIM_OC_InitStruct);
00430       break;
00431     case LL_TIM_CHANNEL_CH3:
00432       result = OC3Config(TIMx, TIM_OC_InitStruct);
00433       break;
00434     case LL_TIM_CHANNEL_CH4:
00435       result = OC4Config(TIMx, TIM_OC_InitStruct);
00436       break;
00437     default:
00438       break;
00439   }
00440
00441   return result;
00442 }
00443
00444 /**
00445   * @brief  Set the fields of the TIMx input channel configuration data
00446   *         structure to their default values.
00447   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
00448   * @retval None
00449   */
00450 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
00451 {
00452   /* Set the default configuration */
00453   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
00454   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00455   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
00456   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
00457 }
00458
00459 /**
00460   * @brief  Configure the TIMx input channel.
00461   * @param  TIMx Timer Instance
00462   * @param  Channel This parameter can be one of the following values:
00463   *         @arg @ref LL_TIM_CHANNEL_CH1
00464   *         @arg @ref LL_TIM_CHANNEL_CH2
00465   *         @arg @ref LL_TIM_CHANNEL_CH3
00466   *         @arg @ref LL_TIM_CHANNEL_CH4
00467   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
00468   * @retval An ErrorStatus enumeration value:
00469   *          - SUCCESS: TIMx output channel is initialized
00470   *          - ERROR: TIMx output channel is not initialized
00471   */
00472 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
00473 {
00474   ErrorStatus result = ERROR;
00475
00476   switch (Channel)
00477   {
00478     case LL_TIM_CHANNEL_CH1:
00479       result = IC1Config(TIMx, TIM_IC_InitStruct);
00480       break;
00481     case LL_TIM_CHANNEL_CH2:
00482       result = IC2Config(TIMx, TIM_IC_InitStruct);
00483       break;
00484     case LL_TIM_CHANNEL_CH3:
00485       result = IC3Config(TIMx, TIM_IC_InitStruct);
00486       break;
00487     case LL_TIM_CHANNEL_CH4:
00488       result = IC4Config(TIMx, TIM_IC_InitStruct);
00489       break;
00490     default:
00491       break;
00492   }
00493
00494   return result;
00495 }
00496
00497 /**
00498   * @brief  Fills each TIM_EncoderInitStruct field with its default value
00499   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
00500   * @retval None
00501   */
00502 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00503 {
00504   /* Set the default configuration */
00505   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
00506   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
00507   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00508   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
00509   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
00510   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
00511   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
00512   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
00513   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
00514 }
00515
00516 /**
00517   * @brief  Configure the encoder interface of the timer instance.
00518   * @param  TIMx Timer Instance
00519   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
00520   * @retval An ErrorStatus enumeration value:
00521   *          - SUCCESS: TIMx registers are de-initialized
00522   *          - ERROR: not applicable
00523   */
00524 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
00525 {
00526   uint32_t tmpccmr1 = 0U;
00527   uint32_t tmpccer = 0U;
00528
00529   /* Check the parameters */
00530   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
00531   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
00532   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
00533   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
00534   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
00535   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
00536   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
00537   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
00538   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
00539   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
00540
00541   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00542   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00543
00544   /* Get the TIMx CCMR1 register value */
00545   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00546
00547   /* Get the TIMx CCER register value */
00548   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00549
00550   /* Configure TI1 */
00551   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00552   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
00553   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
00554   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
00555
00556   /* Configure TI2 */
00557   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
00558   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
00559   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
00560   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
00561
00562   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
00563   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00564   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
00565   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
00566   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00567
00568   /* Set encoder mode */
00569   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
00570
00571   /* Write to TIMx CCMR1 */
00572   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00573
00574   /* Write to TIMx CCER */
00575   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00576
00577   return SUCCESS;
00578 }
00579
00580 /**
00581   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
00582   *         structure to their default values.
00583   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
00584   * @retval None
00585   */
00586 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00587 {
00588   /* Set the default configuration */
00589   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
00590   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
00591   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
00592   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
00593 }
00594
00595 /**
00596   * @brief  Configure the Hall sensor interface of the timer instance.
00597   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
00598   *       to the TI1 input channel
00599   * @note TIMx slave mode controller is configured in reset mode.
00600           Selected internal trigger is TI1F_ED.
00601   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
00602   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
00603   *       between 2 changes on the inputs. It gives information about motor speed.
00604   * @note Channel 2 is configured in output PWM 2 mode.
00605   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
00606   * @note OC2REF is selected as trigger output on TRGO.
00607   * @param  TIMx Timer Instance
00608   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
00609   * @retval An ErrorStatus enumeration value:
00610   *          - SUCCESS: TIMx registers are de-initialized
00611   *          - ERROR: not applicable
00612   */
00613 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
00614 {
00615   uint32_t tmpcr2 = 0U;
00616   uint32_t tmpccmr1 = 0U;
00617   uint32_t tmpccer = 0U;
00618   uint32_t tmpsmcr = 0U;
00619
00620   /* Check the parameters */
00621   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
00622   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
00623   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
00624   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
00625
00626   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
00627   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
00628
00629   /* Get the TIMx CR2 register value */
00630   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00631
00632   /* Get the TIMx CCMR1 register value */
00633   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00634
00635   /* Get the TIMx CCER register value */
00636   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00637
00638   /* Get the TIMx SMCR register value */
00639   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
00640
00641   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
00642   tmpcr2 |= TIM_CR2_TI1S;
00643
00644   /* OC2REF signal is used as trigger output (TRGO) */
00645   tmpcr2 |= LL_TIM_TRGO_OC2REF;
00646
00647   /* Configure the slave mode controller */
00648   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
00649   tmpsmcr |= LL_TIM_TS_TI1F_ED;
00650   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
00651
00652   /* Configure input channel 1 */
00653   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
00654   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
00655   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
00656   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
00657
00658   /* Configure input channel 2 */
00659   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
00660   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
00661
00662   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
00663   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
00664   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
00665   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
00666
00667   /* Write to TIMx CR2 */
00668   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00669
00670   /* Write to TIMx SMCR */
00671   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
00672
00673   /* Write to TIMx CCMR1 */
00674   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00675
00676   /* Write to TIMx CCER */
00677   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00678
00679   /* Write to TIMx CCR2 */
00680   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
00681
00682   return SUCCESS;
00683 }
00684
00685 /**
00686   * @brief  Set the fields of the Break and Dead Time configuration data structure
00687   *         to their default values.
00688   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
00689   * @retval None
00690   */
00691 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00692 {
00693   /* Set the default configuration */
00694   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
00695   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
00696   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
00697   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00U;
00698   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
00699   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
00700   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
00701 }
00702
00703 /**
00704   * @brief  Configure the Break and Dead Time feature of the timer instance.
00705   * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
00706   *  depending on the LOCK configuration, it can be necessary to configure all of
00707   *  them during the first write access to the TIMx_BDTR register.
00708   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
00709   *       a timer instance provides a break input.
00710   * @param  TIMx Timer Instance
00711   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
00712   * @retval An ErrorStatus enumeration value:
00713   *          - SUCCESS: Break and Dead Time is initialized
00714   *          - ERROR: not applicable
00715   */
00716 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
00717 {
00718   uint32_t tmpbdtr = 0;
00719
00720   /* Check the parameters */
00721   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
00722   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
00723   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
00724   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
00725   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
00726   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
00727   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
00728
00729   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
00730   the OSSI State, the dead time value and the Automatic Output Enable Bit */
00731
00732   /* Set the BDTR bits */
00733   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
00734   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
00735   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
00736   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
00737   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
00738   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
00739   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
00740   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
00741
00742   /* Set TIMx_BDTR */
00743   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
00744
00745   return SUCCESS;
00746 }
00747 /**
00748   * @}
00749   */
00750
00751 /**
00752   * @}
00753   */
00754
00755 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
00756  *  @brief   Private functions
00757   * @{
00758   */
00759 /**
00760   * @brief  Configure the TIMx output channel 1.
00761   * @param  TIMx Timer Instance
00762   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
00763   * @retval An ErrorStatus enumeration value:
00764   *          - SUCCESS: TIMx registers are de-initialized
00765   *          - ERROR: not applicable
00766   */
00767 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00768 {
00769   uint32_t tmpccmr1 = 0U;
00770   uint32_t tmpccer = 0U;
00771   uint32_t tmpcr2 = 0U;
00772
00773   /* Check the parameters */
00774   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
00775   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00776   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00777   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00778   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00779   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00780
00781   /* Disable the Channel 1: Reset the CC1E Bit */
00782   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
00783
00784   /* Get the TIMx CCER register value */
00785   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
00786
00787   /* Get the TIMx CR2 register value */
00788   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00789
00790   /* Get the TIMx CCMR1 register value */
00791   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00792
00793   /* Reset Capture/Compare selection Bits */
00794   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
00795
00796   /* Set the Output Compare Mode */
00797   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
00798
00799   /* Set the Output Compare Polarity */
00800   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
00801
00802   /* Set the Output State */
00803   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
00804
00805   if (IS_TIM_BREAK_INSTANCE(TIMx))
00806   {
00807     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00808     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00809
00810     /* Set the complementary output Polarity */
00811     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
00812
00813     /* Set the complementary output State */
00814     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
00815
00816     /* Set the Output Idle state */
00817     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
00818
00819     /* Set the complementary output Idle state */
00820     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
00821   }
00822
00823   /* Write to TIMx CR2 */
00824   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00825
00826   /* Write to TIMx CCMR1 */
00827   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00828
00829   /* Set the Capture Compare Register value */
00830   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
00831
00832   /* Write to TIMx CCER */
00833   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00834
00835   return SUCCESS;
00836 }
00837
00838 /**
00839   * @brief  Configure the TIMx output channel 2.
00840   * @param  TIMx Timer Instance
00841   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
00842   * @retval An ErrorStatus enumeration value:
00843   *          - SUCCESS: TIMx registers are de-initialized
00844   *          - ERROR: not applicable
00845   */
00846 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00847 {
00848   uint32_t tmpccmr1 = 0U;
00849   uint32_t tmpccer = 0U;
00850   uint32_t tmpcr2 = 0U;
00851
00852   /* Check the parameters */
00853   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
00854   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00855   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00856   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00857   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00858   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00859
00860   /* Disable the Channel 2: Reset the CC2E Bit */
00861   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
00862
00863   /* Get the TIMx CCER register value */
00864   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00865
00866   /* Get the TIMx CR2 register value */
00867   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00868
00869   /* Get the TIMx CCMR1 register value */
00870   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
00871
00872   /* Reset Capture/Compare selection Bits */
00873   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
00874
00875   /* Select the Output Compare Mode */
00876   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
00877
00878   /* Set the Output Compare Polarity */
00879   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
00880
00881   /* Set the Output State */
00882   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
00883
00884   if (IS_TIM_BREAK_INSTANCE(TIMx))
00885   {
00886     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00887     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00888
00889     /* Set the complementary output Polarity */
00890     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
00891
00892     /* Set the complementary output State */
00893     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
00894
00895     /* Set the Output Idle state */
00896     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
00897
00898     /* Set the complementary output Idle state */
00899     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
00900   }
00901
00902   /* Write to TIMx CR2 */
00903   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00904
00905   /* Write to TIMx CCMR1 */
00906   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
00907
00908   /* Set the Capture Compare Register value */
00909   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
00910
00911   /* Write to TIMx CCER */
00912   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00913
00914   return SUCCESS;
00915 }
00916
00917 /**
00918   * @brief  Configure the TIMx output channel 3.
00919   * @param  TIMx Timer Instance
00920   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
00921   * @retval An ErrorStatus enumeration value:
00922   *          - SUCCESS: TIMx registers are de-initialized
00923   *          - ERROR: not applicable
00924   */
00925 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
00926 {
00927   uint32_t tmpccmr2 = 0U;
00928   uint32_t tmpccer = 0U;
00929   uint32_t tmpcr2 = 0U;
00930
00931   /* Check the parameters */
00932   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
00933   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
00934   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
00935   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
00936   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
00937   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
00938
00939   /* Disable the Channel 3: Reset the CC3E Bit */
00940   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
00941
00942   /* Get the TIMx CCER register value */
00943   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
00944
00945   /* Get the TIMx CR2 register value */
00946   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
00947
00948   /* Get the TIMx CCMR2 register value */
00949   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
00950
00951   /* Reset Capture/Compare selection Bits */
00952   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
00953
00954   /* Select the Output Compare Mode */
00955   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
00956
00957   /* Set the Output Compare Polarity */
00958   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
00959
00960   /* Set the Output State */
00961   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
00962
00963   if (IS_TIM_BREAK_INSTANCE(TIMx))
00964   {
00965     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
00966     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
00967
00968     /* Set the complementary output Polarity */
00969     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
00970
00971     /* Set the complementary output State */
00972     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
00973
00974     /* Set the Output Idle state */
00975     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
00976
00977     /* Set the complementary output Idle state */
00978     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
00979   }
00980
00981   /* Write to TIMx CR2 */
00982   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
00983
00984   /* Write to TIMx CCMR2 */
00985   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
00986
00987   /* Set the Capture Compare Register value */
00988   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
00989
00990   /* Write to TIMx CCER */
00991   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
00992
00993   return SUCCESS;
00994 }
00995
00996 /**
00997   * @brief  Configure the TIMx output channel 4.
00998   * @param  TIMx Timer Instance
00999   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
01000   * @retval An ErrorStatus enumeration value:
01001   *          - SUCCESS: TIMx registers are de-initialized
01002   *          - ERROR: not applicable
01003   */
01004 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
01005 {
01006   uint32_t tmpccmr2 = 0U;
01007   uint32_t tmpccer = 0U;
01008   uint32_t tmpcr2 = 0U;
01009
01010   /* Check the parameters */
01011   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01012   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
01013   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
01014   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
01015   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
01016   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
01017
01018   /* Disable the Channel 4: Reset the CC4E Bit */
01019   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
01020
01021   /* Get the TIMx CCER register value */
01022   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
01023
01024   /* Get the TIMx CR2 register value */
01025   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
01026
01027   /* Get the TIMx CCMR2 register value */
01028   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
01029
01030   /* Reset Capture/Compare selection Bits */
01031   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
01032
01033   /* Select the Output Compare Mode */
01034   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
01035
01036   /* Set the Output Compare Polarity */
01037   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
01038
01039   /* Set the Output State */
01040   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
01041
01042   if (IS_TIM_BREAK_INSTANCE(TIMx))
01043   {
01044     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
01045     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
01046
01047     /* Set the Output Idle state */
01048     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
01049   }
01050
01051   /* Write to TIMx CR2 */
01052   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
01053
01054   /* Write to TIMx CCMR2 */
01055   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
01056
01057   /* Set the Capture Compare Register value */
01058   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
01059
01060   /* Write to TIMx CCER */
01061   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
01062
01063   return SUCCESS;
01064 }
01065
01066
01067 /**
01068   * @brief  Configure the TIMx input channel 1.
01069   * @param  TIMx Timer Instance
01070   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
01071   * @retval An ErrorStatus enumeration value:
01072   *          - SUCCESS: TIMx registers are de-initialized
01073   *          - ERROR: not applicable
01074   */
01075 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01076 {
01077   /* Check the parameters */
01078   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
01079   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01080   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01081   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01082   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01083
01084   /* Disable the Channel 1: Reset the CC1E Bit */
01085   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
01086
01087   /* Select the Input and set the filter and the prescaler value */
01088   MODIFY_REG(TIMx->CCMR1,
01089              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
01090              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01091
01092   /* Select the Polarity and set the CC1E Bit */
01093   MODIFY_REG(TIMx->CCER,
01094              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
01095              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
01096
01097   return SUCCESS;
01098 }
01099
01100 /**
01101   * @brief  Configure the TIMx input channel 2.
01102   * @param  TIMx Timer Instance
01103   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
01104   * @retval An ErrorStatus enumeration value:
01105   *          - SUCCESS: TIMx registers are de-initialized
01106   *          - ERROR: not applicable
01107   */
01108 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01109 {
01110   /* Check the parameters */
01111   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
01112   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01113   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01114   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01115   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01116
01117   /* Disable the Channel 2: Reset the CC2E Bit */
01118   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
01119
01120   /* Select the Input and set the filter and the prescaler value */
01121   MODIFY_REG(TIMx->CCMR1,
01122              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
01123              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01124
01125   /* Select the Polarity and set the CC2E Bit */
01126   MODIFY_REG(TIMx->CCER,
01127              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
01128              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
01129
01130   return SUCCESS;
01131 }
01132
01133 /**
01134   * @brief  Configure the TIMx input channel 3.
01135   * @param  TIMx Timer Instance
01136   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
01137   * @retval An ErrorStatus enumeration value:
01138   *          - SUCCESS: TIMx registers are de-initialized
01139   *          - ERROR: not applicable
01140   */
01141 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01142 {
01143   /* Check the parameters */
01144   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
01145   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01146   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01147   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01148   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01149
01150   /* Disable the Channel 3: Reset the CC3E Bit */
01151   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
01152
01153   /* Select the Input and set the filter and the prescaler value */
01154   MODIFY_REG(TIMx->CCMR2,
01155              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
01156              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
01157
01158   /* Select the Polarity and set the CC3E Bit */
01159   MODIFY_REG(TIMx->CCER,
01160              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
01161              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
01162
01163   return SUCCESS;
01164 }
01165
01166 /**
01167   * @brief  Configure the TIMx input channel 4.
01168   * @param  TIMx Timer Instance
01169   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
01170   * @retval An ErrorStatus enumeration value:
01171   *          - SUCCESS: TIMx registers are de-initialized
01172   *          - ERROR: not applicable
01173   */
01174 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
01175 {
01176   /* Check the parameters */
01177   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
01178   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
01179   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
01180   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
01181   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
01182
01183   /* Disable the Channel 4: Reset the CC4E Bit */
01184   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
01185
01186   /* Select the Input and set the filter and the prescaler value */
01187   MODIFY_REG(TIMx->CCMR2,
01188              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
01189              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
01190
01191   /* Select the Polarity and set the CC4E Bit */
01192   MODIFY_REG(TIMx->CCER,
01193              TIM_CCER_CC4P,
01194              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
01195
01196   return SUCCESS;
01197 }
01198
01199
01200 /**
01201   * @}
01202   */
01203
01204 /**
01205   * @}
01206   */
01207
01208 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14  || TIM15 || TIM16 || TIM17 */
01209
01210 /**
01211   * @}
01212   */
01213
01214 #endif /* USE_FULL_LL_DRIVER */
01215
01216 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_tim.h Source File

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stm32f1xx_ll_tim.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_tim.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of TIM LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_TIM_H
00040 #define __STM32F1xx_LL_TIM_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
00054
00055 /** @defgroup TIM_LL TIM
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
00062   * @{
00063   */
00064 static const uint8_t OFFSET_TAB_CCMRx[] =
00065 {
00066   0x00U,   /* 0: TIMx_CH1  */
00067   0x00U,   /* 1: TIMx_CH1N */
00068   0x00U,   /* 2: TIMx_CH2  */
00069   0x00U,   /* 3: TIMx_CH2N */
00070   0x04U,   /* 4: TIMx_CH3  */
00071   0x04U,   /* 5: TIMx_CH3N */
00072   0x04U    /* 6: TIMx_CH4  */
00073 };
00074
00075 static const uint8_t SHIFT_TAB_OCxx[] =
00076 {
00077   0U,            /* 0: OC1M, OC1FE, OC1PE */
00078   0U,            /* 1: - NA */
00079   8U,            /* 2: OC2M, OC2FE, OC2PE */
00080   0U,            /* 3: - NA */
00081   0U,            /* 4: OC3M, OC3FE, OC3PE */
00082   0U,            /* 5: - NA */
00083   8U             /* 6: OC4M, OC4FE, OC4PE */
00084 };
00085
00086 static const uint8_t SHIFT_TAB_ICxx[] =
00087 {
00088   0U,            /* 0: CC1S, IC1PSC, IC1F */
00089   0U,            /* 1: - NA */
00090   8U,            /* 2: CC2S, IC2PSC, IC2F */
00091   0U,            /* 3: - NA */
00092   0U,            /* 4: CC3S, IC3PSC, IC3F */
00093   0U,            /* 5: - NA */
00094   8U             /* 6: CC4S, IC4PSC, IC4F */
00095 };
00096
00097 static const uint8_t SHIFT_TAB_CCxP[] =
00098 {
00099   0U,            /* 0: CC1P */
00100   2U,            /* 1: CC1NP */
00101   4U,            /* 2: CC2P */
00102   6U,            /* 3: CC2NP */
00103   8U,            /* 4: CC3P */
00104   10U,           /* 5: CC3NP */
00105   12U            /* 6: CC4P */
00106 };
00107
00108 static const uint8_t SHIFT_TAB_OISx[] =
00109 {
00110   0U,            /* 0: OIS1 */
00111   1U,            /* 1: OIS1N */
00112   2U,            /* 2: OIS2 */
00113   3U,            /* 3: OIS2N */
00114   4U,            /* 4: OIS3 */
00115   5U,            /* 5: OIS3N */
00116   6U             /* 6: OIS4 */
00117 };
00118 /**
00119   * @}
00120   */
00121
00122
00123 /* Private constants ---------------------------------------------------------*/
00124 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
00125   * @{
00126   */
00127
00128
00129
00130 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
00131 #define DT_DELAY_1 ((uint8_t)0x7FU)
00132 #define DT_DELAY_2 ((uint8_t)0x3FU)
00133 #define DT_DELAY_3 ((uint8_t)0x1FU)
00134 #define DT_DELAY_4 ((uint8_t)0x1FU)
00135
00136 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
00137 #define DT_RANGE_1 ((uint8_t)0x00U)
00138 #define DT_RANGE_2 ((uint8_t)0x80U)
00139 #define DT_RANGE_3 ((uint8_t)0xC0U)
00140 #define DT_RANGE_4 ((uint8_t)0xE0U)
00141
00142
00143 /**
00144   * @}
00145   */
00146
00147 /* Private macros ------------------------------------------------------------*/
00148 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
00149   * @{
00150   */
00151 /** @brief  Convert channel id into channel index.
00152   * @param  __CHANNEL__ This parameter can be one of the following values:
00153   *         @arg @ref LL_TIM_CHANNEL_CH1
00154   *         @arg @ref LL_TIM_CHANNEL_CH1N
00155   *         @arg @ref LL_TIM_CHANNEL_CH2
00156   *         @arg @ref LL_TIM_CHANNEL_CH2N
00157   *         @arg @ref LL_TIM_CHANNEL_CH3
00158   *         @arg @ref LL_TIM_CHANNEL_CH3N
00159   *         @arg @ref LL_TIM_CHANNEL_CH4
00160   * @retval none
00161   */
00162 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
00163 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
00164 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
00165 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
00166 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
00167 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
00168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
00169
00170 /** @brief  Calculate the deadtime sampling period(in ps).
00171   * @param  __TIMCLK__ timer input clock frequency (in Hz).
00172   * @param  __CKD__ This parameter can be one of the following values:
00173   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00174   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00175   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00176   * @retval none
00177   */
00178 #define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
00179     (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
00180      ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
00181      ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
00182 /**
00183   * @}
00184   */
00185
00186
00187 /* Exported types ------------------------------------------------------------*/
00188 #if defined(USE_FULL_LL_DRIVER)
00189 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
00190   * @{
00191   */
00192
00193 /**
00194   * @brief  TIM Time Base configuration structure definition.
00195   */
00196 typedef struct
00197 {
00198   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
00199                                    This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00200
00201                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
00202
00203   uint32_t CounterMode;       /*!< Specifies the counter mode.
00204                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
00205
00206                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
00207
00208   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
00209                                    Auto-Reload Register at the next update event.
00210                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00211                                    Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
00212
00213                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
00214
00215   uint32_t ClockDivision;     /*!< Specifies the clock division.
00216                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
00217
00218                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
00219
00220   uint8_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
00221                                    reaches zero, an update event is generated and counting restarts
00222                                    from the RCR value (N).
00223                                    This means in PWM mode that (N+1) corresponds to:
00224                                       - the number of PWM periods in edge-aligned mode
00225                                       - the number of half PWM period in center-aligned mode
00226                                    This parameter must be a number between 0x00 and 0xFF.
00227
00228                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
00229 } LL_TIM_InitTypeDef;
00230
00231 /**
00232   * @brief  TIM Output Compare configuration structure definition.
00233   */
00234 typedef struct
00235 {
00236   uint32_t OCMode;        /*!< Specifies the output mode.
00237                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
00238
00239                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
00240
00241   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
00242                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00243
00244                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00245
00246   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
00247                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
00248
00249                                This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
00250
00251   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
00252                                This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
00253
00254                                This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
00255
00256   uint32_t OCPolarity;    /*!< Specifies the output polarity.
00257                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00258
00259                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00260
00261   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
00262                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
00263
00264                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
00265
00266
00267   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
00268                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00269
00270                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00271
00272   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
00273                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
00274
00275                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
00276 } LL_TIM_OC_InitTypeDef;
00277
00278 /**
00279   * @brief  TIM Input Capture configuration structure definition.
00280   */
00281
00282 typedef struct
00283 {
00284
00285   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
00286                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00287
00288                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00289
00290   uint32_t ICActiveInput; /*!< Specifies the input.
00291                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00292
00293                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00294
00295   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
00296                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00297
00298                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00299
00300   uint32_t ICFilter;      /*!< Specifies the input capture filter.
00301                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00302
00303                                This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00304 } LL_TIM_IC_InitTypeDef;
00305
00306
00307 /**
00308   * @brief  TIM Encoder interface configuration structure definition.
00309   */
00310 typedef struct
00311 {
00312   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
00313                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
00314
00315                                  This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
00316
00317   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
00318                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00319
00320                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00321
00322   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
00323                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00324
00325                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00326
00327   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
00328                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00329
00330                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00331
00332   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
00333                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00334
00335                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00336
00337   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
00338                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00339
00340                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00341
00342   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
00343                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
00344
00345                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
00346
00347   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
00348                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00349
00350                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00351
00352   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
00353                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00354
00355                                  This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00356
00357 } LL_TIM_ENCODER_InitTypeDef;
00358
00359 /**
00360   * @brief  TIM Hall sensor interface configuration structure definition.
00361   */
00362 typedef struct
00363 {
00364
00365   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
00366                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
00367
00368                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
00369
00370   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
00371                                     Prescaler must be set to get a maximum counter period longer than the
00372                                     time interval between 2 consecutive changes on the Hall inputs.
00373                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
00374
00375                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
00376
00377   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
00378                                     This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
00379
00380                                     This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
00381
00382   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
00383                                     A positive pulse (TRGO event) is generated with a programmable delay every time
00384                                     a change occurs on the Hall inputs.
00385                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
00386
00387                                     This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
00388 } LL_TIM_HALLSENSOR_InitTypeDef;
00389
00390 /**
00391   * @brief  BDTR (Break and Dead Time) structure definition
00392   */
00393 typedef struct
00394 {
00395   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
00396                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
00397
00398                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
00399
00400                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
00401
00402   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
00403                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
00404
00405                                       This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
00406
00407                                       @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
00408
00409   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
00410                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
00411
00412                                       @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
00413                                             has been written, their content is frozen until the next reset.*/
00414
00415   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
00416                                       switching-on of the outputs.
00417                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
00418
00419                                       This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
00420
00421                                       @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
00422
00423   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
00424                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
00425
00426                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
00427
00428                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00429
00430   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
00431                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
00432
00433                                       This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
00434
00435                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00436
00437   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
00438                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
00439
00440                                       This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
00441
00442                                       @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
00443 } LL_TIM_BDTR_InitTypeDef;
00444
00445 /**
00446   * @}
00447   */
00448 #endif /* USE_FULL_LL_DRIVER */
00449
00450 /* Exported constants --------------------------------------------------------*/
00451 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
00452   * @{
00453   */
00454
00455 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
00456   * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
00457   * @{
00458   */
00459 #define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
00460 #define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
00461 #define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
00462 #define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
00463 #define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
00464 #define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
00465 #define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
00466 #define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
00467 #define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
00468 #define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
00469 #define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
00470 #define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
00471 /**
00472   * @}
00473   */
00474
00475 #if defined(USE_FULL_LL_DRIVER)
00476 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
00477   * @{
00478   */
00479 #define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
00480 #define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
00481 /**
00482   * @}
00483   */
00484
00485 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
00486   * @{
00487   */
00488 #define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
00489 #define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
00490 /**
00491   * @}
00492   */
00493 #endif /* USE_FULL_LL_DRIVER */
00494
00495 /** @defgroup TIM_LL_EC_IT IT Defines
00496   * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
00497   * @{
00498   */
00499 #define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
00500 #define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
00501 #define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
00502 #define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
00503 #define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
00504 #define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
00505 #define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
00506 #define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
00507 /**
00508   * @}
00509   */
00510
00511 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
00512   * @{
00513   */
00514 #define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
00515 #define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
00516 /**
00517   * @}
00518   */
00519
00520 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
00521   * @{
00522   */
00523 #define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter is not stopped at update event */
00524 #define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter stops counting at the next update event */
00525 /**
00526   * @}
00527   */
00528
00529 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
00530   * @{
00531   */
00532 #define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
00533 #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
00534 #define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
00535 #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
00536 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
00537 /**
00538   * @}
00539   */
00540
00541 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
00542   * @{
00543   */
00544 #define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
00545 #define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
00546 #define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
00547 /**
00548   * @}
00549   */
00550
00551 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
00552   * @{
00553   */
00554 #define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
00555 #define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
00556 /**
00557   * @}
00558   */
00559
00560 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
00561   * @{
00562   */
00563 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
00564 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
00565 /**
00566   * @}
00567   */
00568
00569 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
00570   * @{
00571   */
00572 #define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
00573 #define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
00574 /**
00575   * @}
00576   */
00577
00578 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
00579   * @{
00580   */
00581 #define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
00582 #define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
00583 #define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
00584 #define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
00585 /**
00586   * @}
00587   */
00588
00589 /** @defgroup TIM_LL_EC_CHANNEL Channel
00590   * @{
00591   */
00592 #define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
00593 #define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
00594 #define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
00595 #define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
00596 #define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
00597 #define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
00598 #define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
00599 /**
00600   * @}
00601   */
00602
00603 #if defined(USE_FULL_LL_DRIVER)
00604 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
00605   * @{
00606   */
00607 #define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
00608 #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
00609 /**
00610   * @}
00611   */
00612 #endif /* USE_FULL_LL_DRIVER */
00613
00614 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
00615   * @{
00616   */
00617 #define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
00618 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
00619 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
00620 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
00621 #define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                       /*!<OCyREF is forced low*/
00622 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
00623 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
00624 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
00625 /**
00626   * @}
00627   */
00628
00629 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
00630   * @{
00631   */
00632 #define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
00633 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
00634 /**
00635   * @}
00636   */
00637
00638 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
00639   * @{
00640   */
00641 #define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
00642 #define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
00643 /**
00644   * @}
00645   */
00646
00647
00648 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
00649   * @{
00650   */
00651 #define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
00652 #define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
00653 #define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
00654 /**
00655   * @}
00656   */
00657
00658 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
00659   * @{
00660   */
00661 #define LL_TIM_ICPSC_DIV1                      0x00000000U                              /*!< No prescaler, capture is done each time an edge is detected on the capture input */
00662 #define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
00663 #define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
00664 #define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
00665 /**
00666   * @}
00667   */
00668
00669 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
00670   * @{
00671   */
00672 #define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
00673 #define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
00674 #define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
00675 #define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
00676 #define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
00677 #define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
00678 #define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
00679 #define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
00680 #define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
00681 #define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
00682 #define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
00683 #define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
00684 #define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
00685 #define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
00686 #define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
00687 #define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
00688 /**
00689   * @}
00690   */
00691
00692 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
00693   * @{
00694   */
00695 #define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
00696 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
00697 /**
00698   * @}
00699   */
00700
00701 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
00702   * @{
00703   */
00704 #define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
00705 #define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected inpu t*/
00706 #define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
00707 /**
00708   * @}
00709   */
00710
00711 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
00712   * @{
00713   */
00714 #define LL_TIM_ENCODERMODE_X2_TI1              TIM_SMCR_SMS_0                    /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
00715 #define LL_TIM_ENCODERMODE_X2_TI2              TIM_SMCR_SMS_1                    /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
00716 #define LL_TIM_ENCODERMODE_X4_TI12             (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges                                                                                                                                                                   depending on the level of the other input l */
00717 /**
00718   * @}
00719   */
00720
00721 /** @defgroup TIM_LL_EC_TRGO Trigger Output
00722   * @{
00723   */
00724 #define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
00725 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
00726 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
00727 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
00728 #define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
00729 #define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
00730 #define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
00731 #define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
00732 /**
00733   * @}
00734   */
00735
00736
00737 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
00738   * @{
00739   */
00740 #define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
00741 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
00742 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
00743 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
00744 /**
00745   * @}
00746   */
00747
00748 /** @defgroup TIM_LL_EC_TS Trigger Selection
00749   * @{
00750   */
00751 #define LL_TIM_TS_ITR0                         0x00000000U                                      /*!< Internal Trigger 0 (ITR0) is used as trigger input */
00752 #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                    /*!< Internal Trigger 1 (ITR1) is used as trigger input */
00753 #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                    /*!< Internal Trigger 2 (ITR2) is used as trigger input */
00754 #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                  /*!< Internal Trigger 3 (ITR3) is used as trigger input */
00755 #define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                    /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
00756 #define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                  /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
00757 #define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                  /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
00758 #define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)  /*!< Filtered external Trigger (ETRF) is used as trigger input */
00759 /**
00760   * @}
00761   */
00762
00763 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
00764   * @{
00765   */
00766 #define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
00767 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
00768 /**
00769   * @}
00770   */
00771
00772 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
00773   * @{
00774   */
00775 #define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
00776 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
00777 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
00778 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
00779 /**
00780   * @}
00781   */
00782
00783 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
00784   * @{
00785   */
00786 #define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
00787 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
00788 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
00789 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
00790 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
00791 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
00792 #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
00793 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
00794 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
00795 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
00796 #define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
00797 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
00798 #define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
00799 #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
00800 #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
00801 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
00802 /**
00803   * @}
00804   */
00805
00806
00807 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
00808   * @{
00809   */
00810 #define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
00811 #define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
00812 /**
00813   * @}
00814   */
00815
00816
00817
00818
00819 /** @defgroup TIM_LL_EC_OSSI OSSI
00820   * @{
00821   */
00822 #define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
00823 #define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
00824 /**
00825   * @}
00826   */
00827
00828 /** @defgroup TIM_LL_EC_OSSR OSSR
00829   * @{
00830   */
00831 #define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
00832 #define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
00833 /**
00834   * @}
00835   */
00836
00837
00838 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
00839   * @{
00840   */
00841 #define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
00842 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
00843 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
00844 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
00845 #define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
00846 #define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
00847 #define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
00848 #define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
00849 #define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
00850 #define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
00851 #define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
00852 #define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
00853 #define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
00854 #define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
00855 #define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
00856 #define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
00857 #define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
00858 #define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
00859 /**
00860   * @}
00861   */
00862
00863 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
00864   * @{
00865   */
00866 #define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
00867 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
00868 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
00869 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
00870 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
00871 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
00872 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
00873 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
00874 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
00875 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
00876 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
00877 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
00878 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
00879 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
00880 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
00881 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
00882 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
00883 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
00884 /**
00885   * @}
00886   */
00887
00888
00889
00890 /**
00891   * @}
00892   */
00893
00894 /* Exported macro ------------------------------------------------------------*/
00895 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
00896   * @{
00897   */
00898
00899 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
00900   * @{
00901   */
00902 /**
00903   * @brief  Write a value in TIM register.
00904   * @param  __INSTANCE__ TIM Instance
00905   * @param  __REG__ Register to be written
00906   * @param  __VALUE__ Value to be written in the register
00907   * @retval None
00908   */
00909 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00910
00911 /**
00912   * @brief  Read a value in TIM register.
00913   * @param  __INSTANCE__ TIM Instance
00914   * @param  __REG__ Register to be read
00915   * @retval Register value
00916   */
00917 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00918 /**
00919   * @}
00920   */
00921
00922 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
00923   * @{
00924   */
00925
00926 /**
00927   * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
00928   * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
00929   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00930   * @param  __CKD__ This parameter can be one of the following values:
00931   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
00932   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
00933   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
00934   * @param  __DT__ deadtime duration (in ns)
00935   * @retval DTG[0:7]
00936   */
00937 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
00938     ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))           ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
00939       (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
00940       (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
00941       (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
00942        0U)
00943
00944 /**
00945   * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
00946   * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
00947   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00948   * @param  __CNTCLK__ counter clock frequency (in Hz)
00949   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
00950   */
00951 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
00952    ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
00953
00954 /**
00955   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
00956   * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
00957   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00958   * @param  __PSC__ prescaler
00959   * @param  __FREQ__ output signal frequency (in Hz)
00960   * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
00961   */
00962 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
00963      (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
00964
00965 /**
00966   * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
00967   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
00968   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00969   * @param  __PSC__ prescaler
00970   * @param  __DELAY__ timer output compare active/inactive delay (in us)
00971   * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
00972   */
00973 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
00974 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
00975           / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
00976
00977 /**
00978   * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
00979   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
00980   * @param  __TIMCLK__ timer input clock frequency (in Hz)
00981   * @param  __PSC__ prescaler
00982   * @param  __DELAY__ timer output compare active/inactive delay (in us)
00983   * @param  __PULSE__ pulse duration (in us)
00984   * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
00985   */
00986 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
00987  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
00988            + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
00989
00990 /**
00991   * @brief  HELPER macro retrieving the ratio of the input capture prescaler
00992   * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
00993   * @param  __ICPSC__ This parameter can be one of the following values:
00994   *         @arg @ref LL_TIM_ICPSC_DIV1
00995   *         @arg @ref LL_TIM_ICPSC_DIV2
00996   *         @arg @ref LL_TIM_ICPSC_DIV4
00997   *         @arg @ref LL_TIM_ICPSC_DIV8
00998   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
00999   */
01000 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
01001    ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
01002
01003
01004 /**
01005   * @}
01006   */
01007
01008
01009 /**
01010   * @}
01011   */
01012
01013 /* Exported functions --------------------------------------------------------*/
01014 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
01015   * @{
01016   */
01017
01018 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
01019   * @{
01020   */
01021 /**
01022   * @brief  Enable timer counter.
01023   * @rmtoll CR1          CEN           LL_TIM_EnableCounter
01024   * @param  TIMx Timer instance
01025   * @retval None
01026   */
01027 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
01028 {
01029   SET_BIT(TIMx->CR1, TIM_CR1_CEN);
01030 }
01031
01032 /**
01033   * @brief  Disable timer counter.
01034   * @rmtoll CR1          CEN           LL_TIM_DisableCounter
01035   * @param  TIMx Timer instance
01036   * @retval None
01037   */
01038 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
01039 {
01040   CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
01041 }
01042
01043 /**
01044   * @brief  Indicates whether the timer counter is enabled.
01045   * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
01046   * @param  TIMx Timer instance
01047   * @retval State of bit (1 or 0).
01048   */
01049 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
01050 {
01051   return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
01052 }
01053
01054 /**
01055   * @brief  Enable update event generation.
01056   * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
01057   * @param  TIMx Timer instance
01058   * @retval None
01059   */
01060 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
01061 {
01062   SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
01063 }
01064
01065 /**
01066   * @brief  Disable update event generation.
01067   * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
01068   * @param  TIMx Timer instance
01069   * @retval None
01070   */
01071 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
01072 {
01073   CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
01074 }
01075
01076 /**
01077   * @brief  Indicates whether update event generation is enabled.
01078   * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
01079   * @param  TIMx Timer instance
01080   * @retval State of bit (1 or 0).
01081   */
01082 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
01083 {
01084   return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
01085 }
01086
01087 /**
01088   * @brief  Set update event source
01089   * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
01090   *       generate an update interrupt or DMA request if enabled:
01091   *        - Counter overflow/underflow
01092   *        - Setting the UG bit
01093   *        - Update generation through the slave mode controller
01094   * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
01095   *       overflow/underflow generates an update interrupt or DMA request if enabled.
01096   * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
01097   * @param  TIMx Timer instance
01098   * @param  UpdateSource This parameter can be one of the following values:
01099   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01100   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01101   * @retval None
01102   */
01103 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
01104 {
01105   MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
01106 }
01107
01108 /**
01109   * @brief  Get actual event update source
01110   * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
01111   * @param  TIMx Timer instance
01112   * @retval Returned value can be one of the following values:
01113   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
01114   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
01115   */
01116 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
01117 {
01118   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
01119 }
01120
01121 /**
01122   * @brief  Set one pulse mode (one shot v.s. repetitive).
01123   * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
01124   * @param  TIMx Timer instance
01125   * @param  OnePulseMode This parameter can be one of the following values:
01126   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01127   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01128   * @retval None
01129   */
01130 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
01131 {
01132   MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
01133 }
01134
01135 /**
01136   * @brief  Get actual one pulse mode.
01137   * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
01138   * @param  TIMx Timer instance
01139   * @retval Returned value can be one of the following values:
01140   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
01141   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
01142   */
01143 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
01144 {
01145   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
01146 }
01147
01148 /**
01149   * @brief  Set the timer counter counting mode.
01150   * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01151   *       check whether or not the counter mode selection feature is supported
01152   *       by a timer instance.
01153   * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
01154   *         CR1          CMS           LL_TIM_SetCounterMode
01155   * @param  TIMx Timer instance
01156   * @param  CounterMode This parameter can be one of the following values:
01157   *         @arg @ref LL_TIM_COUNTERMODE_UP
01158   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01159   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01160   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01161   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01162   * @retval None
01163   */
01164 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
01165 {
01166   MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
01167 }
01168
01169 /**
01170   * @brief  Get actual counter mode.
01171   * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
01172   *       check whether or not the counter mode selection feature is supported
01173   *       by a timer instance.
01174   * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
01175   *         CR1          CMS           LL_TIM_GetCounterMode
01176   * @param  TIMx Timer instance
01177   * @retval Returned value can be one of the following values:
01178   *         @arg @ref LL_TIM_COUNTERMODE_UP
01179   *         @arg @ref LL_TIM_COUNTERMODE_DOWN
01180   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
01181   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
01182   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
01183   */
01184 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
01185 {
01186   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
01187 }
01188
01189 /**
01190   * @brief  Enable auto-reload (ARR) preload.
01191   * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
01192   * @param  TIMx Timer instance
01193   * @retval None
01194   */
01195 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
01196 {
01197   SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
01198 }
01199
01200 /**
01201   * @brief  Disable auto-reload (ARR) preload.
01202   * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
01203   * @param  TIMx Timer instance
01204   * @retval None
01205   */
01206 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
01207 {
01208   CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
01209 }
01210
01211 /**
01212   * @brief  Indicates whether auto-reload (ARR) preload is enabled.
01213   * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
01214   * @param  TIMx Timer instance
01215   * @retval State of bit (1 or 0).
01216   */
01217 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
01218 {
01219   return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
01220 }
01221
01222 /**
01223   * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01224   * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01225   *       whether or not the clock division feature is supported by the timer
01226   *       instance.
01227   * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
01228   * @param  TIMx Timer instance
01229   * @param  ClockDivision This parameter can be one of the following values:
01230   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01231   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01232   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01233   * @retval None
01234   */
01235 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
01236 {
01237   MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
01238 }
01239
01240 /**
01241   * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
01242   * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
01243   *       whether or not the clock division feature is supported by the timer
01244   *       instance.
01245   * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
01246   * @param  TIMx Timer instance
01247   * @retval Returned value can be one of the following values:
01248   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
01249   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
01250   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
01251   */
01252 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
01253 {
01254   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
01255 }
01256
01257 /**
01258   * @brief  Set the counter value.
01259   * @rmtoll CNT          CNT           LL_TIM_SetCounter
01260   * @param  TIMx Timer instance
01261   * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
01262   * @retval None
01263   */
01264 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
01265 {
01266   WRITE_REG(TIMx->CNT, Counter);
01267 }
01268
01269 /**
01270   * @brief  Get the counter value.
01271   * @rmtoll CNT          CNT           LL_TIM_GetCounter
01272   * @param  TIMx Timer instance
01273   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
01274   */
01275 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
01276 {
01277   return (uint32_t)(READ_REG(TIMx->CNT));
01278 }
01279
01280 /**
01281   * @brief  Get the current direction of the counter
01282   * @rmtoll CR1          DIR           LL_TIM_GetDirection
01283   * @param  TIMx Timer instance
01284   * @retval Returned value can be one of the following values:
01285   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
01286   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
01287   */
01288 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
01289 {
01290   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
01291 }
01292
01293 /**
01294   * @brief  Set the prescaler value.
01295   * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
01296   * @note The prescaler can be changed on the fly as this control register is buffered. The new
01297   *       prescaler ratio is taken into account at the next update event.
01298   * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
01299   * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
01300   * @param  TIMx Timer instance
01301   * @param  Prescaler between Min_Data=0 and Max_Data=65535
01302   * @retval None
01303   */
01304 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
01305 {
01306   WRITE_REG(TIMx->PSC, Prescaler);
01307 }
01308
01309 /**
01310   * @brief  Get the prescaler value.
01311   * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
01312   * @param  TIMx Timer instance
01313   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
01314   */
01315 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
01316 {
01317   return (uint32_t)(READ_REG(TIMx->PSC));
01318 }
01319
01320 /**
01321   * @brief  Set the auto-reload value.
01322   * @note The counter is blocked while the auto-reload value is null.
01323   * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
01324   * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
01325   * @param  TIMx Timer instance
01326   * @param  AutoReload between Min_Data=0 and Max_Data=65535
01327   * @retval None
01328   */
01329 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
01330 {
01331   WRITE_REG(TIMx->ARR, AutoReload);
01332 }
01333
01334 /**
01335   * @brief  Get the auto-reload value.
01336   * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
01337   * @param  TIMx Timer instance
01338   * @retval Auto-reload value
01339   */
01340 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
01341 {
01342   return (uint32_t)(READ_REG(TIMx->ARR));
01343 }
01344
01345 /**
01346   * @brief  Set the repetition counter value.
01347   * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01348   *       whether or not a timer instance supports a repetition counter.
01349   * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
01350   * @param  TIMx Timer instance
01351   * @param  RepetitionCounter between Min_Data=0 and Max_Data=255
01352   * @retval None
01353   */
01354 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
01355 {
01356   WRITE_REG(TIMx->RCR, RepetitionCounter);
01357 }
01358
01359 /**
01360   * @brief  Get the repetition counter value.
01361   * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
01362   *       whether or not a timer instance supports a repetition counter.
01363   * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
01364   * @param  TIMx Timer instance
01365   * @retval Repetition counter value
01366   */
01367 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
01368 {
01369   return (uint32_t)(READ_REG(TIMx->RCR));
01370 }
01371
01372 /**
01373   * @}
01374   */
01375
01376 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
01377   * @{
01378   */
01379 /**
01380   * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01381   * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
01382   *       they are updated only when a commutation event (COM) occurs.
01383   * @note Only on channels that have a complementary output.
01384   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01385   *       whether or not a timer instance is able to generate a commutation event.
01386   * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
01387   * @param  TIMx Timer instance
01388   * @retval None
01389   */
01390 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
01391 {
01392   SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
01393 }
01394
01395 /**
01396   * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
01397   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01398   *       whether or not a timer instance is able to generate a commutation event.
01399   * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
01400   * @param  TIMx Timer instance
01401   * @retval None
01402   */
01403 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
01404 {
01405   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
01406 }
01407
01408 /**
01409   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
01410   * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
01411   *       whether or not a timer instance is able to generate a commutation event.
01412   * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
01413   * @param  TIMx Timer instance
01414   * @param  CCUpdateSource This parameter can be one of the following values:
01415   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
01416   *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
01417   * @retval None
01418   */
01419 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
01420 {
01421   MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
01422 }
01423
01424 /**
01425   * @brief  Set the trigger of the capture/compare DMA request.
01426   * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
01427   * @param  TIMx Timer instance
01428   * @param  DMAReqTrigger This parameter can be one of the following values:
01429   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01430   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01431   * @retval None
01432   */
01433 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
01434 {
01435   MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
01436 }
01437
01438 /**
01439   * @brief  Get actual trigger of the capture/compare DMA request.
01440   * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
01441   * @param  TIMx Timer instance
01442   * @retval Returned value can be one of the following values:
01443   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
01444   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
01445   */
01446 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
01447 {
01448   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
01449 }
01450
01451 /**
01452   * @brief  Set the lock level to freeze the
01453   *         configuration of several capture/compare parameters.
01454   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
01455   *       the lock mechanism is supported by a timer instance.
01456   * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
01457   * @param  TIMx Timer instance
01458   * @param  LockLevel This parameter can be one of the following values:
01459   *         @arg @ref LL_TIM_LOCKLEVEL_OFF
01460   *         @arg @ref LL_TIM_LOCKLEVEL_1
01461   *         @arg @ref LL_TIM_LOCKLEVEL_2
01462   *         @arg @ref LL_TIM_LOCKLEVEL_3
01463   * @retval None
01464   */
01465 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
01466 {
01467   MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
01468 }
01469
01470 /**
01471   * @brief  Enable capture/compare channels.
01472   * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
01473   *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
01474   *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
01475   *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
01476   *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
01477   *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
01478   *         CCER         CC4E          LL_TIM_CC_EnableChannel
01479   * @param  TIMx Timer instance
01480   * @param  Channels This parameter can be a combination of the following values:
01481   *         @arg @ref LL_TIM_CHANNEL_CH1
01482   *         @arg @ref LL_TIM_CHANNEL_CH1N
01483   *         @arg @ref LL_TIM_CHANNEL_CH2
01484   *         @arg @ref LL_TIM_CHANNEL_CH2N
01485   *         @arg @ref LL_TIM_CHANNEL_CH3
01486   *         @arg @ref LL_TIM_CHANNEL_CH3N
01487   *         @arg @ref LL_TIM_CHANNEL_CH4
01488   * @retval None
01489   */
01490 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01491 {
01492   SET_BIT(TIMx->CCER, Channels);
01493 }
01494
01495 /**
01496   * @brief  Disable capture/compare channels.
01497   * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
01498   *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
01499   *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
01500   *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
01501   *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
01502   *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
01503   *         CCER         CC4E          LL_TIM_CC_DisableChannel
01504   * @param  TIMx Timer instance
01505   * @param  Channels This parameter can be a combination of the following values:
01506   *         @arg @ref LL_TIM_CHANNEL_CH1
01507   *         @arg @ref LL_TIM_CHANNEL_CH1N
01508   *         @arg @ref LL_TIM_CHANNEL_CH2
01509   *         @arg @ref LL_TIM_CHANNEL_CH2N
01510   *         @arg @ref LL_TIM_CHANNEL_CH3
01511   *         @arg @ref LL_TIM_CHANNEL_CH3N
01512   *         @arg @ref LL_TIM_CHANNEL_CH4
01513   * @retval None
01514   */
01515 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01516 {
01517   CLEAR_BIT(TIMx->CCER, Channels);
01518 }
01519
01520 /**
01521   * @brief  Indicate whether channel(s) is(are) enabled.
01522   * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
01523   *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
01524   *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
01525   *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
01526   *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
01527   *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
01528   *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel
01529   * @param  TIMx Timer instance
01530   * @param  Channels This parameter can be a combination of the following values:
01531   *         @arg @ref LL_TIM_CHANNEL_CH1
01532   *         @arg @ref LL_TIM_CHANNEL_CH1N
01533   *         @arg @ref LL_TIM_CHANNEL_CH2
01534   *         @arg @ref LL_TIM_CHANNEL_CH2N
01535   *         @arg @ref LL_TIM_CHANNEL_CH3
01536   *         @arg @ref LL_TIM_CHANNEL_CH3N
01537   *         @arg @ref LL_TIM_CHANNEL_CH4
01538   * @retval State of bit (1 or 0).
01539   */
01540 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
01541 {
01542   return (READ_BIT(TIMx->CCER, Channels) == (Channels));
01543 }
01544
01545 /**
01546   * @}
01547   */
01548
01549 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
01550   * @{
01551   */
01552 /**
01553   * @brief  Configure an output channel.
01554   * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
01555   *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
01556   *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
01557   *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
01558   *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
01559   *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
01560   *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
01561   *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
01562   *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
01563   *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
01564   *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
01565   *         CR2          OIS4          LL_TIM_OC_ConfigOutput
01566   * @param  TIMx Timer instance
01567   * @param  Channel This parameter can be one of the following values:
01568   *         @arg @ref LL_TIM_CHANNEL_CH1
01569   *         @arg @ref LL_TIM_CHANNEL_CH2
01570   *         @arg @ref LL_TIM_CHANNEL_CH3
01571   *         @arg @ref LL_TIM_CHANNEL_CH4
01572   * @param  Configuration This parameter must be a combination of all the following values:
01573   *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
01574   *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
01575   * @retval None
01576   */
01577 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
01578 {
01579   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01580   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01581   CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
01582   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
01583              (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
01584   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
01585              (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
01586 }
01587
01588 /**
01589   * @brief  Define the behavior of the output reference signal OCxREF from which
01590   *         OCx and OCxN (when relevant) are derived.
01591   * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
01592   *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
01593   *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
01594   *         CCMR2        OC4M          LL_TIM_OC_SetMode
01595   * @param  TIMx Timer instance
01596   * @param  Channel This parameter can be one of the following values:
01597   *         @arg @ref LL_TIM_CHANNEL_CH1
01598   *         @arg @ref LL_TIM_CHANNEL_CH2
01599   *         @arg @ref LL_TIM_CHANNEL_CH3
01600   *         @arg @ref LL_TIM_CHANNEL_CH4
01601   * @param  Mode This parameter can be one of the following values:
01602   *         @arg @ref LL_TIM_OCMODE_FROZEN
01603   *         @arg @ref LL_TIM_OCMODE_ACTIVE
01604   *         @arg @ref LL_TIM_OCMODE_INACTIVE
01605   *         @arg @ref LL_TIM_OCMODE_TOGGLE
01606   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
01607   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
01608   *         @arg @ref LL_TIM_OCMODE_PWM1
01609   *         @arg @ref LL_TIM_OCMODE_PWM2
01610   * @retval None
01611   */
01612 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
01613 {
01614   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01615   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01616   MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
01617 }
01618
01619 /**
01620   * @brief  Get the output compare mode of an output channel.
01621   * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
01622   *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
01623   *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
01624   *         CCMR2        OC4M          LL_TIM_OC_GetMode
01625   * @param  TIMx Timer instance
01626   * @param  Channel This parameter can be one of the following values:
01627   *         @arg @ref LL_TIM_CHANNEL_CH1
01628   *         @arg @ref LL_TIM_CHANNEL_CH2
01629   *         @arg @ref LL_TIM_CHANNEL_CH3
01630   *         @arg @ref LL_TIM_CHANNEL_CH4
01631   * @retval Returned value can be one of the following values:
01632   *         @arg @ref LL_TIM_OCMODE_FROZEN
01633   *         @arg @ref LL_TIM_OCMODE_ACTIVE
01634   *         @arg @ref LL_TIM_OCMODE_INACTIVE
01635   *         @arg @ref LL_TIM_OCMODE_TOGGLE
01636   *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
01637   *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
01638   *         @arg @ref LL_TIM_OCMODE_PWM1
01639   *         @arg @ref LL_TIM_OCMODE_PWM2
01640   */
01641 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
01642 {
01643   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01644   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01645   return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
01646 }
01647
01648 /**
01649   * @brief  Set the polarity of an output channel.
01650   * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
01651   *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
01652   *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
01653   *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
01654   *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
01655   *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
01656   *         CCER         CC4P          LL_TIM_OC_SetPolarity
01657   * @param  TIMx Timer instance
01658   * @param  Channel This parameter can be one of the following values:
01659   *         @arg @ref LL_TIM_CHANNEL_CH1
01660   *         @arg @ref LL_TIM_CHANNEL_CH1N
01661   *         @arg @ref LL_TIM_CHANNEL_CH2
01662   *         @arg @ref LL_TIM_CHANNEL_CH2N
01663   *         @arg @ref LL_TIM_CHANNEL_CH3
01664   *         @arg @ref LL_TIM_CHANNEL_CH3N
01665   *         @arg @ref LL_TIM_CHANNEL_CH4
01666   * @param  Polarity This parameter can be one of the following values:
01667   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
01668   *         @arg @ref LL_TIM_OCPOLARITY_LOW
01669   * @retval None
01670   */
01671 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
01672 {
01673   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01674   MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
01675 }
01676
01677 /**
01678   * @brief  Get the polarity of an output channel.
01679   * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
01680   *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
01681   *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
01682   *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
01683   *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
01684   *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
01685   *         CCER         CC4P          LL_TIM_OC_GetPolarity
01686   * @param  TIMx Timer instance
01687   * @param  Channel This parameter can be one of the following values:
01688   *         @arg @ref LL_TIM_CHANNEL_CH1
01689   *         @arg @ref LL_TIM_CHANNEL_CH1N
01690   *         @arg @ref LL_TIM_CHANNEL_CH2
01691   *         @arg @ref LL_TIM_CHANNEL_CH2N
01692   *         @arg @ref LL_TIM_CHANNEL_CH3
01693   *         @arg @ref LL_TIM_CHANNEL_CH3N
01694   *         @arg @ref LL_TIM_CHANNEL_CH4
01695   * @retval Returned value can be one of the following values:
01696   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
01697   *         @arg @ref LL_TIM_OCPOLARITY_LOW
01698   */
01699 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
01700 {
01701   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01702   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
01703 }
01704
01705 /**
01706   * @brief  Set the IDLE state of an output channel
01707   * @note This function is significant only for the timer instances
01708   *       supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
01709   *       can be used to check whether or not a timer instance provides
01710   *       a break input.
01711   * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
01712   *         CR2         OIS1N         LL_TIM_OC_SetIdleState\n
01713   *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
01714   *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
01715   *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
01716   *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
01717   *         CR2         OIS4          LL_TIM_OC_SetIdleState
01718   * @param  TIMx Timer instance
01719   * @param  Channel This parameter can be one of the following values:
01720   *         @arg @ref LL_TIM_CHANNEL_CH1
01721   *         @arg @ref LL_TIM_CHANNEL_CH1N
01722   *         @arg @ref LL_TIM_CHANNEL_CH2
01723   *         @arg @ref LL_TIM_CHANNEL_CH2N
01724   *         @arg @ref LL_TIM_CHANNEL_CH3
01725   *         @arg @ref LL_TIM_CHANNEL_CH3N
01726   *         @arg @ref LL_TIM_CHANNEL_CH4
01727   * @param  IdleState This parameter can be one of the following values:
01728   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
01729   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
01730   * @retval None
01731   */
01732 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
01733 {
01734   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01735   MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
01736 }
01737
01738 /**
01739   * @brief  Get the IDLE state of an output channel
01740   * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
01741   *         CR2         OIS1N         LL_TIM_OC_GetIdleState\n
01742   *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
01743   *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
01744   *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
01745   *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
01746   *         CR2         OIS4          LL_TIM_OC_GetIdleState
01747   * @param  TIMx Timer instance
01748   * @param  Channel This parameter can be one of the following values:
01749   *         @arg @ref LL_TIM_CHANNEL_CH1
01750   *         @arg @ref LL_TIM_CHANNEL_CH1N
01751   *         @arg @ref LL_TIM_CHANNEL_CH2
01752   *         @arg @ref LL_TIM_CHANNEL_CH2N
01753   *         @arg @ref LL_TIM_CHANNEL_CH3
01754   *         @arg @ref LL_TIM_CHANNEL_CH3N
01755   *         @arg @ref LL_TIM_CHANNEL_CH4
01756   * @retval Returned value can be one of the following values:
01757   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
01758   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
01759   */
01760 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
01761 {
01762   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01763   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
01764 }
01765
01766 /**
01767   * @brief  Enable fast mode for the output channel.
01768   * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
01769   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
01770   *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
01771   *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
01772   *         CCMR2        OC4FE          LL_TIM_OC_EnableFast
01773   * @param  TIMx Timer instance
01774   * @param  Channel This parameter can be one of the following values:
01775   *         @arg @ref LL_TIM_CHANNEL_CH1
01776   *         @arg @ref LL_TIM_CHANNEL_CH2
01777   *         @arg @ref LL_TIM_CHANNEL_CH3
01778   *         @arg @ref LL_TIM_CHANNEL_CH4
01779   * @retval None
01780   */
01781 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
01782 {
01783   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01784   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01785   SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
01786
01787 }
01788
01789 /**
01790   * @brief  Disable fast mode for the output channel.
01791   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
01792   *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
01793   *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
01794   *         CCMR2        OC4FE          LL_TIM_OC_DisableFast
01795   * @param  TIMx Timer instance
01796   * @param  Channel This parameter can be one of the following values:
01797   *         @arg @ref LL_TIM_CHANNEL_CH1
01798   *         @arg @ref LL_TIM_CHANNEL_CH2
01799   *         @arg @ref LL_TIM_CHANNEL_CH3
01800   *         @arg @ref LL_TIM_CHANNEL_CH4
01801   * @retval None
01802   */
01803 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
01804 {
01805   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01806   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01807   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
01808
01809 }
01810
01811 /**
01812   * @brief  Indicates whether fast mode is enabled for the output channel.
01813   * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
01814   *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
01815   *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
01816   *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
01817   * @param  TIMx Timer instance
01818   * @param  Channel This parameter can be one of the following values:
01819   *         @arg @ref LL_TIM_CHANNEL_CH1
01820   *         @arg @ref LL_TIM_CHANNEL_CH2
01821   *         @arg @ref LL_TIM_CHANNEL_CH3
01822   *         @arg @ref LL_TIM_CHANNEL_CH4
01823   * @retval State of bit (1 or 0).
01824   */
01825 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
01826 {
01827   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01828   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01829   register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
01830   return (READ_BIT(*pReg, bitfield) == bitfield);
01831 }
01832
01833 /**
01834   * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
01835   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
01836   *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
01837   *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
01838   *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload
01839   * @param  TIMx Timer instance
01840   * @param  Channel This parameter can be one of the following values:
01841   *         @arg @ref LL_TIM_CHANNEL_CH1
01842   *         @arg @ref LL_TIM_CHANNEL_CH2
01843   *         @arg @ref LL_TIM_CHANNEL_CH3
01844   *         @arg @ref LL_TIM_CHANNEL_CH4
01845   * @retval None
01846   */
01847 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
01848 {
01849   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01850   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01851   SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
01852 }
01853
01854 /**
01855   * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
01856   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
01857   *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
01858   *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
01859   *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload
01860   * @param  TIMx Timer instance
01861   * @param  Channel This parameter can be one of the following values:
01862   *         @arg @ref LL_TIM_CHANNEL_CH1
01863   *         @arg @ref LL_TIM_CHANNEL_CH2
01864   *         @arg @ref LL_TIM_CHANNEL_CH3
01865   *         @arg @ref LL_TIM_CHANNEL_CH4
01866   * @retval None
01867   */
01868 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
01869 {
01870   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01871   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01872   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
01873 }
01874
01875 /**
01876   * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
01877   * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
01878   *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
01879   *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
01880   *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
01881   * @param  TIMx Timer instance
01882   * @param  Channel This parameter can be one of the following values:
01883   *         @arg @ref LL_TIM_CHANNEL_CH1
01884   *         @arg @ref LL_TIM_CHANNEL_CH2
01885   *         @arg @ref LL_TIM_CHANNEL_CH3
01886   *         @arg @ref LL_TIM_CHANNEL_CH4
01887   * @retval State of bit (1 or 0).
01888   */
01889 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
01890 {
01891   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01892   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01893   register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
01894   return (READ_BIT(*pReg, bitfield) == bitfield);
01895 }
01896
01897 /**
01898   * @brief  Enable clearing the output channel on an external event.
01899   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
01900   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
01901   *       or not a timer instance can clear the OCxREF signal on an external event.
01902   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
01903   *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
01904   *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
01905   *         CCMR2        OC4CE          LL_TIM_OC_EnableClear
01906   * @param  TIMx Timer instance
01907   * @param  Channel This parameter can be one of the following values:
01908   *         @arg @ref LL_TIM_CHANNEL_CH1
01909   *         @arg @ref LL_TIM_CHANNEL_CH2
01910   *         @arg @ref LL_TIM_CHANNEL_CH3
01911   *         @arg @ref LL_TIM_CHANNEL_CH4
01912   * @retval None
01913   */
01914 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
01915 {
01916   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01917   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01918   SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
01919 }
01920
01921 /**
01922   * @brief  Disable clearing the output channel on an external event.
01923   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
01924   *       or not a timer instance can clear the OCxREF signal on an external event.
01925   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
01926   *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
01927   *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
01928   *         CCMR2        OC4CE          LL_TIM_OC_DisableClear
01929   * @param  TIMx Timer instance
01930   * @param  Channel This parameter can be one of the following values:
01931   *         @arg @ref LL_TIM_CHANNEL_CH1
01932   *         @arg @ref LL_TIM_CHANNEL_CH2
01933   *         @arg @ref LL_TIM_CHANNEL_CH3
01934   *         @arg @ref LL_TIM_CHANNEL_CH4
01935   * @retval None
01936   */
01937 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
01938 {
01939   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01940   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01941   CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
01942 }
01943
01944 /**
01945   * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
01946   * @note This function enables clearing the output channel on an external event.
01947   * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
01948   * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
01949   *       or not a timer instance can clear the OCxREF signal on an external event.
01950   * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
01951   *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
01952   *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
01953   *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
01954   * @param  TIMx Timer instance
01955   * @param  Channel This parameter can be one of the following values:
01956   *         @arg @ref LL_TIM_CHANNEL_CH1
01957   *         @arg @ref LL_TIM_CHANNEL_CH2
01958   *         @arg @ref LL_TIM_CHANNEL_CH3
01959   *         @arg @ref LL_TIM_CHANNEL_CH4
01960   * @retval State of bit (1 or 0).
01961   */
01962 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
01963 {
01964   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
01965   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
01966   register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
01967   return (READ_BIT(*pReg, bitfield) == bitfield);
01968 }
01969
01970 /**
01971   * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
01972   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
01973   *       dead-time insertion feature is supported by a timer instance.
01974   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
01975   * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
01976   * @param  TIMx Timer instance
01977   * @param  DeadTime between Min_Data=0 and Max_Data=255
01978   * @retval None
01979   */
01980 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
01981 {
01982   MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
01983 }
01984
01985 /**
01986   * @brief  Set compare value for output channel 1 (TIMx_CCR1).
01987   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
01988   *       output channel 1 is supported by a timer instance.
01989   * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
01990   * @param  TIMx Timer instance
01991   * @param  CompareValue between Min_Data=0 and Max_Data=65535
01992   * @retval None
01993   */
01994 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
01995 {
01996   WRITE_REG(TIMx->CCR1, CompareValue);
01997 }
01998
01999 /**
02000   * @brief  Set compare value for output channel 2 (TIMx_CCR2).
02001   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02002   *       output channel 2 is supported by a timer instance.
02003   * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
02004   * @param  TIMx Timer instance
02005   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02006   * @retval None
02007   */
02008 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
02009 {
02010   WRITE_REG(TIMx->CCR2, CompareValue);
02011 }
02012
02013 /**
02014   * @brief  Set compare value for output channel 3 (TIMx_CCR3).
02015   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02016   *       output channel is supported by a timer instance.
02017   * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
02018   * @param  TIMx Timer instance
02019   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02020   * @retval None
02021   */
02022 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
02023 {
02024   WRITE_REG(TIMx->CCR3, CompareValue);
02025 }
02026
02027 /**
02028   * @brief  Set compare value for output channel 4 (TIMx_CCR4).
02029   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02030   *       output channel 4 is supported by a timer instance.
02031   * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
02032   * @param  TIMx Timer instance
02033   * @param  CompareValue between Min_Data=0 and Max_Data=65535
02034   * @retval None
02035   */
02036 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
02037 {
02038   WRITE_REG(TIMx->CCR4, CompareValue);
02039 }
02040
02041 /**
02042   * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
02043   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02044   *       output channel 1 is supported by a timer instance.
02045   * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
02046   * @param  TIMx Timer instance
02047   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02048   */
02049 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
02050 {
02051   return (uint32_t)(READ_REG(TIMx->CCR1));
02052 }
02053
02054 /**
02055   * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
02056   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02057   *       output channel 2 is supported by a timer instance.
02058   * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
02059   * @param  TIMx Timer instance
02060   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02061   */
02062 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
02063 {
02064   return (uint32_t)(READ_REG(TIMx->CCR2));
02065 }
02066
02067 /**
02068   * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
02069   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02070   *       output channel 3 is supported by a timer instance.
02071   * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
02072   * @param  TIMx Timer instance
02073   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02074   */
02075 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
02076 {
02077   return (uint32_t)(READ_REG(TIMx->CCR3));
02078 }
02079
02080 /**
02081   * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
02082   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02083   *       output channel 4 is supported by a timer instance.
02084   * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
02085   * @param  TIMx Timer instance
02086   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
02087   */
02088 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
02089 {
02090   return (uint32_t)(READ_REG(TIMx->CCR4));
02091 }
02092
02093 /**
02094   * @}
02095   */
02096
02097 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
02098   * @{
02099   */
02100 /**
02101   * @brief  Configure input channel.
02102   * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
02103   *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
02104   *         CCMR1        IC1F          LL_TIM_IC_Config\n
02105   *         CCMR1        CC2S          LL_TIM_IC_Config\n
02106   *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
02107   *         CCMR1        IC2F          LL_TIM_IC_Config\n
02108   *         CCMR2        CC3S          LL_TIM_IC_Config\n
02109   *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
02110   *         CCMR2        IC3F          LL_TIM_IC_Config\n
02111   *         CCMR2        CC4S          LL_TIM_IC_Config\n
02112   *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
02113   *         CCMR2        IC4F          LL_TIM_IC_Config\n
02114   *         CCER         CC1P          LL_TIM_IC_Config\n
02115   *         CCER         CC1NP         LL_TIM_IC_Config\n
02116   *         CCER         CC2P          LL_TIM_IC_Config\n
02117   *         CCER         CC2NP         LL_TIM_IC_Config\n
02118   *         CCER         CC3P          LL_TIM_IC_Config\n
02119   *         CCER         CC3NP         LL_TIM_IC_Config\n
02120   *         CCER         CC4P          LL_TIM_IC_Config\n
02121   * @param  TIMx Timer instance
02122   * @param  Channel This parameter can be one of the following values:
02123   *         @arg @ref LL_TIM_CHANNEL_CH1
02124   *         @arg @ref LL_TIM_CHANNEL_CH2
02125   *         @arg @ref LL_TIM_CHANNEL_CH3
02126   *         @arg @ref LL_TIM_CHANNEL_CH4
02127   * @param  Configuration This parameter must be a combination of all the following values:
02128   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
02129   *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
02130   *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
02131   *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
02132   * @retval None
02133   */
02134 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
02135 {
02136   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02137   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02138   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
02139              ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
02140   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
02141              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
02142 }
02143
02144 /**
02145   * @brief  Set the active input.
02146   * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
02147   *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
02148   *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
02149   *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
02150   * @param  TIMx Timer instance
02151   * @param  Channel This parameter can be one of the following values:
02152   *         @arg @ref LL_TIM_CHANNEL_CH1
02153   *         @arg @ref LL_TIM_CHANNEL_CH2
02154   *         @arg @ref LL_TIM_CHANNEL_CH3
02155   *         @arg @ref LL_TIM_CHANNEL_CH4
02156   * @param  ICActiveInput This parameter can be one of the following values:
02157   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02158   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02159   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02160   * @retval None
02161   */
02162 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
02163 {
02164   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02165   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02166   MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02167 }
02168
02169 /**
02170   * @brief  Get the current active input.
02171   * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
02172   *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
02173   *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
02174   *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
02175   * @param  TIMx Timer instance
02176   * @param  Channel This parameter can be one of the following values:
02177   *         @arg @ref LL_TIM_CHANNEL_CH1
02178   *         @arg @ref LL_TIM_CHANNEL_CH2
02179   *         @arg @ref LL_TIM_CHANNEL_CH3
02180   *         @arg @ref LL_TIM_CHANNEL_CH4
02181   * @retval Returned value can be one of the following values:
02182   *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
02183   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
02184   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
02185   */
02186 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
02187 {
02188   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02189   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02190   return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02191 }
02192
02193 /**
02194   * @brief  Set the prescaler of input channel.
02195   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
02196   *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
02197   *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
02198   *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
02199   * @param  TIMx Timer instance
02200   * @param  Channel This parameter can be one of the following values:
02201   *         @arg @ref LL_TIM_CHANNEL_CH1
02202   *         @arg @ref LL_TIM_CHANNEL_CH2
02203   *         @arg @ref LL_TIM_CHANNEL_CH3
02204   *         @arg @ref LL_TIM_CHANNEL_CH4
02205   * @param  ICPrescaler This parameter can be one of the following values:
02206   *         @arg @ref LL_TIM_ICPSC_DIV1
02207   *         @arg @ref LL_TIM_ICPSC_DIV2
02208   *         @arg @ref LL_TIM_ICPSC_DIV4
02209   *         @arg @ref LL_TIM_ICPSC_DIV8
02210   * @retval None
02211   */
02212 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
02213 {
02214   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02215   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02216   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02217 }
02218
02219 /**
02220   * @brief  Get the current prescaler value acting on an  input channel.
02221   * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
02222   *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
02223   *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
02224   *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
02225   * @param  TIMx Timer instance
02226   * @param  Channel This parameter can be one of the following values:
02227   *         @arg @ref LL_TIM_CHANNEL_CH1
02228   *         @arg @ref LL_TIM_CHANNEL_CH2
02229   *         @arg @ref LL_TIM_CHANNEL_CH3
02230   *         @arg @ref LL_TIM_CHANNEL_CH4
02231   * @retval Returned value can be one of the following values:
02232   *         @arg @ref LL_TIM_ICPSC_DIV1
02233   *         @arg @ref LL_TIM_ICPSC_DIV2
02234   *         @arg @ref LL_TIM_ICPSC_DIV4
02235   *         @arg @ref LL_TIM_ICPSC_DIV8
02236   */
02237 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
02238 {
02239   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02240   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02241   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02242 }
02243
02244 /**
02245   * @brief  Set the input filter duration.
02246   * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
02247   *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
02248   *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
02249   *         CCMR2        IC4F          LL_TIM_IC_SetFilter
02250   * @param  TIMx Timer instance
02251   * @param  Channel This parameter can be one of the following values:
02252   *         @arg @ref LL_TIM_CHANNEL_CH1
02253   *         @arg @ref LL_TIM_CHANNEL_CH2
02254   *         @arg @ref LL_TIM_CHANNEL_CH3
02255   *         @arg @ref LL_TIM_CHANNEL_CH4
02256   * @param  ICFilter This parameter can be one of the following values:
02257   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02258   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02259   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02260   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02261   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02262   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02263   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02264   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02265   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02266   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02267   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02268   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02269   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02270   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02271   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02272   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02273   * @retval None
02274   */
02275 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
02276 {
02277   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02278   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02279   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
02280 }
02281
02282 /**
02283   * @brief  Get the input filter duration.
02284   * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
02285   *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
02286   *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
02287   *         CCMR2        IC4F          LL_TIM_IC_GetFilter
02288   * @param  TIMx Timer instance
02289   * @param  Channel This parameter can be one of the following values:
02290   *         @arg @ref LL_TIM_CHANNEL_CH1
02291   *         @arg @ref LL_TIM_CHANNEL_CH2
02292   *         @arg @ref LL_TIM_CHANNEL_CH3
02293   *         @arg @ref LL_TIM_CHANNEL_CH4
02294   * @retval Returned value can be one of the following values:
02295   *         @arg @ref LL_TIM_IC_FILTER_FDIV1
02296   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
02297   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
02298   *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
02299   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
02300   *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
02301   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
02302   *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
02303   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
02304   *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
02305   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
02306   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
02307   *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
02308   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
02309   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
02310   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
02311   */
02312 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
02313 {
02314   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02315   register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
02316   return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
02317 }
02318
02319 /**
02320   * @brief  Set the input channel polarity.
02321   * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
02322   *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
02323   *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
02324   *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
02325   *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
02326   *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
02327   *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
02328   * @param  TIMx Timer instance
02329   * @param  Channel This parameter can be one of the following values:
02330   *         @arg @ref LL_TIM_CHANNEL_CH1
02331   *         @arg @ref LL_TIM_CHANNEL_CH2
02332   *         @arg @ref LL_TIM_CHANNEL_CH3
02333   *         @arg @ref LL_TIM_CHANNEL_CH4
02334   * @param  ICPolarity This parameter can be one of the following values:
02335   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02336   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02337   * @retval None
02338   */
02339 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
02340 {
02341   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02342   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
02343              ICPolarity << SHIFT_TAB_CCxP[iChannel]);
02344 }
02345
02346 /**
02347   * @brief  Get the current input channel polarity.
02348   * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
02349   *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
02350   *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
02351   *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
02352   *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
02353   *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
02354   *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
02355   * @param  TIMx Timer instance
02356   * @param  Channel This parameter can be one of the following values:
02357   *         @arg @ref LL_TIM_CHANNEL_CH1
02358   *         @arg @ref LL_TIM_CHANNEL_CH2
02359   *         @arg @ref LL_TIM_CHANNEL_CH3
02360   *         @arg @ref LL_TIM_CHANNEL_CH4
02361   * @retval Returned value can be one of the following values:
02362   *         @arg @ref LL_TIM_IC_POLARITY_RISING
02363   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
02364   */
02365 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
02366 {
02367   register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
02368   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
02369           SHIFT_TAB_CCxP[iChannel]);
02370 }
02371
02372 /**
02373   * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
02374   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02375   *       a timer instance provides an XOR input.
02376   * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
02377   * @param  TIMx Timer instance
02378   * @retval None
02379   */
02380 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
02381 {
02382   SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
02383 }
02384
02385 /**
02386   * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
02387   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02388   *       a timer instance provides an XOR input.
02389   * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
02390   * @param  TIMx Timer instance
02391   * @retval None
02392   */
02393 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
02394 {
02395   CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
02396 }
02397
02398 /**
02399   * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
02400   * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
02401   * a timer instance provides an XOR input.
02402   * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
02403   * @param  TIMx Timer instance
02404   * @retval State of bit (1 or 0).
02405   */
02406 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
02407 {
02408   return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
02409 }
02410
02411 /**
02412   * @brief  Get captured value for input channel 1.
02413   * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
02414   *       input channel 1 is supported by a timer instance.
02415   * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
02416   * @param  TIMx Timer instance
02417   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02418   */
02419 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
02420 {
02421   return (uint32_t)(READ_REG(TIMx->CCR1));
02422 }
02423
02424 /**
02425   * @brief  Get captured value for input channel 2.
02426   * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
02427   *       input channel 2 is supported by a timer instance.
02428   * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
02429   * @param  TIMx Timer instance
02430   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02431   */
02432 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
02433 {
02434   return (uint32_t)(READ_REG(TIMx->CCR2));
02435 }
02436
02437 /**
02438   * @brief  Get captured value for input channel 3.
02439   * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
02440   *       input channel 3 is supported by a timer instance.
02441   * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
02442   * @param  TIMx Timer instance
02443   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02444   */
02445 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
02446 {
02447   return (uint32_t)(READ_REG(TIMx->CCR3));
02448 }
02449
02450 /**
02451   * @brief  Get captured value for input channel 4.
02452   * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
02453   *       input channel 4 is supported by a timer instance.
02454   * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
02455   * @param  TIMx Timer instance
02456   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
02457   */
02458 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
02459 {
02460   return (uint32_t)(READ_REG(TIMx->CCR4));
02461 }
02462
02463 /**
02464   * @}
02465   */
02466
02467 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
02468   * @{
02469   */
02470 /**
02471   * @brief  Enable external clock mode 2.
02472   * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
02473   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
02474   *       whether or not a timer instance supports external clock mode2.
02475   * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
02476   * @param  TIMx Timer instance
02477   * @retval None
02478   */
02479 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
02480 {
02481   SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
02482 }
02483
02484 /**
02485   * @brief  Disable external clock mode 2.
02486   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
02487   *       whether or not a timer instance supports external clock mode2.
02488   * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
02489   * @param  TIMx Timer instance
02490   * @retval None
02491   */
02492 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
02493 {
02494   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
02495 }
02496
02497 /**
02498   * @brief  Indicate whether external clock mode 2 is enabled.
02499   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
02500   *       whether or not a timer instance supports external clock mode2.
02501   * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
02502   * @param  TIMx Timer instance
02503   * @retval State of bit (1 or 0).
02504   */
02505 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
02506 {
02507   return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
02508 }
02509
02510 /**
02511   * @brief  Set the clock source of the counter clock.
02512   * @note when selected clock source is external clock mode 1, the timer input
02513   *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
02514   *       function. This timer input must be configured by calling
02515   *       the @ref LL_TIM_IC_Config() function.
02516   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
02517   *       whether or not a timer instance supports external clock mode1.
02518   * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
02519   *       whether or not a timer instance supports external clock mode2.
02520   * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
02521   *         SMCR         ECE           LL_TIM_SetClockSource
02522   * @param  TIMx Timer instance
02523   * @param  ClockSource This parameter can be one of the following values:
02524   *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
02525   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
02526   *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
02527   * @retval None
02528   */
02529 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
02530 {
02531   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
02532 }
02533
02534 /**
02535   * @brief  Set the encoder interface mode.
02536   * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
02537   *       whether or not a timer instance supports the encoder mode.
02538   * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
02539   * @param  TIMx Timer instance
02540   * @param  EncoderMode This parameter can be one of the following values:
02541   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
02542   *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
02543   *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
02544   * @retval None
02545   */
02546 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
02547 {
02548   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
02549 }
02550
02551 /**
02552   * @}
02553   */
02554
02555 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
02556   * @{
02557   */
02558 /**
02559   * @brief  Set the trigger output (TRGO) used for timer synchronization .
02560   * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
02561   *       whether or not a timer instance can operate as a master timer.
02562   * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
02563   * @param  TIMx Timer instance
02564   * @param  TimerSynchronization This parameter can be one of the following values:
02565   *         @arg @ref LL_TIM_TRGO_RESET
02566   *         @arg @ref LL_TIM_TRGO_ENABLE
02567   *         @arg @ref LL_TIM_TRGO_UPDATE
02568   *         @arg @ref LL_TIM_TRGO_CC1IF
02569   *         @arg @ref LL_TIM_TRGO_OC1REF
02570   *         @arg @ref LL_TIM_TRGO_OC2REF
02571   *         @arg @ref LL_TIM_TRGO_OC3REF
02572   *         @arg @ref LL_TIM_TRGO_OC4REF
02573   * @retval None
02574   */
02575 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
02576 {
02577   MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
02578 }
02579
02580 /**
02581   * @brief  Set the synchronization mode of a slave timer.
02582   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
02583   *       a timer instance can operate as a slave timer.
02584   * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
02585   * @param  TIMx Timer instance
02586   * @param  SlaveMode This parameter can be one of the following values:
02587   *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
02588   *         @arg @ref LL_TIM_SLAVEMODE_RESET
02589   *         @arg @ref LL_TIM_SLAVEMODE_GATED
02590   *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
02591   * @retval None
02592   */
02593 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
02594 {
02595   MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
02596 }
02597
02598 /**
02599   * @brief  Set the selects the trigger input to be used to synchronize the counter.
02600   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
02601   *       a timer instance can operate as a slave timer.
02602   * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
02603   * @param  TIMx Timer instance
02604   * @param  TriggerInput This parameter can be one of the following values:
02605   *         @arg @ref LL_TIM_TS_ITR0
02606   *         @arg @ref LL_TIM_TS_ITR1
02607   *         @arg @ref LL_TIM_TS_ITR2
02608   *         @arg @ref LL_TIM_TS_ITR3
02609   *         @arg @ref LL_TIM_TS_TI1F_ED
02610   *         @arg @ref LL_TIM_TS_TI1FP1
02611   *         @arg @ref LL_TIM_TS_TI2FP2
02612   *         @arg @ref LL_TIM_TS_ETRF
02613   * @retval None
02614   */
02615 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
02616 {
02617   MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
02618 }
02619
02620 /**
02621   * @brief  Enable the Master/Slave mode.
02622   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
02623   *       a timer instance can operate as a slave timer.
02624   * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
02625   * @param  TIMx Timer instance
02626   * @retval None
02627   */
02628 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
02629 {
02630   SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
02631 }
02632
02633 /**
02634   * @brief  Disable the Master/Slave mode.
02635   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
02636   *       a timer instance can operate as a slave timer.
02637   * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
02638   * @param  TIMx Timer instance
02639   * @retval None
02640   */
02641 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
02642 {
02643   CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
02644 }
02645
02646 /**
02647   * @brief Indicates whether the Master/Slave mode is enabled.
02648   * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
02649   * a timer instance can operate as a slave timer.
02650   * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
02651   * @param  TIMx Timer instance
02652   * @retval State of bit (1 or 0).
02653   */
02654 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
02655 {
02656   return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
02657 }
02658
02659 /**
02660   * @brief  Configure the external trigger (ETR) input.
02661   * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
02662   *       a timer instance provides an external trigger input.
02663   * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
02664   *         SMCR         ETPS          LL_TIM_ConfigETR\n
02665   *         SMCR         ETF           LL_TIM_ConfigETR
02666   * @param  TIMx Timer instance
02667   * @param  ETRPolarity This parameter can be one of the following values:
02668   *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
02669   *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
02670   * @param  ETRPrescaler This parameter can be one of the following values:
02671   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
02672   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
02673   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
02674   *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
02675   * @param  ETRFilter This parameter can be one of the following values:
02676   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
02677   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
02678   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
02679   *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
02680   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
02681   *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
02682   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
02683   *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
02684   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
02685   *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
02686   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
02687   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
02688   *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
02689   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
02690   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
02691   *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
02692   * @retval None
02693   */
02694 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
02695                                       uint32_t ETRFilter)
02696 {
02697   MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
02698 }
02699
02700 /**
02701   * @}
02702   */
02703
02704 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
02705   * @{
02706   */
02707 /**
02708   * @brief  Enable the break function.
02709   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02710   *       a timer instance provides a break input.
02711   * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
02712   * @param  TIMx Timer instance
02713   * @retval None
02714   */
02715 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
02716 {
02717   SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
02718 }
02719
02720 /**
02721   * @brief  Disable the break function.
02722   * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
02723   * @param  TIMx Timer instance
02724   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02725   *       a timer instance provides a break input.
02726   * @retval None
02727   */
02728 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
02729 {
02730   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
02731 }
02732
02733 /**
02734   * @brief  Configure the break input.
02735   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02736   *       a timer instance provides a break input.
02737   * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK
02738   * @param  TIMx Timer instance
02739   * @param  BreakPolarity This parameter can be one of the following values:
02740   *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
02741   *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
02742   * @retval None
02743   */
02744 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
02745 {
02746   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
02747 }
02748
02749 /**
02750   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
02751   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02752   *       a timer instance provides a break input.
02753   * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
02754   *         BDTR         OSSR          LL_TIM_SetOffStates
02755   * @param  TIMx Timer instance
02756   * @param  OffStateIdle This parameter can be one of the following values:
02757   *         @arg @ref LL_TIM_OSSI_DISABLE
02758   *         @arg @ref LL_TIM_OSSI_ENABLE
02759   * @param  OffStateRun This parameter can be one of the following values:
02760   *         @arg @ref LL_TIM_OSSR_DISABLE
02761   *         @arg @ref LL_TIM_OSSR_ENABLE
02762   * @retval None
02763   */
02764 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
02765 {
02766   MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
02767 }
02768
02769 /**
02770   * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
02771   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02772   *       a timer instance provides a break input.
02773   * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
02774   * @param  TIMx Timer instance
02775   * @retval None
02776   */
02777 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
02778 {
02779   SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
02780 }
02781
02782 /**
02783   * @brief  Disable automatic output (MOE can be set only by software).
02784   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02785   *       a timer instance provides a break input.
02786   * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
02787   * @param  TIMx Timer instance
02788   * @retval None
02789   */
02790 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
02791 {
02792   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
02793 }
02794
02795 /**
02796   * @brief  Indicate whether automatic output is enabled.
02797   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02798   *       a timer instance provides a break input.
02799   * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
02800   * @param  TIMx Timer instance
02801   * @retval State of bit (1 or 0).
02802   */
02803 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
02804 {
02805   return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
02806 }
02807
02808 /**
02809   * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
02810   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
02811   *       software and is reset in case of break or break2 event
02812   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02813   *       a timer instance provides a break input.
02814   * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
02815   * @param  TIMx Timer instance
02816   * @retval None
02817   */
02818 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
02819 {
02820   SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
02821 }
02822
02823 /**
02824   * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
02825   * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
02826   *       software and is reset in case of break or break2 event.
02827   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02828   *       a timer instance provides a break input.
02829   * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
02830   * @param  TIMx Timer instance
02831   * @retval None
02832   */
02833 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
02834 {
02835   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
02836 }
02837
02838 /**
02839   * @brief  Indicates whether outputs are enabled.
02840   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
02841   *       a timer instance provides a break input.
02842   * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
02843   * @param  TIMx Timer instance
02844   * @retval State of bit (1 or 0).
02845   */
02846 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
02847 {
02848   return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
02849 }
02850
02851 /**
02852   * @}
02853   */
02854
02855 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
02856   * @{
02857   */
02858 /**
02859   * @brief  Configures the timer DMA burst feature.
02860   * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
02861   *       not a timer instance supports the DMA burst mode.
02862   * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
02863   *         DCR          DBA           LL_TIM_ConfigDMABurst
02864   * @param  TIMx Timer instance
02865   * @param  DMABurstBaseAddress This parameter can be one of the following values:
02866   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
02867   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
02868   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
02869   *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
02870   *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
02871   *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
02872   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
02873   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
02874   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
02875   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
02876   *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
02877   *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
02878   *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
02879   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
02880   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
02881   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
02882   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
02883   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
02884   * @param  DMABurstLength This parameter can be one of the following values:
02885   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
02886   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
02887   *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
02888   *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
02889   *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
02890   *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
02891   *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
02892   *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
02893   *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
02894   *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
02895   *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
02896   *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
02897   *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
02898   *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
02899   *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
02900   *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
02901   *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
02902   *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
02903   * @retval None
02904   */
02905 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
02906 {
02907   MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
02908 }
02909
02910 /**
02911   * @}
02912   */
02913
02914
02915 /**
02916   * @}
02917   */
02918
02919
02920 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
02921   * @{
02922   */
02923 /**
02924   * @brief  Clear the update interrupt flag (UIF).
02925   * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
02926   * @param  TIMx Timer instance
02927   * @retval None
02928   */
02929 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
02930 {
02931   WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
02932 }
02933
02934 /**
02935   * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
02936   * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
02937   * @param  TIMx Timer instance
02938   * @retval State of bit (1 or 0).
02939   */
02940 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
02941 {
02942   return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
02943 }
02944
02945 /**
02946   * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
02947   * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
02948   * @param  TIMx Timer instance
02949   * @retval None
02950   */
02951 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
02952 {
02953   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
02954 }
02955
02956 /**
02957   * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
02958   * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
02959   * @param  TIMx Timer instance
02960   * @retval State of bit (1 or 0).
02961   */
02962 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
02963 {
02964   return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
02965 }
02966
02967 /**
02968   * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
02969   * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
02970   * @param  TIMx Timer instance
02971   * @retval None
02972   */
02973 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
02974 {
02975   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
02976 }
02977
02978 /**
02979   * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
02980   * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
02981   * @param  TIMx Timer instance
02982   * @retval State of bit (1 or 0).
02983   */
02984 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
02985 {
02986   return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
02987 }
02988
02989 /**
02990   * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
02991   * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
02992   * @param  TIMx Timer instance
02993   * @retval None
02994   */
02995 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
02996 {
02997   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
02998 }
02999
03000 /**
03001   * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
03002   * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
03003   * @param  TIMx Timer instance
03004   * @retval State of bit (1 or 0).
03005   */
03006 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
03007 {
03008   return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
03009 }
03010
03011 /**
03012   * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
03013   * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
03014   * @param  TIMx Timer instance
03015   * @retval None
03016   */
03017 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
03018 {
03019   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
03020 }
03021
03022 /**
03023   * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
03024   * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
03025   * @param  TIMx Timer instance
03026   * @retval State of bit (1 or 0).
03027   */
03028 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
03029 {
03030   return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
03031 }
03032
03033 /**
03034   * @brief  Clear the commutation interrupt flag (COMIF).
03035   * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
03036   * @param  TIMx Timer instance
03037   * @retval None
03038   */
03039 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
03040 {
03041   WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
03042 }
03043
03044 /**
03045   * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
03046   * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
03047   * @param  TIMx Timer instance
03048   * @retval State of bit (1 or 0).
03049   */
03050 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
03051 {
03052   return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
03053 }
03054
03055 /**
03056   * @brief  Clear the trigger interrupt flag (TIF).
03057   * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
03058   * @param  TIMx Timer instance
03059   * @retval None
03060   */
03061 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
03062 {
03063   WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
03064 }
03065
03066 /**
03067   * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
03068   * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
03069   * @param  TIMx Timer instance
03070   * @retval State of bit (1 or 0).
03071   */
03072 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
03073 {
03074   return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
03075 }
03076
03077 /**
03078   * @brief  Clear the break interrupt flag (BIF).
03079   * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
03080   * @param  TIMx Timer instance
03081   * @retval None
03082   */
03083 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
03084 {
03085   WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
03086 }
03087
03088 /**
03089   * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
03090   * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
03091   * @param  TIMx Timer instance
03092   * @retval State of bit (1 or 0).
03093   */
03094 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
03095 {
03096   return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
03097 }
03098
03099 /**
03100   * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
03101   * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
03102   * @param  TIMx Timer instance
03103   * @retval None
03104   */
03105 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
03106 {
03107   WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
03108 }
03109
03110 /**
03111   * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
03112   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
03113   * @param  TIMx Timer instance
03114   * @retval State of bit (1 or 0).
03115   */
03116 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
03117 {
03118   return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
03119 }
03120
03121 /**
03122   * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
03123   * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
03124   * @param  TIMx Timer instance
03125   * @retval None
03126   */
03127 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
03128 {
03129   WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
03130 }
03131
03132 /**
03133   * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
03134   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
03135   * @param  TIMx Timer instance
03136   * @retval State of bit (1 or 0).
03137   */
03138 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
03139 {
03140   return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
03141 }
03142
03143 /**
03144   * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
03145   * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
03146   * @param  TIMx Timer instance
03147   * @retval None
03148   */
03149 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
03150 {
03151   WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
03152 }
03153
03154 /**
03155   * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
03156   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
03157   * @param  TIMx Timer instance
03158   * @retval State of bit (1 or 0).
03159   */
03160 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
03161 {
03162   return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
03163 }
03164
03165 /**
03166   * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
03167   * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
03168   * @param  TIMx Timer instance
03169   * @retval None
03170   */
03171 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
03172 {
03173   WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
03174 }
03175
03176 /**
03177   * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
03178   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
03179   * @param  TIMx Timer instance
03180   * @retval State of bit (1 or 0).
03181   */
03182 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
03183 {
03184   return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
03185 }
03186
03187 /**
03188   * @}
03189   */
03190
03191 /** @defgroup TIM_LL_EF_IT_Management IT-Management
03192   * @{
03193   */
03194 /**
03195   * @brief  Enable update interrupt (UIE).
03196   * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
03197   * @param  TIMx Timer instance
03198   * @retval None
03199   */
03200 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
03201 {
03202   SET_BIT(TIMx->DIER, TIM_DIER_UIE);
03203 }
03204
03205 /**
03206   * @brief  Disable update interrupt (UIE).
03207   * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
03208   * @param  TIMx Timer instance
03209   * @retval None
03210   */
03211 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
03212 {
03213   CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
03214 }
03215
03216 /**
03217   * @brief  Indicates whether the update interrupt (UIE) is enabled.
03218   * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
03219   * @param  TIMx Timer instance
03220   * @retval State of bit (1 or 0).
03221   */
03222 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
03223 {
03224   return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
03225 }
03226
03227 /**
03228   * @brief  Enable capture/compare 1 interrupt (CC1IE).
03229   * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
03230   * @param  TIMx Timer instance
03231   * @retval None
03232   */
03233 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
03234 {
03235   SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
03236 }
03237
03238 /**
03239   * @brief  Disable capture/compare 1  interrupt (CC1IE).
03240   * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
03241   * @param  TIMx Timer instance
03242   * @retval None
03243   */
03244 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
03245 {
03246   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
03247 }
03248
03249 /**
03250   * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
03251   * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
03252   * @param  TIMx Timer instance
03253   * @retval State of bit (1 or 0).
03254   */
03255 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
03256 {
03257   return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
03258 }
03259
03260 /**
03261   * @brief  Enable capture/compare 2 interrupt (CC2IE).
03262   * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
03263   * @param  TIMx Timer instance
03264   * @retval None
03265   */
03266 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
03267 {
03268   SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
03269 }
03270
03271 /**
03272   * @brief  Disable capture/compare 2  interrupt (CC2IE).
03273   * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
03274   * @param  TIMx Timer instance
03275   * @retval None
03276   */
03277 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
03278 {
03279   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
03280 }
03281
03282 /**
03283   * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
03284   * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
03285   * @param  TIMx Timer instance
03286   * @retval State of bit (1 or 0).
03287   */
03288 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
03289 {
03290   return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
03291 }
03292
03293 /**
03294   * @brief  Enable capture/compare 3 interrupt (CC3IE).
03295   * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
03296   * @param  TIMx Timer instance
03297   * @retval None
03298   */
03299 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
03300 {
03301   SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
03302 }
03303
03304 /**
03305   * @brief  Disable capture/compare 3  interrupt (CC3IE).
03306   * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
03307   * @param  TIMx Timer instance
03308   * @retval None
03309   */
03310 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
03311 {
03312   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
03313 }
03314
03315 /**
03316   * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
03317   * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
03318   * @param  TIMx Timer instance
03319   * @retval State of bit (1 or 0).
03320   */
03321 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
03322 {
03323   return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
03324 }
03325
03326 /**
03327   * @brief  Enable capture/compare 4 interrupt (CC4IE).
03328   * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
03329   * @param  TIMx Timer instance
03330   * @retval None
03331   */
03332 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
03333 {
03334   SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
03335 }
03336
03337 /**
03338   * @brief  Disable capture/compare 4  interrupt (CC4IE).
03339   * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
03340   * @param  TIMx Timer instance
03341   * @retval None
03342   */
03343 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
03344 {
03345   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
03346 }
03347
03348 /**
03349   * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
03350   * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
03351   * @param  TIMx Timer instance
03352   * @retval State of bit (1 or 0).
03353   */
03354 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
03355 {
03356   return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
03357 }
03358
03359 /**
03360   * @brief  Enable commutation interrupt (COMIE).
03361   * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
03362   * @param  TIMx Timer instance
03363   * @retval None
03364   */
03365 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
03366 {
03367   SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
03368 }
03369
03370 /**
03371   * @brief  Disable commutation interrupt (COMIE).
03372   * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
03373   * @param  TIMx Timer instance
03374   * @retval None
03375   */
03376 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
03377 {
03378   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
03379 }
03380
03381 /**
03382   * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
03383   * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
03384   * @param  TIMx Timer instance
03385   * @retval State of bit (1 or 0).
03386   */
03387 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
03388 {
03389   return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
03390 }
03391
03392 /**
03393   * @brief  Enable trigger interrupt (TIE).
03394   * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
03395   * @param  TIMx Timer instance
03396   * @retval None
03397   */
03398 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
03399 {
03400   SET_BIT(TIMx->DIER, TIM_DIER_TIE);
03401 }
03402
03403 /**
03404   * @brief  Disable trigger interrupt (TIE).
03405   * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
03406   * @param  TIMx Timer instance
03407   * @retval None
03408   */
03409 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
03410 {
03411   CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
03412 }
03413
03414 /**
03415   * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
03416   * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
03417   * @param  TIMx Timer instance
03418   * @retval State of bit (1 or 0).
03419   */
03420 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
03421 {
03422   return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
03423 }
03424
03425 /**
03426   * @brief  Enable break interrupt (BIE).
03427   * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
03428   * @param  TIMx Timer instance
03429   * @retval None
03430   */
03431 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
03432 {
03433   SET_BIT(TIMx->DIER, TIM_DIER_BIE);
03434 }
03435
03436 /**
03437   * @brief  Disable break interrupt (BIE).
03438   * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
03439   * @param  TIMx Timer instance
03440   * @retval None
03441   */
03442 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
03443 {
03444   CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
03445 }
03446
03447 /**
03448   * @brief  Indicates whether the break interrupt (BIE) is enabled.
03449   * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
03450   * @param  TIMx Timer instance
03451   * @retval State of bit (1 or 0).
03452   */
03453 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
03454 {
03455   return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
03456 }
03457
03458 /**
03459   * @}
03460   */
03461
03462 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
03463   * @{
03464   */
03465 /**
03466   * @brief  Enable update DMA request (UDE).
03467   * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
03468   * @param  TIMx Timer instance
03469   * @retval None
03470   */
03471 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
03472 {
03473   SET_BIT(TIMx->DIER, TIM_DIER_UDE);
03474 }
03475
03476 /**
03477   * @brief  Disable update DMA request (UDE).
03478   * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
03479   * @param  TIMx Timer instance
03480   * @retval None
03481   */
03482 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
03483 {
03484   CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
03485 }
03486
03487 /**
03488   * @brief  Indicates whether the update DMA request  (UDE) is enabled.
03489   * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
03490   * @param  TIMx Timer instance
03491   * @retval State of bit (1 or 0).
03492   */
03493 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
03494 {
03495   return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
03496 }
03497
03498 /**
03499   * @brief  Enable capture/compare 1 DMA request (CC1DE).
03500   * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
03501   * @param  TIMx Timer instance
03502   * @retval None
03503   */
03504 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
03505 {
03506   SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
03507 }
03508
03509 /**
03510   * @brief  Disable capture/compare 1  DMA request (CC1DE).
03511   * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
03512   * @param  TIMx Timer instance
03513   * @retval None
03514   */
03515 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
03516 {
03517   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
03518 }
03519
03520 /**
03521   * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
03522   * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
03523   * @param  TIMx Timer instance
03524   * @retval State of bit (1 or 0).
03525   */
03526 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
03527 {
03528   return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
03529 }
03530
03531 /**
03532   * @brief  Enable capture/compare 2 DMA request (CC2DE).
03533   * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
03534   * @param  TIMx Timer instance
03535   * @retval None
03536   */
03537 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
03538 {
03539   SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
03540 }
03541
03542 /**
03543   * @brief  Disable capture/compare 2  DMA request (CC2DE).
03544   * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
03545   * @param  TIMx Timer instance
03546   * @retval None
03547   */
03548 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
03549 {
03550   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
03551 }
03552
03553 /**
03554   * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
03555   * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
03556   * @param  TIMx Timer instance
03557   * @retval State of bit (1 or 0).
03558   */
03559 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
03560 {
03561   return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
03562 }
03563
03564 /**
03565   * @brief  Enable capture/compare 3 DMA request (CC3DE).
03566   * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
03567   * @param  TIMx Timer instance
03568   * @retval None
03569   */
03570 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
03571 {
03572   SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
03573 }
03574
03575 /**
03576   * @brief  Disable capture/compare 3  DMA request (CC3DE).
03577   * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
03578   * @param  TIMx Timer instance
03579   * @retval None
03580   */
03581 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
03582 {
03583   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
03584 }
03585
03586 /**
03587   * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
03588   * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
03589   * @param  TIMx Timer instance
03590   * @retval State of bit (1 or 0).
03591   */
03592 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
03593 {
03594   return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
03595 }
03596
03597 /**
03598   * @brief  Enable capture/compare 4 DMA request (CC4DE).
03599   * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
03600   * @param  TIMx Timer instance
03601   * @retval None
03602   */
03603 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
03604 {
03605   SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
03606 }
03607
03608 /**
03609   * @brief  Disable capture/compare 4  DMA request (CC4DE).
03610   * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
03611   * @param  TIMx Timer instance
03612   * @retval None
03613   */
03614 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
03615 {
03616   CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
03617 }
03618
03619 /**
03620   * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
03621   * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
03622   * @param  TIMx Timer instance
03623   * @retval State of bit (1 or 0).
03624   */
03625 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
03626 {
03627   return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
03628 }
03629
03630 /**
03631   * @brief  Enable commutation DMA request (COMDE).
03632   * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
03633   * @param  TIMx Timer instance
03634   * @retval None
03635   */
03636 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
03637 {
03638   SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
03639 }
03640
03641 /**
03642   * @brief  Disable commutation DMA request (COMDE).
03643   * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
03644   * @param  TIMx Timer instance
03645   * @retval None
03646   */
03647 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
03648 {
03649   CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
03650 }
03651
03652 /**
03653   * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
03654   * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
03655   * @param  TIMx Timer instance
03656   * @retval State of bit (1 or 0).
03657   */
03658 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
03659 {
03660   return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
03661 }
03662
03663 /**
03664   * @brief  Enable trigger interrupt (TDE).
03665   * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
03666   * @param  TIMx Timer instance
03667   * @retval None
03668   */
03669 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
03670 {
03671   SET_BIT(TIMx->DIER, TIM_DIER_TDE);
03672 }
03673
03674 /**
03675   * @brief  Disable trigger interrupt (TDE).
03676   * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
03677   * @param  TIMx Timer instance
03678   * @retval None
03679   */
03680 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
03681 {
03682   CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
03683 }
03684
03685 /**
03686   * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
03687   * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
03688   * @param  TIMx Timer instance
03689   * @retval State of bit (1 or 0).
03690   */
03691 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
03692 {
03693   return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
03694 }
03695
03696 /**
03697   * @}
03698   */
03699
03700 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
03701   * @{
03702   */
03703 /**
03704   * @brief  Generate an update event.
03705   * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
03706   * @param  TIMx Timer instance
03707   * @retval None
03708   */
03709 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
03710 {
03711   SET_BIT(TIMx->EGR, TIM_EGR_UG);
03712 }
03713
03714 /**
03715   * @brief  Generate Capture/Compare 1 event.
03716   * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
03717   * @param  TIMx Timer instance
03718   * @retval None
03719   */
03720 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
03721 {
03722   SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
03723 }
03724
03725 /**
03726   * @brief  Generate Capture/Compare 2 event.
03727   * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
03728   * @param  TIMx Timer instance
03729   * @retval None
03730   */
03731 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
03732 {
03733   SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
03734 }
03735
03736 /**
03737   * @brief  Generate Capture/Compare 3 event.
03738   * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
03739   * @param  TIMx Timer instance
03740   * @retval None
03741   */
03742 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
03743 {
03744   SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
03745 }
03746
03747 /**
03748   * @brief  Generate Capture/Compare 4 event.
03749   * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
03750   * @param  TIMx Timer instance
03751   * @retval None
03752   */
03753 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
03754 {
03755   SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
03756 }
03757
03758 /**
03759   * @brief  Generate commutation event.
03760   * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
03761   * @param  TIMx Timer instance
03762   * @retval None
03763   */
03764 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
03765 {
03766   SET_BIT(TIMx->EGR, TIM_EGR_COMG);
03767 }
03768
03769 /**
03770   * @brief  Generate trigger event.
03771   * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
03772   * @param  TIMx Timer instance
03773   * @retval None
03774   */
03775 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
03776 {
03777   SET_BIT(TIMx->EGR, TIM_EGR_TG);
03778 }
03779
03780 /**
03781   * @brief  Generate break event.
03782   * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
03783   * @param  TIMx Timer instance
03784   * @retval None
03785   */
03786 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
03787 {
03788   SET_BIT(TIMx->EGR, TIM_EGR_BG);
03789 }
03790
03791 /**
03792   * @}
03793   */
03794
03795 #if defined(USE_FULL_LL_DRIVER)
03796 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
03797   * @{
03798   */
03799
03800 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
03801 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
03802 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
03803 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
03804 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
03805 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
03806 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
03807 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
03808 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
03809 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
03810 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
03811 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
03812 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
03813 /**
03814   * @}
03815   */
03816 #endif /* USE_FULL_LL_DRIVER */
03817
03818 /**
03819   * @}
03820   */
03821
03822 /**
03823   * @}
03824   */
03825
03826 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14  || TIM15 || TIM16 || TIM17 */
03827
03828 /**
03829   * @}
03830   */
03831
03832 #ifdef __cplusplus
03833 }
03834 #endif
03835
03836 #endif /* __STM32F1xx_LL_TIM_H */
03837 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_usart.c Source File

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stm32f1xx_ll_usart.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_usart.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   USART LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 #if defined(USE_FULL_LL_DRIVER)
00038
00039 /* Includes ------------------------------------------------------------------*/
00040 #include "stm32f1xx_ll_usart.h"
00041 #include "stm32f1xx_ll_rcc.h"
00042 #include "stm32f1xx_ll_bus.h"
00043 #ifdef  USE_FULL_ASSERT
00044 #include "stm32_assert.h"
00045 #else
00046 #define assert_param(expr) ((void)0U)
00047 #endif
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
00054
00055 /** @addtogroup USART_LL
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /** @addtogroup USART_LL_Private_Constants
00063   * @{
00064   */
00065
00066 /**
00067   * @}
00068   */
00069
00070
00071 /* Private macros ------------------------------------------------------------*/
00072 /** @addtogroup USART_LL_Private_Macros
00073   * @{
00074   */
00075
00076 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
00077  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
00078 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
00079
00080 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
00081                                        || ((__VALUE__) == LL_USART_DIRECTION_RX) \
00082                                        || ((__VALUE__) == LL_USART_DIRECTION_TX) \
00083                                        || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
00084
00085 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
00086                                     || ((__VALUE__) == LL_USART_PARITY_EVEN) \
00087                                     || ((__VALUE__) == LL_USART_PARITY_ODD))
00088
00089 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
00090                                        || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
00091
00092 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
00093                                           || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
00094
00095 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
00096                                               || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
00097
00098 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
00099                                         || ((__VALUE__) == LL_USART_PHASE_2EDGE))
00100
00101 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
00102                                            || ((__VALUE__) == LL_USART_POLARITY_HIGH))
00103
00104 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
00105                                          || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
00106
00107 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
00108                                       || ((__VALUE__) == LL_USART_STOPBITS_1) \
00109                                       || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
00110                                       || ((__VALUE__) == LL_USART_STOPBITS_2))
00111
00112 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
00113                                        || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
00114                                        || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
00115                                        || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
00116
00117 /**
00118   * @}
00119   */
00120
00121 /* Private function prototypes -----------------------------------------------*/
00122
00123 /* Exported functions --------------------------------------------------------*/
00124 /** @addtogroup USART_LL_Exported_Functions
00125   * @{
00126   */
00127
00128 /** @addtogroup USART_LL_EF_Init
00129   * @{
00130   */
00131
00132 /**
00133   * @brief  De-initialize USART registers (Registers restored to their default values).
00134   * @param  USARTx USART Instance
00135   * @retval An ErrorStatus enumeration value:
00136   *          - SUCCESS: USART registers are de-initialized
00137   *          - ERROR: USART registers are not de-initialized
00138   */
00139 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
00140 {
00141   ErrorStatus status = SUCCESS;
00142
00143   /* Check the parameters */
00144   assert_param(IS_UART_INSTANCE(USARTx));
00145
00146   if (USARTx == USART1)
00147   {
00148     /* Force reset of USART clock */
00149     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
00150
00151     /* Release reset of USART clock */
00152     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
00153   }
00154   else if (USARTx == USART2)
00155   {
00156     /* Force reset of USART clock */
00157     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
00158
00159     /* Release reset of USART clock */
00160     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
00161   }
00162 #if defined(USART3)
00163   else if (USARTx == USART3)
00164   {
00165     /* Force reset of USART clock */
00166     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
00167
00168     /* Release reset of USART clock */
00169     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
00170   }
00171 #endif /* USART3 */
00172 #if defined(UART4)
00173   else if (USARTx == UART4)
00174   {
00175     /* Force reset of UART clock */
00176     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
00177
00178     /* Release reset of UART clock */
00179     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
00180   }
00181 #endif /* UART4 */
00182 #if defined(UART5)
00183   else if (USARTx == UART5)
00184   {
00185     /* Force reset of UART clock */
00186     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
00187
00188     /* Release reset of UART clock */
00189     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
00190   }
00191 #endif /* UART5 */
00192   else
00193   {
00194     status = ERROR;
00195   }
00196
00197   return (status);
00198 }
00199
00200 /**
00201   * @brief  Initialize USART registers according to the specified
00202   *         parameters in USART_InitStruct.
00203   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00204   *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00205   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
00206   * @param  USARTx USART Instance
00207   * @param  USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
00208   *         that contains the configuration information for the specified USART peripheral.
00209   * @retval An ErrorStatus enumeration value:
00210   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
00211   *          - ERROR: Problem occurred during USART Registers initialization
00212   */
00213 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
00214 {
00215   ErrorStatus status = ERROR;
00216   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
00217   LL_RCC_ClocksTypeDef rcc_clocks;
00218
00219   /* Check the parameters */
00220   assert_param(IS_UART_INSTANCE(USARTx));
00221   assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
00222   assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
00223   assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
00224   assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
00225   assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
00226   assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
00227 #if defined(USART_CR1_OVER8)
00228   assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
00229 #endif /* USART_OverSampling_Feature */
00230
00231   /* USART needs to be in disabled state, in order to be able to configure some bits in
00232      CRx registers */
00233   if (LL_USART_IsEnabled(USARTx) == 0U)
00234   {
00235     /*---------------------------- USART CR1 Configuration -----------------------
00236      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
00237      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
00238      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
00239      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
00240      * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
00241      */
00242 #if defined(USART_CR1_OVER8)
00243     MODIFY_REG(USARTx->CR1,
00244                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
00245                 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
00246                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
00247                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
00248 #else
00249     MODIFY_REG(USARTx->CR1,
00250                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
00251                 USART_CR1_TE | USART_CR1_RE),
00252                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
00253                 USART_InitStruct->TransferDirection));
00254 #endif /* USART_OverSampling_Feature */
00255
00256     /*---------------------------- USART CR2 Configuration -----------------------
00257      * Configure USARTx CR2 (Stop bits) with parameters:
00258      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
00259      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
00260      */
00261     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
00262
00263     /*---------------------------- USART CR3 Configuration -----------------------
00264      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
00265      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
00266      */
00267     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
00268
00269     /*---------------------------- USART BRR Configuration -----------------------
00270      * Retrieve Clock frequency used for USART Peripheral
00271      */
00272     LL_RCC_GetSystemClocksFreq(&rcc_clocks);
00273     if (USARTx == USART1)
00274     {
00275       periphclk = rcc_clocks.PCLK2_Frequency;
00276     }
00277     else if (USARTx == USART2)
00278     {
00279       periphclk = rcc_clocks.PCLK1_Frequency;
00280     }
00281 #if defined(USART3)
00282     else if (USARTx == USART3)
00283     {
00284       periphclk = rcc_clocks.PCLK1_Frequency;
00285     }
00286 #endif /* USART3 */
00287 #if defined(UART4)
00288     else if (USARTx == UART4)
00289     {
00290       periphclk = rcc_clocks.PCLK1_Frequency;
00291     }
00292 #endif /* UART4 */
00293 #if defined(UART5)
00294     else if (USARTx == UART5)
00295     {
00296       periphclk = rcc_clocks.PCLK1_Frequency;
00297     }
00298 #endif /* UART5 */
00299     else
00300     {
00301       /* Nothing to do, as error code is already assigned to ERROR value */
00302     }
00303
00304     /* Configure the USART Baud Rate :
00305        - valid baud rate value (different from 0) is required
00306        - Peripheral clock as returned by RCC service, should be valid (different from 0).
00307     */
00308     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
00309         && (USART_InitStruct->BaudRate != 0U))
00310     {
00311       status = SUCCESS;
00312 #if defined(USART_CR1_OVER8)
00313       LL_USART_SetBaudRate(USARTx,
00314                            periphclk,
00315                            USART_InitStruct->OverSampling,
00316                            USART_InitStruct->BaudRate);
00317 #else
00318       LL_USART_SetBaudRate(USARTx,
00319                            periphclk,
00320                            USART_InitStruct->BaudRate);
00321 #endif /* USART_OverSampling_Feature */
00322     }
00323   }
00324   /* Endif (=> USART not in Disabled state => return ERROR) */
00325
00326   return (status);
00327 }
00328
00329 /**
00330   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
00331   * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
00332   *                          whose fields will be set to default values.
00333   * @retval None
00334   */
00335
00336 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
00337 {
00338   /* Set USART_InitStruct fields to default values */
00339   USART_InitStruct->BaudRate            = 9600U;
00340   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
00341   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
00342   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
00343   USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
00344   USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
00345 #if defined(USART_CR1_OVER8)
00346   USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
00347 #endif /* USART_OverSampling_Feature */
00348 }
00349
00350 /**
00351   * @brief  Initialize USART Clock related settings according to the
00352   *         specified parameters in the USART_ClockInitStruct.
00353   * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
00354   *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
00355   * @param  USARTx USART Instance
00356   * @param  USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
00357   *         that contains the Clock configuration information for the specified USART peripheral.
00358   * @retval An ErrorStatus enumeration value:
00359   *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
00360   *          - ERROR: Problem occurred during USART Registers initialization
00361   */
00362 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00363 {
00364   ErrorStatus status = SUCCESS;
00365
00366   /* Check USART Instance and Clock signal output parameters */
00367   assert_param(IS_UART_INSTANCE(USARTx));
00368   assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
00369
00370   /* USART needs to be in disabled state, in order to be able to configure some bits in
00371      CRx registers */
00372   if (LL_USART_IsEnabled(USARTx) == 0U)
00373   {
00374     /*---------------------------- USART CR2 Configuration -----------------------*/
00375     /* If Clock signal has to be output */
00376     if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
00377     {
00378       /* Deactivate Clock signal delivery :
00379        * - Disable Clock Output:        USART_CR2_CLKEN cleared
00380        */
00381       LL_USART_DisableSCLKOutput(USARTx);
00382     }
00383     else
00384     {
00385       /* Ensure USART instance is USART capable */
00386       assert_param(IS_USART_INSTANCE(USARTx));
00387
00388       /* Check clock related parameters */
00389       assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
00390       assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
00391       assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
00392
00393       /*---------------------------- USART CR2 Configuration -----------------------
00394        * Configure USARTx CR2 (Clock signal related bits) with parameters:
00395        * - Enable Clock Output:         USART_CR2_CLKEN set
00396        * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
00397        * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
00398        * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
00399        */
00400       MODIFY_REG(USARTx->CR2,
00401                  USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
00402                  USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
00403                  USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
00404     }
00405   }
00406   /* Else (USART not in Disabled state => return ERROR */
00407   else
00408   {
00409     status = ERROR;
00410   }
00411
00412   return (status);
00413 }
00414
00415 /**
00416   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
00417   * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
00418   *                               whose fields will be set to default values.
00419   * @retval None
00420   */
00421 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
00422 {
00423   /* Set LL_USART_ClockInitStruct fields with default values */
00424   USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
00425   USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00426   USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00427   USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
00428 }
00429
00430 /**
00431   * @}
00432   */
00433
00434 /**
00435   * @}
00436   */
00437
00438 /**
00439   * @}
00440   */
00441
00442 #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
00443
00444 /**
00445   * @}
00446   */
00447
00448 #endif /* USE_FULL_LL_DRIVER */
00449
00450 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00451
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STM32F103xB HAL User Manual: stm32f1xx_ll_usart.h Source File

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stm32f1xx_ll_usart.h
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_usart.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of USART LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_USART_H
00040 #define __STM32F1xx_LL_USART_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
00054
00055 /** @defgroup USART_LL USART
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup USART_LL_Private_Constants USART Private Constants
00064   * @{
00065   */
00066
00067 /* Defines used for the bit position in the register and perform offsets*/
00068 #define USART_POSITION_GTPR_GT                  USART_GTPR_GT_Pos
00069 /**
00070   * @}
00071   */
00072
00073 /* Private macros ------------------------------------------------------------*/
00074 #if defined(USE_FULL_LL_DRIVER)
00075 /** @defgroup USART_LL_Private_Macros USART Private Macros
00076   * @{
00077   */
00078 /**
00079   * @}
00080   */
00081 #endif /*USE_FULL_LL_DRIVER*/
00082
00083 /* Exported types ------------------------------------------------------------*/
00084 #if defined(USE_FULL_LL_DRIVER)
00085 /** @defgroup USART_LL_ES_INIT USART Exported Init structures
00086   * @{
00087   */
00088
00089 /**
00090   * @brief LL USART Init Structure definition
00091   */
00092 typedef struct
00093 {
00094   uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
00095
00096                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
00097
00098   uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
00099                                            This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
00100
00101                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
00102
00103   uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
00104                                            This parameter can be a value of @ref USART_LL_EC_STOPBITS.
00105
00106                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
00107
00108   uint32_t Parity;                    /*!< Specifies the parity mode.
00109                                            This parameter can be a value of @ref USART_LL_EC_PARITY.
00110
00111                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
00112
00113   uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
00114                                            This parameter can be a value of @ref USART_LL_EC_DIRECTION.
00115
00116                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
00117
00118   uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
00119                                            This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
00120
00121                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
00122
00123 #if defined(USART_CR1_OVER8)
00124   uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
00125                                            This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
00126
00127                                            This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
00128
00129 #endif /* USART_OverSampling_Feature */
00130 } LL_USART_InitTypeDef;
00131
00132 /**
00133   * @brief LL USART Clock Init Structure definition
00134   */
00135 typedef struct
00136 {
00137   uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
00138                                            This parameter can be a value of @ref USART_LL_EC_CLOCK.
00139
00140                                            USART HW configuration can be modified afterwards using unitary functions
00141                                            @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
00142                                            For more details, refer to description of this function. */
00143
00144   uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
00145                                            This parameter can be a value of @ref USART_LL_EC_POLARITY.
00146
00147                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
00148                                            For more details, refer to description of this function. */
00149
00150   uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
00151                                            This parameter can be a value of @ref USART_LL_EC_PHASE.
00152
00153                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
00154                                            For more details, refer to description of this function. */
00155
00156   uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
00157                                            data bit (MSB) has to be output on the SCLK pin in synchronous mode.
00158                                            This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
00159
00160                                            USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
00161                                            For more details, refer to description of this function. */
00162
00163 } LL_USART_ClockInitTypeDef;
00164
00165 /**
00166   * @}
00167   */
00168 #endif /* USE_FULL_LL_DRIVER */
00169
00170 /* Exported constants --------------------------------------------------------*/
00171 /** @defgroup USART_LL_Exported_Constants USART Exported Constants
00172   * @{
00173   */
00174
00175 /** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
00176   * @brief    Flags defines which can be used with LL_USART_ReadReg function
00177   * @{
00178   */
00179 #define LL_USART_SR_PE                          USART_SR_PE                   /*!< Parity error flag */
00180 #define LL_USART_SR_FE                          USART_SR_FE                   /*!< Framing error flag */
00181 #define LL_USART_SR_NE                          USART_SR_NE                   /*!< Noise detected flag */
00182 #define LL_USART_SR_ORE                         USART_SR_ORE                  /*!< Overrun error flag */
00183 #define LL_USART_SR_IDLE                        USART_SR_IDLE                 /*!< Idle line detected flag */
00184 #define LL_USART_SR_RXNE                        USART_SR_RXNE                 /*!< Read data register not empty flag */
00185 #define LL_USART_SR_TC                          USART_SR_TC                   /*!< Transmission complete flag */
00186 #define LL_USART_SR_TXE                         USART_SR_TXE                  /*!< Transmit data register empty flag */
00187 #define LL_USART_SR_LBD                         USART_SR_LBD                  /*!< LIN break detection flag */
00188 #define LL_USART_SR_CTS                         USART_SR_CTS                  /*!< CTS flag */
00189 /**
00190   * @}
00191   */
00192
00193 /** @defgroup USART_LL_EC_IT IT Defines
00194   * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
00195   * @{
00196   */
00197 #define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
00198 #define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
00199 #define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
00200 #define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
00201 #define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
00202 #define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
00203 #define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
00204 #define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
00205 /**
00206   * @}
00207   */
00208
00209 /** @defgroup USART_LL_EC_DIRECTION Communication Direction
00210   * @{
00211   */
00212 #define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
00213 #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
00214 #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
00215 #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
00216 /**
00217   * @}
00218   */
00219
00220 /** @defgroup USART_LL_EC_PARITY Parity Control
00221   * @{
00222   */
00223 #define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
00224 #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
00225 #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
00226 /**
00227   * @}
00228   */
00229
00230 /** @defgroup USART_LL_EC_WAKEUP Wakeup
00231   * @{
00232   */
00233 #define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
00234 #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
00235 /**
00236   * @}
00237   */
00238
00239 /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
00240   * @{
00241   */
00242 #define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
00243 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M             /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
00244 /**
00245   * @}
00246   */
00247
00248 #if defined(USART_CR1_OVER8)
00249 /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
00250   * @{
00251   */
00252 #define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
00253 #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
00254 /**
00255   * @}
00256   */
00257
00258 #endif /* USART_OverSampling_Feature */
00259 #if defined(USE_FULL_LL_DRIVER)
00260 /** @defgroup USART_LL_EC_CLOCK Clock Signal
00261   * @{
00262   */
00263
00264 #define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
00265 #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
00266 /**
00267   * @}
00268   */
00269 #endif /*USE_FULL_LL_DRIVER*/
00270
00271 /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
00272   * @{
00273   */
00274 #define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
00275 #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
00276 /**
00277   * @}
00278   */
00279
00280 /** @defgroup USART_LL_EC_PHASE Clock Phase
00281   * @{
00282   */
00283 #define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
00284 #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
00285 /**
00286   * @}
00287   */
00288
00289 /** @defgroup USART_LL_EC_POLARITY Clock Polarity
00290   * @{
00291   */
00292 #define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
00293 #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
00294 /**
00295   * @}
00296   */
00297
00298 /** @defgroup USART_LL_EC_STOPBITS Stop Bits
00299   * @{
00300   */
00301 #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
00302 #define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
00303 #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
00304 #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
00305 /**
00306   * @}
00307   */
00308
00309 /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
00310   * @{
00311   */
00312 #define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
00313 #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
00314 #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
00315 #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
00316 /**
00317   * @}
00318   */
00319
00320 /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
00321   * @{
00322   */
00323 #define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
00324 #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
00325 /**
00326   * @}
00327   */
00328
00329 /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
00330   * @{
00331   */
00332 #define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
00333 #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
00334 /**
00335   * @}
00336   */
00337
00338 /**
00339   * @}
00340   */
00341
00342 /* Exported macro ------------------------------------------------------------*/
00343 /** @defgroup USART_LL_Exported_Macros USART Exported Macros
00344   * @{
00345   */
00346
00347 /** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
00348   * @{
00349   */
00350
00351 /**
00352   * @brief  Write a value in USART register
00353   * @param  __INSTANCE__ USART Instance
00354   * @param  __REG__ Register to be written
00355   * @param  __VALUE__ Value to be written in the register
00356   * @retval None
00357   */
00358 #define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00359
00360 /**
00361   * @brief  Read a value in USART register
00362   * @param  __INSTANCE__ USART Instance
00363   * @param  __REG__ Register to be read
00364   * @retval Register value
00365   */
00366 #define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00367 /**
00368   * @}
00369   */
00370
00371 /** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
00372   * @{
00373   */
00374
00375 /**
00376   * @brief  Compute USARTDIV value according to Peripheral Clock and
00377   *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
00378   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00379   * @param  __BAUDRATE__ Baud rate value to achieve
00380   * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
00381   */
00382 #define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__)      (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))
00383 #define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
00384 #define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
00385 /* UART BRR = mantissa + overflow + fraction
00386             = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
00387 #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)             (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
00388                                                                            ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
00389                                                                            (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
00390
00391 /**
00392   * @brief  Compute USARTDIV value according to Peripheral Clock and
00393   *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
00394   * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
00395   * @param  __BAUDRATE__ Baud rate value to achieve
00396   * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
00397   */
00398 #define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__)     (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
00399 #define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
00400 #define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
00401 /* USART BRR = mantissa + overflow + fraction
00402             = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
00403 #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)            (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
00404                                                                            (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
00405                                                                            (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
00406
00407 /**
00408   * @}
00409   */
00410
00411 /**
00412   * @}
00413   */
00414
00415 /* Exported functions --------------------------------------------------------*/
00416
00417 /** @defgroup USART_LL_Exported_Functions USART Exported Functions
00418   * @{
00419   */
00420
00421 /** @defgroup USART_LL_EF_Configuration Configuration functions
00422   * @{
00423   */
00424
00425 /**
00426   * @brief  USART Enable
00427   * @rmtoll CR1          UE            LL_USART_Enable
00428   * @param  USARTx USART Instance
00429   * @retval None
00430   */
00431 __STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
00432 {
00433   SET_BIT(USARTx->CR1, USART_CR1_UE);
00434 }
00435
00436 /**
00437   * @brief  USART Disable (all USART prescalers and outputs are disabled)
00438   * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
00439   *         and current operations are discarded. The configuration of the USART is kept, but all the status
00440   *         flags, in the USARTx_SR are set to their default values.
00441   * @rmtoll CR1          UE            LL_USART_Disable
00442   * @param  USARTx USART Instance
00443   * @retval None
00444   */
00445 __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
00446 {
00447   CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
00448 }
00449
00450 /**
00451   * @brief  Indicate if USART is enabled
00452   * @rmtoll CR1          UE            LL_USART_IsEnabled
00453   * @param  USARTx USART Instance
00454   * @retval State of bit (1 or 0).
00455   */
00456 __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
00457 {
00458   return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
00459 }
00460
00461 /**
00462   * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
00463   * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
00464   * @param  USARTx USART Instance
00465   * @retval None
00466   */
00467 __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
00468 {
00469   SET_BIT(USARTx->CR1, USART_CR1_RE);
00470 }
00471
00472 /**
00473   * @brief  Receiver Disable
00474   * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
00475   * @param  USARTx USART Instance
00476   * @retval None
00477   */
00478 __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
00479 {
00480   CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
00481 }
00482
00483 /**
00484   * @brief  Transmitter Enable
00485   * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
00486   * @param  USARTx USART Instance
00487   * @retval None
00488   */
00489 __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
00490 {
00491   SET_BIT(USARTx->CR1, USART_CR1_TE);
00492 }
00493
00494 /**
00495   * @brief  Transmitter Disable
00496   * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
00497   * @param  USARTx USART Instance
00498   * @retval None
00499   */
00500 __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
00501 {
00502   CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
00503 }
00504
00505 /**
00506   * @brief  Configure simultaneously enabled/disabled states
00507   *         of Transmitter and Receiver
00508   * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
00509   *         CR1          TE            LL_USART_SetTransferDirection
00510   * @param  USARTx USART Instance
00511   * @param  TransferDirection This parameter can be one of the following values:
00512   *         @arg @ref LL_USART_DIRECTION_NONE
00513   *         @arg @ref LL_USART_DIRECTION_RX
00514   *         @arg @ref LL_USART_DIRECTION_TX
00515   *         @arg @ref LL_USART_DIRECTION_TX_RX
00516   * @retval None
00517   */
00518 __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
00519 {
00520   MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
00521 }
00522
00523 /**
00524   * @brief  Return enabled/disabled states of Transmitter and Receiver
00525   * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
00526   *         CR1          TE            LL_USART_GetTransferDirection
00527   * @param  USARTx USART Instance
00528   * @retval Returned value can be one of the following values:
00529   *         @arg @ref LL_USART_DIRECTION_NONE
00530   *         @arg @ref LL_USART_DIRECTION_RX
00531   *         @arg @ref LL_USART_DIRECTION_TX
00532   *         @arg @ref LL_USART_DIRECTION_TX_RX
00533   */
00534 __STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
00535 {
00536   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
00537 }
00538
00539 /**
00540   * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
00541   * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
00542   *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
00543   *         (9th or 8th bit depending on data width) and parity is checked on the received data.
00544   * @rmtoll CR1          PS            LL_USART_SetParity\n
00545   *         CR1          PCE           LL_USART_SetParity
00546   * @param  USARTx USART Instance
00547   * @param  Parity This parameter can be one of the following values:
00548   *         @arg @ref LL_USART_PARITY_NONE
00549   *         @arg @ref LL_USART_PARITY_EVEN
00550   *         @arg @ref LL_USART_PARITY_ODD
00551   * @retval None
00552   */
00553 __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
00554 {
00555   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
00556 }
00557
00558 /**
00559   * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
00560   * @rmtoll CR1          PS            LL_USART_GetParity\n
00561   *         CR1          PCE           LL_USART_GetParity
00562   * @param  USARTx USART Instance
00563   * @retval Returned value can be one of the following values:
00564   *         @arg @ref LL_USART_PARITY_NONE
00565   *         @arg @ref LL_USART_PARITY_EVEN
00566   *         @arg @ref LL_USART_PARITY_ODD
00567   */
00568 __STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
00569 {
00570   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
00571 }
00572
00573 /**
00574   * @brief  Set Receiver Wake Up method from Mute mode.
00575   * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
00576   * @param  USARTx USART Instance
00577   * @param  Method This parameter can be one of the following values:
00578   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00579   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00580   * @retval None
00581   */
00582 __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
00583 {
00584   MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
00585 }
00586
00587 /**
00588   * @brief  Return Receiver Wake Up method from Mute mode
00589   * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
00590   * @param  USARTx USART Instance
00591   * @retval Returned value can be one of the following values:
00592   *         @arg @ref LL_USART_WAKEUP_IDLELINE
00593   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
00594   */
00595 __STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
00596 {
00597   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
00598 }
00599
00600 /**
00601   * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
00602   * @rmtoll CR1          M             LL_USART_SetDataWidth
00603   * @param  USARTx USART Instance
00604   * @param  DataWidth This parameter can be one of the following values:
00605   *         @arg @ref LL_USART_DATAWIDTH_8B
00606   *         @arg @ref LL_USART_DATAWIDTH_9B
00607   * @retval None
00608   */
00609 __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
00610 {
00611   MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
00612 }
00613
00614 /**
00615   * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
00616   * @rmtoll CR1          M             LL_USART_GetDataWidth
00617   * @param  USARTx USART Instance
00618   * @retval Returned value can be one of the following values:
00619   *         @arg @ref LL_USART_DATAWIDTH_8B
00620   *         @arg @ref LL_USART_DATAWIDTH_9B
00621   */
00622 __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
00623 {
00624   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
00625 }
00626
00627 #if defined(USART_CR1_OVER8)
00628 /**
00629   * @brief  Set Oversampling to 8-bit or 16-bit mode
00630   * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
00631   * @param  USARTx USART Instance
00632   * @param  OverSampling This parameter can be one of the following values:
00633   *         @arg @ref LL_USART_OVERSAMPLING_16
00634   *         @arg @ref LL_USART_OVERSAMPLING_8
00635   * @retval None
00636   */
00637 __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
00638 {
00639   MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
00640 }
00641
00642 /**
00643   * @brief  Return Oversampling mode
00644   * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
00645   * @param  USARTx USART Instance
00646   * @retval Returned value can be one of the following values:
00647   *         @arg @ref LL_USART_OVERSAMPLING_16
00648   *         @arg @ref LL_USART_OVERSAMPLING_8
00649   */
00650 __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
00651 {
00652   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
00653 }
00654
00655 #endif /* USART_OverSampling_Feature */
00656 /**
00657   * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
00658   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00659   *         Synchronous mode is supported by the USARTx instance.
00660   * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
00661   * @param  USARTx USART Instance
00662   * @param  LastBitClockPulse This parameter can be one of the following values:
00663   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
00664   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
00665   * @retval None
00666   */
00667 __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
00668 {
00669   MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
00670 }
00671
00672 /**
00673   * @brief  Retrieve Clock pulse of the last data bit output configuration
00674   *         (Last bit Clock pulse output to the SCLK pin or not)
00675   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00676   *         Synchronous mode is supported by the USARTx instance.
00677   * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
00678   * @param  USARTx USART Instance
00679   * @retval Returned value can be one of the following values:
00680   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
00681   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
00682   */
00683 __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
00684 {
00685   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
00686 }
00687
00688 /**
00689   * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
00690   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00691   *         Synchronous mode is supported by the USARTx instance.
00692   * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
00693   * @param  USARTx USART Instance
00694   * @param  ClockPhase This parameter can be one of the following values:
00695   *         @arg @ref LL_USART_PHASE_1EDGE
00696   *         @arg @ref LL_USART_PHASE_2EDGE
00697   * @retval None
00698   */
00699 __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
00700 {
00701   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
00702 }
00703
00704 /**
00705   * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
00706   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00707   *         Synchronous mode is supported by the USARTx instance.
00708   * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
00709   * @param  USARTx USART Instance
00710   * @retval Returned value can be one of the following values:
00711   *         @arg @ref LL_USART_PHASE_1EDGE
00712   *         @arg @ref LL_USART_PHASE_2EDGE
00713   */
00714 __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
00715 {
00716   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
00717 }
00718
00719 /**
00720   * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
00721   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00722   *         Synchronous mode is supported by the USARTx instance.
00723   * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
00724   * @param  USARTx USART Instance
00725   * @param  ClockPolarity This parameter can be one of the following values:
00726   *         @arg @ref LL_USART_POLARITY_LOW
00727   *         @arg @ref LL_USART_POLARITY_HIGH
00728   * @retval None
00729   */
00730 __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
00731 {
00732   MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
00733 }
00734
00735 /**
00736   * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
00737   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00738   *         Synchronous mode is supported by the USARTx instance.
00739   * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
00740   * @param  USARTx USART Instance
00741   * @retval Returned value can be one of the following values:
00742   *         @arg @ref LL_USART_POLARITY_LOW
00743   *         @arg @ref LL_USART_POLARITY_HIGH
00744   */
00745 __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
00746 {
00747   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
00748 }
00749
00750 /**
00751   * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
00752   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00753   *         Synchronous mode is supported by the USARTx instance.
00754   * @note   Call of this function is equivalent to following function call sequence :
00755   *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
00756   *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
00757   *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
00758   * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
00759   *         CR2          CPOL          LL_USART_ConfigClock\n
00760   *         CR2          LBCL          LL_USART_ConfigClock
00761   * @param  USARTx USART Instance
00762   * @param  Phase This parameter can be one of the following values:
00763   *         @arg @ref LL_USART_PHASE_1EDGE
00764   *         @arg @ref LL_USART_PHASE_2EDGE
00765   * @param  Polarity This parameter can be one of the following values:
00766   *         @arg @ref LL_USART_POLARITY_LOW
00767   *         @arg @ref LL_USART_POLARITY_HIGH
00768   * @param  LBCPOutput This parameter can be one of the following values:
00769   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
00770   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
00771   * @retval None
00772   */
00773 __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
00774 {
00775   MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
00776 }
00777
00778 /**
00779   * @brief  Enable Clock output on SCLK pin
00780   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00781   *         Synchronous mode is supported by the USARTx instance.
00782   * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
00783   * @param  USARTx USART Instance
00784   * @retval None
00785   */
00786 __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
00787 {
00788   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
00789 }
00790
00791 /**
00792   * @brief  Disable Clock output on SCLK pin
00793   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00794   *         Synchronous mode is supported by the USARTx instance.
00795   * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
00796   * @param  USARTx USART Instance
00797   * @retval None
00798   */
00799 __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
00800 {
00801   CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
00802 }
00803
00804 /**
00805   * @brief  Indicate if Clock output on SCLK pin is enabled
00806   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
00807   *         Synchronous mode is supported by the USARTx instance.
00808   * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
00809   * @param  USARTx USART Instance
00810   * @retval State of bit (1 or 0).
00811   */
00812 __STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
00813 {
00814   return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
00815 }
00816
00817 /**
00818   * @brief  Set the length of the stop bits
00819   * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
00820   * @param  USARTx USART Instance
00821   * @param  StopBits This parameter can be one of the following values:
00822   *         @arg @ref LL_USART_STOPBITS_0_5
00823   *         @arg @ref LL_USART_STOPBITS_1
00824   *         @arg @ref LL_USART_STOPBITS_1_5
00825   *         @arg @ref LL_USART_STOPBITS_2
00826   * @retval None
00827   */
00828 __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
00829 {
00830   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
00831 }
00832
00833 /**
00834   * @brief  Retrieve the length of the stop bits
00835   * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
00836   * @param  USARTx USART Instance
00837   * @retval Returned value can be one of the following values:
00838   *         @arg @ref LL_USART_STOPBITS_0_5
00839   *         @arg @ref LL_USART_STOPBITS_1
00840   *         @arg @ref LL_USART_STOPBITS_1_5
00841   *         @arg @ref LL_USART_STOPBITS_2
00842   */
00843 __STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
00844 {
00845   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
00846 }
00847
00848 /**
00849   * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
00850   * @note   Call of this function is equivalent to following function call sequence :
00851   *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
00852   *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
00853   *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
00854   * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
00855   *         CR1          PCE           LL_USART_ConfigCharacter\n
00856   *         CR1          M             LL_USART_ConfigCharacter\n
00857   *         CR2          STOP          LL_USART_ConfigCharacter
00858   * @param  USARTx USART Instance
00859   * @param  DataWidth This parameter can be one of the following values:
00860   *         @arg @ref LL_USART_DATAWIDTH_8B
00861   *         @arg @ref LL_USART_DATAWIDTH_9B
00862   * @param  Parity This parameter can be one of the following values:
00863   *         @arg @ref LL_USART_PARITY_NONE
00864   *         @arg @ref LL_USART_PARITY_EVEN
00865   *         @arg @ref LL_USART_PARITY_ODD
00866   * @param  StopBits This parameter can be one of the following values:
00867   *         @arg @ref LL_USART_STOPBITS_0_5
00868   *         @arg @ref LL_USART_STOPBITS_1
00869   *         @arg @ref LL_USART_STOPBITS_1_5
00870   *         @arg @ref LL_USART_STOPBITS_2
00871   * @retval None
00872   */
00873 __STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
00874                                               uint32_t StopBits)
00875 {
00876   MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
00877   MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
00878 }
00879
00880 /**
00881   * @brief  Set Address of the USART node.
00882   * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
00883   *         for wake up with address mark detection.
00884   * @rmtoll CR2          ADD           LL_USART_SetNodeAddress
00885   * @param  USARTx USART Instance
00886   * @param  NodeAddress 4 bit Address of the USART node.
00887   * @retval None
00888   */
00889 __STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
00890 {
00891   MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
00892 }
00893
00894 /**
00895   * @brief  Return 4 bit Address of the USART node as set in ADD field of CR2.
00896   * @note   only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
00897   * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
00898   * @param  USARTx USART Instance
00899   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
00900   */
00901 __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
00902 {
00903   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
00904 }
00905
00906 /**
00907   * @brief  Enable RTS HW Flow Control
00908   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
00909   *         Hardware Flow control feature is supported by the USARTx instance.
00910   * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
00911   * @param  USARTx USART Instance
00912   * @retval None
00913   */
00914 __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
00915 {
00916   SET_BIT(USARTx->CR3, USART_CR3_RTSE);
00917 }
00918
00919 /**
00920   * @brief  Disable RTS HW Flow Control
00921   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
00922   *         Hardware Flow control feature is supported by the USARTx instance.
00923   * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
00924   * @param  USARTx USART Instance
00925   * @retval None
00926   */
00927 __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
00928 {
00929   CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
00930 }
00931
00932 /**
00933   * @brief  Enable CTS HW Flow Control
00934   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
00935   *         Hardware Flow control feature is supported by the USARTx instance.
00936   * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
00937   * @param  USARTx USART Instance
00938   * @retval None
00939   */
00940 __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
00941 {
00942   SET_BIT(USARTx->CR3, USART_CR3_CTSE);
00943 }
00944
00945 /**
00946   * @brief  Disable CTS HW Flow Control
00947   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
00948   *         Hardware Flow control feature is supported by the USARTx instance.
00949   * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
00950   * @param  USARTx USART Instance
00951   * @retval None
00952   */
00953 __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
00954 {
00955   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
00956 }
00957
00958 /**
00959   * @brief  Configure HW Flow Control mode (both CTS and RTS)
00960   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
00961   *         Hardware Flow control feature is supported by the USARTx instance.
00962   * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
00963   *         CR3          CTSE          LL_USART_SetHWFlowCtrl
00964   * @param  USARTx USART Instance
00965   * @param  HardwareFlowControl This parameter can be one of the following values:
00966   *         @arg @ref LL_USART_HWCONTROL_NONE
00967   *         @arg @ref LL_USART_HWCONTROL_RTS
00968   *         @arg @ref LL_USART_HWCONTROL_CTS
00969   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
00970   * @retval None
00971   */
00972 __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
00973 {
00974   MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
00975 }
00976
00977 /**
00978   * @brief  Return HW Flow Control configuration (both CTS and RTS)
00979   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
00980   *         Hardware Flow control feature is supported by the USARTx instance.
00981   * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
00982   *         CR3          CTSE          LL_USART_GetHWFlowCtrl
00983   * @param  USARTx USART Instance
00984   * @retval Returned value can be one of the following values:
00985   *         @arg @ref LL_USART_HWCONTROL_NONE
00986   *         @arg @ref LL_USART_HWCONTROL_RTS
00987   *         @arg @ref LL_USART_HWCONTROL_CTS
00988   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
00989   */
00990 __STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
00991 {
00992   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
00993 }
00994
00995 #if defined(USART_CR3_ONEBIT)
00996 /**
00997   * @brief  Enable One bit sampling method
00998   * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
00999   * @param  USARTx USART Instance
01000   * @retval None
01001   */
01002 __STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
01003 {
01004   SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01005 }
01006
01007 /**
01008   * @brief  Disable One bit sampling method
01009   * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
01010   * @param  USARTx USART Instance
01011   * @retval None
01012   */
01013 __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
01014 {
01015   CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
01016 }
01017
01018 /**
01019   * @brief  Indicate if One bit sampling method is enabled
01020   * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
01021   * @param  USARTx USART Instance
01022   * @retval State of bit (1 or 0).
01023   */
01024 __STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
01025 {
01026   return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
01027 }
01028 #endif /* USART_OneBitSampling_Feature */
01029
01030 #if defined(USART_CR1_OVER8)
01031 /**
01032   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
01033   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
01034   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
01035   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
01036   *         (Baud rate value != 0)
01037   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
01038   * @param  USARTx USART Instance
01039   * @param  PeriphClk Peripheral Clock
01040   * @param  OverSampling This parameter can be one of the following values:
01041   *         @arg @ref LL_USART_OVERSAMPLING_16
01042   *         @arg @ref LL_USART_OVERSAMPLING_8
01043   * @param  BaudRate Baud Rate
01044   * @retval None
01045   */
01046 __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
01047                                           uint32_t BaudRate)
01048 {
01049   if (OverSampling == LL_USART_OVERSAMPLING_8)
01050   {
01051     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
01052   }
01053   else
01054   {
01055     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
01056   }
01057 }
01058
01059 /**
01060   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
01061   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
01062   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01063   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
01064   * @param  USARTx USART Instance
01065   * @param  PeriphClk Peripheral Clock
01066   * @param  OverSampling This parameter can be one of the following values:
01067   *         @arg @ref LL_USART_OVERSAMPLING_16
01068   *         @arg @ref LL_USART_OVERSAMPLING_8
01069   * @retval Baud Rate
01070   */
01071 __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
01072 {
01073   register uint32_t usartdiv = 0x0U;
01074   register uint32_t brrresult = 0x0U;
01075
01076   usartdiv = USARTx->BRR;
01077
01078   if (OverSampling == LL_USART_OVERSAMPLING_8)
01079   {
01080     if ((usartdiv & 0xFFF7U) != 0U)
01081     {
01082       usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
01083       brrresult = (PeriphClk * 2U) / usartdiv;
01084     }
01085   }
01086   else
01087   {
01088     if ((usartdiv & 0xFFFFU) != 0U)
01089     {
01090       brrresult = PeriphClk / usartdiv;
01091     }
01092   }
01093   return (brrresult);
01094 }
01095 #else
01096 /**
01097   * @brief  Configure USART BRR register for achieving expected Baud Rate value.
01098   * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
01099   *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
01100   * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
01101   *         (Baud rate value != 0)
01102   * @rmtoll BRR          BRR           LL_USART_SetBaudRate
01103   * @param  USARTx USART Instance
01104   * @param  PeriphClk Peripheral Clock
01105   * @param  BaudRate Baud Rate
01106   * @retval None
01107   */
01108 __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaudRate)
01109 {
01110     USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
01111 }
01112
01113 /**
01114   * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
01115   *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
01116   * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
01117   * @rmtoll BRR          BRR           LL_USART_GetBaudRate
01118   * @param  USARTx USART Instance
01119   * @param  PeriphClk Peripheral Clock
01120   * @retval Baud Rate
01121   */
01122 __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk)
01123 {
01124   register uint32_t usartdiv = 0x0U;
01125   register uint32_t brrresult = 0x0U;
01126
01127   usartdiv = USARTx->BRR;
01128
01129   if ((usartdiv & 0xFFFFU) != 0U)
01130   {
01131     brrresult = PeriphClk / usartdiv;
01132   }
01133   return (brrresult);
01134 }
01135 #endif /* USART_OverSampling_Feature */
01136
01137 /**
01138   * @}
01139   */
01140
01141 /** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
01142   * @{
01143   */
01144
01145 /**
01146   * @brief  Enable IrDA mode
01147   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01148   *         IrDA feature is supported by the USARTx instance.
01149   * @rmtoll CR3          IREN          LL_USART_EnableIrda
01150   * @param  USARTx USART Instance
01151   * @retval None
01152   */
01153 __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
01154 {
01155   SET_BIT(USARTx->CR3, USART_CR3_IREN);
01156 }
01157
01158 /**
01159   * @brief  Disable IrDA mode
01160   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01161   *         IrDA feature is supported by the USARTx instance.
01162   * @rmtoll CR3          IREN          LL_USART_DisableIrda
01163   * @param  USARTx USART Instance
01164   * @retval None
01165   */
01166 __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
01167 {
01168   CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
01169 }
01170
01171 /**
01172   * @brief  Indicate if IrDA mode is enabled
01173   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01174   *         IrDA feature is supported by the USARTx instance.
01175   * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
01176   * @param  USARTx USART Instance
01177   * @retval State of bit (1 or 0).
01178   */
01179 __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
01180 {
01181   return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
01182 }
01183
01184 /**
01185   * @brief  Configure IrDA Power Mode (Normal or Low Power)
01186   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01187   *         IrDA feature is supported by the USARTx instance.
01188   * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
01189   * @param  USARTx USART Instance
01190   * @param  PowerMode This parameter can be one of the following values:
01191   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
01192   *         @arg @ref LL_USART_IRDA_POWER_LOW
01193   * @retval None
01194   */
01195 __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
01196 {
01197   MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
01198 }
01199
01200 /**
01201   * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
01202   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01203   *         IrDA feature is supported by the USARTx instance.
01204   * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
01205   * @param  USARTx USART Instance
01206   * @retval Returned value can be one of the following values:
01207   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
01208   *         @arg @ref LL_USART_PHASE_2EDGE
01209   */
01210 __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
01211 {
01212   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
01213 }
01214
01215 /**
01216   * @brief  Set Irda prescaler value, used for dividing the USART clock source
01217   *         to achieve the Irda Low Power frequency (8 bits value)
01218   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01219   *         IrDA feature is supported by the USARTx instance.
01220   * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
01221   * @param  USARTx USART Instance
01222   * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
01223   * @retval None
01224   */
01225 __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01226 {
01227   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
01228 }
01229
01230 /**
01231   * @brief  Return Irda prescaler value, used for dividing the USART clock source
01232   *         to achieve the Irda Low Power frequency (8 bits value)
01233   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01234   *         IrDA feature is supported by the USARTx instance.
01235   * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
01236   * @param  USARTx USART Instance
01237   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
01238   */
01239 __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
01240 {
01241   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
01242 }
01243
01244 /**
01245   * @}
01246   */
01247
01248 /** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
01249   * @{
01250   */
01251
01252 /**
01253   * @brief  Enable Smartcard NACK transmission
01254   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01255   *         Smartcard feature is supported by the USARTx instance.
01256   * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
01257   * @param  USARTx USART Instance
01258   * @retval None
01259   */
01260 __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
01261 {
01262   SET_BIT(USARTx->CR3, USART_CR3_NACK);
01263 }
01264
01265 /**
01266   * @brief  Disable Smartcard NACK transmission
01267   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01268   *         Smartcard feature is supported by the USARTx instance.
01269   * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
01270   * @param  USARTx USART Instance
01271   * @retval None
01272   */
01273 __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
01274 {
01275   CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
01276 }
01277
01278 /**
01279   * @brief  Indicate if Smartcard NACK transmission is enabled
01280   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01281   *         Smartcard feature is supported by the USARTx instance.
01282   * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
01283   * @param  USARTx USART Instance
01284   * @retval State of bit (1 or 0).
01285   */
01286 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
01287 {
01288   return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
01289 }
01290
01291 /**
01292   * @brief  Enable Smartcard mode
01293   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01294   *         Smartcard feature is supported by the USARTx instance.
01295   * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
01296   * @param  USARTx USART Instance
01297   * @retval None
01298   */
01299 __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
01300 {
01301   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
01302 }
01303
01304 /**
01305   * @brief  Disable Smartcard mode
01306   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01307   *         Smartcard feature is supported by the USARTx instance.
01308   * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
01309   * @param  USARTx USART Instance
01310   * @retval None
01311   */
01312 __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
01313 {
01314   CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
01315 }
01316
01317 /**
01318   * @brief  Indicate if Smartcard mode is enabled
01319   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01320   *         Smartcard feature is supported by the USARTx instance.
01321   * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
01322   * @param  USARTx USART Instance
01323   * @retval State of bit (1 or 0).
01324   */
01325 __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
01326 {
01327   return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
01328 }
01329
01330 /**
01331   * @brief  Set Smartcard prescaler value, used for dividing the USART clock
01332   *         source to provide the SMARTCARD Clock (5 bits value)
01333   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01334   *         Smartcard feature is supported by the USARTx instance.
01335   * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
01336   * @param  USARTx USART Instance
01337   * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
01338   * @retval None
01339   */
01340 __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
01341 {
01342   MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
01343 }
01344
01345 /**
01346   * @brief  Return Smartcard prescaler value, used for dividing the USART clock
01347   *         source to provide the SMARTCARD Clock (5 bits value)
01348   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01349   *         Smartcard feature is supported by the USARTx instance.
01350   * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
01351   * @param  USARTx USART Instance
01352   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
01353   */
01354 __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
01355 {
01356   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
01357 }
01358
01359 /**
01360   * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
01361   *         (GT[7:0] bits : Guard time value)
01362   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01363   *         Smartcard feature is supported by the USARTx instance.
01364   * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
01365   * @param  USARTx USART Instance
01366   * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
01367   * @retval None
01368   */
01369 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
01370 {
01371   MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
01372 }
01373
01374 /**
01375   * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
01376   *         (GT[7:0] bits : Guard time value)
01377   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01378   *         Smartcard feature is supported by the USARTx instance.
01379   * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
01380   * @param  USARTx USART Instance
01381   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
01382   */
01383 __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
01384 {
01385   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
01386 }
01387
01388 /**
01389   * @}
01390   */
01391
01392 /** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
01393   * @{
01394   */
01395
01396 /**
01397   * @brief  Enable Single Wire Half-Duplex mode
01398   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
01399   *         Half-Duplex mode is supported by the USARTx instance.
01400   * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
01401   * @param  USARTx USART Instance
01402   * @retval None
01403   */
01404 __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
01405 {
01406   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
01407 }
01408
01409 /**
01410   * @brief  Disable Single Wire Half-Duplex mode
01411   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
01412   *         Half-Duplex mode is supported by the USARTx instance.
01413   * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
01414   * @param  USARTx USART Instance
01415   * @retval None
01416   */
01417 __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
01418 {
01419   CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
01420 }
01421
01422 /**
01423   * @brief  Indicate if Single Wire Half-Duplex mode is enabled
01424   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
01425   *         Half-Duplex mode is supported by the USARTx instance.
01426   * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
01427   * @param  USARTx USART Instance
01428   * @retval State of bit (1 or 0).
01429   */
01430 __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
01431 {
01432   return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
01433 }
01434
01435 /**
01436   * @}
01437   */
01438
01439 /** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
01440   * @{
01441   */
01442
01443 /**
01444   * @brief  Set LIN Break Detection Length
01445   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
01446   *         LIN feature is supported by the USARTx instance.
01447   * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
01448   * @param  USARTx USART Instance
01449   * @param  LINBDLength This parameter can be one of the following values:
01450   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
01451   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
01452   * @retval None
01453   */
01454 __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
01455 {
01456   MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
01457 }
01458
01459 /**
01460   * @brief  Return LIN Break Detection Length
01461   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
01462   *         LIN feature is supported by the USARTx instance.
01463   * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
01464   * @param  USARTx USART Instance
01465   * @retval Returned value can be one of the following values:
01466   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
01467   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
01468   */
01469 __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
01470 {
01471   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
01472 }
01473
01474 /**
01475   * @brief  Enable LIN mode
01476   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
01477   *         LIN feature is supported by the USARTx instance.
01478   * @rmtoll CR2          LINEN         LL_USART_EnableLIN
01479   * @param  USARTx USART Instance
01480   * @retval None
01481   */
01482 __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
01483 {
01484   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
01485 }
01486
01487 /**
01488   * @brief  Disable LIN mode
01489   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
01490   *         LIN feature is supported by the USARTx instance.
01491   * @rmtoll CR2          LINEN         LL_USART_DisableLIN
01492   * @param  USARTx USART Instance
01493   * @retval None
01494   */
01495 __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
01496 {
01497   CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
01498 }
01499
01500 /**
01501   * @brief  Indicate if LIN mode is enabled
01502   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
01503   *         LIN feature is supported by the USARTx instance.
01504   * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
01505   * @param  USARTx USART Instance
01506   * @retval State of bit (1 or 0).
01507   */
01508 __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
01509 {
01510   return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
01511 }
01512
01513 /**
01514   * @}
01515   */
01516
01517 /** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
01518   * @{
01519   */
01520
01521 /**
01522   * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
01523   * @note   In UART mode, the following bits must be kept cleared:
01524   *           - LINEN bit in the USART_CR2 register,
01525   *           - CLKEN bit in the USART_CR2 register,
01526   *           - SCEN bit in the USART_CR3 register,
01527   *           - IREN bit in the USART_CR3 register,
01528   *           - HDSEL bit in the USART_CR3 register.
01529   * @note   Call of this function is equivalent to following function call sequence :
01530   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
01531   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
01532   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
01533   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
01534   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
01535   * @note   Other remaining configurations items related to Asynchronous Mode
01536   *         (as Baud Rate, Word length, Parity, ...) should be set using
01537   *         dedicated functions
01538   * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
01539   *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
01540   *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
01541   *         CR3          IREN          LL_USART_ConfigAsyncMode\n
01542   *         CR3          HDSEL         LL_USART_ConfigAsyncMode
01543   * @param  USARTx USART Instance
01544   * @retval None
01545   */
01546 __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
01547 {
01548   /* In Asynchronous mode, the following bits must be kept cleared:
01549   - LINEN, CLKEN bits in the USART_CR2 register,
01550   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
01551   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
01552   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
01553 }
01554
01555 /**
01556   * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
01557   * @note   In Synchronous mode, the following bits must be kept cleared:
01558   *           - LINEN bit in the USART_CR2 register,
01559   *           - SCEN bit in the USART_CR3 register,
01560   *           - IREN bit in the USART_CR3 register,
01561   *           - HDSEL bit in the USART_CR3 register.
01562   *         This function also sets the USART in Synchronous mode.
01563   * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
01564   *         Synchronous mode is supported by the USARTx instance.
01565   * @note   Call of this function is equivalent to following function call sequence :
01566   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
01567   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
01568   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
01569   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
01570   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
01571   * @note   Other remaining configurations items related to Synchronous Mode
01572   *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
01573   *         dedicated functions
01574   * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
01575   *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
01576   *         CR3          SCEN          LL_USART_ConfigSyncMode\n
01577   *         CR3          IREN          LL_USART_ConfigSyncMode\n
01578   *         CR3          HDSEL         LL_USART_ConfigSyncMode
01579   * @param  USARTx USART Instance
01580   * @retval None
01581   */
01582 __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
01583 {
01584   /* In Synchronous mode, the following bits must be kept cleared:
01585   - LINEN bit in the USART_CR2 register,
01586   - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
01587   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
01588   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
01589   /* set the UART/USART in Synchronous mode */
01590   SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
01591 }
01592
01593 /**
01594   * @brief  Perform basic configuration of USART for enabling use in LIN Mode
01595   * @note   In LIN mode, the following bits must be kept cleared:
01596   *           - STOP and CLKEN bits in the USART_CR2 register,
01597   *           - SCEN bit in the USART_CR3 register,
01598   *           - IREN bit in the USART_CR3 register,
01599   *           - HDSEL bit in the USART_CR3 register.
01600   *         This function also set the UART/USART in LIN mode.
01601   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
01602   *         LIN feature is supported by the USARTx instance.
01603   * @note   Call of this function is equivalent to following function call sequence :
01604   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
01605   *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
01606   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
01607   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
01608   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
01609   *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
01610   * @note   Other remaining configurations items related to LIN Mode
01611   *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
01612   *         dedicated functions
01613   * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
01614   *         CR2          STOP          LL_USART_ConfigLINMode\n
01615   *         CR2          LINEN         LL_USART_ConfigLINMode\n
01616   *         CR3          IREN          LL_USART_ConfigLINMode\n
01617   *         CR3          SCEN          LL_USART_ConfigLINMode\n
01618   *         CR3          HDSEL         LL_USART_ConfigLINMode
01619   * @param  USARTx USART Instance
01620   * @retval None
01621   */
01622 __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
01623 {
01624   /* In LIN mode, the following bits must be kept cleared:
01625   - STOP and CLKEN bits in the USART_CR2 register,
01626   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
01627   CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
01628   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
01629   /* Set the UART/USART in LIN mode */
01630   SET_BIT(USARTx->CR2, USART_CR2_LINEN);
01631 }
01632
01633 /**
01634   * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
01635   * @note   In Half Duplex mode, the following bits must be kept cleared:
01636   *           - LINEN bit in the USART_CR2 register,
01637   *           - CLKEN bit in the USART_CR2 register,
01638   *           - SCEN bit in the USART_CR3 register,
01639   *           - IREN bit in the USART_CR3 register,
01640   *         This function also sets the UART/USART in Half Duplex mode.
01641   * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
01642   *         Half-Duplex mode is supported by the USARTx instance.
01643   * @note   Call of this function is equivalent to following function call sequence :
01644   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
01645   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
01646   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
01647   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
01648   *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
01649   * @note   Other remaining configurations items related to Half Duplex Mode
01650   *         (as Baud Rate, Word length, Parity, ...) should be set using
01651   *         dedicated functions
01652   * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
01653   *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
01654   *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
01655   *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
01656   *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
01657   * @param  USARTx USART Instance
01658   * @retval None
01659   */
01660 __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
01661 {
01662   /* In Half Duplex mode, the following bits must be kept cleared:
01663   - LINEN and CLKEN bits in the USART_CR2 register,
01664   - SCEN and IREN bits in the USART_CR3 register.*/
01665   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
01666   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
01667   /* set the UART/USART in Half Duplex mode */
01668   SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
01669 }
01670
01671 /**
01672   * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
01673   * @note   In Smartcard mode, the following bits must be kept cleared:
01674   *           - LINEN bit in the USART_CR2 register,
01675   *           - IREN bit in the USART_CR3 register,
01676   *           - HDSEL bit in the USART_CR3 register.
01677   *         This function also configures Stop bits to 1.5 bits and
01678   *         sets the USART in Smartcard mode (SCEN bit).
01679   *         Clock Output is also enabled (CLKEN).
01680   * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
01681   *         Smartcard feature is supported by the USARTx instance.
01682   * @note   Call of this function is equivalent to following function call sequence :
01683   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
01684   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
01685   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
01686   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
01687   *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
01688   *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
01689   * @note   Other remaining configurations items related to Smartcard Mode
01690   *         (as Baud Rate, Word length, Parity, ...) should be set using
01691   *         dedicated functions
01692   * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
01693   *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
01694   *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
01695   *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
01696   *         CR3          SCEN          LL_USART_ConfigSmartcardMode
01697   * @param  USARTx USART Instance
01698   * @retval None
01699   */
01700 __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
01701 {
01702   /* In Smartcard mode, the following bits must be kept cleared:
01703   - LINEN bit in the USART_CR2 register,
01704   - IREN and HDSEL bits in the USART_CR3 register.*/
01705   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
01706   CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
01707   /* Configure Stop bits to 1.5 bits */
01708   /* Synchronous mode is activated by default */
01709   SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
01710   /* set the UART/USART in Smartcard mode */
01711   SET_BIT(USARTx->CR3, USART_CR3_SCEN);
01712 }
01713
01714 /**
01715   * @brief  Perform basic configuration of USART for enabling use in Irda Mode
01716   * @note   In IRDA mode, the following bits must be kept cleared:
01717   *           - LINEN bit in the USART_CR2 register,
01718   *           - STOP and CLKEN bits in the USART_CR2 register,
01719   *           - SCEN bit in the USART_CR3 register,
01720   *           - HDSEL bit in the USART_CR3 register.
01721   *         This function also sets the UART/USART in IRDA mode (IREN bit).
01722   * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
01723   *         IrDA feature is supported by the USARTx instance.
01724   * @note   Call of this function is equivalent to following function call sequence :
01725   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
01726   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
01727   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
01728   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
01729   *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
01730   *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
01731   * @note   Other remaining configurations items related to Irda Mode
01732   *         (as Baud Rate, Word length, Power mode, ...) should be set using
01733   *         dedicated functions
01734   * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
01735   *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
01736   *         CR2          STOP          LL_USART_ConfigIrdaMode\n
01737   *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
01738   *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
01739   *         CR3          IREN          LL_USART_ConfigIrdaMode
01740   * @param  USARTx USART Instance
01741   * @retval None
01742   */
01743 __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
01744 {
01745   /* In IRDA mode, the following bits must be kept cleared:
01746   - LINEN, STOP and CLKEN bits in the USART_CR2 register,
01747   - SCEN and HDSEL bits in the USART_CR3 register.*/
01748   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
01749   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
01750   /* set the UART/USART in IRDA mode */
01751   SET_BIT(USARTx->CR3, USART_CR3_IREN);
01752 }
01753
01754 /**
01755   * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
01756   *         (several USARTs connected in a network, one of the USARTs can be the master,
01757   *         its TX output connected to the RX inputs of the other slaves USARTs).
01758   * @note   In MultiProcessor mode, the following bits must be kept cleared:
01759   *           - LINEN bit in the USART_CR2 register,
01760   *           - CLKEN bit in the USART_CR2 register,
01761   *           - SCEN bit in the USART_CR3 register,
01762   *           - IREN bit in the USART_CR3 register,
01763   *           - HDSEL bit in the USART_CR3 register.
01764   * @note   Call of this function is equivalent to following function call sequence :
01765   *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
01766   *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
01767   *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
01768   *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
01769   *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
01770   * @note   Other remaining configurations items related to Multi processor Mode
01771   *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
01772   *         dedicated functions
01773   * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
01774   *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
01775   *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
01776   *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
01777   *         CR3          IREN          LL_USART_ConfigMultiProcessMode
01778   * @param  USARTx USART Instance
01779   * @retval None
01780   */
01781 __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
01782 {
01783   /* In Multi Processor mode, the following bits must be kept cleared:
01784   - LINEN and CLKEN bits in the USART_CR2 register,
01785   - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
01786   CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
01787   CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
01788 }
01789
01790 /**
01791   * @}
01792   */
01793
01794 /** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
01795   * @{
01796   */
01797
01798 /**
01799   * @brief  Check if the USART Parity Error Flag is set or not
01800   * @rmtoll SR           PE            LL_USART_IsActiveFlag_PE
01801   * @param  USARTx USART Instance
01802   * @retval State of bit (1 or 0).
01803   */
01804 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
01805 {
01806   return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
01807 }
01808
01809 /**
01810   * @brief  Check if the USART Framing Error Flag is set or not
01811   * @rmtoll SR           FE            LL_USART_IsActiveFlag_FE
01812   * @param  USARTx USART Instance
01813   * @retval State of bit (1 or 0).
01814   */
01815 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
01816 {
01817   return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
01818 }
01819
01820 /**
01821   * @brief  Check if the USART Noise error detected Flag is set or not
01822   * @rmtoll SR           NF            LL_USART_IsActiveFlag_NE
01823   * @param  USARTx USART Instance
01824   * @retval State of bit (1 or 0).
01825   */
01826 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
01827 {
01828   return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
01829 }
01830
01831 /**
01832   * @brief  Check if the USART OverRun Error Flag is set or not
01833   * @rmtoll SR           ORE           LL_USART_IsActiveFlag_ORE
01834   * @param  USARTx USART Instance
01835   * @retval State of bit (1 or 0).
01836   */
01837 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
01838 {
01839   return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
01840 }
01841
01842 /**
01843   * @brief  Check if the USART IDLE line detected Flag is set or not
01844   * @rmtoll SR           IDLE          LL_USART_IsActiveFlag_IDLE
01845   * @param  USARTx USART Instance
01846   * @retval State of bit (1 or 0).
01847   */
01848 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
01849 {
01850   return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
01851 }
01852
01853 /**
01854   * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
01855   * @rmtoll SR           RXNE          LL_USART_IsActiveFlag_RXNE
01856   * @param  USARTx USART Instance
01857   * @retval State of bit (1 or 0).
01858   */
01859 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
01860 {
01861   return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
01862 }
01863
01864 /**
01865   * @brief  Check if the USART Transmission Complete Flag is set or not
01866   * @rmtoll SR           TC            LL_USART_IsActiveFlag_TC
01867   * @param  USARTx USART Instance
01868   * @retval State of bit (1 or 0).
01869   */
01870 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
01871 {
01872   return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
01873 }
01874
01875 /**
01876   * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
01877   * @rmtoll SR           TXE           LL_USART_IsActiveFlag_TXE
01878   * @param  USARTx USART Instance
01879   * @retval State of bit (1 or 0).
01880   */
01881 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
01882 {
01883   return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
01884 }
01885
01886 /**
01887   * @brief  Check if the USART LIN Break Detection Flag is set or not
01888   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
01889   *         LIN feature is supported by the USARTx instance.
01890   * @rmtoll SR           LBD           LL_USART_IsActiveFlag_LBD
01891   * @param  USARTx USART Instance
01892   * @retval State of bit (1 or 0).
01893   */
01894 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
01895 {
01896   return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
01897 }
01898
01899 /**
01900   * @brief  Check if the USART CTS Flag is set or not
01901   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
01902   *         Hardware Flow control feature is supported by the USARTx instance.
01903   * @rmtoll SR           CTS           LL_USART_IsActiveFlag_nCTS
01904   * @param  USARTx USART Instance
01905   * @retval State of bit (1 or 0).
01906   */
01907 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
01908 {
01909   return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
01910 }
01911
01912 /**
01913   * @brief  Check if the USART Send Break Flag is set or not
01914   * @rmtoll CR1          SBK           LL_USART_IsActiveFlag_SBK
01915   * @param  USARTx USART Instance
01916   * @retval State of bit (1 or 0).
01917   */
01918 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
01919 {
01920   return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
01921 }
01922
01923 /**
01924   * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
01925   * @rmtoll CR1          RWU           LL_USART_IsActiveFlag_RWU
01926   * @param  USARTx USART Instance
01927   * @retval State of bit (1 or 0).
01928   */
01929 __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
01930 {
01931   return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
01932 }
01933
01934 /**
01935   * @brief  Clear Parity Error Flag
01936   * @note   Clearing this flag is done by a read access to the USARTx_SR
01937   *         register followed by a read access to the USARTx_DR register.
01938   * @note   Please also consider that when clearing this flag, other flags as
01939   *         NE, FE, ORE, IDLE would also be cleared.
01940   * @rmtoll SR           PE            LL_USART_ClearFlag_PE
01941   * @param  USARTx USART Instance
01942   * @retval None
01943   */
01944 __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
01945 {
01946   __IO uint32_t tmpreg;
01947   tmpreg = USARTx->SR;
01948   (void) tmpreg;
01949   tmpreg = USARTx->DR;
01950   (void) tmpreg;
01951 }
01952
01953 /**
01954   * @brief  Clear Framing Error Flag
01955   * @note   Clearing this flag is done by a read access to the USARTx_SR
01956   *         register followed by a read access to the USARTx_DR register.
01957   * @note   Please also consider that when clearing this flag, other flags as
01958   *         PE, NE, ORE, IDLE would also be cleared.
01959   * @rmtoll SR           FE            LL_USART_ClearFlag_FE
01960   * @param  USARTx USART Instance
01961   * @retval None
01962   */
01963 __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
01964 {
01965   __IO uint32_t tmpreg;
01966   tmpreg = USARTx->SR;
01967   (void) tmpreg;
01968   tmpreg = USARTx->DR;
01969   (void) tmpreg;
01970 }
01971
01972 /**
01973   * @brief  Clear Noise detected Flag
01974   * @note   Clearing this flag is done by a read access to the USARTx_SR
01975   *         register followed by a read access to the USARTx_DR register.
01976   * @note   Please also consider that when clearing this flag, other flags as
01977   *         PE, FE, ORE, IDLE would also be cleared.
01978   * @rmtoll SR           NF            LL_USART_ClearFlag_NE
01979   * @param  USARTx USART Instance
01980   * @retval None
01981   */
01982 __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
01983 {
01984   __IO uint32_t tmpreg;
01985   tmpreg = USARTx->SR;
01986   (void) tmpreg;
01987   tmpreg = USARTx->DR;
01988   (void) tmpreg;
01989 }
01990
01991 /**
01992   * @brief  Clear OverRun Error Flag
01993   * @note   Clearing this flag is done by a read access to the USARTx_SR
01994   *         register followed by a read access to the USARTx_DR register.
01995   * @note   Please also consider that when clearing this flag, other flags as
01996   *         PE, NE, FE, IDLE would also be cleared.
01997   * @rmtoll SR           ORE           LL_USART_ClearFlag_ORE
01998   * @param  USARTx USART Instance
01999   * @retval None
02000   */
02001 __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
02002 {
02003   __IO uint32_t tmpreg;
02004   tmpreg = USARTx->SR;
02005   (void) tmpreg;
02006   tmpreg = USARTx->DR;
02007   (void) tmpreg;
02008 }
02009
02010 /**
02011   * @brief  Clear IDLE line detected Flag
02012   * @note   Clearing this flag is done by a read access to the USARTx_SR
02013   *         register followed by a read access to the USARTx_DR register.
02014   * @note   Please also consider that when clearing this flag, other flags as
02015   *         PE, NE, FE, ORE would also be cleared.
02016   * @rmtoll SR           IDLE          LL_USART_ClearFlag_IDLE
02017   * @param  USARTx USART Instance
02018   * @retval None
02019   */
02020 __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
02021 {
02022   __IO uint32_t tmpreg;
02023   tmpreg = USARTx->SR;
02024   (void) tmpreg;
02025   tmpreg = USARTx->DR;
02026   (void) tmpreg;
02027 }
02028
02029 /**
02030   * @brief  Clear Transmission Complete Flag
02031   * @rmtoll SR           TC            LL_USART_ClearFlag_TC
02032   * @param  USARTx USART Instance
02033   * @retval None
02034   */
02035 __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
02036 {
02037   WRITE_REG(USARTx->SR , ~(USART_SR_TC));
02038 }
02039
02040 /**
02041   * @brief  Clear RX Not Empty Flag
02042   * @rmtoll SR           RXNE          LL_USART_ClearFlag_RXNE
02043   * @param  USARTx USART Instance
02044   * @retval None
02045   */
02046 __STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
02047 {
02048   WRITE_REG(USARTx->SR , ~(USART_SR_RXNE));
02049 }
02050
02051 /**
02052   * @brief  Clear LIN Break Detection Flag
02053   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02054   *         LIN feature is supported by the USARTx instance.
02055   * @rmtoll SR           LBD           LL_USART_ClearFlag_LBD
02056   * @param  USARTx USART Instance
02057   * @retval None
02058   */
02059 __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
02060 {
02061   WRITE_REG(USARTx->SR , ~(USART_SR_LBD));
02062 }
02063
02064 /**
02065   * @brief  Clear CTS Interrupt Flag
02066   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
02067   *         Hardware Flow control feature is supported by the USARTx instance.
02068   * @rmtoll SR           CTS           LL_USART_ClearFlag_nCTS
02069   * @param  USARTx USART Instance
02070   * @retval None
02071   */
02072 __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
02073 {
02074   WRITE_REG(USARTx->SR , ~(USART_SR_CTS));
02075 }
02076
02077 /**
02078   * @}
02079   */
02080
02081 /** @defgroup USART_LL_EF_IT_Management IT_Management
02082   * @{
02083   */
02084
02085 /**
02086   * @brief  Enable IDLE Interrupt
02087   * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
02088   * @param  USARTx USART Instance
02089   * @retval None
02090   */
02091 __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
02092 {
02093   SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
02094 }
02095
02096 /**
02097   * @brief  Enable RX Not Empty Interrupt
02098   * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
02099   * @param  USARTx USART Instance
02100   * @retval None
02101   */
02102 __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
02103 {
02104   SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
02105 }
02106
02107 /**
02108   * @brief  Enable Transmission Complete Interrupt
02109   * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
02110   * @param  USARTx USART Instance
02111   * @retval None
02112   */
02113 __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
02114 {
02115   SET_BIT(USARTx->CR1, USART_CR1_TCIE);
02116 }
02117
02118 /**
02119   * @brief  Enable TX Empty Interrupt
02120   * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
02121   * @param  USARTx USART Instance
02122   * @retval None
02123   */
02124 __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
02125 {
02126   SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
02127 }
02128
02129 /**
02130   * @brief  Enable Parity Error Interrupt
02131   * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
02132   * @param  USARTx USART Instance
02133   * @retval None
02134   */
02135 __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
02136 {
02137   SET_BIT(USARTx->CR1, USART_CR1_PEIE);
02138 }
02139
02140 /**
02141   * @brief  Enable LIN Break Detection Interrupt
02142   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02143   *         LIN feature is supported by the USARTx instance.
02144   * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
02145   * @param  USARTx USART Instance
02146   * @retval None
02147   */
02148 __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
02149 {
02150   SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
02151 }
02152
02153 /**
02154   * @brief  Enable Error Interrupt
02155   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
02156   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
02157   *           0: Interrupt is inhibited
02158   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
02159   * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
02160   * @param  USARTx USART Instance
02161   * @retval None
02162   */
02163 __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
02164 {
02165   SET_BIT(USARTx->CR3, USART_CR3_EIE);
02166 }
02167
02168 /**
02169   * @brief  Enable CTS Interrupt
02170   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
02171   *         Hardware Flow control feature is supported by the USARTx instance.
02172   * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
02173   * @param  USARTx USART Instance
02174   * @retval None
02175   */
02176 __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
02177 {
02178   SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
02179 }
02180
02181 /**
02182   * @brief  Disable IDLE Interrupt
02183   * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
02184   * @param  USARTx USART Instance
02185   * @retval None
02186   */
02187 __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
02188 {
02189   CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
02190 }
02191
02192 /**
02193   * @brief  Disable RX Not Empty Interrupt
02194   * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
02195   * @param  USARTx USART Instance
02196   * @retval None
02197   */
02198 __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
02199 {
02200   CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
02201 }
02202
02203 /**
02204   * @brief  Disable Transmission Complete Interrupt
02205   * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
02206   * @param  USARTx USART Instance
02207   * @retval None
02208   */
02209 __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
02210 {
02211   CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
02212 }
02213
02214 /**
02215   * @brief  Disable TX Empty Interrupt
02216   * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
02217   * @param  USARTx USART Instance
02218   * @retval None
02219   */
02220 __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
02221 {
02222   CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
02223 }
02224
02225 /**
02226   * @brief  Disable Parity Error Interrupt
02227   * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
02228   * @param  USARTx USART Instance
02229   * @retval None
02230   */
02231 __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
02232 {
02233   CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
02234 }
02235
02236 /**
02237   * @brief  Disable LIN Break Detection Interrupt
02238   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02239   *         LIN feature is supported by the USARTx instance.
02240   * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
02241   * @param  USARTx USART Instance
02242   * @retval None
02243   */
02244 __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
02245 {
02246   CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
02247 }
02248
02249 /**
02250   * @brief  Disable Error Interrupt
02251   * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
02252   *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
02253   *           0: Interrupt is inhibited
02254   *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
02255   * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
02256   * @param  USARTx USART Instance
02257   * @retval None
02258   */
02259 __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
02260 {
02261   CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
02262 }
02263
02264 /**
02265   * @brief  Disable CTS Interrupt
02266   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
02267   *         Hardware Flow control feature is supported by the USARTx instance.
02268   * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
02269   * @param  USARTx USART Instance
02270   * @retval None
02271   */
02272 __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
02273 {
02274   CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
02275 }
02276
02277 /**
02278   * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
02279   * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
02280   * @param  USARTx USART Instance
02281   * @retval State of bit (1 or 0).
02282   */
02283 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
02284 {
02285   return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
02286 }
02287
02288 /**
02289   * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
02290   * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
02291   * @param  USARTx USART Instance
02292   * @retval State of bit (1 or 0).
02293   */
02294 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
02295 {
02296   return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
02297 }
02298
02299 /**
02300   * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
02301   * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
02302   * @param  USARTx USART Instance
02303   * @retval State of bit (1 or 0).
02304   */
02305 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
02306 {
02307   return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
02308 }
02309
02310 /**
02311   * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
02312   * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
02313   * @param  USARTx USART Instance
02314   * @retval State of bit (1 or 0).
02315   */
02316 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
02317 {
02318   return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
02319 }
02320
02321 /**
02322   * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
02323   * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
02324   * @param  USARTx USART Instance
02325   * @retval State of bit (1 or 0).
02326   */
02327 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
02328 {
02329   return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
02330 }
02331
02332 /**
02333   * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
02334   * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
02335   *         LIN feature is supported by the USARTx instance.
02336   * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
02337   * @param  USARTx USART Instance
02338   * @retval State of bit (1 or 0).
02339   */
02340 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
02341 {
02342   return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
02343 }
02344
02345 /**
02346   * @brief  Check if the USART Error Interrupt is enabled or disabled.
02347   * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
02348   * @param  USARTx USART Instance
02349   * @retval State of bit (1 or 0).
02350   */
02351 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
02352 {
02353   return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
02354 }
02355
02356 /**
02357   * @brief  Check if the USART CTS Interrupt is enabled or disabled.
02358   * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
02359   *         Hardware Flow control feature is supported by the USARTx instance.
02360   * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
02361   * @param  USARTx USART Instance
02362   * @retval State of bit (1 or 0).
02363   */
02364 __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
02365 {
02366   return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
02367 }
02368
02369 /**
02370   * @}
02371   */
02372
02373 /** @defgroup USART_LL_EF_DMA_Management DMA_Management
02374   * @{
02375   */
02376
02377 /**
02378   * @brief  Enable DMA Mode for reception
02379   * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
02380   * @param  USARTx USART Instance
02381   * @retval None
02382   */
02383 __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
02384 {
02385   SET_BIT(USARTx->CR3, USART_CR3_DMAR);
02386 }
02387
02388 /**
02389   * @brief  Disable DMA Mode for reception
02390   * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
02391   * @param  USARTx USART Instance
02392   * @retval None
02393   */
02394 __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
02395 {
02396   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
02397 }
02398
02399 /**
02400   * @brief  Check if DMA Mode is enabled for reception
02401   * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
02402   * @param  USARTx USART Instance
02403   * @retval State of bit (1 or 0).
02404   */
02405 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
02406 {
02407   return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
02408 }
02409
02410 /**
02411   * @brief  Enable DMA Mode for transmission
02412   * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
02413   * @param  USARTx USART Instance
02414   * @retval None
02415   */
02416 __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
02417 {
02418   SET_BIT(USARTx->CR3, USART_CR3_DMAT);
02419 }
02420
02421 /**
02422   * @brief  Disable DMA Mode for transmission
02423   * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
02424   * @param  USARTx USART Instance
02425   * @retval None
02426   */
02427 __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
02428 {
02429   CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
02430 }
02431
02432 /**
02433   * @brief  Check if DMA Mode is enabled for transmission
02434   * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
02435   * @param  USARTx USART Instance
02436   * @retval State of bit (1 or 0).
02437   */
02438 __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
02439 {
02440   return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
02441 }
02442
02443 /**
02444   * @brief  Get the data register address used for DMA transfer
02445   * @rmtoll DR           DR            LL_USART_DMA_GetRegAddr
02446   * @note   Address of Data Register is valid for both Transmit and Receive transfers.
02447   * @param  USARTx USART Instance
02448   * @retval Address of data register
02449   */
02450 __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
02451 {
02452   /* return address of DR register */
02453   return ((uint32_t) &(USARTx->DR));
02454 }
02455
02456 /**
02457   * @}
02458   */
02459
02460 /** @defgroup USART_LL_EF_Data_Management Data_Management
02461   * @{
02462   */
02463
02464 /**
02465   * @brief  Read Receiver Data register (Receive Data value, 8 bits)
02466   * @rmtoll DR           DR            LL_USART_ReceiveData8
02467   * @param  USARTx USART Instance
02468   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02469   */
02470 __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
02471 {
02472   return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
02473 }
02474
02475 /**
02476   * @brief  Read Receiver Data register (Receive Data value, 9 bits)
02477   * @rmtoll DR           DR            LL_USART_ReceiveData9
02478   * @param  USARTx USART Instance
02479   * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
02480   */
02481 __STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
02482 {
02483   return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
02484 }
02485
02486 /**
02487   * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
02488   * @rmtoll DR           DR            LL_USART_TransmitData8
02489   * @param  USARTx USART Instance
02490   * @param  Value between Min_Data=0x00 and Max_Data=0xFF
02491   * @retval None
02492   */
02493 __STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
02494 {
02495   USARTx->DR = Value;
02496 }
02497
02498 /**
02499   * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
02500   * @rmtoll DR           DR            LL_USART_TransmitData9
02501   * @param  USARTx USART Instance
02502   * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
02503   * @retval None
02504   */
02505 __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
02506 {
02507   USARTx->DR = Value & 0x1FFU;
02508 }
02509
02510 /**
02511   * @}
02512   */
02513
02514 /** @defgroup USART_LL_EF_Execution Execution
02515   * @{
02516   */
02517
02518 /**
02519   * @brief  Request Break sending
02520   * @rmtoll CR1          SBK           LL_USART_RequestBreakSending
02521   * @param  USARTx USART Instance
02522   * @retval None
02523   */
02524 __STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
02525 {
02526   SET_BIT(USARTx->CR1, USART_CR1_SBK);
02527 }
02528
02529 /**
02530   * @brief  Put USART in Mute mode
02531   * @rmtoll CR1          RWU           LL_USART_RequestEnterMuteMode
02532   * @param  USARTx USART Instance
02533   * @retval None
02534   */
02535 __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
02536 {
02537   SET_BIT(USARTx->CR1, USART_CR1_RWU);
02538 }
02539
02540 /**
02541   * @brief  Put USART in Active mode
02542   * @rmtoll CR1          RWU           LL_USART_RequestExitMuteMode
02543   * @param  USARTx USART Instance
02544   * @retval None
02545   */
02546 __STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
02547 {
02548   CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
02549 }
02550
02551 /**
02552   * @}
02553   */
02554
02555 #if defined(USE_FULL_LL_DRIVER)
02556 /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
02557   * @{
02558   */
02559 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
02560 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
02561 void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
02562 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
02563 void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
02564 /**
02565   * @}
02566   */
02567 #endif /* USE_FULL_LL_DRIVER */
02568
02569 /**
02570   * @}
02571   */
02572
02573 /**
02574   * @}
02575   */
02576
02577 #endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
02578
02579 /**
02580   * @}
02581   */
02582
02583 #ifdef __cplusplus
02584 }
02585 #endif
02586
02587 #endif /* __STM32F1xx_LL_USART_H */
02588
02589 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_utils.c Source File

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stm32f1xx_ll_utils.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_utils.c
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   UTILS LL module driver.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f1xx_ll_rcc.h"
00039 #include "stm32f1xx_ll_utils.h"
00040 #include "stm32f1xx_ll_system.h"
00041 #ifdef  USE_FULL_ASSERT
00042 #include "stm32_assert.h"
00043 #else
00044 #define assert_param(expr) ((void)0U)
00045 #endif
00046
00047 /** @addtogroup STM32F1xx_LL_Driver
00048   * @{
00049   */
00050
00051 /** @addtogroup UTILS_LL
00052   * @{
00053   */
00054
00055 /* Private types -------------------------------------------------------------*/
00056 /* Private variables ---------------------------------------------------------*/
00057 /* Private constants ---------------------------------------------------------*/
00058 /** @addtogroup UTILS_LL_Private_Constants
00059   * @{
00060   */
00061
00062 /* Defines used for PLL range */
00063 #define UTILS_PLL_OUTPUT_MAX        RCC_MAX_FREQUENCY    /*!< Frequency max for PLL output, in Hz  */
00064
00065 /* Defines used for HSE range */
00066 #define UTILS_HSE_FREQUENCY_MIN     RCC_HSE_MIN       /*!< Frequency min for HSE frequency, in Hz   */
00067 #define UTILS_HSE_FREQUENCY_MAX     RCC_HSE_MAX       /*!< Frequency max for HSE frequency, in Hz   */
00068
00069 /* Defines used for FLASH latency according to HCLK Frequency */
00070 #if defined(FLASH_ACR_LATENCY)
00071 #define UTILS_LATENCY1_FREQ         24000000U        /*!< SYSCLK frequency to set FLASH latency 1 */
00072 #define UTILS_LATENCY2_FREQ         48000000U        /*!< SYSCLK frequency to set FLASH latency 2 */
00073 #else
00074     /*!< No Latency Configuration in this device */
00075 #endif
00076 /**
00077   * @}
00078   */
00079 /* Private macros ------------------------------------------------------------*/
00080 /** @addtogroup UTILS_LL_Private_Macros
00081   * @{
00082   */
00083 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
00084                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
00085                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
00086                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
00087                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
00088                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
00089                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
00090                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
00091                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
00092
00093 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
00094                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
00095                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
00096                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
00097                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
00098
00099 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
00100                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
00101                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
00102                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
00103                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
00104
00105 #if defined(RCC_CFGR_PLLMULL6_5)
00106 #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
00107                                           || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
00108                                           || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
00109                                           || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
00110                                           || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
00111                                           || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
00112                                           || ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
00113 #else
00114 #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
00115                                           || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
00116                                           || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
00117                                           || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
00118                                           || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
00119                                           || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
00120                                           || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
00121                                           || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
00122                                           || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
00123                                           || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
00124                                           || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
00125                                           || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
00126                                           || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
00127                                           || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
00128                                           || ((__VALUE__) == LL_RCC_PLL_MUL_16))
00129 #endif /* RCC_CFGR_PLLMULL6_5 */
00130
00131 #if defined(RCC_CFGR2_PREDIV1)
00132 #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_2)   || \
00133                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_3)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_4)   || \
00134                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_5)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_6)   || \
00135                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_7)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_8)   || \
00136                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_9)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_10)  || \
00137                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12)  || \
00138                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14)  || \
00139                                              ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
00140 #else
00141 #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1)  || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
00142 #endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
00143
00144 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
00145
00146
00147 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
00148                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
00149
00150 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
00151 /**
00152   * @}
00153   */
00154 /* Private function prototypes -----------------------------------------------*/
00155 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
00156   * @{
00157   */
00158 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
00159                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
00160 #if defined(FLASH_ACR_LATENCY)
00161 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
00162 #endif /* FLASH_ACR_LATENCY */
00163 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00164 static ErrorStatus UTILS_PLL_IsBusy(void);
00165 /**
00166   * @}
00167   */
00168
00169 /* Exported functions --------------------------------------------------------*/
00170 /** @addtogroup UTILS_LL_Exported_Functions
00171   * @{
00172   */
00173
00174 /** @addtogroup UTILS_LL_EF_DELAY
00175   * @{
00176   */
00177
00178 /**
00179   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
00180   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
00181   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00182   * @param  HCLKFrequency HCLK frequency in Hz
00183   * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
00184   * @retval None
00185   */
00186 void LL_Init1msTick(uint32_t HCLKFrequency)
00187 {
00188   /* Use frequency provided in argument */
00189   LL_InitTick(HCLKFrequency, 1000U);
00190 }
00191
00192 /**
00193   * @brief  This function provides accurate delay (in milliseconds) based
00194   *         on SysTick counter flag
00195   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
00196   *         and use rather osDelay service.
00197   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
00198   *         will configure Systick to 1ms
00199   * @param  Delay specifies the delay time length, in milliseconds.
00200   * @retval None
00201   */
00202 void LL_mDelay(uint32_t Delay)
00203 {
00204   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
00205   /* Add this code to indicate that local variable is not used */
00206   ((void)tmp);
00207
00208   /* Add a period to guaranty minimum wait */
00209   if (Delay < LL_MAX_DELAY)
00210   {
00211     Delay++;
00212   }
00213
00214   while (Delay)
00215   {
00216     if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
00217     {
00218       Delay--;
00219     }
00220   }
00221 }
00222
00223 /**
00224   * @}
00225   */
00226
00227 /** @addtogroup UTILS_EF_SYSTEM
00228   *  @brief    System Configuration functions
00229   *
00230   @verbatim
00231  ===============================================================================
00232            ##### System Configuration functions #####
00233  ===============================================================================
00234     [..]
00235          System, AHB and APB buses clocks configuration
00236
00237          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
00238   @endverbatim
00239   @internal
00240              Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
00241              (++) +-----------------------------------------------+
00242              (++) | Latency       | SYSCLK clock frequency (MHz)  |
00243              (++) |---------------|-------------------------------|
00244              (++) |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
00245              (++) |---------------|-------------------------------|
00246              (++) |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
00247              (++) |---------------|-------------------------------|
00248              (++) |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |
00249              (++) +-----------------------------------------------+
00250   @endinternal
00251   * @{
00252   */
00253
00254 /**
00255   * @brief  This function sets directly SystemCoreClock CMSIS variable.
00256   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
00257   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00258   * @retval None
00259   */
00260 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
00261 {
00262   /* HCLK clock frequency */
00263   SystemCoreClock = HCLKFrequency;
00264 }
00265
00266 /**
00267   * @brief  This function configures system clock with HSI as clock source of the PLL
00268   * @note   The application need to ensure that PLL is disabled.
00269   * @note   Function is based on the following formula:
00270   *         - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
00271   *         - PREDIV: Set to 2 for few devices
00272   *         - PLLMUL: The application software must set correctly the PLL multiplication factor to
00273   *                   not exceed 72MHz
00274   * @note   FLASH latency can be modified through this function.
00275   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00276   *                             the configuration information for the PLL.
00277   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00278   *                             the configuration information for the BUS prescalers.
00279   * @retval An ErrorStatus enumeration value:
00280   *          - SUCCESS: Max frequency configuration done
00281   *          - ERROR: Max frequency configuration not done
00282   */
00283 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00284                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00285 {
00286   ErrorStatus status = SUCCESS;
00287   uint32_t pllfreq = 0U;
00288
00289   /* Check if one of the PLL is enabled */
00290   if (UTILS_PLL_IsBusy() == SUCCESS)
00291   {
00292 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
00293     /* Check PREDIV value */
00294     assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
00295 #else
00296     /* Force PREDIV value to 2 */
00297     UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
00298 #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
00299     /* Calculate the new PLL output frequency */
00300     pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
00301
00302     /* Enable HSI if not enabled */
00303     if (LL_RCC_HSI_IsReady() != 1U)
00304     {
00305       LL_RCC_HSI_Enable();
00306       while (LL_RCC_HSI_IsReady() != 1U)
00307       {
00308         /* Wait for HSI ready */
00309       }
00310     }
00311
00312     /* Configure PLL */
00313     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
00314
00315     /* Enable PLL and switch system clock to PLL */
00316     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00317   }
00318   else
00319   {
00320     /* Current PLL configuration cannot be modified */
00321     status = ERROR;
00322   }
00323
00324   return status;
00325 }
00326
00327 /**
00328   * @brief  This function configures system clock with HSE as clock source of the PLL
00329   * @note   The application need to ensure that PLL is disabled.
00330   * @note   Function is based on the following formula:
00331   *         - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
00332   *         - PREDIV: Set to 2 for few devices
00333   *         - PLLMUL: The application software must set correctly the PLL multiplication factor to
00334   *                   not exceed @ref UTILS_PLL_OUTPUT_MAX
00335   * @note   FLASH latency can be modified through this function.
00336   * @param  HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
00337   * @param  HSEBypass This parameter can be one of the following values:
00338   *         @arg @ref LL_UTILS_HSEBYPASS_ON
00339   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
00340   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00341   *                             the configuration information for the PLL.
00342   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00343   *                             the configuration information for the BUS prescalers.
00344   * @retval An ErrorStatus enumeration value:
00345   *          - SUCCESS: Max frequency configuration done
00346   *          - ERROR: Max frequency configuration not done
00347   */
00348 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00349                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00350 {
00351   ErrorStatus status = SUCCESS;
00352   uint32_t pllfreq = 0U;
00353
00354   /* Check the parameters */
00355   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
00356   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
00357
00358   /* Check if one of the PLL is enabled */
00359   if (UTILS_PLL_IsBusy() == SUCCESS)
00360   {
00361     assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
00362
00363     /* Calculate the new PLL output frequency */
00364     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
00365
00366     /* Enable HSE if not enabled */
00367     if (LL_RCC_HSE_IsReady() != 1U)
00368     {
00369       /* Check if need to enable HSE bypass feature or not */
00370       if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
00371       {
00372         LL_RCC_HSE_EnableBypass();
00373       }
00374       else
00375       {
00376         LL_RCC_HSE_DisableBypass();
00377       }
00378
00379       /* Enable HSE */
00380       LL_RCC_HSE_Enable();
00381       while (LL_RCC_HSE_IsReady() != 1U)
00382       {
00383         /* Wait for HSE ready */
00384       }
00385     }
00386
00387       /* Configure PLL */
00388     LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
00389
00390     /* Enable PLL and switch system clock to PLL */
00391     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
00392   }
00393   else
00394   {
00395     /* Current PLL configuration cannot be modified */
00396     status = ERROR;
00397   }
00398
00399   return status;
00400 }
00401
00402 /**
00403   * @}
00404   */
00405
00406 /**
00407   * @}
00408   */
00409
00410 /** @addtogroup UTILS_LL_Private_Functions
00411   * @{
00412   */
00413 /**
00414   * @brief  Update number of Flash wait states in line with new frequency and current
00415             voltage range.
00416   * @param  Frequency  SYSCLK frequency
00417   * @retval An ErrorStatus enumeration value:
00418   *          - SUCCESS: Latency has been modified
00419   *          - ERROR: Latency cannot be modified
00420   */
00421 #if defined(FLASH_ACR_LATENCY)
00422 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
00423 {
00424   ErrorStatus status = SUCCESS;
00425
00426   uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
00427
00428   /* Frequency cannot be equal to 0 */
00429   if (Frequency == 0U)
00430   {
00431     status = ERROR;
00432   }
00433   else
00434   {
00435     if (Frequency > UTILS_LATENCY2_FREQ)
00436     {
00437       /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
00438       latency = LL_FLASH_LATENCY_2;
00439     }
00440     else
00441     {
00442       if (Frequency > UTILS_LATENCY1_FREQ)
00443       {
00444         /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
00445         latency = LL_FLASH_LATENCY_1;
00446       }
00447       /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
00448     }
00449
00450     LL_FLASH_SetLatency(latency);
00451
00452     /* Check that the new number of wait states is taken into account to access the Flash
00453        memory by reading the FLASH_ACR register */
00454     if (LL_FLASH_GetLatency() != latency)
00455     {
00456       status = ERROR;
00457     }
00458   }
00459   return status;
00460 }
00461 #endif /* FLASH_ACR_LATENCY */
00462
00463 /**
00464   * @brief  Function to check that PLL can be modified
00465   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
00466   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
00467   *                             the configuration information for the PLL.
00468   * @retval PLL output frequency (in Hz)
00469   */
00470 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
00471 {
00472   uint32_t pllfreq = 0U;
00473
00474   /* Check the parameters */
00475   assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
00476
00477   /* Check different PLL parameters according to RM                          */
00478 #if defined (RCC_CFGR2_PREDIV1)
00479   pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
00480 #elif defined(RCC_CFGR2_PREDIV1SRC)
00481   pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
00482 #else
00483   pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
00484 #endif /*RCC_CFGR2_PREDIV1SRC*/
00485   assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
00486
00487   return pllfreq;
00488 }
00489
00490 /**
00491   * @brief  Function to check that PLL can be modified
00492   * @retval An ErrorStatus enumeration value:
00493   *          - SUCCESS: PLL modification can be done
00494   *          - ERROR: PLL is busy
00495   */
00496 static ErrorStatus UTILS_PLL_IsBusy(void)
00497 {
00498   ErrorStatus status = SUCCESS;
00499
00500   /* Check if PLL is busy*/
00501   if (LL_RCC_PLL_IsReady() != 0U)
00502   {
00503     /* PLL configuration cannot be modified */
00504     status = ERROR;
00505   }
00506 #if defined(RCC_PLL2_SUPPORT)
00507   /* Check if PLL2 is busy*/
00508   if (LL_RCC_PLL2_IsReady() != 0U)
00509   {
00510     /* PLL2 configuration cannot be modified */
00511     status = ERROR;
00512   }
00513 #endif /* RCC_PLL2_SUPPORT */
00514
00515 #if defined(RCC_PLLI2S_SUPPORT)
00516   /* Check if PLLI2S  is busy*/
00517   if (LL_RCC_PLLI2S_IsReady() != 0U)
00518   {
00519     /* PLLI2S configuration cannot be modified */
00520     status = ERROR;
00521   }
00522 #endif /* RCC_PLLI2S_SUPPORT */
00523
00524   return status;
00525 }
00526
00527 /**
00528   * @brief  Function to enable PLL and switch system clock to PLL
00529   * @param  SYSCLK_Frequency SYSCLK frequency
00530   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
00531   *                             the configuration information for the BUS prescalers.
00532   * @retval An ErrorStatus enumeration value:
00533   *          - SUCCESS: No problem to switch system to PLL
00534   *          - ERROR: Problem to switch system to PLL
00535   */
00536 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
00537 {
00538   ErrorStatus status = SUCCESS;
00539 #if defined(FLASH_ACR_LATENCY)
00540   uint32_t sysclk_frequency_current = 0U;
00541 #endif /* FLASH_ACR_LATENCY */
00542
00543   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
00544   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
00545   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
00546
00547 #if defined(FLASH_ACR_LATENCY)
00548   /* Calculate current SYSCLK frequency */
00549   sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
00550 #endif /* FLASH_ACR_LATENCY */
00551
00552   /* Increasing the number of wait states because of higher CPU frequency */
00553 #if defined (FLASH_ACR_LATENCY)
00554   if (sysclk_frequency_current < SYSCLK_Frequency)
00555   {
00556     /* Set FLASH latency to highest latency */
00557     status = UTILS_SetFlashLatency(SYSCLK_Frequency);
00558   }
00559 #endif /* FLASH_ACR_LATENCY */
00560
00561   /* Update system clock configuration */
00562   if (status == SUCCESS)
00563   {
00564 #if defined(RCC_PLL2_SUPPORT)
00565     /* Enable PLL2 */
00566     LL_RCC_PLL2_Enable();
00567     while (LL_RCC_PLL2_IsReady() != 1U)
00568     {
00569       /* Wait for PLL2 ready */
00570     }
00571
00572 #endif /* RCC_PLL2_SUPPORT */
00573     /* Enable PLL */
00574     LL_RCC_PLL_Enable();
00575     while (LL_RCC_PLL_IsReady() != 1U)
00576     {
00577       /* Wait for PLL ready */
00578     }
00579
00580     /* Sysclk activation on the main PLL */
00581     LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
00582     LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
00583     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
00584     {
00585       /* Wait for system clock switch to PLL */
00586     }
00587
00588     /* Set APB1 & APB2 prescaler*/
00589     LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
00590     LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
00591   }
00592
00593   /* Decreasing the number of wait states because of lower CPU frequency */
00594 #if defined (FLASH_ACR_LATENCY)
00595   if (sysclk_frequency_current > SYSCLK_Frequency)
00596   {
00597     /* Set FLASH latency to lowest latency */
00598     status = UTILS_SetFlashLatency(SYSCLK_Frequency);
00599   }
00600 #endif /* FLASH_ACR_LATENCY */
00601
00602   /* Update SystemCoreClock variable */
00603   if (status == SUCCESS)
00604   {
00605     LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
00606   }
00607
00608   return status;
00609 }
00610
00611 /**
00612   * @}
00613   */
00614
00615 /**
00616   * @}
00617   */
00618
00619 /**
00620   * @}
00621   */
00622
00623 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_utils.h Source File

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stm32f1xx_ll_utils.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_utils.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of UTILS LL module.
00008   @verbatim
00009   ==============================================================================
00010                      ##### How to use this driver #####
00011   ==============================================================================
00012     [..]
00013     The LL UTILS driver contains a set of generic APIs that can be
00014     used by user:
00015       (+) Device electronic signature
00016       (+) Timing functions
00017       (+) PLL configuration functions
00018
00019   @endverbatim
00020   ******************************************************************************
00021   * @attention
00022   *
00023   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00024   *
00025   * Redistribution and use in source and binary forms, with or without modification,
00026   * are permitted provided that the following conditions are met:
00027   *   1. Redistributions of source code must retain the above copyright notice,
00028   *      this list of conditions and the following disclaimer.
00029   *   2. Redistributions in binary form must reproduce the above copyright notice,
00030   *      this list of conditions and the following disclaimer in the documentation
00031   *      and/or other materials provided with the distribution.
00032   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00033   *      may be used to endorse or promote products derived from this software
00034   *      without specific prior written permission.
00035   *
00036   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00037   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00038   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00039   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00040   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00041   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00042   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00043   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00044   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00045   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00046   *
00047   ******************************************************************************
00048   */
00049
00050 /* Define to prevent recursive inclusion -------------------------------------*/
00051 #ifndef __STM32F1xx_LL_UTILS_H
00052 #define __STM32F1xx_LL_UTILS_H
00053
00054 #ifdef __cplusplus
00055 extern "C" {
00056 #endif
00057
00058 /* Includes ------------------------------------------------------------------*/
00059 #include "stm32f1xx.h"
00060
00061 /** @addtogroup STM32F1xx_LL_Driver
00062   * @{
00063   */
00064
00065 /** @defgroup UTILS_LL UTILS
00066   * @{
00067   */
00068
00069 /* Private types -------------------------------------------------------------*/
00070 /* Private variables ---------------------------------------------------------*/
00071
00072 /* Private constants ---------------------------------------------------------*/
00073 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
00074   * @{
00075   */
00076
00077 /* Max delay can be used in LL_mDelay */
00078 #define LL_MAX_DELAY                  0xFFFFFFFFU
00079
00080 /**
00081  * @brief Unique device ID register base address
00082  */
00083 #define UID_BASE_ADDRESS              UID_BASE
00084
00085 /**
00086  * @brief Flash size data register base address
00087  */
00088 #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
00089
00090 /**
00091   * @}
00092   */
00093
00094 /* Private macros ------------------------------------------------------------*/
00095 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
00096   * @{
00097   */
00098 /**
00099   * @}
00100   */
00101 /* Exported types ------------------------------------------------------------*/
00102 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
00103   * @{
00104   */
00105 /**
00106   * @brief  UTILS PLL structure definition
00107   */
00108 typedef struct
00109 {
00110   uint32_t PLLMul;   /*!< Multiplication factor for PLL VCO input clock.
00111                           This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
00112
00113                           This feature can be modified afterwards using unitary function
00114                           @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00115
00116   uint32_t Prediv;   /*!< Division factor for HSE used as PLL clock source.
00117                           This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
00118
00119                           This feature can be modified afterwards using unitary function
00120                           @ref LL_RCC_PLL_ConfigDomain_SYS(). */
00121 } LL_UTILS_PLLInitTypeDef;
00122
00123 /**
00124   * @brief  UTILS System, AHB and APB buses clock configuration structure definition
00125   */
00126 typedef struct
00127 {
00128   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
00129                                        This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
00130
00131                                        This feature can be modified afterwards using unitary function
00132                                        @ref LL_RCC_SetAHBPrescaler(). */
00133
00134   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
00135                                        This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
00136
00137                                        This feature can be modified afterwards using unitary function
00138                                        @ref LL_RCC_SetAPB1Prescaler(). */
00139
00140   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
00141                                        This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
00142
00143                                        This feature can be modified afterwards using unitary function
00144                                        @ref LL_RCC_SetAPB2Prescaler(). */
00145
00146 } LL_UTILS_ClkInitTypeDef;
00147
00148 /**
00149   * @}
00150   */
00151
00152 /* Exported constants --------------------------------------------------------*/
00153 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
00154   * @{
00155   */
00156
00157 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
00158   * @{
00159   */
00160 #define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
00161 #define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
00162 /**
00163   * @}
00164   */
00165
00166 /**
00167   * @}
00168   */
00169
00170 /* Exported macro ------------------------------------------------------------*/
00171
00172 /* Exported functions --------------------------------------------------------*/
00173 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
00174   * @{
00175   */
00176
00177 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
00178   * @{
00179   */
00180
00181 /**
00182   * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
00183   * @retval UID[31:0]
00184   */
00185 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
00186 {
00187   return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
00188 }
00189
00190 /**
00191   * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
00192   * @retval UID[63:32]
00193   */
00194 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
00195 {
00196   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
00197 }
00198
00199 /**
00200   * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
00201   * @retval UID[95:64]
00202   */
00203 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
00204 {
00205   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
00206 }
00207
00208 /**
00209   * @brief  Get Flash memory size
00210   * @note   This bitfield indicates the size of the device Flash memory expressed in
00211   *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
00212   * @retval FLASH_SIZE[15:0]: Flash memory size
00213   */
00214 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
00215 {
00216   return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
00217 }
00218
00219
00220 /**
00221   * @}
00222   */
00223
00224 /** @defgroup UTILS_LL_EF_DELAY DELAY
00225   * @{
00226   */
00227
00228 /**
00229   * @brief  This function configures the Cortex-M SysTick source of the time base.
00230   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
00231   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
00232   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
00233   * @param  Ticks Number of ticks
00234   * @retval None
00235   */
00236 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
00237 {
00238   /* Configure the SysTick to have interrupt in 1ms time base */
00239   SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
00240   SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
00241   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
00242                    SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
00243 }
00244
00245 void        LL_Init1msTick(uint32_t HCLKFrequency);
00246 void        LL_mDelay(uint32_t Delay);
00247
00248 /**
00249   * @}
00250   */
00251
00252 /** @defgroup UTILS_EF_SYSTEM SYSTEM
00253   * @{
00254   */
00255
00256 void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
00257 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
00258                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00259 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
00260                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
00261
00262 /**
00263   * @}
00264   */
00265
00266 /**
00267   * @}
00268   */
00269
00270 /**
00271   * @}
00272   */
00273
00274 /**
00275   * @}
00276   */
00277
00278 #ifdef __cplusplus
00279 }
00280 #endif
00281
00282 #endif /* __STM32F1xx_LL_UTILS_H */
00283
00284 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Thu Mar 23 2017 15:22:24 for STM32F103xB HAL User Manual by doxygen 1.7.6.1


STM32F103xB HAL User Manual: stm32f1xx_ll_wwdg.h Source File

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stm32f1xx_ll_wwdg.h
Go to the documentation of this file.
00001 /**
00002   ******************************************************************************
00003   * @file    stm32f1xx_ll_wwdg.h
00004   * @author  MCD Application Team
00005   * @version $VERSION$
00006   * @date    $DATE$
00007   * @brief   Header file of WWDG LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32F1xx_LL_WWDG_H
00040 #define __STM32F1xx_LL_WWDG_H
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32f1xx.h"
00048
00049 /** @addtogroup STM32F1xx_LL_Driver
00050   * @{
00051   */
00052
00053 #if defined (WWDG)
00054
00055 /** @defgroup WWDG_LL WWDG
00056   * @{
00057   */
00058
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061
00062 /* Private constants ---------------------------------------------------------*/
00063
00064 /* Private macros ------------------------------------------------------------*/
00065
00066 /* Exported types ------------------------------------------------------------*/
00067 /* Exported constants --------------------------------------------------------*/
00068 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
00069   * @{
00070   */
00071
00072
00073 /** @defgroup WWDG_LL_EC_IT IT Defines
00074   * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions
00075   * @{
00076   */
00077 #define LL_WWDG_CFR_EWI                    WWDG_CFR_EWI
00078 /**
00079   * @}
00080   */
00081
00082 /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
00083 * @{
00084 */
00085 #define LL_WWDG_PRESCALER_1                0x00000000U                                             /*!< WWDG counter clock = (PCLK1/4096)/1 */
00086 #define LL_WWDG_PRESCALER_2                WWDG_CFR_WDGTB_0                                        /*!< WWDG counter clock = (PCLK1/4096)/2 */
00087 #define LL_WWDG_PRESCALER_4                WWDG_CFR_WDGTB_1                                        /*!< WWDG counter clock = (PCLK1/4096)/4 */
00088 #define LL_WWDG_PRESCALER_8                (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                   /*!< WWDG counter clock = (PCLK1/4096)/8 */
00089 /**
00090   * @}
00091   */
00092
00093 /**
00094   * @}
00095   */
00096
00097 /* Exported macro ------------------------------------------------------------*/
00098 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
00099   * @{
00100   */
00101 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
00102   * @{
00103   */
00104 /**
00105   * @brief  Write a value in WWDG register
00106   * @param  __INSTANCE__ WWDG Instance
00107   * @param  __REG__ Register to be written
00108   * @param  __VALUE__ Value to be written in the register
00109   * @retval None
00110   */
00111 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00112
00113 /**
00114   * @brief  Read a value in WWDG register
00115   * @param  __INSTANCE__ WWDG Instance
00116   * @param  __REG__ Register to be read
00117   * @retval Register value
00118   */
00119 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00120 /**
00121   * @}
00122   */
00123
00124
00125 /**
00126   * @}
00127   */
00128
00129 /* Exported functions --------------------------------------------------------*/
00130 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
00131   * @{
00132   */
00133
00134 /** @defgroup WWDG_LL_EF_Configuration Configuration
00135   * @{
00136   */
00137 /**
00138   * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.
00139   * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,
00140   *         then it cannot be disabled again except by a reset.
00141   *         This bit is set by software and only cleared by hardware after a reset.
00142   *         When WDGA = 1, the watchdog can generate a reset.
00143   * @rmtoll CR           WDGA          LL_WWDG_Enable
00144   * @param  WWDGx WWDG Instance
00145   * @retval None
00146   */
00147 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
00148 {
00149   SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
00150 }
00151
00152 /**
00153   * @brief  Checks if Window Watchdog is enabled
00154   * @rmtoll CR           WDGA          LL_WWDG_IsEnabled
00155   * @param  WWDGx WWDG Instance
00156   * @retval State of bit (1 or 0).
00157   */
00158 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
00159 {
00160   return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
00161 }
00162
00163 /**
00164   * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])
00165   * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
00166   *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
00167   *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
00168   *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
00169   * @rmtoll CR           T             LL_WWDG_SetCounter
00170   * @param  WWDGx WWDG Instance
00171   * @param  Counter 0..0x7F (7 bit counter value)
00172   * @retval None
00173   */
00174 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
00175 {
00176   MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
00177 }
00178
00179 /**
00180   * @brief  Return current Watchdog Counter Value (7 bits counter value)
00181   * @rmtoll CR           T             LL_WWDG_GetCounter
00182   * @param  WWDGx WWDG Instance
00183   * @retval 7 bit Watchdog Counter value
00184   */
00185 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
00186 {
00187   return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
00188 }
00189
00190 /**
00191   * @brief  Set the time base of the prescaler (WDGTB).
00192   * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
00193   *         is decremented every (4096 x 2expWDGTB) PCLK cycles
00194   * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler
00195   * @param  WWDGx WWDG Instance
00196   * @param  Prescaler This parameter can be one of the following values:
00197   *         @arg @ref LL_WWDG_PRESCALER_1
00198   *         @arg @ref LL_WWDG_PRESCALER_2
00199   *         @arg @ref LL_WWDG_PRESCALER_4
00200   *         @arg @ref LL_WWDG_PRESCALER_8
00201   * @retval None
00202   */
00203 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
00204 {
00205   MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
00206 }
00207
00208 /**
00209   * @brief  Return current Watchdog Prescaler Value
00210   * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler
00211   * @param  WWDGx WWDG Instance
00212   * @retval Returned value can be one of the following values:
00213   *         @arg @ref LL_WWDG_PRESCALER_1
00214   *         @arg @ref LL_WWDG_PRESCALER_2
00215   *         @arg @ref LL_WWDG_PRESCALER_4
00216   *         @arg @ref LL_WWDG_PRESCALER_8
00217   */
00218 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
00219 {
00220   return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
00221 }
00222
00223 /**
00224   * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
00225   * @note   This window value defines when write in the WWDG_CR register
00226   *         to program Watchdog counter is allowed.
00227   *         Watchdog counter value update must occur only when the counter value
00228   *         is lower than the Watchdog window register value.
00229   *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
00230   *         (in the control register) is refreshed before the downcounter has reached
00231   *         the watchdog window register value.
00232   *         Physically is possible to set the Window lower then 0x40 but it is not recommended.
00233   *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.
00234   * @rmtoll CFR          W             LL_WWDG_SetWindow
00235   * @param  WWDGx WWDG Instance
00236   * @param  Window 0x00..0x7F (7 bit Window value)
00237   * @retval None
00238   */
00239 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
00240 {
00241   MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
00242 }
00243
00244 /**
00245   * @brief  Return current Watchdog Window Value (7 bits value)
00246   * @rmtoll CFR          W             LL_WWDG_GetWindow
00247   * @param  WWDGx WWDG Instance
00248   * @retval 7 bit Watchdog Window value
00249   */
00250 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
00251 {
00252   return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
00253 }
00254
00255 /**
00256   * @}
00257   */
00258
00259 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
00260   * @{
00261   */
00262 /**
00263   * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
00264   * @note   This bit is set by hardware when the counter has reached the value 0x40.
00265   *         It must be cleared by software by writing 0.
00266   *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
00267   * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP
00268   * @param  WWDGx WWDG Instance
00269   * @retval State of bit (1 or 0).
00270   */
00271 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
00272 {
00273   return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
00274 }
00275
00276 /**
00277   * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)
00278   * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP
00279   * @param  WWDGx WWDG Instance
00280   * @retval None
00281   */
00282 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
00283 {
00284   WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
00285 }
00286
00287 /**
00288   * @}
00289   */
00290
00291 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
00292   * @{
00293   */
00294 /**
00295   * @brief  Enable the Early Wakeup Interrupt.
00296   * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.
00297   *         This interrupt is only cleared by hardware after a reset
00298   * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP
00299   * @param  WWDGx WWDG Instance
00300   * @retval None
00301   */
00302 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
00303 {
00304   SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
00305 }
00306
00307 /**
00308   * @brief  Check if Early Wakeup Interrupt is enabled
00309   * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP
00310   * @param  WWDGx WWDG Instance
00311   * @retval State of bit (1 or 0).
00312   */
00313 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
00314 {
00315   return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
00316 }
00317
00318 /**
00319   * @}
00320   */
00321
00322 /**
00323   * @}
00324   */
00325
00326 /**
00327   * @}
00328   */
00329
00330 #endif /* WWDG */
00331
00332 /**
00333   * @}
00334   */
00335
00336 #ifdef __cplusplus
00337 }
00338 #endif
00339
00340 #endif /* __STM32F1xx_LL_WWDG_H */
00341
00342 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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