Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
[binutils-gdb.git] / ld / testsuite / ld-aarch64 / farcall-bl-plt.d
blob457a4faa0b39f3ab55f97eef73ea4bc8212c3eac
1 #name: aarch64-farcall-bl-plt
2 #source: farcall-bl-plt.s
3 #as:
4 #ld: -shared
5 #objdump: -dr
6 #...
8 Disassembly of section .plt:
10 .* <foo@plt.*>:
11 .*: a9bf7bf0 stp x16, x30, \[sp,#-16\]!
12 .*: .* adrp x16, .* <__foo_veneer\+.*>
13 .*: .* ldr x17, \[x16,#.*\]
14 .*: .* add x16, x16, #.*
15 .*: d61f0220 br x17
16 .*: d503201f nop
17 .*: d503201f nop
18 .*: d503201f nop
20 .* <foo@plt>:
21 .*: .* adrp x16, .* <__foo_veneer\+.*>
22 .*: .* ldr x17, \[x16,#.*\]
23 .*: .* add x16, x16, #.*
24 .*: d61f0220 br x17
26 Disassembly of section .text:
28 .* <_start>:
29 ...
30 .*: .* bl .* <__foo_veneer>
31 .*: d65f03c0 ret
32 .*: .* b .* <__foo_veneer\+.*>
34 .* <__foo_veneer>:
35 .*: .* adrp x16, 0 <foo@plt.*>
36 .*: .* add x16, x16, #.*
37 .*: d61f0200 br x16
38 ...