1 static const struct dis386 evex_len_table
[][3] = {
5 { "vpermp%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
6 { "vpermp%XW", { XM
, Vex
, EXx
}, PREFIX_DATA
},
12 { VEX_W_TABLE (EVEX_W_0F3819_L_n
) },
13 { VEX_W_TABLE (EVEX_W_0F3819_L_n
) },
16 /* EVEX_LEN_0F381A_M_0 */
19 { VEX_W_TABLE (EVEX_W_0F381A_M_0_L_n
) },
20 { VEX_W_TABLE (EVEX_W_0F381A_M_0_L_n
) },
23 /* EVEX_LEN_0F381B_M_0 */
27 { VEX_W_TABLE (EVEX_W_0F381B_M_0_L_2
) },
33 { "vperm%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
34 { "vperm%DQ", { XM
, Vex
, EXx
}, PREFIX_DATA
},
37 /* EVEX_LEN_0F385A_M_0 */
40 { VEX_W_TABLE (EVEX_W_0F385A_M_0_L_n
) },
41 { VEX_W_TABLE (EVEX_W_0F385A_M_0_L_n
) },
44 /* EVEX_LEN_0F385B_M_0 */
48 { VEX_W_TABLE (EVEX_W_0F385B_M_0_L_2
) },
51 /* EVEX_LEN_0F38C6_M_0 */
55 { REG_TABLE (REG_EVEX_0F38C6_M_0_L_2
) },
58 /* EVEX_LEN_0F38C7_M_0 */
62 { REG_TABLE (REG_EVEX_0F38C7_M_0_L_2
) },
68 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
69 { VEX_W_TABLE (VEX_W_0F3A00_L_1
) },
75 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
76 { VEX_W_TABLE (VEX_W_0F3A01_L_1
) },
82 { VEX_W_TABLE (EVEX_W_0F3A18_L_n
) },
83 { VEX_W_TABLE (EVEX_W_0F3A18_L_n
) },
89 { VEX_W_TABLE (EVEX_W_0F3A19_L_n
) },
90 { VEX_W_TABLE (EVEX_W_0F3A19_L_n
) },
97 { VEX_W_TABLE (EVEX_W_0F3A1A_L_2
) },
100 /* EVEX_LEN_0F3A1B */
104 { VEX_W_TABLE (EVEX_W_0F3A1B_L_2
) },
107 /* EVEX_LEN_0F3A23 */
110 { VEX_W_TABLE (EVEX_W_0F3A23_L_n
) },
111 { VEX_W_TABLE (EVEX_W_0F3A23_L_n
) },
114 /* EVEX_LEN_0F3A38 */
117 { VEX_W_TABLE (EVEX_W_0F3A38_L_n
) },
118 { VEX_W_TABLE (EVEX_W_0F3A38_L_n
) },
121 /* EVEX_LEN_0F3A39 */
124 { VEX_W_TABLE (EVEX_W_0F3A39_L_n
) },
125 { VEX_W_TABLE (EVEX_W_0F3A39_L_n
) },
128 /* EVEX_LEN_0F3A3A */
132 { VEX_W_TABLE (EVEX_W_0F3A3A_L_2
) },
135 /* EVEX_LEN_0F3A3B */
139 { VEX_W_TABLE (EVEX_W_0F3A3B_L_2
) },
142 /* EVEX_LEN_0F3A43 */
145 { VEX_W_TABLE (EVEX_W_0F3A43_L_n
) },
146 { VEX_W_TABLE (EVEX_W_0F3A43_L_n
) },